[PATCH] D122533: [avr] Remove AVRRelaxMemOperations

2022-03-26 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 created this revision.
Herald added subscribers: Jim, hiraditya, mgorny, dylanmckay.
Herald added a project: All.
Patryk27 requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This commit contains a refactoring that merges AVRRelaxMemOperations
into AVRExpandPseudoInsts, so that we have a single place in code that
expands the STDWPtrQRr opcode.

Seizing the day, I've also fixed a couple of potential bugs with our
previous implementation (e.g. when the destination register was killed,
the previous implementation would try to `.addDef()` that killed
register, crashing LLVM in the process - that's fixed now, as proved by
the test).

In the bigger picture, this commit is the first step of fixing
https://reviews.llvm.org/D114611.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122533

Files:
  clang/docs/tools/clang-formatted-files.txt
  llvm/lib/Target/AVR/AVR.h
  llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
  llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp
  llvm/lib/Target/AVR/AVRTargetMachine.cpp
  llvm/lib/Target/AVR/CMakeLists.txt
  llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
  llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
  llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn

Index: llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
===
--- llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
+++ llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
@@ -37,7 +37,6 @@
 "AVRInstrInfo.cpp",
 "AVRMCInstLower.cpp",
 "AVRRegisterInfo.cpp",
-"AVRRelaxMemOperations.cpp",
 "AVRShiftExpand.cpp",
 "AVRSubtarget.cpp",
 "AVRTargetMachine.cpp",
Index: llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
===
--- llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
+++ /dev/null
@@ -1,31 +0,0 @@
-# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - | FileCheck %s
-
 |
-  target triple = "avr--"
-  define void @test() {
-  entry:
-ret void
-  }
-...
-

-name:test
-body: |
-  bb.0.entry:
-
-; CHECK-LABEL: test
-
-; We shouldn't expand things which already have 6-bit imms.
-; CHECK: STDWPtrQRr $r29r28, 63, $r1r0
-STDWPtrQRr $r29r28, 63, $r1r0
-
-; We shouldn't expand things which already have 6-bit imms.
-; CHECK-NEXT: STDWPtrQRr $r29r28, 0, $r1r0
-STDWPtrQRr $r29r28, 0, $r1r0
-
-; CHECK-NEXT: PUSHWRr $r29r28, implicit-def $sp, implicit $sp
-; CHECK-NEXT: $r29r28 = SBCIWRdK $r29r28, -64, implicit-def $sreg, implicit $sreg
-; CHECK-NEXT: STWPtrRr $r29r28, $r1r0
-; CHECK-NEXT: $r29r28 = POPWRd implicit-def $sp, implicit $sp
-STDWPtrQRr $r29r28, 64, $r1r0
-...
Index: llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
===
--- llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
+++ llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo  %s -o - | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
@@ -15,8 +15,52 @@
 
 ; CHECK-LABEL: test
 
-; CHECK:  STDPtrQRr $r29r28, 10, $r0
-; CHECK-NEXT: STDPtrQRr $r29r28, 11, $r1
+; Small displacement (<63):
+; CHECK:  STDPtrQRr $r29r28, 3, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 4, $r1
+STDWPtrQRr $r29r28, 3, $r1r0
 
-STDWPtrQRr $r29r28, 10, $r1r0
+; Small displacement where the destination register is killed:
+; CHECK:  STDPtrQRr $r29r28, 3, $r0
+; CHECK-NEXT: STDPtrQRr killed $r29r28, 4, $r1
+STDWPtrQRr killed $r29r28, 3, $r1r0
+
+; Small displacement where the source register is killed:
+; CHECK:  STDPtrQRr $r29r28, 3, killed $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 4, killed $r1
+STDWPtrQRr $r29r28, 3, killed $r1r0
+
+; Small displacement, near the limit (=62):
+; CHECK:  STDPtrQRr $r29r28, 62, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 63, $r1
+STDWPtrQRr $r29r28, 62, $r1r0
+
+; Large displacement (>=63):
+; CHECK: PUSHRr $r28, implicit-def $sp, implicit $sp
+; CHECK-NEXT: PUSHRr $r29, implicit-def $sp, implicit $sp
+; CHECK-NEXT: $r28 = SBCIRdK killed $r28, 193, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: STPtrRr $r29r28, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 1, $r1
+; CHECK-NEXT: $r29 = POPRd implicit-def $sp, implicit $sp
+; CHECK-NEXT: $r28 = POPRd implicit-def $sp, implicit $sp
+STDWPtrQRr $r29r28, 63, $r1r0
+
+; Large displacement where the destination register is killed:
+; CHECK: $r28 = SBCIRdK killed $r28, 193, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: STPtrRr $r

[PATCH] D122533: [AVR] Remove AVRRelaxMemOperations

2022-03-26 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 updated this revision to Diff 418413.
Patryk27 retitled this revision from "[avr] Remove AVRRelaxMemOperations" to 
"[AVR] Remove AVRRelaxMemOperations".
Patryk27 added a comment.

avr -> AVR


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122533/new/

https://reviews.llvm.org/D122533

Files:
  clang/docs/tools/clang-formatted-files.txt
  llvm/lib/Target/AVR/AVR.h
  llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
  llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp
  llvm/lib/Target/AVR/AVRTargetMachine.cpp
  llvm/lib/Target/AVR/CMakeLists.txt
  llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
  llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
  llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn

Index: llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
===
--- llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
+++ llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
@@ -37,7 +37,6 @@
 "AVRInstrInfo.cpp",
 "AVRMCInstLower.cpp",
 "AVRRegisterInfo.cpp",
-"AVRRelaxMemOperations.cpp",
 "AVRShiftExpand.cpp",
 "AVRSubtarget.cpp",
 "AVRTargetMachine.cpp",
Index: llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
===
--- llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
+++ /dev/null
@@ -1,31 +0,0 @@
-# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - | FileCheck %s
-
 |
-  target triple = "avr--"
-  define void @test() {
-  entry:
-ret void
-  }
-...
-

-name:test
-body: |
-  bb.0.entry:
-
-; CHECK-LABEL: test
-
-; We shouldn't expand things which already have 6-bit imms.
-; CHECK: STDWPtrQRr $r29r28, 63, $r1r0
-STDWPtrQRr $r29r28, 63, $r1r0
-
-; We shouldn't expand things which already have 6-bit imms.
-; CHECK-NEXT: STDWPtrQRr $r29r28, 0, $r1r0
-STDWPtrQRr $r29r28, 0, $r1r0
-
-; CHECK-NEXT: PUSHWRr $r29r28, implicit-def $sp, implicit $sp
-; CHECK-NEXT: $r29r28 = SBCIWRdK $r29r28, -64, implicit-def $sreg, implicit $sreg
-; CHECK-NEXT: STWPtrRr $r29r28, $r1r0
-; CHECK-NEXT: $r29r28 = POPWRd implicit-def $sp, implicit $sp
-STDWPtrQRr $r29r28, 64, $r1r0
-...
Index: llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
===
--- llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
+++ llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo  %s -o - | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
@@ -15,8 +15,52 @@
 
 ; CHECK-LABEL: test
 
-; CHECK:  STDPtrQRr $r29r28, 10, $r0
-; CHECK-NEXT: STDPtrQRr $r29r28, 11, $r1
+; Small displacement (<63):
+; CHECK:  STDPtrQRr $r29r28, 3, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 4, $r1
+STDWPtrQRr $r29r28, 3, $r1r0
 
-STDWPtrQRr $r29r28, 10, $r1r0
+; Small displacement where the destination register is killed:
+; CHECK:  STDPtrQRr $r29r28, 3, $r0
+; CHECK-NEXT: STDPtrQRr killed $r29r28, 4, $r1
+STDWPtrQRr killed $r29r28, 3, $r1r0
+
+; Small displacement where the source register is killed:
+; CHECK:  STDPtrQRr $r29r28, 3, killed $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 4, killed $r1
+STDWPtrQRr $r29r28, 3, killed $r1r0
+
+; Small displacement, near the limit (=62):
+; CHECK:  STDPtrQRr $r29r28, 62, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 63, $r1
+STDWPtrQRr $r29r28, 62, $r1r0
+
+; Large displacement (>=63):
+; CHECK: PUSHRr $r28, implicit-def $sp, implicit $sp
+; CHECK-NEXT: PUSHRr $r29, implicit-def $sp, implicit $sp
+; CHECK-NEXT: $r28 = SBCIRdK killed $r28, 193, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: STPtrRr $r29r28, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 1, $r1
+; CHECK-NEXT: $r29 = POPRd implicit-def $sp, implicit $sp
+; CHECK-NEXT: $r28 = POPRd implicit-def $sp, implicit $sp
+STDWPtrQRr $r29r28, 63, $r1r0
+
+; Large displacement where the destination register is killed:
+; CHECK: $r28 = SBCIRdK killed $r28, 193, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: STPtrRr $r29r28, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 1, $r1
+STDWPtrQRr killed $r29r28, 63, $r1r0
+
+; Large displacement where the source register is killed:
+; CHECK: PUSHRr $r28, implicit-def $sp, implicit $sp
+; CHECK-NEXT: PUSHRr $r29, implicit-def $sp, implicit $sp
+; CHECK-NEXT: $r28 = SBCIRdK killed $r28, 193, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: STPtrRr $r29r28, killed $r0
+; CHECK-NEXT: STDPtrQRr

[PATCH] D122533: [AVR] Remove AVRRelaxMemOperations

2022-03-26 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 added a subscriber: benshi001.
Patryk27 added a comment.

cc @benshi001 (from https://reviews.llvm.org/D114611) 🙂


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[PATCH] D114611: [AVR] Expand STDWSPQRr & STDSPQRr, approach #2

2022-03-26 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 marked 6 inline comments as done.
Patryk27 added a comment.

Thanks for the review!

For the time being, I have extracted the first set of changes into:
https://reviews.llvm.org/D122533




Comment at: llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp:1234
+
+  MachineOperand &Dst = MI.getOperand(0);
+  Register DstReg = Dst.getReg();

benshi001 wrote:
> Why we need an extra `Dst` local variable here? I did not find there is any 
> more use besides `.getReg()` .
Right, I think it must have been an oversight on my side; I have fixed it in 
the follow-up merge request (https://reviews.llvm.org/D122533).



Comment at: llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp:1246
+  // few operations
+  if (Imm >= 63) {
+if (!DstIsKill) {

benshi001 wrote:
> I suggest we make another patch for merge 
> `AVRRelaxMem::relax` into `expand`, for the 
> case `Imm >= 63`. And we select that merge patch as baseline / parent of 
> current patch.
Sure! https://reviews.llvm.org/D122533


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[PATCH] D122533: [AVR] Remove AVRRelaxMemOperations

2022-03-27 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 added a comment.

Hmm, that's weird - I've just re-checked and everything's working correctly on 
my side; maybe you're testing it on an older LLVM revision? (for reference, my 
patch is based off of the current LLVM's main branch, which - at the time of 
writing this comment - is the d9cea8d3a8fff86672174780312674871729578c 
 commit).


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[PATCH] D122533: [AVR] Remove AVRRelaxMemOperations

2022-03-27 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 added inline comments.



Comment at: llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp:1174
 
-  auto MIBLO = buildMI(MBB, MBBI, OpLo)
-   .addReg(DstReg)
-   .addImm(Imm)
-   .addReg(SrcLoReg, getKillRegState(SrcIsKill));
+buildMI(MBB, MBBI, AVR::SBCIWRdK)
+.addReg(DstReg, RegState::Define)

benshi001 wrote:
> The above built error is caused by this line, this should be a SUBI other 
> than a SBCI.
Out of curiosity, why SUBI? (just trying to understand what is the difference 
between both)

It looks like currently - 
https://github.com/llvm/llvm-project/blob/d9cea8d3a8fff86672174780312674871729578c/llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp#L101
 - we expand to SBCI.


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[PATCH] D122533: [AVR] Remove AVRRelaxMemOperations

2022-03-27 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 added a comment.

I think I'm using `=Release` instead of `=Debug`, that would explain the 
difference, yeah;


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[PATCH] D122533: [AVR] Remove AVRRelaxMemOperations

2022-03-27 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 updated this revision to Diff 418443.
Patryk27 added a comment.

SBCI -> SUBI


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D122533

Files:
  clang/docs/tools/clang-formatted-files.txt
  llvm/lib/Target/AVR/AVR.h
  llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
  llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp
  llvm/lib/Target/AVR/AVRTargetMachine.cpp
  llvm/lib/Target/AVR/CMakeLists.txt
  llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
  llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
  llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn

Index: llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
===
--- llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
+++ llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
@@ -37,7 +37,6 @@
 "AVRInstrInfo.cpp",
 "AVRMCInstLower.cpp",
 "AVRRegisterInfo.cpp",
-"AVRRelaxMemOperations.cpp",
 "AVRShiftExpand.cpp",
 "AVRSubtarget.cpp",
 "AVRTargetMachine.cpp",
Index: llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
===
--- llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
+++ /dev/null
@@ -1,31 +0,0 @@
-# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - | FileCheck %s
-
 |
-  target triple = "avr--"
-  define void @test() {
-  entry:
-ret void
-  }
-...
-

-name:test
-body: |
-  bb.0.entry:
-
-; CHECK-LABEL: test
-
-; We shouldn't expand things which already have 6-bit imms.
-; CHECK: STDWPtrQRr $r29r28, 63, $r1r0
-STDWPtrQRr $r29r28, 63, $r1r0
-
-; We shouldn't expand things which already have 6-bit imms.
-; CHECK-NEXT: STDWPtrQRr $r29r28, 0, $r1r0
-STDWPtrQRr $r29r28, 0, $r1r0
-
-; CHECK-NEXT: PUSHWRr $r29r28, implicit-def $sp, implicit $sp
-; CHECK-NEXT: $r29r28 = SBCIWRdK $r29r28, -64, implicit-def $sreg, implicit $sreg
-; CHECK-NEXT: STWPtrRr $r29r28, $r1r0
-; CHECK-NEXT: $r29r28 = POPWRd implicit-def $sp, implicit $sp
-STDWPtrQRr $r29r28, 64, $r1r0
-...
Index: llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
===
--- llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
+++ llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo  %s -o - | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
@@ -15,8 +15,52 @@
 
 ; CHECK-LABEL: test
 
-; CHECK:  STDPtrQRr $r29r28, 10, $r0
-; CHECK-NEXT: STDPtrQRr $r29r28, 11, $r1
+; Small displacement (<63):
+; CHECK:  STDPtrQRr $r29r28, 3, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 4, $r1
+STDWPtrQRr $r29r28, 3, $r1r0
 
-STDWPtrQRr $r29r28, 10, $r1r0
+; Small displacement where the destination register is killed:
+; CHECK:  STDPtrQRr $r29r28, 3, $r0
+; CHECK-NEXT: STDPtrQRr killed $r29r28, 4, $r1
+STDWPtrQRr killed $r29r28, 3, $r1r0
+
+; Small displacement where the source register is killed:
+; CHECK:  STDPtrQRr $r29r28, 3, killed $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 4, killed $r1
+STDWPtrQRr $r29r28, 3, killed $r1r0
+
+; Small displacement, near the limit (=62):
+; CHECK:  STDPtrQRr $r29r28, 62, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 63, $r1
+STDWPtrQRr $r29r28, 62, $r1r0
+
+; Large displacement (>=63):
+; CHECK: PUSHRr $r28, implicit-def $sp, implicit $sp
+; CHECK-NEXT: PUSHRr $r29, implicit-def $sp, implicit $sp
+; CHECK-NEXT: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
+; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: STPtrRr $r29r28, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 1, $r1
+; CHECK-NEXT: $r29 = POPRd implicit-def $sp, implicit $sp
+; CHECK-NEXT: $r28 = POPRd implicit-def $sp, implicit $sp
+STDWPtrQRr $r29r28, 63, $r1r0
+
+; Large displacement where the destination register is killed:
+; CHECK: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
+; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: STPtrRr $r29r28, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 1, $r1
+STDWPtrQRr killed $r29r28, 63, $r1r0
+
+; Large displacement where the source register is killed:
+; CHECK: PUSHRr $r28, implicit-def $sp, implicit $sp
+; CHECK-NEXT: PUSHRr $r29, implicit-def $sp, implicit $sp
+; CHECK-NEXT: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
+; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: STPtrRr $r29r28, killed $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 1, killed $r1
+; CHECK-NEXT: $r29 = POPRd implicit-def $sp, implicit $sp
+; CHECK-NEXT: $r28 = POPRd implicit-def $sp, implicit $sp
+STDWPtrQRr $r29r28, 63, kille

[PATCH] D122533: [AVR] Remove AVRRelaxMemOperations

2022-03-27 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 marked 2 inline comments as done.
Patryk27 added inline comments.



Comment at: llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp:1174
 
-  auto MIBLO = buildMI(MBB, MBBI, OpLo)
-   .addReg(DstReg)
-   .addImm(Imm)
-   .addReg(SrcLoReg, getKillRegState(SrcIsKill));
+buildMI(MBB, MBBI, AVR::SBCIWRdK)
+.addReg(DstReg, RegState::Define)

benshi001 wrote:
> benshi001 wrote:
> > Patryk27 wrote:
> > > benshi001 wrote:
> > > > The above built error is caused by this line, this should be a SUBI 
> > > > other than a SBCI.
> > > Out of curiosity, why SUBI? (just trying to understand what is the 
> > > difference between both)
> > > 
> > > It looks like currently - 
> > > https://github.com/llvm/llvm-project/blob/d9cea8d3a8fff86672174780312674871729578c/llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp#L101
> > >  - we expand to SBCI.
> > I thought this should be an old bug which has never been triggered. 
> > Actually if C bit in SREG is set before current `STWPtrPdRr`, then it is 
> > sure to run into  wrong.
> Sorry, I think this should be a SUBIW, neither SBCIW nor SUBI.
Right, great catch - fixed!


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[PATCH] D122533: [AVR] Remove AVRRelaxMemOperations

2022-03-27 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 added a comment.

Ah, sorry - I've pushed my changes at the same time you created your comment; 
one moment, let me change to SUBIW, then.


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[PATCH] D122533: [AVR] Remove AVRRelaxMemOperations

2022-03-27 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 added a comment.

Ah, nevermind - looks like I've already actually used `SUBIWRdK`.


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[PATCH] D122533: [AVR] Remove AVRRelaxMemOperations

2022-03-27 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 updated this revision to Diff 418460.
Patryk27 added a comment.

Add `-verify-machineinstrs`


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Files:
  clang/docs/tools/clang-formatted-files.txt
  llvm/lib/Target/AVR/AVR.h
  llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
  llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp
  llvm/lib/Target/AVR/AVRTargetMachine.cpp
  llvm/lib/Target/AVR/CMakeLists.txt
  llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
  llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
  llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn

Index: llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
===
--- llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
+++ llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
@@ -37,7 +37,6 @@
 "AVRInstrInfo.cpp",
 "AVRMCInstLower.cpp",
 "AVRRegisterInfo.cpp",
-"AVRRelaxMemOperations.cpp",
 "AVRShiftExpand.cpp",
 "AVRSubtarget.cpp",
 "AVRTargetMachine.cpp",
Index: llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
===
--- llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
+++ /dev/null
@@ -1,31 +0,0 @@
-# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - | FileCheck %s
-
 |
-  target triple = "avr--"
-  define void @test() {
-  entry:
-ret void
-  }
-...
-

-name:test
-body: |
-  bb.0.entry:
-
-; CHECK-LABEL: test
-
-; We shouldn't expand things which already have 6-bit imms.
-; CHECK: STDWPtrQRr $r29r28, 63, $r1r0
-STDWPtrQRr $r29r28, 63, $r1r0
-
-; We shouldn't expand things which already have 6-bit imms.
-; CHECK-NEXT: STDWPtrQRr $r29r28, 0, $r1r0
-STDWPtrQRr $r29r28, 0, $r1r0
-
-; CHECK-NEXT: PUSHWRr $r29r28, implicit-def $sp, implicit $sp
-; CHECK-NEXT: $r29r28 = SBCIWRdK $r29r28, -64, implicit-def $sreg, implicit $sreg
-; CHECK-NEXT: STWPtrRr $r29r28, $r1r0
-; CHECK-NEXT: $r29r28 = POPWRd implicit-def $sp, implicit $sp
-STDWPtrQRr $r29r28, 64, $r1r0
-...
Index: llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
===
--- llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
+++ llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo  %s -o - | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
@@ -15,8 +15,52 @@
 
 ; CHECK-LABEL: test
 
-; CHECK:  STDPtrQRr $r29r28, 10, $r0
-; CHECK-NEXT: STDPtrQRr $r29r28, 11, $r1
+; Small displacement (<63):
+; CHECK:  STDPtrQRr $r29r28, 3, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 4, $r1
+STDWPtrQRr $r29r28, 3, $r1r0
 
-STDWPtrQRr $r29r28, 10, $r1r0
+; Small displacement where the destination register is killed:
+; CHECK:  STDPtrQRr $r29r28, 3, $r0
+; CHECK-NEXT: STDPtrQRr killed $r29r28, 4, $r1
+STDWPtrQRr killed $r29r28, 3, $r1r0
+
+; Small displacement where the source register is killed:
+; CHECK:  STDPtrQRr $r29r28, 3, killed $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 4, killed $r1
+STDWPtrQRr $r29r28, 3, killed $r1r0
+
+; Small displacement, near the limit (=62):
+; CHECK:  STDPtrQRr $r29r28, 62, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 63, $r1
+STDWPtrQRr $r29r28, 62, $r1r0
+
+; Large displacement (>=63):
+; CHECK: PUSHRr $r28, implicit-def $sp, implicit $sp
+; CHECK-NEXT: PUSHRr $r29, implicit-def $sp, implicit $sp
+; CHECK-NEXT: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
+; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: STPtrRr $r29r28, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 1, $r1
+; CHECK-NEXT: $r29 = POPRd implicit-def $sp, implicit $sp
+; CHECK-NEXT: $r28 = POPRd implicit-def $sp, implicit $sp
+STDWPtrQRr $r29r28, 63, $r1r0
+
+; Large displacement where the destination register is killed:
+; CHECK: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
+; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: STPtrRr $r29r28, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 1, $r1
+STDWPtrQRr killed $r29r28, 63, $r1r0
+
+; Large displacement where the source register is killed:
+; CHECK: PUSHRr $r28, implicit-def $sp, implicit $sp
+; CHECK-NEXT: PUSHRr $r29, implicit-def $sp, implicit $sp
+; CHECK-NEXT: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
+; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
+; CHECK-NEXT: STPtrRr $r29r28, killed $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 1, killed $r1
+; CHECK-NEXT: $r29 = POPRd implicit-def $sp, implicit $sp
+; CHECK-NEXT: $r28 = POPRd implicit-def $sp, implicit $

[PATCH] D122533: [AVR] Remove AVRRelaxMemOperations

2022-03-27 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 added a comment.

Ok, I have added the switch; I think a separate patch that adds that switch to 
all the tests would be handy - what do you think?


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[PATCH] D122533: [AVR] Remove AVRRelaxMemOperations

2022-03-27 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 added a comment.

In D122533#3410428 , @benshi001 wrote:

> In D122533#3410259 , @Patryk27 
> wrote:
>
>> Ok, I have added the switch; I think a separate patch that adds that switch 
>> to all of the AVR tests could come handy - what do you think?
>
> No. `-verify-machineinstrs` might be default in the future, which is still 
> under discuss, since it costs longer time. Currently we just make highly 
> risky case with explicit `-verify-machineinstrs`, such as yours. ^_^

Okie, understood - thanks :-)


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[PATCH] D114611: [AVR] Expand STDWSPQRr & STDSPQRr, approach #2

2022-05-09 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 abandoned this revision.
Patryk27 marked 2 inline comments as done.
Patryk27 added a comment.

Changes in this revision were split into separate revisions, so this one is not 
needed anymore.


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[PATCH] D153197: [AVR] Expand shifts during AVRISelLowering

2023-07-09 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 added a comment.

ping ping, @benshi001 👀


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[PATCH] D153197: [AVR] Expand shifts during AVRISelLowering

2023-07-09 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 abandoned this revision.
Patryk27 added a comment.

Superseded by:

- https://reviews.llvm.org/D154785


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[PATCH] D153197: [AVR] Expand shifts during AVRISelLowering

2023-06-18 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 added inline comments.



Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:2207
+  MF->push_back(LoopBB);
+  MachineBasicBlock *ExitBB = EntryBB->splitAt(MI, false);
+

Alright, this is wrong, after all - I've just tested it on a more elaborate 
code in rustc and `EntryBB->removeSuccessor(ExitBB);` triggers an LLVM panic 
(presumably because EntryBB == ExitBB).

I kinda don't understand why doing something like this:

```
MachineBasicBlock *ExitBB = EntryBB->splitAt(MI, false);

if (EntryBB == ExitBB) {
  assert(EntryBB->canFallThrough() && "Expected a fallthrough block!");
  ExitBB = EntryBB->getFallThrough();
}
```

... is not sufficient, though 👀


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[PATCH] D153197: [AVR] Expand shifts during AVRISelLowering

2023-06-24 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 added a comment.

Now that I think about it, there //might// be a simpler way!

So, the underlying issue is that sometimes LLVM spawns new shifts during the 
instruction selection pass - for instance given this IR¹:

  define i64 @test(i64 %x, i32 %y) {
  start:
%0 = or i32 %y, 38
%1 = zext i32 %0 to i64
%2 = lshr i64 %x, %1
ret i64 %2
  }

... this 64-bit shift will not get considered by our shift-expansion pass due 
to a condition here:

https://github.com/llvm/llvm-project/blob/eaaacc3c651e5b2c23bfa9648b6b0d69aab64d00/llvm/lib/Target/AVR/AVRShiftExpand.cpp#L54

... but later, during isel, LLVM **will** reduce this 64-bit shift into a 
32-bit shift² and then ask us to expand this brand new 32-bit shift - that 
causes a panic since we expect those to have been already expanded.

In order to solve this issue, I think we could simply expand //all// 
variable-shifts greater than i8 (instead of expanding only 32-bit shifts):

  diff --git a/llvm/lib/Target/AVR/AVRShiftExpand.cpp 
b/llvm/lib/Target/AVR/AVRShiftExpand.cpp
  index b7dcd860467d..4ea6d9fdb57c 100644
  --- a/llvm/lib/Target/AVR/AVRShiftExpand.cpp
  +++ b/llvm/lib/Target/AVR/AVRShiftExpand.cpp
  @@ -51,8 +51,7 @@ bool AVRShiftExpand::runOnFunction(Function &F) {
   if (!I.isShift())
 // Only expand shift instructions (shl, lshr, ashr).
 continue;
  -if (I.getType() != Type::getInt32Ty(Ctx))
  -  // Only expand plain i32 types.
  +if (I.getType() == Type::getInt8Ty(Ctx))
 continue;
   if (isa(I.getOperand(1)))
 // Only expand when the shift amount is not known.
  @@ -75,7 +74,7 @@ bool AVRShiftExpand::runOnFunction(Function &F) {
   void AVRShiftExpand::expand(BinaryOperator *BI) {
 auto &Ctx = BI->getContext();
 IRBuilder<> Builder(BI);
  -  Type *Int32Ty = Type::getInt32Ty(Ctx);
  +  Type *InputTy = cast(BI)->getType();
 Type *Int8Ty = Type::getInt8Ty(Ctx);
 Value *Int8Zero = ConstantInt::get(Int8Ty, 0);
   
  @@ -101,7 +100,7 @@ void AVRShiftExpand::expand(BinaryOperator *BI) {
 Builder.SetInsertPoint(LoopBB);
 PHINode *ShiftAmountPHI = Builder.CreatePHI(Int8Ty, 2);
 ShiftAmountPHI->addIncoming(ShiftAmount, BB);
  -  PHINode *ValuePHI = Builder.CreatePHI(Int32Ty, 2);
  +  PHINode *ValuePHI = Builder.CreatePHI(InputTy, 2);
 ValuePHI->addIncoming(BI->getOperand(0), BB);
   
 // Subtract the shift amount by one, as we're shifting one this loop
  @@ -116,13 +115,13 @@ void AVRShiftExpand::expand(BinaryOperator *BI) {
 Value *ValueShifted;
 switch (BI->getOpcode()) {
 case Instruction::Shl:
  -ValueShifted = Builder.CreateShl(ValuePHI, ConstantInt::get(Int32Ty, 1));
  +ValueShifted = Builder.CreateShl(ValuePHI, ConstantInt::get(InputTy, 1));
   break;
 case Instruction::LShr:
  -ValueShifted = Builder.CreateLShr(ValuePHI, ConstantInt::get(Int32Ty, 
1));
  +ValueShifted = Builder.CreateLShr(ValuePHI, ConstantInt::get(InputTy, 
1));
   break;
 case Instruction::AShr:
  -ValueShifted = Builder.CreateAShr(ValuePHI, ConstantInt::get(Int32Ty, 
1));
  +ValueShifted = Builder.CreateAShr(ValuePHI, ConstantInt::get(InputTy, 
1));
   break;
 default:
   llvm_unreachable("asked to expand an instruction that is not a shift");
  @@ -137,7 +136,7 @@ void AVRShiftExpand::expand(BinaryOperator *BI) {
 // Collect the resulting value. This is necessary in the IR but won't 
produce
 // any actual instructions.
 Builder.SetInsertPoint(BI);
  -  PHINode *Result = Builder.CreatePHI(Int32Ty, 2);
  +  PHINode *Result = Builder.CreatePHI(InputTy, 2);
 Result->addIncoming(BI->getOperand(0), BB);
 Result->addIncoming(ValueShifted, LoopBB);

Overall, this solution seems to work - I've checked it on a couple of Rust 
applications and the binaries behave correctly, both some simple and more 
complex ones.

I think the only disadvantage of this approach, as compared to expanding shifts 
during isel, are optimizations: expanding shifts eagerly means that we'll lose 
some of the optimizations we could have applied otherwise.

For instance, following that first example from Rust's standard library, we 
will expand that instruction into a 64-bit shift even though in principle a 
32-bit shift would suffice (but we don't know that yet during shift-expansion 
pass).

For safety, we could implement this simpler approach first, as presented in the 
diff here, and maybe come back to merging shift-expansion with isel in the 
future - what do you think about it?

¹ minimized case from Rust's standard library - originally: 
`_ZN4core3num7dec2flt6lemire13compute_float17hc1d4de6247502c96E`
² I'm not 100% sure why, though - seems to be somehow related to this `or + 
zext` combination


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[PATCH] D153197: [AVR] Expand shifts during AVRISelLowering

2023-06-17 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 created this revision.
Herald added subscribers: Jim, JDevlieghere, hiraditya, dylanmckay.
Herald added a project: All.
Patryk27 requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Some passes can introduce shifts after AVRShiftExpandPass has completed;
if this happens, we panic during isel because we assume such shifts must
have been already expanded before.

This commit integrates our shift-expansion pass with isel-selection pass
so that isel doesn't get surprised by shifts of non-constant amounts
anymore.

Spotted in the wild in rustc:

- https://github.com/rust-lang/compiler-builtins/issues/523
- https://github.com/rust-lang/rust/issues/112140


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Files:
  clang/docs/tools/clang-formatted-files.txt
  llvm/lib/Target/AVR/AVR.h
  llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
  llvm/lib/Target/AVR/AVRISelLowering.cpp
  llvm/lib/Target/AVR/AVRShiftExpand.cpp
  llvm/lib/Target/AVR/AVRTargetMachine.cpp
  llvm/lib/Target/AVR/CMakeLists.txt
  llvm/test/CodeGen/AVR/shift-expand.ll
  llvm/test/CodeGen/AVR/shift-loop.ll
  llvm/test/CodeGen/AVR/shift32.ll
  llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn

Index: llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
===
--- llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
+++ llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
@@ -37,7 +37,6 @@
 "AVRInstrInfo.cpp",
 "AVRMCInstLower.cpp",
 "AVRRegisterInfo.cpp",
-"AVRShiftExpand.cpp",
 "AVRSubtarget.cpp",
 "AVRTargetMachine.cpp",
 "AVRTargetObjectFile.cpp",
Index: llvm/test/CodeGen/AVR/shift32.ll
===
--- llvm/test/CodeGen/AVR/shift32.ll
+++ llvm/test/CodeGen/AVR/shift32.ll
@@ -1,6 +1,67 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=avr -mattr=movw -verify-machineinstrs | FileCheck %s
 
+; Shift by a number unknown at compile time.
+; The 'optsize' attribute is set to avoid duplicating part of the loop.
+; TODO: it is more efficent to jump at the start and do the check where the
+; 'rjmp' is now. The branch relaxation pass puts them in this non-optimal order.
+
+define i32 @shl_i32_n(i32 %a, i32 %b) #0 {
+; CHECK-LABEL: shl_i32_n:
+; CHECK:   ; %bb.0:
+; CHECK-NEXT:  .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:dec r18
+; CHECK-NEXT:brmi .LBB0_3
+; CHECK-NEXT:  ; %bb.2: ; in Loop: Header=BB0_1 Depth=1
+; CHECK-NEXT:lsl r22
+; CHECK-NEXT:rol r23
+; CHECK-NEXT:rol r24
+; CHECK-NEXT:rol r25
+; CHECK-NEXT:rjmp .LBB0_1
+; CHECK-NEXT:  .LBB0_3:
+; CHECK-NEXT:ret
+  %res = shl i32 %a, %b
+  ret i32 %res
+}
+
+define i32 @lshr_i32_n(i32 %a, i32 %b) #0 {
+; CHECK-LABEL: lshr_i32_n:
+; CHECK:   ; %bb.0:
+; CHECK-NEXT:  .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:dec r18
+; CHECK-NEXT:brmi .LBB1_3
+; CHECK-NEXT:  ; %bb.2: ; in Loop: Header=BB1_1 Depth=1
+; CHECK-NEXT:lsr r25
+; CHECK-NEXT:ror r24
+; CHECK-NEXT:ror r23
+; CHECK-NEXT:ror r22
+; CHECK-NEXT:rjmp .LBB1_1
+; CHECK-NEXT:  .LBB1_3:
+; CHECK-NEXT:ret
+  %res = lshr i32 %a, %b
+  ret i32 %res
+}
+
+define i32 @ashr_i32_n(i32 %a, i32 %b) #0 {
+; CHECK-LABEL: ashr_i32_n:
+; CHECK:   ; %bb.0:
+; CHECK-NEXT:  .LBB2_1: ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:dec r18
+; CHECK-NEXT:brmi .LBB2_3
+; CHECK-NEXT:  ; %bb.2: ; in Loop: Header=BB2_1 Depth=1
+; CHECK-NEXT:asr r25
+; CHECK-NEXT:ror r24
+; CHECK-NEXT:ror r23
+; CHECK-NEXT:ror r22
+; CHECK-NEXT:rjmp .LBB2_1
+; CHECK-NEXT:  .LBB2_3:
+; CHECK-NEXT:ret
+  %res = ashr i32 %a, %b
+  ret i32 %res
+}
+
+; Shift by a constant known at compile time.
+
 define i32 @shl_i32_1(i32 %a) {
 ; CHECK-LABEL: shl_i32_1:
 ; CHECK:   ; %bb.0:
@@ -575,3 +636,5 @@
   %res = ashr i32 %a, 31
   ret i32 %res
 }
+
+attributes #0 = { optsize }
Index: llvm/test/CodeGen/AVR/shift-loop.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AVR/shift-loop.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc < %s -mtriple=avr -verify-machineinstrs -stop-after=dead-mi-elimination | FileCheck %s
+
+; This test shows the machine IR that is generated when lowering a shift
+; operation to a loop.
+
+define i32 @shl_i32_n(i32 %a, i32 %b) #0 {
+  ; CHECK-LABEL: name: shl_i32_n
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   successors: %bb.1(0x8000)
+  ; CHECK-NEXT:   liveins: $r23r22, $r25r24, $r19r18
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:dregs = COPY $r19r18
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:dregs = COPY $r25r24
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:dregs = COPY $r23r22
+  ; CHECK-NEXT:   [[COPY3:%[0

[PATCH] D153197: [AVR] Expand shifts during AVRISelLowering

2023-06-17 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 added inline comments.



Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:2193
+// (the output registers are stored in this array on return).
+static MachineBasicBlock *insertMultibyteShiftLoop(
+MachineInstr &MI, MachineBasicBlock *BB, Register ShiftNum,

Note that I've changed to code to re-arrange the generated blocks a bit, from:

```
body: |
  bb.0 (%ir-block.0):
successors: %bb.2(0x8000)
liveins: $r23r22, $r25r24, $r19r18
  
%2:dregs = COPY $r19r18
%1:dregs = COPY $r25r24
%0:dregs = COPY $r23r22
%4:gpr8 = COPY %2.sub_lo
RJMPk %bb.2
  
  bb.1 (%ir-block.0):
successors: %bb.2(0x8000)
  
%12:gpr8 = ADDRdRr %10, %10, implicit-def $sreg
%13:gpr8 = ADCRdRr %9, %9, implicit-def $sreg, implicit $sreg
%14:gpr8 = ADCRdRr %8, %8, implicit-def $sreg, implicit $sreg
%15:gpr8 = ADCRdRr %7, %7, implicit-def $sreg, implicit $sreg
  
  bb.2 (%ir-block.0):
successors: %bb.1(0x4000), %bb.3(0x4000)
  
%7:gpr8 = PHI %1.sub_hi, %bb.0, %15, %bb.1
%8:gpr8 = PHI %1.sub_lo, %bb.0, %14, %bb.1
%9:gpr8 = PHI %0.sub_hi, %bb.0, %13, %bb.1
%10:gpr8 = PHI %0.sub_lo, %bb.0, %12, %bb.1
%16:gpr8 = PHI %4, %bb.0, %17, %bb.1
%17:gpr8 = DECRd %16, implicit-def $sreg
BRPLk %bb.1, implicit $sreg
  
  bb.3 (%ir-block.0):
%6:dregs = REG_SEQUENCE %7, %subreg.sub_hi, %8, %subreg.sub_lo
%5:dregs = REG_SEQUENCE %9, %subreg.sub_hi, %10, %subreg.sub_lo
$r23r22 = COPY %5
$r25r24 = COPY %6
RET implicit $r23r22, implicit $r25r24, implicit $r1
```

... to:

```
body: |
  bb.0 (%ir-block.0):
successors: %bb.1(0x8000)
liveins: $r23r22, $r25r24, $r19r18
  
%2:dregs = COPY $r19r18
%1:dregs = COPY $r25r24
%0:dregs = COPY $r23r22
%4:gpr8 = COPY %2.sub_lo
# fall-through instead of jumping
  
  bb.1 (%ir-block.0):
successors: %bb.2(0x4000), %bb.3(0x4000)
  
%7:gpr8 = PHI %1.sub_hi, %bb.0, %15, %bb.2
%8:gpr8 = PHI %1.sub_lo, %bb.0, %14, %bb.2
%9:gpr8 = PHI %0.sub_hi, %bb.0, %13, %bb.2
%10:gpr8 = PHI %0.sub_lo, %bb.0, %12, %bb.2
%16:gpr8 = PHI %4, %bb.0, %17, %bb.2
%17:gpr8 = DECRd %16, implicit-def $sreg
BRMIk %bb.3, implicit $sreg # <- reversed comparison + fallthrough
  
  bb.2 (%ir-block.0):
successors: %bb.1(0x8000)
  
%12:gpr8 = ADDRdRr %10, %10, implicit-def $sreg
%13:gpr8 = ADCRdRr %9, %9, implicit-def $sreg, implicit $sreg
%14:gpr8 = ADCRdRr %8, %8, implicit-def $sreg, implicit $sreg
%15:gpr8 = ADCRdRr %7, %7, implicit-def $sreg, implicit $sreg
RJMPk %bb.1 # <- jump to the beginning
  
  bb.3 (%ir-block.0):
%6:dregs = REG_SEQUENCE %7, %subreg.sub_hi, %8, %subreg.sub_lo
%5:dregs = REG_SEQUENCE %9, %subreg.sub_hi, %10, %subreg.sub_lo
$r23r22 = COPY %5
$r25r24 = COPY %6
RET implicit $r23r22, implicit $r25r24, implicit $r1
```

It looks like the generated assembly remained the same, I've also checked the 
actual binary through rustc + simavr.


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[PATCH] D114611: [AVR] Expand STDWSPQRr & STDSPQRr, approach #2

2022-01-22 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 updated this revision to Diff 402203.
Herald added subscribers: cfe-commits, mgorny.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114611/new/

https://reviews.llvm.org/D114611

Files:
  clang/docs/tools/clang-formatted-files.txt
  llvm/lib/Target/AVR/AVR.h
  llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
  llvm/lib/Target/AVR/AVRFrameLowering.cpp
  llvm/lib/Target/AVR/AVRRegisterInfo.cpp
  llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp
  llvm/lib/Target/AVR/AVRSubtarget.h
  llvm/lib/Target/AVR/AVRTargetMachine.cpp
  llvm/lib/Target/AVR/CMakeLists.txt
  llvm/test/CodeGen/AVR/PR31344.ll
  llvm/test/CodeGen/AVR/PR31345.ll
  llvm/test/CodeGen/AVR/PR37143.ll
  llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
  llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
  llvm/test/CodeGen/AVR/hardware-mul.ll
  llvm/test/CodeGen/AVR/mul-hardware.ll
  llvm/test/CodeGen/AVR/mul-software.ll
  llvm/test/CodeGen/AVR/past-bugs/D114611.ll
  llvm/test/CodeGen/AVR/past-bugs/PR31344.ll
  llvm/test/CodeGen/AVR/past-bugs/PR31345.ll
  llvm/test/CodeGen/AVR/past-bugs/PR37143.ll
  llvm/test/CodeGen/AVR/past-bugs/avr-rust-issue-123.ll
  llvm/test/CodeGen/AVR/past-bugs/frmidx-iterator-bug.ll
  llvm/test/CodeGen/AVR/past-bugs/rust-avr-bug-112.ll
  llvm/test/CodeGen/AVR/past-bugs/rust-avr-bug-37.ll
  llvm/test/CodeGen/AVR/past-bugs/rust-avr-bug-95.ll
  llvm/test/CodeGen/AVR/past-bugs/rust-avr-bug-99.ll
  llvm/test/CodeGen/AVR/pseudo/STDSPQRr.mir
  llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
  llvm/test/CodeGen/AVR/pseudo/STDWSPQRr.mir
  llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
  llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
  llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
  llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
  llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
  llvm/test/CodeGen/AVR/software-mul.ll
  llvm/utils/UpdateTestChecks/asm.py
  llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn

Index: llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
===
--- llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
+++ llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
@@ -37,7 +37,6 @@
 "AVRInstrInfo.cpp",
 "AVRMCInstLower.cpp",
 "AVRRegisterInfo.cpp",
-"AVRRelaxMemOperations.cpp",
 "AVRShiftExpand.cpp",
 "AVRSubtarget.cpp",
 "AVRTargetMachine.cpp",
Index: llvm/utils/UpdateTestChecks/asm.py
===
--- llvm/utils/UpdateTestChecks/asm.py
+++ llvm/utils/UpdateTestChecks/asm.py
@@ -391,6 +391,7 @@
 def get_triple_from_march(march):
   triples = {
   'amdgcn': 'amdgcn',
+  'avr': 'avr',
   'r600': 'r600',
   'mips': 'mips',
   'sparc': 'sparc',
Index: llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
===
--- llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
+++ /dev/null
@@ -1,31 +0,0 @@
-# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - | FileCheck %s
-
 |
-  target triple = "avr--"
-  define void @test() {
-  entry:
-ret void
-  }
-...
-

-name:test
-body: |
-  bb.0.entry:
-
-; CHECK-LABEL: test
-
-; We shouldn't expand things which already have 6-bit imms.
-; CHECK: STDWPtrQRr $r29r28, 63, $r1r0
-STDWPtrQRr $r29r28, 63, $r1r0
-
-; We shouldn't expand things which already have 6-bit imms.
-; CHECK-NEXT: STDWPtrQRr $r29r28, 0, $r1r0
-STDWPtrQRr $r29r28, 0, $r1r0
-
-; CHECK-NEXT: PUSHWRr $r29r28, implicit-def $sp, implicit $sp
-; CHECK-NEXT: $r29r28 = SBCIWRdK $r29r28, -64, implicit-def $sreg, implicit $sreg
-; CHECK-NEXT: STWPtrRr $r29r28, $r1r0
-; CHECK-NEXT: $r29r28 = POPWRd implicit-def $sp, implicit $sp
-STDWPtrQRr $r29r28, 64, $r1r0
-...
Index: llvm/test/CodeGen/AVR/pseudo/STDWSPQRr.mir
===
--- /dev/null
+++ llvm/test/CodeGen/AVR/pseudo/STDWSPQRr.mir
@@ -0,0 +1,20 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+ret void
+  }
+...
+
+---
+name:test
+body: |
+  bb.0.entry:
+
+; CHECK: STDPtrQRr $r31r30, 10, $r9
+; CHECK-NEXT: STDPtrQRr $r31r30, 11, $r10
+
+STDWSPQRr $sp, 10, $r10r9, implicit-def $sp
+...
Index: llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
===
--- llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
+++ llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
@@ -15,8 +15,52 @@
 
 ; CHECK-LABEL: test
 
-; CHECK:  STDPtrQRr $r29r28, 10, $r0
-; CHECK-NEXT: STDPtrQRr $r29r28, 11, $r1
+; Small displacement (<63):
+; CHECK:  STDPtrQRr $r29r28, 3, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 4, $r1
+STDWPtrQRr $r29r28, 3, $r1r0
 
-STDWPtrQRr $r29r28, 10, $r1r0
+; Small displacement where the destination register is

[PATCH] D114611: [AVR] Expand STDWSPQRr & STDSPQRr, approach #2

2022-01-22 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 added inline comments.



Comment at: llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp:1261
+if (!DstIsKill) {
+  buildMI(MBB, MBBI, AVR::POPWRd).addDef(Dst.getReg());
+}

I'm not sure if that's correct, but the previous approach:
```
buildMI(MBB, MBBI, AVR::POPWRd)
.addDef(Ptr.getReg(), getKillRegState(Ptr.isKill()));
```
... wasn't correct either, since it's not possible to `addDef()` a killed 
register (this crashes LLVM, but there was no test to check it on our side).


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[PATCH] D114611: [AVR] Expand STDWSPQRr & STDSPQRr, approach #2

2022-01-22 Thread Patryk Wychowaniec via Phabricator via cfe-commits 
Patryk27 updated this revision to Diff 402213.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114611/new/

https://reviews.llvm.org/D114611

Files:
  clang/docs/tools/clang-formatted-files.txt
  llvm/lib/Target/AVR/AVR.h
  llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
  llvm/lib/Target/AVR/AVRFrameLowering.cpp
  llvm/lib/Target/AVR/AVRRegisterInfo.cpp
  llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp
  llvm/lib/Target/AVR/AVRSubtarget.h
  llvm/lib/Target/AVR/AVRTargetMachine.cpp
  llvm/lib/Target/AVR/CMakeLists.txt
  llvm/test/CodeGen/AVR/PR31344.ll
  llvm/test/CodeGen/AVR/PR31345.ll
  llvm/test/CodeGen/AVR/PR37143.ll
  llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
  llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
  llvm/test/CodeGen/AVR/hardware-mul.ll
  llvm/test/CodeGen/AVR/mul-hardware.ll
  llvm/test/CodeGen/AVR/mul-software.ll
  llvm/test/CodeGen/AVR/past-bugs/D114611.ll
  llvm/test/CodeGen/AVR/past-bugs/PR31344.ll
  llvm/test/CodeGen/AVR/past-bugs/PR31345.ll
  llvm/test/CodeGen/AVR/past-bugs/PR37143.ll
  llvm/test/CodeGen/AVR/past-bugs/avr-rust-issue-123.ll
  llvm/test/CodeGen/AVR/past-bugs/frmidx-iterator-bug.ll
  llvm/test/CodeGen/AVR/past-bugs/rust-avr-bug-112.ll
  llvm/test/CodeGen/AVR/past-bugs/rust-avr-bug-37.ll
  llvm/test/CodeGen/AVR/past-bugs/rust-avr-bug-95.ll
  llvm/test/CodeGen/AVR/past-bugs/rust-avr-bug-99.ll
  llvm/test/CodeGen/AVR/pseudo/STDSPQRr.mir
  llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
  llvm/test/CodeGen/AVR/pseudo/STDWSPQRr.mir
  llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
  llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
  llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
  llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
  llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
  llvm/test/CodeGen/AVR/software-mul.ll
  llvm/utils/UpdateTestChecks/asm.py
  llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn

Index: llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
===
--- llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
+++ llvm/utils/gn/secondary/llvm/lib/Target/AVR/BUILD.gn
@@ -37,7 +37,6 @@
 "AVRInstrInfo.cpp",
 "AVRMCInstLower.cpp",
 "AVRRegisterInfo.cpp",
-"AVRRelaxMemOperations.cpp",
 "AVRShiftExpand.cpp",
 "AVRSubtarget.cpp",
 "AVRTargetMachine.cpp",
Index: llvm/utils/UpdateTestChecks/asm.py
===
--- llvm/utils/UpdateTestChecks/asm.py
+++ llvm/utils/UpdateTestChecks/asm.py
@@ -391,6 +391,7 @@
 def get_triple_from_march(march):
   triples = {
   'amdgcn': 'amdgcn',
+  'avr': 'avr',
   'r600': 'r600',
   'mips': 'mips',
   'sparc': 'sparc',
Index: llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
===
--- llvm/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
+++ /dev/null
@@ -1,31 +0,0 @@
-# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - | FileCheck %s
-
 |
-  target triple = "avr--"
-  define void @test() {
-  entry:
-ret void
-  }
-...
-

-name:test
-body: |
-  bb.0.entry:
-
-; CHECK-LABEL: test
-
-; We shouldn't expand things which already have 6-bit imms.
-; CHECK: STDWPtrQRr $r29r28, 63, $r1r0
-STDWPtrQRr $r29r28, 63, $r1r0
-
-; We shouldn't expand things which already have 6-bit imms.
-; CHECK-NEXT: STDWPtrQRr $r29r28, 0, $r1r0
-STDWPtrQRr $r29r28, 0, $r1r0
-
-; CHECK-NEXT: PUSHWRr $r29r28, implicit-def $sp, implicit $sp
-; CHECK-NEXT: $r29r28 = SBCIWRdK $r29r28, -64, implicit-def $sreg, implicit $sreg
-; CHECK-NEXT: STWPtrRr $r29r28, $r1r0
-; CHECK-NEXT: $r29r28 = POPWRd implicit-def $sp, implicit $sp
-STDWPtrQRr $r29r28, 64, $r1r0
-...
Index: llvm/test/CodeGen/AVR/pseudo/STDWSPQRr.mir
===
--- /dev/null
+++ llvm/test/CodeGen/AVR/pseudo/STDWSPQRr.mir
@@ -0,0 +1,20 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+ret void
+  }
+...
+
+---
+name:test
+body: |
+  bb.0.entry:
+
+; CHECK: STDPtrQRr $r31r30, 10, $r9
+; CHECK-NEXT: STDPtrQRr $r31r30, 11, $r10
+
+STDWSPQRr $sp, 10, $r10r9, implicit-def $sp
+...
Index: llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
===
--- llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
+++ llvm/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
@@ -15,8 +15,52 @@
 
 ; CHECK-LABEL: test
 
-; CHECK:  STDPtrQRr $r29r28, 10, $r0
-; CHECK-NEXT: STDPtrQRr $r29r28, 11, $r1
+; Small displacement (<63):
+; CHECK:  STDPtrQRr $r29r28, 3, $r0
+; CHECK-NEXT: STDPtrQRr $r29r28, 4, $r1
+STDWPtrQRr $r29r28, 3, $r1r0
 
-STDWPtrQRr $r29r28, 10, $r1r0
+; Small displacement where the destination register is killed:
+; CHECK:  STDPtrQRr $r29r28, 3, $r0
+; CHECK-NEXT: STDPt