[PATCH] D49890: Clang-Tidy Export Problem

2020-04-29 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian added a comment.

I found this patch while searching for a similar problem I faced while tryin to 
use clang-tidy to fix some warnings in V8 (Chrome's JavaScript engine).
The setup for our compilation is as such:

- basedir
  - src/
  - out/ -arch1/
  - .o files, generated files
  - compile_commands.json
- arch2/

We use ninja to build, so usually with a command like `ninja -C out/arch1`, 
this means (roughly) cd into out/arch1 and build.

Given this, I have an alternative suggestion for a fix. In run-clang-tidy.py 
apply_fixes, we call the clang-apply-replacement with cwd set to build_path, 
like so:

  diff --git a/clang-tools-extra/clang-tidy/tool/run-clang-tidy.py 
b/clang-tools-extra/clang-tidy/tool/run-clang-tidy.py
  index 1eb13529575..cde9e3671af 100755
  --- a/clang-tools-extra/clang-tidy/tool/run-clang-tidy.py
  +++ b/clang-tools-extra/clang-tidy/tool/run-clang-tidy.py
  @@ -150,7 +150,7 @@ def apply_fixes(args, tmpdir):
 if args.style:
   invocation.append('-style=' + args.style)
 invocation.append(tmpdir)
  -  subprocess.call(invocation)
  +  subprocess.call(invocation, cwd=args.build_path)

def run_tidy(args, tmpdir, build_path, queue, lock, failed_files):

I don't know the internals of clang-tidy enough to do this, but it works for 
me. And it seems reasonable, since the Replacement FilePath in the yaml file 
consumed by clang-apply-replacement was generated as a path relative to the 
build_path anyway. For now this is a sufficient hack for my use case (tried 
with with just 1 data point as a test), and it will be good to get feedback if 
this fix is correct. Thanks!


Repository:
  rCTE Clang Tools Extra

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D49890/new/

https://reviews.llvm.org/D49890



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D110111: [WebAssembly] Add relaxed-simd feature

2021-09-20 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian created this revision.
ngzhian added a reviewer: tlively.
Herald added subscribers: dang, ecnelises, sunfish, jgravelle-google, sbc100, 
dschuff.
ngzhian requested review of this revision.
Herald added subscribers: cfe-commits, aheejin.
Herald added a project: clang.

This currently only defines a constant, but it the future will be used
to gate builtins for experimenting and prototyping relaxed-simd proposal
(https://github.com/WebAssembly/relaxed-simd/).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110111

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/WebAssembly.cpp
  clang/lib/Basic/Targets/WebAssembly.h
  clang/test/Preprocessor/wasm-target-features.c

Index: clang/test/Preprocessor/wasm-target-features.c
===
--- clang/test/Preprocessor/wasm-target-features.c
+++ clang/test/Preprocessor/wasm-target-features.c
@@ -7,6 +7,15 @@
 //
 // SIMD128:#define __wasm_simd128__ 1{{$}}
 
+// RUN: %clang -E -dM %s -o - 2>&1 \
+// RUN: -target wasm32-unknown-unknown -mrelaxed-simd \
+// RUN:   | FileCheck %s -check-prefix=RELAXED-SIMD
+// RUN: %clang -E -dM %s -o - 2>&1 \
+// RUN: -target wasm64-unknown-unknown -mrelaxed-simd \
+// RUN:   | FileCheck %s -check-prefix=RELAXED-SIMD
+//
+// RELAXED-SIMD:#define __wasm_relaxed_simd__ 1{{$}}
+
 // RUN: %clang -E -dM %s -o - 2>&1 \
 // RUN: -target wasm32-unknown-unknown -mnontrapping-fptoint \
 // RUN:   | FileCheck %s -check-prefix=NONTRAPPING-FPTOINT
Index: clang/lib/Basic/Targets/WebAssembly.h
===
--- clang/lib/Basic/Targets/WebAssembly.h
+++ clang/lib/Basic/Targets/WebAssembly.h
@@ -27,6 +27,7 @@
   enum SIMDEnum {
 NoSIMD,
 SIMD128,
+RelaxedSIMD,
   } SIMDLevel = NoSIMD;
 
   bool HasNontrappingFPToInt = false;
Index: clang/lib/Basic/Targets/WebAssembly.cpp
===
--- clang/lib/Basic/Targets/WebAssembly.cpp
+++ clang/lib/Basic/Targets/WebAssembly.cpp
@@ -46,6 +46,7 @@
 bool WebAssemblyTargetInfo::hasFeature(StringRef Feature) const {
   return llvm::StringSwitch(Feature)
   .Case("simd128", SIMDLevel >= SIMD128)
+  .Case("relaxed-simd", SIMDLevel >= RelaxedSIMD)
   .Case("nontrapping-fptoint", HasNontrappingFPToInt)
   .Case("sign-ext", HasSignExt)
   .Case("exception-handling", HasExceptionHandling)
@@ -72,6 +73,8 @@
   defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
   if (SIMDLevel >= SIMD128)
 Builder.defineMacro("__wasm_simd128__");
+  if (SIMDLevel >= RelaxedSIMD)
+Builder.defineMacro("__wasm_relaxed_simd__");
   if (HasNontrappingFPToInt)
 Builder.defineMacro("__wasm_nontrapping_fptoint__");
   if (HasSignExt)
@@ -99,6 +102,9 @@
 case SIMD128:
   Features["simd128"] = true;
   LLVM_FALLTHROUGH;
+case RelaxedSIMD:
+  Features["relaxed-simd"] = true;
+  LLVM_FALLTHROUGH;
 case NoSIMD:
   break;
 }
@@ -109,6 +115,9 @@
   case NoSIMD:
   case SIMD128:
 Features["simd128"] = false;
+LLVM_FALLTHROUGH;
+  case RelaxedSIMD:
+Features["relaxed-simd"] = false;
 break;
   }
 }
@@ -118,6 +127,8 @@
   bool Enabled) const {
   if (Name == "simd128")
 setSIMDLevel(Features, SIMD128, Enabled);
+  else if (Name == "relaxed-simd")
+setSIMDLevel(Features, RelaxedSIMD, Enabled);
   else
 Features[Name] = Enabled;
 }
@@ -149,6 +160,14 @@
   SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
   continue;
 }
+if (Feature == "+relaxed-simd") {
+  SIMDLevel = std::max(SIMDLevel, RelaxedSIMD);
+  continue;
+}
+if (Feature == "-relaxed-simd") {
+  SIMDLevel = std::min(SIMDLevel, SIMDEnum(RelaxedSIMD - 1));
+  continue;
+}
 if (Feature == "+nontrapping-fptoint") {
   HasNontrappingFPToInt = true;
   continue;
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3310,6 +3310,8 @@
 
 def msimd128 : Flag<["-"], "msimd128">, Group;
 def mno_simd128 : Flag<["-"], "mno-simd128">, Group;
+def mrelaxed_simd : Flag<["-"], "mrelaxed-simd">, Group;
+def mno_relaxed_simd : Flag<["-"], "mno-relaxed-simd">, Group;
 def mnontrapping_fptoint : Flag<["-"], "mnontrapping-fptoint">, Group;
 def mno_nontrapping_fptoint : Flag<["-"], "mno-nontrapping-fptoint">, Group;
 def msign_ext : Flag<["-"], "msign-ext">, Group;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D110111: [WebAssembly] Add relaxed-simd feature

2021-09-20 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian added a comment.

I followed https://reviews.llvm.org/rGb7b9fdc114c1f9c788da914dac5c343277805446 
for this, hope it's right, ptal Thomas.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110111/new/

https://reviews.llvm.org/D110111

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D110111: [WebAssembly] Add relaxed-simd feature

2021-09-22 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian updated this revision to Diff 374262.
ngzhian marked an inline comment as done.
ngzhian added a comment.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

Fix fallthrough, add feature to WebAssembly subtarget


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110111/new/

https://reviews.llvm.org/D110111

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/WebAssembly.cpp
  clang/lib/Basic/Targets/WebAssembly.h
  clang/test/Preprocessor/wasm-target-features.c
  llvm/lib/Target/WebAssembly/WebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h

Index: llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
===
--- llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
+++ llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
@@ -36,6 +36,7 @@
   enum SIMDEnum {
 NoSIMD,
 SIMD128,
+RelaxedSIMD,
   } SIMDLevel = NoSIMD;
 
   bool HasAtomics = false;
@@ -89,6 +90,7 @@
   // Predicates used by WebAssemblyInstrInfo.td.
   bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
   bool hasSIMD128() const { return SIMDLevel >= SIMD128; }
+  bool hasRelaxedSIMD() const { return SIMDLevel >= RelaxedSIMD; }
   bool hasAtomics() const { return HasAtomics; }
   bool hasNontrappingFPToInt() const { return HasNontrappingFPToInt; }
   bool hasSignExt() const { return HasSignExt; }
Index: llvm/lib/Target/WebAssembly/WebAssembly.td
===
--- llvm/lib/Target/WebAssembly/WebAssembly.td
+++ llvm/lib/Target/WebAssembly/WebAssembly.td
@@ -25,6 +25,9 @@
 def FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128",
   "Enable 128-bit SIMD">;
 
+def FeatureRelaxedSIMD : SubtargetFeature<"relaxed-simd", "SIMDLevel", "RelaxedSIMD",
+  "Enable relaxed-simd instructions">;
+
 def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
   "Enable Atomics">;
 
Index: clang/test/Preprocessor/wasm-target-features.c
===
--- clang/test/Preprocessor/wasm-target-features.c
+++ clang/test/Preprocessor/wasm-target-features.c
@@ -7,6 +7,15 @@
 //
 // SIMD128:#define __wasm_simd128__ 1{{$}}
 
+// RUN: %clang -E -dM %s -o - 2>&1 \
+// RUN: -target wasm32-unknown-unknown -mrelaxed-simd \
+// RUN:   | FileCheck %s -check-prefix=RELAXED-SIMD
+// RUN: %clang -E -dM %s -o - 2>&1 \
+// RUN: -target wasm64-unknown-unknown -mrelaxed-simd \
+// RUN:   | FileCheck %s -check-prefix=RELAXED-SIMD
+//
+// RELAXED-SIMD:#define __wasm_relaxed_simd__ 1{{$}}
+
 // RUN: %clang -E -dM %s -o - 2>&1 \
 // RUN: -target wasm32-unknown-unknown -mnontrapping-fptoint \
 // RUN:   | FileCheck %s -check-prefix=NONTRAPPING-FPTOINT
Index: clang/lib/Basic/Targets/WebAssembly.h
===
--- clang/lib/Basic/Targets/WebAssembly.h
+++ clang/lib/Basic/Targets/WebAssembly.h
@@ -27,6 +27,7 @@
   enum SIMDEnum {
 NoSIMD,
 SIMD128,
+RelaxedSIMD,
   } SIMDLevel = NoSIMD;
 
   bool HasNontrappingFPToInt = false;
Index: clang/lib/Basic/Targets/WebAssembly.cpp
===
--- clang/lib/Basic/Targets/WebAssembly.cpp
+++ clang/lib/Basic/Targets/WebAssembly.cpp
@@ -46,6 +46,7 @@
 bool WebAssemblyTargetInfo::hasFeature(StringRef Feature) const {
   return llvm::StringSwitch(Feature)
   .Case("simd128", SIMDLevel >= SIMD128)
+  .Case("relaxed-simd", SIMDLevel >= RelaxedSIMD)
   .Case("nontrapping-fptoint", HasNontrappingFPToInt)
   .Case("sign-ext", HasSignExt)
   .Case("exception-handling", HasExceptionHandling)
@@ -72,6 +73,8 @@
   defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
   if (SIMDLevel >= SIMD128)
 Builder.defineMacro("__wasm_simd128__");
+  if (SIMDLevel >= RelaxedSIMD)
+Builder.defineMacro("__wasm_relaxed_simd__");
   if (HasNontrappingFPToInt)
 Builder.defineMacro("__wasm_nontrapping_fptoint__");
   if (HasSignExt)
@@ -96,6 +99,9 @@
  SIMDEnum Level, bool Enabled) {
   if (Enabled) {
 switch (Level) {
+case RelaxedSIMD:
+  Features["relaxed-simd"] = true;
+  LLVM_FALLTHROUGH;
 case SIMD128:
   Features["simd128"] = true;
   LLVM_FALLTHROUGH;
@@ -109,6 +115,9 @@
   case NoSIMD:
   case SIMD128:
 Features["simd128"] = false;
+LLVM_FALLTHROUGH;
+  case RelaxedSIMD:
+Features["relaxed-simd"] = false;
 break;
   }
 }
@@ -118,6 +127,8 @@
   bool Enabled) const {
   if (Name == "simd128")
 setSIMDLevel(Features, SIMD128, Enabled);
+  else if (Name == "relaxed-simd")
+setSIMDLevel(Features, RelaxedSIMD, Enabled);
   else
 Features[Name] = Enable

[PATCH] D110111: [WebAssembly] Add relaxed-simd feature

2021-09-22 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian added a comment.

In D110111#3013948 , @tlively wrote:

> Nice! Thanks for writing this :D Do you know what happens when you actually 
> try to compile some code with `-mrelaxed-simd`? I'm concerned that it will 
> throw an error because the "relaxed-simd" target feature has not yet been 
> defined in the backend (specifically in WebAssembly.td and in 
> WebAssemblySubtarget.{h,cpp}).

It output "'+relaxed-simd' is not a recognized feature for this target 
(ignoring feature)" but didn't fail compilation. I fixed it by adding to 
WebAssembly.td and WebAssemblySubtarget.h, thanks!

> Edit: Here's the corresponding previous patch that added the target feature 
> in the backend: https://reviews.llvm.org/D56501.




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110111/new/

https://reviews.llvm.org/D110111

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D110295: [WebAssembly] Add prototype relaxed SIMD fma/fms instructions

2021-09-22 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian accepted this revision.
ngzhian added a comment.
This revision is now accepted and ready to land.

The binary opcodes LGTM, not too sure about the tablegen stuff, tests look good 
too.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110295/new/

https://reviews.llvm.org/D110295

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D112186: [WebAssembly] Add prototype relaxed float to int trunc instructions

2021-10-26 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian updated this revision to Diff 382451.
ngzhian added a comment.

No shuffles


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112186/new/

https://reviews.llvm.org/D112186

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -818,4 +818,16 @@
 # CHECK: f64x2.relaxed_max # encoding: [0xfd,0xee,0x01]
 f64x2.relaxed_max
 
+# CHECK: i32x4.relaxed_trunc_f32x4_s # encoding: [0xfd,0xa5,0x01]
+i32x4.relaxed_trunc_f32x4_s
+
+# CHECK: i32x4.relaxed_trunc_f32x4_u # encoding: [0xfd,0xa6,0x01]
+i32x4.relaxed_trunc_f32x4_u
+
+# CHECK: i32x4.relaxed_trunc_f64x2_s_zero # encoding: [0xfd,0xc5,0x01]
+i32x4.relaxed_trunc_f64x2_s_zero
+
+# CHECK: i32x4.relaxed_trunc_f64x2_u_zero # encoding: [0xfd,0xc6,0x01]
+i32x4.relaxed_trunc_f64x2_u_zero
+
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -526,6 +526,48 @@
   ret <4 x i32> %v
 }
 
+; CHECK-LABEL: relaxed_trunc_s_v4i32:
+; NO-CHECK-NOT: f32x4
+; CHECK-NEXT: .functype relaxed_trunc_s_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f32x4_s $push[[R:[0-9]+]]=, $0
+; CHECK-NEXT: return $pop[[R]]
+declare <4 x i32> @llvm.wasm.relaxed.trunc.signed.v4i32.v4f32(<4 x float>)
+define <4 x i32> @relaxed_trunc_s_v4i32(<4 x float> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.signed.v4i32.v4f32(<4 x float> %x)
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: relaxed_trunc_u_v4i32:
+; NO-CHECK-NOT: f32x4
+; CHECK-NEXT: .functype relaxed_trunc_u_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f32x4_u $push[[R:[0-9]+]]=, $0
+; CHECK-NEXT: return $pop[[R]]
+declare <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.v4i32.v4f32(<4 x float>)
+define <4 x i32> @relaxed_trunc_u_v4i32(<4 x float> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.v4i32.v4f32(<4 x float> %x)
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: relaxed_trunc_zero_s_v4i32:
+; CHECK-NEXT: .functype relaxed_trunc_zero_s_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f64x2_s_zero $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.relaxed.trunc.zero.signed.v4i32.v2f64(<2 x double>)
+define <4 x i32> @relaxed_trunc_zero_s_v4i32(<2 x double> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.zero.signed.v4i32.v2f64(<2 x double> %x)
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: relaxed_trunc_zero_u_v4i32:
+; CHECK-NEXT: .functype relaxed_trunc_zero_u_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f64x2_u_zero $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.relaxed.trunc.zero.unsigned.v4i32.v2f64(<2 x double>)
+define <4 x i32> @relaxed_trunc_zero_u_v4i32(<2 x double> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.zero.unsigned.v4i32.v2f64(<2 x double> %x)
+  ret <4 x i32> %a
+}
+
 ; ==
 ; 2 x i64
 ; ==
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1392,3 +1392,20 @@
 
 defm "" : SIMD_RELAXED_FMINMAX;
 defm "" : SIMD_RELAXED_FMINMAX;
+
+//===--===//
+// Relaxed floating-point to int conversions
+//===--===//
+
+multiclass SIMD_RELAXED_CONVERT simdop> {
+  defm op#_#vec :
+RELAXED_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
+  [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec],
+  vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
+}
+
+defm "" : SIMD_RELAXED_CONVERT;
+defm "" : SIMD_RELAXED_CONVERT;
+
+defm "" : SIMD_RELAXED_CONVERT;
+defm "" : SIMD_RELAXED_CONVERT;
Index: llvm/include/llvm/IR/IntrinsicsWebAssembly.td
===
--- llvm/include/llvm/IR/IntrinsicsWebAssembly.td
+++ llvm/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -214,6 +214,27 @@
 [LLVMMatchType<0>, LLVMMatchType<0>],
 [IntrN

[PATCH] D112186: [WebAssembly] Add prototype relaxed float to int trunc instructions

2021-10-26 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:18262-18267
+case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2:
+  IntNo = Intrinsic::wasm_relaxed_trunc_zero_signed;
+  break;
+case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2:
+  IntNo = Intrinsic::wasm_relaxed_trunc_zero_unsigned;
+  break;

tlively wrote:
> ngzhian wrote:
> > @tlively I'm having trouble with this, getting this stack trace
> > 
> > ```
> > WidenVectorResult #0: t4: v2i32 = llvm.wasm.relaxed.trunc.zero.signed 
> > TargetConstant:i32<9112>, t2
> > 
> > Do not know how to widen the result of this operator!
> > UNREACHABLE executed at 
> > /usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:3035!
> > PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash 
> > backtrace.
> > Stack dump:
> > 0.  Program arguments: 
> > /usr/local/google/home/zhin/ssd2/llvm-project/build-wasm/bin/llc 
> > -asm-verbose=false -verify-machineinstrs 
> > -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals 
> > -wasm-keep-registers -mattr=+simd128,+relaxed-simd -debug
> > 1.  Running pass 'Function Pass Manager' on module ''.
> > 2.  Running pass 'WebAssembly Instruction Selection' on function 
> > '@relaxed_trunc_zero_s_v4i32'
> >  #0 0x7f3012db05bb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) 
> > /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Unix/Signals.inc:565:22
> >  #1 0x7f3012db0672 PrintStackTraceSignalHandler(void*) 
> > /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Unix/Signals.inc:632:1
> >  #2 0x7f3012dae668 llvm::sys::RunSignalHandlers() 
> > /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Signals.cpp:97:20
> >  #3 0x7f3012db000e SignalHandler(int) 
> > /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Unix/Signals.inc:407:1
> >  #4 0x7f301276fef0 (/lib/x86_64-linux-gnu/libc.so.6+0x3cef0)
> >  #5 0x7f301276fe71 raise 
> > ./signal/../sysdeps/unix/sysv/linux/raise.c:50:1
> >  #6 0x7f3012759536 abort ./stdlib/abort.c:81:7
> >  #7 0x7f3012c5a974 bindingsErrorHandler(void*, char const*, bool) 
> > /usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/ErrorHandling.cpp:218:55
> >  #8 0x7f3016e7856c 
> > llvm::DAGTypeLegalizer::WidenVectorResult(llvm::SDNode*, unsigned int) 
> > /usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:3037:71
> >  #9 0x7f3016e4a338 llvm::DAGTypeLegalizer::run() 
> > /usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:280:17
> > #10 0x7f3016e4e34f llvm::SelectionDAG::LegalizeTypes() 
> > /usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:1055:37
> > ```
> > 
> > Do I need to add some stuff to LegalizeTypes?
> Sorry for the delay in review! The issue is that the code below generates the 
> intrinsic calls with return type <2 x i32>, which is not a legal type, as 
> well as a shuffle to get back to <4 x i32>. For the existing builtins, we use 
> target-independent LLVM intrinsics, so LLVM already knows how to expand them, 
> but it doesn't know how to expand these new target-specific intrinsics. 
> Rather than piggybacking on the  existing logic here, it would be good to 
> generate intrinsics that return the expected <4 x i32> type (and no shuffle) 
> so there is nothing to expand.
Got it, thanks! Updated in the latest diff, ptal.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112186/new/

https://reviews.llvm.org/D112186

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D112186: [WebAssembly] Add prototype relaxed float to int trunc instructions

2021-10-27 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian updated this revision to Diff 382717.
ngzhian added a comment.

Make intrinsics monomorphic


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112186/new/

https://reviews.llvm.org/D112186

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -818,4 +818,16 @@
 # CHECK: f64x2.relaxed_max # encoding: [0xfd,0xee,0x01]
 f64x2.relaxed_max
 
+# CHECK: i32x4.relaxed_trunc_f32x4_s # encoding: [0xfd,0xa5,0x01]
+i32x4.relaxed_trunc_f32x4_s
+
+# CHECK: i32x4.relaxed_trunc_f32x4_u # encoding: [0xfd,0xa6,0x01]
+i32x4.relaxed_trunc_f32x4_u
+
+# CHECK: i32x4.relaxed_trunc_f64x2_s_zero # encoding: [0xfd,0xc5,0x01]
+i32x4.relaxed_trunc_f64x2_s_zero
+
+# CHECK: i32x4.relaxed_trunc_f64x2_u_zero # encoding: [0xfd,0xc6,0x01]
+i32x4.relaxed_trunc_f64x2_u_zero
+
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -526,6 +526,48 @@
   ret <4 x i32> %v
 }
 
+; CHECK-LABEL: relaxed_trunc_s:
+; NO-CHECK-NOT: f32x4
+; CHECK-NEXT: .functype relaxed_trunc_s (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f32x4_s $push[[R:[0-9]+]]=, $0
+; CHECK-NEXT: return $pop[[R]]
+declare <4 x i32> @llvm.wasm.relaxed.trunc.signed(<4 x float>)
+define <4 x i32> @relaxed_trunc_s(<4 x float> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.signed(<4 x float> %x)
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: relaxed_trunc_u:
+; NO-CHECK-NOT: f32x4
+; CHECK-NEXT: .functype relaxed_trunc_u (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f32x4_u $push[[R:[0-9]+]]=, $0
+; CHECK-NEXT: return $pop[[R]]
+declare <4 x i32> @llvm.wasm.relaxed.trunc.unsigned(<4 x float>)
+define <4 x i32> @relaxed_trunc_u(<4 x float> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.unsigned(<4 x float> %x)
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: relaxed_trunc_zero_s:
+; CHECK-NEXT: .functype relaxed_trunc_zero_s (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f64x2_s_zero $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.relaxed.trunc.zero.signed(<2 x double>)
+define <4 x i32> @relaxed_trunc_zero_s(<2 x double> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.zero.signed(<2 x double> %x)
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: relaxed_trunc_zero_u:
+; CHECK-NEXT: .functype relaxed_trunc_zero_u (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f64x2_u_zero $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.relaxed.trunc.zero.unsigned(<2 x double>)
+define <4 x i32> @relaxed_trunc_zero_u(<2 x double> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.zero.unsigned(<2 x double> %x)
+  ret <4 x i32> %a
+}
+
 ; ==
 ; 2 x i64
 ; ==
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1392,3 +1392,20 @@
 
 defm "" : SIMD_RELAXED_FMINMAX;
 defm "" : SIMD_RELAXED_FMINMAX;
+
+//===--===//
+// Relaxed floating-point to int conversions
+//===--===//
+
+multiclass SIMD_RELAXED_CONVERT simdop> {
+  defm op#_#vec :
+RELAXED_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
+  [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec],
+  vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
+}
+
+defm "" : SIMD_RELAXED_CONVERT;
+defm "" : SIMD_RELAXED_CONVERT;
+
+defm "" : SIMD_RELAXED_CONVERT;
+defm "" : SIMD_RELAXED_CONVERT;
Index: llvm/include/llvm/IR/IntrinsicsWebAssembly.td
===
--- llvm/include/llvm/IR/IntrinsicsWebAssembly.td
+++ llvm/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -214,6 +214,27 @@
 [LLVMMatchType<0>, LLVMMatchType<0>],
 [IntrNoMem, IntrSpeculatable]>;
 
+def int_wasm_relaxed_trunc_signed:
+  Intrinsic<[llvm_v4i32_ty],
+[llvm_v4f32_ty],
+[IntrNoMem, Int

[PATCH] D112186: [WebAssembly] Add prototype relaxed float to int trunc instructions

2021-10-27 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian marked 2 inline comments as done.
ngzhian added a comment.

Good suggestion, done.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112186/new/

https://reviews.llvm.org/D112186

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D111914: [WebAssembly] Add prototype relaxed laneselect instructions

2021-10-15 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian created this revision.
ngzhian added a reviewer: tlively.
Herald added subscribers: ecnelises, sunfish, hiraditya, jgravelle-google, 
sbc100, dschuff.
ngzhian requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, aheejin.
Herald added projects: clang, LLVM.

Add i8x16, i16x8, i32x4, i64x2 laneselect instructions. These are only
exposed as builtins, and require user opt-in.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111914

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -791,4 +791,16 @@
 # CHECK: f64x2.fms # encoding: [0xfd,0xd0,0x01]
 f64x2.fms
 
+# CHECK: i8x16.laneselect # encoding: [0xfd,0xb2,0x01]
+i8x16.laneselect
+
+# CHECK: i16x8.laneselect # encoding: [0xfd,0xb3,0x01]
+i16x8.laneselect
+
+# CHECK: i32x4.laneselect # encoding: [0xfd,0xd2,0x01]
+i32x4.laneselect
+
+# CHECK: i64x2.laneselect # encoding: [0xfd,0xd3,0x01]
+i64x2.laneselect
+
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -180,6 +180,18 @@
   ret <16 x i8> %res
 }
 
+; CHECK-LABEL: laneselect_v16i8:
+; CHECK-NEXT: .functype laneselect_v16i8 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
+define <16 x i8> @laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+  %v = call <16 x i8> @llvm.wasm.laneselect.v16i8(
+<16 x i8> %a, <16 x i8> %b, <16 x i8> %c
+  )
+  ret <16 x i8> %v
+}
+
 ; ==
 ; 8 x i16
 ; ==
@@ -334,6 +346,18 @@
   ret <8 x i16> %a
 }
 
+; CHECK-LABEL: laneselect_v8i16:
+; CHECK-NEXT: .functype laneselect_v8i16 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i16x8.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <8 x i16> @llvm.wasm.laneselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
+define <8 x i16> @laneselect_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
+  %v = call <8 x i16> @llvm.wasm.laneselect.v8i16(
+<8 x i16> %a, <8 x i16> %b, <8 x i16> %c
+  )
+  ret <8 x i16> %v
+}
+
 ; ==
 ; 4 x i32
 ; ==
@@ -480,6 +504,18 @@
   ret <4 x i32> %a
 }
 
+; CHECK-LABEL: laneselect_v4i32:
+; CHECK-NEXT: .functype laneselect_v4i32 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.laneselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+define <4 x i32> @laneselect_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+  %v = call <4 x i32> @llvm.wasm.laneselect.v4i32(
+<4 x i32> %a, <4 x i32> %b, <4 x i32> %c
+  )
+  ret <4 x i32> %v
+}
+
 ; ==
 ; 2 x i64
 ; ==
@@ -525,6 +561,18 @@
   ret <2 x i64> %a
 }
 
+; CHECK-LABEL: laneselect_v2i64:
+; CHECK-NEXT: .functype laneselect_v2i64 (v128, v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <2 x i64> @llvm.wasm.laneselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
+define <2 x i64> @laneselect_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+  %v = call <2 x i64> @llvm.wasm.laneselect.v2i64(
+<2 x i64> %a, <2 x i64> %b, <2 x i64> %c
+  )
+  ret <2 x i64> %v
+}
+
 ; ==
 ; 4 x f32
 ; ==
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1344,3 +1344,20 @@
 
 defm "" : SIMDFM;
 defm "" : SIMDFM;
+
+//===--===//
+// Lanese

[PATCH] D112022: [WebAssembly] Add prototype relaxed swizzle instructions

2021-10-18 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian created this revision.
ngzhian added a reviewer: tlively.
Herald added subscribers: ecnelises, sunfish, hiraditya, jgravelle-google, 
sbc100, dschuff.
ngzhian requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, aheejin.
Herald added projects: clang, LLVM.

Add i8x16 relaxed_swizzle instructions. These are only
exposed as builtins, and require user opt-in.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112022

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyISD.def
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -803,4 +803,7 @@
 # CHECK: i64x2.laneselect # encoding: [0xfd,0xd3,0x01]
 i64x2.laneselect
 
+# CHECK: i8x16.relaxed_swizzle # encoding: [0xfd,0xa2,0x01]
+i8x16.relaxed_swizzle
+
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -192,6 +192,16 @@
   ret <16 x i8> %v
 }
 
+; CHECK-LABEL: relaxed_swizzle_v16i8:
+; CHECK-NEXT: .functype relaxed_swizzle_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.relaxed_swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8>, <16 x i8>)
+define <16 x i8> @relaxed_swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) {
+  %a = call <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8> %x, <16 x i8> %y)
+  ret <16 x i8> %a
+}
+
 ; ==
 ; 8 x i16
 ; ==
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1361,3 +1361,14 @@
 defm "" : SIMDLANESELECT;
 defm "" : SIMDLANESELECT;
 defm "" : SIMDLANESELECT;
+
+def wasm_relaxed_swizzle : SDNode<"WebAssemblyISD::RELAXED_SWIZZLE", wasm_swizzle_t>;
+
+defm RELAXED_SWIZZLE :
+  RELAXED_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins),
+ [(set (v16i8 V128:$dst),
+   (wasm_relaxed_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
+ "i8x16.relaxed_swizzle\t$dst, $src, $mask", "i8x16.relaxed_swizzle", 162>;
+
+def : Pat<(int_wasm_relaxed_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)),
+  (RELAXED_SWIZZLE $src, $mask)>;
Index: llvm/lib/Target/WebAssembly/WebAssemblyISD.def
===
--- llvm/lib/Target/WebAssembly/WebAssemblyISD.def
+++ llvm/lib/Target/WebAssembly/WebAssemblyISD.def
@@ -49,3 +49,6 @@
 HANDLE_MEM_NODETYPE(GLOBAL_GET)
 HANDLE_MEM_NODETYPE(GLOBAL_SET)
 HANDLE_MEM_NODETYPE(TABLE_SET)
+
+// Relaxed SIMD proposal.
+HANDLE_NODETYPE(RELAXED_SWIZZLE)
Index: llvm/include/llvm/IR/IntrinsicsWebAssembly.td
===
--- llvm/include/llvm/IR/IntrinsicsWebAssembly.td
+++ llvm/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -200,6 +200,11 @@
 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 [IntrNoMem, IntrSpeculatable]>;
 
+def int_wasm_relaxed_swizzle :
+  Intrinsic<[llvm_v16i8_ty],
+[llvm_v16i8_ty, llvm_v16i8_ty],
+[IntrNoMem, IntrSpeculatable]>;
+
 //===--===//
 // Thread-local storage intrinsics
 //===--===//
Index: clang/test/CodeGen/builtins-wasm.c
===
--- clang/test/CodeGen/builtins-wasm.c
+++ clang/test/CodeGen/builtins-wasm.c
@@ -732,3 +732,8 @@
   // WEBASSEMBLY-SAME: <2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
   // WEBASSEMBLY-NEXT: ret
 }
+
+i8x16 relaxed_swizzle_i8x16(i8x16 x, i8x16 y) {
+  return __builtin_wasm_relaxed_swizzle_i8x16(x, y);
+  // WEBASSEMBLY: call <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8> %x, <16 x i8> %y)
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -18319,6 +18319,12 @@
 CGM.getIntrinsic(Intrinsic::wasm_laneselect, A->getType());
 return Builder.CreateCall(Callee, {A, B, C});
   }
+  case We

[PATCH] D112022: [WebAssembly] Add prototype relaxed swizzle instructions

2021-10-18 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian added inline comments.



Comment at: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td:1365
+
+def wasm_relaxed_swizzle : SDNode<"WebAssemblyISD::RELAXED_SWIZZLE", 
wasm_swizzle_t>;
+

@tlively i'm not 100% sure if this is needed or the right thing to do, i looked 
at what i8x16.swizzle currently does and just replaced the name and opcode. LMK 
if this needs to be changed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112022/new/

https://reviews.llvm.org/D112022

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D112022: [WebAssembly] Add prototype relaxed swizzle instructions

2021-10-18 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian updated this revision to Diff 380542.
ngzhian added a comment.

Add title for relaxed swizzle instruction


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112022/new/

https://reviews.llvm.org/D112022

Files:
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td


Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1362,6 +1362,11 @@
 defm "" : SIMDLANESELECT;
 defm "" : SIMDLANESELECT;
 
+
+//===--===//
+// Relaxed swizzle
+//===--===//
+
 def wasm_relaxed_swizzle : SDNode<"WebAssemblyISD::RELAXED_SWIZZLE", 
wasm_swizzle_t>;
 
 defm RELAXED_SWIZZLE :


Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1362,6 +1362,11 @@
 defm "" : SIMDLANESELECT;
 defm "" : SIMDLANESELECT;
 
+
+//===--===//
+// Relaxed swizzle
+//===--===//
+
 def wasm_relaxed_swizzle : SDNode<"WebAssemblyISD::RELAXED_SWIZZLE", wasm_swizzle_t>;
 
 defm RELAXED_SWIZZLE :
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D112022: [WebAssembly] Add prototype relaxed swizzle instructions

2021-10-19 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian updated this revision to Diff 380779.
ngzhian added a comment.

Wrong commits


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112022/new/

https://reviews.llvm.org/D112022

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyISD.def
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -803,4 +803,7 @@
 # CHECK: i64x2.laneselect # encoding: [0xfd,0xd3,0x01]
 i64x2.laneselect
 
+# CHECK: i8x16.relaxed_swizzle # encoding: [0xfd,0xa2,0x01]
+i8x16.relaxed_swizzle
+
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -192,6 +192,16 @@
   ret <16 x i8> %v
 }
 
+; CHECK-LABEL: relaxed_swizzle_v16i8:
+; CHECK-NEXT: .functype relaxed_swizzle_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.relaxed_swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8>, <16 x i8>)
+define <16 x i8> @relaxed_swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) {
+  %a = call <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8> %x, <16 x i8> %y)
+  ret <16 x i8> %a
+}
+
 ; ==
 ; 8 x i16
 ; ==
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1361,3 +1361,19 @@
 defm "" : SIMDLANESELECT;
 defm "" : SIMDLANESELECT;
 defm "" : SIMDLANESELECT;
+
+
+//===--===//
+// Relaxed swizzle
+//===--===//
+
+def wasm_relaxed_swizzle : SDNode<"WebAssemblyISD::RELAXED_SWIZZLE", wasm_swizzle_t>;
+
+defm RELAXED_SWIZZLE :
+  RELAXED_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins),
+ [(set (v16i8 V128:$dst),
+   (wasm_relaxed_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
+ "i8x16.relaxed_swizzle\t$dst, $src, $mask", "i8x16.relaxed_swizzle", 162>;
+
+def : Pat<(int_wasm_relaxed_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)),
+  (RELAXED_SWIZZLE $src, $mask)>;
Index: llvm/lib/Target/WebAssembly/WebAssemblyISD.def
===
--- llvm/lib/Target/WebAssembly/WebAssemblyISD.def
+++ llvm/lib/Target/WebAssembly/WebAssemblyISD.def
@@ -49,3 +49,6 @@
 HANDLE_MEM_NODETYPE(GLOBAL_GET)
 HANDLE_MEM_NODETYPE(GLOBAL_SET)
 HANDLE_MEM_NODETYPE(TABLE_SET)
+
+// Relaxed SIMD proposal.
+HANDLE_NODETYPE(RELAXED_SWIZZLE)
Index: llvm/include/llvm/IR/IntrinsicsWebAssembly.td
===
--- llvm/include/llvm/IR/IntrinsicsWebAssembly.td
+++ llvm/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -200,6 +200,11 @@
 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 [IntrNoMem, IntrSpeculatable]>;
 
+def int_wasm_relaxed_swizzle :
+  Intrinsic<[llvm_v16i8_ty],
+[llvm_v16i8_ty, llvm_v16i8_ty],
+[IntrNoMem, IntrSpeculatable]>;
+
 //===--===//
 // Thread-local storage intrinsics
 //===--===//
Index: clang/test/CodeGen/builtins-wasm.c
===
--- clang/test/CodeGen/builtins-wasm.c
+++ clang/test/CodeGen/builtins-wasm.c
@@ -732,3 +732,8 @@
   // WEBASSEMBLY-SAME: <2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
   // WEBASSEMBLY-NEXT: ret
 }
+
+i8x16 relaxed_swizzle_i8x16(i8x16 x, i8x16 y) {
+  return __builtin_wasm_relaxed_swizzle_i8x16(x, y);
+  // WEBASSEMBLY: call <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8> %x, <16 x i8> %y)
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -18319,6 +18319,12 @@
 CGM.getIntrinsic(Intrinsic::wasm_laneselect, A->getType());
 return Builder.CreateCall(Callee, {A, B, C});
   }
+  case WebAssembly::BI__builtin_wasm_relaxed_swizzle_i8x16: {
+Val

[PATCH] D112022: [WebAssembly] Add prototype relaxed swizzle instructions

2021-10-19 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian updated this revision to Diff 380783.
ngzhian added a comment.

- Remove RELAXED_SWIZZLE sdnode


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112022/new/

https://reviews.llvm.org/D112022

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -803,4 +803,7 @@
 # CHECK: i64x2.laneselect # encoding: [0xfd,0xd3,0x01]
 i64x2.laneselect
 
+# CHECK: i8x16.relaxed_swizzle # encoding: [0xfd,0xa2,0x01]
+i8x16.relaxed_swizzle
+
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -192,6 +192,16 @@
   ret <16 x i8> %v
 }
 
+; CHECK-LABEL: relaxed_swizzle_v16i8:
+; CHECK-NEXT: .functype relaxed_swizzle_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.relaxed_swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8>, <16 x i8>)
+define <16 x i8> @relaxed_swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) {
+  %a = call <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8> %x, <16 x i8> %y)
+  ret <16 x i8> %a
+}
+
 ; ==
 ; 8 x i16
 ; ==
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1361,3 +1361,14 @@
 defm "" : SIMDLANESELECT;
 defm "" : SIMDLANESELECT;
 defm "" : SIMDLANESELECT;
+
+
+//===--===//
+// Relaxed swizzle
+//===--===//
+
+defm RELAXED_SWIZZLE :
+  RELAXED_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins),
+ [(set (v16i8 V128:$dst),
+   (int_wasm_relaxed_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
+ "i8x16.relaxed_swizzle\t$dst, $src, $mask", "i8x16.relaxed_swizzle", 162>;
Index: llvm/include/llvm/IR/IntrinsicsWebAssembly.td
===
--- llvm/include/llvm/IR/IntrinsicsWebAssembly.td
+++ llvm/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -200,6 +200,11 @@
 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 [IntrNoMem, IntrSpeculatable]>;
 
+def int_wasm_relaxed_swizzle :
+  Intrinsic<[llvm_v16i8_ty],
+[llvm_v16i8_ty, llvm_v16i8_ty],
+[IntrNoMem, IntrSpeculatable]>;
+
 //===--===//
 // Thread-local storage intrinsics
 //===--===//
Index: clang/test/CodeGen/builtins-wasm.c
===
--- clang/test/CodeGen/builtins-wasm.c
+++ clang/test/CodeGen/builtins-wasm.c
@@ -732,3 +732,8 @@
   // WEBASSEMBLY-SAME: <2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
   // WEBASSEMBLY-NEXT: ret
 }
+
+i8x16 relaxed_swizzle_i8x16(i8x16 x, i8x16 y) {
+  return __builtin_wasm_relaxed_swizzle_i8x16(x, y);
+  // WEBASSEMBLY: call <16 x i8> @llvm.wasm.relaxed.swizzle(<16 x i8> %x, <16 x i8> %y)
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -18319,6 +18319,12 @@
 CGM.getIntrinsic(Intrinsic::wasm_laneselect, A->getType());
 return Builder.CreateCall(Callee, {A, B, C});
   }
+  case WebAssembly::BI__builtin_wasm_relaxed_swizzle_i8x16: {
+Value *Src = EmitScalarExpr(E->getArg(0));
+Value *Indices = EmitScalarExpr(E->getArg(1));
+Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_relaxed_swizzle);
+return Builder.CreateCall(Callee, {Src, Indices});
+  }
   default:
 return nullptr;
   }
Index: clang/include/clang/Basic/BuiltinsWebAssembly.def
===
--- clang/include/clang/Basic/BuiltinsWebAssembly.def
+++ clang/include/clang/Basic/BuiltinsWebAssembly.def
@@ -172,5 +172,7 @@
 TARGET_BUILTIN(__builtin_wasm_laneselect_i32x4, "V4iV4iV4iV4i", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_lane

[PATCH] D112146: [WebAssembly] Add prototype relaxed float min max instructions

2021-10-20 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian created this revision.
ngzhian added a reviewer: tlively.
Herald added subscribers: ecnelises, sunfish, hiraditya, jgravelle-google, 
sbc100, dschuff.
ngzhian requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, aheejin.
Herald added projects: clang, LLVM.

Add relaxed. f32x4.min, f32x4.max, f64x2.min, f64x2.max. These are only
exposed as builtins, and require user opt-in.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112146

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -806,4 +806,16 @@
 # CHECK: i8x16.relaxed_swizzle # encoding: [0xfd,0xa2,0x01]
 i8x16.relaxed_swizzle
 
+# CHECK: f32x4.relaxed_min # encoding: [0xfd,0xb4,0x01]
+f32x4.relaxed_min
+
+# CHECK: f32x4.relaxed_max # encoding: [0xfd,0xe2,0x01]
+f32x4.relaxed_max
+
+# CHECK: f64x2.relaxed_min # encoding: [0xfd,0xd4,0x01]
+f64x2.relaxed_min
+
+# CHECK: f64x2.relaxed_max # encoding: [0xfd,0xee,0x01]
+f64x2.relaxed_max
+
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -682,6 +682,30 @@
   ret <4 x float> %v
 }
 
+; CHECK-LABEL: relaxed_min_v4f32:
+; CHECK-NEXT: .functype relaxed_min_v4f32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.relaxed_min $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <4 x float> @llvm.wasm.relaxed.min.v4f32(<4 x float>, <4 x float>)
+define <4 x float> @relaxed_min_v4f32(<4 x float> %a, <4 x float> %b) {
+  %v = call <4 x float> @llvm.wasm.relaxed.min.v4f32(
+<4 x float> %a, <4 x float> %b
+  )
+  ret <4 x float> %v
+}
+
+; CHECK-LABEL: relaxed_max_v4f32:
+; CHECK-NEXT: .functype relaxed_max_v4f32 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f32x4.relaxed_max $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <4 x float> @llvm.wasm.relaxed.max.v4f32(<4 x float>, <4 x float>)
+define <4 x float> @relaxed_max_v4f32(<4 x float> %a, <4 x float> %b) {
+  %v = call <4 x float> @llvm.wasm.relaxed.max.v4f32(
+<4 x float> %a, <4 x float> %b
+  )
+  ret <4 x float> %v
+}
+
 ; ==
 ; 2 x f64
 ; ==
@@ -780,3 +804,27 @@
   )
   ret <2 x double> %v
 }
+
+; CHECK-LABEL: relaxed_min_v2f64:
+; CHECK-NEXT: .functype relaxed_min_v2f64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.relaxed_min $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.wasm.relaxed.min.v2f64(<2 x double>, <2 x double>)
+define <2 x double> @relaxed_min_v2f64(<2 x double> %a, <2 x double> %b) {
+  %v = call <2 x double> @llvm.wasm.relaxed.min.v2f64(
+<2 x double> %a, <2 x double> %b
+  )
+  ret <2 x double> %v
+}
+
+; CHECK-LABEL: relaxed_max_v2f64:
+; CHECK-NEXT: .functype relaxed_max_v2f64 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: f64x2.relaxed_max $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.wasm.relaxed.max.v2f64(<2 x double>, <2 x double>)
+define <2 x double> @relaxed_max_v2f64(<2 x double> %a, <2 x double> %b) {
+  %v = call <2 x double> @llvm.wasm.relaxed.max.v2f64(
+<2 x double> %a, <2 x double> %b
+  )
+  ret <2 x double> %v
+}
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1372,3 +1372,23 @@
  [(set (v16i8 V128:$dst),
(int_wasm_relaxed_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
  "i8x16.relaxed_swizzle\t$dst, $src, $mask", "i8x16.relaxed_swizzle", 162>;
+
+//===--===//
+// Relaxed floating-point min and max.
+//===--===//
+
+multiclass SIMD_RELAXED_FMINMAX simdopMin, bits<32> simdopMax> {
+  defm RELAXED_FMIN_#vec :
+RELAXED_I<(outs V128:$dst), (ins V128:$a, V128:$b), (outs), (ins),
+  [(set (vec.vt V128:$dst), (int_wasm_relaxed_min
+(vec.vt V128:$a), (vec.vt V128:$b)))],
+  vec.prefix#".relaxed_min\t$dst, $a, $b", vec.prefix#".relaxed_min", simdopMi

[PATCH] D112186: [WebAssembly] Add prototype relaxed float to int trunc instructions

2021-10-20 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian created this revision.
Herald added subscribers: ecnelises, sunfish, hiraditya, jgravelle-google, 
sbc100, dschuff.
ngzhian requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, aheejin.
Herald added projects: clang, LLVM.

Add i32x4.relaxed_trunc_f32x4_s, i32x4.relaxed_trunc_f32x4_u,
i32x4.relaxed_trunc_f64x2_s_zero, i32x4.relaxed_trunc_f64x2_u_zero.

These are only exposed as builtins, and require user opt-in.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D112186

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyISD.def
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -466,6 +466,40 @@
   ret <4 x i32> %a
 }
 
+; CHECK-LABEL: relaxed_trunc_s_v4i32:
+; NO-CHECK-NOT: f32x4
+; CHECK-NEXT: .functype relaxed_trunc_s_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f32x4_s $push[[R:[0-9]+]]=, $0
+; CHECK-NEXT: return $pop[[R]]
+declare <4 x i32> @llvm.wasm.relaxed.trunc.signed.v4i32.v4f32(<4 x float>)
+define <4 x i32> @relaxed_trunc_s_v4i32(<4 x float> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.signed.v4i32.v4f32(<4 x float> %x)
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: relaxed_trunc_u_v4i32:
+; NO-CHECK-NOT: f32x4
+; CHECK-NEXT: .functype relaxed_trunc_u_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_f32x4_u $push[[R:[0-9]+]]=, $0
+; CHECK-NEXT: return $pop[[R]]
+declare <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.v4i32.v4f32(<4 x float>)
+define <4 x i32> @relaxed_trunc_u_v4i32(<4 x float> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.v4i32.v4f32(<4 x float> %x)
+  ret <4 x i32> %a
+}
+
+; CHECK-LABEL: relaxed_trunc_zero_s_v4i32:
+; CHECK-NEXT: .functype relaxed_trunc_zero_s_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.relaxed_trunc_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <2 x i32> @llvm.wasm.relaxed.trunc.zero.signed.v2i32.v2f64(<2 x double>)
+define <4 x i32> @relaxed_trunc_zero_s_v4i32(<2 x double> %x) {
+  %v = call <2 x i32> @llvm.wasm.relaxed.trunc.zero.signed.v2i32.v2f64(<2 x double> %x)
+  %a = shufflevector <2 x i32> %v, <2 x i32> ,
+   <4 x i32> 
+  ret <4 x i32> %a
+}
+
 ; CHECK-LABEL: trunc_sat_zero_s_v4i32:
 ; CHECK-NEXT: .functype trunc_sat_zero_s_v4i32 (v128) -> (v128){{$}}
 ; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}}
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1392,3 +1392,20 @@
 
 defm "" : SIMD_RELAXED_FMINMAX;
 defm "" : SIMD_RELAXED_FMINMAX;
+
+//===--===//
+// Relaxed floating-point to int conversions
+//===--===//
+
+multiclass SIMD_RELAXED_CONVERT simdop> {
+  defm op#_#vec :
+RELAXED_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
+  [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec],
+  vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
+}
+
+defm "" : SIMD_RELAXED_CONVERT;
+defm "" : SIMD_RELAXED_CONVERT;
+
+defm "" : SIMD_RELAXED_CONVERT;
+defm "" : SIMD_RELAXED_CONVERT;
Index: llvm/lib/Target/WebAssembly/WebAssemblyISD.def
===
--- llvm/lib/Target/WebAssembly/WebAssemblyISD.def
+++ llvm/lib/Target/WebAssembly/WebAssemblyISD.def
@@ -50,3 +50,7 @@
 HANDLE_MEM_NODETYPE(GLOBAL_SET)
 HANDLE_MEM_NODETYPE(TABLE_GET)
 HANDLE_MEM_NODETYPE(TABLE_SET)
+
+// Relaxed SIMD proposal.
+HANDLE_NODETYPE(RELAXED_TRUNC_ZERO_S)
+HANDLE_NODETYPE(RELAXED_TRUNC_ZERO_U)
Index: llvm/include/llvm/IR/IntrinsicsWebAssembly.td
===
--- llvm/include/llvm/IR/IntrinsicsWebAssembly.td
+++ llvm/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -214,6 +214,27 @@
 [LLVMMatchType<0>, LLVMMatchType<0>],
 [IntrNoMem, IntrSpeculatable]>;
 
+def int_wasm_relaxed_trunc_signed:
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
+
+def int_wasm_relaxed_trunc_unsigned:
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
+
+def int_wasm_relaxed_trunc_zero_signed:
+  Intrinsic<[llvm_anyvector_ty],
+[llvm_anyvector_ty

[PATCH] D112186: [WebAssembly] Add prototype relaxed float to int trunc instructions

2021-10-20 Thread Ng Zhi An via Phabricator via cfe-commits 
ngzhian added a subscriber: tlively.
ngzhian added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:18262-18267
+case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2:
+  IntNo = Intrinsic::wasm_relaxed_trunc_zero_signed;
+  break;
+case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2:
+  IntNo = Intrinsic::wasm_relaxed_trunc_zero_unsigned;
+  break;

@tlively I'm having trouble with this, getting this stack trace

```
WidenVectorResult #0: t4: v2i32 = llvm.wasm.relaxed.trunc.zero.signed 
TargetConstant:i32<9112>, t2

Do not know how to widen the result of this operator!
UNREACHABLE executed at 
/usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:3035!
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash 
backtrace.
Stack dump:
0.  Program arguments: 
/usr/local/google/home/zhin/ssd2/llvm-project/build-wasm/bin/llc 
-asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt 
-wasm-disable-explicit-locals -wasm-keep-registers 
-mattr=+simd128,+relaxed-simd -debug
1.  Running pass 'Function Pass Manager' on module ''.
2.  Running pass 'WebAssembly Instruction Selection' on function 
'@relaxed_trunc_zero_s_v4i32'
 #0 0x7f3012db05bb llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) 
/usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Unix/Signals.inc:565:22
 #1 0x7f3012db0672 PrintStackTraceSignalHandler(void*) 
/usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Unix/Signals.inc:632:1
 #2 0x7f3012dae668 llvm::sys::RunSignalHandlers() 
/usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Signals.cpp:97:20
 #3 0x7f3012db000e SignalHandler(int) 
/usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/Unix/Signals.inc:407:1
 #4 0x7f301276fef0 (/lib/x86_64-linux-gnu/libc.so.6+0x3cef0)
 #5 0x7f301276fe71 raise ./signal/../sysdeps/unix/sysv/linux/raise.c:50:1
 #6 0x7f3012759536 abort ./stdlib/abort.c:81:7
 #7 0x7f3012c5a974 bindingsErrorHandler(void*, char const*, bool) 
/usr/local/google/home/zhin/src/llvm-project/llvm/lib/Support/ErrorHandling.cpp:218:55
 #8 0x7f3016e7856c llvm::DAGTypeLegalizer::WidenVectorResult(llvm::SDNode*, 
unsigned int) 
/usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:3037:71
 #9 0x7f3016e4a338 llvm::DAGTypeLegalizer::run() 
/usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:280:17
#10 0x7f3016e4e34f llvm::SelectionDAG::LegalizeTypes() 
/usr/local/google/home/zhin/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp:1055:37
```

Do I need to add some stuff to LegalizeTypes?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112186/new/

https://reviews.llvm.org/D112186

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits