r337449 - [PowerPC] Handle __builtin_xxpermdi the same way as GCC does
Author: nemanjai
Date: Thu Jul 19 05:44:15 2018
New Revision: 337449
URL: http://llvm.org/viewvc/llvm-project?rev=337449&view=rev
Log:
[PowerPC] Handle __builtin_xxpermdi the same way as GCC does
The codegen for this builtin was initially implemented to match GCC.
However, due to interest from users GCC changed behaviour to account for the
big endian bias of the instruction and correct it. This patch brings the
handling inline with GCC.
Fixes https://bugs.llvm.org/show_bug.cgi?id=38192
Differential Revision: https://reviews.llvm.org/D49424
Modified:
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/test/CodeGen/builtins-ppc-vsx.c
Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=337449&r1=337448&r2=337449&view=diff
==
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Thu Jul 19 05:44:15 2018
@@ -10831,19 +10831,11 @@ Value *CodeGenFunction::EmitPPCBuiltinEx
Ops[0] = Builder.CreateBitCast(Ops[0], llvm::VectorType::get(Int64Ty, 2));
Ops[1] = Builder.CreateBitCast(Ops[1], llvm::VectorType::get(Int64Ty, 2));
-// Element zero comes from the first input vector and element one comes
from
-// the second. The element indices within each vector are numbered in big
-// endian order so the shuffle mask must be adjusted for this on little
-// endian platforms (i.e. index is complemented and source vector
reversed).
-unsigned ElemIdx0;
-unsigned ElemIdx1;
-if (getTarget().isLittleEndian()) {
- ElemIdx0 = (~Index & 1) + 2;
- ElemIdx1 = (~Index & 2) >> 1;
-} else { // BigEndian
- ElemIdx0 = (Index & 2) >> 1;
- ElemIdx1 = 2 + (Index & 1);
-}
+// Account for endianness by treating this as just a shuffle. So we use the
+// same indices for both LE and BE in order to produce expected results in
+// both cases.
+unsigned ElemIdx0 = (Index & 2) >> 1;;
+unsigned ElemIdx1 = 2 + (Index & 1);;
Constant *ShuffleElts[2] = {ConstantInt::get(Int32Ty, ElemIdx0),
ConstantInt::get(Int32Ty, ElemIdx1)};
Modified: cfe/trunk/test/CodeGen/builtins-ppc-vsx.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-vsx.c?rev=337449&r1=337448&r2=337449&view=diff
==
--- cfe/trunk/test/CodeGen/builtins-ppc-vsx.c (original)
+++ cfe/trunk/test/CodeGen/builtins-ppc-vsx.c Thu Jul 19 05:44:15 2018
@@ -1694,43 +1694,43 @@ vec_xst_be(vd, sll, ad);
res_vd = vec_xxpermdi(vd, vd, 0);
// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
-// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
+// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
res_vf = vec_xxpermdi(vf, vf, 1);
// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
-// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
+// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
res_vsll = vec_xxpermdi(vsll, vsll, 2);
// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
-// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
+// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
res_vull = vec_xxpermdi(vull, vull, 3);
// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
-// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
+// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
res_vsi = vec_xxpermdi(vsi, vsi, 0);
// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
-// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
+// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
res_vui = vec_xxpermdi(vui, vui, 1);
// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
-// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
+// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
res_vss = vec_xxpermdi(vss, vss, 2);
// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
-// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
+// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
res_vus = vec_xxpermdi(vus, vus, 3);
// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
-// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x
i32>
+// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2
r337451 - NFC: Remove extraneous semicolons as pointed out in the differential review
Author: nemanjai
Date: Thu Jul 19 05:49:27 2018
New Revision: 337451
URL: http://llvm.org/viewvc/llvm-project?rev=337451&view=rev
Log:
NFC: Remove extraneous semicolons as pointed out in the differential review
The commit for
https://reviews.llvm.org/D49424
missed the comment about the extraneous semicolons. Remove them.
Modified:
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=337451&r1=337450&r2=337451&view=diff
==
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Thu Jul 19 05:49:27 2018
@@ -10834,8 +10834,8 @@ Value *CodeGenFunction::EmitPPCBuiltinEx
// Account for endianness by treating this as just a shuffle. So we use the
// same indices for both LE and BE in order to produce expected results in
// both cases.
-unsigned ElemIdx0 = (Index & 2) >> 1;;
-unsigned ElemIdx1 = 2 + (Index & 1);;
+unsigned ElemIdx0 = (Index & 2) >> 1;
+unsigned ElemIdx1 = 2 + (Index & 1);
Constant *ShuffleElts[2] = {ConstantInt::get(Int32Ty, ElemIdx0),
ConstantInt::get(Int32Ty, ElemIdx1)};
___
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r347556 - [PowerPC] Vector load/store builtins overstate alignment of pointers
Author: nemanjai
Date: Mon Nov 26 06:35:38 2018
New Revision: 347556
URL: http://llvm.org/viewvc/llvm-project?rev=347556&view=rev
Log:
[PowerPC] Vector load/store builtins overstate alignment of pointers
A number of builtins in altivec.h load/store vectors from pointers to scalar
types. Currently they just cast the pointer to a vector pointer, but expressions
like that have the alignment of the target type. Of course, the input pointer
did not have that alignment so this triggers UBSan (and rightly so).
This resolves https://bugs.llvm.org/show_bug.cgi?id=39704
Differential revision: https://reviews.llvm.org/D54787
Modified:
cfe/trunk/lib/Headers/altivec.h
cfe/trunk/test/CodeGen/builtins-ppc-altivec.c
cfe/trunk/test/CodeGen/builtins-ppc-quadword.c
cfe/trunk/test/CodeGen/builtins-ppc-vsx.c
Modified: cfe/trunk/lib/Headers/altivec.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/altivec.h?rev=347556&r1=347555&r2=347556&view=diff
==
--- cfe/trunk/lib/Headers/altivec.h (original)
+++ cfe/trunk/lib/Headers/altivec.h Mon Nov 26 06:35:38 2018
@@ -16355,67 +16355,82 @@ vec_revb(vector unsigned __int128 __a) {
/* vec_xl */
+typedef vector signed char unaligned_vec_schar __attribute__((aligned(1)));
+typedef vector unsigned char unaligned_vec_uchar __attribute__((aligned(1)));
+typedef vector signed short unaligned_vec_sshort __attribute__((aligned(1)));
+typedef vector unsigned short unaligned_vec_ushort __attribute__((aligned(1)));
+typedef vector signed int unaligned_vec_sint __attribute__((aligned(1)));
+typedef vector unsigned int unaligned_vec_uint __attribute__((aligned(1)));
+typedef vector float unaligned_vec_float __attribute__((aligned(1)));
+
static inline __ATTRS_o_ai vector signed char vec_xl(signed long long __offset,
signed char *__ptr) {
- return *(vector signed char *)(__ptr + __offset);
+ return *(unaligned_vec_schar *)(__ptr + __offset);
}
static inline __ATTRS_o_ai vector unsigned char
vec_xl(signed long long __offset, unsigned char *__ptr) {
- return *(vector unsigned char *)(__ptr + __offset);
+ return *(unaligned_vec_uchar*)(__ptr + __offset);
}
static inline __ATTRS_o_ai vector signed short vec_xl(signed long long
__offset,
signed short *__ptr) {
- return *(vector signed short *)(__ptr + __offset);
+ return *(unaligned_vec_sshort *)(__ptr + __offset);
}
static inline __ATTRS_o_ai vector unsigned short
vec_xl(signed long long __offset, unsigned short *__ptr) {
- return *(vector unsigned short *)(__ptr + __offset);
+ return *(unaligned_vec_ushort *)(__ptr + __offset);
}
static inline __ATTRS_o_ai vector signed int vec_xl(signed long long __offset,
signed int *__ptr) {
- return *(vector signed int *)(__ptr + __offset);
+ return *(unaligned_vec_sint *)(__ptr + __offset);
}
static inline __ATTRS_o_ai vector unsigned int vec_xl(signed long long
__offset,
unsigned int *__ptr) {
- return *(vector unsigned int *)(__ptr + __offset);
+ return *(unaligned_vec_uint *)(__ptr + __offset);
}
static inline __ATTRS_o_ai vector float vec_xl(signed long long __offset,
float *__ptr) {
- return *(vector float *)(__ptr + __offset);
+ return *(unaligned_vec_float *)(__ptr + __offset);
}
#ifdef __VSX__
+typedef vector signed long long unaligned_vec_sll __attribute__((aligned(1)));
+typedef vector unsigned long long unaligned_vec_ull
__attribute__((aligned(1)));
+typedef vector double unaligned_vec_double __attribute__((aligned(1)));
+
static inline __ATTRS_o_ai vector signed long long
vec_xl(signed long long __offset, signed long long *__ptr) {
- return *(vector signed long long *)(__ptr + __offset);
+ return *(unaligned_vec_sll *)(__ptr + __offset);
}
static inline __ATTRS_o_ai vector unsigned long long
vec_xl(signed long long __offset, unsigned long long *__ptr) {
- return *(vector unsigned long long *)(__ptr + __offset);
+ return *(unaligned_vec_ull *)(__ptr + __offset);
}
static inline __ATTRS_o_ai vector double vec_xl(signed long long __offset,
double *__ptr) {
- return *(vector double *)(__ptr + __offset);
+ return *(unaligned_vec_double *)(__ptr + __offset);
}
#endif
#if defined(__POWER8_VECTOR__) && defined(__powerpc64__)
+typedef vector signed __int128 unaligned_vec_si128 __attribute__((aligned(1)));
+typedef vector unsigned __int128 unaligned_vec_ui128
+__attribute__((aligned(1)));
static inline __ATTRS_o_ai vector signed __int128
vec_xl(signed long long __offset, signed __int128 *__ptr) {
- return *(vector signed __int128 *)(__ptr + __offset);
+ return *(unaligned_vec_si128 *)(__ptr + __offset);
}
sta
r356111 - Fix invocation of Gold plugin with LTO after r355331
Author: nemanjai
Date: Wed Mar 13 16:54:52 2019
New Revision: 356111
URL: http://llvm.org/viewvc/llvm-project?rev=356111&view=rev
Log:
Fix invocation of Gold plugin with LTO after r355331
The above commit breaks the usage of PGO and LTO when -fprofile-use is
supplied without a path. This patch changes the usage of this argument
to be inline with its use in addPGOAndCoverageFlags().
Differential revision: https://reviews.llvm.org/D59304
Added:
cfe/trunk/test/Driver/cspgo-lto.c
Modified:
cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp
Modified: cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp?rev=356111&r1=356110&r2=356111&view=diff
==
--- cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp Wed Mar 13 16:54:52 2019
@@ -464,8 +464,12 @@ void tools::AddGoldPlugin(const ToolChai
CmdArgs.push_back(
Args.MakeArgString("-plugin-opt=cs-profile-path=default_%m.profraw"));
} else if (ProfileUseArg) {
+SmallString<128> Path(
+ProfileUseArg->getNumValues() == 0 ? "" : ProfileUseArg->getValue());
+if (Path.empty() || llvm::sys::fs::is_directory(Path))
+ llvm::sys::path::append(Path, "default.profdata");
CmdArgs.push_back(Args.MakeArgString(Twine("-plugin-opt=cs-profile-path=")
+
- ProfileUseArg->getValue()));
+ Path));
}
// Need this flag to turn on new pass manager via Gold plugin.
Added: cfe/trunk/test/Driver/cspgo-lto.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/cspgo-lto.c?rev=356111&view=auto
==
--- cfe/trunk/test/Driver/cspgo-lto.c (added)
+++ cfe/trunk/test/Driver/cspgo-lto.c Wed Mar 13 16:54:52 2019
@@ -0,0 +1,6 @@
+// RUN: touch %t.o
+//
+// RUN: %clang -target x86_64-unknown-linux -### %t.o -flto=thin \
+// RUN: -fprofile-use 2>&1 | FileCheck %s
+
+// CHECK: -plugin-opt=cs-profile-path=default.profdata
___
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r360220 - Fix buildbot break after r360195
Author: nemanjai Date: Tue May 7 19:03:32 2019 New Revision: 360220 URL: http://llvm.org/viewvc/llvm-project?rev=360220&view=rev Log: Fix buildbot break after r360195 Modified: cfe/trunk/test/Modules/preprocess-umbrella.cpp Modified: cfe/trunk/test/Modules/preprocess-umbrella.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Modules/preprocess-umbrella.cpp?rev=360220&r1=360219&r2=360220&view=diff == --- cfe/trunk/test/Modules/preprocess-umbrella.cpp (original) +++ cfe/trunk/test/Modules/preprocess-umbrella.cpp Tue May 7 19:03:32 2019 @@ -1,7 +1,9 @@ // FIXME: The standalone module still seems to cause clang to want to test for // the existence of a 'foo' directory: +// RUN: rm -rf %t // RUN: mkdir %t // RUN: cp %s %t +// RUN: rm -rf %t/foo // RUN: mkdir %t/foo // RUN: cd %t // RUN: not %clang_cc1 -fmodules -fsyntax-only %s 2>&1 | FileCheck %s ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r353163 - [NFC] Explicitly add -std=c++14 option to tests that rely on the C++14 default
Author: nemanjai
Date: Tue Feb 5 04:05:53 2019
New Revision: 353163
URL: http://llvm.org/viewvc/llvm-project?rev=353163&view=rev
Log:
[NFC] Explicitly add -std=c++14 option to tests that rely on the C++14 default
When Clang/LLVM is built with the CLANG_DEFAULT_STD_CXX CMake macro that sets
the default standard to something other than C++14, there are a number of lit
tests that fail as they rely on the C++14 default.
This patch just adds the language standard option explicitly to such test cases.
Differential revision: https://reviews.llvm.org/D57581
Modified:
cfe/trunk/test/CodeCompletion/crash-skipped-bodies-template-inst.cpp
cfe/trunk/test/CodeCompletion/skip-auto-funcs.cpp
cfe/trunk/test/CodeGenCXX/auto-var-init.cpp
cfe/trunk/test/CodeGenCXX/dllexport-no-dllexport-inlines.cpp
cfe/trunk/test/CodeGenCXX/new-overflow.cpp
cfe/trunk/test/CodeGenCXX/new.cpp
cfe/trunk/test/Lexer/cxx-features.cpp
cfe/trunk/test/Lexer/half-literal.cpp
cfe/trunk/test/Modules/friend-definition-2.cpp
cfe/trunk/test/Modules/merge-lambdas.cpp
cfe/trunk/test/SemaCXX/int-ptr-cast-SFINAE.cpp
cfe/trunk/test/SemaTemplate/argument-dependent-lookup.cpp
cfe/trunk/test/SemaTemplate/class-template-decl.cpp
cfe/trunk/test/SemaTemplate/typo-dependent-name.cpp
Modified: cfe/trunk/test/CodeCompletion/crash-skipped-bodies-template-inst.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeCompletion/crash-skipped-bodies-template-inst.cpp?rev=353163&r1=353162&r2=353163&view=diff
==
--- cfe/trunk/test/CodeCompletion/crash-skipped-bodies-template-inst.cpp
(original)
+++ cfe/trunk/test/CodeCompletion/crash-skipped-bodies-template-inst.cpp Tue
Feb 5 04:05:53 2019
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -fsyntax-only -code-completion-at=%s:24:5 %s -o - 2>&1 |
FileCheck %s
+// RUN: %clang_cc1 -fsyntax-only -std=c++14 -code-completion-at=%s:24:5 %s -o
- 2>&1 | FileCheck %s
template
auto make_func() {
struct impl {
Modified: cfe/trunk/test/CodeCompletion/skip-auto-funcs.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeCompletion/skip-auto-funcs.cpp?rev=353163&r1=353162&r2=353163&view=diff
==
--- cfe/trunk/test/CodeCompletion/skip-auto-funcs.cpp (original)
+++ cfe/trunk/test/CodeCompletion/skip-auto-funcs.cpp Tue Feb 5 04:05:53 2019
@@ -1,7 +1,7 @@
// We run clang in completion mode to force skipping of function bodies and
// check if the function bodies were skipped by observing the warnings that
// clang produces.
-// RUN: not %clang_cc1 -fsyntax-only -code-completion-at=%s:60:1 %s -o - 2>&1
| FileCheck %s
+// RUN: not %clang_cc1 -std=c++14 -fsyntax-only -code-completion-at=%s:60:1 %s
-o - 2>&1 | FileCheck %s
template
auto not_skipped() {
int x;
Modified: cfe/trunk/test/CodeGenCXX/auto-var-init.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenCXX/auto-var-init.cpp?rev=353163&r1=353162&r2=353163&view=diff
==
--- cfe/trunk/test/CodeGenCXX/auto-var-init.cpp (original)
+++ cfe/trunk/test/CodeGenCXX/auto-var-init.cpp Tue Feb 5 04:05:53 2019
@@ -1,6 +1,6 @@
-// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fblocks %s -emit-llvm -o -
| FileCheck %s
-// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fblocks
-ftrivial-auto-var-init=pattern %s -emit-llvm -o - | FileCheck %s
-check-prefix=PATTERN
-// RUN: %clang_cc1 -triple x86_64-unknown-unknown -fblocks
-ftrivial-auto-var-init=zero %s -emit-llvm -o - | FileCheck %s
-check-prefix=ZERO
+// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown -fblocks %s
-emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown -fblocks
-ftrivial-auto-var-init=pattern %s -emit-llvm -o - | FileCheck %s
-check-prefix=PATTERN
+// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown -fblocks
-ftrivial-auto-var-init=zero %s -emit-llvm -o - | FileCheck %s
-check-prefix=ZERO
template void used(T &) noexcept;
Modified: cfe/trunk/test/CodeGenCXX/dllexport-no-dllexport-inlines.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenCXX/dllexport-no-dllexport-inlines.cpp?rev=353163&r1=353162&r2=353163&view=diff
==
--- cfe/trunk/test/CodeGenCXX/dllexport-no-dllexport-inlines.cpp (original)
+++ cfe/trunk/test/CodeGenCXX/dllexport-no-dllexport-inlines.cpp Tue Feb 5
04:05:53 2019
@@ -1,10 +1,10 @@
// RUN: %clang_cc1 %s -fms-extensions -triple x86_64-windows-msvc \
-// RUN: -disable-llvm-passes\
+// RUN: -disable-llvm-passes -std=c++14 \
// RUN: -fno-dllexport-inlines -emit-llvm -O1 -o - |\
// RUN: FileCheck --check-prefix=CHECK --check-pref
r354512 - Make predefined FLT16 macros conditional on support for the type
Author: nemanjai
Date: Wed Feb 20 12:27:33 2019
New Revision: 354512
URL: http://llvm.org/viewvc/llvm-project?rev=354512&view=rev
Log:
Make predefined FLT16 macros conditional on support for the type
We unconditionally predefine these macros. However, they may be used to
determine if the type is supported. In that case, there are unnecessary
failures to compile the code.
This is the proposed fix for https://bugs.llvm.org/show_bug.cgi?id=40559
Differential revision: https://reviews.llvm.org/D57577
Modified:
cfe/trunk/lib/Frontend/InitPreprocessor.cpp
cfe/trunk/test/Headers/float16.c
cfe/trunk/test/Preprocessor/init.c
Modified: cfe/trunk/lib/Frontend/InitPreprocessor.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Frontend/InitPreprocessor.cpp?rev=354512&r1=354511&r2=354512&view=diff
==
--- cfe/trunk/lib/Frontend/InitPreprocessor.cpp (original)
+++ cfe/trunk/lib/Frontend/InitPreprocessor.cpp Wed Feb 20 12:27:33 2019
@@ -830,7 +830,8 @@ static void InitializePredefinedMacros(c
DefineFmt("__UINTPTR", TI.getUIntPtrType(), TI, Builder);
DefineTypeWidth("__UINTPTR_WIDTH__", TI.getUIntPtrType(), TI, Builder);
- DefineFloatMacros(Builder, "FLT16", &TI.getHalfFormat(), "F16");
+ if (TI.hasFloat16Type())
+DefineFloatMacros(Builder, "FLT16", &TI.getHalfFormat(), "F16");
DefineFloatMacros(Builder, "FLT", &TI.getFloatFormat(), "F");
DefineFloatMacros(Builder, "DBL", &TI.getDoubleFormat(), "");
DefineFloatMacros(Builder, "LDBL", &TI.getLongDoubleFormat(), "L");
Modified: cfe/trunk/test/Headers/float16.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Headers/float16.c?rev=354512&r1=354511&r2=354512&view=diff
==
--- cfe/trunk/test/Headers/float16.c (original)
+++ cfe/trunk/test/Headers/float16.c Wed Feb 20 12:27:33 2019
@@ -1,7 +1,11 @@
-// RUN: %clang_cc1 -fsyntax-only -verify -std=c89 -ffreestanding %s
-// RUN: %clang_cc1 -fsyntax-only -verify -std=c99 -ffreestanding %s
-// RUN: %clang_cc1 -fsyntax-only -verify -std=c11 -ffreestanding %s
-// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 -x c++ -ffreestanding %s
+// RUN: %clang_cc1 -triple=aarch64-none-none -fsyntax-only -verify -std=c89 \
+// RUN: -ffreestanding %s
+// RUN: %clang_cc1 -triple=aarch64-none-none -fsyntax-only -verify \
+// RUN: -std=c99 -ffreestanding %s
+// RUN: %clang_cc1 -triple=aarch64-none-none -fsyntax-only -verify -std=c11 \
+// RUN: -ffreestanding %s
+// RUN: %clang_cc1 -triple=aarch64-none-none -fsyntax-only -verify \
+// RUN: -std=c++11 -x c++ -ffreestanding %s
// expected-no-diagnostics
#define __STDC_WANT_IEC_60559_TYPES_EXT__
Modified: cfe/trunk/test/Preprocessor/init.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/init.c?rev=354512&r1=354511&r2=354512&view=diff
==
--- cfe/trunk/test/Preprocessor/init.c (original)
+++ cfe/trunk/test/Preprocessor/init.c Wed Feb 20 12:27:33 2019
@@ -9166,20 +9166,20 @@
// WEBASSEMBLY-NOT:#define __ELF__
// WEBASSEMBLY-NEXT:#define __FINITE_MATH_ONLY__ 0
// WEBASSEMBLY-NEXT:#define __FLOAT128__ 1
-// WEBASSEMBLY-NEXT:#define __FLT16_DECIMAL_DIG__ 5
-// WEBASSEMBLY-NEXT:#define __FLT16_DENORM_MIN__ 5.9604644775390625e-8F16
-// WEBASSEMBLY-NEXT:#define __FLT16_DIG__ 3
-// WEBASSEMBLY-NEXT:#define __FLT16_EPSILON__ 9.765625e-4F16
-// WEBASSEMBLY-NEXT:#define __FLT16_HAS_DENORM__ 1
-// WEBASSEMBLY-NEXT:#define __FLT16_HAS_INFINITY__ 1
-// WEBASSEMBLY-NEXT:#define __FLT16_HAS_QUIET_NAN__ 1
-// WEBASSEMBLY-NEXT:#define __FLT16_MANT_DIG__ 11
-// WEBASSEMBLY-NEXT:#define __FLT16_MAX_10_EXP__ 4
-// WEBASSEMBLY-NEXT:#define __FLT16_MAX_EXP__ 15
-// WEBASSEMBLY-NEXT:#define __FLT16_MAX__ 6.5504e+4F16
-// WEBASSEMBLY-NEXT:#define __FLT16_MIN_10_EXP__ (-13)
-// WEBASSEMBLY-NEXT:#define __FLT16_MIN_EXP__ (-14)
-// WEBASSEMBLY-NEXT:#define __FLT16_MIN__ 6.103515625e-5F16
+// WEBASSEMBLY-NOT:#define __FLT16_DECIMAL_DIG__
+// WEBASSEMBLY-NOT:#define __FLT16_DENORM_MIN__
+// WEBASSEMBLY-NOT:#define __FLT16_DIG__
+// WEBASSEMBLY-NOT:#define __FLT16_EPSILON__
+// WEBASSEMBLY-NOT:#define __FLT16_HAS_DENORM__
+// WEBASSEMBLY-NOT:#define __FLT16_HAS_INFINITY__
+// WEBASSEMBLY-NOT:#define __FLT16_HAS_QUIET_NAN__
+// WEBASSEMBLY-NOT:#define __FLT16_MANT_DIG__
+// WEBASSEMBLY-NOT:#define __FLT16_MAX_10_EXP__
+// WEBASSEMBLY-NOT:#define __FLT16_MAX_EXP__
+// WEBASSEMBLY-NOT:#define __FLT16_MAX__
+// WEBASSEMBLY-NOT:#define __FLT16_MIN_10_EXP__
+// WEBASSEMBLY-NOT:#define __FLT16_MIN_EXP__
+// WEBASSEMBLY-NOT:#define __FLT16_MIN__
// WEBASSEMBLY-NEXT:#define __FLT_DECIMAL_DIG__ 9
// WEBASSEMBLY-NEXT:#define __FLT_DENORM_MIN__ 1.40129846e-45F
// WEBASSEMBLY-NEXT:#define __FLT_DIG__ 6
___
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r362571 - Initial support for vectorization using MASSV (IBM MASS vector library)
Author: nemanjai
Date: Tue Jun 4 18:57:57 2019
New Revision: 362571
URL: http://llvm.org/viewvc/llvm-project?rev=362571&view=rev
Log:
Initial support for vectorization using MASSV (IBM MASS vector library)
Part 2 (the Clang portion) of D59881.
This patch (first of two patches) enables the vectorizer to recognize the
IBM MASS vector library routines. This patch specifically adds support for
recognizing the -vector-library=MASSV option, and defines mappings from IEEE
standard scalar math functions to generic PowerPC MASS vector counterparts.
For instance, the generic PowerPC MASS vector entry for double-precision
cbrt function is __cbrtd2_massv.
The second patch will further lower the generic PowerPC vector entries to
PowerPC subtarget-specific entries.
For instance, the PowerPC generic entry cbrtd2_massv is lowered to
cbrtd2_P9 for Power9 subtarget.
The overall support for MASS vector library is presented as such in two patches
for ease of review.
Patch by Jeeva Paudel.
Differential revision: https://reviews.llvm.org/D59881
Modified:
cfe/trunk/include/clang/Basic/CodeGenOptions.h
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/CodeGen/BackendUtil.cpp
cfe/trunk/lib/Frontend/CompilerInvocation.cpp
cfe/trunk/test/Driver/autocomplete.c
cfe/trunk/test/Driver/fveclib.c
Modified: cfe/trunk/include/clang/Basic/CodeGenOptions.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/CodeGenOptions.h?rev=362571&r1=362570&r2=362571&view=diff
==
--- cfe/trunk/include/clang/Basic/CodeGenOptions.h (original)
+++ cfe/trunk/include/clang/Basic/CodeGenOptions.h Tue Jun 4 18:57:57 2019
@@ -53,6 +53,7 @@ public:
enum VectorLibrary {
NoLibrary, // Don't use any vector library.
Accelerate, // Use the Accelerate framework.
+MASSV, // IBM MASS vector library.
SVML// Intel short vector math library.
};
Modified: cfe/trunk/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=362571&r1=362570&r2=362571&view=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Tue Jun 4 18:57:57 2019
@@ -1418,7 +1418,7 @@ def fno_experimental_new_pass_manager :
Group, Flags<[CC1Option]>,
HelpText<"Disables an experimental new pass manager in LLVM.">;
def fveclib : Joined<["-"], "fveclib=">, Group, Flags<[CC1Option]>,
-HelpText<"Use the given vector functions library">,
Values<"Accelerate,SVML,none">;
+HelpText<"Use the given vector functions library">,
Values<"Accelerate,MASSV,SVML,none">;
def fno_lax_vector_conversions : Flag<["-"], "fno-lax-vector-conversions">,
Group,
HelpText<"Disallow implicit conversions between vectors with a different
number of elements or different element types">, Flags<[CC1Option]>;
def fno_merge_all_constants : Flag<["-"], "fno-merge-all-constants">,
Group,
Modified: cfe/trunk/lib/CodeGen/BackendUtil.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/BackendUtil.cpp?rev=362571&r1=362570&r2=362571&view=diff
==
--- cfe/trunk/lib/CodeGen/BackendUtil.cpp (original)
+++ cfe/trunk/lib/CodeGen/BackendUtil.cpp Tue Jun 4 18:57:57 2019
@@ -340,6 +340,9 @@ static TargetLibraryInfoImpl *createTLII
case CodeGenOptions::Accelerate:
TLII->addVectorizableFunctionsFromVecLib(TargetLibraryInfoImpl::Accelerate);
break;
+ case CodeGenOptions::MASSV:
+TLII->addVectorizableFunctionsFromVecLib(TargetLibraryInfoImpl::MASSV);
+break;
case CodeGenOptions::SVML:
TLII->addVectorizableFunctionsFromVecLib(TargetLibraryInfoImpl::SVML);
break;
Modified: cfe/trunk/lib/Frontend/CompilerInvocation.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Frontend/CompilerInvocation.cpp?rev=362571&r1=362570&r2=362571&view=diff
==
--- cfe/trunk/lib/Frontend/CompilerInvocation.cpp (original)
+++ cfe/trunk/lib/Frontend/CompilerInvocation.cpp Tue Jun 4 18:57:57 2019
@@ -682,6 +682,8 @@ static bool ParseCodeGenArgs(CodeGenOpti
StringRef Name = A->getValue();
if (Name == "Accelerate")
Opts.setVecLib(CodeGenOptions::Accelerate);
+else if (Name == "MASSV")
+ Opts.setVecLib(CodeGenOptions::MASSV);
else if (Name == "SVML")
Opts.setVecLib(CodeGenOptions::SVML);
else if (Name == "none")
Modified: cfe/trunk/test/Driver/autocomplete.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/autocomplete.c?rev=362571&r1=362570&r2=362571&view=diff
==
--- cfe/trunk/test/Driver/autocomplete.c (original)
+++ cfe/trunk/test/Driver/autocomplete.c
Re: [llvm-dev] Zorg migration to GitHub/monorepo
I think what she is referring to was that the build seemed to be triggered by a commit to a project that shouldn't trigger builds on a libcxx bot (i.e. the change was in llvm). I have a somewhat orthogonal but related question. In the past, commits to compiler-rt did not trigger builds on llvm/clang/sanitizer bots. Has this behaviour been rectified with the move to github? I am really sorry if you already answered this question and I just missed it. On Mon, Oct 28, 2019 at 2:37 PM Galina Kistanova via llvm-dev < llvm-...@lists.llvm.org> wrote: > Hi Diana, > > It is not clear from your description of what is the problem. Could > you elaborate, please? > > I have looked at the build history closer and see that this build > configuration depends on libcxx, libcxxabi, libunwind, llvm projects, > and changes to any of these would trigger a build. Depending on a bot > performance, patches could be grouped to a longer blame list. To me, > this is exactly how it supposedly should be. Are you missing any > particular changes in libcxx, libcxxabi,or libunwind project which > should trigger a build but they didn't? If so, could you point me to > such change, please? > > Thanks > > Galina > > > > On Mon, Oct 28, 2019 at 5:16 AM Diana Picus > wrote: > > > > Hi Galina, > > > > It seems that our libcxx bots are now triggering builds for any changes > to llvm: > > > http://lab.llvm.org:8011/builders/libcxx-libcxxabi-libunwind-aarch64-linux/builds/2434 > > > > Should I file a bug report for this? > > > > Thanks, > > Diana > > > > On Sat, 19 Oct 2019 at 11:36, Galina Kistanova via cfe-commits > > wrote: > > > > > > Hello everyone, > > > > > > The staging master is ready to accept bots from the list I have sent > yesterday. Don't wait too long. > > > > > > The master has been updated and works with both SVN and Github > monorepo now. > > > > > > The following builders are already listening for changes in monorepo > and building monorepo. More are coming. > > > > > > * clang-sphinx-docs > > > * clang-tools-sphinx-docs > > > * clang-x86_64-linux-abi-test > > > * clang-lld-x86_64-2stage > > > * libcxx-libcxxabi-singlethreaded-x86_64-linux-debian > > > * libcxx-sphinx-docs > > > * libunwind-sphinx-docs > > > * lld-sphinx-docs > > > * lld-x86_64-darwin13 > > > * lld-x86_64-ubuntu-fast > > > * lldb-sphinx-docs > > > * llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast > > > * llvm-clang-x86_64-win-fast <<-- ? > > > * llvm-sphinx-docs > > > * clang-x86_64-debian-fast > > > * libcxx-libcxxabi-libunwind-x86_64-linux-debian > > > * libcxx-libcxxabi-singlethreaded-x86_64-linux-debian > > > * libcxx-libcxxabi-x86_64-linux-debian > > > * libcxx-libcxxabi-x86_64-linux-debian-noexceptions > > > > > > A friendly reminder. If your bots are using one of these build > factories, you would need either update your build configurations to use > one of the currently supported build factories, or port that factory to > work with github and monorepo. > > > > > > * LLVMBuilder (3 bots) > > > * PollyBuilder (3 bots) > > > * LLDBBuilder (6 bots) > > > * SanitizerBuilder (10 bots) > > > * CUDATestsuiteBuilder (1 bot) - depends on > ClangBuilder.getClangBuildFactory > > > * AOSPBuilder (1 bot) - depends on PollyBuilder > > > * AnnotatedBuilder (2 bots) > > > * OpenMPBuilder (2 bots) > > > * FuchsiaBuilder (1 bot) > > > > > > Thanks > > > > > > Galina > > > > > > > > > On Fri, Oct 18, 2019 at 12:05 AM Galina Kistanova < > gkistan...@gmail.com> wrote: > > >> > > >> Hello build bot owners! > > >> > > >> The staging master is ready. Please feel free to use it to make sure > your bots would work well with the monorepo and github. > > >> > > >> The following builders could be configured to build monorepo: > > >> > > >> * clang-atom-d525-fedora-rel > > >> * clang-native-arm-lnt-perf > > >> * clang-cmake-armv7-lnt > > >> * clang-cmake-armv7-selfhost-neon > > >> * clang-cmake-armv7-quick > > >> * clang-cmake-armv7-global-isel > > >> * clang-cmake-armv7-selfhost > > >> * clang-cmake-aarch64-quick > > >> * clang-cmake-aarch64-lld > > >> * clang-cmake-aarch64-global-isel > > >> * clang-ppc64be-linux-lnt > > >> * clang-ppc64be-linux-multistage > > >> * clang-ppc64le-linux-lnt > > >> * clang-ppc64le-linux-multistage > > >> * clang-ppc64be-linux > > >> * clang-ppc64le-linux > > >> * clang-s390x-linux > > >> * clang-s390x-linux-multistage > > >> * clang-s390x-linux-lnt > > >> * clang-hexagon-elf > > >> * clang-cmake-x86_64-avx2-linux > > >> * clang-cmake-x86_64-avx2-linux-perf > > >> * clang-cmake-x86_64-sde-avx512-linux > > >> * clang-solaris11-amd64 > > >> * clang-x64-ninja-win7 > > >> * clang-solaris11-sparcv9 > > >> * clang-cmake-armv7-full > > >> * clang-cmake-thumbv7-full-sh > > >> * clang-cmake-armv8-lld > > >> * clang-cmake-aarch64-full > > >> * clang-armv7-linux-build-cache > > >> * clang-aarch64-linux-build-cache > > >> * libcxx-libcxxabi-x86_64-linux-debian > > >> * libcxx-libcxxabi-x86_64-linux-debian-noexceptions > > >> * libcxx-libcxxabi-libunwind-x86_64-linu
[clang] aede24e - [PowerPC] Treat 'Z' inline asm constraint as a true memory constraint
Author: Nemanja Ivanovic
Date: 2020-05-22T07:59:21-05:00
New Revision: aede24ecaa08db806fb173faf2de9cff95df8cee
URL:
https://github.com/llvm/llvm-project/commit/aede24ecaa08db806fb173faf2de9cff95df8cee
DIFF:
https://github.com/llvm/llvm-project/commit/aede24ecaa08db806fb173faf2de9cff95df8cee.diff
LOG: [PowerPC] Treat 'Z' inline asm constraint as a true memory constraint
We currently emit incorrect codegen for this constraint because we set it as a
constraint that allows registers. This will cause the value to be copied to the
stack and that address to be passed as the address. This is not what we want.
Fixes: https://bugs.llvm.org/show_bug.cgi?id=42762
Differential revision: https://reviews.llvm.org/D77542
Added:
Modified:
clang/lib/Basic/Targets/PPC.h
clang/test/CodeGen/ppc64-inline-asm.c
Removed:
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 6261a49c4fde..7c19a96a99c7 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -276,11 +276,12 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
break;
case 'Q': // Memory operand that is an offset from a register (it is
// usually better to use `m' or `es' in asm statements)
+ Info.setAllowsRegister();
+ LLVM_FALLTHROUGH;
case 'Z': // Memory operand that is an indexed or indirect from a
// register (it is usually better to use `m' or `es' in
// asm statements)
Info.setAllowsMemory();
- Info.setAllowsRegister();
break;
case 'R': // AIX TOC entry
case 'a': // Address operand that is an indexed or indirect from a
diff --git a/clang/test/CodeGen/ppc64-inline-asm.c
b/clang/test/CodeGen/ppc64-inline-asm.c
index 3e958c328f92..0b32d0bf4820 100644
--- a/clang/test/CodeGen/ppc64-inline-asm.c
+++ b/clang/test/CodeGen/ppc64-inline-asm.c
@@ -37,3 +37,16 @@ double test_fmax(double x, double y) {
// CHECK-LABEL: double @test_fmax(double %x, double %y)
// CHECK: call double asm "xsmaxdp ${0:x}, ${1:x}, ${2:x}",
"=^ws,^ws,^ws"(double %x, double %y)
}
+
+void testZ(void *addr) {
+ asm volatile ("dcbz %y0\n" :: "Z"(*(unsigned char *)addr) : "memory");
+// CHECK-LABEL: void @testZ(i8* %addr)
+// CHECK: call void asm sideeffect "dcbz ${0:y}\0A", "*Z,~{memory}"(i8* %addr)
+}
+
+void testZwOff(void *addr, long long off) {
+ asm volatile ("dcbz %y0\n" :: "Z"(*(unsigned char *)(addr + off)) :
"memory");
+// CHECK-LABEL: void @testZwOff(i8* %addr, i64 %off)
+// CHECK: %[[VAL:[^ ]+]] = getelementptr i8, i8* %addr, i64 %off
+// CHECK: call void asm sideeffect "dcbz ${0:y}\0A", "*Z,~{memory}"(i8*
%[[VAL]])
+}
___
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[clang] f9e94eb - [Clang] Enable _Complex __float128
Author: Nemanja Ivanovic
Date: 2020-05-28T06:55:49-05:00
New Revision: f9e94eb8688d1fe1727360462e957fbbfb754e59
URL:
https://github.com/llvm/llvm-project/commit/f9e94eb8688d1fe1727360462e957fbbfb754e59
DIFF:
https://github.com/llvm/llvm-project/commit/f9e94eb8688d1fe1727360462e957fbbfb754e59.diff
LOG: [Clang] Enable _Complex __float128
When I added __float128 a while ago, I neglected to add support for the complex
variant of the type. This patch just adds that.
Differential revision: https://reviews.llvm.org/D80533
Added:
Modified:
clang/lib/Sema/DeclSpec.cpp
clang/test/CodeGen/ppc64-complex-parms.c
clang/test/CodeGen/ppc64-complex-return.c
Removed:
diff --git a/clang/lib/Sema/DeclSpec.cpp b/clang/lib/Sema/DeclSpec.cpp
index 276e35a3497e..834e2533342d 100644
--- a/clang/lib/Sema/DeclSpec.cpp
+++ b/clang/lib/Sema/DeclSpec.cpp
@@ -1269,7 +1269,8 @@ void DeclSpec::Finish(Sema &S, const PrintingPolicy
&Policy) {
// Note that this intentionally doesn't include _Complex _Bool.
if (!S.getLangOpts().CPlusPlus)
S.Diag(TSTLoc, diag::ext_integer_complex);
-} else if (TypeSpecType != TST_float && TypeSpecType != TST_double) {
+} else if (TypeSpecType != TST_float && TypeSpecType != TST_double &&
+ TypeSpecType != TST_float128) {
S.Diag(TSCLoc, diag::err_invalid_complex_spec)
<< getSpecifierName((TST)TypeSpecType, Policy);
TypeSpecComplex = TSC_unspecified;
diff --git a/clang/test/CodeGen/ppc64-complex-parms.c
b/clang/test/CodeGen/ppc64-complex-parms.c
index c0e1794bf47c..1c8aa1d568cf 100644
--- a/clang/test/CodeGen/ppc64-complex-parms.c
+++ b/clang/test/CodeGen/ppc64-complex-parms.c
@@ -1,8 +1,19 @@
+// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s |
FileCheck %s
+// RUN: %clang_cc1 -target-feature +float128 -DTEST_F128 -triple \
+// RUN: powerpc64le-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s \
+// RUN: --check-prefix CHECK-F128
float crealf(_Complex float);
double creal(_Complex double);
long double creall(_Complex long double);
+#ifdef TEST_F128
+__float128 crealf128(_Complex __float128);
+__float128 foo_f128(_Complex __float128 x) {
+ return crealf128(x);
+}
+// CHECK-F128: define fp128 @foo_f128(fp128 {{[%A-Za-z0-9.]+}}, fp128
{{[%A-Za-z0-9.]+}})
+#endif
float foo_float(_Complex float x) {
return crealf(x);
diff --git a/clang/test/CodeGen/ppc64-complex-return.c
b/clang/test/CodeGen/ppc64-complex-return.c
index 02bfe82d4efe..a27286d85b8f 100644
--- a/clang/test/CodeGen/ppc64-complex-return.c
+++ b/clang/test/CodeGen/ppc64-complex-return.c
@@ -1,9 +1,20 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s |
FileCheck %s
+// RUN: %clang_cc1 -target-feature +float128 -DTEST_F128 -triple \
+// RUN: powerpc64le-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s \
+// RUN: --check-prefix CHECK-F128
float crealf(_Complex float);
double creal(_Complex double);
long double creall(_Complex long double);
+#ifdef TEST_F128
+__float128 crealf128(_Complex __float128);
+_Complex __float128 foo_f128(_Complex __float128 x) {
+ return x;
+}
+
+// CHECK-F128: define { fp128, fp128 } @foo_f128(fp128 {{[%A-Za-z0-9.]+}},
fp128 {{[%A-Za-z0-9.]+}}) [[NUW:#[0-9]+]] {
+#endif
_Complex float foo_float(_Complex float x) {
return x;
@@ -80,6 +91,17 @@ long double bar_long_double(void) {
// CHECK: extractvalue { ppc_fp128, ppc_fp128 } [[VAR3]], 0
// CHECK: extractvalue { ppc_fp128, ppc_fp128 } [[VAR3]], 1
+#ifdef TEST_F128
+__float128 bar_f128(void) {
+ return crealf128(foo_f128(2.0Q - 2.5Qi));
+}
+
+// CHECK-F128: define fp128 @bar_f128() [[NUW]] {
+// CHECK-F128: [[VAR3:[%A-Za-z0-9.]+]] = call { fp128, fp128 } @foo_f128
+// CHECK-F128: extractvalue { fp128, fp128 } [[VAR3]], 0
+// CHECK-F128: extractvalue { fp128, fp128 } [[VAR3]], 1
+#endif
+
int bar_int(void) {
return __real__(foo_int(2 - 3i));
}
___
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[clang] 9021ce9 - [Clang] Enable KF and KC mode for [_Complex] __float128
Author: Nemanja Ivanovic
Date: 2020-05-28T15:48:15-05:00
New Revision: 9021ce9576e438ae5a6fdb574327d30ea6b67fa8
URL:
https://github.com/llvm/llvm-project/commit/9021ce9576e438ae5a6fdb574327d30ea6b67fa8
DIFF:
https://github.com/llvm/llvm-project/commit/9021ce9576e438ae5a6fdb574327d30ea6b67fa8.diff
LOG: [Clang] Enable KF and KC mode for [_Complex] __float128
The headers provided with recent GNU toolchains for PPC have code that includes
typedefs such as:
typedef _Complex float __cfloat128 __attribute__ ((__mode__ (__KC__)))
This patch allows clang to compile programs that contain
#include
with -mfloat128 which it currently fails to compile.
Fixes: https://bugs.llvm.org/show_bug.cgi?id=46068
Differential revision: https://reviews.llvm.org/D80374
Added:
Modified:
clang/include/clang/AST/ASTContext.h
clang/include/clang/Basic/TargetInfo.h
clang/lib/AST/ASTContext.cpp
clang/lib/Basic/TargetInfo.cpp
clang/lib/Sema/SemaDeclAttr.cpp
clang/test/Sema/attr-mode.c
Removed:
diff --git a/clang/include/clang/AST/ASTContext.h
b/clang/include/clang/AST/ASTContext.h
index 509ada3c9696..a5bb9a34c2fb 100644
--- a/clang/include/clang/AST/ASTContext.h
+++ b/clang/include/clang/AST/ASTContext.h
@@ -657,7 +657,7 @@ class ASTContext : public RefCountedBase {
/// getRealTypeForBitwidth -
/// sets floating point QualTy according to specified bitwidth.
/// Returns empty type if there is no appropriate target types.
- QualType getRealTypeForBitwidth(unsigned DestWidth) const;
+ QualType getRealTypeForBitwidth(unsigned DestWidth, bool ExplicitIEEE) const;
bool AtomicUsesUnsupportedLibcall(const AtomicExpr *E) const;
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 910a4d6846aa..0a5379225caf 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -368,8 +368,13 @@ class TargetInfo : public virtual TransferrableTargetInfo,
virtual IntType getLeastIntTypeByWidth(unsigned BitWidth,
bool IsSigned) const;
- /// Return floating point type with specified width.
- RealType getRealTypeByWidth(unsigned BitWidth) const;
+ /// Return floating point type with specified width. On PPC, there are
+ /// three possible types for 128-bit floating point: "PPC double-double",
+ /// IEEE 754R quad precision, and "long double" (which under the covers
+ /// is represented as one of those two). At this time, there is no support
+ /// for an explicit "PPC double-double" type (i.e. __ibm128) so we only
+ /// need to
diff erentiate between "long double" and IEEE quad precision.
+ RealType getRealTypeByWidth(unsigned BitWidth, bool ExplicitIEEE) const;
/// Return the alignment (in bits) of the specified integer type enum.
///
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index c457a5537168..bfb6014027f4 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -10644,8 +10644,10 @@ QualType ASTContext::getIntTypeForBitwidth(unsigned
DestWidth,
/// getRealTypeForBitwidth -
/// sets floating point QualTy according to specified bitwidth.
/// Returns empty type if there is no appropriate target types.
-QualType ASTContext::getRealTypeForBitwidth(unsigned DestWidth) const {
- TargetInfo::RealType Ty = getTargetInfo().getRealTypeByWidth(DestWidth);
+QualType ASTContext::getRealTypeForBitwidth(unsigned DestWidth,
+bool ExplicitIEEE) const {
+ TargetInfo::RealType Ty =
+ getTargetInfo().getRealTypeByWidth(DestWidth, ExplicitIEEE);
switch (Ty) {
case TargetInfo::Float:
return FloatTy;
diff --git a/clang/lib/Basic/TargetInfo.cpp b/clang/lib/Basic/TargetInfo.cpp
index 2f1e044bb106..a3c8da5885b8 100644
--- a/clang/lib/Basic/TargetInfo.cpp
+++ b/clang/lib/Basic/TargetInfo.cpp
@@ -265,7 +265,8 @@ TargetInfo::IntType
TargetInfo::getLeastIntTypeByWidth(unsigned BitWidth,
return NoInt;
}
-TargetInfo::RealType TargetInfo::getRealTypeByWidth(unsigned BitWidth) const {
+TargetInfo::RealType TargetInfo::getRealTypeByWidth(unsigned BitWidth,
+bool ExplicitIEEE) const {
if (getFloatWidth() == BitWidth)
return Float;
if (getDoubleWidth() == BitWidth)
@@ -277,6 +278,10 @@ TargetInfo::RealType
TargetInfo::getRealTypeByWidth(unsigned BitWidth) const {
return LongDouble;
break;
case 128:
+// The caller explicitly asked for an IEEE compliant type but we still
+// have to check if the target supports it.
+if (ExplicitIEEE)
+ return hasFloat128Type() ? Float128 : NoFloat;
if (&getLongDoubleFormat() == &llvm::APFloat::PPCDoubleDouble() ||
&getLongDoubleFormat() == &llvm::APFloat::IEEEquad())
return LongDouble;
diff --git a/clang/lib/Sema/SemaDecl
r282481 - [Power9] Builtins for ELF v.2 ABI conformance - front end portion
Author: nemanjai
Date: Tue Sep 27 05:45:22 2016
New Revision: 282481
URL: http://llvm.org/viewvc/llvm-project?rev=282481&view=rev
Log:
[Power9] Builtins for ELF v.2 ABI conformance - front end portion
This patch corresponds to review:
https://reviews.llvm.org/D24397
It adds the __POWER9_VECTOR__ macro and the -mpower9-vector option along with
a number of altivec.h functions (refer to the code review for a list).
Added:
cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c
Modified:
cfe/trunk/include/clang/Basic/BuiltinsPPC.def
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/lib/Headers/altivec.h
cfe/trunk/test/Driver/ppc-dependent-options.cpp
cfe/trunk/test/Preprocessor/predefined-arch-macros.c
Modified: cfe/trunk/include/clang/Basic/BuiltinsPPC.def
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsPPC.def?rev=282481&r1=282480&r2=282481&view=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsPPC.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsPPC.def Tue Sep 27 05:45:22 2016
@@ -134,6 +134,14 @@ BUILTIN(__builtin_altivec_vcmpequw, "V4i
BUILTIN(__builtin_altivec_vcmpequd, "V2LLiV2LLiV2LLi", "")
BUILTIN(__builtin_altivec_vcmpeqfp, "V4iV4fV4f", "")
+BUILTIN(__builtin_altivec_vcmpneb, "V16cV16cV16c", "")
+BUILTIN(__builtin_altivec_vcmpneh, "V8sV8sV8s", "")
+BUILTIN(__builtin_altivec_vcmpnew, "V4iV4iV4i", "")
+
+BUILTIN(__builtin_altivec_vcmpnezb, "V16cV16cV16c", "")
+BUILTIN(__builtin_altivec_vcmpnezh, "V8sV8sV8s", "")
+BUILTIN(__builtin_altivec_vcmpnezw, "V4iV4iV4i", "")
+
BUILTIN(__builtin_altivec_vcmpgtsb, "V16cV16ScV16Sc", "")
BUILTIN(__builtin_altivec_vcmpgtub, "V16cV16UcV16Uc", "")
BUILTIN(__builtin_altivec_vcmpgtsh, "V8sV8SsV8Ss", "")
@@ -223,6 +231,11 @@ BUILTIN(__builtin_altivec_vcmpequw_p, "i
BUILTIN(__builtin_altivec_vcmpequd_p, "iiV2LLiV2LLi", "")
BUILTIN(__builtin_altivec_vcmpeqfp_p, "iiV4fV4f", "")
+BUILTIN(__builtin_altivec_vcmpneb_p, "iiV16cV16c", "")
+BUILTIN(__builtin_altivec_vcmpneh_p, "iiV8sV8s", "")
+BUILTIN(__builtin_altivec_vcmpnew_p, "iiV4iV4i", "")
+BUILTIN(__builtin_altivec_vcmpned_p, "iiV2LLiV2LLi", "")
+
BUILTIN(__builtin_altivec_vcmpgtsb_p, "iiV16ScV16Sc", "")
BUILTIN(__builtin_altivec_vcmpgtub_p, "iiV16UcV16Uc", "")
BUILTIN(__builtin_altivec_vcmpgtsh_p, "iiV8SsV8Ss", "")
@@ -254,6 +267,16 @@ BUILTIN(__builtin_altivec_vclzb, "V16UcV
BUILTIN(__builtin_altivec_vclzh, "V8UsV8Us", "")
BUILTIN(__builtin_altivec_vclzw, "V4UiV4Ui", "")
BUILTIN(__builtin_altivec_vclzd, "V2ULLiV2ULLi", "")
+BUILTIN(__builtin_altivec_vctzb, "V16UcV16Uc", "")
+BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "")
+BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "")
+BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "")
+
+// Vector population count built-ins
+BUILTIN(__builtin_altivec_vpopcntb, "V16UcV16Uc", "")
+BUILTIN(__builtin_altivec_vpopcnth, "V8UsV8Us", "")
+BUILTIN(__builtin_altivec_vpopcntw, "V4UiV4Ui", "")
+BUILTIN(__builtin_altivec_vpopcntd, "V2ULLiV2ULLi", "")
// VSX built-ins.
Modified: cfe/trunk/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=282481&r1=282480&r2=282481&view=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Tue Sep 27 05:45:22 2016
@@ -1572,6 +1572,10 @@ def mpower8_vector : Flag<["-"], "mpower
Group;
def mno_power8_vector : Flag<["-"], "mno-power8-vector">,
Group;
+def mpower9_vector : Flag<["-"], "mpower9-vector">,
+Group;
+def mno_power9_vector : Flag<["-"], "mno-power9-vector">,
+Group;
def mpower8_crypto : Flag<["-"], "mcrypto">,
Group;
def mnopower8_crypto : Flag<["-"], "mno-crypto">,
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=282481&r1=282480&r2=282481&view=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Tue Sep 27 05:45:22 2016
@@ -870,6 +870,7 @@ class PPCTargetInfo : public TargetInfo
bool HasHTM;
bool HasBPERMD;
bool HasExtDiv;
+ bool HasP9Vector;
protected:
std::string ABI;
@@ -878,7 +879,7 @@ public:
PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
: TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
- HasBPERMD(false), HasExtDiv(false) {
+ HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) {
SimdDefaultAlign = 128;
LongDoubleWidth = LongDoubleAlign = 128;
LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
@@ -1157,6 +1158,8 @@ bool PPCTargetInfo::handleTargetFeatures
Re: [PATCH] D24397: Target Power9 bit counting and vector comparison instructions through builtins (front end portion)
nemanjai closed this revision. nemanjai added a comment. Committed revision 282481. Repository: rL LLVM https://reviews.llvm.org/D24397 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D24397: Target Power9 bit counting and vector comparison instructions through builtins (front end portion)
nemanjai added a comment.
In https://reviews.llvm.org/D24397#555057, @bjope wrote:
> This test/CodeGen/builtins-ppc-p9vector.c test will fail together with this
> upcoming LLVM patch https://reviews.llvm.org/D24955
>
> Problem is that lots of your
>
> add i64 {{.*}}, 64
>
> checks will fails since the improved analysis will find out that the add has
> the "nsw" "nuw" properties.
>
> I'm not so familiar with the regexps used by FileCheck, but somehow we need
> to (also) allow
>
> add nsw nuw i64 {{.*}}, 64
>
> in the checks to make it more future proof.
I can change the patterns that check for the add instructions to the following:
// CHECK: add {{[nsuw ]*}}i64 {{.*}}, 64
That will pass with:
add nsw i64
add nuw i64
add nsw nuw i64
...
Basically if all that is found between the "add" and "i64" is any combination
of the letters "nsuw" and space, it will pass. As far as I'm concerned,
ensuring that the strings there are well formed is irrelevant - all I'm testing
is that an add instruction is emitted that adds the constant 64.
I can make the change and check it in if you're in agreement.
Repository:
rL LLVM
https://reviews.llvm.org/D24397
___
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http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D24397: Target Power9 bit counting and vector comparison instructions through builtins (front end portion)
nemanjai added a comment. In https://reviews.llvm.org/D24397#555470, @spatel wrote: > Having a clang regression/unit test that depends on optimizer behavior is > generally viewed as wrong. Can the tests be split into front-end (clang) > tests and separate tests for the IR optimizer? Both x86 and AArch64 have done > something like that in the last few months for testing of builtins/intrinsics. Yeah, that sounds reasonable. I'll remove the -O2 from the test case and remove the checks for the select instructions. That's really the only major difference. So am I to understand the nsw/nuw flags will not be added without -O2 and the aforementioned changes will suffice? Repository: rL LLVM https://reviews.llvm.org/D24397 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D24397: Target Power9 bit counting and vector comparison instructions through builtins (front end portion)
Well, I don't know much about what Clang will actually do here, but I'll follow your advice and add -O0 and pipe to opt -S -mem2reg. I'll also add a test case in LLVM (test/CodeGen/PowerPC) that will test that after opt and llc, we generate the desired code for these builtins. Thanks Sanjay and Bjorn. On Wed, Sep 28, 2016 at 6:53 PM, Sanjay Patel wrote: > spatel added a comment. > > In https://reviews.llvm.org/D24397#52, @nemanjai wrote: > > > In https://reviews.llvm.org/D24397#555470, @spatel wrote: > > > > > Having a clang regression/unit test that depends on optimizer behavior > is generally viewed as wrong. Can the tests be split into front-end (clang) > tests and separate tests for the IR optimizer? Both x86 and AArch64 have > done something like that in the last few months for testing of > builtins/intrinsics. > > > > > > Yeah, that sounds reasonable. I'll remove the -O2 from the test case and > remove the checks for the select instructions. That's really the only major > difference. So am I to understand the nsw/nuw flags will not be added > without -O2 and the aforementioned changes will suffice? > > > Changing to -O0 or using -disable-llvm-optzns should keep the clang tests > from breaking due to underlying changes in the IR optimizer. That may lead > to a lot of bloat though. In http://lists.llvm.org/ > pipermail/cfe-commits/Week-of-Mon-20160307/152324.html , it was viewed as > ok, if not ideal, to pipe the clang IR output using "opt -S -mem2reg". > > Note that clang itself uses APIs like IRBuilder::CreateNUWSub(), so I > think it's possible to see no-wrap IR even without the IR optimizer kicking > in (but probably isn't a concern in this case?). > > > Repository: > rL LLVM > > https://reviews.llvm.org/D24397 > > > > ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D24397: Target Power9 bit counting and vector comparison instructions through builtins (front end portion)
OK, I get testing that I'm fine with if I remove the -O2 and the checks for 'select i1'. Does that change suffice for the purposes of https://reviews.llvm.org/D24955 ? Namely, do I need to account for the possible addition of nsw/nuw flags to the add instructions even without -O2? On Wed, Oct 5, 2016 at 8:24 PM, Sanjay Patel wrote: > spatel added a comment. > > In https://reviews.llvm.org/D24397#562469, @bjope wrote: > > > (I'm still hesitating about commiting https://reviews.llvm.org/D24955 > in llvm since that would make these clang tests fail...) > > > You can't do that. Bots will send you fail mail all day as they choke on > the clang tests - speaking from experience. :) > We either need to fix or revert this commit in order to let > https://reviews.llvm.org/D24955 proceed. > > > Repository: > rL LLVM > > https://reviews.llvm.org/D24397 > > > > ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D24397: Target Power9 bit counting and vector comparison instructions through builtins (front end portion)
OK, will remove optimization and the selects and commit this now. Sorry about the delay. On Wed, Oct 5, 2016 at 9:16 PM, Sanjay Patel wrote: > You should not need to account for any nsw/nuw flags if the clang test > does not enable the optimizer. > Ie, D24955 should not be running at -O0. > > On Wed, Oct 5, 2016 at 1:09 PM, Nemanja Ivanovic > wrote: > >> OK, I get testing that I'm fine with if I remove the -O2 and the checks >> for 'select i1'. >> >> Does that change suffice for the purposes of >> https://reviews.llvm.org/D24955? >> >> Namely, do I need to account for the possible addition of nsw/nuw flags >> to the add instructions even without -O2? >> >> On Wed, Oct 5, 2016 at 8:24 PM, Sanjay Patel >> wrote: >> >>> spatel added a comment. >>> >>> In https://reviews.llvm.org/D24397#562469, @bjope wrote: >>> >>> > (I'm still hesitating about commiting https://reviews.llvm.org/D24955 >>> in llvm since that would make these clang tests fail...) >>> >>> >>> You can't do that. Bots will send you fail mail all day as they choke on >>> the clang tests - speaking from experience. :) >>> We either need to fix or revert this commit in order to let >>> https://reviews.llvm.org/D24955 proceed. >>> >>> >>> Repository: >>> rL LLVM >>> >>> https://reviews.llvm.org/D24397 >>> >>> >>> >>> >> > ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r283363 - Removing optimization from the RUN lines and adjusting the checks
Author: nemanjai
Date: Wed Oct 5 14:11:36 2016
New Revision: 283363
URL: http://llvm.org/viewvc/llvm-project?rev=283363&view=rev
Log:
Removing optimization from the RUN lines and adjusting the checks
to not rely on optimization.
Modified:
cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c
Modified: cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c?rev=283363&r1=283362&r2=283363&view=diff
==
--- cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c (original)
+++ cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c Wed Oct 5 14:11:36 2016
@@ -1,11 +1,11 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -faltivec -target-feature +power9-vector \
// RUN: -triple powerpc64-unknown-unknown -emit-llvm %s \
-// RUN: -O2 -o - | FileCheck %s -check-prefix=CHECK-BE
+// RUN: -o - | FileCheck %s -check-prefix=CHECK-BE
// RUN: %clang_cc1 -faltivec -target-feature +power9-vector \
// RUN: -triple powerpc64le-unknown-unknown -emit-llvm %s \
-// RUN: -O2 -o - | FileCheck %s
+// RUN: -o - | FileCheck %s
#include
@@ -31,7 +31,6 @@ unsigned test1(void) {
// CHECK-BE: icmp eq i64 {{.*}}, 64
// CHECK-BE: extractelement <2 x i64>
// CHECK-BE: add i64 {{.*}}, 64
-// CHECK-BE: select i1
// CHECK-BE: lshr i64 {{.*}}, 3
// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
// CHECK: @llvm.cttz.v2i64(<2 x i64>
@@ -39,7 +38,6 @@ unsigned test1(void) {
// CHECK: icmp eq i64 {{.*}}, 64
// CHECK: extractelement <2 x i64>
// CHECK: add i64 {{.*}}, 64
-// CHECK: select i1
// CHECK: lshr i64 {{.*}}, 3
return vec_first_match_index (vsca, vscb);
}
@@ -50,7 +48,6 @@ unsigned test2(void) {
// CHECK-BE: icmp eq i64 {{.*}}, 64
// CHECK-BE: extractelement <2 x i64>
// CHECK-BE: add i64 {{.*}}, 64
-// CHECK-BE: select i1
// CHECK-BE: lshr i64 {{.*}}, 3
// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
// CHECK: @llvm.cttz.v2i64(<2 x i64>
@@ -58,7 +55,6 @@ unsigned test2(void) {
// CHECK: icmp eq i64 {{.*}}, 64
// CHECK: extractelement <2 x i64>
// CHECK: add i64 {{.*}}, 64
-// CHECK: select i1
// CHECK: lshr i64 {{.*}}, 3
return vec_first_match_index (vuca, vucb);
}
@@ -69,7 +65,6 @@ unsigned test3(void) {
// CHECK-BE: icmp eq i64 {{.*}}, 64
// CHECK-BE: extractelement <2 x i64>
// CHECK-BE: add i64 {{.*}}, 64
-// CHECK-BE: select i1
// CHECK-BE: lshr i64 {{.*}}, 5
// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
// CHECK: @llvm.cttz.v2i64(<2 x i64>
@@ -77,7 +72,6 @@ unsigned test3(void) {
// CHECK: icmp eq i64 {{.*}}, 64
// CHECK: extractelement <2 x i64>
// CHECK: add i64 {{.*}}, 64
-// CHECK: select i1
// CHECK: lshr i64 {{.*}}, 5
return vec_first_match_index (vsia, vsib);
}
@@ -88,7 +82,6 @@ unsigned test4(void) {
// CHECK-BE: icmp eq i64 {{.*}}, 64
// CHECK-BE: extractelement <2 x i64>
// CHECK-BE: add i64 {{.*}}, 64
-// CHECK-BE: select i1
// CHECK-BE: lshr i64 {{.*}}, 5
// CHECK: @llvm.ppc.altivec.vcmpequw(<4 x i32>
// CHECK: @llvm.cttz.v2i64(<2 x i64>
@@ -96,7 +89,6 @@ unsigned test4(void) {
// CHECK: icmp eq i64 {{.*}}, 64
// CHECK: extractelement <2 x i64>
// CHECK: add i64 {{.*}}, 64
-// CHECK: select i1
// CHECK: lshr i64 {{.*}}, 5
return vec_first_match_index (vuia, vuib);
}
@@ -107,7 +99,6 @@ unsigned test5(void) {
// CHECK-BE: icmp eq i64 {{.*}}, 64
// CHECK-BE: extractelement <2 x i64>
// CHECK-BE: add i64 {{.*}}, 64
-// CHECK-BE: select i1
// CHECK-BE: lshr i64 {{.*}}, 4
// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
// CHECK: @llvm.cttz.v2i64(<2 x i64>
@@ -115,7 +106,6 @@ unsigned test5(void) {
// CHECK: icmp eq i64 {{.*}}, 64
// CHECK: extractelement <2 x i64>
// CHECK: add i64 {{.*}}, 64
-// CHECK: select i1
// CHECK: lshr i64 {{.*}}, 4
return vec_first_match_index (vssa, vssb);
}
@@ -126,7 +116,6 @@ unsigned test6(void) {
// CHECK-BE: icmp eq i64 {{.*}}, 64
// CHECK-BE: extractelement <2 x i64>
// CHECK-BE: add i64 {{.*}}, 64
-// CHECK-BE: select i1
// CHECK-BE: lshr i64 {{.*}}, 4
// CHECK: @llvm.ppc.altivec.vcmpequh(<8 x i16>
// CHECK: @llvm.cttz.v2i64(<2 x i64>
@@ -134,7 +123,6 @@ unsigned test6(void) {
// CHECK: icmp eq i64 {{.*}}, 64
// CHECK: extractelement <2 x i64>
// CHECK: add i64 {{.*}}, 64
-// CHECK: select i1
// CHECK: lshr i64 {{.*}}, 4
return vec_first_match_index (vusa, vusb);
}
@@ -149,7 +137,6 @@ unsigned test7(void) {
// CHECK-BE: icmp eq i64 {{.*}}, 64
// CHECK-BE: extractelement <2 x i64>
// CHECK-BE: add i64 {{.*}}, 64
-// CHECK-BE: select i1
// CHECK-BE: lshr i64 {{.*}}, 3
// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
// CHECK: @llvm.ppc.altivec.vcmpequb(<16 x i8>
@@ -161,7 +148,6 @@ unsigned test7(void) {
// CHECK: icmp eq i64 {{.*}}, 64
// CHECK: extractelement <2 x i64>
// CHECK: add i64 {{.*}}, 64
-// CHECK: select i1
// CHECK: lshr i64 {{.*}}, 3
return vec_first_match_or_eos_index (vsca, vscb);
}
@@ -176,7 +162,6 @@ unsigned tes
Re: [PATCH] D24397: Target Power9 bit counting and vector comparison instructions through builtins (front end portion)
Committed revision 283363. On Wed, Oct 5, 2016 at 9:18 PM, Nemanja Ivanovic wrote: > OK, will remove optimization and the selects and commit this now. > Sorry about the delay. > > On Wed, Oct 5, 2016 at 9:16 PM, Sanjay Patel > wrote: > >> You should not need to account for any nsw/nuw flags if the clang test >> does not enable the optimizer. >> Ie, D24955 should not be running at -O0. >> >> On Wed, Oct 5, 2016 at 1:09 PM, Nemanja Ivanovic > > wrote: >> >>> OK, I get testing that I'm fine with if I remove the -O2 and the checks >>> for 'select i1'. >>> >>> Does that change suffice for the purposes of >>> https://reviews.llvm.org/D24955? >>> >>> Namely, do I need to account for the possible addition of nsw/nuw flags >>> to the add instructions even without -O2? >>> >>> On Wed, Oct 5, 2016 at 8:24 PM, Sanjay Patel >>> wrote: >>> spatel added a comment. In https://reviews.llvm.org/D24397#562469, @bjope wrote: > (I'm still hesitating about commiting https://reviews.llvm.org/D24955 in llvm since that would make these clang tests fail...) You can't do that. Bots will send you fail mail all day as they choke on the clang tests - speaking from experience. :) We either need to fix or revert this commit in order to let https://reviews.llvm.org/D24955 proceed. Repository: rL LLVM https://reviews.llvm.org/D24397 >>> >> > ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
nemanjai wrote: > @nemanjai I'm curious if you have an interest / need to support RVE or not? I most certainly do. Thank you for alerting me to this PR. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
https://github.com/nemanjai commented: It is not my intent to hold up approval of this patch. In addition to the minor comments I added, I plan to do some local testing but even if the testing reveals issues, they can be fixed on subsequent commits. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
https://github.com/nemanjai edited https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -38,3 +40,14 @@ def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, // Same as CSR_Interrupt, but including all 64-bit FP registers. def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt, (sequence "F%u_D", 0, 31))>; + +// Same as CSR_Interrupt, but excluding X16-X31. +def CSR_Interrupt_RVE : CalleeSavedRegs<(add X1, (sequence "X%u", 5, 15))>; nemanjai wrote: Minor nit: I think it would be nice if the code reads as clearly as this comment does. Namely `(sub CSR_Interrupt, (sequence "X%u, 16, 31))` Similarly below. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -83,13 +88,14 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction
*MF) const {
}
BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+ const RISCVSubtarget &STI = MF.getSubtarget();
nemanjai wrote:
Why was this added? Or perhaps, why wasn't the `Subtarget` variable removed?
https://github.com/llvm/llvm-project/pull/76777
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[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -985,9 +1003,10 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, }; for (auto Reg : CSRegs) - SavedRegs.set(Reg); + if (Reg < RISCV::X16 || !Subtarget.isRVE()) nemanjai wrote: What happens if we are using `ilp32e/lp64e` ABI on a subtarget that isn't RVE? Should these registers be saved? https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -17,6 +17,13 @@ def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">, AssemblerPredicate<(all_of FeatureStdExtZicsr), "'Zicsr' (CSRs)">; +def FeatureStdExtI +: SubtargetFeature<"i", "HasStdExtI", "true", + "'I' (Base Integer Instruction Set)">; +def HasStdExtI : Predicate<"Subtarget->hasStdExtI()">, + AssemblerPredicate<(all_of FeatureStdExtI), + "'I' (Base Integer Instruction Set)">; + nemanjai wrote: Just out of curiosity, why was this added in this patch? https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -179,6 +180,11 @@ Assembly Support Supported Fully supported by the compiler. This includes everything in Assembly Support, along with - if relevant - C language intrinsics for the instructions and pattern matching by the compiler to recognize idiomatic patterns which can be lowered to the associated instructions. +.. _riscv-rve-note: + +``E`` + Support of RV32E/RV64E and ilp32e/lp64e ABIs are experimental. To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass variadic arguments and set stack alignment to 4-bytes for types with length of 2*XLEN. nemanjai wrote: Use of `and` in the second sentence is ambiguous. Given statements A and B: A: we use aligned registers to pass variadic arguments B: we set the stack alignment to 4 bytes for types with length 2*XLEN - we don't (A and B) == we don't A nor B - we don't A and we do B I think it would be clearer as: ``` To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass variadic arguments. Furthermore, we set the stack alignment to 4 bytes for types with length of 2*XLEN. ``` https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -50,11 +50,14 @@ void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
bool EmitStackAlign) {
- if (STI.hasFeature(RISCV::FeatureRVE))
-report_fatal_error("Codegen not yet implemented for RVE");
-
- if (EmitStackAlign)
-emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
+ if (EmitStackAlign) {
+if (STI.hasFeature(RISCV::FeatureRVE))
nemanjai wrote:
This seems to not match what the usage doc above says. Namely, the doc says
that the alignment is dependent on the ABI but this uses the ISA feature rather
than the ABI.
Furthermore, `getABIStackAlignment()` also obviously uses the ABI rather than
the ISA feature.
https://github.com/llvm/llvm-project/pull/76777
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[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
@@ -985,9 +1003,10 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, }; for (auto Reg : CSRegs) - SavedRegs.set(Reg); + if (Reg < RISCV::X16 || !Subtarget.isRVE()) nemanjai wrote: Sounds good. Maybe just a little comment here to demonstrate to the user that this isn't an omission but a conscious decision. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
https://github.com/nemanjai approved this pull request. My comments have been addressed, so this LGTM. I'll of course defer to @asb and @topperc for final approval. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
https://github.com/nemanjai updated
https://github.com/llvm/llvm-project/pull/68919
>From 71f1352bf00d6a9eefa3f199859d47d093f272f8 Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic
Date: Thu, 12 Oct 2023 14:08:42 -0400
Subject: [PATCH 1/3] [PowerPC][X86] Make cpu id builtins target independent
and lower for PPC
Make __builtin_cpu_{init|supports|is} target independent and provide
an opt-in query for targets that want to support it. Each target is
still responsible for their specific lowering/code-gen.
Also provide code-gen for PowerPC.
---
clang/include/clang/Basic/Builtins.def| 5 +
clang/include/clang/Basic/BuiltinsX86.def | 7 -
clang/include/clang/Basic/TargetInfo.h| 6 +
clang/lib/Basic/Targets/PPC.cpp | 14 ++
clang/lib/Basic/Targets/PPC.h | 7 +
clang/lib/Basic/Targets/X86.h | 4 +
clang/lib/CodeGen/CGBuiltin.cpp | 42 +-
clang/lib/Sema/SemaChecking.cpp | 124 +++---
clang/test/CodeGen/builtin-cpu-supports.c | 68 ++
clang/test/Sema/builtin-cpu-supports.c| 8 +-
llvm/include/llvm/IR/IntrinsicsPowerPC.td | 6 +
.../llvm/TargetParser/PPCTargetParser.def | 80 +++
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 4 +
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 33 +
llvm/lib/Target/PowerPC/PPCInstrInfo.td | 3 +
llvm/lib/Target/PowerPC/PPCTargetMachine.h| 3 +
llvm/test/CodeGen/PowerPC/cpu-supports.ll | 111
17 files changed, 443 insertions(+), 82 deletions(-)
create mode 100644 llvm/include/llvm/TargetParser/PPCTargetParser.def
create mode 100644 llvm/test/CodeGen/PowerPC/cpu-supports.ll
diff --git a/clang/include/clang/Basic/Builtins.def
b/clang/include/clang/Basic/Builtins.def
index 6ea8484606cfd5..5e1f4088ff63f8 100644
--- a/clang/include/clang/Basic/Builtins.def
+++ b/clang/include/clang/Basic/Builtins.def
@@ -118,6 +118,11 @@
# define LANGBUILTIN(ID, TYPE, ATTRS, BUILTIN_LANG) BUILTIN(ID, TYPE, ATTRS)
#endif
+// Builtins for checking CPU features based on the GCC builtins.
+BUILTIN(__builtin_cpu_supports, "bcC*", "nc")
+BUILTIN(__builtin_cpu_is, "bcC*", "nc")
+BUILTIN(__builtin_cpu_init, "v", "n")
+
// Standard libc/libm functions:
BUILTIN(__builtin_atan2 , "ddd" , "Fne")
BUILTIN(__builtin_atan2f, "fff" , "Fne")
diff --git a/clang/include/clang/Basic/BuiltinsX86.def
b/clang/include/clang/Basic/BuiltinsX86.def
index e4802f8ab1c156..2acc5ce0f4a365 100644
--- a/clang/include/clang/Basic/BuiltinsX86.def
+++ b/clang/include/clang/Basic/BuiltinsX86.def
@@ -26,13 +26,6 @@
# define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANG, FEATURE)
BUILTIN(ID, TYPE, ATTRS)
#endif
-// Miscellaneous builtin for checking x86 cpu features.
-// TODO: Make this somewhat generic so that other backends
-// can use it?
-BUILTIN(__builtin_cpu_init, "v", "n")
-BUILTIN(__builtin_cpu_supports, "bcC*", "nc")
-BUILTIN(__builtin_cpu_is, "bcC*", "nc")
-
// Undefined Values
//
TARGET_BUILTIN(__builtin_ia32_undef128, "V2d", "ncV:128:", "")
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 9d56e97a3d4bb8..3d83b387aac093 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1415,6 +1415,12 @@ class TargetInfo : public TransferrableTargetInfo,
getTriple().isOSFreeBSD());
}
+ // Identify whether this target supports __builtin_cpu_supports and
+ // __builtin_cpu_is.
+ virtual bool supportsCpuSupports() const { return false; }
+ virtual bool supportsCpuIs() const { return false; }
+ virtual bool supportsCpuInit() const { return false; }
+
// Validate the contents of the __builtin_cpu_supports(const char*)
// argument.
virtual bool validateCpuSupports(StringRef Name) const { return false; }
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 0d87a3a4e8c20f..d8759c86c9932c 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -873,3 +873,17 @@ ArrayRef PPCTargetInfo::getTargetBuiltins()
const {
return llvm::ArrayRef(BuiltinInfo,
clang::PPC::LastTSBuiltin - Builtin::FirstTSBuiltin);
}
+
+bool PPCTargetInfo::validateCpuSupports(StringRef FeatureStr) const {
+#define PPC_FEATURE(NAME, DESC, ENUMNAME, ENUMVAL, HWCAPN) .Case(NAME, true)
+ return llvm::StringSwitch(FeatureStr)
+#include "llvm/TargetParser/PPCTargetParser.def"
+ .Default(false);
+}
+
+bool PPCTargetInfo::validateCpuIs(StringRef CPUName) const {
+#define PPC_CPU(NAME, NUM) .Case(NAME, true)
+ return llvm::StringSwitch(CPUName)
+#include "llvm/TargetParser/PPCTargetParser.def"
+ .Default(false);
+}
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 4d62673ba7fb8c..f700b625b79030 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -359,6 +359,13 @@ class LL
[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S,
SourceLocation Loc,
return false;
}
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI,
+ const TargetInfo *AuxTI, CallExpr *TheCall)
{
+ Expr *Arg = TheCall->getArg(0);
+
+ const TargetInfo *TheTI = nullptr;
+ if (TI.supportsCpuSupports())
+TheTI = &TI;
+ else if (AuxTI && AuxTI->supportsCpuSupports())
+TheTI = AuxTI;
nemanjai wrote:
It does not appear that this is needed for the auxiliary target. I have removed
that now.
https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -0,0 +1,80 @@ +#ifndef PPC_FEATURE nemanjai wrote: Sounds good. https://github.com/llvm/llvm-project/pull/68919 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -1830,6 +1830,10 @@ void PPCLinuxAsmPrinter::emitEndOfAsmFile(Module &M) {
PPCTargetStreamer *TS =
static_cast(OutStreamer->getTargetStreamer());
+ if (static_cast(TM).hasGlibcHWCAPAccess())
nemanjai wrote:
Ha ha, more as in "any"?
https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -1,11 +1,16 @@ -// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s| FileCheck %s +// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s | FileCheck %s \ +// RUN: --check-prefix=CHECK-X86 +// RUN: %clang_cc1 -triple ppc64le-linux-gnu -emit-llvm < %s | FileCheck %s \ +// RUN: --check-prefix=CHECK-PPC + +#ifndef __PPC__ nemanjai wrote: If you feel strongly about this, I don't mind doing it. However, I did it this way to keep the test in the target-independent directory as these are now target-independent builtins. https://github.com/llvm/llvm-project/pull/68919 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -210,6 +210,12 @@ let TargetPrefix = "ppc" in { // All intrinsics start
with "llvm.ppc.".
[llvm_float_ty],
[llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_vararg_ty],
[IntrNoMem]>;
+ // Load of a value provided by the system library at a fixed address. Used
for
+ // accessing things like HWCAP word provided by GLIBC.
nemanjai wrote:
I don't think that comment would make sense any longer now that I have made
this intrinsic PPC-specific. This is why I removed it and shortened it. I will
put back the PPC-specific portions of the elaborated comment though.
https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S,
SourceLocation Loc,
return false;
}
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI,
+ const TargetInfo *AuxTI, CallExpr *TheCall)
{
+ Expr *Arg = TheCall->getArg(0);
+
+ const TargetInfo *TheTI = nullptr;
+ if (TI.supportsCpuSupports())
+TheTI = &TI;
+ else if (AuxTI && AuxTI->supportsCpuSupports())
+TheTI = AuxTI;
+ else
+return S.Diag(TheCall->getBeginLoc(), diag::err_builtin_target_unsupported)
+ << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc());
+
+ // Check if the argument is a string literal.
+ if (!isa(Arg->IgnoreParenImpCasts()))
+return S.Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal)
+ << Arg->getSourceRange();
+
+ // Check the contents of the string.
+ StringRef Feature =
+ cast(Arg->IgnoreParenImpCasts())->getString();
+ if (!TheTI->validateCpuSupports(Feature))
+return S.Diag(TheCall->getBeginLoc(), diag::err_invalid_cpu_supports)
+ << Arg->getSourceRange();
+ return false;
+}
+
+/// SemaBuiltinCpuIs - Handle __builtin_cpu_is(char *).
+/// This checks that the target supports __builtin_cpu_is and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuIs(Sema &S, const TargetInfo &TI,
+ const TargetInfo *AuxTI, CallExpr *TheCall) {
+ Expr *Arg = TheCall->getArg(0);
+
+ const TargetInfo *TheTI = nullptr;
+ if (TI.supportsCpuIs())
+TheTI = &TI;
+ else if (AuxTI && AuxTI->supportsCpuIs())
+TheTI = AuxTI;
+ else
+return S.Diag(TheCall->getBeginLoc(), diag::err_builtin_target_unsupported)
+ << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc());
+
+ // Check if the argument is a string literal.
+ if (!isa(Arg->IgnoreParenImpCasts()))
+return S.Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal)
+ << Arg->getSourceRange();
+
+ // Check the contents of the string.
+ StringRef Feature =
nemanjai wrote:
Sure. But I ended up merging the two.
https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -32,6 +32,7 @@ class PPCTargetMachine final : public LLVMTargetMachine {
std::unique_ptr TLOF;
PPCABI TargetABI;
Endian Endianness = Endian::NOT_DETECTED;
+ mutable bool HasGlibcHWCAPAccess = false;
nemanjai wrote:
Target machine is not modifiable where we need to call `setGlibcHWCAPAccess()`
- namely in `PPCInstrInfo`.
https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S,
SourceLocation Loc,
return false;
}
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI,
+ const TargetInfo *AuxTI, CallExpr *TheCall)
{
nemanjai wrote:
I believe this is for OpenMP when compiling for both the host and device. I had
it in here because it was in the original code but seems to have been removed.
https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S,
SourceLocation Loc,
return false;
}
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI,
+ const TargetInfo *AuxTI, CallExpr *TheCall)
{
+ Expr *Arg = TheCall->getArg(0);
+
+ const TargetInfo *TheTI = nullptr;
+ if (TI.supportsCpuSupports())
+TheTI = &TI;
+ else if (AuxTI && AuxTI->supportsCpuSupports())
+TheTI = AuxTI;
+ else
+return S.Diag(TheCall->getBeginLoc(), diag::err_builtin_target_unsupported)
+ << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc());
+
+ // Check if the argument is a string literal.
+ if (!isa(Arg->IgnoreParenImpCasts()))
nemanjai wrote:
Done. In fact, it makes sense to point to the source location of the actual
argument in the messages too, rather than the parens.
https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -359,6 +359,13 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
bool isSPRegName(StringRef RegName) const override {
return RegName.equals("r1") || RegName.equals("x1");
}
+
+ // We support __builtin_cpu_supports/__builtin_cpu_is on targets that
nemanjai wrote:
Thanks for the info @efriedma-quic. I'll leave the query as it is currently.
https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -873,3 +873,17 @@ ArrayRef PPCTargetInfo::getTargetBuiltins()
const {
return llvm::ArrayRef(BuiltinInfo,
clang::PPC::LastTSBuiltin - Builtin::FirstTSBuiltin);
}
+
+bool PPCTargetInfo::validateCpuSupports(StringRef FeatureStr) const {
nemanjai wrote:
These are existing names that I didn't see a compelling reason to change. There
may be out of tree users of these interfaces, so I opt to not change API's
without a strong reason.
https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -15,38 +20,57 @@ int main(void) {
if (__builtin_cpu_supports("sse4.2"))
a("sse4.2");
- // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32,
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0)
- // CHECK: [[AND:%[^ ]+]] = and i32 [[LOAD]], 256
- // CHECK: = icmp eq i32 [[AND]], 256
+ // CHECK-X86: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32,
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0)
+ // CHECK-X86: [[AND:%[^ ]+]] = and i32 [[LOAD]], 256
+ // CHECK-X86: = icmp eq i32 [[AND]], 256
if (__builtin_cpu_supports("gfni"))
a("gfni");
- // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr @__cpu_features2
- // CHECK: [[AND:%[^ ]+]] = and i32 [[LOAD]], 1
- // CHECK: = icmp eq i32 [[AND]], 1
+ // CHECK-X86: [[LOAD:%[^ ]+]] = load i32, ptr @__cpu_features2
+ // CHECK-X86: [[AND:%[^ ]+]] = and i32 [[LOAD]], 1
+ // CHECK-X86: = icmp eq i32 [[AND]], 1
return 0;
}
-// CHECK: declare dso_local void @__cpu_indicator_init()
+// CHECK-X86: declare dso_local void @__cpu_indicator_init()
-// CHECK-LABEL: define{{.*}} @baseline(
-// CHECK: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]]
x i32], ptr @__cpu_features2, i32 0, i32 1)
-// CHECK-NEXT:and i32 [[LOAD]], -2147483648
+// CHECK-X86-LABEL: define{{.*}} @baseline(
+// CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds
([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 1)
+// CHECK-X86-NEXT:and i32 [[LOAD]], -2147483648
int baseline() { return __builtin_cpu_supports("x86-64"); }
-// CHECK-LABEL: define{{.*}} @v2(
-// CHECK: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]]
x i32], ptr @__cpu_features2, i32 0, i32 2)
-// CHECK-NEXT:and i32 [[LOAD]], 1
+// CHECK-X86-LABEL: define{{.*}} @v2(
+// CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds
([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
+// CHECK-X86-NEXT:and i32 [[LOAD]], 1
int v2() { return __builtin_cpu_supports("x86-64-v2"); }
-// CHECK-LABEL: define{{.*}} @v3(
-// CHECK: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]]
x i32], ptr @__cpu_features2, i32 0, i32 2)
-// CHECK-NEXT:and i32 [[LOAD]], 2
+// CHECK-X86-LABEL: define{{.*}} @v3(
+// CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds
([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
+// CHECK-X86-NEXT:and i32 [[LOAD]], 2
int v3() { return __builtin_cpu_supports("x86-64-v3"); }
-// CHECK-LABEL: define{{.*}} @v4(
-// CHECK: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]]
x i32], ptr @__cpu_features2, i32 0, i32 2)
-// CHECK-NEXT:and i32 [[LOAD]], 4
+// CHECK-X86-LABEL: define{{.*}} @v4(
+// CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds
([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
+// CHECK-X86-NEXT:and i32 [[LOAD]], 4
int v4() { return __builtin_cpu_supports("x86-64-v4"); }
+#else
+int test(int a) {
+// CHECK-PPC: [[CPUSUP:%[^ ]+]] = call i32 @llvm.ppc.fixed.addr.ld(i32 2)
+// CHECK-PPC: [[AND:%[^ ]+]] = and i32 [[CPUSUP]], 8388608
nemanjai wrote:
Sure. I just re-generated the checks using the script.
https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -3124,6 +3125,36 @@ bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI)
const {
.addReg(Reg);
return true;
}
+ case PPC::PPCLdFixedAddr: {
+assert(Subtarget.isTargetLinux() &&
+ "Only Linux target is expected to contain PPCLdFixedAddr");
+int64_t Offset = 0;
+const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
+MI.setDesc(get(PPC::LWZ));
+uint64_t FAType = MI.getOperand(1).getImm();
+#undef PPC_FEATURE
+#undef PPC_CPU
+#include "llvm/TargetParser/PPCTargetParser.def"
+// The HWCAP and HWCAP2 word offsets are reversed on big endian Linux.
+if ((FAType == PPC_FAWORD_HWCAP && Subtarget.isLittleEndian()) ||
+(FAType == PPC_FAWORD_HWCAP2 && !Subtarget.isLittleEndian()))
+ Offset = Subtarget.isPPC64() ? -0x7064 : -0x703C;
nemanjai wrote:
That is a good point. These aren't externally documented- by Glibc, but they
should be documented here in the code.
https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -15,38 +20,57 @@ int main(void) {
if (__builtin_cpu_supports("sse4.2"))
a("sse4.2");
- // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32,
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0)
- // CHECK: [[AND:%[^ ]+]] = and i32 [[LOAD]], 256
- // CHECK: = icmp eq i32 [[AND]], 256
+ // CHECK-X86: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32,
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0)
+ // CHECK-X86: [[AND:%[^ ]+]] = and i32 [[LOAD]], 256
+ // CHECK-X86: = icmp eq i32 [[AND]], 256
if (__builtin_cpu_supports("gfni"))
a("gfni");
- // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr @__cpu_features2
- // CHECK: [[AND:%[^ ]+]] = and i32 [[LOAD]], 1
- // CHECK: = icmp eq i32 [[AND]], 1
+ // CHECK-X86: [[LOAD:%[^ ]+]] = load i32, ptr @__cpu_features2
+ // CHECK-X86: [[AND:%[^ ]+]] = and i32 [[LOAD]], 1
+ // CHECK-X86: = icmp eq i32 [[AND]], 1
return 0;
}
-// CHECK: declare dso_local void @__cpu_indicator_init()
+// CHECK-X86: declare dso_local void @__cpu_indicator_init()
-// CHECK-LABEL: define{{.*}} @baseline(
-// CHECK: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]]
x i32], ptr @__cpu_features2, i32 0, i32 1)
-// CHECK-NEXT:and i32 [[LOAD]], -2147483648
+// CHECK-X86-LABEL: define{{.*}} @baseline(
+// CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds
([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 1)
+// CHECK-X86-NEXT:and i32 [[LOAD]], -2147483648
int baseline() { return __builtin_cpu_supports("x86-64"); }
-// CHECK-LABEL: define{{.*}} @v2(
-// CHECK: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]]
x i32], ptr @__cpu_features2, i32 0, i32 2)
-// CHECK-NEXT:and i32 [[LOAD]], 1
+// CHECK-X86-LABEL: define{{.*}} @v2(
+// CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds
([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
+// CHECK-X86-NEXT:and i32 [[LOAD]], 1
int v2() { return __builtin_cpu_supports("x86-64-v2"); }
-// CHECK-LABEL: define{{.*}} @v3(
-// CHECK: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]]
x i32], ptr @__cpu_features2, i32 0, i32 2)
-// CHECK-NEXT:and i32 [[LOAD]], 2
+// CHECK-X86-LABEL: define{{.*}} @v3(
+// CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds
([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
+// CHECK-X86-NEXT:and i32 [[LOAD]], 2
int v3() { return __builtin_cpu_supports("x86-64-v3"); }
-// CHECK-LABEL: define{{.*}} @v4(
-// CHECK: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]]
x i32], ptr @__cpu_features2, i32 0, i32 2)
-// CHECK-NEXT:and i32 [[LOAD]], 4
+// CHECK-X86-LABEL: define{{.*}} @v4(
+// CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds
([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
+// CHECK-X86-NEXT:and i32 [[LOAD]], 4
int v4() { return __builtin_cpu_supports("x86-64-v4"); }
+#else
+int test(int a) {
+// CHECK-PPC: [[CPUSUP:%[^ ]+]] = call i32 @llvm.ppc.fixed.addr.ld(i32 2)
+// CHECK-PPC: [[AND:%[^ ]+]] = and i32 [[CPUSUP]], 8388608
+// CHECK-PPC: icmp ne i32 [[AND]], 0
nemanjai wrote:
Sure. I just re-generated the checks using the script.
https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S, SourceLocation Loc, return false; } +/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *). +/// This checks that the target supports __builtin_cpu_supports and +/// that the string argument is constant and valid. +static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI, nemanjai wrote: Makes sense. https://github.com/llvm/llvm-project/pull/68919 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)
nemanjai wrote: > > Individual implementations will provide different sets of CSR's and need a > > way to read/write them. Of course, this can be done with inline asm, but > > doing such things with inline asm has its limitations (no error checking, > > Wouldn't the assembler error check the constant? Diagnostic is probably a bit > uglier, but its not nothing. Perhaps it would, but I really don't think it is particularly friendly to the user to rely on the assembler for this. > > > if a user attempts to wrap the asm in a function, they won't be able to > > build code that calls those functions with -O0 as inlining/constant > > propagation is required, etc.). > > You mean if they write a generic write_csr or read_csr function? If they use > a `write_frm` or `read_fcsr` function then there is no constant propagation > issue and they get to refer to the CSR by name in the assembly string instead > of maintaining a constant in their code. Yes, I mean the general, unnamed CSR's. https://github.com/llvm/llvm-project/pull/85091 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)
nemanjai wrote:
> I have always been unconvinced that these are a good idea to have / add
> significant value over using inline assembly. IIRC Arm has them but nobody
> uses them?
Is this a comment about the general concept of builtins to produce specific
instructions or about these specific ones?
For these ones, the patch isn't something I materialized out of thin air just
because I think it's nice to have - it was in response to the very use case I
described (from a library writer). They had something like:
```
void __attribute__((always_inline)) set_csr(unsigned CSRNum, unsigned Val) {
__asm__ volatile ...
```
Which works great if you're optimizing, but doesn't with -O0. Of course they
could write it as a macro, but that has all the pitfalls of function-style
macros.
Of course, if the consensus is to not provide these because of some reason, I'm
fine with that - I would just like to understand the reason for the opposition
to this.
https://github.com/llvm/llvm-project/pull/85091
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[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)
@@ -20,6 +20,12 @@ class RISCVBuiltin :
TargetBuiltin {
let Attributes = [NoThrow, Const] in {
//===--===//
+// Zicsr extension.
+//===--===//
+def csrr : RISCVBuiltin<"unsigned long int(unsigned long int)", "zicsr">;
nemanjai wrote:
I can certainly change it to `size_t`. And I'll move them out of the section
marked with `Const`.
https://github.com/llvm/llvm-project/pull/85091
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[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)
@@ -74,6 +74,21 @@ let TargetPrefix = "riscv" in {
} // TargetPrefix = "riscv"
+let TargetPrefix = "riscv" in {
+ // Zicsr
+ def int_riscv_csrr :
+DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
+ [IntrNoMem, IntrHasSideEffects,
ImmArg>]>;
+ def int_riscv_csrr64 :
+DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty],
+ [IntrNoMem, IntrHasSideEffects,
ImmArg>]>;
+ def int_riscv_csrw :
+DefaultAttrsIntrinsic<[], [llvm_i32_ty, llvm_i32_ty],
+ [IntrNoMem, IntrHasSideEffects,
ImmArg>]>;
+ def int_riscv_csrw64 :
+DefaultAttrsIntrinsic<[], [llvm_i64_ty, llvm_i64_ty],
+ [IntrNoMem, IntrHasSideEffects,
ImmArg>]>;
+} // TargetPrefix = "riscv"
nemanjai wrote:
TBH, I only implemented these two initially for 2 reasons
1. The user that requested them only needs these for now
2. To validate the approach with the community
I think ultimately, we could provide read, write, set, clear and swap (and
handle producing the immediate forms if the operand allows it).
https://github.com/llvm/llvm-project/pull/85091
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[clang] [DRAFT][RISCV] Emit arch string macro to facilitate ASM programming (PR #85063)
https://github.com/nemanjai closed https://github.com/llvm/llvm-project/pull/85063 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [DRAFT][RISCV] Emit arch string macro to facilitate ASM programming (PR #85063)
nemanjai wrote: Ah, I missed the fact that there is an option `-riscv-add-build-attributes` that the clang driver passes when invoking `cc1as`. Perhaps that option should default to `true`? Thanks and sorry for the noise. https://github.com/llvm/llvm-project/pull/85063 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)
nemanjai wrote:
> > > I have always been unconvinced that these are a good idea to have / add
> > > significant value over using inline assembly. IIRC Arm has them but
> > > nobody uses them?
...
> If it’s not a constant integer for inline assembly then how would it
> magically be a constant integer for an intrinsic? The IR’s going to be the
> same with an alloca/store/load, no?
To be completely clear with the use case:
```
$ cat csrread.c
// An obvious way a library writer tries to provide a
// convenience function for reading CSR's.
#ifdef _ASM
static unsigned __attribute__((always_inline)) read_csr(const unsigned CSR) {
unsigned Ret;
__asm__ volatile("csrr %0, %1" : "=r"(Ret) : "I"(CSR));
return Ret;
}
#else
#define read_csr __builtin_riscv_csrr
#endif
// Use the convenience function.
unsigned someFunc() {
return read_csr(0x300);
}
$ clang csrread.c -S --target=riscv32 -D_ASM -O1 && echo Success # No error
checking for no Zicsr but it compiles
Success
$ clang csrread.c -S --target=riscv32 -D_ASM && echo Success # Does not compile
at -O0
csrread.c:6:20: error: constraint 'I' expects an integer constant expression
6 | __asm__ volatile("csrr %0, %1" : "=r"(Ret) : "I"(CSR));
$ clang csrread.c -S --target=riscv32 -O1 && echo Success # The builtin
provides a nice error message for no Zicsr
csrread.c:15:10: error: builtin requires at least one of the following
extensions: 'Zicsr'
15 | return read_csr(0x300);
$ clang csrread.c -S --target=riscv32 -march=rv32i_zicsr && echo Success # The
builtin compiles fine at -O0
Success
```
In my view, the builtin solution is superior from a usability perspective.
https://github.com/llvm/llvm-project/pull/85091
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[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)
nemanjai wrote:
> You can just use `({ ... })` to achieve that same goal with inline assembly
> (and write doesn't even need that, you can do it with a single statement).
> I'm not convinced the intrinsics gain you anything.
Hmm... I think there's a bit of a disconnect here between the point I am trying
to make and your responses. I have attempted to illustrate that this is meant
as a **usability** enhancement. Not something that will increase the expressive
power of the language. Any usability feature, more or less by nature, can be
achieved in **another way**. Whatever usability enhancement one proposes, there
can always be a rebuttal suggesting that the **semantics** can be achieved
through some other mechanism. Sometimes that mechanism is an exotic one such as
GNU statement expressions.
I view the compiler as a tool that users use to achieve the goal of developing
and building their project and its usability has a direct contribution to the
users' ability to effectively achieve their goal. If a tool can easily provide
a convenient and consistent mechanism to achieve a specific goal without
significant drawbacks, it should probably do so.
Suggesting that a facility the compiler can easily provide can be achieved with
something like a GNU statement expression, in my opinion is in direct
opposition to the goal of improving the usability of the compiler. Calls to
functions/intrinsics are a fundamental aspect of a language such as C/C++ that
everyone is familiar with. GNU statement expressions exist in an entirely
different realm and are familiar to an exceedingly small subset of developers.
I feel that the argument of "you don't need this, you can achieve it in another
way" is only meaningful if "this" has significant drawbacks or if "another way"
is equivalently convenient. As an absurd example that regresses this argument
to the absolute extreme, one could state that "you don't need a compiler or
high level language, you can just write your code in assembly." I am of course
not making any attempt to draw a false equivalence between your suggestion and
that absurd example. I am simply illustrating the point that not every way of
achieving a goal is equivalent in terms of skill and effort required to achieve
it.
I am sorry to digress into a philosophical discussion in this post, but I feel
like our discussion is not converging as we are making somewhat orthogonal
arguments.
So can we please discuss the way forward based on whether we feel this
usability enhancement is desirable and whether its benefits outweigh the cost
of providing it. What is not at all clear to me is what you view as the cost of
providing this convenience. And to a lesser extent whether you feel that a
familiar interface such as a builtin would at all be preferrable to any user.
https://github.com/llvm/llvm-project/pull/85091
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[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)
nemanjai wrote: > > Should we use strings like ARM does so we can get register by name? > > Good point! We may provide two kinds of builtins: one by name, and another by > CSR number. We should continue @lenary's proposal and discuss it in > https://github.com/riscv-non-isa/riscv-toolchain-conventions or > https://github.com/riscv-non-isa/riscv-c-api-doc. My personal preference would be to not use strings, but I think a close analog could be pre-defined macro names for existing named CSR's. I just find string matching to be tedious. https://github.com/llvm/llvm-project/pull/85091 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)
https://github.com/nemanjai commented:
Do we really want to support only `__builtin_cpu_is` on AIX? It doesn't seem
like this would achieve the desired goal. Most users will use these builtins to
test for some capability on the target machine. It almost never really matters
to a user whether the CPU is a Power10. They are much more likely to care about
whether the system supports MMA so they can insert calls to MMA functions;
prefixed instructions so they can add them in inline asm, etc.
It is not clear to me what goal is achieved by just providing the processor
identification and not its capabilities.
I think it would be better if (in consultation with the AIX team), we determine
what it means when the kernel reports that the CPU is for example `Power10` and
then we emulate `__builtin_cpu_supports` as well based on that.
For example, a call to `__builtin_cpu_supports("mma")` ends up emitting a check
for whether the CPU is `Power10` or above.
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)
https://github.com/nemanjai edited https://github.com/llvm/llvm-project/pull/80069 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)
@@ -10347,6 +10347,8 @@ def err_x86_builtin_tile_arg_duplicate : Error< def err_builtin_target_unsupported : Error< "builtin is not supported on this target">; +def err_builtin_aix_os_unsupported : Error< + "this builtin is available only in AIX 7.2 and later operating systems">; nemanjai wrote: s/in AIX.../on AIX... https://github.com/llvm/llvm-project/pull/80069 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)
@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, Intrinsic::ID ID = Intrinsic::not_intrinsic; +#include "llvm/TargetParser/PPCTargetParser.def" nemanjai wrote: This is getting a bit tangled. Can you please provide two static functions: `EmitPPCAIXCpuIDFunc(...), EmitPPCLinuxCpuIDFunc(...)` and just call the right one from here. https://github.com/llvm/llvm-project/pull/80069 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)
@@ -362,8 +362,18 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
// We support __builtin_cpu_supports/__builtin_cpu_is on targets that
// have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
+#define MINIMUM_AIX_OS_MAJOR 7
nemanjai wrote:
We can probably just make these `constexpr int` variables rather than #defining
them.
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)
@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
+#include "llvm/TargetParser/PPCTargetParser.def"
+ auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op,
+ unsigned Op_Value) -> Value * {
+Value *Value1 = FieldValue;
nemanjai wrote:
Can you please name the variables for what they're for rather than names such
as `Value1`?
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)
@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
+#include "llvm/TargetParser/PPCTargetParser.def"
+ auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op,
+ unsigned Op_Value) -> Value * {
+Value *Value1 = FieldValue;
+if (Mask)
+ Value1 = Builder.CreateAnd(Value1, Mask);
+assert((Op == OP_EQ) && "Only support equal comparision");
+return Builder.CreateICmp(ICmpInst::ICMP_EQ, FieldValue,
+ ConstantInt::get(Int32Ty, Op_Value));
+ };
+
+ auto ConvBuiltinCpu = [&](unsigned SupportOP, unsigned FieldIdx,
+unsigned Op_Mask, unsigned Op,
+unsigned Op_Value) -> Value * {
+if (SupportOP == AIX_BUILTIN_PPC_FALSE)
+ return llvm::ConstantInt::getFalse(ConvertType(E->getType()));
+
+if (SupportOP == AIX_BUILTIN_PPC_TRUE)
+ return llvm::ConstantInt::getTrue(ConvertType(E->getType()));
+
+assert(SupportOP <= COMP_OP && "Invalid value for SupportOP.");
+llvm::Type *STy = llvm::StructType::get(PPC_SYSTEMCONFIG_TYPE);
+
+llvm::Constant *SysConf =
+CGM.CreateRuntimeVariable(STy, "_system_configuration");
+
+// Grab the appropriate field from _system_configuration.
+llvm::Value *Idxs[] = {ConstantInt::get(Int32Ty, 0),
+ ConstantInt::get(Int32Ty, FieldIdx)};
+
+llvm::Value *FieldValue = Builder.CreateGEP(STy, SysConf, Idxs);
+FieldValue = Builder.CreateAlignedLoad(Int32Ty, FieldValue,
+ CharUnits::fromQuantity(4));
+
+return GetOpRes(FieldValue, Op_Mask, Op, Op_Value);
+ };
+
switch (BuiltinID) {
default: return nullptr;
case Builtin::BI__builtin_cpu_is: {
const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
StringRef CPUStr = cast(CPUExpr)->getString();
-unsigned NumCPUID = StringSwitch(CPUStr)
+llvm::Triple Triple = getTarget().getTriple();
+if (Triple.isOSLinux()) {
+ unsigned NumCPUID = StringSwitch(CPUStr)
#define PPC_LNX_CPU(Name, NumericID) .Case(Name, NumericID)
#include "llvm/TargetParser/PPCTargetParser.def"
-.Default(-1U);
+ .Default(-1U);
assert(NumCPUID < -1U && "Invalid CPU name. Missed by SemaChecking?");
Value *Op0 = llvm::ConstantInt::get(Int32Ty, PPC_FAWORD_CPUID);
llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_fixed_addr_ld);
Value *TheCall = Builder.CreateCall(F, {Op0}, "cpu_is");
return Builder.CreateICmpEQ(TheCall,
llvm::ConstantInt::get(Int32Ty, NumCPUID));
+} else if (Triple.isOSAIX()) {
+ unsigned IsCpuSupport, FieldIdx, CpuIdMask, CpuIdOp, CpuIdValue;
+ typedef std::tuple
+ CPUType;
+ std::tie(IsCpuSupport, FieldIdx, CpuIdMask, CpuIdOp, CpuIdValue) =
+ static_cast(StringSwitch(CPUStr)
+#define PPC_AIX_CPU(NAME, SUPPORT, MASK, INDEX, OP, VALUE)
\
+ .Case(NAME, {SUPPORT, MASK, INDEX, OP, VALUE})
+#include "llvm/TargetParser/PPCTargetParser.def"
+ );
+ return ConvBuiltinCpu(IsCpuSupport, FieldIdx, CpuIdMask, CpuIdOp,
+CpuIdValue);
+}
+LLVM_FALLTHROUGH;
nemanjai wrote:
This is suspicious. Am I reading this right that if we get into the
`__builtin_cpu_is` case and we are compiling for a PPC system that neither
reports itself as AIX nor Linux, we will fall through and emit code for
`__builtin_cpu_supports`?
https://github.com/llvm/llvm-project/pull/80069
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[clang] [clang][PowerPC] Add flag to enable compatibility with GNU for complex arguments (PR #77732)
@@ -2540,6 +2540,10 @@ def ffp_contract : Joined<["-"], "ffp-contract=">, Group, HelpText<"Form fused FP ops (e.g. FMAs)">, Values<"fast,on,off,fast-honor-pragmas">; +def fcomplex_ppc_gnu_abi : Flag<["-"], "fcomplex-ppc-gnu-abi">, Group, Visibility<[ClangOption, CC1Option]>, + DocBrief<"Follow the GNU ABI, store Complex values in GPR instead of stack for PowerPC-32">, nemanjai wrote: Please use "Pass" instead of "Store" as the latter generally refers to storing values in memory and this actually affects parameter passing. https://github.com/llvm/llvm-project/pull/77732 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][PowerPC] Add flag to enable compatibility with GNU for complex arguments (PR #77732)
@@ -78,6 +78,13 @@ class CodeGenOptions : public CodeGenOptionsBase {
SRCK_InRegs// Small structs in registers (-freg-struct-return).
};
+ enum ComplexArgumentConventionKind {
+CMPLX_Default,
+CMPLX_OnStack,
+CMPLX_OnGPR, // if ppc32 -fcomplex-ppc-gnu-abi
nemanjai wrote:
Nit: can we use `In[GF]PR` in the names as "in registers"/"on stack" are in
common usage.
https://github.com/llvm/llvm-project/pull/77732
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[clang] [clang][PowerPC] Add flag to enable compatibility with GNU for complex arguments (PR #77732)
@@ -486,7 +486,8 @@ std::unique_ptr createAIXTargetCodeGenInfo(CodeGenModule &CGM, bool Is64Bit); std::unique_ptr -createPPC32TargetCodeGenInfo(CodeGenModule &CGM, bool SoftFloatABI); +createPPC32TargetCodeGenInfo(CodeGenModule &CGM, bool SoftFloatABI, + unsigned RLen); nemanjai wrote: Please explain this change. It is not clear to me why we're adding this parameter. Are we adding support for 32-bit targets with 64-bit pointers? If so, please justify. Also, this is something that would belong in a separate patch. https://github.com/llvm/llvm-project/pull/77732 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][PowerPC] Add flag to enable compatibility with GNU for complex arguments (PR #77732)
nemanjai wrote: My review is not complete, I just submitted what I have so far so at least we can get started on answering the questions I have so far. https://github.com/llvm/llvm-project/pull/77732 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)
@@ -141,23 +149,30 @@ PPC_LNX_CPU("power10",47)
#define AIX_BUILTIN_PPC_TRUE 1
#define AIX_BUILTIN_PPC_FALSE 0
#define USE_SYS_CONF 2
+ #define SYS_CALL 3
// Supported COMPARE_OP values.
#define COMP_EQ 0
+ #define COMP_GT 1
+ #define COMP_GE 2
+ #define COMP_NE 3
#endif
// The value of SUPPORT_METHOD can be AIX_BUILTIN_PPC_TRUE,
-// AIX_BUILTIN_PPC_FALSE, or USE_SYS_CONF.
-// When the value of SUPPORT_METHOD is USE_SYS_CONF, the return value
-// depends on the result of comparing the data member of
-// _system_configuration specified by INDEX with a certain value.
+// AIX_BUILTIN_PPC_FALSE, USE_SYS_CONF, SYS_CALL.
+// When the value of SUPPORT_METHOD is set to USE_SYS_CONF, the return value
+// depends on comparing VALUE with the specified data member of
+// _system_configuration at INDEX, where the data member is masked by Mask.
+// When the SUPPORT_METHOD value is set to SYS_CALL, the return value depends
+// on comparing a VALUE with the return value of calling `getsystemcfg`
+// with the parameter INDEX, which is then masked by Mask.
nemanjai wrote:
And presumably:
```
// AIX_BUILTIN_PPC_TRUE and AIX_BUILTIN_PPC_FALSE are for features
// that are supported or unsupported on all systems respectively.
```
?
https://github.com/llvm/llvm-project/pull/82809
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[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)
@@ -16570,32 +16570,72 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, #include "llvm/TargetParser/PPCTargetParser.def" auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx, nemanjai wrote: This is now a very large lambda function AFAICT. Please extract it into a static function to aid readability. https://github.com/llvm/llvm-project/pull/82809 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)
@@ -0,0 +1,171 @@
+// RUN: echo "int main() { return __builtin_cpu_supports(\"4xxmac\");}" > %t.c
nemanjai wrote:
This is an interesting way of testing, where we create each test on the fly. I
am not against it if it works on all platforms (including Windows). However, I
would like to see one test case where we have multiple calls to the builtins,
with multiple uses of each "support method" in the same compilation unit.
https://github.com/llvm/llvm-project/pull/82809
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[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)
@@ -141,23 +149,30 @@ PPC_LNX_CPU("power10",47)
#define AIX_BUILTIN_PPC_TRUE 1
#define AIX_BUILTIN_PPC_FALSE 0
#define USE_SYS_CONF 2
+ #define SYS_CALL 3
// Supported COMPARE_OP values.
#define COMP_EQ 0
+ #define COMP_GT 1
+ #define COMP_GE 2
+ #define COMP_NE 3
nemanjai wrote:
Can we not omit this and use `CmpInst::Predicate` in the function-style macros
(thereby eliminating the need for the switch statement that uses them as well)?
https://github.com/llvm/llvm-project/pull/82809
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[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)
@@ -364,7 +364,14 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
// have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
static constexpr int MINIMUM_AIX_OS_MAJOR = 7;
static constexpr int MINIMUM_AIX_OS_MINOR = 2;
- bool supportsCpuSupports() const override { return getTriple().isOSGlibc(); }
+ bool supportsCpuSupports() const override {
nemanjai wrote:
My personal preference is to keep them separate as the added verbosity makes it
very obvious what is being queried.
https://github.com/llvm/llvm-project/pull/82809
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[clang] [RISCV] Emit arch string macro to facilitate ASM programming (PR #85063)
https://github.com/nemanjai created
https://github.com/llvm/llvm-project/pull/85063
In order to make assembly programming more convenient, emit macro
__riscv_cmdline_arch_string that will be defined to the arch string based on
the command line arguments. This string may differ from the actual string that
is added to the object or assembly file. This provides a convenient mechanism
for the programmer to add the .attribute directive into pre-processed asm files.
Example file.S:
.attribute 5, __riscv_cmdline_arch_string
>From ee8d994564e843c889a46f361edb6ca652a0589f Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic
Date: Wed, 13 Mar 2024 12:59:42 +0100
Subject: [PATCH] [RISCV] Emit arch string macro to facilitate ASM programming
In order to make assembly programming more convenient,
emit macro __riscv_cmdline_arch_string that will be defined
to the arch string based on the command line arguments.
This string may differ from the actual string that is
added to the object or assembly file. This provides a
convenient mechanism for the programmer to add the
.attribute directive into pre-processed asm files.
Example file.S:
.attribute 5, __riscv_cmdline_arch_string
---
clang/lib/Basic/Targets/RISCV.cpp | 2 ++
clang/test/Preprocessor/riscv-target-features.c | 8
2 files changed, 10 insertions(+)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..718d94f2d2621e 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -139,6 +139,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions
&Opts,
unsigned MinVLen = ISAInfo->getMinVLen();
unsigned MaxELen = ISAInfo->getMaxELen();
unsigned MaxELenFp = ISAInfo->getMaxELenFp();
+ std::string ArchString = "\"" + ISAInfo->toString() + "\"";
if (CodeModel == "default")
CodeModel = "small";
@@ -222,6 +223,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions
&Opts,
else
Builder.defineMacro("__riscv_32e");
}
+ Builder.defineMacro("__riscv_cmdline_arch_string", ArchString);
}
static constexpr Builtin::Info BuiltinInfo[] = {
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 1a15be1c6e4dc1..6023abe2665c2a 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -185,8 +185,10 @@
// RUN: %clang --target=riscv64-unknown-linux-gnu \
// RUN: -march=rv64ia -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-A-EXT %s
+// CHECK-A-EXT: __INTPTR_WIDTH__ [[WIDTH:[1-9]+]]
// CHECK-A-EXT: __riscv_a 2001000{{$}}
// CHECK-A-EXT: __riscv_atomic 1
+// CHECK-A-EXT: __riscv_cmdline_arch_string "rv[[WIDTH]]i2p1_a2p1"
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ic -E -dM %s \
@@ -203,6 +205,8 @@
// RUN: %clang --target=riscv64-unknown-linux-gnu \
// RUN: -march=rv64ifd -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-D-EXT %s
+// CHECK-D-EXT: __INTPTR_WIDTH__ [[WIDTH:[1-9]+]]
+// CHECK-D-EXT: __riscv_cmdline_arch_string
"rv[[WIDTH]]i2p1_f2p2_d2p2_zicsr2p0"
// CHECK-D-EXT: __riscv_d 2002000{{$}}
// CHECK-D-EXT: __riscv_fdiv 1
// CHECK-D-EXT: __riscv_flen 64
@@ -217,6 +221,8 @@
// CHECK-RV32E: __riscv_32e 1
// CHECK-RV64E: __riscv_64e 1
// CHECK-E-EXT: __riscv_abi_rve 1
+// CHECK-RV32E: __riscv_cmdline_arch_string "rv32e2p0"
+// CHECK-RV64E: __riscv_cmdline_arch_string "rv64e2p0"
// CHECK-E-EXT: __riscv_e 200{{$}}
// RUN: %clang --target=riscv32-unknown-linux-gnu \
@@ -225,6 +231,8 @@
// RUN: %clang --target=riscv64-unknown-linux-gnu \
// RUN: -march=rv64if -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-F-EXT %s
+// CHECK-F-EXT: __INTPTR_WIDTH__ [[WIDTH:[1-9]+]]
+// CHECK-F-EXT: __riscv_cmdline_arch_string "rv[[WIDTH]]i2p1_f2p2_zicsr2p0"
// CHECK-F-EXT: __riscv_f 2002000{{$}}
// CHECK-F-EXT: __riscv_fdiv 1
// CHECK-F-EXT: __riscv_flen 32
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[clang] [DRAFT][RISCV] Emit arch string macro to facilitate ASM programming (PR #85063)
https://github.com/nemanjai edited https://github.com/llvm/llvm-project/pull/85063 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [DRAFT][RISCV] Emit arch string macro to facilitate ASM programming (PR #85063)
nemanjai wrote: This is a suggestion born out of a request from a user to have a way to emit the ISA attributes into objects produced from pre-processed asm files. Perhaps there is already a method to do this that I'm not aware of, but if not, I think this is a convenient and lightweight way to do so. https://github.com/llvm/llvm-project/pull/85063 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)
https://github.com/nemanjai created
https://github.com/llvm/llvm-project/pull/85091
To facilitate proper range checking and better error messages if an attempt is
made to call these with non-litaral arguments, we provide builtins to emit the
read/write CSR instructions.
>From 543086dd6a20852721bd54667196c68011d0e46e Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic
Date: Wed, 13 Mar 2024 15:44:15 +0100
Subject: [PATCH] [RISC-V] Add CSR read/write builtins
To facilitate proper range checking and better error messages
if an attempt is made to call these with non-litaral arguments,
we provide builtins to emit the read/write CSR instructions.
---
clang/include/clang/Basic/BuiltinsRISCV.td| 6 ++
clang/lib/CodeGen/CGBuiltin.cpp | 10 +++
clang/lib/Sema/SemaChecking.cpp | 3 +
.../csr-intrinsics/riscv-zicsr-invalid.c | 25
.../RISCV/csr-intrinsics/riscv-zicsr.c| 63 +++
llvm/include/llvm/IR/IntrinsicsRISCV.td | 15 +
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 17 +
.../test/CodeGen/RISCV/rv32zicsr-intrinsic.ll | 34 ++
.../test/CodeGen/RISCV/rv64zicsr-intrinsic.ll | 34 ++
9 files changed, 207 insertions(+)
create mode 100644
clang/test/CodeGen/RISCV/csr-intrinsics/riscv-zicsr-invalid.c
create mode 100644 clang/test/CodeGen/RISCV/csr-intrinsics/riscv-zicsr.c
create mode 100644 llvm/test/CodeGen/RISCV/rv32zicsr-intrinsic.ll
create mode 100644 llvm/test/CodeGen/RISCV/rv64zicsr-intrinsic.ll
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 4cc89a8a9d8af2..14ef6f9d313a41 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -20,6 +20,12 @@ class RISCVBuiltin :
TargetBuiltin {
let Attributes = [NoThrow, Const] in {
//===--===//
+// Zicsr extension.
+//===--===//
+def csrr : RISCVBuiltin<"unsigned long int(unsigned long int)", "zicsr">;
+def csrw :
+ RISCVBuiltin<"void(unsigned long int, unsigned long int)", "zicsr">;
+//===--===//
// Zbb extension.
//===--===//
def orc_b_32 : RISCVBuiltin<"unsigned int(unsigned int)", "zbb">;
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 93ab465079777b..99486d8aee6f9e 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21379,6 +21379,16 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned
BuiltinID,
llvm::SmallVector IntrinsicTypes;
switch (BuiltinID) {
default: llvm_unreachable("unexpected builtin ID");
+ // Zicsr
+ case RISCV::BI__builtin_riscv_csrr:
+ case RISCV::BI__builtin_riscv_csrw:
+if (IntPtrTy->getScalarSizeInBits() == 32)
+ ID = BuiltinID == RISCV::BI__builtin_riscv_csrr ? Intrinsic::riscv_csrr
+ : Intrinsic::riscv_csrw;
+else
+ ID = BuiltinID == RISCV::BI__builtin_riscv_csrr ? Intrinsic::riscv_csrr64
+ :
Intrinsic::riscv_csrw64;
+break;
case RISCV::BI__builtin_riscv_orc_b_32:
case RISCV::BI__builtin_riscv_orc_b_64:
case RISCV::BI__builtin_riscv_clz_32:
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index a5f42b630c3fa2..637da165c73589 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6223,6 +6223,9 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_mu:
return SemaBuiltinConstantArgRange(TheCall, 4, 0, 4);
+ case RISCV::BI__builtin_riscv_csrr:
+ case RISCV::BI__builtin_riscv_csrw:
+return SemaBuiltinConstantArgRange(TheCall, 0, 0, 4095);
case RISCV::BI__builtin_riscv_ntl_load:
case RISCV::BI__builtin_riscv_ntl_store:
DeclRefExpr *DRE =
diff --git a/clang/test/CodeGen/RISCV/csr-intrinsics/riscv-zicsr-invalid.c
b/clang/test/CodeGen/RISCV/csr-intrinsics/riscv-zicsr-invalid.c
new file mode 100644
index 00..d0420731977d05
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/csr-intrinsics/riscv-zicsr-invalid.c
@@ -0,0 +1,25 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +zicsr %s -fsyntax-only
-verify
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zicsr %s -fsyntax-only
-verify
+// RUN: %clang_cc1 -triple riscv32 %s -fsyntax-only -verify
+
+#ifdef __riscv_zicsr
+unsigned long non_const(unsigned long a) {
+ return __builtin_riscv_csrr(a); // expected-error {{argument to
'__builtin_riscv_csrr' must be a constant integer}}
+}
+
+unsigned lo
[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)
nemanjai wrote: Individual implementations will provide different sets of CSR's and need a way to read/write them. Of course, this can be done with inline asm, but doing such things with inline asm has its limitations (no error checking, if a user attempts to wrap the asm in a function, they won't be able to build code that calls those functions with -O0 as inlining/constant propagation is required, etc.). Providing builtins to do this allows the compiler to do range checking and ensure CSR # is a literal. https://github.com/llvm/llvm-project/pull/85091 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
nemanjai wrote: Sorry, I'll put up a patch for review shortly to fix this problem. https://github.com/llvm/llvm-project/pull/68919 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Preprocessor] Fix __has_builtin for CPU ID functions (PR #80058)
https://github.com/nemanjai created
https://github.com/llvm/llvm-project/pull/80058
My recent commit (67c1c1d) made the CPU ID builtins target-independent so they
can be used on PPC as well. However, that had the unintended consequence of
changing the behaviour of __has_builtin in that it reports these as supported
at the pre-processor level. This makes it impossible to guard the use of these
with this feature test macro which is clearly not ideal.
This patch restores the behaviour of __has_builtin for __builtin_cpu_is,
__builtin_cpu_init,
__builtin_cpu_supports. Now the preprocessor queries the target to determine
whether the target supports the builtin.
>From 85b246ea3882999c9b397e1e30c7656448e63bbf Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic
Date: Tue, 30 Jan 2024 21:39:24 +0100
Subject: [PATCH] [Preprocessor] Fix __has_builtin for CPU ID functions
My recent commit (67c1c1d) made the CPU ID builtins
target-independent so they can be used on PPC as well.
However, that had the unintended consequence of changing
the behaviour of __has_builtin in that it reports these
as supported at the pre-processor level. This makes it
impossible to guard the use of these with this feature
test macro which is clearly not ideal.
This patch restores the behaviour of __has_builtin
for __builtin_cpu_is, __builtin_cpu_init,
__builtin_cpu_supports. Now the preprocessor queries
the target to determine whether the target supports
the builtin.
---
clang/lib/Lex/PPMacroExpansion.cpp | 6 ++
clang/test/Preprocessor/has_builtin_cpuid.c | 20
2 files changed, 26 insertions(+)
create mode 100644 clang/test/Preprocessor/has_builtin_cpuid.c
diff --git a/clang/lib/Lex/PPMacroExpansion.cpp
b/clang/lib/Lex/PPMacroExpansion.cpp
index ad02f31209b0b..3017461dc66e8 100644
--- a/clang/lib/Lex/PPMacroExpansion.cpp
+++ b/clang/lib/Lex/PPMacroExpansion.cpp
@@ -1672,6 +1672,12 @@ void Preprocessor::ExpandBuiltinMacro(Token &Tok) {
return false;
else if (II->getBuiltinID() != 0) {
switch (II->getBuiltinID()) {
+ case Builtin::BI__builtin_cpu_is:
+return getTargetInfo().supportsCpuIs();
+ case Builtin::BI__builtin_cpu_init:
+return getTargetInfo().supportsCpuInit();
+ case Builtin::BI__builtin_cpu_supports:
+return getTargetInfo().supportsCpuSupports();
case Builtin::BI__builtin_operator_new:
case Builtin::BI__builtin_operator_delete:
// denotes date of behavior change to support calling arbitrary
diff --git a/clang/test/Preprocessor/has_builtin_cpuid.c
b/clang/test/Preprocessor/has_builtin_cpuid.c
new file mode 100644
index 0..8de6331e62d6e
--- /dev/null
+++ b/clang/test/Preprocessor/has_builtin_cpuid.c
@@ -0,0 +1,20 @@
+// RUN: %clang_cc1 -fsyntax-only -triple arm64-- -DARM -verify %s
+// RUN: %clang_cc1 -fsyntax-only -triple x86_64-- -DX86 -verify %s
+// RUN: %clang_cc1 -fsyntax-only -triple powerpc64-unknown-linux-gnu -DPPC \
+// RUN: -verify %s
+// expected-no-diagnostics
+#if __has_builtin(__builtin_cpu_is)
+# ifdef ARM
+# error "ARM shouldn't have __builtin_cpu_is"
+# endif
+#endif
+#if __has_builtin(__builtin_cpu_init)
+# if defined(ARM) || defined(PPC)
+# error "ARM/PPC shouldn't have __builtin_cpu_init"
+# endif
+#endif
+#if __has_builtin(__builtin_cpu_supports)
+# ifdef ARM
+# error "ARM shouldn't have __builtin_cpu_supports"
+# endif
+#endif
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
nemanjai wrote: Fix in https://github.com/llvm/llvm-project/pull/80058 https://github.com/llvm/llvm-project/pull/68919 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Preprocessor] Fix __has_builtin for CPU ID functions (PR #80058)
https://github.com/nemanjai closed https://github.com/llvm/llvm-project/pull/80058 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -210,6 +210,15 @@ let TargetPrefix = "ppc" in { // All intrinsics start
with "llvm.ppc.".
[llvm_float_ty],
[llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_vararg_ty],
[IntrNoMem]>;
+ // Load of a value provided by the system library at a fixed address. Used
for
+ // accessing things like HWCAP word provided by GLIBC. The immediate argument
nemanjai wrote:
I'm fine with both of these suggestions.
https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -16086,6 +16086,41 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
switch (BuiltinID) {
default: return nullptr;
+ case Builtin::BI__builtin_cpu_is: {
+const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
+StringRef CPUStr = cast(CPUExpr)->getString();
+unsigned NumCPUID = StringSwitch(CPUStr)
+#define PPC_LNX_CPU(Name, NumericID) .Case(Name, NumericID)
+#include "llvm/TargetParser/PPCTargetParser.def"
+.Default(-1U);
+Value *Op0 = llvm::ConstantInt::get(Int32Ty, PPC_FAWORD_CPUID);
+llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_fixed_addr_ld);
+Value *TheCall = Builder.CreateCall(F, {Op0}, "cpu_is");
+return Builder.CreateICmpEQ(TheCall,
+llvm::ConstantInt::get(Int32Ty, NumCPUID));
+ }
+ case Builtin::BI__builtin_cpu_supports: {
+unsigned FeatureWord;
+unsigned BitMask;
+const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
+StringRef CPUStr = cast(CPUExpr)->getString();
+std::tie(FeatureWord, BitMask) =
+StringSwitch>(CPUStr)
+#define PPC_LNX_FEATURE(Name, Description, EnumName, Bitmask, FA_WORD)
\
+ .Case(Name, {FA_WORD, Bitmask})
+#include "llvm/TargetParser/PPCTargetParser.def"
+.Default({0, 0});
nemanjai wrote:
I think this is a good point. If we somehow have a string argument that would
produce the `default` case and it has made it past Sema checking, it would be
good to crash here rather than produce an invalid call to the intrinsic (or an
invalid mask).
Of course, that assert is not all that friendly and it might be better to
assert within this function.
What do you think about keeping the `default` and adding an assert below such
as:
```
assert(BitMask && "Invalid target feature string. Missed by SemaChecking?");
```
https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -359,6 +359,13 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
bool isSPRegName(StringRef RegName) const override {
return RegName.equals("r1") || RegName.equals("x1");
}
+
+ // We support __builtin_cpu_supports/__builtin_cpu_is on targets that
nemanjai wrote:
We can certainly expand this in a follow-up patch, but since I don't really
have a way to do any functional testing on a musl machine, I'll leave it out of
this patch.
https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
https://github.com/nemanjai updated
https://github.com/llvm/llvm-project/pull/68919
>From 65c84f2ba78efcbf92ce9c8232fc40f493414930 Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic
Date: Thu, 12 Oct 2023 14:08:42 -0400
Subject: [PATCH 1/5] [PowerPC][X86] Make cpu id builtins target independent
and lower for PPC
Make __builtin_cpu_{init|supports|is} target independent and provide
an opt-in query for targets that want to support it. Each target is
still responsible for their specific lowering/code-gen.
Also provide code-gen for PowerPC.
---
clang/include/clang/Basic/Builtins.td | 20 +++
clang/include/clang/Basic/BuiltinsX86.def | 7 -
clang/include/clang/Basic/TargetInfo.h| 6 +
clang/lib/Basic/Targets/PPC.cpp | 14 ++
clang/lib/Basic/Targets/PPC.h | 7 +
clang/lib/Basic/Targets/X86.h | 4 +
clang/lib/CodeGen/CGBuiltin.cpp | 42 +-
clang/lib/Sema/SemaChecking.cpp | 124 +++---
clang/test/CodeGen/builtin-cpu-supports.c | 68 ++
clang/test/Sema/builtin-cpu-supports.c| 8 +-
llvm/include/llvm/IR/IntrinsicsPowerPC.td | 6 +
.../llvm/TargetParser/PPCTargetParser.def | 80 +++
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 4 +
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 33 +
llvm/lib/Target/PowerPC/PPCInstrInfo.td | 3 +
llvm/lib/Target/PowerPC/PPCTargetMachine.h| 3 +
llvm/test/CodeGen/PowerPC/cpu-supports.ll | 111
17 files changed, 458 insertions(+), 82 deletions(-)
create mode 100644 llvm/include/llvm/TargetParser/PPCTargetParser.def
create mode 100644 llvm/test/CodeGen/PowerPC/cpu-supports.ll
diff --git a/clang/include/clang/Basic/Builtins.td
b/clang/include/clang/Basic/Builtins.td
index 22e616e6cde599..1af01fe0d700c9 100644
--- a/clang/include/clang/Basic/Builtins.td
+++ b/clang/include/clang/Basic/Builtins.td
@@ -727,6 +727,26 @@ def RotateRight : BitInt8_16_32_64BuiltinsTemplate,
Builtin {
// FIXME: The builtins marked FunctionWithBuiltinPrefix below should be
//merged with the library definitions. They are currently not because
//the attributes are different.
+
+// Builtins for checking CPU features based on the GCC builtins.
+def BuiltinCPUIs : Builtin {
+ let Spellings = ["__builtin_cpu_is"];
+ let Attributes = [NoThrow, Const];
+ let Prototype = "bool(char const*)";
+}
+
+def BuiltinCPUSupports : Builtin {
+ let Spellings = ["__builtin_cpu_supports"];
+ let Attributes = [NoThrow, Const];
+ let Prototype = "bool(char const*)";
+}
+
+def BuiltinCPUInit : Builtin {
+ let Spellings = ["__builtin_cpu_init"];
+ let Attributes = [NoThrow];
+ let Prototype = "void()";
+}
+
def BuiltinCalloc : Builtin {
let Spellings = ["__builtin_calloc"];
let Attributes = [FunctionWithBuiltinPrefix, NoThrow];
diff --git a/clang/include/clang/Basic/BuiltinsX86.def
b/clang/include/clang/Basic/BuiltinsX86.def
index 60b752ad48548f..207cde0414b54e 100644
--- a/clang/include/clang/Basic/BuiltinsX86.def
+++ b/clang/include/clang/Basic/BuiltinsX86.def
@@ -26,13 +26,6 @@
# define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANG, FEATURE)
BUILTIN(ID, TYPE, ATTRS)
#endif
-// Miscellaneous builtin for checking x86 cpu features.
-// TODO: Make this somewhat generic so that other backends
-// can use it?
-BUILTIN(__builtin_cpu_init, "v", "n")
-BUILTIN(__builtin_cpu_supports, "bcC*", "nc")
-BUILTIN(__builtin_cpu_is, "bcC*", "nc")
-
// Undefined Values
//
TARGET_BUILTIN(__builtin_ia32_undef128, "V2d", "ncV:128:", "")
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 3eb23ebdacf0ed..9432154d5063ce 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1432,6 +1432,12 @@ class TargetInfo : public TransferrableTargetInfo,
getTriple().isOSFreeBSD());
}
+ // Identify whether this target supports __builtin_cpu_supports and
+ // __builtin_cpu_is.
+ virtual bool supportsCpuSupports() const { return false; }
+ virtual bool supportsCpuIs() const { return false; }
+ virtual bool supportsCpuInit() const { return false; }
+
// Validate the contents of the __builtin_cpu_supports(const char*)
// argument.
virtual bool validateCpuSupports(StringRef Name) const { return false; }
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 41935abfb65d3b..2cf1bacd95fd95 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -878,3 +878,17 @@ ArrayRef PPCTargetInfo::getTargetBuiltins()
const {
return llvm::ArrayRef(BuiltinInfo,
clang::PPC::LastTSBuiltin - Builtin::FirstTSBuiltin);
}
+
+bool PPCTargetInfo::validateCpuSupports(StringRef FeatureStr) const {
+#define PPC_FEATURE(NAME, DESC, ENUMNAME, ENUMVAL, HWCAPN) .Case(NAME, true)
+ return llvm::StringSwitch(FeatureStr)
+#include "llv
[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S,
SourceLocation Loc,
return false;
}
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI,
+ const TargetInfo *AuxTI, CallExpr *TheCall)
{
nemanjai wrote:
Turns out this is actually needed. There is a test that builds with `-triple
aarch64 -aux-triple x86_64`. I will have to put the AUX target checks back.
https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
https://github.com/nemanjai updated
https://github.com/llvm/llvm-project/pull/68919
>From 71f1352bf00d6a9eefa3f199859d47d093f272f8 Mon Sep 17 00:00:00 2001
From: Nemanja Ivanovic
Date: Thu, 12 Oct 2023 14:08:42 -0400
Subject: [PATCH 1/4] [PowerPC][X86] Make cpu id builtins target independent
and lower for PPC
Make __builtin_cpu_{init|supports|is} target independent and provide
an opt-in query for targets that want to support it. Each target is
still responsible for their specific lowering/code-gen.
Also provide code-gen for PowerPC.
---
clang/include/clang/Basic/Builtins.def| 5 +
clang/include/clang/Basic/BuiltinsX86.def | 7 -
clang/include/clang/Basic/TargetInfo.h| 6 +
clang/lib/Basic/Targets/PPC.cpp | 14 ++
clang/lib/Basic/Targets/PPC.h | 7 +
clang/lib/Basic/Targets/X86.h | 4 +
clang/lib/CodeGen/CGBuiltin.cpp | 42 +-
clang/lib/Sema/SemaChecking.cpp | 124 +++---
clang/test/CodeGen/builtin-cpu-supports.c | 68 ++
clang/test/Sema/builtin-cpu-supports.c| 8 +-
llvm/include/llvm/IR/IntrinsicsPowerPC.td | 6 +
.../llvm/TargetParser/PPCTargetParser.def | 80 +++
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 4 +
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 33 +
llvm/lib/Target/PowerPC/PPCInstrInfo.td | 3 +
llvm/lib/Target/PowerPC/PPCTargetMachine.h| 3 +
llvm/test/CodeGen/PowerPC/cpu-supports.ll | 111
17 files changed, 443 insertions(+), 82 deletions(-)
create mode 100644 llvm/include/llvm/TargetParser/PPCTargetParser.def
create mode 100644 llvm/test/CodeGen/PowerPC/cpu-supports.ll
diff --git a/clang/include/clang/Basic/Builtins.def
b/clang/include/clang/Basic/Builtins.def
index 6ea8484606cfd5..5e1f4088ff63f8 100644
--- a/clang/include/clang/Basic/Builtins.def
+++ b/clang/include/clang/Basic/Builtins.def
@@ -118,6 +118,11 @@
# define LANGBUILTIN(ID, TYPE, ATTRS, BUILTIN_LANG) BUILTIN(ID, TYPE, ATTRS)
#endif
+// Builtins for checking CPU features based on the GCC builtins.
+BUILTIN(__builtin_cpu_supports, "bcC*", "nc")
+BUILTIN(__builtin_cpu_is, "bcC*", "nc")
+BUILTIN(__builtin_cpu_init, "v", "n")
+
// Standard libc/libm functions:
BUILTIN(__builtin_atan2 , "ddd" , "Fne")
BUILTIN(__builtin_atan2f, "fff" , "Fne")
diff --git a/clang/include/clang/Basic/BuiltinsX86.def
b/clang/include/clang/Basic/BuiltinsX86.def
index e4802f8ab1c156..2acc5ce0f4a365 100644
--- a/clang/include/clang/Basic/BuiltinsX86.def
+++ b/clang/include/clang/Basic/BuiltinsX86.def
@@ -26,13 +26,6 @@
# define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANG, FEATURE)
BUILTIN(ID, TYPE, ATTRS)
#endif
-// Miscellaneous builtin for checking x86 cpu features.
-// TODO: Make this somewhat generic so that other backends
-// can use it?
-BUILTIN(__builtin_cpu_init, "v", "n")
-BUILTIN(__builtin_cpu_supports, "bcC*", "nc")
-BUILTIN(__builtin_cpu_is, "bcC*", "nc")
-
// Undefined Values
//
TARGET_BUILTIN(__builtin_ia32_undef128, "V2d", "ncV:128:", "")
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 9d56e97a3d4bb8..3d83b387aac093 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1415,6 +1415,12 @@ class TargetInfo : public TransferrableTargetInfo,
getTriple().isOSFreeBSD());
}
+ // Identify whether this target supports __builtin_cpu_supports and
+ // __builtin_cpu_is.
+ virtual bool supportsCpuSupports() const { return false; }
+ virtual bool supportsCpuIs() const { return false; }
+ virtual bool supportsCpuInit() const { return false; }
+
// Validate the contents of the __builtin_cpu_supports(const char*)
// argument.
virtual bool validateCpuSupports(StringRef Name) const { return false; }
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 0d87a3a4e8c20f..d8759c86c9932c 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -873,3 +873,17 @@ ArrayRef PPCTargetInfo::getTargetBuiltins()
const {
return llvm::ArrayRef(BuiltinInfo,
clang::PPC::LastTSBuiltin - Builtin::FirstTSBuiltin);
}
+
+bool PPCTargetInfo::validateCpuSupports(StringRef FeatureStr) const {
+#define PPC_FEATURE(NAME, DESC, ENUMNAME, ENUMVAL, HWCAPN) .Case(NAME, true)
+ return llvm::StringSwitch(FeatureStr)
+#include "llvm/TargetParser/PPCTargetParser.def"
+ .Default(false);
+}
+
+bool PPCTargetInfo::validateCpuIs(StringRef CPUName) const {
+#define PPC_CPU(NAME, NUM) .Case(NAME, true)
+ return llvm::StringSwitch(CPUName)
+#include "llvm/TargetParser/PPCTargetParser.def"
+ .Default(false);
+}
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 4d62673ba7fb8c..f700b625b79030 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -359,6 +359,13 @@ class LL
[clang] 3bc3983 - Fix bot failure after ccb4124a4172
Author: Nemanja Ivanovic
Date: 2020-09-15T12:36:47-05:00
New Revision: 3bc3983f229f9277d5bea3692b691f72ab8740dd
URL:
https://github.com/llvm/llvm-project/commit/3bc3983f229f9277d5bea3692b691f72ab8740dd
DIFF:
https://github.com/llvm/llvm-project/commit/3bc3983f229f9277d5bea3692b691f72ab8740dd.diff
LOG: Fix bot failure after ccb4124a4172
The test case has a check line for the option on a line that includes
the string lld surrounded by any characters. This causes failures
when said string is in the build path. What the test case presumably
means to test is the actual invocation of the LLD linker (i.e. a
linker that has that string as a suffix). This patch simply removes
the erroneous wildcard after the string.
Added:
Modified:
clang/test/Driver/hip-gz-options.hip
Removed:
diff --git a/clang/test/Driver/hip-gz-options.hip
b/clang/test/Driver/hip-gz-options.hip
index b2544a42ebed..705c1be7b94e 100644
--- a/clang/test/Driver/hip-gz-options.hip
+++ b/clang/test/Driver/hip-gz-options.hip
@@ -9,6 +9,6 @@
// RUN: -ggdb -gz=zlib 2>&1 | FileCheck %s
// CHECK-DAG: {{".*clang.*" .* "--compress-debug-sections=zlib"}}
-// CHECK-DAG: {{".*lld.*" .* "--compress-debug-sections=zlib"}}
+// CHECK-DAG: {{".*lld" .* "--compress-debug-sections=zlib"}}
// CHECK-DAG: {{".*clang.*" .* "--compress-debug-sections=zlib"}}
// CHECK: "--compress-debug-sections=zlib"
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[clang] 54205f0 - [PowerPC] Allow const pointers for load builtins in altivec.h
Author: Nemanja Ivanovic
Date: 2020-09-04T13:56:39-04:00
New Revision: 54205f0bd2377503b818d7f62cc4ed63ef5b1e94
URL:
https://github.com/llvm/llvm-project/commit/54205f0bd2377503b818d7f62cc4ed63ef5b1e94
DIFF:
https://github.com/llvm/llvm-project/commit/54205f0bd2377503b818d7f62cc4ed63ef5b1e94.diff
LOG: [PowerPC] Allow const pointers for load builtins in altivec.h
The load builtins in altivec.h do not have const in the signature
for the pointer parameter. This prevents using them for loading
from constant pointers. A notable case for such a use is Eigen.
This patch simply adds the missing const.
Fixes: https://bugs.llvm.org/show_bug.cgi?id=47408
Added:
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-altivec.c
clang/test/CodeGen/builtins-ppc-p10vector.c
clang/test/CodeGen/builtins-ppc-xl-xst.c
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 47119d702683..9fda383074f6 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -2702,67 +2702,67 @@ vec_insert_exp(vector unsigned int __a, vector unsigned
int __b) {
}
#if defined(__powerpc64__)
-static __inline__ vector signed char __ATTRS_o_ai vec_xl_len(signed char *__a,
+static __inline__ vector signed char __ATTRS_o_ai vec_xl_len(const signed char
*__a,
size_t __b) {
return (vector signed char)__builtin_vsx_lxvl(__a, (__b << 56));
}
static __inline__ vector unsigned char __ATTRS_o_ai
-vec_xl_len(unsigned char *__a, size_t __b) {
+vec_xl_len(const unsigned char *__a, size_t __b) {
return (vector unsigned char)__builtin_vsx_lxvl(__a, (__b << 56));
}
-static __inline__ vector signed short __ATTRS_o_ai vec_xl_len(signed short
*__a,
+static __inline__ vector signed short __ATTRS_o_ai vec_xl_len(const signed
short *__a,
size_t __b) {
return (vector signed short)__builtin_vsx_lxvl(__a, (__b << 56));
}
static __inline__ vector unsigned short __ATTRS_o_ai
-vec_xl_len(unsigned short *__a, size_t __b) {
+vec_xl_len(const unsigned short *__a, size_t __b) {
return (vector unsigned short)__builtin_vsx_lxvl(__a, (__b << 56));
}
-static __inline__ vector signed int __ATTRS_o_ai vec_xl_len(signed int *__a,
+static __inline__ vector signed int __ATTRS_o_ai vec_xl_len(const signed int
*__a,
size_t __b) {
return (vector signed int)__builtin_vsx_lxvl(__a, (__b << 56));
}
-static __inline__ vector unsigned int __ATTRS_o_ai vec_xl_len(unsigned int
*__a,
+static __inline__ vector unsigned int __ATTRS_o_ai vec_xl_len(const unsigned
int *__a,
size_t __b) {
return (vector unsigned int)__builtin_vsx_lxvl(__a, (__b << 56));
}
-static __inline__ vector float __ATTRS_o_ai vec_xl_len(float *__a, size_t __b)
{
+static __inline__ vector float __ATTRS_o_ai vec_xl_len(const float *__a,
size_t __b) {
return (vector float)__builtin_vsx_lxvl(__a, (__b << 56));
}
static __inline__ vector signed __int128 __ATTRS_o_ai
-vec_xl_len(signed __int128 *__a, size_t __b) {
+vec_xl_len(const signed __int128 *__a, size_t __b) {
return (vector signed __int128)__builtin_vsx_lxvl(__a, (__b << 56));
}
static __inline__ vector unsigned __int128 __ATTRS_o_ai
-vec_xl_len(unsigned __int128 *__a, size_t __b) {
+vec_xl_len(const unsigned __int128 *__a, size_t __b) {
return (vector unsigned __int128)__builtin_vsx_lxvl(__a, (__b << 56));
}
static __inline__ vector signed long long __ATTRS_o_ai
-vec_xl_len(signed long long *__a, size_t __b) {
+vec_xl_len(const signed long long *__a, size_t __b) {
return (vector signed long long)__builtin_vsx_lxvl(__a, (__b << 56));
}
static __inline__ vector unsigned long long __ATTRS_o_ai
-vec_xl_len(unsigned long long *__a, size_t __b) {
+vec_xl_len(const unsigned long long *__a, size_t __b) {
return (vector unsigned long long)__builtin_vsx_lxvl(__a, (__b << 56));
}
-static __inline__ vector double __ATTRS_o_ai vec_xl_len(double *__a,
+static __inline__ vector double __ATTRS_o_ai vec_xl_len(const double *__a,
size_t __b) {
return (vector double)__builtin_vsx_lxvl(__a, (__b << 56));
}
static __inline__ vector unsigned char __ATTRS_o_ai
-vec_xl_len_r(unsigned char *__a, size_t __b) {
+vec_xl_len_r(const unsigned char *__a, size_t __b) {
vector unsigned char __res =
(vector unsigned char)__builtin_vsx_lxvll(__a, (__b << 56));
#ifdef __LITTLE_ENDIAN__
@@ -16447,41 +16447,41 @@ typedef vector unsigned int unaligned_vec_uint
__attribute__((aligned(1)));
typedef vector float unaligned_vec_float __attribute__((aligned(1)));
static inline __ATTRS_o_ai vector signed char vec_xl(signed long lon
[clang] 2d65294 - [PowerPC] Provide vec_cmpne on pre-Power9 architectures in altivec.h
Author: Nemanja Ivanovic
Date: 2020-09-04T21:48:38-04:00
New Revision: 2d652949be4b772f2c11577621b0ad33052ac844
URL:
https://github.com/llvm/llvm-project/commit/2d652949be4b772f2c11577621b0ad33052ac844
DIFF:
https://github.com/llvm/llvm-project/commit/2d652949be4b772f2c11577621b0ad33052ac844.diff
LOG: [PowerPC] Provide vec_cmpne on pre-Power9 architectures in altivec.h
These overloads are listed in appendix A of the ELFv2 ABI specification
without a requirement for ISA 3.0. So these need to be available on
all Altivec-capable architectures. The implementation in altivec.h
erroneously had them guarded for Power9 due to the availability of
the VCMPNE[BHW] instructions. However these need to be implemented
in terms of the VCMPEQ[BHW] instructions on older architectures.
Fixes: https://bugs.llvm.org/show_bug.cgi?id=47423
Added:
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-altivec.c
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 9fda383074f6..a7c4fd23ef19 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -1766,36 +1766,12 @@ vec_cmpne(vector unsigned int __a, vector unsigned int
__b) {
(vector int)__b);
}
-static __inline__ vector bool long long __ATTRS_o_ai
-vec_cmpne(vector bool long long __a, vector bool long long __b) {
- return (vector bool long long)
-~(__builtin_altivec_vcmpequd((vector long long)__a, (vector long
long)__b));
-}
-
-static __inline__ vector bool long long __ATTRS_o_ai
-vec_cmpne(vector signed long long __a, vector signed long long __b) {
- return (vector bool long long)
-~(__builtin_altivec_vcmpequd((vector long long)__a, (vector long
long)__b));
-}
-
-static __inline__ vector bool long long __ATTRS_o_ai
-vec_cmpne(vector unsigned long long __a, vector unsigned long long __b) {
- return (vector bool long long)
-~(__builtin_altivec_vcmpequd((vector long long)__a, (vector long
long)__b));
-}
-
static __inline__ vector bool int __ATTRS_o_ai
vec_cmpne(vector float __a, vector float __b) {
return (vector bool int)__builtin_altivec_vcmpnew((vector int)__a,
(vector int)__b);
}
-static __inline__ vector bool long long __ATTRS_o_ai
-vec_cmpne(vector double __a, vector double __b) {
- return (vector bool long long)
-~(__builtin_altivec_vcmpequd((vector long long)__a, (vector long
long)__b));
-}
-
/* vec_cmpnez */
static __inline__ vector bool char __ATTRS_o_ai
@@ -1900,6 +1876,86 @@ vec_parity_lsbb(vector signed long long __a) {
return __builtin_altivec_vprtybd(__a);
}
+#else
+/* vec_cmpne */
+
+static __inline__ vector bool char __ATTRS_o_ai
+vec_cmpne(vector bool char __a, vector bool char __b) {
+ return ~(vec_cmpeq(__a, __b));
+}
+
+static __inline__ vector bool char __ATTRS_o_ai
+vec_cmpne(vector signed char __a, vector signed char __b) {
+ return ~(vec_cmpeq(__a, __b));
+}
+
+static __inline__ vector bool char __ATTRS_o_ai
+vec_cmpne(vector unsigned char __a, vector unsigned char __b) {
+ return ~(vec_cmpeq(__a, __b));
+}
+
+static __inline__ vector bool short __ATTRS_o_ai
+vec_cmpne(vector bool short __a, vector bool short __b) {
+ return ~(vec_cmpeq(__a, __b));
+}
+
+static __inline__ vector bool short __ATTRS_o_ai
+vec_cmpne(vector signed short __a, vector signed short __b) {
+ return ~(vec_cmpeq(__a, __b));
+}
+
+static __inline__ vector bool short __ATTRS_o_ai
+vec_cmpne(vector unsigned short __a, vector unsigned short __b) {
+ return ~(vec_cmpeq(__a, __b));
+}
+
+static __inline__ vector bool int __ATTRS_o_ai
+vec_cmpne(vector bool int __a, vector bool int __b) {
+ return ~(vec_cmpeq(__a, __b));
+}
+
+static __inline__ vector bool int __ATTRS_o_ai
+vec_cmpne(vector signed int __a, vector signed int __b) {
+ return ~(vec_cmpeq(__a, __b));
+}
+
+static __inline__ vector bool int __ATTRS_o_ai
+vec_cmpne(vector unsigned int __a, vector unsigned int __b) {
+ return ~(vec_cmpeq(__a, __b));
+}
+
+static __inline__ vector bool int __ATTRS_o_ai
+vec_cmpne(vector float __a, vector float __b) {
+ return ~(vec_cmpeq(__a, __b));
+}
+#endif
+
+#ifdef __POWER8_VECTOR__
+static __inline__ vector bool long long __ATTRS_o_ai
+vec_cmpne(vector bool long long __a, vector bool long long __b) {
+ return (vector bool long long)
+~(__builtin_altivec_vcmpequd((vector long long)__a, (vector long
long)__b));
+}
+
+static __inline__ vector bool long long __ATTRS_o_ai
+vec_cmpne(vector signed long long __a, vector signed long long __b) {
+ return (vector bool long long)
+~(__builtin_altivec_vcmpequd((vector long long)__a, (vector long
long)__b));
+}
+
+static __inline__ vector bool long long __ATTRS_o_ai
+vec_cmpne(vector unsigned long long __a, vector unsigned long long __b) {
+ return (vector bool long long)
+~(__builtin_altivec_vcmpe
[clang] 39e4676 - [PowerPC] Provide doubleword vector predicate form comparisons on Power7
Author: Nemanja Ivanovic
Date: 2021-05-13T04:56:56-05:00
New Revision: 39e4676ca798d9aba58823515ac9d48eb64863be
URL:
https://github.com/llvm/llvm-project/commit/39e4676ca798d9aba58823515ac9d48eb64863be
DIFF:
https://github.com/llvm/llvm-project/commit/39e4676ca798d9aba58823515ac9d48eb64863be.diff
LOG: [PowerPC] Provide doubleword vector predicate form comparisons on Power7
There are two reasons this shouldn't be restricted to Power8 and up:
1. For XL compatibility
2. Because clang will expand comparison operators to these intrinsics*
*Without this patch, the following causes a selection error:
int test(vector signed long a, vector signed long b) {
return a < b;
}
This patch provides the handling for the intrinsics in the back
end and removes the Power8 guards from the predicate functions
(vec_{all|any}_{eq|ne|gt|ge|lt|le}).
Added:
llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p8vector.c
clang/test/CodeGen/builtins-ppc-vsx.c
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrVSX.td
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index e28d234880fbb..25c1b1de998df 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -14790,7 +14790,7 @@ static __inline__ int __ATTRS_o_ai vec_all_eq(vector
bool int __a,
(vector int)__b);
}
-#ifdef __POWER8_VECTOR__
+#ifdef __VSX__
static __inline__ int __ATTRS_o_ai vec_all_eq(vector signed long long __a,
vector signed long long __b) {
return __builtin_altivec_vcmpequd_p(__CR6_LT, __a, __b);
@@ -14974,7 +14974,7 @@ static __inline__ int __ATTRS_o_ai vec_all_ge(vector
bool int __a,
(vector unsigned int)__a);
}
-#ifdef __POWER8_VECTOR__
+#ifdef __VSX__
static __inline__ int __ATTRS_o_ai vec_all_ge(vector signed long long __a,
vector signed long long __b) {
return __builtin_altivec_vcmpgtsd_p(__CR6_EQ, __b, __a);
@@ -15157,7 +15157,7 @@ static __inline__ int __ATTRS_o_ai vec_all_gt(vector
bool int __a,
(vector unsigned int)__b);
}
-#ifdef __POWER8_VECTOR__
+#ifdef __VSX__
static __inline__ int __ATTRS_o_ai vec_all_gt(vector signed long long __a,
vector signed long long __b) {
return __builtin_altivec_vcmpgtsd_p(__CR6_LT, __a, __b);
@@ -15347,7 +15347,7 @@ static __inline__ int __ATTRS_o_ai vec_all_le(vector
bool int __a,
(vector unsigned int)__b);
}
-#ifdef __POWER8_VECTOR__
+#ifdef __VSX__
static __inline__ int __ATTRS_o_ai vec_all_le(vector signed long long __a,
vector signed long long __b) {
return __builtin_altivec_vcmpgtsd_p(__CR6_EQ, __a, __b);
@@ -15531,7 +15531,7 @@ static __inline__ int __ATTRS_o_ai vec_all_lt(vector
bool int __a,
(vector unsigned int)__a);
}
-#ifdef __POWER8_VECTOR__
+#ifdef __VSX__
static __inline__ int __ATTRS_o_ai vec_all_lt(vector signed long long __a,
vector signed long long __b) {
return __builtin_altivec_vcmpgtsd_p(__CR6_LT, __b, __a);
@@ -15746,7 +15746,7 @@ static __inline__ int __ATTRS_o_ai vec_all_ne(vector
bool int __a,
(vector int)__b);
}
-#ifdef __POWER8_VECTOR__
+#ifdef __VSX__
static __inline__ int __ATTRS_o_ai vec_all_ne(vector signed long long __a,
vector signed long long __b) {
return __builtin_altivec_vcmpequd_p(__CR6_EQ, __a, __b);
@@ -16035,7 +16035,7 @@ static __inline__ int __ATTRS_o_ai vec_any_eq(vector
bool int __a,
(vector int)__b);
}
-#ifdef __POWER8_VECTOR__
+#ifdef __VSX__
static __inline__ int __ATTRS_o_ai vec_any_eq(vector signed long long __a,
vector signed long long __b) {
return __builtin_altivec_vcmpequd_p(__CR6_EQ_REV, __a, __b);
@@ -16225,7 +16225,7 @@ static __inline__ int __ATTRS_o_ai vec_any_ge(vector
bool int __a,
(vector unsigned int)__a);
}
-#ifdef __POWER8_VECTOR__
+#ifdef __VSX__
static __inline__ int __ATTRS_o_ai vec_any_ge(vector signed long long __a,
vector signed long long __b) {
return __builtin_altivec_vcmpgtsd_p(__CR6_LT_REV, __b, __a);
@@ -16416,7 +16416,7 @@ static __inline__ int __ATTRS_o_ai vec_any_gt(vector
bool int __a,
(vector unsigned int)__b);
}
-#ifdef __POWER8_VECTOR__
+#ifdef __VSX__
static __inline__ int __ATTRS_o_ai vec_any_gt(vector s
[clang] 7cd2833 - [PowerPC] Add vec_vupkhpx and vec_vupklpx for XL compatibility
Author: Nemanja Ivanovic
Date: 2021-05-14T08:02:00-05:00
New Revision: 7cd2833311ab614775bc695e7bb808159a02e2a9
URL:
https://github.com/llvm/llvm-project/commit/7cd2833311ab614775bc695e7bb808159a02e2a9
DIFF:
https://github.com/llvm/llvm-project/commit/7cd2833311ab614775bc695e7bb808159a02e2a9.diff
LOG: [PowerPC] Add vec_vupkhpx and vec_vupklpx for XL compatibility
These are old names for these functions that XL still supports.
Added:
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-altivec.c
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 25c1b1de998df..dadf6b5cf75bb 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -12520,6 +12520,13 @@ vec_vrfiz(vector float __a) {
/* The vector unpack instructions all have a big-endian bias, so for
little endian we must reverse the meanings of "high" and "low." */
+#ifdef __LITTLE_ENDIAN__
+#define vec_vupkhpx(__a) __builtin_altivec_vupklpx((vector short)(__a))
+#define vec_vupklpx(__a) __builtin_altivec_vupkhpx((vector short)(__a))
+#else
+#define vec_vupkhpx(__a) __builtin_altivec_vupkhpx((vector short)(__a))
+#define vec_vupklpx(__a) __builtin_altivec_vupklpx((vector short)(__a))
+#endif
static __inline__ vector short __ATTRS_o_ai
vec_unpackh(vector signed char __a) {
diff --git a/clang/test/CodeGen/builtins-ppc-altivec.c
b/clang/test/CodeGen/builtins-ppc-altivec.c
index e7593ca9021cf..8edef9806af22 100644
--- a/clang/test/CodeGen/builtins-ppc-altivec.c
+++ b/clang/test/CodeGen/builtins-ppc-altivec.c
@@ -5788,6 +5788,10 @@ void test6() {
res_vui = vec_unpackh(vp);
// CHECK: @llvm.ppc.altivec.vupkhpx
+// CHECK-LE: @llvm.ppc.altivec.vupklpx
+
+ res_vui = vec_vupkhpx(vp);
+// CHECK: @llvm.ppc.altivec.vupkhpx
// CHECK-LE: @llvm.ppc.altivec.vupklpx
res_vs = vec_vupkhsb(vsc);
@@ -5829,6 +5833,10 @@ void test6() {
res_vui = vec_unpackl(vp);
// CHECK: @llvm.ppc.altivec.vupklpx
+// CHECK-LE: @llvm.ppc.altivec.vupkhpx
+
+ res_vui = vec_vupklpx(vp);
+// CHECK: @llvm.ppc.altivec.vupklpx
// CHECK-LE: @llvm.ppc.altivec.vupkhpx
res_vs = vec_vupklsb(vsc);
___
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[clang] 76d845c - [clang-format] Fix unittest failures with -Werror
Author: Nemanja Ivanovic
Date: 2021-09-23T18:24:39-05:00
New Revision: 76d845cb169f048cb6f2176c3e7a6534dc5af097
URL:
https://github.com/llvm/llvm-project/commit/76d845cb169f048cb6f2176c3e7a6534dc5af097
DIFF:
https://github.com/llvm/llvm-project/commit/76d845cb169f048cb6f2176c3e7a6534dc5af097.diff
LOG: [clang-format] Fix unittest failures with -Werror
Commit a44ab1702539 added a unit test that fails to build with
-Werror which causes build bot breaks on bots that include that
option in their build. This patch just adds the necessary casts to
silence the warnings.
Added:
Modified:
clang/unittests/Format/QualifierFixerTest.cpp
Removed:
diff --git a/clang/unittests/Format/QualifierFixerTest.cpp
b/clang/unittests/Format/QualifierFixerTest.cpp
index 1bb1792113049..0592cef1eaae5 100755
--- a/clang/unittests/Format/QualifierFixerTest.cpp
+++ b/clang/unittests/Format/QualifierFixerTest.cpp
@@ -554,7 +554,7 @@ TEST_F(QualifierFixerTest, ConstVolatileQualifiersOrder) {
Style.QualifierOrder = {"inline", "static", "const", "volatile", "type"};
// The Default
- EXPECT_EQ(Style.QualifierOrder.size(), 5);
+ EXPECT_EQ(Style.QualifierOrder.size(), (size_t)5);
verifyFormat("const volatile int a;", "const volatile int a;", Style);
verifyFormat("const volatile int a;", "volatile const int a;", Style);
@@ -603,7 +603,7 @@ TEST_F(QualifierFixerTest, InlineStatics) {
FormatStyle Style = getLLVMStyle();
Style.QualifierAlignment = FormatStyle::QAS_Left;
Style.QualifierOrder = {"inline", "static", "const", "volatile", "type"};
- EXPECT_EQ(Style.QualifierOrder.size(), 5);
+ EXPECT_EQ(Style.QualifierOrder.size(), (size_t)5);
verifyFormat("inline static const volatile int a;",
"const inline static volatile int a;", Style);
@@ -621,7 +621,7 @@ TEST_F(QualifierFixerTest, AmpEqual) {
FormatStyle Style = getLLVMStyle();
Style.QualifierAlignment = FormatStyle::QAS_Custom;
Style.QualifierOrder = {"static", "type", "const"};
- EXPECT_EQ(Style.QualifierOrder.size(), 3);
+ EXPECT_EQ(Style.QualifierOrder.size(), (size_t)3);
verifyFormat("foo(std::string const & = std::string()) const",
"foo(const std::string & = std::string()) const", Style);
@@ -634,7 +634,7 @@ TEST_F(QualifierFixerTest, MoveConstBeyondTypeSmall) {
FormatStyle Style = getLLVMStyle();
Style.QualifierAlignment = FormatStyle::QAS_Custom;
Style.QualifierOrder = {"type", "const"};
- EXPECT_EQ(Style.QualifierOrder.size(), 2);
+ EXPECT_EQ(Style.QualifierOrder.size(), (size_t)2);
verifyFormat("int const a;", "const int a;", Style);
verifyFormat("int const *a;", "const int*a;", Style);
@@ -648,7 +648,7 @@ TEST_F(QualifierFixerTest, MoveConstBeforeTypeSmall) {
FormatStyle Style = getLLVMStyle();
Style.QualifierAlignment = FormatStyle::QAS_Custom;
Style.QualifierOrder = {"const", "type"};
- EXPECT_EQ(Style.QualifierOrder.size(), 2);
+ EXPECT_EQ(Style.QualifierOrder.size(), (size_t)2);
verifyFormat("const int a;", "int const a;", Style);
verifyFormat("const int *a;", "int const *a;", Style);
@@ -670,7 +670,7 @@ TEST_F(QualifierFixerTest, MoveConstBeyondType) {
FormatStyle Style = getLLVMStyle();
Style.QualifierAlignment = FormatStyle::QAS_Custom;
Style.QualifierOrder = {"static", "inline", "type", "const", "volatile"};
- EXPECT_EQ(Style.QualifierOrder.size(), 5);
+ EXPECT_EQ(Style.QualifierOrder.size(), (size_t)5);
verifyFormat("static inline int const volatile a;",
"const inline static volatile int a;", Style);
@@ -698,8 +698,8 @@ TEST_F(QualifierFixerTest, PrepareLeftRightOrdering) {
QualifierAlignmentFixer::PrepareLeftRightOrdering(Style.QualifierOrder, Left,
Right, ConfiguredTokens);
- EXPECT_EQ(Left.size(), 2);
- EXPECT_EQ(Right.size(), 2);
+ EXPECT_EQ(Left.size(), (size_t)2);
+ EXPECT_EQ(Right.size(), (size_t)2);
std::vector LeftResult = {"inline", "static"};
std::vector RightResult = {"const", "volatile"};
___
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[clang] c9539f9 - [PowerPC] Define XL-compatible macros only for AIX and Linux
Author: Nemanja Ivanovic
Date: 2021-09-29T06:14:45-05:00
New Revision: c9539f957f57c0c2c59dab98f25215f241d4debf
URL:
https://github.com/llvm/llvm-project/commit/c9539f957f57c0c2c59dab98f25215f241d4debf
DIFF:
https://github.com/llvm/llvm-project/commit/c9539f957f57c0c2c59dab98f25215f241d4debf.diff
LOG: [PowerPC] Define XL-compatible macros only for AIX and Linux
Since XLC only ever shipped on PowerPC AIX and Linux, it is not reasonable to
provide the compatibility macros on any target other than those two. This patch
restricts those macros to AIX/Linux.
Differential revision: https://reviews.llvm.org/D110213
Added:
Modified:
clang/lib/Basic/Targets/PPC.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
clang/test/CodeGen/builtins-ppc-xlcompat-cipher.c
clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
clang/test/CodeGen/builtins-ppc-xlcompat-compare.c
clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-expect.c
clang/test/CodeGen/builtins-ppc-xlcompat-fetch.c
clang/test/CodeGen/builtins-ppc-xlcompat-fp.c
clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
clang/test/CodeGen/builtins-ppc-xlcompat-macros.c
clang/test/CodeGen/builtins-ppc-xlcompat-math.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
clang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c
clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
clang/test/CodeGen/builtins-ppc-xlcompat-test.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
clang/test/CodeGen/builtins-ppc-xlcompat-vec-error.c
clang/test/CodeGen/builtins-ppc-xlcompat.c
Removed:
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 8ada8c5106b31..4835f1d816741 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -250,7 +250,10 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
- defineXLCompatMacros(Builder);
+ // We define the XLC compatibility macros only on AIX and Linux since XLC
+ // was never available on any other platforms.
+ if (getTriple().isOSAIX() || getTriple().isOSLinux())
+defineXLCompatMacros(Builder);
// Target identification.
Builder.defineMacro("__ppc__");
diff --git
a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
index f305166f2b088..81bf4d54db025 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
@@ -3,9 +3,9 @@
// RUN: FileCheck %s --check-prefix=CHECK32-ERROR
// RUN: %clang_cc1 -O2 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \
// RUN: FileCheck %s --check-prefix=CHECK64
-// RUN: %clang_cc1 -O2 -triple=powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN: %clang_cc1 -O2 -triple=powerpc64le-unknown-linux-gnu -emit-llvm %s \
// RUN: -o - | FileCheck %s --check-prefix=CHECK64
-// RUN: %clang_cc1 -O2 -triple=powerpc64-unknown-unknown -emit-llvm %s \
+// RUN: %clang_cc1 -O2 -triple=powerpc64-unknown-linux-gnu -emit-llvm %s \
// RUN: -o - | FileCheck %s --check-prefix=CHECK64
long test_ldarx(volatile long* a) {
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
index 22c668f73f3d9..7c898f523dc85 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -3,9 +3,9 @@
// RUN: -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -O2 -target-cpu pwr8 -triple=powerpc64-unknown-aix \
// RUN: -e
[clang] 09b67aa - [PowerPC] Implement builtin for vbpermd
Author: Nemanja Ivanovic
Date: 2021-09-29T06:34:31-05:00
New Revision: 09b67aa1c38279daa54246e3f216186e35a3e5b9
URL:
https://github.com/llvm/llvm-project/commit/09b67aa1c38279daa54246e3f216186e35a3e5b9
DIFF:
https://github.com/llvm/llvm-project/commit/09b67aa1c38279daa54246e3f216186e35a3e5b9.diff
LOG: [PowerPC] Implement builtin for vbpermd
The instruction has similar semantics to vbpermq but for doublewords.
It was added in Power9 and the ABI documents the builtin.
Differential revision: https://reviews.llvm.org/D107899
Added:
llvm/test/CodeGen/PowerPC/p9-vbpermd.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p8vector.c
clang/test/CodeGen/builtins-ppc-p9vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index 76c953272b4db..6fee978530dd6 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -397,6 +397,7 @@ BUILTIN(__builtin_altivec_vcmpgtfp_p, "iiV4fV4f", "")
BUILTIN(__builtin_altivec_vgbbd, "V16UcV16Uc", "")
BUILTIN(__builtin_altivec_vbpermq, "V2ULLiV16UcV16Uc", "")
+BUILTIN(__builtin_altivec_vbpermd, "V2ULLiV2ULLiV16Uc", "")
// P8 Crypto built-ins.
BUILTIN(__builtin_altivec_crypto_vsbox, "V2ULLiV2ULLi", "")
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 6cfe9815228fa..0ccd63af8791a 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -17369,12 +17369,22 @@ vec_vbpermq(vector unsigned char __a, vector unsigned
char __b) {
}
#if defined(__powerpc64__) && defined(__SIZEOF_INT128__)
-static __inline__ vector unsigned long long __attribute__((__always_inline__))
+static __inline__ vector unsigned long long __ATTRS_o_ai
vec_bperm(vector unsigned __int128 __a, vector unsigned char __b) {
return __builtin_altivec_vbpermq((vector unsigned char)__a,
(vector unsigned char)__b);
}
#endif
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_bperm(vector unsigned char __a, vector unsigned char __b) {
+ return __builtin_altivec_vbpermq(__a, __b);
+}
+#endif // __POWER8_VECTOR__
+#ifdef __POWER9_VECTOR__
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_bperm(vector unsigned long long __a, vector unsigned char __b) {
+ return __builtin_altivec_vbpermd(__a, __b);
+}
#endif
diff --git a/clang/test/CodeGen/builtins-ppc-p8vector.c
b/clang/test/CodeGen/builtins-ppc-p8vector.c
index 68a2c95e870eb..16a306cc82ed2 100644
--- a/clang/test/CodeGen/builtins-ppc-p8vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p8vector.c
@@ -1177,10 +1177,13 @@ void test1() {
// CHECK: llvm.ppc.altivec.vgbbd
// CHECK-LE: llvm.ppc.altivec.vgbbd
- res_vull = vec_bperm(vux, vux);
-// CHECK: llvm.ppc.altivec.vbpermq
-// CHECK-LE: llvm.ppc.altivec.vbpermq
-// CHECK-PPC: warning: implicit declaration of function 'vec_bperm'
+ res_vull = vec_bperm(vux, vuc);
+ // CHECK: llvm.ppc.altivec.vbpermq
+ // CHECK-LE: llvm.ppc.altivec.vbpermq
+
+ res_vull = vec_bperm(vuc, vuc);
+ // CHECK: llvm.ppc.altivec.vbpermq
+ // CHECK-LE: llvm.ppc.altivec.vbpermq
res_vsll = vec_neg(vsll);
// CHECK: sub <2 x i64> zeroinitializer, {{%[0-9]+}}
diff --git a/clang/test/CodeGen/builtins-ppc-p9vector.c
b/clang/test/CodeGen/builtins-ppc-p9vector.c
index 1766f2507308b..d984deb58d3e1 100644
--- a/clang/test/CodeGen/builtins-ppc-p9vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p9vector.c
@@ -1260,3 +1260,9 @@ vector signed long long test_vec_signextll_sll_si(void) {
// CHECK-NEXT: ret <2 x i64>
return vec_signextll(vsia);
}
+
+vector unsigned long long test_vbpermd(void) {
+ // CHECK: @llvm.ppc.altivec.vbpermd(<2 x i64>
+ // CHECK-BE: @llvm.ppc.altivec.vbpermd(<2 x i64>
+ return vec_bperm(vula, vuca);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index be2a795f26d21..d4f1e5e985b22 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1042,6 +1042,9 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics
start with "llvm.ppc.".
def int_ppc_altivec_vbpermq : GCCBuiltin<"__builtin_altivec_vbpermq">,
Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
[IntrNoMem]>;
+ def int_ppc_altivec_vbpermd : GCCBuiltin<"__builtin_altivec_vbpermd">,
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v16i8_ty],
+[IntrNoMem]>;
}
def int_ppc_altivec_vexptefp : PowerPC_Vec_FF_Intrinsic<"vexptefp">;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
index 2bc7fb2a1a5fa..1e0e2d88e54be 100
[clang] fad14a1 - [PowerPC] Truncate element index for vec_insert in altivec.h
Author: Nemanja Ivanovic
Date: 2021-09-30T05:58:22-05:00
New Revision: fad14a17a490b1825b0c7c40ace7e83c91af4b8a
URL:
https://github.com/llvm/llvm-project/commit/fad14a17a490b1825b0c7c40ace7e83c91af4b8a
DIFF:
https://github.com/llvm/llvm-project/commit/fad14a17a490b1825b0c7c40ace7e83c91af4b8a.diff
LOG: [PowerPC] Truncate element index for vec_insert in altivec.h
When a user specifies an out-of-range index for vec_insert, we
just produce IR that has undefined behaviour even though the
documentation states that modulo arithmetic is used. This patch
just truncates the value to a valid index.
Added:
Modified:
clang/lib/Headers/altivec.h
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 0ccd63af8791a..6a179d86d71f9 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -13571,82 +13571,82 @@ vec_extract_fp32_from_shortl(vector unsigned short
__a) {
static __inline__ vector signed char __ATTRS_o_ai
vec_insert(signed char __a, vector signed char __b, int __c) {
- __b[__c] = __a;
+ __b[__c & 0xF] = __a;
return __b;
}
static __inline__ vector unsigned char __ATTRS_o_ai
vec_insert(unsigned char __a, vector unsigned char __b, int __c) {
- __b[__c] = __a;
+ __b[__c & 0xF] = __a;
return __b;
}
static __inline__ vector bool char __ATTRS_o_ai vec_insert(unsigned char __a,
vector bool char
__b,
int __c) {
- __b[__c] = __a;
+ __b[__c & 0xF] = __a;
return __b;
}
static __inline__ vector signed short __ATTRS_o_ai
vec_insert(signed short __a, vector signed short __b, int __c) {
- __b[__c] = __a;
+ __b[__c & 0x7] = __a;
return __b;
}
static __inline__ vector unsigned short __ATTRS_o_ai
vec_insert(unsigned short __a, vector unsigned short __b, int __c) {
- __b[__c] = __a;
+ __b[__c & 0x7] = __a;
return __b;
}
static __inline__ vector bool short __ATTRS_o_ai
vec_insert(unsigned short __a, vector bool short __b, int __c) {
- __b[__c] = __a;
+ __b[__c & 0x7] = __a;
return __b;
}
static __inline__ vector signed int __ATTRS_o_ai
vec_insert(signed int __a, vector signed int __b, int __c) {
- __b[__c] = __a;
+ __b[__c & 0x3] = __a;
return __b;
}
static __inline__ vector unsigned int __ATTRS_o_ai
vec_insert(unsigned int __a, vector unsigned int __b, int __c) {
- __b[__c] = __a;
+ __b[__c & 0x3] = __a;
return __b;
}
static __inline__ vector bool int __ATTRS_o_ai vec_insert(unsigned int __a,
vector bool int __b,
int __c) {
- __b[__c] = __a;
+ __b[__c & 0x3] = __a;
return __b;
}
#ifdef __VSX__
static __inline__ vector signed long long __ATTRS_o_ai
vec_insert(signed long long __a, vector signed long long __b, int __c) {
- __b[__c] = __a;
+ __b[__c & 0x1] = __a;
return __b;
}
static __inline__ vector unsigned long long __ATTRS_o_ai
vec_insert(unsigned long long __a, vector unsigned long long __b, int __c) {
- __b[__c] = __a;
+ __b[__c & 0x1] = __a;
return __b;
}
static __inline__ vector bool long long __ATTRS_o_ai
vec_insert(unsigned long long __a, vector bool long long __b, int __c) {
- __b[__c] = __a;
+ __b[__c & 0x1] = __a;
return __b;
}
static __inline__ vector double __ATTRS_o_ai vec_insert(double __a,
vector double __b,
int __c) {
- __b[__c] = __a;
+ __b[__c & 0x1] = __a;
return __b;
}
#endif
@@ -13654,7 +13654,7 @@ static __inline__ vector double __ATTRS_o_ai
vec_insert(double __a,
static __inline__ vector float __ATTRS_o_ai vec_insert(float __a,
vector float __b,
int __c) {
- __b[__c] = __a;
+ __b[__c & 0x3] = __a;
return __b;
}
___
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[clang] 369d785 - [PowerPC] Optimal sequence for doubleword vec_all_{eq|ne} on Power7
Author: Nemanja Ivanovic
Date: 2021-10-01T08:27:15-05:00
New Revision: 369d785574f5a22c086d0c40268a39a64bdd7217
URL:
https://github.com/llvm/llvm-project/commit/369d785574f5a22c086d0c40268a39a64bdd7217
DIFF:
https://github.com/llvm/llvm-project/commit/369d785574f5a22c086d0c40268a39a64bdd7217.diff
LOG: [PowerPC] Optimal sequence for doubleword vec_all_{eq|ne} on Power7
These builtins produce inefficient code for CPU's prior to Power8
due to vcmpequd being unavailable. The predicate forms can actually
leverage the available vcmpequw along with xxlxor to produce a better
sequence.
Added:
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-vsx.c
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 6a179d86d71f9..5da4fbf72ce97 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -14815,42 +14815,43 @@ static __inline__ int __ATTRS_o_ai vec_all_eq(vector
bool int __a,
#ifdef __VSX__
static __inline__ int __ATTRS_o_ai vec_all_eq(vector signed long long __a,
vector signed long long __b) {
+#ifdef __POWER8_VECTOR__
return __builtin_altivec_vcmpequd_p(__CR6_LT, __a, __b);
+#else
+ // No vcmpequd on Power7 so we xor the two vectors and compare against zero
as
+ // 32-bit elements.
+ return vec_all_eq((vector signed int)vec_xor(__a, __b), (vector signed
int)0);
+#endif
}
static __inline__ int __ATTRS_o_ai vec_all_eq(vector long long __a,
vector bool long long __b) {
- return __builtin_altivec_vcmpequd_p(__CR6_LT, __a, (vector long long)__b);
+ return vec_all_eq((vector signed long long)__a, (vector signed long
long)__b);
}
static __inline__ int __ATTRS_o_ai vec_all_eq(vector unsigned long long __a,
vector unsigned long long __b) {
- return __builtin_altivec_vcmpequd_p(__CR6_LT, (vector long long)__a,
- (vector long long)__b);
+ return vec_all_eq((vector signed long long)__a, (vector signed long
long)__b);
}
static __inline__ int __ATTRS_o_ai vec_all_eq(vector unsigned long long __a,
vector bool long long __b) {
- return __builtin_altivec_vcmpequd_p(__CR6_LT, (vector long long)__a,
- (vector long long)__b);
+ return vec_all_eq((vector signed long long)__a, (vector signed long
long)__b);
}
static __inline__ int __ATTRS_o_ai vec_all_eq(vector bool long long __a,
vector long long __b) {
- return __builtin_altivec_vcmpequd_p(__CR6_LT, (vector long long)__a,
- (vector long long)__b);
+ return vec_all_eq((vector signed long long)__a, (vector signed long
long)__b);
}
static __inline__ int __ATTRS_o_ai vec_all_eq(vector bool long long __a,
vector unsigned long long __b) {
- return __builtin_altivec_vcmpequd_p(__CR6_LT, (vector long long)__a,
- (vector long long)__b);
+ return vec_all_eq((vector signed long long)__a, (vector signed long
long)__b);
}
static __inline__ int __ATTRS_o_ai vec_all_eq(vector bool long long __a,
vector bool long long __b) {
- return __builtin_altivec_vcmpequd_p(__CR6_LT, (vector long long)__a,
- (vector long long)__b);
+ return vec_all_eq((vector signed long long)__a, (vector signed long
long)__b);
}
#endif
@@ -17038,43 +17039,43 @@ static __inline__ int __ATTRS_o_ai vec_any_ne(vector
bool int __a,
#ifdef __VSX__
static __inline__ int __ATTRS_o_ai vec_any_ne(vector signed long long __a,
vector signed long long __b) {
+#ifdef __POWER8_VECTOR__
return __builtin_altivec_vcmpequd_p(__CR6_LT_REV, __a, __b);
+#else
+ // Take advantage of the optimized sequence for vec_all_eq when vcmpequd is
+ // not available.
+ return !vec_all_eq(__a, __b);
+#endif
}
static __inline__ int __ATTRS_o_ai vec_any_ne(vector unsigned long long __a,
vector unsigned long long __b) {
- return __builtin_altivec_vcmpequd_p(__CR6_LT_REV, (vector long long)__a,
- (vector long long)__b);
+ return vec_any_ne((vector signed long long)__a, (vector signed long
long)__b);
}
static __inline__ int __ATTRS_o_ai vec_any_ne(vector signed long long __a,
vector bool long long __b) {
- return __builtin_altivec_vcmpequd_p(__CR6_LT_REV, __a,
- (vector signed long long)__b);
+ return vec_any_ne((vector signed long long)__a, (vector signed long
long)__b);
}
static __inl
[clang] ef90657 - [PowerPC] Fix vec_add for 64-bit on pre-Power7 subtargets
Author: Nemanja Ivanovic
Date: 2021-06-24T18:42:44-05:00
New Revision: ef906573a127cffef7cae75d5155c15a8a2a3a5e
URL:
https://github.com/llvm/llvm-project/commit/ef906573a127cffef7cae75d5155c15a8a2a3a5e
DIFF:
https://github.com/llvm/llvm-project/commit/ef906573a127cffef7cae75d5155c15a8a2a3a5e.diff
LOG: [PowerPC] Fix vec_add for 64-bit on pre-Power7 subtargets
The shift of the carry was actually incorrect.
Added:
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-vsx.c
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index dadf6b5cf75bb..3517da798547a 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -312,16 +312,20 @@ vec_add_u128(vector unsigned char __a, vector unsigned
char __b) {
#elif defined(__VSX__)
static __inline__ vector signed long long __ATTRS_o_ai
vec_add(vector signed long long __a, vector signed long long __b) {
+#ifdef __LITTLE_ENDIAN__
+ // Little endian systems on CPU's prior to Power8 don't really exist
+ // so scalarizing is fine.
+ return __a + __b;
+#else
vector unsigned int __res =
(vector unsigned int)__a + (vector unsigned int)__b;
vector unsigned int __carry = __builtin_altivec_vaddcuw(
(vector unsigned int)__a, (vector unsigned int)__b);
-#ifdef __LITTLE_ENDIAN__
- __carry = __builtin_shufflevector(__carry, __carry, 3, 0, 1, 2);
-#else
- __carry = __builtin_shufflevector(__carry, __carry, 1, 2, 3, 0);
-#endif
+ __carry = __builtin_shufflevector((vector unsigned char)__carry,
+(vector unsigned char)__carry, 0, 0, 0, 7,
+0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0);
return (vector signed long long)(__res + __carry);
+#endif
}
static __inline__ vector unsigned long long __ATTRS_o_ai
diff --git a/clang/test/CodeGen/builtins-ppc-vsx.c
b/clang/test/CodeGen/builtins-ppc-vsx.c
index abd08d463e634..b5ddd03722ad0 100644
--- a/clang/test/CodeGen/builtins-ppc-vsx.c
+++ b/clang/test/CodeGen/builtins-ppc-vsx.c
@@ -2319,21 +2319,15 @@ void test_p8overloads_backwards_compat() {
res_vsll = vec_add(vsll, vsll);
// CHECK: add <4 x i32>
// CHECK: call <4 x i32> @llvm.ppc.altivec.vaddcuw
- // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32>
+ // CHECK: shufflevector <16 x i8> {{%.*}}, <16 x i8> {{%.*}}, <16 x i32>
// CHECK: add <4 x i32>
- // CHECK-LE: add <4 x i32>
- // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vaddcuw
- // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32>
- // CHECK-LE: add <4 x i32>
+ // CHECK-LE: add <2 x i64>
res_vull = vec_add(vull, vull);
// CHECK: add <4 x i32>
// CHECK: call <4 x i32> @llvm.ppc.altivec.vaddcuw
- // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32>
+ // CHECK: shufflevector <16 x i8> {{%.*}}, <16 x i8> {{%.*}}, <16 x i32>
// CHECK: add <4 x i32>
- // CHECK-LE: add <4 x i32>
- // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vaddcuw
- // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32>
- // CHECK-LE: add <4 x i32>
+ // CHECK-LE: add <2 x i64>
dummy();
// CHECK: call void @dummy()
// CHECK-LE: call void @dummy()
___
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[clang] 9019b55 - [PowerPC] Fix byte ordering of ld/st with length on BE
Author: Nemanja Ivanovic
Date: 2021-07-30T14:37:24-05:00
New Revision: 9019b55b605a26cb5389399eceb34fa9ea0f
URL:
https://github.com/llvm/llvm-project/commit/9019b55b605a26cb5389399eceb34fa9ea0f
DIFF:
https://github.com/llvm/llvm-project/commit/9019b55b605a26cb5389399eceb34fa9ea0f.diff
LOG: [PowerPC] Fix byte ordering of ld/st with length on BE
The builtins vec_xl_len_r and vec_xst_len_r actually use the
wrong side of the vector on big endian Power9 systems. We never
spotted this before because there was no such thing as a big
endian distro that supported Power9. Now we have AIX and the
elements are in the wrong part of the vector. This just fixes
it so the elements are loaded to and stored from the right
side of the vector.
Added:
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-ld-st-rmb.c
clang/test/CodeGen/builtins-ppc-p9vector.c
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 0dd8c859366b..d548d8a0dd75 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -3049,13 +3049,10 @@ static __inline__ vector unsigned char __ATTRS_o_ai
vec_xl_len_r(const unsigned char *__a, size_t __b) {
vector unsigned char __res =
(vector unsigned char)__builtin_vsx_lxvll(__a, (__b << 56));
-#ifdef __LITTLE_ENDIAN__
vector unsigned char __mask =
(vector unsigned char)__builtin_altivec_lvsr(16 - __b, (int *)NULL);
- __res = (vector unsigned char)__builtin_altivec_vperm_4si(
+ return (vector unsigned char)__builtin_altivec_vperm_4si(
(vector int)__res, (vector int)__res, __mask);
-#endif
- return __res;
}
// vec_xst_len
@@ -3130,15 +3127,11 @@ static __inline__ void __ATTRS_o_ai vec_xst_len(vector
double __a, double *__b,
static __inline__ void __ATTRS_o_ai vec_xst_len_r(vector unsigned char __a,
unsigned char *__b,
size_t __c) {
-#ifdef __LITTLE_ENDIAN__
vector unsigned char __mask =
(vector unsigned char)__builtin_altivec_lvsl(16 - __c, (int *)NULL);
vector unsigned char __res =
__builtin_altivec_vperm_4si((vector int)__a, (vector int)__a, __mask);
return __builtin_vsx_stxvll((vector int)__res, __b, (__c << 56));
-#else
- return __builtin_vsx_stxvll((vector int)__a, __b, (__c << 56));
-#endif
}
#endif
#endif
diff --git a/clang/test/CodeGen/builtins-ppc-ld-st-rmb.c
b/clang/test/CodeGen/builtins-ppc-ld-st-rmb.c
index 0921d05f0325..76eb87c8db59 100644
--- a/clang/test/CodeGen/builtins-ppc-ld-st-rmb.c
+++ b/clang/test/CodeGen/builtins-ppc-ld-st-rmb.c
@@ -46,6 +46,7 @@
// BE-PWR9-NEXT:[[__A_ADDR_I:%.*]] = alloca i8*, align 8
// BE-PWR9-NEXT:[[__B_ADDR_I:%.*]] = alloca i64, align 8
// BE-PWR9-NEXT:[[__RES_I:%.*]] = alloca <16 x i8>, align 16
+// BE-PWR9-NEXT:[[__MASK_I:%.*]] = alloca <16 x i8>, align 16
// BE-PWR9-NEXT:[[PTR_ADDR:%.*]] = alloca i8*, align 8
// BE-PWR9-NEXT:store i8* [[PTR:%.*]], i8** [[PTR_ADDR]], align 8
// BE-PWR9-NEXT:[[TMP0:%.*]] = load i8*, i8** [[PTR_ADDR]], align 8
@@ -54,11 +55,23 @@
// BE-PWR9-NEXT:[[TMP1:%.*]] = load i8*, i8** [[__A_ADDR_I]], align 8
// BE-PWR9-NEXT:[[TMP2:%.*]] = load i64, i64* [[__B_ADDR_I]], align 8
// BE-PWR9-NEXT:[[SHL_I:%.*]] = shl i64 [[TMP2]], 56
-// BE-PWR9-NEXT:[[TMP3:%.*]] = call <4 x i32> @llvm.ppc.vsx.lxvll(i8*
[[TMP1]], i64 [[SHL_I]]) #[[ATTR3:[0-9]+]]
+// BE-PWR9-NEXT:[[TMP3:%.*]] = call <4 x i32> @llvm.ppc.vsx.lxvll(i8*
[[TMP1]], i64 [[SHL_I]]) #[[ATTR4:[0-9]+]]
// BE-PWR9-NEXT:[[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <16 x i8>
// BE-PWR9-NEXT:store <16 x i8> [[TMP4]], <16 x i8>* [[__RES_I]], align 16
-// BE-PWR9-NEXT:[[TMP5:%.*]] = load <16 x i8>, <16 x i8>* [[__RES_I]],
align 16
-// BE-PWR9-NEXT:ret <16 x i8> [[TMP5]]
+// BE-PWR9-NEXT:[[TMP5:%.*]] = load i64, i64* [[__B_ADDR_I]], align 8
+// BE-PWR9-NEXT:[[SUB_I:%.*]] = sub i64 16, [[TMP5]]
+// BE-PWR9-NEXT:[[CONV_I:%.*]] = trunc i64 [[SUB_I]] to i8
+// BE-PWR9-NEXT:[[TMP6:%.*]] = getelementptr i8, i8* null, i8 [[CONV_I]]
+// BE-PWR9-NEXT:[[TMP7:%.*]] = call <16 x i8> @llvm.ppc.altivec.lvsr(i8*
[[TMP6]]) #[[ATTR4]]
+// BE-PWR9-NEXT:store <16 x i8> [[TMP7]], <16 x i8>* [[__MASK_I]], align 16
+// BE-PWR9-NEXT:[[TMP8:%.*]] = load <16 x i8>, <16 x i8>* [[__RES_I]],
align 16
+// BE-PWR9-NEXT:[[TMP9:%.*]] = bitcast <16 x i8> [[TMP8]] to <4 x i32>
+// BE-PWR9-NEXT:[[TMP10:%.*]] = load <16 x i8>, <16 x i8>* [[__RES_I]],
align 16
+// BE-PWR9-NEXT:[[TMP11:%.*]] = bitcast <16 x i8> [[TMP10]] to <4 x i32>
+// BE-PWR9-NEXT:[[TMP12:%.*]] = load <16 x i8>, <16 x i8>* [[__MASK_I]],
align 16
+// BE-PWR9-NEXT:[[TMP13:%.*]] = call <4 x i32> @llvm.ppc.altivec.vperm(<4
x i32> [[TMP9]], <4 x i32> [[TMP11]], <16 x i8> [[TMP12]]) #[[ATTR
