[clang] [clang-repl] Typo within InterpreterTest.cpp (PR #79119)

2024-01-26 Thread Nashe Mncube via cfe-commits 

https://github.com/nasherm closed 
https://github.com/llvm/llvm-project/pull/79119
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[clang] [clang-repl] Typo within InterpreterTest.cpp (PR #79119)

2024-01-26 Thread Nashe Mncube via cfe-commits 

nasherm wrote:

Need to follow proper contribution process. So closing for now

https://github.com/llvm/llvm-project/pull/79119
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[clang] [clang-repl] Typo within InterpreterTest.cpp (PR #79119)

2024-01-23 Thread Nashe Mncube via cfe-commits 

https://github.com/nasherm created 
https://github.com/llvm/llvm-project/pull/79119

Recent changes to InterpreterTest.cpp 
(https://github.com/llvm/llvm-project/pull/76218) introduced typos within code 
passed to a Parse() function. This causes some tests to fail, namely 
IncrementalProcessing.InstantiateTemplate. 


>From 91a0b265ce85359efb60821b419bb9754e48bdbe Mon Sep 17 00:00:00 2001
From: nasmnc01 
Date: Tue, 23 Jan 2024 10:43:08 +
Subject: [PATCH] [clang-repl] Typo within InterpreterTest.cpp

Recent changes to InterpreterTest.cpp introduced typos
within code passed to a Parse() function. This causes some
tests to fail, namely IncrementalProcessing.InstantiateTemplate.

Change-Id: I79a09030f980b1bc766e27cc6acb944fbc2422ac
---
 clang/unittests/Interpreter/InterpreterTest.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/clang/unittests/Interpreter/InterpreterTest.cpp 
b/clang/unittests/Interpreter/InterpreterTest.cpp
index e76c0677db5ead1..6d2e5c79bc242ce 100644
--- a/clang/unittests/Interpreter/InterpreterTest.cpp
+++ b/clang/unittests/Interpreter/InterpreterTest.cpp
@@ -256,7 +256,8 @@ static Value AllocateObject(TypeDecl *TD, Interpreter 
&Interp) {
   // cantFail(Interp.ParseAndExecute("new " + Name + "()", &Addr));
 
   // The lifetime of the temporary is extended by the clang::Value.
-  cantFail(Interp.ParseAndExecute(Name + "()", &Addr));
+  cantFail(Interp.ParseAndExecute(Name + "();", &Addr));
+  Addr.setKind(Value::Kind::K_PtrOrObj);
   return Addr;
 }
 

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[clang] [llvm] Add support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-15 Thread Nashe Mncube via cfe-commits 

https://github.com/nasherm created 
https://github.com/llvm/llvm-project/pull/112341

Add support for the following Armv9.6-A memory systems extensions:
  FEAT_LSUI  - Unprivileged Load Store
  FEAT_OCCMO - Outer Cacheable Cache Maintenance Operation
  FEAT_PCDPHINT  - Producer-Consumer Data Placement Hints
  FEAT_SRMASK- Bitwise System Register Write Masks

as documented here:
  
https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-6-architecture-extension



>From 345f58ec293e3b5861965726403b53b5fff47255 Mon Sep 17 00:00:00 2001
From: Nashe Mncube 
Date: Fri, 4 Oct 2024 10:22:10 +0100
Subject: [PATCH] Add support for Armv9.6-A memory systems extensions

Add support for the following Armv9.6-A memory systems extensions:
  FEAT_LSUI  - Unprivileged Load Store
  FEAT_OCCMO - Outer Cacheable Cache Maintenance Operation
  FEAT_PCDPHINT  - Producer-Consumer Data Placement Hints
  FEAT_SRMASK- Bitwise System Register Write Masks

as documented here:
  
https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-6-architecture-extension

Co-authored-by: Jonathan Thackray 
Change-Id: Icbbdd194b8885d8a1b9d513faf0b85e74011201d
---
 clang/test/Driver/aarch64-v96a.c  |  13 +
 .../print-supported-extensions-aarch64.c  |   3 +
 llvm/lib/Target/AArch64/AArch64Features.td|  12 +-
 .../lib/Target/AArch64/AArch64InstrFormats.td | 304 ++
 llvm/lib/Target/AArch64/AArch64InstrInfo.td   | 101 +
 .../Target/AArch64/AArch64SystemOperands.td   |  67 +++
 .../AArch64/AsmParser/AArch64AsmParser.cpp|  61 ++-
 .../Disassembler/AArch64Disassembler.cpp  |  24 ++
 .../MCTargetDesc/AArch64InstPrinter.cpp   |  27 ++
 .../AArch64/MCTargetDesc/AArch64InstPrinter.h |   2 +
 .../Target/AArch64/Utils/AArch64BaseInfo.cpp  |   7 +
 .../Target/AArch64/Utils/AArch64BaseInfo.h|  20 +
 llvm/test/MC/AArch64/armv9.6a-lsui.s  | 395 ++
 llvm/test/MC/AArch64/armv9.6a-occmo.s |  14 +
 llvm/test/MC/AArch64/armv9.6a-pcdphint.s  |  12 +
 llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s  |  12 +
 llvm/test/MC/AArch64/armv9.6a-srmask.s| 104 +
 .../MC/Disassembler/AArch64/armv9.6a-lsui.txt | 324 ++
 .../Disassembler/AArch64/armv9.6a-occmo.txt   |  12 +
 .../AArch64/armv9.6a-pcdphint.txt |   9 +
 .../AArch64/armv9.6a-rme-gpc3.txt |  11 +
 .../Disassembler/AArch64/armv9.6a-srmask.txt  | 102 +
 .../TargetParser/TargetParserTest.cpp |  10 +-
 23 files changed, 1641 insertions(+), 5 deletions(-)
 create mode 100644 llvm/test/MC/AArch64/armv9.6a-lsui.s
 create mode 100644 llvm/test/MC/AArch64/armv9.6a-occmo.s
 create mode 100644 llvm/test/MC/AArch64/armv9.6a-pcdphint.s
 create mode 100644 llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s
 create mode 100644 llvm/test/MC/AArch64/armv9.6a-srmask.s
 create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt
 create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-occmo.txt
 create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-pcdphint.txt
 create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
 create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-srmask.txt

diff --git a/clang/test/Driver/aarch64-v96a.c b/clang/test/Driver/aarch64-v96a.c
index 0aaadddb2842f8..fd24585acf24f2 100644
--- a/clang/test/Driver/aarch64-v96a.c
+++ b/clang/test/Driver/aarch64-v96a.c
@@ -17,3 +17,16 @@
 // GENERICV96A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+v9.6a"
 //
 // = Features supported on aarch64 =
+//
+// RUN: %clang -target aarch64 -march=armv9.6a+lsui -### -c %s 2>&1 | 
FileCheck -check-prefix=V96A-LSUI %s
+// RUN: %clang -target aarch64 -march=armv9.6-a+lsui -### -c %s 2>&1 | 
FileCheck -check-prefix=V96A-LSUI %s
+// V96A-LSUI: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" 
"-target-feature" "+v9.6a"{{.*}} "-target-feature" "+lsui"
+//
+// RUN: %clang -target aarch64 -march=armv9.6a+occmo -### -c %s 2>&1 | 
FileCheck -check-prefix=V96A-OCCMO %s
+// RUN: %clang -target aarch64 -march=armv9.6-a+occmo -### -c %s 2>&1 | 
FileCheck -check-prefix=V96A-OCCMO %s
+// V96A-OCCMO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" 
"-target-feature" "+v9.6a"{{.*}} "-target-feature" "+occmo"
+//
+// RUN: %clang -target aarch64 -march=armv9.6a+pcdphint -### -c %s 2>&1 | 
FileCheck -check-prefix=V96A-PCDPHINT %s
+// RUN: %clang -target aarch64 -march=armv9.6-a+pcdphint -### -c %s 2>&1 | 
FileCheck -check-prefix=V96A-PCDPHINT %s
+// V96A-PCDPHINT: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+pcdphint"
+//
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c 
b/clang/test/Driver/print-supported-extensions-aarch64.c
index e6247307c7219f..642df4b699ecc3 100644
--- a/clang/test/Driver/print-supported-extensions-a

[clang] [llvm] [LLVM][MC][AArch64support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-15 Thread Nashe Mncube via cfe-commits 

https://github.com/nasherm edited 
https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-15 Thread Nashe Mncube via cfe-commits 

https://github.com/nasherm edited 
https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-15 Thread Nashe Mncube via cfe-commits 

https://github.com/nasherm updated 
https://github.com/llvm/llvm-project/pull/112341

>From a20ed3469726b53d0bff59710ad367766e839a45 Mon Sep 17 00:00:00 2001
From: Nashe Mncube 
Date: Fri, 4 Oct 2024 10:22:10 +0100
Subject: [PATCH] Add support for Armv9.6-A memory systems extensions

Add support for the following Armv9.6-A memory systems extensions:
  FEAT_LSUI  - Unprivileged Load Store
  FEAT_OCCMO - Outer Cacheable Cache Maintenance Operation
  FEAT_PCDPHINT  - Producer-Consumer Data Placement Hints
  FEAT_SRMASK- Bitwise System Register Write Masks

as documented here:
  
https://developer.arm.com/documentation/109697/2024_09/Feature-descriptions/The-Armv9-6-architecture-extension

Co-authored-by: Jonathan Thackray 
Change-Id: Icbbdd194b8885d8a1b9d513faf0b85e74011201d
---
 clang/test/Driver/aarch64-v96a.c  |  13 +
 .../print-supported-extensions-aarch64.c  |   3 +
 llvm/lib/Target/AArch64/AArch64Features.td|  12 +-
 .../lib/Target/AArch64/AArch64InstrFormats.td | 304 ++
 llvm/lib/Target/AArch64/AArch64InstrInfo.td   | 101 +
 .../Target/AArch64/AArch64SystemOperands.td   |  67 +++
 .../AArch64/AsmParser/AArch64AsmParser.cpp|  61 ++-
 .../Disassembler/AArch64Disassembler.cpp  |  24 ++
 .../MCTargetDesc/AArch64InstPrinter.cpp   |  27 ++
 .../AArch64/MCTargetDesc/AArch64InstPrinter.h |   2 +
 .../Target/AArch64/Utils/AArch64BaseInfo.cpp  |   7 +
 .../Target/AArch64/Utils/AArch64BaseInfo.h|  20 +
 llvm/test/MC/AArch64/armv9.6a-lsui.s  | 395 ++
 llvm/test/MC/AArch64/armv9.6a-occmo.s |  14 +
 llvm/test/MC/AArch64/armv9.6a-pcdphint.s  |  12 +
 llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s  |  12 +
 llvm/test/MC/AArch64/armv9.6a-srmask.s| 104 +
 .../MC/Disassembler/AArch64/armv9.6a-lsui.txt | 324 ++
 .../Disassembler/AArch64/armv9.6a-occmo.txt   |  12 +
 .../AArch64/armv9.6a-pcdphint.txt |   9 +
 .../AArch64/armv9.6a-rme-gpc3.txt |  11 +
 .../Disassembler/AArch64/armv9.6a-srmask.txt  | 102 +
 .../TargetParser/TargetParserTest.cpp |  10 +-
 23 files changed, 1641 insertions(+), 5 deletions(-)
 create mode 100644 llvm/test/MC/AArch64/armv9.6a-lsui.s
 create mode 100644 llvm/test/MC/AArch64/armv9.6a-occmo.s
 create mode 100644 llvm/test/MC/AArch64/armv9.6a-pcdphint.s
 create mode 100644 llvm/test/MC/AArch64/armv9.6a-rme-gpc3.s
 create mode 100644 llvm/test/MC/AArch64/armv9.6a-srmask.s
 create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt
 create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-occmo.txt
 create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-pcdphint.txt
 create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
 create mode 100644 llvm/test/MC/Disassembler/AArch64/armv9.6a-srmask.txt

diff --git a/clang/test/Driver/aarch64-v96a.c b/clang/test/Driver/aarch64-v96a.c
index 0aaadddb2842f8..fd24585acf24f2 100644
--- a/clang/test/Driver/aarch64-v96a.c
+++ b/clang/test/Driver/aarch64-v96a.c
@@ -17,3 +17,16 @@
 // GENERICV96A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+v9.6a"
 //
 // = Features supported on aarch64 =
+//
+// RUN: %clang -target aarch64 -march=armv9.6a+lsui -### -c %s 2>&1 | 
FileCheck -check-prefix=V96A-LSUI %s
+// RUN: %clang -target aarch64 -march=armv9.6-a+lsui -### -c %s 2>&1 | 
FileCheck -check-prefix=V96A-LSUI %s
+// V96A-LSUI: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" 
"-target-feature" "+v9.6a"{{.*}} "-target-feature" "+lsui"
+//
+// RUN: %clang -target aarch64 -march=armv9.6a+occmo -### -c %s 2>&1 | 
FileCheck -check-prefix=V96A-OCCMO %s
+// RUN: %clang -target aarch64 -march=armv9.6-a+occmo -### -c %s 2>&1 | 
FileCheck -check-prefix=V96A-OCCMO %s
+// V96A-OCCMO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" 
"-target-feature" "+v9.6a"{{.*}} "-target-feature" "+occmo"
+//
+// RUN: %clang -target aarch64 -march=armv9.6a+pcdphint -### -c %s 2>&1 | 
FileCheck -check-prefix=V96A-PCDPHINT %s
+// RUN: %clang -target aarch64 -march=armv9.6-a+pcdphint -### -c %s 2>&1 | 
FileCheck -check-prefix=V96A-PCDPHINT %s
+// V96A-PCDPHINT: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"generic" "-target-feature" "+v9.6a"{{.*}} "-target-feature" "+pcdphint"
+//
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c 
b/clang/test/Driver/print-supported-extensions-aarch64.c
index e6247307c7219f..642df4b699ecc3 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -35,12 +35,15 @@
 // CHECK-NEXT: ls64FEAT_LS64, FEAT_LS64_V, 
FEAT_LS64_ACCDATA  Enable Armv8.7-A LD64B/ST64B Accelerator 
Extension
 // CHECK-NEXT: lse FEAT_LSE
   Enable Armv8.1-A Large System Extension (LSE) atomic instructions
 // CHECK-NEXT: lse1

[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-16 Thread Nashe Mncube via cfe-commits 


@@ -4769,6 +4843,109 @@ class LoadExclusivePair sz, bit o2, bit L, bit 
o1, bit o0,
   let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
 }
 
+// Armv9.6-a load-store exclusive instructions
+let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
+class BaseLoadStoreExclusiveLSUI sz, bit L, bit o0,
+ dag oops, dag iops, string asm, string operands>
+: I {
+  let Inst{31-30} = sz;
+  let Inst{29-23} = 0b0010010;
+  let Inst{22}= L;
+  let Inst{15}= o0;
+}
+
+
+// Neither Rs nor Rt2 operands.
+
+class LoadExclusiveLSUI sz, bit L, bit o0,
+RegisterClass regtype, string asm>
+: BaseLoadStoreExclusiveLSUI,
+  Sched<[WriteLD]>
+{
+  bits<5> Rt;
+  bits<5> Rn;
+  let Inst{20-16} = 0b1;
+  let Unpredictable{20-16} = 0b1;
+  let Inst{14-10} = 0b1;
+  let Unpredictable{14-10} = 0b1;
+  let Inst{9-5} = Rn;
+  let Inst{4-0} = Rt;
+
+  let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
+}
+
+ class StoreExclusiveLSUI sz, bit L, bit o0,
+  RegisterClass regtype, string asm>
+ : BaseLoadStoreExclusiveLSUI,
+   Sched<[WriteSTX]> {
+   bits<5> Ws;
+   bits<5> Rt;
+   bits<5> Rn;
+   let Inst{20-16} = Ws;
+   let Inst{15} = o0;
+   let Inst{14-10} = 0b1;
+   let Unpredictable{14-10} = 0b1;
+   let Inst{9-5} = Rn;
+   let Inst{4-0} = Rt;
+
+   let Constraints = "@earlyclobber $Ws";
+   let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
+ }
+
+// Armv9.6-a load-store unprivileged instructions
+class BaseLoadUnprivilegedLSUI sz, dag oops, dag iops, string asm>
+: I {
+   bits<5> Rt;
+   bits<5> Rn;
+   let Inst{31-30} = sz;
+   let Inst{29-23} = 0b0010010;
+   let Inst{22}  = 0b1;
+   let Inst{21} = 0b0;
+   let Inst{20-16} = 0b1;
+   let Unpredictable{20-16} = 0b1;
+   let Inst{15} = 0b0;
+   let Inst{14-10} = 0b1;
+   let Unpredictable{14-10} = 0b1;
+   let Inst{9-5} = Rn;
+   let Inst{4-0} = Rt;
+   let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
+}
+
+multiclass LoadUnprivilegedLSUI sz, RegisterClass regtype, string asm> 
{
+  def i : BaseLoadUnprivilegedLSUIhttps://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-16 Thread Nashe Mncube via cfe-commits 


@@ -0,0 +1,14 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+occmo 
-mattr=+mte < %s | FileCheck %s

nasherm wrote:

Done

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-16 Thread Nashe Mncube via cfe-commits 

nasherm wrote:

> Thank you for the work @nasherm . I left some comments. I am not sure if all 
> of them proceed. Carol

Thank you for the review. I'm not sure about the instruction alias suggestions. 
I would've thought that although these instructions are equivalent the 
different execution conditions mean they don't alias. Am I wrong in my thinking?

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-16 Thread Nashe Mncube via cfe-commits 


@@ -988,6 +988,22 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
   Name = std::string(AT->Name);
 }
 break;
+// Overlaps with AT and DC

nasherm wrote:

Yeah. These are for the newly introduced DC instructions

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-16 Thread Nashe Mncube via cfe-commits 

https://github.com/nasherm edited 
https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-16 Thread Nashe Mncube via cfe-commits 


@@ -0,0 +1,12 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+pcdphint %s | FileCheck 
%s

nasherm wrote:

Done

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-16 Thread Nashe Mncube via cfe-commits 


@@ -0,0 +1,395 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py

nasherm wrote:

Done

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-16 Thread Nashe Mncube via cfe-commits 


@@ -4020,6 +4079,33 @@ defm STNPD : StorePairNoAlloc<0b01, 1, FPR64Op, simm7s8, 
"stnp">;
 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128Op, simm7s16, "stnp">;
 }
 
+// Armv9.6-a Load/store no-allocate pair (FEAT_LSUI)

nasherm wrote:

Thanks. Done

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-16 Thread Nashe Mncube via cfe-commits 


@@ -3736,6 +3776,8 @@ static const struct Extension {
 {"sme-fa64", {AArch64::FeatureSMEFA64}},
 {"cpa", {AArch64::FeatureCPA}},
 {"tlbiw", {AArch64::FeatureTLBIW}},
+{"lsui", {AArch64::FeatureLSUI}},
+{"occmo", {AArch64::FeatureOCCMO}},

nasherm wrote:

Yes. Done

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-17 Thread Nashe Mncube via cfe-commits 


@@ -0,0 +1,395 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+// RUN: llvm-mc -triple aarch64 -mattr=+lsui -show-encoding %s  | FileCheck %s

nasherm wrote:

Done

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-17 Thread Nashe Mncube via cfe-commits 


@@ -4020,6 +4079,33 @@ defm STNPD : StorePairNoAlloc<0b01, 1, FPR64Op, simm7s8, 
"stnp">;
 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128Op, simm7s16, "stnp">;
 }
 
+// Armv9.6-a Load/store no-allocate pair (FEAT_LSUI)
+let Predicates = [HasLSUI] in {
+  defm LDTP: LoadPairOffset<0b11, 0, GPR64z, simm7s8, "ldtp">;
+  def LDTPpre  : LoadPairPreIdx<0b11, 0, GPR64z, simm7s8, "ldtp">;
+  def LDTPpost : LoadPairPostIdx<0b11, 0, GPR64z, simm7s8, "ldtp">;
+
+  defm STTNPX : StorePairNoAllocLSUI<0b11, 0, GPR64z, simm7s8, "sttnp">;
+  defm LDTNPX : LoadPairNoAllocLSUI<0b11, 0, GPR64z, simm7s8, "ldtnp">;
+
+  defm STTP: StorePairOffset<0b11, 0, GPR64z, simm7s8, "sttp">;
+  def STTPpre  : StorePairPreIdx<0b11, 0, GPR64z, simm7s8, "sttp">;
+  def STTPpost : StorePairPostIdx<0b11, 0, GPR64z, simm7s8, "sttp">;
+}
+
+let Predicates = [HasLSUI, HasFPARMv8] in {

nasherm wrote:

That's a mistake on my part. Thanks for spotting

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-17 Thread Nashe Mncube via cfe-commits 


@@ -4660,6 +4746,21 @@ let Predicates = [HasLOR] in {
   def STLLRH0 : InstAlias<"stllrh\t$Rt, [$Rn, #0]",  (STLLRH   GPR32: $Rt, 
GPR64sp:$Rn)>;
 }
 
+// v9.6-a Unprivileged load store operations
+let Predicates = [HasLSUI] in {
+defm LDTXRW : LoadUnprivilegedLSUI<0b10, GPR32, "ldtxr">;
+defm LDTXRX : LoadUnprivilegedLSUI<0b11, GPR64, "ldtxr">;
+
+def LDATXRW : LoadExclusiveLSUI <0b10, 1, 1, GPR32, "ldatxr">;
+def LDATXRX : LoadExclusiveLSUI <0b11, 1, 1, GPR64, "ldatxr">;
+
+defm STTXRW : StoreUnprivilegedLSUI<0b10, GPR32, "sttxr">;
+defm STTXRX : StoreUnprivilegedLSUI<0b11, GPR64, "sttxr">;
+
+def STLTXRW : StoreExclusiveLSUI<0b10, 0, 1, GPR32, "stltxr">;

nasherm wrote:

Done

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-17 Thread Nashe Mncube via cfe-commits 


@@ -4660,6 +4746,21 @@ let Predicates = [HasLOR] in {
   def STLLRH0 : InstAlias<"stllrh\t$Rt, [$Rn, #0]",  (STLLRH   GPR32: $Rt, 
GPR64sp:$Rn)>;
 }
 
+// v9.6-a Unprivileged load store operations
+let Predicates = [HasLSUI] in {
+defm LDTXRW : LoadUnprivilegedLSUI<0b10, GPR32, "ldtxr">;
+defm LDTXRX : LoadUnprivilegedLSUI<0b11, GPR64, "ldtxr">;
+
+def LDATXRW : LoadExclusiveLSUI <0b10, 1, 1, GPR32, "ldatxr">;
+def LDATXRX : LoadExclusiveLSUI <0b11, 1, 1, GPR64, "ldatxr">;
+
+defm STTXRW : StoreUnprivilegedLSUI<0b10, GPR32, "sttxr">;

nasherm wrote:

Done

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-17 Thread Nashe Mncube via cfe-commits 


@@ -4660,6 +4746,21 @@ let Predicates = [HasLOR] in {
   def STLLRH0 : InstAlias<"stllrh\t$Rt, [$Rn, #0]",  (STLLRH   GPR32: $Rt, 
GPR64sp:$Rn)>;
 }
 
+// v9.6-a Unprivileged load store operations
+let Predicates = [HasLSUI] in {
+defm LDTXRW : LoadUnprivilegedLSUI<0b10, GPR32, "ldtxr">;
+defm LDTXRX : LoadUnprivilegedLSUI<0b11, GPR64, "ldtxr">;

nasherm wrote:

Done

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-17 Thread Nashe Mncube via cfe-commits 


@@ -2568,12 +2580,59 @@ defm CASPA  : CompareAndSwapPair<1, 0, "a">;
 defm CASPL  : CompareAndSwapPair<0, 1, "l">;
 defm CASPAL : CompareAndSwapPair<1, 1, "al">;
 
+// v9.6-a atomic CAST

nasherm wrote:

Done

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-17 Thread Nashe Mncube via cfe-commits 


@@ -4660,6 +4746,21 @@ let Predicates = [HasLOR] in {
   def STLLRH0 : InstAlias<"stllrh\t$Rt, [$Rn, #0]",  (STLLRH   GPR32: $Rt, 
GPR64sp:$Rn)>;
 }
 
+// v9.6-a Unprivileged load store operations
+let Predicates = [HasLSUI] in {
+defm LDTXRW : LoadUnprivilegedLSUI<0b10, GPR32, "ldtxr">;
+defm LDTXRX : LoadUnprivilegedLSUI<0b11, GPR64, "ldtxr">;
+
+def LDATXRW : LoadExclusiveLSUI <0b10, 1, 1, GPR32, "ldatxr">;

nasherm wrote:

Done

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-22 Thread Nashe Mncube via cfe-commits 

nasherm wrote:

@CarolineConcatto I hope I answered your question. If so I'm hoping to merge 
this by EOD if there's no more to do

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-22 Thread Nashe Mncube via cfe-commits 


@@ -988,6 +988,22 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
   Name = std::string(AT->Name);
 }
 break;
+// Overlaps with AT and DC

nasherm wrote:

The newly added DC instructions map to the same case (15) as the AT 
instructions as they have overlapping encodings 

https://github.com/llvm/llvm-project/pull/112341
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[clang] [llvm] [LLVM][MC][AArch64] Assembler support for Armv9.6-A memory systems extensions (PR #112341)

2024-10-22 Thread Nashe Mncube via cfe-commits 

https://github.com/nasherm closed 
https://github.com/llvm/llvm-project/pull/112341
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