[PATCH] D92935: Introduce support for PowerPC devices with an Embedded Floating-point APU version 2 (efpu2)

2021-07-28 Thread Michael Kiausch via Phabricator via cfe-commits 
kiausch added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/spe.ll:2
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
-; RUN:  -mattr=+spe |  FileCheck %s
+; RUN: split-file %s %t
+; RUN: llc -verify-machineinstrs < %t/single.ll 
-mtriple=powerpc-unknown-linux-gnu \

jrtc27 wrote:
> jrtc27 wrote:
> > jrtc27 wrote:
> > > This breaks being able to run update_llc_test_checks.py without first 
> > > running the test itself to generate the files
> > In fact it breaks it completely, update_llc_test_checks.py doesn't support 
> > the %t substitutions, and even if it did it's unclear what that even means; 
> > should it update the CHECK lines in the file with the RUN lines or the 
> > files being used by FileCheck?
> > 
> > This should have just been manually split.
> Most of this is also entirely unnecessary if you use 
> --check-prefixes=CHECK,SPE/EFPU2; update_llc_test_checks.py will merge CHECK 
> lines when possible. The only thing that needs splitting is the hwdouble 
> test, by just putting it in a separate file (or using sed to preprocess the 
> file so SPE sees the test uncommented and EFPU2 sees the test commented out, 
> but that seems unnecessary, though does work). I'll write a patch for the 
> former.
In the first revison of this patch the tests were split into two separate files 
for SPE and EFPU2 but this was legitimately criticised for duplicating the 
single precision tests. This is why I tried to use the split-file feature.
My intention was to
- run the single.ll part on both, spe and efpu2
- run the double.ll part on both, spe and efpu2, but with different assertions. 
When using efpu2 there are no hardware double instructions generated but 
library calls, and I just wanted to check that in this case the correct calls 
were genereated. The assertions for these cases were hand-crafted because I was 
not really able to get the update_llc_test_checks.py to work. The comment above 
came from the original test file.
- the hwdouble.ll part needs to be excluded because this uses an assembly 
instruction which is not available on efpu2 devices.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D92935: Introduce support for PowerPC devices with an Embedded Floating-point APU version 2 (efpu2)

2020-12-09 Thread Michael Kiausch via Phabricator via cfe-commits 
kiausch created this revision.
kiausch added reviewers: nemanjai, jhibbits.
Herald added subscribers: dang, steven.zhang, shchenz, kbarton, hiraditya.
kiausch requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

PowerPC cores like e200z759n3 [1] using an efpu2 only support single precision 
hardware floating point instructions.
The single precision instructions efs* and evfs* are identical to the spe float 
instructions while efd* and evfd* instructions trigger a not implemented 
exception.

This patch introduces a new command line option -mefpu2 which leads to 
single-hardware / double-software code generation.

I added a regression test efpu2.ll based on spe.ll where all single tests are 
identical to the tests in spe.ll while the double tests taken from spe.ll were 
modified to basically check that the correct library calls are generated.

[1] Core reference: 
https://www.nxp.com/files-static/32bit/doc/ref_manual/e200z759CRM.pdf


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92935

Files:
  clang/include/clang/Driver/Options.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/test/CodeGen/PowerPC/efpu2.ll

Index: llvm/test/CodeGen/PowerPC/efpu2.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/efpu2.ll
@@ -0,0 +1,1141 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
+; RUN:  -mattr=+efpu2 |  FileCheck %s
+
+; Single tests 
+; identical to tests in spe.ll
+
+declare float @llvm.fabs.float(float)
+define float @test_float_abs(float %a) #0 {
+; CHECK-LABEL: test_float_abs:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efsabs 3, 3
+; CHECK-NEXT:blr
+  entry:
+%0 = tail call float @llvm.fabs.float(float %a)
+ret float %0
+}
+
+define float @test_fnabs(float %a) #0 {
+; CHECK-LABEL: test_fnabs:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efsnabs 3, 3
+; CHECK-NEXT:blr
+  entry:
+%0 = tail call float @llvm.fabs.float(float %a)
+%sub = fsub float -0.00e+00, %0
+ret float %sub
+}
+
+define float @test_fdiv(float %a, float %b) {
+; CHECK-LABEL: test_fdiv:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efsdiv 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %v = fdiv float %a, %b
+  ret float %v
+
+}
+
+define float @test_fmul(float %a, float %b) {
+; CHECK-LABEL: test_fmul:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efsmul 3, 3, 4
+; CHECK-NEXT:blr
+  entry:
+  %v = fmul float %a, %b
+  ret float %v
+}
+
+define float @test_fadd(float %a, float %b) {
+; CHECK-LABEL: test_fadd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efsadd 3, 3, 4
+; CHECK-NEXT:blr
+  entry:
+  %v = fadd float %a, %b
+  ret float %v
+}
+
+define float @test_fsub(float %a, float %b) {
+; CHECK-LABEL: test_fsub:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efssub 3, 3, 4
+; CHECK-NEXT:blr
+  entry:
+  %v = fsub float %a, %b
+  ret float %v
+}
+
+define float @test_fneg(float %a) {
+; CHECK-LABEL: test_fneg:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efsneg 3, 3
+; CHECK-NEXT:blr
+  entry:
+  %v = fsub float -0.0, %a
+  ret float %v
+}
+
+; todo
+define float @test_dtos(double %a) {
+; CHECK-LABEL: test_dtos:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mflr 0
+; CHECK-NEXT:stw 0, 4(1)
+; CHECK-NEXT:stwu 1, -16(1)
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:.cfi_offset lr, 4
+; CHECK-NEXT:bl __truncdfsf2
+; CHECK-NEXT:lwz 0, 20(1)
+; CHECK-NEXT:addi 1, 1, 16
+; CHECK-NEXT:mtlr 0
+; CHECK-NEXT:blr
+  entry:
+  %v = fptrunc double %a to float
+  ret float %v
+}
+
+define i32 @test_fcmpgt(float %a, float %b) {
+; CHECK-LABEL: test_fcmpgt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:stwu 1, -16(1)
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:efscmpgt 0, 3, 4
+; CHECK-NEXT:ble 0, .LBB8_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:li 3, 1
+; CHECK-NEXT:b .LBB8_3
+; CHECK-NEXT:  .LBB8_2: # %fa
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:  .LBB8_3: # %ret
+; CHECK-NEXT:stw 3, 12(1)
+; CHECK-NEXT:lwz 3, 12(1)
+; CHECK-NEXT:addi 1, 1, 16
+; CHECK-NEXT:blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp ogt float %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_fcmpugt(float %a, float %b) {
+; CHECK-LABEL: test_fcmpugt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:stwu 1, -16(1)
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:efscmpeq 0, 4, 4
+; CHECK-NEXT:bc 4, 1, .LBB9_4
+; CHEC

[PATCH] D92935: Introduce support for PowerPC devices with an Embedded Floating-point APU version 2 (efpu2)

2020-12-10 Thread Michael Kiausch via Phabricator via cfe-commits 
kiausch updated this revision to Diff 310853.
kiausch added a comment.

fixed format errors


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Files:
  clang/include/clang/Driver/Options.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/test/CodeGen/PowerPC/efpu2.ll

Index: llvm/test/CodeGen/PowerPC/efpu2.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/efpu2.ll
@@ -0,0 +1,1141 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
+; RUN:  -mattr=+efpu2 |  FileCheck %s
+
+; Single tests 
+; identical to tests in spe.ll
+
+declare float @llvm.fabs.float(float)
+define float @test_float_abs(float %a) #0 {
+; CHECK-LABEL: test_float_abs:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efsabs 3, 3
+; CHECK-NEXT:blr
+  entry:
+%0 = tail call float @llvm.fabs.float(float %a)
+ret float %0
+}
+
+define float @test_fnabs(float %a) #0 {
+; CHECK-LABEL: test_fnabs:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efsnabs 3, 3
+; CHECK-NEXT:blr
+  entry:
+%0 = tail call float @llvm.fabs.float(float %a)
+%sub = fsub float -0.00e+00, %0
+ret float %sub
+}
+
+define float @test_fdiv(float %a, float %b) {
+; CHECK-LABEL: test_fdiv:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efsdiv 3, 3, 4
+; CHECK-NEXT:blr
+entry:
+  %v = fdiv float %a, %b
+  ret float %v
+
+}
+
+define float @test_fmul(float %a, float %b) {
+; CHECK-LABEL: test_fmul:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efsmul 3, 3, 4
+; CHECK-NEXT:blr
+  entry:
+  %v = fmul float %a, %b
+  ret float %v
+}
+
+define float @test_fadd(float %a, float %b) {
+; CHECK-LABEL: test_fadd:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efsadd 3, 3, 4
+; CHECK-NEXT:blr
+  entry:
+  %v = fadd float %a, %b
+  ret float %v
+}
+
+define float @test_fsub(float %a, float %b) {
+; CHECK-LABEL: test_fsub:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efssub 3, 3, 4
+; CHECK-NEXT:blr
+  entry:
+  %v = fsub float %a, %b
+  ret float %v
+}
+
+define float @test_fneg(float %a) {
+; CHECK-LABEL: test_fneg:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:efsneg 3, 3
+; CHECK-NEXT:blr
+  entry:
+  %v = fsub float -0.0, %a
+  ret float %v
+}
+
+; todo
+define float @test_dtos(double %a) {
+; CHECK-LABEL: test_dtos:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mflr 0
+; CHECK-NEXT:stw 0, 4(1)
+; CHECK-NEXT:stwu 1, -16(1)
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:.cfi_offset lr, 4
+; CHECK-NEXT:bl __truncdfsf2
+; CHECK-NEXT:lwz 0, 20(1)
+; CHECK-NEXT:addi 1, 1, 16
+; CHECK-NEXT:mtlr 0
+; CHECK-NEXT:blr
+  entry:
+  %v = fptrunc double %a to float
+  ret float %v
+}
+
+define i32 @test_fcmpgt(float %a, float %b) {
+; CHECK-LABEL: test_fcmpgt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:stwu 1, -16(1)
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:efscmpgt 0, 3, 4
+; CHECK-NEXT:ble 0, .LBB8_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:li 3, 1
+; CHECK-NEXT:b .LBB8_3
+; CHECK-NEXT:  .LBB8_2: # %fa
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:  .LBB8_3: # %ret
+; CHECK-NEXT:stw 3, 12(1)
+; CHECK-NEXT:lwz 3, 12(1)
+; CHECK-NEXT:addi 1, 1, 16
+; CHECK-NEXT:blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp ogt float %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_fcmpugt(float %a, float %b) {
+; CHECK-LABEL: test_fcmpugt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:stwu 1, -16(1)
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:efscmpeq 0, 4, 4
+; CHECK-NEXT:bc 4, 1, .LBB9_4
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:efscmpeq 0, 3, 3
+; CHECK-NEXT:bc 4, 1, .LBB9_4
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:efscmpgt 0, 3, 4
+; CHECK-NEXT:bc 12, 1, .LBB9_4
+; CHECK-NEXT:  # %bb.3: # %fa
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:b .LBB9_5
+; CHECK-NEXT:  .LBB9_4: # %tr
+; CHECK-NEXT:li 3, 1
+; CHECK-NEXT:  .LBB9_5: # %ret
+; CHECK-NEXT:stw 3, 12(1)
+; CHECK-NEXT:lwz 3, 12(1)
+; CHECK-NEXT:addi 1, 1, 16
+; CHECK-NEXT:blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp ugt float %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_fcmple(float %a, float %b) {
+; CHECK-LABEL: test_fcmple:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:stwu 1,

[PATCH] D92935: Introduce support for PowerPC devices with an Embedded Floating-point APU version 2 (efpu2)

2021-01-04 Thread Michael Kiausch via Phabricator via cfe-commits 
kiausch added a comment.

Ping.


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[PATCH] D92935: Introduce support for PowerPC devices with an Embedded Floating-point APU version 2 (efpu2)

2021-01-04 Thread Michael Kiausch via Phabricator via cfe-commits 
kiausch added a comment.

Regarding similar GCC options:

AFAIK GCC has had the spe options -msingle-float and -mdouble-float until spe 
support was dropped after version 8.3.
These options would kind of match here, but they are already used as MIPS 
subtarget features in LLVM and I was not able to find out if and how it is 
possible to use identical target features for multiple targets and if this is a 
good idea at all? If somebody could point out how this can be done I'm happy to 
change the options...


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[PATCH] D92935: Introduce support for PowerPC devices with an Embedded Floating-point APU version 2 (efpu2)

2021-01-05 Thread Michael Kiausch via Phabricator via cfe-commits 
kiausch updated this revision to Diff 314566.
kiausch edited the summary of this revision.
kiausch added a comment.

implemented review suggestions:

- updated clang/docs/ClangCommandLineReference.rst
- removed unneccessary HasEFPU2() wrapper function
- initialize HasEFPU member
- merged tests into spe.ll to remove identical parts


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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Driver/Options.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/test/CodeGen/PowerPC/spe.ll

Index: llvm/test/CodeGen/PowerPC/spe.ll
===
--- llvm/test/CodeGen/PowerPC/spe.ll
+++ llvm/test/CodeGen/PowerPC/spe.ll
@@ -1,6 +1,18 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
-; RUN:  -mattr=+spe |  FileCheck %s
+; RUN: split-file %s %t
+; RUN: llc -verify-machineinstrs < %t/single.ll -mtriple=powerpc-unknown-linux-gnu \
+; RUN:  -mattr=+spe |  FileCheck %t/single.ll
+; RUN: llc -verify-machineinstrs < %t/double.ll -mtriple=powerpc-unknown-linux-gnu \
+; RUN:  -mattr=+spe |  FileCheck %t/double.ll -check-prefix=SPE
+; RUN: llc -verify-machineinstrs < %t/hwdouble.ll -mtriple=powerpc-unknown-linux-gnu \
+; RUN:  -mattr=+spe |  FileCheck %t/hwdouble.ll -check-prefix=SPE
+; RUN: llc -verify-machineinstrs < %t/single.ll -mtriple=powerpc-unknown-linux-gnu \
+; RUN:  -mattr=+efpu2 |  FileCheck %t/single.ll
+; RUN: llc -verify-machineinstrs < %t/double.ll -mtriple=powerpc-unknown-linux-gnu \
+; RUN:  -mattr=+efpu2 |  FileCheck %t/double.ll -check-prefix=EFPU2
+
+;--- single.ll
+; single tests (identical for -mattr=+spe and -mattr=+efpu2)
 
 declare float @llvm.fabs.float(float)
 define float @test_float_abs(float %a) #0 {
@@ -75,30 +87,19 @@
   ret float %v
 }
 
-define float @test_dtos(double %a) {
-; CHECK-LABEL: test_dtos:
-; CHECK:   # %bb.0: # %entry
-; CHECK-NEXT:evmergelo 3, 3, 4
-; CHECK-NEXT:efscfd 3, 3
-; CHECK-NEXT:blr
-  entry:
-  %v = fptrunc double %a to float
-  ret float %v
-}
-
 define i32 @test_fcmpgt(float %a, float %b) {
 ; CHECK-LABEL: test_fcmpgt:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:stwu 1, -16(1)
 ; CHECK-NEXT:.cfi_def_cfa_offset 16
 ; CHECK-NEXT:efscmpgt 0, 3, 4
-; CHECK-NEXT:ble 0, .LBB8_2
+; CHECK-NEXT:ble 0, .LBB7_2
 ; CHECK-NEXT:  # %bb.1: # %tr
 ; CHECK-NEXT:li 3, 1
-; CHECK-NEXT:b .LBB8_3
-; CHECK-NEXT:  .LBB8_2: # %fa
+; CHECK-NEXT:b .LBB7_3
+; CHECK-NEXT:  .LBB7_2: # %fa
 ; CHECK-NEXT:li 3, 0
-; CHECK-NEXT:  .LBB8_3: # %ret
+; CHECK-NEXT:  .LBB7_3: # %ret
 ; CHECK-NEXT:stw 3, 12(1)
 ; CHECK-NEXT:lwz 3, 12(1)
 ; CHECK-NEXT:addi 1, 1, 16
@@ -124,19 +125,19 @@
 ; CHECK-NEXT:stwu 1, -16(1)
 ; CHECK-NEXT:.cfi_def_cfa_offset 16
 ; CHECK-NEXT:efscmpeq 0, 4, 4
-; CHECK-NEXT:bc 4, 1, .LBB9_4
+; CHECK-NEXT:bc 4, 1, .LBB8_4
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:efscmpeq 0, 3, 3
-; CHECK-NEXT:bc 4, 1, .LBB9_4
+; CHECK-NEXT:bc 4, 1, .LBB8_4
 ; CHECK-NEXT:  # %bb.2: # %entry
 ; CHECK-NEXT:efscmpgt 0, 3, 4
-; CHECK-NEXT:bc 12, 1, .LBB9_4
+; CHECK-NEXT:bc 12, 1, .LBB8_4
 ; CHECK-NEXT:  # %bb.3: # %fa
 ; CHECK-NEXT:li 3, 0
-; CHECK-NEXT:b .LBB9_5
-; CHECK-NEXT:  .LBB9_4: # %tr
+; CHECK-NEXT:b .LBB8_5
+; CHECK-NEXT:  .LBB8_4: # %tr
 ; CHECK-NEXT:li 3, 1
-; CHECK-NEXT:  .LBB9_5: # %ret
+; CHECK-NEXT:  .LBB8_5: # %ret
 ; CHECK-NEXT:stw 3, 12(1)
 ; CHECK-NEXT:lwz 3, 12(1)
 ; CHECK-NEXT:addi 1, 1, 16
@@ -162,19 +163,19 @@
 ; CHECK-NEXT:stwu 1, -16(1)
 ; CHECK-NEXT:.cfi_def_cfa_offset 16
 ; CHECK-NEXT:efscmpeq 0, 3, 3
-; CHECK-NEXT:bc 4, 1, .LBB10_4
+; CHECK-NEXT:bc 4, 1, .LBB9_4
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:efscmpeq 0, 4, 4
-; CHECK-NEXT:bc 4, 1, .LBB10_4
+; CHECK-NEXT:bc 4, 1, .LBB9_4
 ; CHECK-NEXT:  # %bb.2: # %entry
 ; CHECK-NEXT:efscmpgt 0, 3, 4
-; CHECK-NEXT:bc 12, 1, .LBB10_4
+; CHECK-NEXT:bc 12, 1, .LBB9_4
 ; CHECK-NEXT:  # %bb.3: # %tr
 ; CHECK-NEXT:li 3, 1
-; CHECK-NEXT:b .LBB10_5
-; CHECK-NEXT:  .LBB10_4: # %fa
+; CHECK-NEXT:b .LBB9_5
+; CHECK-NEXT:  .LBB9_4: # %fa
 ; CHECK-NEXT:li 3, 0
-; CHECK-NEXT:  .LBB10_5: # %ret
+; CHECK-NEXT:  .LBB9_5: # %ret
 ; CHECK-NEXT:stw 3, 12(1)
 ; CHECK-NEXT:lwz 3, 12(1)
 ; CHECK-NEXT:addi 1, 1, 16
@@ -200,13 +201,13 @@
 ; CHECK-NEXT:stwu 1, -16(1)
 ; CHECK-NEXT:.cfi_def_cfa_offset 16
 ; CHECK-NEXT:efscmpgt 0, 3, 4
-; CHECK-NEXT:bgt 0, .LBB11_2
+; CHECK-NEXT:bgt 0, .LBB10_2
 ; CHECK-NEXT:  # %bb.1: # %tr
 ; CHECK-NEXT:li 3, 1
-; CHECK-NEXT:b .LBB11_3
-; CHECK

[PATCH] D92935: Introduce support for PowerPC devices with an Embedded Floating-point APU version 2 (efpu2)

2021-01-05 Thread Michael Kiausch via Phabricator via cfe-commits 
kiausch marked 4 inline comments as done.
kiausch added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/efpu2.ll:6
+; Single tests 
+; identical to tests in spe.ll
+

nemanjai wrote:
> It might make sense to just add a RUN line in that test case rather than 
> stating in a comment that they are identical (i.e. they may not be identical 
> if the original one changes down the road).
Merged the tests into spe.ll which is now executed multiple times using 
additional RUN lines.
Using split-file the file is separeted into a single-precision part which is 
supposed to generate identical code to the spe implementation and a 
double-precision part which is checked to generate different results for the 
efpu2 option.
Is that kind of what you had in mind?


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[PATCH] D92935: Introduce support for PowerPC devices with an Embedded Floating-point APU version 2 (efpu2)

2021-01-07 Thread Michael Kiausch via Phabricator via cfe-commits 
kiausch updated this revision to Diff 315119.
kiausch marked an inline comment as done.
kiausch added a comment.

- enable -mspe if -mefpu2 is defined in clang interface
- added clang feature test


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Files:
  clang/docs/ClangCommandLineReference.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/Driver/ppc-features.cpp
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/test/CodeGen/PowerPC/spe.ll

Index: llvm/test/CodeGen/PowerPC/spe.ll
===
--- llvm/test/CodeGen/PowerPC/spe.ll
+++ llvm/test/CodeGen/PowerPC/spe.ll
@@ -1,6 +1,18 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
-; RUN:  -mattr=+spe |  FileCheck %s
+; RUN: split-file %s %t
+; RUN: llc -verify-machineinstrs < %t/single.ll -mtriple=powerpc-unknown-linux-gnu \
+; RUN:  -mattr=+spe |  FileCheck %t/single.ll
+; RUN: llc -verify-machineinstrs < %t/double.ll -mtriple=powerpc-unknown-linux-gnu \
+; RUN:  -mattr=+spe |  FileCheck %t/double.ll -check-prefix=SPE
+; RUN: llc -verify-machineinstrs < %t/hwdouble.ll -mtriple=powerpc-unknown-linux-gnu \
+; RUN:  -mattr=+spe |  FileCheck %t/hwdouble.ll -check-prefix=SPE
+; RUN: llc -verify-machineinstrs < %t/single.ll -mtriple=powerpc-unknown-linux-gnu \
+; RUN:  -mattr=+efpu2 |  FileCheck %t/single.ll
+; RUN: llc -verify-machineinstrs < %t/double.ll -mtriple=powerpc-unknown-linux-gnu \
+; RUN:  -mattr=+efpu2 |  FileCheck %t/double.ll -check-prefix=EFPU2
+
+;--- single.ll
+; single tests (identical for -mattr=+spe and -mattr=+efpu2)
 
 declare float @llvm.fabs.float(float)
 define float @test_float_abs(float %a) #0 {
@@ -75,30 +87,19 @@
   ret float %v
 }
 
-define float @test_dtos(double %a) {
-; CHECK-LABEL: test_dtos:
-; CHECK:   # %bb.0: # %entry
-; CHECK-NEXT:evmergelo 3, 3, 4
-; CHECK-NEXT:efscfd 3, 3
-; CHECK-NEXT:blr
-  entry:
-  %v = fptrunc double %a to float
-  ret float %v
-}
-
 define i32 @test_fcmpgt(float %a, float %b) {
 ; CHECK-LABEL: test_fcmpgt:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:stwu 1, -16(1)
 ; CHECK-NEXT:.cfi_def_cfa_offset 16
 ; CHECK-NEXT:efscmpgt 0, 3, 4
-; CHECK-NEXT:ble 0, .LBB8_2
+; CHECK-NEXT:ble 0, .LBB7_2
 ; CHECK-NEXT:  # %bb.1: # %tr
 ; CHECK-NEXT:li 3, 1
-; CHECK-NEXT:b .LBB8_3
-; CHECK-NEXT:  .LBB8_2: # %fa
+; CHECK-NEXT:b .LBB7_3
+; CHECK-NEXT:  .LBB7_2: # %fa
 ; CHECK-NEXT:li 3, 0
-; CHECK-NEXT:  .LBB8_3: # %ret
+; CHECK-NEXT:  .LBB7_3: # %ret
 ; CHECK-NEXT:stw 3, 12(1)
 ; CHECK-NEXT:lwz 3, 12(1)
 ; CHECK-NEXT:addi 1, 1, 16
@@ -124,19 +125,19 @@
 ; CHECK-NEXT:stwu 1, -16(1)
 ; CHECK-NEXT:.cfi_def_cfa_offset 16
 ; CHECK-NEXT:efscmpeq 0, 4, 4
-; CHECK-NEXT:bc 4, 1, .LBB9_4
+; CHECK-NEXT:bc 4, 1, .LBB8_4
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:efscmpeq 0, 3, 3
-; CHECK-NEXT:bc 4, 1, .LBB9_4
+; CHECK-NEXT:bc 4, 1, .LBB8_4
 ; CHECK-NEXT:  # %bb.2: # %entry
 ; CHECK-NEXT:efscmpgt 0, 3, 4
-; CHECK-NEXT:bc 12, 1, .LBB9_4
+; CHECK-NEXT:bc 12, 1, .LBB8_4
 ; CHECK-NEXT:  # %bb.3: # %fa
 ; CHECK-NEXT:li 3, 0
-; CHECK-NEXT:b .LBB9_5
-; CHECK-NEXT:  .LBB9_4: # %tr
+; CHECK-NEXT:b .LBB8_5
+; CHECK-NEXT:  .LBB8_4: # %tr
 ; CHECK-NEXT:li 3, 1
-; CHECK-NEXT:  .LBB9_5: # %ret
+; CHECK-NEXT:  .LBB8_5: # %ret
 ; CHECK-NEXT:stw 3, 12(1)
 ; CHECK-NEXT:lwz 3, 12(1)
 ; CHECK-NEXT:addi 1, 1, 16
@@ -162,19 +163,19 @@
 ; CHECK-NEXT:stwu 1, -16(1)
 ; CHECK-NEXT:.cfi_def_cfa_offset 16
 ; CHECK-NEXT:efscmpeq 0, 3, 3
-; CHECK-NEXT:bc 4, 1, .LBB10_4
+; CHECK-NEXT:bc 4, 1, .LBB9_4
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:efscmpeq 0, 4, 4
-; CHECK-NEXT:bc 4, 1, .LBB10_4
+; CHECK-NEXT:bc 4, 1, .LBB9_4
 ; CHECK-NEXT:  # %bb.2: # %entry
 ; CHECK-NEXT:efscmpgt 0, 3, 4
-; CHECK-NEXT:bc 12, 1, .LBB10_4
+; CHECK-NEXT:bc 12, 1, .LBB9_4
 ; CHECK-NEXT:  # %bb.3: # %tr
 ; CHECK-NEXT:li 3, 1
-; CHECK-NEXT:b .LBB10_5
-; CHECK-NEXT:  .LBB10_4: # %fa
+; CHECK-NEXT:b .LBB9_5
+; CHECK-NEXT:  .LBB9_4: # %fa
 ; CHECK-NEXT:li 3, 0
-; CHECK-NEXT:  .LBB10_5: # %ret
+; CHECK-NEXT:  .LBB9_5: # %ret
 ; CHECK-NEXT:stw 3, 12(1)
 ; CHECK-NEXT:lwz 3, 12(1)
 ; CHECK-NEXT:addi 1, 1, 16
@@ -200,13 +201,13 @@
 ; CHECK-NEXT:stwu 1, -16(1)
 ; CHECK-NEXT:.cfi_def_cfa_offset 16
 ; CHECK-NEXT:efscmpgt 0, 3, 4
-; CHECK-NEXT:bgt 0, .LBB11_2
+; CHECK-NEXT:bgt 0, .LBB10_2
 ; CHECK-NEXT:  # %bb.1: # %tr
 ; CHECK-NEXT:li 3, 1
-; CHECK-NEXT:b .LBB11_3
-; CHECK-NEXT:  .LBB11_2: # %fa
+; CHECK-NEXT:b .LBB10_3
+; CHECK-NEX

[PATCH] D92935: Introduce support for PowerPC devices with an Embedded Floating-point APU version 2 (efpu2)

2021-01-12 Thread Michael Kiausch via Phabricator via cfe-commits 
kiausch added a comment.

Could somebody with write access please commit this patch if there are no 
further objections? Thanks!


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