[clang] e8dd7ec - Revert "[AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics (#71795)"
Author: Matt Devereau
Date: 2023-11-16T11:01:27Z
New Revision: e8dd7ecbc4668cdf767478fd9b1dd666c38d0105
URL:
https://github.com/llvm/llvm-project/commit/e8dd7ecbc4668cdf767478fd9b1dd666c38d0105
DIFF:
https://github.com/llvm/llvm-project/commit/e8dd7ecbc4668cdf767478fd9b1dd666c38d0105.diff
LOG: Revert "[AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics
(#71795)"
This reverts commit cc1244980b74f45a06e2002a33444ce757b577aa.
Added:
Modified:
clang/include/clang/Basic/arm_sme.td
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
llvm/lib/Target/AArch64/SMEInstrFormats.td
Removed:
clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c
llvm/test/CodeGen/AArch64/sme2-intrinsics-zt0.ll
diff --git a/clang/include/clang/Basic/arm_sme.td
b/clang/include/clang/Basic/arm_sme.td
index fb3f54ecff95080..b5655afdf419ecf 100644
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -298,11 +298,3 @@ multiclass ZAAddSub {
defm SVADD : ZAAddSub<"add">;
defm SVSUB : ZAAddSub<"sub">;
-
-//
-// Spill and fill of ZT0
-//
-let TargetGuard = "sme2" in {
- def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
[ImmCheck<0, ImmCheck0_0>]>;
- def SVSTR_ZT : Inst<"svstr_zt", "vi%", "", MergeNone, "aarch64_sme_str_zt",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
[ImmCheck<0, ImmCheck0_0>]>;
-}
diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c
deleted file mode 100644
index 7ae6769c8237f6c..000
--- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c
+++ /dev/null
@@ -1,51 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-
-// REQUIRES: aarch64-registered-target
-
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s |
opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x
c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
-check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror
-Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim |
FileCheck %s
-// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror
-Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim |
FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
-
-#include
-
-#ifdef SVE_OVERLOADED_FORMS
-// A simple used,unused... macro, long enough to represent any SVE builtin.
-#define SVE_ACLE_FUNC(A1,A2_UNUSED) A1
-#else
-#define SVE_ACLE_FUNC(A1,A2) A1##A2
-#endif
-
-// LDR ZT0
-
-// CHECK-LABEL: @test_svldr_zt(
-// CHECK-NEXT: entry:
-// CHECK-NEXT:tail call void @llvm.aarch64.sme.ldr.zt(i32 0, ptr
[[BASE:%.*]])
-// CHECK-NEXT:ret void
-//
-// CPP-CHECK-LABEL: @_Z13test_svldr_ztPKv(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT:tail call void @llvm.aarch64.sme.ldr.zt(i32 0, ptr
[[BASE:%.*]])
-// CPP-CHECK-NEXT:ret void
-//
-void test_svldr_zt(const void *base) __arm_streaming_compatible
__arm_shared_za __arm_preserves_za {
- svldr_zt(0, base);
-} ;
-
-
-// STR ZT0
-
-// CHECK-LABEL: @test_svstr_zt(
-// CHECK-NEXT: entry:
-// CHECK-NEXT:tail call void @llvm.aarch64.sme.str.zt(i32 0, ptr
[[BASE:%.*]])
-// CHECK-NEXT:ret void
-//
-// CPP-CHECK-LABEL: @_Z13test_svstr_ztPv(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT:tail call void @llvm.aarch64.sme.str.zt(i32 0, ptr
[[BASE:%.*]])
-// CPP-CHECK-NEXT:ret void
-//
-void test_svstr_zt(void *base) __arm_streaming_compatible __arm_shared_za
__arm_preserves_za {
- svstr_zt(0, base);
-}
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td
b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 9164604f7d78cbc..a42e2c49cb477ba 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -2679,10 +2679,10 @@ let TargetPrefix = "aarch64" in {
def int_aarch64_sme_st1q_vert : SME_Load_Store_Int
[clang] 5fe7ae8 - [AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics (#72849)
Author: Matt Devereau
Date: 2023-12-01T09:34:38Z
New Revision: 5fe7ae848cc6cb2afc3aab332743ffa2bb635fc3
URL:
https://github.com/llvm/llvm-project/commit/5fe7ae848cc6cb2afc3aab332743ffa2bb635fc3
DIFF:
https://github.com/llvm/llvm-project/commit/5fe7ae848cc6cb2afc3aab332743ffa2bb635fc3.diff
LOG: [AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics (#72849)
Adds the builtins:
void svldr_zt(uint64_t zt, const void *rn)
void svstr_zt(uint64_t zt, void *rn)
And the intrinsics:
call void @llvm.aarch64.sme.ldr.zt(i32, ptr)
tail call void @llvm.aarch64.sme.str.zt(i32, ptr)
Patch by: Kerry McLaughlin kerry.mclaugh...@arm.com
Added:
clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c
llvm/test/CodeGen/AArch64/sme2-intrinsics-zt0.ll
Modified:
clang/include/clang/Basic/arm_sme.td
clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
llvm/lib/Target/AArch64/SMEInstrFormats.td
Removed:
diff --git a/clang/include/clang/Basic/arm_sme.td
b/clang/include/clang/Basic/arm_sme.td
index d55deeaa40bbcd5..7aae3c832bb1fe2 100644
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -314,3 +314,11 @@ let TargetGuard = "sme2" in {
def SVBMOPS : Inst<"svbmops_za32[_{d}]_m", "viPPdd", "iUi", MergeNone,
"aarch64_sme_bmops_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
}
+
+//
+// Spill and fill of ZT0
+//
+let TargetGuard = "sme2" in {
+ def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
[ImmCheck<0, ImmCheck0_0>]>;
+ def SVSTR_ZT : Inst<"svstr_zt", "vi%", "", MergeNone, "aarch64_sme_str_zt",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
[ImmCheck<0, ImmCheck0_0>]>;
+}
diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c
new file mode 100644
index 000..126a4fc1045853f
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p
mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p
mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -o /dev/null %s
+
+#include
+
+// LDR ZT0
+
+// CHECK-LABEL: @test_svldr_zt(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.ldr.zt(i32 0, ptr
[[BASE:%.*]])
+// CHECK-NEXT:ret void
+//
+// CPP-CHECK-LABEL: @_Z13test_svldr_ztPKv(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT:tail call void @llvm.aarch64.sme.ldr.zt(i32 0, ptr
[[BASE:%.*]])
+// CPP-CHECK-NEXT:ret void
+//
+void test_svldr_zt(const void *base) __arm_streaming_compatible
__arm_shared_za __arm_preserves_za {
+ svldr_zt(0, base);
+}
+
+// STR ZT0
+
+// CHECK-LABEL: @test_svstr_zt(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str.zt(i32 0, ptr
[[BASE:%.*]])
+// CHECK-NEXT:ret void
+//
+// CPP-CHECK-LABEL: @_Z13test_svstr_ztPv(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT:tail call void @llvm.aarch64.sme.str.zt(i32 0, ptr
[[BASE:%.*]])
+// CPP-CHECK-NEXT:ret void
+//
+void test_svstr_zt(void *base) __arm_streaming_compatible __arm_shared_za
__arm_preserves_za {
+ svstr_zt(0, base);
+}
diff --git a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp
b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp
index 4c35a238d9f9e2c..70987ad395f735a 100644
--- a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp
+++ b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \
-// RUN:-target-feature +sve2 -target-feature +sme2 -target-feature +sve
-fsyntax-only -verify %s
+// RUN:-target-feature +sve2 -target-feature +sme2 -target-feature
+sme-i16i64 -target-feature +sme-f64f64 -fsyntax-only -verify %s
// REQUIRES: aarch64-registered-target
@@ -19,3 +19,8 @@ void test_outer_product(svbool_t pred, svint16_t s16,
svuint16_t u16, svint32_t
svbmops_za32_u32_m(4, pred, pred, u32, u32); // expected-error {{argument
[clang] 6c5da88 - [AArch64][SVE][Clang] Fix crash for incorrect svptrue and svcnt parameters
Author: Matt Devereau
Date: 2022-03-11T11:19:53Z
New Revision: 6c5da880e03cafc49008612eb687910f3f805057
URL:
https://github.com/llvm/llvm-project/commit/6c5da880e03cafc49008612eb687910f3f805057
DIFF:
https://github.com/llvm/llvm-project/commit/6c5da880e03cafc49008612eb687910f3f805057.diff
LOG: [AArch64][SVE][Clang] Fix crash for incorrect svptrue and svcnt parameters
Giving an int parameter to SVE intrinsics svptrue and svcnt caused Clang
to crash on compilation. Changing their parameter types to void instead of
omitting args results in a diagnostic error message instead.
Differential Revision: https://reviews.llvm.org/D121294
Added:
clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svcnt.c
clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svptrue.c
Modified:
clang/include/clang/Basic/arm_sve.td
Removed:
diff --git a/clang/include/clang/Basic/arm_sve.td
b/clang/include/clang/Basic/arm_sve.td
index 5e9d1c96558b9..220b830c368fe 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1263,10 +1263,10 @@ def SVZIP2_B : SInst<"svzip2_{d}", "PPP",
"PcPsPiPl", MergeNone, "aarch64_
// Predicate creation
-def SVPFALSE : SInst<"svpfalse[_b]", "P", "", MergeNone, "", [IsOverloadNone]>;
+def SVPFALSE : SInst<"svpfalse[_b]", "Pv", "", MergeNone, "",
[IsOverloadNone]>;
def SVPTRUE_PAT : SInst<"svptrue_pat_{d}", "PI", "PcPsPiPl", MergeNone,
"aarch64_sve_ptrue">;
-def SVPTRUE : SInst<"svptrue_{d}", "P", "PcPsPiPl", MergeNone,
"aarch64_sve_ptrue", [IsAppendSVALL]>;
+def SVPTRUE : SInst<"svptrue_{d}", "Pv", "PcPsPiPl", MergeNone,
"aarch64_sve_ptrue", [IsAppendSVALL]>;
def SVDUPQ_B8 : SInst<"svdupq[_n]_{d}", "P", "Pc",
MergeNone>;
def SVDUPQ_B16 : SInst<"svdupq[_n]_{d}", "P", "Ps", MergeNone>;
@@ -1309,9 +1309,9 @@ def SVPTEST_LAST : SInst<"svptest_last", "sPP", "Pc",
MergeNone, "aarch64_sve_
// FFR manipulation
-def SVRDFFR : SInst<"svrdffr", "P", "Pc", MergeNone, "",
[IsOverloadNone]>;
+def SVRDFFR : SInst<"svrdffr", "Pv", "Pc", MergeNone, "",
[IsOverloadNone]>;
def SVRDFFR_Z : SInst<"svrdffr_z", "PP", "Pc", MergeNone, "",
[IsOverloadNone]>;
-def SVSETFFR : SInst<"svsetffr", "v", "", MergeNone, "",
[IsOverloadNone]>;
+def SVSETFFR : SInst<"svsetffr", "vv", "", MergeNone, "",
[IsOverloadNone]>;
def SVWRFFR : SInst<"svwrffr", "vP", "Pc", MergeNone, "",
[IsOverloadNone]>;
@@ -1322,10 +1322,10 @@ def SVCNTH_PAT : SInst<"svcnth_pat", "nI", "",
MergeNone, "aarch64_sve_cnth", [I
def SVCNTW_PAT : SInst<"svcntw_pat", "nI", "", MergeNone, "aarch64_sve_cntw",
[IsOverloadNone]>;
def SVCNTD_PAT : SInst<"svcntd_pat", "nI", "", MergeNone, "aarch64_sve_cntd",
[IsOverloadNone]>;
-def SVCNTB : SInst<"svcntb", "n", "", MergeNone, "aarch64_sve_cntb",
[IsAppendSVALL, IsOverloadNone]>;
-def SVCNTH : SInst<"svcnth", "n", "", MergeNone, "aarch64_sve_cnth",
[IsAppendSVALL, IsOverloadNone]>;
-def SVCNTW : SInst<"svcntw", "n", "", MergeNone, "aarch64_sve_cntw",
[IsAppendSVALL, IsOverloadNone]>;
-def SVCNTD : SInst<"svcntd", "n", "", MergeNone, "aarch64_sve_cntd",
[IsAppendSVALL, IsOverloadNone]>;
+def SVCNTB : SInst<"svcntb", "nv", "", MergeNone, "aarch64_sve_cntb",
[IsAppendSVALL, IsOverloadNone]>;
+def SVCNTH : SInst<"svcnth", "nv", "", MergeNone, "aarch64_sve_cnth",
[IsAppendSVALL, IsOverloadNone]>;
+def SVCNTW : SInst<"svcntw", "nv", "", MergeNone, "aarch64_sve_cntw",
[IsAppendSVALL, IsOverloadNone]>;
+def SVCNTD : SInst<"svcntd", "nv", "", MergeNone, "aarch64_sve_cntd",
[IsAppendSVALL, IsOverloadNone]>;
def SVCNTP : SInst<"svcntp_{d}", "nPP", "PcPsPiPl",MergeNone,
"aarch64_sve_cntp">;
def SVLEN : SInst<"svlen[_{d}]", "nd", "csilUcUsUiUlhfd", MergeNone>;
@@ -1435,20 +1435,20 @@ def SVZIP2Q_BF16 : SInst<"svzip2q[_{d}]",
"ddd", "b", MergeNone, "aarc
// Vector creation
-def SVUNDEF_1 : SInst<"svundef_{d}", "d", "csilUcUsUiUlhfd", MergeNone, "",
[IsUndef]>;
-def SVUNDEF_2 : SInst<"svundef2_{d}", "2", "csilUcUsUiUlhfd", MergeNone, "",
[IsUndef]>;
-def SVUNDEF_3 : SInst<"svundef3_{d}", "3", "csilUcUsUiUlhfd", MergeNone, "",
[IsUndef]>;
-def SVUNDEF_4 : SInst<"svundef4_{d}", "4", "csilUcUsUiUlhfd", MergeNone, "",
[IsUndef]>;
+def SVUNDEF_1 : SInst<"svundef_{d}", "dv", "csilUcUsUiUlhfd", MergeNone, "",
[IsUndef]>;
+def SVUNDEF_2 : SInst<"svundef2_{d}", "2v", "csilUcUsUiUlhfd", MergeNone, "",
[IsUndef]>;
+def SVUNDEF_3 : SInst<"svundef3_{d}", "3v", "csilUcUsUiUlhfd", MergeNone, "",
[IsUnde
[clang] 75bb815 - [AArch64][SVE] Add aarch64_sve_pcs attribute to Clang
Author: Matt Devereau
Date: 2022-05-11T13:33:56Z
New Revision: 75bb815231f6967bd5f4e24143141b9fe69d01f8
URL:
https://github.com/llvm/llvm-project/commit/75bb815231f6967bd5f4e24143141b9fe69d01f8
DIFF:
https://github.com/llvm/llvm-project/commit/75bb815231f6967bd5f4e24143141b9fe69d01f8.diff
LOG: [AArch64][SVE] Add aarch64_sve_pcs attribute to Clang
Enable function attribute aarch64_sve_pcs at the C level, which correspondes to
aarch64_sve_vector_pcs at the LLVM IR level.
This requirement was created by this addition to the ARM C Language Extension:
https://github.com/ARM-software/acle/pull/194
Differential Revision: https://reviews.llvm.org/D124998
Added:
clang/test/CodeGen/aarch64-svepcs.c
clang/test/Sema/aarch64-svepcs.c
Modified:
clang/include/clang-c/Index.h
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/Specifiers.h
clang/lib/AST/ItaniumMangle.cpp
clang/lib/AST/Type.cpp
clang/lib/AST/TypePrinter.cpp
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/CodeGen/CGCall.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/Sema/SemaDeclAttr.cpp
clang/lib/Sema/SemaType.cpp
clang/test/Sema/callingconv.c
clang/tools/libclang/CXType.cpp
Removed:
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index f28601c37d8ef..c4da7df6595d1 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -3445,6 +3445,7 @@ enum CXCallingConv {
CXCallingConv_PreserveAll = 15,
CXCallingConv_AArch64VectorCall = 16,
CXCallingConv_SwiftAsync = 17,
+ CXCallingConv_AArch64SVEPCS = 18,
CXCallingConv_Invalid = 100,
CXCallingConv_Unexposed = 200
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 39359f414ae78..3c41edb474e89 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -2313,6 +2313,11 @@ def AArch64VectorPcs: DeclOrTypeAttr {
let Documentation = [AArch64VectorPcsDocs];
}
+def AArch64SVEPcs: DeclOrTypeAttr {
+ let Spellings = [Clang<"aarch64_sve_pcs">];
+ let Documentation = [AArch64SVEPcsDocs];
+}
+
def Pure : InheritableAttr {
let Spellings = [GCC<"pure">];
let Documentation = [Undocumented];
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index c7ef52f67afa3..b389ff9c02c45 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -2551,6 +2551,32 @@ the Arm Developer website.
}];
}
+def AArch64SVEPcsDocs : Documentation {
+ let Category = DocCatCallingConvs;
+ let Content = [{
+On AArch64 targets, this attribute changes the calling convention of a
+function to preserve additional Scalable Vector registers and Scalable
+Predicate registers relative to the default calling convention used for
+AArch64.
+
+This means it is more efficient to call such functions from code that performs
+extensive scalable vector and scalable predicate calculations, because fewer
+live SVE registers need to be saved. This property makes it well-suited for SVE
+math library functions, which are typically leaf functions that require a small
+number of registers.
+
+However, using this attribute also means that it is more expensive to call
+a function that adheres to the default calling convention from within such
+a function. Therefore, it is recommended that this attribute is only used
+for leaf functions.
+
+For more information, see the documentation for `aarch64_sve_pcs` in the
+ARM C Language Extension (ACLE) documentation.
+
+.. _`aarch64_sve_pcs`:
https://github.com/ARM-software/acle/blob/main/main/acle.md#scalable-vector-extension-procedure-call-standard-attribute
+ }];
+}
+
def RegparmDocs : Documentation {
let Category = DocCatCallingConvs;
let Content = [{
diff --git a/clang/include/clang/Basic/Specifiers.h
b/clang/include/clang/Basic/Specifiers.h
index 52ca7cce9d961..7a727e7088deb 100644
--- a/clang/include/clang/Basic/Specifiers.h
+++ b/clang/include/clang/Basic/Specifiers.h
@@ -280,6 +280,7 @@ namespace clang {
CC_PreserveMost, // __attribute__((preserve_most))
CC_PreserveAll, // __attribute__((preserve_all))
CC_AArch64VectorCall, // __attribute__((aarch64_vector_pcs))
+CC_AArch64SVEPCS, // __attribute__((aarch64_sve_pcs))
};
/// Checks whether the given calling convention supports variadic
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index 8d90575385fc4..1be70487c1b4e 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -3149,6 +3149,7 @@ StringRef
CXXNameMangler::getCallingConvQualifierName(CallingConv CC) {
case CC_AAPCS:
case CC_AAPCS_VFP:
case CC_AArch64VectorCall:
+ case CC_AArch64SVEPCS:
case CC_IntelOclBicc:
case CC_SpirFunction:
case CC_OpenCLKernel:
diff
[clang] 485c193 - Regenerate acle_st1*.c tests
Author: Matt Devereau
Date: 2021-11-15T15:07:52Z
New Revision: 485c193aa12addea13a0db12f4c6bc6252244319
URL:
https://github.com/llvm/llvm-project/commit/485c193aa12addea13a0db12f4c6bc6252244319
DIFF:
https://github.com/llvm/llvm-project/commit/485c193aa12addea13a0db12f4c6bc6252244319.diff
LOG: Regenerate acle_st1*.c tests
Regenerate acle_st1*.c tests using update_cc_test_checks.py
Added:
Modified:
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1h.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1w.c
Removed:
diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c
b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c
index 2ae45552b13b..957add02437c 100644
--- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c
+++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c
@@ -12,294 +12,350 @@
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif
+// CHECK-LABEL: @test_svst1b_s16(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = trunc [[DATA:%.*]] to
+// CHECK-NEXT:call void @llvm.aarch64.sve.st1.nxv8i8(
[[TMP1]], [[TMP0]], i8* [[BASE:%.*]])
+// CHECK-NEXT:ret void
+//
void test_svst1b_s16(svbool_t pg, int8_t *base, svint16_t data)
{
- // CHECK-LABEL: test_svst1b_s16
- // CHECK-DAG: %[[PG:.*]] = call
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg)
- // CHECK-DAG: %[[DATA:.*]] = trunc %data to
- // CHECK: call void @llvm.aarch64.sve.st1.nxv8i8(
%[[DATA]], %[[PG]], i8* %base)
- // CHECK: ret void
return SVE_ACLE_FUNC(svst1b,_s16,,)(pg, base, data);
}
+// CHECK-LABEL: @test_svst1b_s32(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call
@llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = trunc [[DATA:%.*]] to
+// CHECK-NEXT:call void @llvm.aarch64.sve.st1.nxv4i8(
[[TMP1]], [[TMP0]], i8* [[BASE:%.*]])
+// CHECK-NEXT:ret void
+//
void test_svst1b_s32(svbool_t pg, int8_t *base, svint32_t data)
{
- // CHECK-LABEL: test_svst1b_s32
- // CHECK-DAG: %[[PG:.*]] = call
@llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg)
- // CHECK-DAG: %[[DATA:.*]] = trunc %data to
- // CHECK: call void @llvm.aarch64.sve.st1.nxv4i8(
%[[DATA]], %[[PG]], i8* %base)
- // CHECK: ret void
return SVE_ACLE_FUNC(svst1b,_s32,,)(pg, base, data);
}
+// CHECK-LABEL: @test_svst1b_s64(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call
@llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = trunc [[DATA:%.*]] to
+// CHECK-NEXT:call void @llvm.aarch64.sve.st1.nxv2i8(
[[TMP1]], [[TMP0]], i8* [[BASE:%.*]])
+// CHECK-NEXT:ret void
+//
void test_svst1b_s64(svbool_t pg, int8_t *base, svint64_t data)
{
- // CHECK-LABEL: test_svst1b_s64
- // CHECK-DAG: %[[PG:.*]] = call
@llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg)
- // CHECK-DAG: %[[DATA:.*]] = trunc %data to
- // CHECK: call void @llvm.aarch64.sve.st1.nxv2i8(
%[[DATA]], %[[PG]], i8* %base)
- // CHECK: ret void
return SVE_ACLE_FUNC(svst1b,_s64,,)(pg, base, data);
}
+// CHECK-LABEL: @test_svst1b_u16(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = trunc [[DATA:%.*]] to
+// CHECK-NEXT:call void @llvm.aarch64.sve.st1.nxv8i8(
[[TMP1]], [[TMP0]], i8* [[BASE:%.*]])
+// CHECK-NEXT:ret void
+//
void test_svst1b_u16(svbool_t pg, uint8_t *base, svuint16_t data)
{
- // CHECK-LABEL: test_svst1b_u16
- // CHECK-DAG: %[[PG:.*]] = call
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg)
- // CHECK-DAG: %[[DATA:.*]] = trunc %data to
- // CHECK: call void @llvm.aarch64.sve.st1.nxv8i8(
%[[DATA]], %[[PG]], i8* %base)
- // CHECK: ret void
return SVE_ACLE_FUNC(svst1b,_u16,,)(pg, base, data);
}
+// CHECK-LABEL: @test_svst1b_u32(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call
@llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = trunc [[DATA:%.*]] to
+// CHECK-NEXT:call void @llvm.aarch64.sve.st1.nxv4i8(
[[TMP1]], [[TMP0]], i8* [[BASE:%.*]])
+// CHECK-NEXT:ret void
+//
void test_svst1b_u32(svbool_t pg, uint8_t *base, svuint32_t data)
{
- // CHECK-LABEL: test_svst1b_u32
- // CHECK-DAG: %[[PG:.*]] = call
@llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg)
- // CHECK-DAG: %[[DATA:.*]] = trunc %data to
- // CHECK: call void @llvm.aarch64.sve.st1.nxv4i8(
%[[DATA]], %[[PG]], i8* %base)
- // CHECK: ret void
return SVE_ACLE_FUNC(svst1b,_u32,,)(pg, base, data);
}
+// CHECK-LABEL: @test_svst1b_u64(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call
@llvm.aarch64.sve.convert
[clang] 83727f2 - [AArch64][SVE] Remove arm-registered-target requirement on bfloat tests
Author: Matt Devereau Date: 2021-11-16T14:38:21Z New Revision: 83727f27719d3f319f746b473ce09be7e1d99b32 URL: https://github.com/llvm/llvm-project/commit/83727f27719d3f319f746b473ce09be7e1d99b32 DIFF: https://github.com/llvm/llvm-project/commit/83727f27719d3f319f746b473ce09be7e1d99b32.diff LOG: [AArch64][SVE] Remove arm-registered-target requirement on bfloat tests Changes in https://reviews.llvm.org/D113489 caused buildbot failures Added: Modified: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1-bfloat.c clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c Removed: diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1-bfloat.c index f2dc5c1d4d6d..38a959fc2917 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1-bfloat.c @@ -5,7 +5,7 @@ // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error -verify-ignore-unexpected=note %s -// REQUIRES: aarch64-registered-target || arm-registered-target +// REQUIRES: aarch64-registered-target #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c index a05da764de44..7a57a3ebf354 100644 --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c @@ -5,7 +5,7 @@ // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error -verify-ignore-unexpected=note %s -// REQUIRES: aarch64-registered-target || arm-registered-target +// REQUIRES: aarch64-registered-target #include ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] c52d950 - [AArch64][SVE] Add asm predicate constraint Uph
Author: Matt Devereau
Date: 2023-08-11T14:48:19Z
New Revision: c52d9509d40d3048914b144618232213e6076e05
URL:
https://github.com/llvm/llvm-project/commit/c52d9509d40d3048914b144618232213e6076e05
DIFF:
https://github.com/llvm/llvm-project/commit/c52d9509d40d3048914b144618232213e6076e05.diff
LOG: [AArch64][SVE] Add asm predicate constraint Uph
Some instructions such as multi-vector LD1 only accept a range
of PN8-PN15 predicate-as-counter. This new constraint allows more
refined parsing and better decision making when parsing these
instructions from ASM, instead of defaulting to Upa which incorrectly
uses the whole range of registers P0-P15 from the register class PPR.
Differential Revision: https://reviews.llvm.org/D157517
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
llvm/docs/LangRef.rst
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 7c4cc5fb33f886..6c43c8b592622d 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -1288,8 +1288,9 @@ bool AArch64TargetInfo::validateAsmConstraint(
Info.setAllowsRegister();
return true;
case 'U':
-if (Name[1] == 'p' && (Name[2] == 'l' || Name[2] == 'a')) {
- // SVE predicate registers ("Upa"=P0-15, "Upl"=P0-P7)
+if (Name[1] == 'p' &&
+(Name[2] == 'l' || Name[2] == 'a' || Name[2] == 'h')) {
+ // SVE predicate registers ("Upa"=P0-15, "Upl"=P0-P7, "Uph"=P8-P15)
Info.setAllowsRegister();
Name += 2;
return true;
diff --git a/clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
b/clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
index 5c1e931a727124..14a29dfac2c7bd 100644
--- a/clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
+++ b/clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
@@ -168,6 +168,30 @@ SVBOOL_TEST_UPL(__SVInt32_t, s) ;
SVBOOL_TEST_UPL(__SVInt64_t, d) ;
// CHECK: call asm sideeffect "fadd $0.d, $1.d, $2.d,
$3.d\0A", "=w,@3Upl,w,w"( %in1, %in2,
%in3)
+#define SVBOOL_TEST_UPH(DT, KIND)\
+__SVBool_t func_bool_uph_##KIND(__SVBool_t in1, DT in2, DT in3)\
+{\
+ __SVBool_t out;\
+ asm volatile (\
+"fadd %[out]." #KIND ", %[in1]." #KIND ", %[in2]." #KIND ", %[in3]." #KIND
"\n"\
+: [out] "=w" (out)\
+: [in1] "Uph" (in1),\
+ [in2] "w" (in2),\
+ [in3] "w" (in3)\
+:);\
+ return out;\
+}
+
+SVBOOL_TEST_UPH(__SVInt8_t, b) ;
+// CHECK: call asm sideeffect "fadd $0.b, $1.b, $2.b,
$3.b\0A", "=w,@3Uph,w,w"( %in1, %in2,
%in3)
+SVBOOL_TEST_UPH(__SVInt16_t, h) ;
+// CHECK: call asm sideeffect "fadd $0.h, $1.h, $2.h,
$3.h\0A", "=w,@3Uph,w,w"( %in1, %in2,
%in3)
+SVBOOL_TEST_UPH(__SVInt32_t, s) ;
+// CHECK: call asm sideeffect "fadd $0.s, $1.s, $2.s,
$3.s\0A", "=w,@3Uph,w,w"( %in1, %in2,
%in3)
+SVBOOL_TEST_UPH(__SVInt64_t, d) ;
+// CHECK: call asm sideeffect "fadd $0.d, $1.d, $2.d,
$3.d\0A", "=w,@3Uph,w,w"( %in1, %in2,
%in3)
+
+
#define SVFLOAT_TEST(DT,KIND)\
DT func_float_##DT##KIND(DT inout1, DT in2)\
{\
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index f024d009966a8d..f7f5cc193a149c 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -4997,7 +4997,8 @@ AArch64:
- ``w``: A 32, 64, or 128-bit floating-point, SIMD or SVE vector register.
- ``x``: Like w, but restricted to registers 0 to 15 inclusive.
- ``y``: Like w, but restricted to SVE vector registers Z0 to Z7 inclusive.
-- ``Upl``: One of the low eight SVE predicate registers (P0 to P7)
+- ``Uph``: One of the upper eight SVE predicate registers (P8 to P15)
+- ``Upl``: One of the lower eight SVE predicate registers (P0 to P7)
- ``Upa``: Any of the SVE predicate registers (P0 to P15)
AMDGPU:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 948419f29b48e9..d0f4789d198058 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9987,19 +9987,31 @@ const char *AArch64TargetLowering::LowerXConstraint(EVT
ConstraintVT) const {
return "r";
}
-enum PredicateConstraint {
- Upl,
- Upa,
- Invalid
-};
+enum PredicateConstraint { Uph, Upl, Upa, Invalid };
static PredicateConstraint parsePredicateConstraint(StringRef Constraint) {
- PredicateConstraint P = PredicateConstraint::Invalid;
- if (Constraint == "Upa")
-P = PredicateConstraint::Upa;
- if (Constraint == "Upl")
-P = PredicateConstraint::Upl;
- return P;
+ return StringSwitch(Constraint)
+ .Case("Uph", PredicateConstraint::Uph)
+ .Case("Upl", PredicateConstraint::Upl)
+ .Case("Upa", PredicateConstraint::Upa)
+ .Default(PredicateConstraint::Invalid);
+}
+
+static const Tar
[clang] 533997b - Fix DISABLE-NOT: cc1 check in debug-info-codeview-buildinfo.c test
Author: Matt Devereau
Date: 2023-03-07T13:22:18Z
New Revision: 533997b026bab9994209d07ab6297d1482289f2d
URL:
https://github.com/llvm/llvm-project/commit/533997b026bab9994209d07ab6297d1482289f2d
DIFF:
https://github.com/llvm/llvm-project/commit/533997b026bab9994209d07ab6297d1482289f2d.diff
LOG: Fix DISABLE-NOT: cc1 check in debug-info-codeview-buildinfo.c test
This check is checking for the cc1 flag but this test has been seen to fail
when FILEPATHVAL has contained cc1 in generated SHAs
Added:
Modified:
clang/test/CodeGen/debug-info-codeview-buildinfo.c
Removed:
diff --git a/clang/test/CodeGen/debug-info-codeview-buildinfo.c
b/clang/test/CodeGen/debug-info-codeview-buildinfo.c
index 4096fac5f7437..4fc55af10a6e2 100644
--- a/clang/test/CodeGen/debug-info-codeview-buildinfo.c
+++ b/clang/test/CodeGen/debug-info-codeview-buildinfo.c
@@ -33,7 +33,7 @@ int main(void) { return 42; }
// RELATIVE: 0x{{.+}} | LF_BUILDINFO [size = {{.+}}]
// RELATIVE: 0x{{.+}}: `.`
-// DISABLE-NOT: cc1
+// DISABLE-NOT: "-cc1"
// DISABLE: 0x{{.+}} | LF_BUILDINFO [size = {{.+}}]
// DISABLE-NEXT: 0x{{.+}}: `{{.*}}`
// DISABLE-NEXT: : ``
___
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[clang] a1fae98 - [AArch64] Add svboolx2_t and svboolx4_t tuple types
Author: Matt Devereau
Date: 2023-03-14T10:16:51Z
New Revision: a1fae98ba95c18ea6b673fc3c177b917e0f5aa56
URL:
https://github.com/llvm/llvm-project/commit/a1fae98ba95c18ea6b673fc3c177b917e0f5aa56
DIFF:
https://github.com/llvm/llvm-project/commit/a1fae98ba95c18ea6b673fc3c177b917e0f5aa56.diff
LOG: [AArch64] Add svboolx2_t and svboolx4_t tuple types
https://reviews.llvm.org/D145505
Added:
clang/test/CodeGen/svboolx2_t.cpp
clang/test/CodeGen/svboolx4_t.cpp
Modified:
clang/include/clang/Basic/AArch64SVEACLETypes.def
clang/lib/AST/ASTContext.cpp
clang/lib/AST/Type.cpp
clang/lib/CodeGen/CodeGenTypes.cpp
clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
clang/utils/TableGen/SveEmitter.cpp
Removed:
diff --git a/clang/include/clang/Basic/AArch64SVEACLETypes.def
b/clang/include/clang/Basic/AArch64SVEACLETypes.def
index cb2f673af06d5..56af270e1d10a 100644
--- a/clang/include/clang/Basic/AArch64SVEACLETypes.def
+++ b/clang/include/clang/Basic/AArch64SVEACLETypes.def
@@ -129,6 +129,8 @@ SVE_VECTOR_TYPE("__clang_svfloat64x4_t", "svfloat64x4_t",
SveFloat64x4, SveFloat
SVE_VECTOR_TYPE("__clang_svbfloat16x4_t", "svbfloat16x4_t", SveBFloat16x4,
SveBFloat16x4Ty, 32, 16, true, false, true)
SVE_PREDICATE_TYPE("__SVBool_t", "__SVBool_t", SveBool, SveBoolTy, 16)
+SVE_PREDICATE_TYPE("__clang_svboolx2_t", "svboolx2_t", SveBoolx2, SveBoolx2Ty,
32)
+SVE_PREDICATE_TYPE("__clang_svboolx4_t", "svboolx4_t", SveBoolx4, SveBoolx4Ty,
64)
SVE_OPAQUE_TYPE("__SVCount_t", "__SVCount_t", SveCount, SveCountTy)
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 90448c378458b..14c9ab9c31a88 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -4041,6 +4041,10 @@ ASTContext::getBuiltinVectorTypeInfo(const BuiltinType
*Ty) const {
return SVE_INT_ELTTY(64, 2, false, 4);
case BuiltinType::SveBool:
return SVE_ELTTY(BoolTy, 16, 1);
+ case BuiltinType::SveBoolx2:
+return SVE_ELTTY(BoolTy, 16, 2);
+ case BuiltinType::SveBoolx4:
+return SVE_ELTTY(BoolTy, 16, 4);
case BuiltinType::SveFloat16:
return SVE_ELTTY(HalfTy, 8, 1);
case BuiltinType::SveFloat16x2:
diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp
index 7710adbb274ae..96e611968ca18 100644
--- a/clang/lib/AST/Type.cpp
+++ b/clang/lib/AST/Type.cpp
@@ -2401,6 +2401,8 @@ bool Type::isVLSTBuiltinType() const {
case BuiltinType::SveFloat64:
case BuiltinType::SveBFloat16:
case BuiltinType::SveBool:
+case BuiltinType::SveBoolx2:
+case BuiltinType::SveBoolx4:
return true;
default:
return false;
diff --git a/clang/lib/CodeGen/CodeGenTypes.cpp
b/clang/lib/CodeGen/CodeGenTypes.cpp
index c31a3f0edf6d5..be9516925da25 100644
--- a/clang/lib/CodeGen/CodeGenTypes.cpp
+++ b/clang/lib/CodeGen/CodeGenTypes.cpp
@@ -596,6 +596,8 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
case BuiltinType::SveInt64x4:
case BuiltinType::SveUint64x4:
case BuiltinType::SveBool:
+case BuiltinType::SveBoolx2:
+case BuiltinType::SveBoolx4:
case BuiltinType::SveFloat16:
case BuiltinType::SveFloat16x2:
case BuiltinType::SveFloat16x3:
diff --git a/clang/test/CodeGen/svboolx2_t.cpp
b/clang/test/CodeGen/svboolx2_t.cpp
new file mode 100644
index 0..060940d8755f5
--- /dev/null
+++ b/clang/test/CodeGen/svboolx2_t.cpp
@@ -0,0 +1,31 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-target-feature +bf16 -S -emit-llvm -o - %s | FileCheck %s
+
+// CHECK-LABEL: @_Z3foo10svboolx2_t(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[ARG_ADDR:%.*]] = alloca , align 2
+// CHECK-NEXT:store [[ARG:%.*]], ptr [[ARG_ADDR]],
align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load , ptr [[ARG_ADDR]],
align 2
+// CHECK-NEXT:ret [[TMP0]]
+//
+__clang_svboolx2_t foo(__clang_svboolx2_t arg) { return arg; }
+
+__clang_svboolx2_t bar();
+// CHECK-LABEL: @_Z4foo2v(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[CALL:%.*]] = call @_Z3barv()
+// CHECK-NEXT:ret [[CALL]]
+//
+__clang_svboolx2_t foo2() { return bar(); }
+
+__clang_svboolx2_t bar2(__clang_svboolx2_t);
+// CHECK-LABEL: @_Z4foo310svboolx2_t(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[ARG_ADDR:%.*]] = alloca , align 2
+// CHECK-NEXT:store [[ARG:%.*]], ptr [[ARG_ADDR]],
align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load , ptr [[ARG_ADDR]],
align 2
+// CHECK-NEXT:[[CALL:%.*]] = call
@_Z4bar210svboolx2_t( [[TMP0]])
+// CHECK-NEXT:ret [[CALL]]
+//
+__clang_svboolx2_t foo3(__clang_svboolx2_t arg) { return bar2(arg); }
+
diff --git a/clang/test/CodeGen/svboolx4_t.cpp
b/clang/test/CodeGen/svboolx4_t.cpp
new file mode 100644
index 0..8360786c06d70
--- /dev/null
+++ b/clang/test/CodeGen/svboolx4_t.cpp
@@ -0,0 +1,31 @@
+// NOTE: Assertio
[clang] 41def32 - [AArch64][SVE][NEON] Add NEON-SVE-Bridge intrinsics
Author: Matt Devereau Date: 2021-12-13T11:31:57Z New Revision: 41def32040787e917b52279cc30231b27f2f02f7 URL: https://github.com/llvm/llvm-project/commit/41def32040787e917b52279cc30231b27f2f02f7 DIFF: https://github.com/llvm/llvm-project/commit/41def32040787e917b52279cc30231b27f2f02f7.diff LOG: [AArch64][SVE][NEON] Add NEON-SVE-Bridge intrinsics Adds svset_neonq, svget_neonq, svdup_neonq AArch64 intrinsics. These are described in the ACLE specification: https://github.com/ARM-software/acle/pull/72 https://reviews.llvm.org/D114713 Added: clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge.def clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge_cg.def clang/lib/Headers/arm_neon_sve_bridge.h clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_dup_neonq.c clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_get_neonq.c clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c Modified: clang/include/clang/Basic/BuiltinsSVE.def clang/lib/Basic/Targets/AArch64.cpp clang/lib/CodeGen/CGBuiltin.cpp clang/lib/Headers/CMakeLists.txt llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn Removed: diff --git a/clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge.def b/clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge.def new file mode 100644 index 0..8e3229984d8b7 --- /dev/null +++ b/clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge.def @@ -0,0 +1,39 @@ +#ifdef GET_SVE_BUILTINS +BUILTIN(__builtin_sve_svget_neonq_s8, "V16Scq16Sc", "n") +BUILTIN(__builtin_sve_svget_neonq_s16, "V8sq8s", "n") +BUILTIN(__builtin_sve_svget_neonq_s32, "V4iq4i", "n") +BUILTIN(__builtin_sve_svget_neonq_s64, "V2Wiq2Wi", "n") +BUILTIN(__builtin_sve_svget_neonq_u8, "V16Ucq16Uc", "n") +BUILTIN(__builtin_sve_svget_neonq_u16, "V16Usq16Us", "n") +BUILTIN(__builtin_sve_svget_neonq_u32, "V4Uiq4Ui", "n") +BUILTIN(__builtin_sve_svget_neonq_u64, "V2UWiq2UWi", "n") +BUILTIN(__builtin_sve_svget_neonq_f16, "V8hq8h", "n") +BUILTIN(__builtin_sve_svget_neonq_f32, "V4fq4f", "n") +BUILTIN(__builtin_sve_svget_neonq_f64, "V2dq2d", "n") +BUILTIN(__builtin_sve_svget_neonq_bf16, "V8yq8y", "n") +BUILTIN(__builtin_sve_svset_neonq_s8, "q16Scq16ScV16Sc", "n") +BUILTIN(__builtin_sve_svset_neonq_s16, "q8sq8sV8s", "n") +BUILTIN(__builtin_sve_svset_neonq_s32, "q4iq4iV4i", "n") +BUILTIN(__builtin_sve_svset_neonq_s64, "q2Wiq2WiV2Wi", "n") +BUILTIN(__builtin_sve_svset_neonq_u8, "q16Ucq16UcV16Uc", "n") +BUILTIN(__builtin_sve_svset_neonq_u16, "q8Usq8UsV8s", "n") +BUILTIN(__builtin_sve_svset_neonq_u32, "q4Uiq4UiV4Ui", "n") +BUILTIN(__builtin_sve_svset_neonq_u64, "q2UWiq2UWiV2UWi", "n") +BUILTIN(__builtin_sve_svset_neonq_f16, "q8hq8hV8h", "n") +BUILTIN(__builtin_sve_svset_neonq_f32, "q4fq4fV4f", "n") +BUILTIN(__builtin_sve_svset_neonq_f64, "q2dq2dV2d", "n") +BUILTIN(__builtin_sve_svset_neonq_bf16, "q8yq8yV8y", "n") +BUILTIN(__builtin_sve_svdup_neonq_s8, "q16ScV16Sc", "n") +BUILTIN(__builtin_sve_svdup_neonq_s16, "q8sV8s", "n") +BUILTIN(__builtin_sve_svdup_neonq_s32, "q4iV4i", "n") +BUILTIN(__builtin_sve_svdup_neonq_s64, "q4iV4i", "n") +BUILTIN(__builtin_sve_svdup_neonq_u8, "q16UcV16Uc", "n") +BUILTIN(__builtin_sve_svdup_neonq_u16, "q8UsV8Us", "n") +BUILTIN(__builtin_sve_svdup_neonq_u32, "q4UiV4Ui", "n") +BUILTIN(__builtin_sve_svdup_neonq_u64, "q2UWiV2UWi", "n") +BUILTIN(__builtin_sve_svdup_neonq_f16, "q8hV8h", "n") +BUILTIN(__builtin_sve_svdup_neonq_f32, "q4fV4f", "n") +BUILTIN(__builtin_sve_svdup_neonq_f64, "q2dV2d", "n") +BUILTIN(__builtin_sve_svdup_neonq_bf16, "q8yV8y", "n") +#endif + diff --git a/clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge_cg.def b/clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge_cg.def new file mode 100644 index 0..7717ba67b4279 --- /dev/null +++ b/clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge_cg.def @@ -0,0 +1,39 @@ +#ifdef GET_SVE_LLVM_INTRINSIC_MAP +SVEMAP2(svget_neonq_s8, SVETypeFlags::EltTyInt8), +SVEMAP2(svget_neonq_s16, SVETypeFlags::EltTyInt16), +SVEMAP2(svget_neonq_s32, SVETypeFlags::EltTyInt32), +SVEMAP2(svget_neonq_s64, SVETypeFlags::EltTyInt64), +SVEMAP2(svget_neonq_u8, SVETypeFlags::EltTyInt8), +SVEMAP2(svget_neonq_u16, SVETypeFlags::EltTyInt16), +SVEMAP2(svget_neonq_u32, SVETypeFlags::EltTyInt32), +SVEMAP2(svget_neonq_u64, SVETypeFlags::EltTyInt64), +SVEMAP2(svget_neonq_f16, SVETypeFlags::EltTyFloat16), +SVEMAP2(svget_neonq_f32, SVETypeFlags::EltTyFloat32), +SVEMAP2(svget_neonq_f64, SVETypeFlags::EltTyFloat64), +SVEMAP2(svget_neonq_bf16, SVETypeFlags::EltTyBFloat16), +SVEMAP2(svset_neonq_s8, SVETypeFlags::EltTyInt8), +SVEMAP2(svset_neonq_s16, SVETypeFlags::EltTyInt16), +SVEMAP2(svset_neonq_s32, SVETypeFlags::EltTyInt32), +SVEMAP2(svset_neonq_s64, SVETypeFlags::EltTyInt64), +SVEMAP2(svset_neonq_u8, SVETypeFlags::EltTyInt8), +SVEMAP2(svset_neonq_u16, SVETypeFlags::E
