[PATCH] D121294: [AArch64][SVE][Clang] Fix crash for incorrect svptrue and svcnt parameters

2022-03-09 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau created this revision.
MattDevereau added reviewers: peterwaller-arm, paulwalker-arm, DavidTruby.
Herald added subscribers: ctetreau, psnobl, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: All.
MattDevereau requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Giving an int parameter to SVE intrinsics svptrue and svcnt caused Clang to 
crash on compilation. Changing their parameter types to void instead of 
omitting args results in a diagnostic error message instead.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121294

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svcnt.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svptrue.c

Index: clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svptrue.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svptrue.c
@@ -0,0 +1,33 @@
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
+#endif
+
+#include 
+
+svbool_t test_svptrue_b8() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svptrue, , _b8, )(1);
+}
+
+svbool_t test_svptrue_b32() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svptrue, , _b32, )(2);
+}
+
+svbool_t test_svptrue_b64() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svptrue, , _b64, )(3);
+}
+
+svbool_t test_svptrue_b16() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svptrue, , _b16, )(4);
+}
Index: clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svcnt.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svcnt.c
@@ -0,0 +1,33 @@
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
+#endif
+
+#include 
+
+uint64_t test_svcntb() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svcnt, , b, )(1);
+}
+
+uint64_t test_svcnth() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svcnt, , h, )(2);
+}
+
+uint64_t test_svcntw() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svcnt, , w, )(3);
+}
+
+uint64_t test_svcntd() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svcnt, , d, )(4);
+}
Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -1263,10 +1263,10 @@
 
 // Predicate creation
 
-def SVPFALSE : SInst<"svpfalse[_b]", "P", "", MergeNone, "", [IsOverloadNone]>;
+def SVPFALSE : SInst<"svpfalse[_b]", "Pv", "", MergeNone, "", [IsOverloadNone]>;
 
 def SVPTRUE_PAT : SInst<"svptrue_pat_{d}", "PI", "PcPsPiPl", MergeNone, "aarch64_sve_ptrue">;
-def SVPTRUE : SInst<"svptrue_{d}", "P",  "PcPsPiPl", MergeNone, "aarch64_sve_ptrue", [IsAppendSVALL]>;
+def SVPTRUE : SInst<"svptrue_{d}", "Pv",  "PcPsPiPl", MergeNone, "aarch64_sve_ptrue", [IsAppendSVALL]>;
 
 def SVDUPQ_B8  : SInst<"svdupq[_n]_{d}",  "P",  "Pc", MergeNone>;
 def SVDUPQ_B16 : SInst<"svdupq[_n]_{d}", "P",  "Ps", MergeNone>;
@@ -1309,9 +1309,9 @@
 
 // FFR manipulation
 
-def SVRDFFR   : SIn

[PATCH] D121294: [AArch64][SVE][Clang] Fix crash for incorrect svptrue and svcnt parameters

2022-03-09 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau added a comment.

In D121294#3370085 , @sdesmalen wrote:

> This is missing tests for svundef, svrdffr, svsetffr and svpfalse?

@sdesmalen Only svcnt and svptrue cause the crash. This might be because of 
extra values added by the `[IsAppendSVALL]` TypeFlag in `arm_sve.td`




Comment at: 
clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svptrue.c:2
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-fallow-half-arguments-and-returns -fsyntax-only -verify %s

sdesmalen wrote:
> Is it possible to use the `update_cc_test_checks.py` script for these tests?
Deleting `// expected-error-re@+1...` and running `update_cc_test_checks.py` 
did not generate anything in its place in either of the tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121294/new/

https://reviews.llvm.org/D121294

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D121294: [AArch64][SVE][Clang] Fix crash for incorrect svptrue and svcnt parameters

2022-03-11 Thread Matt Devereau via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6c5da880e03c: [AArch64][SVE][Clang] Fix crash for incorrect 
svptrue and svcnt parameters (authored by MattDevereau).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121294/new/

https://reviews.llvm.org/D121294

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svcnt.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svptrue.c

Index: clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svptrue.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svptrue.c
@@ -0,0 +1,33 @@
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
+#endif
+
+#include 
+
+svbool_t test_svptrue_b8() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svptrue, , _b8, )(1);
+}
+
+svbool_t test_svptrue_b32() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svptrue, , _b32, )(2);
+}
+
+svbool_t test_svptrue_b64() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svptrue, , _b64, )(3);
+}
+
+svbool_t test_svptrue_b16() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svptrue, , _b16, )(4);
+}
Index: clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svcnt.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_svcnt.c
@@ -0,0 +1,33 @@
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
+#endif
+
+#include 
+
+uint64_t test_svcntb() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svcnt, , b, )(1);
+}
+
+uint64_t test_svcnth() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svcnt, , h, )(2);
+}
+
+uint64_t test_svcntw() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svcnt, , w, )(3);
+}
+
+uint64_t test_svcntd() {
+  // expected-error-re@+1 {{too many arguments to function call, expected {{0}}, have {{1
+  return SVE_ACLE_FUNC(svcnt, , d, )(4);
+}
Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -1263,10 +1263,10 @@
 
 // Predicate creation
 
-def SVPFALSE : SInst<"svpfalse[_b]", "P", "", MergeNone, "", [IsOverloadNone]>;
+def SVPFALSE : SInst<"svpfalse[_b]", "Pv", "", MergeNone, "", [IsOverloadNone]>;
 
 def SVPTRUE_PAT : SInst<"svptrue_pat_{d}", "PI", "PcPsPiPl", MergeNone, "aarch64_sve_ptrue">;
-def SVPTRUE : SInst<"svptrue_{d}", "P",  "PcPsPiPl", MergeNone, "aarch64_sve_ptrue", [IsAppendSVALL]>;
+def SVPTRUE : SInst<"svptrue_{d}", "Pv",  "PcPsPiPl", MergeNone, "aarch64_sve_ptrue", [IsAppendSVALL]>;
 
 def SVDUPQ_B8  : SInst<"svdupq[_n]_{d}",  "P",  "Pc", MergeNone>;
 def SVDUPQ_B16 : SInst<"svdupq[_n]_{d}", "P",  "Ps", MergeNone>;
@@ -1309,9 +1309,9 @@
 
 // FFR manipulation
 
-def SVRDFFR   : SInst<"svrdffr",   "P",  "Pc", MergeNone, "", [IsOverloadNone]>;
+def SVRDFFR   : SInst<"svrdffr",   "Pv",  "Pc", MergeNone, "", [IsOverloadNone]>;
 def SVRDFFR_Z : SInst<"svrdffr_z", "PP", "Pc", MergeNone, "", [IsOverloadNone]>;
-def SVSETFFR  : SInst<"svsetffr",  "v",  "",   MergeNone, "", [IsOverl

[PATCH] D121792: [AArch64][SVE] InstCombine llvm.aarch64.sve.sel to select

2022-03-16 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau created this revision.
MattDevereau added reviewers: peterwaller-arm, paulwalker-arm, DavidTruby, 
bsmith.
Herald added subscribers: ctetreau, psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: All.
MattDevereau requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

InstCombine llvm.aarch64.sve.sel to select. This allows an existing InstCombine 
added in 20b0fa91c9ee 
 to fire.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121792

Files:
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asr.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asrd.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cadd.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsl.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsr.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mad.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnm.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnm.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mls.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_msb.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulx.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmad.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmls.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmsb.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_scale.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_adalp.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hadd.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsub.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsubr.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qadd.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrshl.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qshl.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qshlu.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsub.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsubr.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rhadd.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rshl.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rshr.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sqadd.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_uqadd.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D121792: [AArch64][SVE] InstCombine llvm.aarch64.sve.sel to select

2022-03-17 Thread Matt Devereau via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa9e08bc7c1e5: [AArch64][SVE] InstCombine 
llvm.aarch64.sve.sel to select (authored by MattDevereau).

Changed prior to commit:
  https://reviews.llvm.org/D121792?vs=415785&id=416206#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121792/new/

https://reviews.llvm.org/D121792

Files:
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asr.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asrd.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cadd.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsl.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsr.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mad.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnm.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnm.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mls.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_msb.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulx.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmad.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmls.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmsb.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_scale.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_adalp.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hadd.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsub.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_hsubr.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qadd.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qrshl.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qshl.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qshlu.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsub.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_qsubr.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rhadd.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rshl.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_rshr.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_sqadd.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_uqadd.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-sel.ll

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D119926: [Clang][AArch64] Enable _Float16 _Complex type

2022-02-16 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau created this revision.
MattDevereau added reviewers: georges, peterwaller-arm, paulwalker-arm, 
DavidTruby, bsmith, teemperor, rjmccall, qiucf.
Herald added a subscriber: kristof.beyls.
MattDevereau requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119926

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/AST/ASTContext.cpp
  clang/test/CodeGen/aarch64-complex-half-math.c

Index: clang/test/CodeGen/aarch64-complex-half-math.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-complex-half-math.c
@@ -0,0 +1,145 @@
+// RUN: %clang_cc1 %s -O1 -emit-llvm -triple aarch64-unknown-unknown -ffast-math -o - | FileCheck %s --check-prefix=AARCH64
+
+_Float16 _Complex add_float_rr(_Float16 a, _Float16 b) {
+  // AARCH64-LABEL: @add_float_rr(
+  // AARCH64: fadd reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fadd
+  // AARCH64: ret { half, half }
+  return a + b;
+}
+_Float16 _Complex add_float_cr(_Float16 _Complex a, _Float16 b) {
+  // AARCH64-LABEL: @add_float_cr(
+  // AARCH64: fadd reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fadd
+  // AARCH64: ret { half, half }
+  return a + b;
+}
+_Float16 _Complex add_float_rc(_Float16 a, _Float16 _Complex b) {
+  // AARCH64-LABEL: @add_float_rc(
+  // AARCH64: fadd reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fadd
+  // AARCH64: ret { half, half }
+  return a + b;
+}
+_Float16 _Complex add_float_cc(_Float16 _Complex a, _Float16 _Complex b) {
+  // AARCH64-LABEL: @add_float_cc(
+  // AARCH64: fadd reassoc nnan ninf nsz arcp afn half
+  // AARCH64: fadd reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fadd
+  // AARCH64: ret { half, half }
+  return a + b;
+}
+
+_Float16 _Complex sub_float_rr(_Float16 a, _Float16 b) {
+  // AARCH64-LABEL: @sub_float_rr(
+  // AARCH64: fsub reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fsub
+  // AARCH64: ret { half, half }
+  return a - b;
+}
+_Float16 _Complex sub_float_cr(_Float16 _Complex a, _Float16 b) {
+  // AARCH64-LABEL: @sub_float_cr(
+  // AARCH64: fsub reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fsub
+  // AARCH64: ret { half, half }
+  return a - b;
+}
+_Float16 _Complex sub_float_rc(_Float16 a, _Float16 _Complex b) {
+  // AARCH64-LABEL: @sub_float_rc(
+  // AARCH64: fsub reassoc nnan ninf nsz arcp afn half
+  // AARCH64: fneg reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fsub
+  // AARCH64: ret { half, half }
+  return a - b;
+}
+_Float16 _Complex sub_float_cc(_Float16 _Complex a, _Float16 _Complex b) {
+  // AARCH64-LABEL: @sub_float_cc(
+  // AARCH64: fsub reassoc nnan ninf nsz arcp afn half
+  // AARCH64: fsub reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fsub
+  // AARCH64: ret { half, half }
+  return a - b;
+}
+
+_Float16 _Complex mul_float_rr(_Float16 a, _Float16 b) {
+  // AARCH64-LABEL: @mul_float_rr(
+  // AARCH64: fmul reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fmul
+  // AARCH64: ret { half, half }
+  return a * b;
+}
+_Float16 _Complex mul_float_cr(_Float16 _Complex a, _Float16 b) {
+  // AARCH64-LABEL: @mul_float_cr(
+  // AARCH64: fmul reassoc nnan ninf nsz arcp afn half
+  // AARCH64: fmul reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fmul
+  // AARCH64: ret { half, half }
+  return a * b;
+}
+_Float16 _Complex mul_float_rc(_Float16 a, _Float16 _Complex b) {
+  // AARCH64-LABEL: @mul_float_rc(
+  // AARCH64: fmul reassoc nnan ninf nsz arcp afn half
+  // AARCH64: fmul reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fmul
+  // AARCH64: ret { half, half }
+  return a * b;
+}
+_Float16 _Complex mul_float_cc(_Float16 _Complex a, _Float16 _Complex b) {
+  // AARCH64-LABEL: @mul_float_cc(
+  // AARCH64: fmul reassoc nnan ninf nsz arcp afn half
+  // AARCH64: fmul reassoc nnan ninf nsz arcp afn half
+  // AARCH64: fadd reassoc nnan ninf nsz arcp afn half
+  // AARCH64: fmul reassoc nnan ninf nsz arcp afn half
+  // AARCH64: fmul reassoc nnan ninf nsz arcp afn half
+  // AARCH64: fsub reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fmul
+  // AARCH64: ret { half, half }
+  return a * b;
+}
+
+_Float16 _Complex div_float_rr(_Float16 a, _Float16 b) {
+  // AARCH64-LABEL: @div_float_rr(
+  // AARCH64: fdiv reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fdiv reassoc nnan ninf nsz arcp afn half
+  // AARCH64: ret { half, half }
+  return a / b;
+}
+_Float16 _Complex div_float_cr(_Float16 _Complex a, _Float16 b) {
+  // AARCH64-LABEL: @div_float_cr(
+  // AARCH64: fdiv reassoc nnan ninf nsz arcp afn half
+  // AARCH64: fdiv reassoc nnan ninf nsz arcp afn half
+  // AARCH64-NOT: fdiv reassoc nnan ninf nsz arcp afn half
+  // AARCH64: ret { half, half }
+  return a / b;
+}
+_Float16 _Complex div_float_rc(_Float16 a, _Float16 _Complex b) {
+  // AARCH64-LABEL: @div_float_rc(
+  // AARCH64: fmul reassoc nnan ninf nsz

[PATCH] D119926: [Clang][AArch64] Enable _Float16 _Complex type

2022-02-16 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau updated this revision to Diff 409236.
MattDevereau added a comment.

Removed -O1 and -ffast-math flags


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119926/new/

https://reviews.llvm.org/D119926

Files:
  clang/lib/AST/ASTContext.cpp
  clang/test/CodeGen/aarch64-complex-half-math.c

Index: clang/test/CodeGen/aarch64-complex-half-math.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-complex-half-math.c
@@ -0,0 +1,419 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 %s -emit-llvm -triple aarch64-unknown-unknown -o - | FileCheck %s --check-prefix=AARCH64
+// REQUIRES: aarch64-registered-target
+
+// AARCH64-LABEL: @add_float_rr(
+// AARCH64-NEXT:  entry:
+// AARCH64-NEXT:[[RETVAL:%.*]] = alloca { half, half }, align 2
+// AARCH64-NEXT:[[A_ADDR:%.*]] = alloca half, align 2
+// AARCH64-NEXT:[[B_ADDR:%.*]] = alloca half, align 2
+// AARCH64-NEXT:store half [[A:%.*]], half* [[A_ADDR]], align 2
+// AARCH64-NEXT:store half [[B:%.*]], half* [[B_ADDR]], align 2
+// AARCH64-NEXT:[[TMP0:%.*]] = load half, half* [[A_ADDR]], align 2
+// AARCH64-NEXT:[[TMP1:%.*]] = load half, half* [[B_ADDR]], align 2
+// AARCH64-NEXT:[[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// AARCH64-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { half, half }, { half, half }* [[RETVAL]], i32 0, i32 0
+// AARCH64-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { half, half }, { half, half }* [[RETVAL]], i32 0, i32 1
+// AARCH64-NEXT:store half [[ADD]], half* [[RETVAL_REALP]], align 2
+// AARCH64-NEXT:store half 0xH, half* [[RETVAL_IMAGP]], align 2
+// AARCH64-NEXT:[[TMP2:%.*]] = load { half, half }, { half, half }* [[RETVAL]], align 2
+// AARCH64-NEXT:ret { half, half } [[TMP2]]
+//
+_Float16 _Complex add_float_rr(_Float16 a, _Float16 b) {
+  return a + b;
+}
+// AARCH64-LABEL: @add_float_cr(
+// AARCH64-NEXT:  entry:
+// AARCH64-NEXT:[[RETVAL:%.*]] = alloca { half, half }, align 2
+// AARCH64-NEXT:[[A:%.*]] = alloca { half, half }, align 2
+// AARCH64-NEXT:[[B_ADDR:%.*]] = alloca half, align 2
+// AARCH64-NEXT:[[TMP0:%.*]] = bitcast { half, half }* [[A]] to [2 x half]*
+// AARCH64-NEXT:store [2 x half] [[A_COERCE:%.*]], [2 x half]* [[TMP0]], align 2
+// AARCH64-NEXT:store half [[B:%.*]], half* [[B_ADDR]], align 2
+// AARCH64-NEXT:[[A_REALP:%.*]] = getelementptr inbounds { half, half }, { half, half }* [[A]], i32 0, i32 0
+// AARCH64-NEXT:[[A_REAL:%.*]] = load half, half* [[A_REALP]], align 2
+// AARCH64-NEXT:[[A_IMAGP:%.*]] = getelementptr inbounds { half, half }, { half, half }* [[A]], i32 0, i32 1
+// AARCH64-NEXT:[[A_IMAG:%.*]] = load half, half* [[A_IMAGP]], align 2
+// AARCH64-NEXT:[[TMP1:%.*]] = load half, half* [[B_ADDR]], align 2
+// AARCH64-NEXT:[[ADD_R:%.*]] = fadd half [[A_REAL]], [[TMP1]]
+// AARCH64-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { half, half }, { half, half }* [[RETVAL]], i32 0, i32 0
+// AARCH64-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { half, half }, { half, half }* [[RETVAL]], i32 0, i32 1
+// AARCH64-NEXT:store half [[ADD_R]], half* [[RETVAL_REALP]], align 2
+// AARCH64-NEXT:store half [[A_IMAG]], half* [[RETVAL_IMAGP]], align 2
+// AARCH64-NEXT:[[TMP2:%.*]] = load { half, half }, { half, half }* [[RETVAL]], align 2
+// AARCH64-NEXT:ret { half, half } [[TMP2]]
+//
+_Float16 _Complex add_float_cr(_Float16 _Complex a, _Float16 b) {
+  return a + b;
+}
+// AARCH64-LABEL: @add_float_rc(
+// AARCH64-NEXT:  entry:
+// AARCH64-NEXT:[[RETVAL:%.*]] = alloca { half, half }, align 2
+// AARCH64-NEXT:[[B:%.*]] = alloca { half, half }, align 2
+// AARCH64-NEXT:[[A_ADDR:%.*]] = alloca half, align 2
+// AARCH64-NEXT:[[TMP0:%.*]] = bitcast { half, half }* [[B]] to [2 x half]*
+// AARCH64-NEXT:store [2 x half] [[B_COERCE:%.*]], [2 x half]* [[TMP0]], align 2
+// AARCH64-NEXT:store half [[A:%.*]], half* [[A_ADDR]], align 2
+// AARCH64-NEXT:[[TMP1:%.*]] = load half, half* [[A_ADDR]], align 2
+// AARCH64-NEXT:[[B_REALP:%.*]] = getelementptr inbounds { half, half }, { half, half }* [[B]], i32 0, i32 0
+// AARCH64-NEXT:[[B_REAL:%.*]] = load half, half* [[B_REALP]], align 2
+// AARCH64-NEXT:[[B_IMAGP:%.*]] = getelementptr inbounds { half, half }, { half, half }* [[B]], i32 0, i32 1
+// AARCH64-NEXT:[[B_IMAG:%.*]] = load half, half* [[B_IMAGP]], align 2
+// AARCH64-NEXT:[[ADD_R:%.*]] = fadd half [[TMP1]], [[B_REAL]]
+// AARCH64-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { half, half }, { half, half }* [[RETVAL]], i32 0, i32 0
+// AARCH64-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { half, half }, { half, half }* [[RETVAL]], i32 0, i32 1
+// AARCH64-NEXT:store half [[ADD_R]], half* [[RETVAL_REALP]], align 2
+// AARCH64-NEXT:store half

[PATCH] D124998: [AArch64][SVE] Add aarch64_sve_pcs attribute to Clang

2022-05-05 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau created this revision.
MattDevereau added reviewers: paulwalker-arm, peterwaller-arm, bsmith, 
DavidTruby, dtemirbulatov.
Herald added subscribers: ctetreau, psnobl, arphaman, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added a reviewer: aaron.ballman.
Herald added a project: All.
MattDevereau requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

[AArch64][SVE] Add aarch64_sve_pcs attribute to Clang

Enable function attribute aarch64_sve_pcs at the C level, which correspondes to 
aarch64_sve_vector_pcs at the LLVM IR level.

This requirement was created by this addition to the ARM C Language Extension:
https://github.com/ARM-software/acle/pull/194


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124998

Files:
  clang/include/clang-c/Index.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/Specifiers.h
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/CodeGen/aarch64-svepcs.c
  clang/test/Sema/aarch64-svepcs.c
  clang/test/Sema/callingconv.c
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -666,6 +666,7 @@
   TCALLINGCONV(X86RegCall);
   TCALLINGCONV(X86VectorCall);
   TCALLINGCONV(AArch64VectorCall);
+  TCALLINGCONV(AArch64SVEPcs);
   TCALLINGCONV(Win64);
   TCALLINGCONV(X86_64SysV);
   TCALLINGCONV(AAPCS);
Index: clang/test/Sema/callingconv.c
===
--- clang/test/Sema/callingconv.c
+++ clang/test/Sema/callingconv.c
@@ -52,6 +52,7 @@
 int __attribute__((pcs("foo"))) pcs7(void); // expected-error {{invalid PCS type}}
 
 int __attribute__((aarch64_vector_pcs)) aavpcs(void); // expected-warning {{'aarch64_vector_pcs' calling convention is not supported for this target}}
+int __attribute__((aarch64_sve_pcs)) aasvepcs(void); // expected-warning {{'aarch64_sve_pcs' calling convention is not supported for this target}}
 
 // PR6361
 void ctest3();
Index: clang/test/Sema/aarch64-svepcs.c
===
--- /dev/null
+++ clang/test/Sema/aarch64-svepcs.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +sve -verify %s
+
+typedef __attribute__((aarch64_sve_pcs)) int invalid_typedef; // expected-warning {{'aarch64_sve_pcs' only applies to function types; type here is 'int'}}
+
+void __attribute__((aarch64_sve_pcs(0))) foo0(void); // expected-error {{'aarch64_sve_pcs' attribute takes no arguments}}
+
+void __attribute__((aarch64_sve_pcs, preserve_all)) foo1(void); // expected-error {{not compatible}}
+
+void __attribute__((cdecl)) foo2(void);// expected-note {{previous declaration is here}}
+void __attribute__((aarch64_sve_pcs)) foo2(void) {} // expected-error {{function declared 'aarch64_sve_pcs' here was previously declared 'cdecl'}}
+
+void foo3(void);   // expected-note {{previous declaration is here}}
+void __attribute__((aarch64_sve_pcs)) foo3(void) {} // expected-error {{function declared 'aarch64_sve_pcs' here was previously declared without calling convention}}
+
+typedef int (*fn_ty)(void);
+typedef int __attribute__((aarch64_sve_pcs)) (*aasvepcs_fn_ty)(void);
+void foo4(fn_ty ptr1, aasvepcs_fn_ty ptr2) {
+  ptr1 = ptr2; // expected-warning {{incompatible function pointer types}}
+}
Index: clang/test/CodeGen/aarch64-svepcs.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-svepcs.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECKC
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -x c++ -o - %s | FileCheck %s -check-prefix=CHECKCXX
+// RUN: %clang_cc1 -triple i686-pc-linux-gnu -verify %s
+
+void __attribute__((aarch64_sve_pcs)) f(int *); // expected-warning {{'aarch64_sve_pcs' calling convention is not supported for this target}}
+
+// CHECKC: define{{.*}} void @g(
+// CHECKCXX: define{{.*}} void @_Z1gPi(
+void g(int *a) {
+
+// CHECKC: call aarch64_sve_vector_pcs void @f(
+// CHECKCXX: call aarch64_sve_vector_pcs void @_Z1fPi
+  f(a);
+}
+
+// CHECKC: declare aarch64_sve_vector_pcs void @f(
+// CHECKCXX: declare aarch64_sve_vector_pcs void @_Z1fPi
+
+void __attribute__((aarch64_sve_pcs)) h(int *a){ // expected-warning {{'aarch64_sve_pcs' calling convention is not supported for this target}}
+// CHECKC: define{{.*}} aarch64_sve_vector_pcs void @h(
+// CHECKCXX: define{{.*}} aarch64_sve_vector_pcs void @_Z1hPi

[PATCH] D124998: [AArch64][SVE] Add aarch64_sve_pcs attribute to Clang

2022-05-05 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau updated this revision to Diff 427335.
MattDevereau added a comment.

set `CXCallingConv_AArch64SVEPcs= 17` to 18 to resolve ABI break
renamed CC_AArch64SVEPcs to CC_AArch64SVEPCS


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124998/new/

https://reviews.llvm.org/D124998

Files:
  clang/include/clang-c/Index.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/Specifiers.h
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/CodeGen/aarch64-svepcs.c
  clang/test/Sema/aarch64-svepcs.c
  clang/test/Sema/callingconv.c
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -666,6 +666,7 @@
   TCALLINGCONV(X86RegCall);
   TCALLINGCONV(X86VectorCall);
   TCALLINGCONV(AArch64VectorCall);
+  TCALLINGCONV(AArch64SVEPCS);
   TCALLINGCONV(Win64);
   TCALLINGCONV(X86_64SysV);
   TCALLINGCONV(AAPCS);
Index: clang/test/Sema/callingconv.c
===
--- clang/test/Sema/callingconv.c
+++ clang/test/Sema/callingconv.c
@@ -52,6 +52,7 @@
 int __attribute__((pcs("foo"))) pcs7(void); // expected-error {{invalid PCS type}}
 
 int __attribute__((aarch64_vector_pcs)) aavpcs(void); // expected-warning {{'aarch64_vector_pcs' calling convention is not supported for this target}}
+int __attribute__((aarch64_sve_pcs)) aasvepcs(void);  // expected-warning {{'aarch64_sve_pcs' calling convention is not supported for this target}}
 
 // PR6361
 void ctest3();
Index: clang/test/Sema/aarch64-svepcs.c
===
--- /dev/null
+++ clang/test/Sema/aarch64-svepcs.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +sve -verify %s
+
+typedef __attribute__((aarch64_sve_pcs)) int invalid_typedef; // expected-warning {{'aarch64_sve_pcs' only applies to function types; type here is 'int'}}
+
+void __attribute__((aarch64_sve_pcs(0))) foo0(void); // expected-error {{'aarch64_sve_pcs' attribute takes no arguments}}
+
+void __attribute__((aarch64_sve_pcs, preserve_all)) foo1(void); // expected-error {{not compatible}}
+
+void __attribute__((cdecl)) foo2(void); // expected-note {{previous declaration is here}}
+void __attribute__((aarch64_sve_pcs)) foo2(void) {} // expected-error {{function declared 'aarch64_sve_pcs' here was previously declared 'cdecl'}}
+
+void foo3(void);// expected-note {{previous declaration is here}}
+void __attribute__((aarch64_sve_pcs)) foo3(void) {} // expected-error {{function declared 'aarch64_sve_pcs' here was previously declared without calling convention}}
+
+typedef int (*fn_ty)(void);
+typedef int __attribute__((aarch64_sve_pcs)) (*aasvepcs_fn_ty)(void);
+void foo4(fn_ty ptr1, aasvepcs_fn_ty ptr2) {
+  ptr1 = ptr2; // expected-warning {{incompatible function pointer types}}
+}
Index: clang/test/CodeGen/aarch64-svepcs.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-svepcs.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECKC
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -x c++ -o - %s | FileCheck %s -check-prefix=CHECKCXX
+// RUN: %clang_cc1 -triple i686-pc-linux-gnu -verify %s
+
+void __attribute__((aarch64_sve_pcs)) f(int *); // expected-warning {{'aarch64_sve_pcs' calling convention is not supported for this target}}
+
+// CHECKC: define{{.*}} void @g(
+// CHECKCXX: define{{.*}} void @_Z1gPi(
+void g(int *a) {
+
+  // CHECKC: call aarch64_sve_vector_pcs void @f(
+  // CHECKCXX: call aarch64_sve_vector_pcs void @_Z1fPi
+  f(a);
+}
+
+// CHECKC: declare aarch64_sve_vector_pcs void @f(
+// CHECKCXX: declare aarch64_sve_vector_pcs void @_Z1fPi
+
+void __attribute__((aarch64_sve_pcs)) h(int *a) { // expected-warning {{'aarch64_sve_pcs' calling convention is not supported for this target}}
+  // CHECKC: define{{.*}} aarch64_sve_vector_pcs void @h(
+  // CHECKCXX: define{{.*}} aarch64_sve_vector_pcs void @_Z1hPi(
+  f(a);
+}
Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -121,6 +121,7 @@
   case ParsedAttr::AT_SwiftAsyncCall:  \
   case ParsedAttr::AT_VectorCall:  \
   case ParsedAttr::A

[PATCH] D124998: [AArch64][SVE] Add aarch64_sve_pcs attribute to Clang

2022-05-11 Thread Matt Devereau via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG75bb815231f6: [AArch64][SVE] Add aarch64_sve_pcs attribute 
to Clang (authored by MattDevereau).

Changed prior to commit:
  https://reviews.llvm.org/D124998?vs=427335&id=428644#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124998/new/

https://reviews.llvm.org/D124998

Files:
  clang/include/clang-c/Index.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/Specifiers.h
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/CodeGen/aarch64-svepcs.c
  clang/test/Sema/aarch64-svepcs.c
  clang/test/Sema/callingconv.c
  clang/tools/libclang/CXType.cpp

Index: clang/tools/libclang/CXType.cpp
===
--- clang/tools/libclang/CXType.cpp
+++ clang/tools/libclang/CXType.cpp
@@ -666,6 +666,7 @@
   TCALLINGCONV(X86RegCall);
   TCALLINGCONV(X86VectorCall);
   TCALLINGCONV(AArch64VectorCall);
+  TCALLINGCONV(AArch64SVEPCS);
   TCALLINGCONV(Win64);
   TCALLINGCONV(X86_64SysV);
   TCALLINGCONV(AAPCS);
Index: clang/test/Sema/callingconv.c
===
--- clang/test/Sema/callingconv.c
+++ clang/test/Sema/callingconv.c
@@ -52,6 +52,7 @@
 int __attribute__((pcs("foo"))) pcs7(void); // expected-error {{invalid PCS type}}
 
 int __attribute__((aarch64_vector_pcs)) aavpcs(void); // expected-warning {{'aarch64_vector_pcs' calling convention is not supported for this target}}
+int __attribute__((aarch64_sve_pcs)) aasvepcs(void);  // expected-warning {{'aarch64_sve_pcs' calling convention is not supported for this target}}
 
 // PR6361
 void ctest3();
Index: clang/test/Sema/aarch64-svepcs.c
===
--- /dev/null
+++ clang/test/Sema/aarch64-svepcs.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +sve -verify %s
+
+typedef __attribute__((aarch64_sve_pcs)) int invalid_typedef; // expected-warning {{'aarch64_sve_pcs' only applies to function types; type here is 'int'}}
+
+void __attribute__((aarch64_sve_pcs(0))) foo0(void); // expected-error {{'aarch64_sve_pcs' attribute takes no arguments}}
+
+void __attribute__((aarch64_sve_pcs, preserve_all)) foo1(void); // expected-error {{not compatible}}
+
+void __attribute__((cdecl)) foo2(void); // expected-note {{previous declaration is here}}
+void __attribute__((aarch64_sve_pcs)) foo2(void) {} // expected-error {{function declared 'aarch64_sve_pcs' here was previously declared 'cdecl'}}
+
+void foo3(void);// expected-note {{previous declaration is here}}
+void __attribute__((aarch64_sve_pcs)) foo3(void) {} // expected-error {{function declared 'aarch64_sve_pcs' here was previously declared without calling convention}}
+
+typedef int (*fn_ty)(void);
+typedef int __attribute__((aarch64_sve_pcs)) (*aasvepcs_fn_ty)(void);
+void foo4(fn_ty ptr1, aasvepcs_fn_ty ptr2) {
+  ptr1 = ptr2; // expected-warning {{incompatible function pointer types}}
+}
Index: clang/test/CodeGen/aarch64-svepcs.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-svepcs.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECKC
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -x c++ -o - %s | FileCheck %s -check-prefix=CHECKCXX
+// RUN: %clang_cc1 -triple i686-pc-linux-gnu -verify %s
+
+void __attribute__((aarch64_sve_pcs)) f(int *); // expected-warning {{'aarch64_sve_pcs' calling convention is not supported for this target}}
+
+// CHECKC: define{{.*}} void @g(
+// CHECKCXX: define{{.*}} void @_Z1gPi(
+void g(int *a) {
+
+  // CHECKC: call aarch64_sve_vector_pcs void @f(
+  // CHECKCXX: call aarch64_sve_vector_pcs void @_Z1fPi
+  f(a);
+}
+
+// CHECKC: declare aarch64_sve_vector_pcs void @f(
+// CHECKCXX: declare aarch64_sve_vector_pcs void @_Z1fPi
+
+void __attribute__((aarch64_sve_pcs)) h(int *a) { // expected-warning {{'aarch64_sve_pcs' calling convention is not supported for this target}}
+  // CHECKC: define{{.*}} aarch64_sve_vector_pcs void @h(
+  // CHECKCXX: define{{.*}} aarch64_sve_vector_pcs void @_Z1hPi(
+  f(a);
+}
Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -121,6 +121,7 @@
   case ParsedAttr::AT_SwiftAsyncCall:  \
   case ParsedAttr::A

[PATCH] D113489: [AArch64][SVE] Instcombine SVE LD1/ST1 to stock LLVM IR

2021-11-12 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau marked 9 inline comments as done.
MattDevereau added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:732
+  Type *VecTyPtr = II.getType()->getPointerTo();
+  IRBuilder<> Builder(II.getContext());
+  Builder.SetInsertPoint(&II);

DavidTruby wrote:
> Nit: I think the default template arguments should just be picked without the 
> `<>`
I'm getting compiler errors when omitting `<>`



Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:750
+  Value *PtrOp = II.getOperand(1);
+  IRBuilder<> Builder(II.getContext());
+  Builder.SetInsertPoint(&II);

DavidTruby wrote:
> 
I'm getting compiler errors when omitting <>



Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:765
+  Type *VecTyPtr = VecOp->getType()->getPointerTo();
+  IRBuilder<> Builder(II.getContext());
+  Builder.SetInsertPoint(&II);

DavidTruby wrote:
> 
I'm getting compiler errors when omitting <>


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113489/new/

https://reviews.llvm.org/D113489

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D113489: [AArch64][SVE] Instcombine SVE LD1/ST1 to stock LLVM IR

2021-11-16 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau added a comment.

This caused buildbot failures which failed on the bfloat tests. Pushed commit 
83727f27719d3f319f746b473ce09be7e1d99b32 
 to fix 
the issue


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113489/new/

https://reviews.llvm.org/D113489

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D114713: [AArch64][SVE][NEON] Add NEON-SVE-Bridge intrinsics

2021-11-29 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau created this revision.
MattDevereau added reviewers: bsmith, peterwaller-arm, DavidTruby, 
paulwalker-arm.
Herald added subscribers: psnobl, hiraditya, kristof.beyls, tschuett, mgorny.
Herald added a reviewer: efriedma.
MattDevereau requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Adds svset_neonq, svget_neonq, svdup_neonq AArch64 intrinsics.

These are described in the ACLE specification:
https://github.com/ARM-software/acle/pull/72


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D114713

Files:
  clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge.def
  clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge_cg.def
  clang/include/clang/Basic/BuiltinsSVE.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/arm_neon_sve_bridge.h
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_dup_neonq.c
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_get_neonq.c
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1322,6 +1322,7 @@
   setOperationAction(ISD::MGATHER, VT, Custom);
   setOperationAction(ISD::MSCATTER, VT, Custom);
   setOperationAction(ISD::MLOAD, VT, Custom);
+  setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
 }
 
 setOperationAction(ISD::SPLAT_VECTOR, MVT::nxv8bf16, Custom);
Index: clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c
@@ -0,0 +1,188 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o /dev/null %s
+#include 
+
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+
+// CHECK-LABEL: @test_svset_neonq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v16i8( [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z19test_svset_neonq_s8u10__SVInt8_t11__Int8x16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v16i8( [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint8_t test_svset_neonq_s8(svint8_t s, int8x16_t n)
+{
+  return SVE_ACLE_FUNC(svset_neonq,_s8,,)(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv8i16.v8i16( [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s16u11__SVInt16_t11__Int16x8_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv8i16.v8i16( [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint16_t test_svset_neonq_s16(svint16_t s, int16x8_t n)
+{
+  return SVE_ACLE_FUNC(svset_neonq,_s16,,)(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v4i32( [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s32u11__SVInt32_t11__Int32x4_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v4i32( [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint32_t test_svset_neonq_s32(svint32_t s, int32x4_t n)
+{
+  return SVE_ACLE_FUNC(svset_neonq,_s32,,)(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s64(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv2i64.v2i64( [[S:%.*]], <2 x i64> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL:

[PATCH] D114713: [AArch64][SVE][NEON] Add NEON-SVE-Bridge intrinsics

2021-11-30 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1325
   setOperationAction(ISD::MLOAD, VT, Custom);
+  setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
 }

paulwalker-arm wrote:
> Can you extract this into its own patch as it's really not relevant to the 
> rest of the patch and is currently missing tests.  Presumably 
> `llvm/test/CodeGen/AArch64/sve-insert-vector.ll` needs updating?
i've been adding some tests to assert this block of code. i've got tests for 
`insert(vscale x n x bfloat, n x bfloat, idx)` and `insert(vscale x n x bfloat, 
vscale x n x bfloat, idx)`.
the n = 4 and n = 8 tests are fine, but n = 2 for `insert(vscale x 2 x bfloat, 
2 x bfloat, idx)`  fails an assertion. i've had a quick poke around but haven't 
seen an obvious reason why its failing, should I worry about this and spend 
more time on it or just submit the tests i've already got for `4bf16` and 
`8bf16`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114713/new/

https://reviews.llvm.org/D114713

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D114713: [AArch64][SVE][NEON] Add NEON-SVE-Bridge intrinsics

2021-11-30 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau updated this revision to Diff 390731.
MattDevereau added a comment.

updated builtin signatures in 
`clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge.def`
removed irrelevant change in `llvm/lib/Target/AArch64/AArch64ISelLowering.cpp`
ran clang-format


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114713/new/

https://reviews.llvm.org/D114713

Files:
  clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge.def
  clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge_cg.def
  clang/include/clang/Basic/BuiltinsSVE.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/arm_neon_sve_bridge.h
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_dup_neonq.c
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_get_neonq.c
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c

Index: clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c
@@ -0,0 +1,176 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o /dev/null %s
+#include 
+
+#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
+
+// CHECK-LABEL: @test_svset_neonq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v16i8( [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z19test_svset_neonq_s8u10__SVInt8_t11__Int8x16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v16i8( [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint8_t test_svset_neonq_s8(svint8_t s, int8x16_t n) {
+  return SVE_ACLE_FUNC(svset_neonq, _s8, , )(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv8i16.v8i16( [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s16u11__SVInt16_t11__Int16x8_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv8i16.v8i16( [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint16_t test_svset_neonq_s16(svint16_t s, int16x8_t n) {
+  return SVE_ACLE_FUNC(svset_neonq, _s16, , )(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v4i32( [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s32u11__SVInt32_t11__Int32x4_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v4i32( [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint32_t test_svset_neonq_s32(svint32_t s, int32x4_t n) {
+  return SVE_ACLE_FUNC(svset_neonq, _s32, , )(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s64(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv2i64.v2i64( [[S:%.*]], <2 x i64> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s64u11__SVInt64_t11__Int64x2_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv2i64.v2i64( [[S:%.*]], <2 x i64> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint64_t test_svset_neonq_s64(svint64_t s, int64x2_t n) {
+  return SVE_ACLE_FUNC(svset_neonq, _s64, , )(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_u8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v16i8( [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z19test_svset_neonq_u8u11__SVUint8_t12__Uint8x16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v16i8( [[S:%.*]], <16 x i8>

[PATCH] D114713: [AArch64][SVE][NEON] Add NEON-SVE-Bridge intrinsics

2021-12-02 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau marked an inline comment as done.
MattDevereau added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1325
   setOperationAction(ISD::MLOAD, VT, Custom);
+  setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
 }

paulwalker-arm wrote:
> MattDevereau wrote:
> > paulwalker-arm wrote:
> > > Can you extract this into its own patch as it's really not relevant to 
> > > the rest of the patch and is currently missing tests.  Presumably 
> > > `llvm/test/CodeGen/AArch64/sve-insert-vector.ll` needs updating?
> > i've been adding some tests to assert this block of code. i've got tests 
> > for `insert(vscale x n x bfloat, n x bfloat, idx)` and `insert(vscale x n x 
> > bfloat, vscale x n x bfloat, idx)`.
> > the n = 4 and n = 8 tests are fine, but n = 2 for `insert(vscale x 2 x 
> > bfloat, 2 x bfloat, idx)`  fails an assertion. i've had a quick poke around 
> > but haven't seen an obvious reason why its failing, should I worry about 
> > this and spend more time on it or just submit the tests i've already got 
> > for `4bf16` and `8bf16`?
> Obviously it would be nice for all combinations to work but that's not 
> something you have to fix if it's not directly affecting what you need.
> 
> I've checked and it seems `2 x half` doesn't work out of the box either so it 
> sounds reasonable to me for your new `bfloat` handling to mirror the existing 
> supported `half` use cases only.
Resolved this in 4244f95cc6ce73ab38fbb91929a0888309f3ca8d


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114713/new/

https://reviews.llvm.org/D114713

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D114713: [AArch64][SVE][NEON] Add NEON-SVE-Bridge intrinsics

2021-12-03 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau updated this revision to Diff 391595.
MattDevereau added a comment.

updated SVEMAP2 types
added overloadable intrinsics
updated BUILTIN function signatures


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114713/new/

https://reviews.llvm.org/D114713

Files:
  clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge.def
  clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge_cg.def
  clang/include/clang/Basic/BuiltinsSVE.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/arm_neon_sve_bridge.h
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_dup_neonq.c
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_get_neonq.c
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c

Index: clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c
@@ -0,0 +1,183 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o /dev/null %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+// CHECK-LABEL: @test_svset_neonq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v16i8( [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z19test_svset_neonq_s8u10__SVInt8_t11__Int8x16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v16i8( [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint8_t test_svset_neonq_s8(svint8_t s, int8x16_t n) {
+  return SVE_ACLE_FUNC(svset_neonq, _s8, , )(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv8i16.v8i16( [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s16u11__SVInt16_t11__Int16x8_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv8i16.v8i16( [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint16_t test_svset_neonq_s16(svint16_t s, int16x8_t n) {
+  return SVE_ACLE_FUNC(svset_neonq, _s16, , )(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v4i32( [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s32u11__SVInt32_t11__Int32x4_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v4i32( [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint32_t test_svset_neonq_s32(svint32_t s, int32x4_t n) {
+  return SVE_ACLE_FUNC(svset_neonq, _s32, , )(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s64(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv2i64.v2i64( [[S:%.*]], <2 x i64> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s64u11__SVInt64_t11__Int64x2_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv2i64.v2i64( [[S:%.*]], <2 x i64> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//

[PATCH] D114713: [AArch64][SVE][NEON] Add NEON-SVE-Bridge intrinsics

2021-12-03 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau updated this revision to Diff 391616.
MattDevereau added a comment.

run clang format to fix test macro


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114713/new/

https://reviews.llvm.org/D114713

Files:
  clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge.def
  clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge_cg.def
  clang/include/clang/Basic/BuiltinsSVE.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/arm_neon_sve_bridge.h
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_dup_neonq.c
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_get_neonq.c
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c

Index: clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c
@@ -0,0 +1,183 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o /dev/null %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
+#endif
+
+// CHECK-LABEL: @test_svset_neonq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v16i8( [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z19test_svset_neonq_s8u10__SVInt8_t11__Int8x16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v16i8( [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint8_t test_svset_neonq_s8(svint8_t s, int8x16_t n) {
+  return SVE_ACLE_FUNC(svset_neonq, _s8, , )(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv8i16.v8i16( [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s16u11__SVInt16_t11__Int16x8_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv8i16.v8i16( [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint16_t test_svset_neonq_s16(svint16_t s, int16x8_t n) {
+  return SVE_ACLE_FUNC(svset_neonq, _s16, , )(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v4i32( [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s32u11__SVInt32_t11__Int32x4_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v4i32( [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint32_t test_svset_neonq_s32(svint32_t s, int32x4_t n) {
+  return SVE_ACLE_FUNC(svset_neonq, _s32, , )(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s64(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv2i64.v2i64( [[S:%.*]], <2 x i64> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s64u11__SVInt64_t11__Int64x2_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv2i64.v2i64( [[S:%.*]], <2 x i64> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint64

[PATCH] D114713: [AArch64][SVE][NEON] Add NEON-SVE-Bridge intrinsics

2021-12-06 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau updated this revision to Diff 392015.
MattDevereau added a comment.

replace numbers in BuiltinsAArch64NeonSVEBridge_cg.def with SVETypeFlags enum 
values


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114713/new/

https://reviews.llvm.org/D114713

Files:
  clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge.def
  clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge_cg.def
  clang/include/clang/Basic/BuiltinsSVE.def
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/arm_neon_sve_bridge.h
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_dup_neonq.c
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_get_neonq.c
  
clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c

Index: clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64_neon_sve_bridge_intrinsics/acle_neon_sve_bridge_set_neonq.c
@@ -0,0 +1,183 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o /dev/null %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
+#endif
+
+// CHECK-LABEL: @test_svset_neonq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v16i8( [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z19test_svset_neonq_s8u10__SVInt8_t11__Int8x16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v16i8( [[S:%.*]], <16 x i8> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint8_t test_svset_neonq_s8(svint8_t s, int8x16_t n) {
+  return SVE_ACLE_FUNC(svset_neonq, _s8, , )(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv8i16.v8i16( [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s16u11__SVInt16_t11__Int16x8_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv8i16.v8i16( [[S:%.*]], <8 x i16> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint16_t test_svset_neonq_s16(svint16_t s, int16x8_t n) {
+  return SVE_ACLE_FUNC(svset_neonq, _s16, , )(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v4i32( [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s32u11__SVInt32_t11__Int32x4_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v4i32( [[S:%.*]], <4 x i32> [[N:%.*]], i64 0)
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint32_t test_svset_neonq_s32(svint32_t s, int32x4_t n) {
+  return SVE_ACLE_FUNC(svset_neonq, _s32, , )(s, n);
+}
+
+// CHECK-LABEL: @test_svset_neonq_s64(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv2i64.v2i64( [[S:%.*]], <2 x i64> [[N:%.*]], i64 0)
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svset_neonq_s64u11__SVInt64_t11__Int64x2_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = call  @llvm.experimental.vector.insert.nxv2i64.v2i64( [[S:%.*]], <2 x i64> [[N:%.*]], i64 0

[PATCH] D114713: [AArch64][SVE][NEON] Add NEON-SVE-Bridge intrinsics

2021-12-06 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau marked an inline comment as done.
MattDevereau added a comment.

clang-format is upset about this ordering:

#include "clang/Basic/arm_sve_builtin_cg.inc"
#include "clang/Basic/BuiltinsAArch64NeonSVEBridge_cg.def"

but swapping the order causes all SVE tests to fail. I'm ignoring the 
clang-format error for this




Comment at: clang/include/clang/Basic/BuiltinsAArch64NeonSVEBridge_cg.def:37
+SVEMAP2(svdup_neonq_f64, 3),
+SVEMAP2(svdup_neonq_bf16, 1),
+#endif

peterwaller-arm wrote:
> The second argument is a 'flags' field and these values don't look right.
> 
> Refs:
> 
> * [[ 
> https://github.com/llvm/llvm-project/blob/84b978da3b80b986327a830c01e32f12cefe86b3/clang/utils/TableGen/SveEmitter.cpp#L1339
>  | SVEMAP2 emitted by tablegen ]]
> * [[ 
> https://github.com/llvm/llvm-project/blob/84b978da3b80b986327a830c01e32f12cefe86b3/clang/include/clang/Basic/arm_sve.td#L137-L149
>  | Element types ]]
> * [[ 
> https://github.com/llvm/llvm-project/blob/main/clang/lib/CodeGen/CGBuiltin.cpp#L9070
>  | Flags used in CGBuiltin ]]
> 
> The flags are a generated enum and live in 
> `clang/include/clang/Basic/arm_sve_typeflags.inc` -- I think you'll need to 
> #include this with `LLVM_GET_SVE_ELTTYPES` defined, and then you can write it 
> symbolically rather than using a literal numeric value.
SVETypeFlags enums are already available by this stage so there's no need for 
any includes. I've replaced the numbers with the enums


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114713/new/

https://reviews.llvm.org/D114713

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D156115: [Clang][SVE] Permit specific predicate-as-counter registers in inline assembly

2023-07-24 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau added inline comments.



Comment at: clang/test/CodeGen/aarch64-sve-inline-asm.c:17
+
+void test_sve2p1_asm(void) {
+  register __SVCount_t x2 asm("pn0");

I think it would be better to keep this test similar to `test_sve_asm` in that 
it tests both ends of the range of predicate registers and also tests it can be 
used as an operand to other valid instructions. Right now it feels like the 
bare minimum.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156115/new/

https://reviews.llvm.org/D156115

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D157517: [AArch64][SVE] Add asm predicate constraint Uph

2023-08-11 Thread Matt Devereau via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc52d9509d40d: [AArch64][SVE] Add asm predicate constraint 
Uph (authored by MattDevereau).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157517/new/

https://reviews.llvm.org/D157517

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
  llvm/docs/LangRef.rst
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll

Index: llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
===
--- llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
+++ llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
@@ -68,3 +68,14 @@
   %1 = tail call  asm "incp $0.s, $1", "=w,@3Upa,0"( %Pg,  %Zn)
   ret  %1
 }
+
+; Function Attrs: nounwind readnone
+; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z1
+; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
+; CHECK: [[ARG3:%[0-9]+]]:ppr = COPY $p0
+; CHECK: [[ARG4:%[0-9]+]]:ppr_p8to15 = COPY [[ARG3]]
+; CHECK: INLINEASM {{.*}} [[ARG4]]
+define  @test_svfadd_f16_Uph_constraint( %Pg,  %Zn,  %Zm) {
+  %1 = tail call  asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Uph,w,w"( %Pg,  %Zn,  %Zm)
+  ret  %1
+}
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9987,19 +9987,31 @@
   return "r";
 }
 
-enum PredicateConstraint {
-  Upl,
-  Upa,
-  Invalid
-};
+enum PredicateConstraint { Uph, Upl, Upa, Invalid };
 
 static PredicateConstraint parsePredicateConstraint(StringRef Constraint) {
-  PredicateConstraint P = PredicateConstraint::Invalid;
-  if (Constraint == "Upa")
-P = PredicateConstraint::Upa;
-  if (Constraint == "Upl")
-P = PredicateConstraint::Upl;
-  return P;
+  return StringSwitch(Constraint)
+  .Case("Uph", PredicateConstraint::Uph)
+  .Case("Upl", PredicateConstraint::Upl)
+  .Case("Upa", PredicateConstraint::Upa)
+  .Default(PredicateConstraint::Invalid);
+}
+
+static const TargetRegisterClass *
+getPredicateRegisterClass(PredicateConstraint Constraint, EVT VT) {
+  if (!VT.isScalableVector() || VT.getVectorElementType() != MVT::i1)
+return nullptr;
+
+  switch (Constraint) {
+  default:
+return nullptr;
+  case PredicateConstraint::Uph:
+return &AArch64::PPR_p8to15RegClass;
+  case PredicateConstraint::Upl:
+return &AArch64::PPR_3bRegClass;
+  case PredicateConstraint::Upa:
+return &AArch64::PPRRegClass;
+  }
 }
 
 // The set of cc code supported is from
@@ -10191,13 +10203,8 @@
 }
   } else {
 PredicateConstraint PC = parsePredicateConstraint(Constraint);
-if (PC != PredicateConstraint::Invalid) {
-  if (!VT.isScalableVector() || VT.getVectorElementType() != MVT::i1)
-return std::make_pair(0U, nullptr);
-  bool restricted = (PC == PredicateConstraint::Upl);
-  return restricted ? std::make_pair(0U, &AArch64::PPR_3bRegClass)
-: std::make_pair(0U, &AArch64::PPRRegClass);
-}
+if (const TargetRegisterClass *RegClass = getPredicateRegisterClass(PC, VT))
+  return std::make_pair(0U, RegClass);
   }
   if (StringRef("{cc}").equals_insensitive(Constraint) ||
   parseConstraintCode(Constraint) != AArch64CC::Invalid)
Index: llvm/docs/LangRef.rst
===
--- llvm/docs/LangRef.rst
+++ llvm/docs/LangRef.rst
@@ -4997,7 +4997,8 @@
 - ``w``: A 32, 64, or 128-bit floating-point, SIMD or SVE vector register.
 - ``x``: Like w, but restricted to registers 0 to 15 inclusive.
 - ``y``: Like w, but restricted to SVE vector registers Z0 to Z7 inclusive.
-- ``Upl``: One of the low eight SVE predicate registers (P0 to P7)
+- ``Uph``: One of the upper eight SVE predicate registers (P8 to P15)
+- ``Upl``: One of the lower eight SVE predicate registers (P0 to P7)
 - ``Upa``: Any of the SVE predicate registers (P0 to P15)
 
 AMDGPU:
Index: clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
===
--- clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
+++ clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
@@ -168,6 +168,30 @@
 SVBOOL_TEST_UPL(__SVInt64_t, d) ;
 // CHECK: call  asm sideeffect "fadd $0.d, $1.d, $2.d, $3.d\0A", "=w,@3Upl,w,w"( %in1,  %in2,  %in3)
 
+#define SVBOOL_TEST_UPH(DT, KIND)\
+__SVBool_t func_bool_uph_##KIND(__SVBool_t in1, DT in2, DT in3)\
+{\
+  __SVBool_t out;\
+  asm volatile (\
+"fadd %[out]." #KIND ", %[in1]." #KIND ", %[in2]." #KIND ", %[in3]." #KIND "\n"\
+: [out] "=w" (out)\
+:  [in1] "Uph" (in1),\
+  [in2] "w" (in2),\
+  [in3] "w" (in3)\
+:);\
+  return out;\
+}
+
+SVBOOL_TEST_UPH(__SVInt8_t, b) ;
+// CHECK: call  asm sideeffect "fadd $0.b, $1.b, $2.b, $3.b\0A", "=w,@3Uph,w,w"( %in1,  %in2,  %in

[PATCH] D157517: [AArch64][SVE] Add asm predicate constraint Uph

2023-08-10 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau updated this revision to Diff 548965.
MattDevereau added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

@sdesmalen I had to make an additional changes to 
`clang/lib/Basic/Targets/AArch64.cpp` and 
`clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c` To get the constraint 
parsing from the clang level. It's pretty minor but thought I'd update the 
review before pushing in case you've anything to add.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157517/new/

https://reviews.llvm.org/D157517

Files:
  clang/lib/Basic/Targets/AArch64.cpp
  clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
  llvm/docs/LangRef.rst
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll

Index: llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
===
--- llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
+++ llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
@@ -68,3 +68,14 @@
   %1 = tail call  asm "incp $0.s, $1", "=w,@3Upa,0"( %Pg,  %Zn)
   ret  %1
 }
+
+; Function Attrs: nounwind readnone
+; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z1
+; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
+; CHECK: [[ARG3:%[0-9]+]]:ppr = COPY $p0
+; CHECK: [[ARG4:%[0-9]+]]:ppr_p8to15 = COPY [[ARG3]]
+; CHECK: INLINEASM {{.*}} [[ARG4]]
+define  @test_svfadd_f16_Uph_constraint( %Pg,  %Zn,  %Zm) {
+  %1 = tail call  asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Uph,w,w"( %Pg,  %Zn,  %Zm)
+  ret  %1
+}
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9978,19 +9978,31 @@
   return "r";
 }
 
-enum PredicateConstraint {
-  Upl,
-  Upa,
-  Invalid
-};
+enum PredicateConstraint { Uph, Upl, Upa, Invalid };
 
 static PredicateConstraint parsePredicateConstraint(StringRef Constraint) {
-  PredicateConstraint P = PredicateConstraint::Invalid;
-  if (Constraint == "Upa")
-P = PredicateConstraint::Upa;
-  if (Constraint == "Upl")
-P = PredicateConstraint::Upl;
-  return P;
+  return StringSwitch(Constraint)
+  .Case("Uph", PredicateConstraint::Uph)
+  .Case("Upl", PredicateConstraint::Upl)
+  .Case("Upa", PredicateConstraint::Upa)
+  .Default(PredicateConstraint::Invalid);
+}
+
+static const TargetRegisterClass *
+getPredicateRegisterClass(PredicateConstraint Constraint, EVT VT) {
+  if (!VT.isScalableVector() || VT.getVectorElementType() != MVT::i1)
+return nullptr;
+
+  switch (Constraint) {
+  default:
+return nullptr;
+  case PredicateConstraint::Uph:
+return &AArch64::PPR_p8to15RegClass;
+  case PredicateConstraint::Upl:
+return &AArch64::PPR_3bRegClass;
+  case PredicateConstraint::Upa:
+return &AArch64::PPRRegClass;
+  }
 }
 
 // The set of cc code supported is from
@@ -10182,13 +10194,8 @@
 }
   } else {
 PredicateConstraint PC = parsePredicateConstraint(Constraint);
-if (PC != PredicateConstraint::Invalid) {
-  if (!VT.isScalableVector() || VT.getVectorElementType() != MVT::i1)
-return std::make_pair(0U, nullptr);
-  bool restricted = (PC == PredicateConstraint::Upl);
-  return restricted ? std::make_pair(0U, &AArch64::PPR_3bRegClass)
-: std::make_pair(0U, &AArch64::PPRRegClass);
-}
+if (const TargetRegisterClass *RegClass = getPredicateRegisterClass(PC, VT))
+  return std::make_pair(0U, RegClass);
   }
   if (StringRef("{cc}").equals_insensitive(Constraint) ||
   parseConstraintCode(Constraint) != AArch64CC::Invalid)
Index: llvm/docs/LangRef.rst
===
--- llvm/docs/LangRef.rst
+++ llvm/docs/LangRef.rst
@@ -4994,7 +4994,8 @@
 - ``w``: A 32, 64, or 128-bit floating-point, SIMD or SVE vector register.
 - ``x``: Like w, but restricted to registers 0 to 15 inclusive.
 - ``y``: Like w, but restricted to SVE vector registers Z0 to Z7 inclusive.
-- ``Upl``: One of the low eight SVE predicate registers (P0 to P7)
+- ``Uph``: One of the upper eight SVE predicate registers (P8 to P15)
+- ``Upl``: One of the lower eight SVE predicate registers (P0 to P7)
 - ``Upa``: Any of the SVE predicate registers (P0 to P15)
 
 AMDGPU:
Index: clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
===
--- clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
+++ clang/test/CodeGen/aarch64-sve-inline-asm-datatypes.c
@@ -168,6 +168,30 @@
 SVBOOL_TEST_UPL(__SVInt64_t, d) ;
 // CHECK: call  asm sideeffect "fadd $0.d, $1.d, $2.d, $3.d\0A", "=w,@3Upl,w,w"( %in1,  %in2,  %in3)
 
+#define SVBOOL_TEST_UPH(DT, KIND)\
+__SVBool_t func_bool_uph_##KIND(__SVBool_t in1, DT in2, DT in3)\
+{\
+  __SVBool_t out;\
+  asm volatile (\
+"fadd %[out]." #KIND ", %[in1]." #KIND ", %[in2]." #KIND ", %[in3]." #KIND

[PATCH] D145505: [AArch64][SVE] Add svboolx2_t and svboolx4_t tuple types

2023-03-07 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau created this revision.
MattDevereau added reviewers: sdesmalen, CarolineConcatto, peterwaller-arm.
Herald added subscribers: psnobl, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: All.
MattDevereau requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145505

Files:
  clang/include/clang/Basic/AArch64SVEACLETypes.def
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/Type.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/test/CodeGen/svboolx2_t.cpp
  clang/test/CodeGen/svboolx4_t.cpp
  clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1140,7 +1140,9 @@
   OS << "typedef __clang_svfloat16x4_t svfloat16x4_t;\n";
   OS << "typedef __clang_svfloat32x4_t svfloat32x4_t;\n";
   OS << "typedef __clang_svfloat64x4_t svfloat64x4_t;\n";
-  OS << "typedef __SVBool_t  svbool_t;\n\n";
+  OS << "typedef __SVBool_t  svbool_t;\n";
+  OS << "typedef __clang_svboolx2_t  svboolx2_t;\n";
+  OS << "typedef __clang_svboolx4_t  svboolx4_t;\n\n";
 
   OS << "typedef __clang_svbfloat16x2_t svbfloat16x2_t;\n";
   OS << "typedef __clang_svbfloat16x3_t svbfloat16x3_t;\n";
Index: clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
===
--- clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
+++ clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
@@ -106,3 +106,7 @@
 void f47(S<__clang_svbfloat16x3_t>) {}
 // CHECK: _Z3f481SI14svbfloat16x4_tE
 void f48(S<__clang_svbfloat16x4_t>) {}
+// CHECK: _Z3f491SI10svboolx2_tE
+void f49(S<__clang_svboolx2_t>) {}
+// CHECK: _Z3f501SI10svboolx4_tE
+void f50(S<__clang_svboolx4_t>) {}
Index: clang/test/CodeGen/svboolx4_t.cpp
===
--- /dev/null
+++ clang/test/CodeGen/svboolx4_t.cpp
@@ -0,0 +1,31 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -emit-llvm -o - %s | FileCheck %s
+
+// CHECK-LABEL: @_Z3foo10svboolx4_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[ARG_ADDR:%.*]] = alloca , align 2
+// CHECK-NEXT:store  [[ARG:%.*]], ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load , ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:ret  [[TMP0]]
+//
+__clang_svboolx4_t foo(__clang_svboolx4_t arg) { return arg; }
+
+__clang_svboolx4_t bar();
+// CHECK-LABEL: @_Z4foo2v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[CALL:%.*]] = call  @_Z3barv()
+// CHECK-NEXT:ret  [[CALL]]
+//
+__clang_svboolx4_t foo2() { return bar(); }
+
+__clang_svboolx4_t bar2(__clang_svboolx4_t);
+// CHECK-LABEL: @_Z4foo310svboolx4_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[ARG_ADDR:%.*]] = alloca , align 2
+// CHECK-NEXT:store  [[ARG:%.*]], ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load , ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:[[CALL:%.*]] = call  @_Z4bar210svboolx4_t( [[TMP0]])
+// CHECK-NEXT:ret  [[CALL]]
+//
+__clang_svboolx4_t foo3(__clang_svboolx4_t arg) { return bar2(arg); }
+
Index: clang/test/CodeGen/svboolx2_t.cpp
===
--- /dev/null
+++ clang/test/CodeGen/svboolx2_t.cpp
@@ -0,0 +1,31 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -emit-llvm -o - %s | FileCheck %s
+
+// CHECK-LABEL: @_Z3foo10svboolx2_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[ARG_ADDR:%.*]] = alloca , align 2
+// CHECK-NEXT:store  [[ARG:%.*]], ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load , ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:ret  [[TMP0]]
+//
+__clang_svboolx2_t foo(__clang_svboolx2_t arg) { return arg; }
+
+__clang_svboolx2_t bar();
+// CHECK-LABEL: @_Z4foo2v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[CALL:%.*]] = call  @_Z3barv()
+// CHECK-NEXT:ret  [[CALL]]
+//
+__clang_svboolx2_t foo2() { return bar(); }
+
+__clang_svboolx2_t bar2(__clang_svboolx2_t);
+// CHECK-LABEL: @_Z4foo310svboolx2_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[ARG_ADDR:%.*]] = alloca , align 2
+// CHECK-NEXT:store  [[ARG:%.*]], ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load , ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:[[CALL:%.*]] = call  @_Z4bar210svboolx2_t( [[TMP0]])
+// CHECK-NEXT:ret  [[CALL]]
+//
+__clang_svboolx2_t foo3(__clang_svboolx2_t arg) { return bar2(arg); }
+
Index: clang/lib/CodeGen/CodeGenTypes.cpp
===
--- clang/lib/CodeGen/CodeGenTypes.cpp
++

[PATCH] D145505: [AArch64][SVE] Add svboolx2_t and svboolx4_t tuple types

2023-03-13 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau updated this revision to Diff 504588.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145505/new/

https://reviews.llvm.org/D145505

Files:
  clang/include/clang/Basic/AArch64SVEACLETypes.def
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/Type.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/test/CodeGen/svboolx2_t.cpp
  clang/test/CodeGen/svboolx4_t.cpp
  clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1140,7 +1140,9 @@
   OS << "typedef __clang_svfloat16x4_t svfloat16x4_t;\n";
   OS << "typedef __clang_svfloat32x4_t svfloat32x4_t;\n";
   OS << "typedef __clang_svfloat64x4_t svfloat64x4_t;\n";
-  OS << "typedef __SVBool_t  svbool_t;\n\n";
+  OS << "typedef __SVBool_t  svbool_t;\n";
+  OS << "typedef __clang_svboolx2_t  svboolx2_t;\n";
+  OS << "typedef __clang_svboolx4_t  svboolx4_t;\n\n";
 
   OS << "typedef __clang_svbfloat16x2_t svbfloat16x2_t;\n";
   OS << "typedef __clang_svbfloat16x3_t svbfloat16x3_t;\n";
Index: clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
===
--- clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
+++ clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
@@ -108,3 +108,7 @@
 void f47(S<__clang_svbfloat16x3_t>) {}
 // CHECK: _Z3f481SI14svbfloat16x4_tE
 void f48(S<__clang_svbfloat16x4_t>) {}
+// CHECK: _Z3f491SI10svboolx2_tE
+void f49(S<__clang_svboolx2_t>) {}
+// CHECK: _Z3f501SI10svboolx4_tE
+void f50(S<__clang_svboolx4_t>) {}
Index: clang/test/CodeGen/svboolx4_t.cpp
===
--- /dev/null
+++ clang/test/CodeGen/svboolx4_t.cpp
@@ -0,0 +1,31 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -emit-llvm -o - %s | FileCheck %s
+
+// CHECK-LABEL: @_Z3foo10svboolx4_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[ARG_ADDR:%.*]] = alloca , align 2
+// CHECK-NEXT:store  [[ARG:%.*]], ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load , ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:ret  [[TMP0]]
+//
+__clang_svboolx4_t foo(__clang_svboolx4_t arg) { return arg; }
+
+__clang_svboolx4_t bar();
+// CHECK-LABEL: @_Z4foo2v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[CALL:%.*]] = call  @_Z3barv()
+// CHECK-NEXT:ret  [[CALL]]
+//
+__clang_svboolx4_t foo2() { return bar(); }
+
+__clang_svboolx4_t bar2(__clang_svboolx4_t);
+// CHECK-LABEL: @_Z4foo310svboolx4_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[ARG_ADDR:%.*]] = alloca , align 2
+// CHECK-NEXT:store  [[ARG:%.*]], ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load , ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:[[CALL:%.*]] = call  @_Z4bar210svboolx4_t( [[TMP0]])
+// CHECK-NEXT:ret  [[CALL]]
+//
+__clang_svboolx4_t foo3(__clang_svboolx4_t arg) { return bar2(arg); }
+
Index: clang/test/CodeGen/svboolx2_t.cpp
===
--- /dev/null
+++ clang/test/CodeGen/svboolx2_t.cpp
@@ -0,0 +1,31 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -emit-llvm -o - %s | FileCheck %s
+
+// CHECK-LABEL: @_Z3foo10svboolx2_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[ARG_ADDR:%.*]] = alloca , align 2
+// CHECK-NEXT:store  [[ARG:%.*]], ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load , ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:ret  [[TMP0]]
+//
+__clang_svboolx2_t foo(__clang_svboolx2_t arg) { return arg; }
+
+__clang_svboolx2_t bar();
+// CHECK-LABEL: @_Z4foo2v(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[CALL:%.*]] = call  @_Z3barv()
+// CHECK-NEXT:ret  [[CALL]]
+//
+__clang_svboolx2_t foo2() { return bar(); }
+
+__clang_svboolx2_t bar2(__clang_svboolx2_t);
+// CHECK-LABEL: @_Z4foo310svboolx2_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[ARG_ADDR:%.*]] = alloca , align 2
+// CHECK-NEXT:store  [[ARG:%.*]], ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load , ptr [[ARG_ADDR]], align 2
+// CHECK-NEXT:[[CALL:%.*]] = call  @_Z4bar210svboolx2_t( [[TMP0]])
+// CHECK-NEXT:ret  [[CALL]]
+//
+__clang_svboolx2_t foo3(__clang_svboolx2_t arg) { return bar2(arg); }
+
Index: clang/lib/CodeGen/CodeGenTypes.cpp
===
--- clang/lib/CodeGen/CodeGenTypes.cpp
+++ clang/lib/CodeGen/CodeGenTypes.cpp
@@ -596,6 +596,8 @@
 case BuiltinType::SveInt64x4:
 case BuiltinType::SveUint64x4:
 case BuiltinType::SveBool:
+case BuiltinType::SveBoolx2:
+case BuiltinType::SveBoolx4:
 cas

[PATCH] D145505: [AArch64][SVE] Add svboolx2_t and svboolx4_t tuple types

2023-03-14 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau closed this revision.
MattDevereau added a comment.

a1fae98ba95c18ea6b673fc3c177b917e0f5aa56 



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145505/new/

https://reviews.llvm.org/D145505

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D119926: [Clang][AArch64] Enable _Float16 _Complex type

2022-02-28 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau abandoned this revision.
MattDevereau added a comment.

Abandoning this patch as it is redundant due to changes in D105331 
. This patch also drew attention to unused 
code removed in 841355c1e4e35fc02b5b171419979f5f9af0ebc8 
. Many 
thanks to @aaron.ballman


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119926/new/

https://reviews.llvm.org/D119926

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D114713: [AArch64][SVE][NEON] Add NEON-SVE-Bridge intrinsics

2021-12-13 Thread Matt Devereau via Phabricator via cfe-commits 
MattDevereau closed this revision.
MattDevereau added a comment.

41def32040787e917b52279cc30231b27f2f02f7 



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114713/new/

https://reviews.llvm.org/D114713

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits