[PATCH] D103702: [AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries

2021-06-21 Thread Matt D. via Phabricator via cfe-commits 
Matt added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64TargetMachine.cpp:161
 EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
 cl::desc("Enable the AAcrh64 branch target pass"),
 cl::init(true));

Just noticed a small typo: s/AAcrh64/AArch64/


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[PATCH] D134352: [AArch64] Add Neoverse V2 CPU support

2022-09-22 Thread Matt D. via Phabricator via cfe-commits 
Matt added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64.td:1112
+   FeatureNEON, FeatureSVE2BitPerm, 
FeatureFP16FML,
+   FeatureMTE, FeatureRandGen];
   list Saphira= [HasV8_4aOps, FeatureCrypto, 
FeatureFPARMv8,

Shouldn't `FeatureMTE` (Enable Memory Tagging Extension) be present, too (as in 
NeoverseN2)?


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[PATCH] D134352: [AArch64] Add Neoverse V2 CPU support

2022-09-23 Thread Matt D. via Phabricator via cfe-commits 
Matt added inline comments.



Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:239
+AARCH64_CPU_NAME("neoverse-v2", ARMV9A, FK_NEON_FP_ARMV8, false,
+ (AArch64::AEK_SVE | AArch64::AEK_SVE2 | AArch64::AEK_SSBS |
+  AArch64::AEK_FP16 | AArch64::AEK_BF16 | AArch64::AEK_RAND |

Should `AEK_SVE2BITPERM` be present? (Noticed that N2 has ` AArch64::AEK_SVE2 | 
AArch64::AEK_SVE2BITPERM`).



Comment at: llvm/lib/Target/AArch64/AArch64.td:
+   FeaturePerfMon, FeatureETE, 
FeatureMatMulInt8,
+   FeatureNEON, FeatureSVE2BitPerm, 
FeatureFP16FML,
+   FeatureMTE, FeatureRandGen];

`FeatureNEON` may be redundant (note that it's in `HasV8_3aOps`).

OTOH, `NeoverseV1` also has `FeatureCrypto`: is this no longer the case for 
`NeoverseV2`?



Comment at: llvm/lib/Target/AArch64/AArch64Subtarget.cpp:202
   case NeoverseN2:
+  case NeoverseV2:
 PrefFunctionLogAlignment = 4;

Are `CacheLineSize` (`= 0` by default) and `MaxInterleaveFactor` (`= 2` by 
default) the same / correct for both N2 and V2?


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[PATCH] D134352: [AArch64] Add Neoverse V2 CPU support

2022-09-26 Thread Matt D. via Phabricator via cfe-commits 
Matt added a comment.

OK, thanks!


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[PATCH] D158252: Fix regression of D157680

2023-08-18 Thread Matt D. via Phabricator via cfe-commits 
Matt added inline comments.



Comment at: llvm/test/CodeGen/X86/x86-prefer-no-gather-no-scatter.ll:3
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2,+fast-gather %s -o - 
| FileCheck %s --check-prefixes=GATHER
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu 
-mattr=+avx2,+fast-gather,+prefer-no-gather %s -o - | FileCheck %s 
--check-prefixes=NO-GATHER
 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu  -mattr=+avx512vl,+avx512dq < %s 
| FileCheck %s --check-prefix=SCATTER

Thinking out loud about this combination, does it ever make sense for any 
subtarget to have both `+fast-gather` _and `+prefer-no-gather` features at the 
same time?


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[PATCH] D111790: [AArch64][Driver][SVE] Allow -msve-vector-bits=+ syntax to mean no maximum vscale

2021-10-15 Thread Matt D. via Phabricator via cfe-commits 
Matt added inline comments.



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:1832
+  else {
+assert(!Val.getAsInteger(10, Bits));
+CmdArgs.push_back(

There may be a way to avoid side-effects in assertions (`getAsInteger` changing 
the value of `Bits` passed by reference) similarly to the `NewToSet` example in 
https://llvm.org/docs/CodingStandards.html#assert-liberally, similarly to 
https://github.com/llvm/llvm-project/blob/release/13.x/llvm/include/llvm/TableGen/Record.h#L1980-L1983
 or 
https://github.com/llvm/llvm-project/blob/release/13.x/clang/lib/StaticAnalyzer/Core/AnalyzerOptions.cpp#L181-L185.


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