r372307 - [TestCommit] Trivial change to test commit access.

2019-09-19 Thread Mark Murray via cfe-commits 
Author: markrvmurray
Date: Thu Sep 19 02:24:42 2019
New Revision: 372307

URL: http://llvm.org/viewvc/llvm-project?rev=372307&view=rev
Log:
[TestCommit] Trivial change to test commit access.

Modified:
cfe/trunk/bindings/python/README.txt

Modified: cfe/trunk/bindings/python/README.txt
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/bindings/python/README.txt?rev=372307&r1=372306&r2=372307&view=diff
==
--- cfe/trunk/bindings/python/README.txt (original)
+++ cfe/trunk/bindings/python/README.txt Thu Sep 19 02:24:42 2019
@@ -1,5 +1,5 @@
 
//===--===//
-// Clang Python Bindings.
+// Clang Python Bindings
 
//===--===//
 
 This directory implements Python bindings for Clang.


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r372306 - [TestCommit] Trivial change to test commit access.

2019-09-19 Thread Mark Murray via cfe-commits 
Author: markrvmurray
Date: Thu Sep 19 02:02:12 2019
New Revision: 372306

URL: http://llvm.org/viewvc/llvm-project?rev=372306&view=rev
Log:
[TestCommit] Trivial change to test commit access.

Modified:
cfe/trunk/bindings/python/README.txt

Modified: cfe/trunk/bindings/python/README.txt
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/bindings/python/README.txt?rev=372306&r1=372305&r2=372306&view=diff
==
--- cfe/trunk/bindings/python/README.txt (original)
+++ cfe/trunk/bindings/python/README.txt Thu Sep 19 02:02:12 2019
@@ -1,5 +1,5 @@
 
//===--===//
-// Clang Python Bindings
+// Clang Python Bindings.
 
//===--===//
 
 This directory implements Python bindings for Clang.


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[clang] da9d57d - [ARM][MVE][Intrinsics] Add VMINAQ, VMINNMAQ, VMAXAQ, VMAXNMAQ intrinsics.

2020-01-15 Thread Mark Murray via cfe-commits 

Author: Mark Murray
Date: 2020-01-15T17:20:15Z
New Revision: da9d57d2c2dc821979490a425142afde5107066c

URL: 
https://github.com/llvm/llvm-project/commit/da9d57d2c2dc821979490a425142afde5107066c
DIFF: 
https://github.com/llvm/llvm-project/commit/da9d57d2c2dc821979490a425142afde5107066c.diff

LOG: [ARM][MVE][Intrinsics] Add VMINAQ, VMINNMAQ, VMAXAQ, VMAXNMAQ intrinsics.

Summary: Add VMINAQ, VMINNMAQ, VMAXAQ, VMAXNMAQ intrinsics and unit tests.

Reviewers: simon_tatham, miyuki, dmgreen

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D72761

Added: 
clang/test/CodeGen/arm-mve-intrinsics/vmaxaq.c
clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c
clang/test/CodeGen/arm-mve-intrinsics/vminaq.c
clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c
llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxaq.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxnmaq.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/vminaq.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/vminnmaq.ll

Modified: 
clang/include/clang/Basic/arm_mve.td
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMInstrMVE.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_mve.td 
b/clang/include/clang/Basic/arm_mve.td
index 0e023b85459c..a348713b2aa3 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -192,6 +192,10 @@ let params = T.Int in {
 let params = T.Signed in {
   defm vqdmulhq : VectorVectorArithmetic<"qdmulh_predicated", (?), 0>;
   defm vqrdmulhq : VectorVectorArithmetic<"qrdmulh_predicated", (?), 0>;
+  def vminaq_m: Intrinsic $a, $b, $pred)>;
+  def vmaxaq_m: Intrinsic $a, $b, $pred)>;
 }
 
 let params = T.Poly, overrideKindLetter = "p" in {
@@ -203,6 +207,10 @@ let params = T.Poly, overrideKindLetter = "p" in {
 let params = T.Float in {
   defm vminnmq : VectorVectorArithmetic<"min_predicated", (? (u32 0))>;
   defm vmaxnmq : VectorVectorArithmetic<"max_predicated", (? (u32 0))>;
+  def vminnmaq_m: Intrinsic $a, $b, $pred)>;
+  def vmaxnmaq_m: Intrinsic $a, $b, $pred)>;
 }
 
 let params = T.Int in {
@@ -275,6 +283,14 @@ let params = T.Signed in {
(select (icmp_sle $a, $b), $a, $b)>;
   def vmaxq: Intrinsic;
+  def vminaq: Intrinsic;
+  def vmaxaq: Intrinsic;
 }
 let params = T.Unsigned in {
   def vminqu: Intrinsic $a, $b)>;
+ (IRIntBase<"minnum", [Vector]> $a, $b)>;
   def vmaxnmq: Intrinsic $a, $b)>;
+ (IRIntBase<"maxnum", [Vector]> $a, $b)>;
+  def vminnmaq: Intrinsic
+   $a, (IRIntBase<"fabs", [Vector]> $b))>;
+  def vmaxnmaq: Intrinsic
+   $a, (IRIntBase<"fabs", [Vector]> $b))>;
 }
 
 def vpselq: Intrinsic
+
+// CHECK-LABEL: @test_vmaxaq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = icmp slt <16 x i8> [[B:%.*]], zeroinitializer
+// CHECK-NEXT:[[TMP1:%.*]] = sub <16 x i8> zeroinitializer, [[B]]
+// CHECK-NEXT:[[TMP2:%.*]] = select <16 x i1> [[TMP0]], <16 x i8> 
[[TMP1]], <16 x i8> [[B]]
+// CHECK-NEXT:[[TMP3:%.*]] = icmp ugt <16 x i8> [[TMP2]], [[A:%.*]]
+// CHECK-NEXT:[[TMP4:%.*]] = select <16 x i1> [[TMP3]], <16 x i8> 
[[TMP2]], <16 x i8> [[A]]
+// CHECK-NEXT:ret <16 x i8> [[TMP4]]
+//
+uint8x16_t test_vmaxaq_s8(uint8x16_t a, int8x16_t b)
+{
+#ifdef POLYMORPHIC
+return vmaxaq(a, b);
+#else /* POLYMORPHIC */
+return vmaxaq_s8(a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmaxaq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = icmp slt <8 x i16> [[B:%.*]], zeroinitializer
+// CHECK-NEXT:[[TMP1:%.*]] = sub <8 x i16> zeroinitializer, [[B]]
+// CHECK-NEXT:[[TMP2:%.*]] = select <8 x i1> [[TMP0]], <8 x i16> [[TMP1]], 
<8 x i16> [[B]]
+// CHECK-NEXT:[[TMP3:%.*]] = icmp ugt <8 x i16> [[TMP2]], [[A:%.*]]
+// CHECK-NEXT:[[TMP4:%.*]] = select <8 x i1> [[TMP3]], <8 x i16> [[TMP2]], 
<8 x i16> [[A]]
+// CHECK-NEXT:ret <8 x i16> [[TMP4]]
+//
+uint16x8_t test_vmaxaq_s16(uint16x8_t a, int16x8_t b)
+{
+#ifdef POLYMORPHIC
+return vmaxaq(a, b);
+#else /* POLYMORPHIC */
+return vmaxaq_s16(a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmaxaq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = icmp slt <4 x i32> [[B:%.*]], zeroinitializer
+// CHECK-NEXT:[[TMP1:%.*]] = sub <4 x i32> zeroinitializer, [[B]]
+// CHECK-NEXT:[[TMP2:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[TMP1]], 
<4 x i32> [[B]]
+// CHECK-NEXT:[[TMP3:%.*]] = icmp ugt <4 x i32> [[TMP2]], [[A:%.*]]
+// CHECK-NEXT:[[TMP4:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[TMP2]], 
<4 x i32> [[A]]
+// CHECK-NEXT:ret <4 x i32> [[TMP4]]
+//
+uint32x4_t test_vmaxaq_s32(uint32x4_t a, int32x4_t b)
+{
+#ifdef POLYMORPHIC
+return vmaxaq(a, b);
+#else /* PO

[clang] 2b66918 - [ARM][AArch64] Adding Neoverse N2 CPU support

2020-11-25 Thread Mark Murray via cfe-commits 

Author: Mark Murray
Date: 2020-11-25T11:42:54Z
New Revision: 2b6691894ab671706051a6d7ef54571546c20d3b

URL: 
https://github.com/llvm/llvm-project/commit/2b6691894ab671706051a6d7ef54571546c20d3b
DIFF: 
https://github.com/llvm/llvm-project/commit/2b6691894ab671706051a6d7ef54571546c20d3b.diff

LOG: [ARM][AArch64] Adding Neoverse N2 CPU support

Add support for the Neoverse N2 CPU to the ARM and AArch64 backends.

Differential Revision: https://reviews.llvm.org/D91695

Added: 


Modified: 
clang/test/Driver/aarch64-cpus.c
clang/test/Driver/arm-cortex-cpus.c
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/ARMTargetParser.def
llvm/lib/Support/Host.cpp
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMSubtarget.cpp
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/test/CodeGen/AArch64/cpus.ll
llvm/test/CodeGen/AArch64/neon-dot-product.ll
llvm/test/CodeGen/AArch64/remat.ll
llvm/test/MC/AArch64/armv8.2a-dotprod.s
llvm/test/MC/AArch64/armv8.3a-rcpc.s
llvm/test/MC/AArch64/armv8.5a-ssbs.s
llvm/test/MC/ARM/armv8.2a-dotprod-a32.s
llvm/test/MC/ARM/armv8.2a-dotprod-t32.s
llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
llvm/unittests/Support/TargetParserTest.cpp

Removed: 




diff  --git a/clang/test/Driver/aarch64-cpus.c 
b/clang/test/Driver/aarch64-cpus.c
index 139746823660..131a57940b4c 100644
--- a/clang/test/Driver/aarch64-cpus.c
+++ b/clang/test/Driver/aarch64-cpus.c
@@ -752,6 +752,9 @@
 // RUN: %clang -target aarch64 -march=armv8-a+ras -### -c %s 2>&1 | FileCheck 
-check-prefix=V8ARAS -check-prefix=GENERIC %s
 // V8ARAS: "-target-feature" "+ras"
 
+// RUN: %clang -target aarch64 -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-N2 %s
+// NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n2"
+
 // == Check whether -march accepts mixed-case values.
 // RUN: %clang -target aarch64_be -march=ARMV8.1A -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A-BE %s
 // RUN: %clang -target aarch64_be -march=ARMV8.1-A -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A-BE %s

diff  --git a/clang/test/Driver/arm-cortex-cpus.c 
b/clang/test/Driver/arm-cortex-cpus.c
index 5df872358a7a..a312ccfda5a1 100644
--- a/clang/test/Driver/arm-cortex-cpus.c
+++ b/clang/test/Driver/arm-cortex-cpus.c
@@ -879,6 +879,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m55 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M55 %s
 // CHECK-CORTEX-M55:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m55"
 
+// RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
+// CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
+
 // == Check whether -mcpu accepts mixed-case values.
 // RUN: %clang -target arm-linux-gnueabi -mcpu=Cortex-a5 -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s
 // RUN: %clang -target arm-linux-gnueabi -mcpu=cortex-A7 -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s

diff  --git a/llvm/include/llvm/Support/AArch64TargetParser.def 
b/llvm/include/llvm/Support/AArch64TargetParser.def
index cbf0d5d079dd..7625f5a6f6ab 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -150,6 +150,11 @@ AARCH64_CPU_NAME("neoverse-n1", ARMV8_2A, 
FK_CRYPTO_NEON_FP_ARMV8, false,
  (AArch64::AEK_DOTPROD | AArch64::AEK_FP16 |
   AArch64::AEK_PROFILE | AArch64::AEK_RAS | AArch64::AEK_RCPC |
   AArch64::AEK_SSBS))
+AARCH64_CPU_NAME("neoverse-n2", ARMV8_5A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (AArch64::AEK_BF16 | AArch64::AEK_DOTPROD | AArch64::AEK_FP16 
|
+  AArch64::AEK_I8MM | AArch64::AEK_MTE | AArch64::AEK_RAS |
+  AArch64::AEK_RCPC | AArch64::AEK_SB | AArch64::AEK_SSBS |
+  AArch64::AEK_SVE | AArch64::AEK_SVE2 | 
AArch64::AEK_SVE2BITPERM))
 AARCH64_CPU_NAME("neoverse-v1", ARMV8_4A, FK_CRYPTO_NEON_FP_ARMV8, false,
  (AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
   AArch64::AEK_RCPC | AArch64::AEK_FP16 | AArch64::AEK_BF16 |

diff  --git a/llvm/include/llvm/Support/ARMTargetParser.def 
b/llvm/include/llvm/Support/ARMTargetParser.def
index 35c94fd5bce0..75ab539762db 100644
--- a/llvm/include/llvm/Support/ARMTargetParser.def
+++ b/llvm/include/llvm/Support/ARMTargetParser.def
@@ -300,6 +300,9 @@ ARM_CPU_NAME("cortex-x1", ARMV8_2A, 
FK_CRYPTO_NEON_FP_ARMV8, false,
  (ARM::AEK_FP16 | ARM::AEK_DOTPROD))
 ARM_CPU_NAME("neoverse-n1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,

[clang] f4bba07 - [ARM][MVE][Intrinsics] Add MVE VABD intrinsics. Add unit tests.

2019-11-27 Thread Mark Murray via cfe-commits 

Author: Mark Murray
Date: 2019-11-27T16:52:04Z
New Revision: f4bba07b87ce7ad60d908d2fe02abe88d2d48fa4

URL: 
https://github.com/llvm/llvm-project/commit/f4bba07b87ce7ad60d908d2fe02abe88d2d48fa4
DIFF: 
https://github.com/llvm/llvm-project/commit/f4bba07b87ce7ad60d908d2fe02abe88d2d48fa4.diff

LOG: [ARM][MVE][Intrinsics] Add MVE VABD intrinsics. Add unit tests.

Summary: Add MVE VABD intrinsics. Add unit tests.

Reviewers: simon_tatham, ostannard, dmgreen

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D70545

Added: 
clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
llvm/test/CodeGen/Thumb2/mve-intrinsics/vabdq.ll

Modified: 
clang/include/clang/Basic/arm_mve.td
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMInstrMVE.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_mve.td 
b/clang/include/clang/Basic/arm_mve.td
index d8d199f464d9..0d827485ae40 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -28,6 +28,7 @@ foreach n = [ 2, 4 ] in {
   "Intrinsic::arm_mve_vld"#n#"q":$IRIntr)>;
 }
 
+
 let params = T.Int in {
 def vaddq: Intrinsic;
 def vsubq: Intrinsic;
@@ -41,6 +42,14 @@ def vsubqf: Intrinsic,
 }
 
 let params = T.Usual in {
+def vabdq: Intrinsic $a, $b)>;
+}
+
+let params = T.Usual in {
+def vabdq_m: Intrinsic<
+Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
+(IRInt<"abd_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
 def vaddq_m: Intrinsic<
 Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
 (IRInt<"add_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;

diff  --git a/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c 
b/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
new file mode 100644
index ..a416bfb773e6
--- /dev/null
+++ b/clang/test/CodeGen/arm-mve-intrinsics/vabdq.c
@@ -0,0 +1,95 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature 
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 
-disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature 
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 
-disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | 
FileCheck %s
+
+#include 
+
+// CHECK-LABEL: @test_vabdq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x 
i8> [[A:%.*]], <16 x i8> [[B:%.*]])
+// CHECK-NEXT:ret <16 x i8> [[TMP0]]
+//
+int8x16_t test_vabdq_s8(int8x16_t a, int8x16_t b)
+{
+#ifdef POLYMORPHIC
+return vabdq(a, b);
+#else /* POLYMORPHIC */
+return vabdq_s8(a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vabdq_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x 
i32> [[A:%.*]], <4 x i32> [[B:%.*]])
+// CHECK-NEXT:ret <4 x i32> [[TMP0]]
+//
+uint32x4_t test_vabdq_u32(uint32x4_t a, uint32x4_t b)
+{
+#ifdef POLYMORPHIC
+return vabdq(a, b);
+#else /* POLYMORPHIC */
+return vabdq_u32(a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vabdq_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x 
half> [[A:%.*]], <8 x half> [[B:%.*]])
+// CHECK-NEXT:ret <8 x half> [[TMP0]]
+//
+float16x8_t test_vabdq_f32(float16x8_t a, float16x8_t b)
+{
+#ifdef POLYMORPHIC
+return vabdq(a, b);
+#else /* POLYMORPHIC */
+return vabdq_f16(a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vabdq_m_u16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:[[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 
[[TMP0]])
+// CHECK-NEXT:[[TMP2:%.*]] = call <8 x i16> 
@llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> 
[[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
+// CHECK-NEXT:ret <8 x i16> [[TMP2]]
+//
+uint16x8_t test_vabdq_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, 
mve_pred16_t p)
+{
+#ifdef POLYMORPHIC
+return vabdq_m(inactive, a, b, p);
+#else /* POLYMORPHIC */
+return vabdq_m_u16(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vabdq_m_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:[[TMP1:%.*]] = call <16 x i1> 
@llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
+// CHECK-NEXT:[[TMP2:%.*]] = call <16 x i8> 
@llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> 
[[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]])
+// CHECK-NEXT:ret <16 x i8> [[TMP

[clang] 510792a - [ARM][MVE][Intrinsics] Add VMINQ/VMAXQ/VMINNMQ/VMAXNMQ intrinsics.

2019-12-02 Thread Mark Murray via cfe-commits 

Author: Mark Murray
Date: 2019-12-02T11:18:53Z
New Revision: 510792a2e0e3792871baa00ed34e162bba7cd9a2

URL: 
https://github.com/llvm/llvm-project/commit/510792a2e0e3792871baa00ed34e162bba7cd9a2
DIFF: 
https://github.com/llvm/llvm-project/commit/510792a2e0e3792871baa00ed34e162bba7cd9a2.diff

LOG: [ARM][MVE][Intrinsics] Add VMINQ/VMAXQ/VMINNMQ/VMAXNMQ intrinsics.

Summary: Add VMINQ/VMAXQ/VMINNMQ/VMAXNMQ intrinsics and their predicated 
versions. Add unit tests.

Subscribers: kristof.beyls, hiraditya, dmgreen, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D70829

Added: 
clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c
clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c
clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c
clang/test/CodeGen/arm-mve-intrinsics/vminq.c
llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxnmq.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxq.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/vminnmq.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/vminq.ll

Modified: 
clang/include/clang/Basic/arm_mve.td
clang/include/clang/Basic/arm_mve_defs.td
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMInstrMVE.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_mve.td 
b/clang/include/clang/Basic/arm_mve.td
index dfd8097f0644..90cccb12472c 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -105,6 +105,26 @@ defm vornq_m: predicated_bit_op_fp<"orn_predicated">;
 defm vorrq_m: predicated_bit_op_fp<"orr_predicated">;
 }
 
+// Predicated intrinsics - Int types only
+let params = T.Int in {
+def vminq_m: Intrinsic<
+Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
+(IRInt<"min_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
+def vmaxq_m: Intrinsic<
+Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
+(IRInt<"max_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
+}
+
+// Predicated intrinsics - Float types only
+let params = T.Float in {
+def vminnmq_m: Intrinsic<
+Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
+(IRInt<"min_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
+def vmaxnmq_m: Intrinsic<
+Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
+(IRInt<"max_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
+}
+
 let params = T.Int in {
 def vminvq: Intrinsic $prev, $vec))>;
@@ -173,6 +193,28 @@ let params = T.Float in {
   defm: compare<"le", fcmp_le>;
 }
 
+let params = T.Signed in {
+  def vminq: Intrinsic;
+  def vmaxq: Intrinsic;
+}
+let params = T.Unsigned in {
+  def vminqu: Intrinsic,
+  NameOverride<"vminq">;
+  def vmaxqu: Intrinsic,
+  NameOverride<"vmaxq">;
+}
+let params = T.Float in {
+  def vminnmq: Intrinsic $a, $b)>;
+  def vmaxnmq: Intrinsic $a, $b)>;
+}
+
+
 multiclass contiguous_load same_size, list wider> {
   // Intrinsics named with explicit memory and element sizes that match:

diff  --git a/clang/include/clang/Basic/arm_mve_defs.td 
b/clang/include/clang/Basic/arm_mve_defs.td
index c0ed80d456a5..d837a1d33d00 100644
--- a/clang/include/clang/Basic/arm_mve_defs.td
+++ b/clang/include/clang/Basic/arm_mve_defs.td
@@ -107,6 +107,7 @@ def fcmp_ge: IRBuilder<"CreateFCmpOGE">;
 def fcmp_lt: IRBuilder<"CreateFCmpOLT">;
 def fcmp_le: IRBuilder<"CreateFCmpOLE">;
 def splat: CGHelperFn<"ARMMVEVectorSplat">;
+def select: IRBuilder<"CreateSelect">;
 
 // A node that makes an Address out of a pointer-typed Value, by
 // providing an alignment as the second argument.

diff  --git a/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c 
b/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c
new file mode 100644
index ..63300466c819
--- /dev/null
+++ b/clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c
@@ -0,0 +1,65 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature 
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 
-disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature 
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 
-disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | 
FileCheck %s
+
+#include 
+
+// CHECK-LABEL: @test_vmaxnmq_f16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call <8 x half> @llvm.maxnum.v8f16(<8 x 
half> [[A:%.*]], <8 x half> [[B:%.*]])
+// CHECK-NEXT:ret <8 x half> [[TMP0]]
+//
+float16x8_t test_vmaxnmq_f16(float16x8_t a, float16x8_t b)
+{
+#ifdef POLYMORPHIC
+return vmaxnmq(a, b);
+#else /* POLYMORPHIC */
+return vmaxnmq_f16(a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL:

[clang] d3f62ce - [ARM][MVE][Intrinsics] Add VMULH/VRMULH intrinsics.

2019-12-04 Thread Mark Murray via cfe-commits 

Author: Mark Murray
Date: 2019-12-04T14:27:12Z
New Revision: d3f62ceac0ce5d35f888c5a2de9c4a41780c8040

URL: 
https://github.com/llvm/llvm-project/commit/d3f62ceac0ce5d35f888c5a2de9c4a41780c8040
DIFF: 
https://github.com/llvm/llvm-project/commit/d3f62ceac0ce5d35f888c5a2de9c4a41780c8040.diff

LOG: [ARM][MVE][Intrinsics] Add VMULH/VRMULH intrinsics.

Summary: Add MVE VMULH/VRMULH intrinsics and unit tests.

Reviewers: simon_tatham, ostannard, dmgreen

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D70948

Added: 
clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c
llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulhq.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/vrmulhq.ll

Modified: 
clang/include/clang/Basic/arm_mve.td
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMInstrMVE.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_mve.td 
b/clang/include/clang/Basic/arm_mve.td
index ed925a200726..5fa9fc008202 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -47,6 +47,10 @@ def vornq: Intrinsic;
 def vorrq: Intrinsic;
 def vsubq: Intrinsic;
 def vmulq: Intrinsic;
+def vmulhq: Intrinsic $a, $b)>;
+def vrmulhq: Intrinsic $a, $b)>;
 }
 
 let params = T.Float in {
@@ -113,6 +117,12 @@ def vminq_m: Intrinsic<
 def vmaxq_m: Intrinsic<
 Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
 (IRInt<"max_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
+def vmulhq_m: Intrinsic<
+Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
+(IRInt<"mulh_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
+def vrmulhq_m: Intrinsic<
+Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
+(IRInt<"rmulh_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
 }
 
 // Predicated intrinsics - Float types only

diff  --git a/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c 
b/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
new file mode 100644
index ..63696d698c50
--- /dev/null
+++ b/clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c
@@ -0,0 +1,95 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature 
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 
-disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature 
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 
-disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | 
FileCheck %s
+
+#include 
+
+// CHECK-LABEL: @test_vmulhq_u8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 
x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
+// CHECK-NEXT:ret <16 x i8> [[TMP0]]
+//
+uint8x16_t test_vmulhq_u8(uint8x16_t a, uint8x16_t b)
+{
+#ifdef POLYMORPHIC
+return vmulhq(a, b);
+#else /* POLYMORPHIC */
+return vmulhq_u8(a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmulhq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x 
i16> [[A:%.*]], <8 x i16> [[B:%.*]])
+// CHECK-NEXT:ret <8 x i16> [[TMP0]]
+//
+int16x8_t test_vmulhq_s16(int16x8_t a, int16x8_t b)
+{
+#ifdef POLYMORPHIC
+return vmulhq(a, b);
+#else /* POLYMORPHIC */
+return vmulhq_s16(a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmulhq_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x 
i32> [[A:%.*]], <4 x i32> [[B:%.*]])
+// CHECK-NEXT:ret <4 x i32> [[TMP0]]
+//
+uint32x4_t test_vmulhq_u32(uint32x4_t a, uint32x4_t b)
+{
+#ifdef POLYMORPHIC
+return vmulhq(a, b);
+#else /* POLYMORPHIC */
+return vmulhq_u32(a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmulhq_m_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:[[TMP1:%.*]] = call <16 x i1> 
@llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
+// CHECK-NEXT:[[TMP2:%.*]] = call <16 x i8> 
@llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> 
[[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]])
+// CHECK-NEXT:ret <16 x i8> [[TMP2]]
+//
+int8x16_t test_vmulhq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, 
mve_pred16_t p)
+{
+#ifdef POLYMORPHIC
+return vmulhq_m(inactive, a, b, p);
+#else /* POLYMORPHIC */
+return vmulhq_m_s8(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vmulhq_m_u16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:[[TMP1:%.*]] = ca

[clang] 2eb61fa - [ARM][MVE][Intrinsics] Add VMULL[BT]Q_(INT|POLY) intrinsics.

2019-12-09 Thread Mark Murray via cfe-commits 

Author: Mark Murray
Date: 2019-12-09T17:41:47Z
New Revision: 2eb61fa5d68567435c4d0f1dcc0620bd9956edca

URL: 
https://github.com/llvm/llvm-project/commit/2eb61fa5d68567435c4d0f1dcc0620bd9956edca
DIFF: 
https://github.com/llvm/llvm-project/commit/2eb61fa5d68567435c4d0f1dcc0620bd9956edca.diff

LOG: [ARM][MVE][Intrinsics] Add VMULL[BT]Q_(INT|POLY) intrinsics.

Summary: Add VMULL[BT]Q_(INT|POLY) intrinsics and unit tests.

Reviewers: simon_tatham, ostannard, dmgreen

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D71066

Added: 
clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
llvm/test/CodeGen/Thumb2/mve-intrinsics/vmullbq.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll

Modified: 
clang/include/clang/Basic/arm_mve.td
clang/include/clang/Basic/arm_mve_defs.td
clang/utils/TableGen/MveEmitter.cpp
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMInstrMVE.td
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/arm_mve.td 
b/clang/include/clang/Basic/arm_mve.td
index cc4b6d9e8234..33e38ce059fc 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -51,6 +51,21 @@ def vmulhq: Intrinsic $a, $b)>;
 def vrmulhq: Intrinsic $a, $b)>;
+def vmullbq_int: Intrinsic
+   $a, $b, 0)>;
+def vmulltq_int: Intrinsic
+   $a, $b, 1)>;
+}
+
+let params = T.Poly, overrideKindLetter = "p" in {
+def vmullbq_poly: Intrinsic
+$a, $b, 0)>;
+def vmulltq_poly: Intrinsic
+$a, $b, 1)>;
 }
 
 let params = T.Float in {
@@ -123,6 +138,25 @@ def vmulhq_m: Intrinsic<
 def vrmulhq_m: Intrinsic<
 Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
 (IRInt<"rmulh_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
+def vmullbq_int_m: Intrinsic<
+DblVector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
+(IRInt<"mull_int_predicated", [DblVector, Vector, Predicate]> $a, $b, 0,
+ $pred, $inactive)>;
+def vmulltq_int_m: Intrinsic<
+DblVector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
+(IRInt<"mull_int_predicated", [DblVector, Vector, Predicate]> $a, $b, 1,
+ $pred, $inactive)>;
+}
+
+let params = T.Poly, overrideKindLetter = "p" in {
+def vmullbq_poly_m: Intrinsic<
+DblVector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
+(IRInt<"mull_poly_predicated", [DblVector, Vector, Predicate]> $a, $b, 0,
+ $pred, $inactive)>;
+def vmulltq_poly_m: Intrinsic<
+DblVector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
+(IRInt<"mull_poly_predicated", [DblVector, Vector, Predicate]> $a, $b, 1,
+ $pred, $inactive)>;
 }
 
 // Predicated intrinsics - Float types only

diff  --git a/clang/include/clang/Basic/arm_mve_defs.td 
b/clang/include/clang/Basic/arm_mve_defs.td
index 5aa10f250eda..6bc9b35f0fc4 100644
--- a/clang/include/clang/Basic/arm_mve_defs.td
+++ b/clang/include/clang/Basic/arm_mve_defs.td
@@ -190,6 +190,7 @@ def CTO_Pred: ComplexTypeOp;
 class CTO_Tuple: ComplexTypeOp { int n = n_; }
 class CTO_Pointer: ComplexTypeOp { bit const = const_; }
 def CTO_CopyKind: ComplexTypeOp;
+def CTO_DoubleSize: ComplexTypeOp;
 
 // 
-
 // Instances of Type intended to be used directly in the specification of an
@@ -264,6 +265,11 @@ class CPtr: ComplexType<(CTO_Pointer<1> t)>;
 // matches that of s.
 class CopyKind: ComplexType<(CTO_CopyKind s, k)>;
 
+// DoubleSize expects k to be a scalar type. It returns a scalar type
+// whose kind (signed, unsigned or float) matches that of k, and whose size
+// is double that of k, if possible.
+class DoubleSize: ComplexType<(CTO_DoubleSize k)>;
+
 // Unsigned expects t to be a scalar type, and expands to the unsigned
 // integer scalar of the same size. So it returns u16 if you give it s16 or
 // f16 (or u16 itself).
@@ -274,6 +280,10 @@ class Unsigned: ComplexType<(CTO_CopyKind t, u32)>;
 def UScalar: Unsigned;
 def UVector: VecOf;
 
+// DblVector expands to a vector of scalars of size twice the size of
+// Scalar.
+def DblVector: VecOf>;
+
 // 
-
 // Internal definitions for specifying immediate arguments for an intrinsic.
 
@@ -405,6 +415,10 @@ class Intrinsic {
 
   // True if the builtin has to avoid evaluating its arguments.
   bit nonEvaluating = 0;
+
+  // Use to override the suffix letter to make e.g.vfooq_p16
+  // with an override suffix letter of "p".
+  string overrideKindLetter = "";
 }
 
 // Sometimes you ha

[clang] 0eb0992 - [ARM][MVE][Intrinsics] remove extraneous intrinsics.

2019-12-13 Thread Mark Murray via cfe-commits 

Author: Mark Murray
Date: 2019-12-13T15:51:31Z
New Revision: 0eb0992739189dba0d86af33722bc27260a9b555

URL: 
https://github.com/llvm/llvm-project/commit/0eb0992739189dba0d86af33722bc27260a9b555
DIFF: 
https://github.com/llvm/llvm-project/commit/0eb0992739189dba0d86af33722bc27260a9b555.diff

LOG: [ARM][MVE][Intrinsics] remove extraneous intrinsics.

Summary:
I overstepped my reach and generated too many intrinsics; these never
made it into the tests.

Remove these extras. Some needed to be signed-olny, and there were some
possible but unrequired _x variants that needed an extra argument to
IntrinsicMX to allow [de-]selection at compile-time.

Reviewers: simon_tatham

Subscribers: kristof.beyls, dmgreen, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D71466

Added: 


Modified: 
clang/include/clang/Basic/arm_mve.td
clang/include/clang/Basic/arm_mve_defs.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_mve.td 
b/clang/include/clang/Basic/arm_mve.td
index 6a27bdb807a9..15ed4ce83f01 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -79,10 +79,6 @@ def vmulhq: Intrinsic $a, $b)>;
 def vrmulhq: Intrinsic $a, $b)>;
-def vqdmulhq: Intrinsic $a, $b)>;
-def vqrdmulhq: Intrinsic $a, $b)>;
 def vmullbq_int: Intrinsic
$a, $b, 0)>;
@@ -90,6 +86,12 @@ def vmulltq_int: Intrinsic
$a, $b, 1)>;
 }
+let params = T.Signed in {
+def vqdmulhq: Intrinsic $a, $b)>;
+def vqrdmulhq: Intrinsic $a, $b)>;
+}
 
 let params = T.Poly, overrideKindLetter = "p" in {
 def vmullbq_poly: Intrinsic $a, $b)>;
 }
 
-multiclass VectorVectorArithmetic {
+multiclass VectorVectorArithmetic {
   defm "" : IntrinsicMX $a, $b,
- $pred, $inactive)>;
+ $pred, $inactive),
+wantXVariant>;
 }
 
 multiclass VectorVectorArithmeticBitcast {
@@ -179,16 +182,18 @@ let params = T.Int in {
   defm vmaxq : VectorVectorArithmetic<"max_predicated">;
   defm vmulhq : VectorVectorArithmetic<"mulh_predicated">;
   defm vrmulhq : VectorVectorArithmetic<"rmulh_predicated">;
-  defm vqdmulhq : VectorVectorArithmetic<"qdmulh_predicated">;
-  defm vqrdmulhq : VectorVectorArithmetic<"qrdmulh_predicated">;
-  defm vqaddq : VectorVectorArithmetic<"qadd_predicated">;
+  defm vqaddq : VectorVectorArithmetic<"qadd_predicated", 0>;
   defm vhaddq : VectorVectorArithmetic<"hadd_predicated">;
   defm vrhaddq : VectorVectorArithmetic<"rhadd_predicated">;
-  defm vqsubq : VectorVectorArithmetic<"qsub_predicated">;
+  defm vqsubq : VectorVectorArithmetic<"qsub_predicated", 0>;
   defm vhsubq : VectorVectorArithmetic<"hsub_predicated">;
   defm vmullbq_int : DblVectorVectorArithmetic<"mull_int_predicated", (u32 0)>;
   defm vmulltq_int : DblVectorVectorArithmetic<"mull_int_predicated", (u32 1)>;
 }
+let params = T.Signed in {
+  defm vqdmulhq : VectorVectorArithmetic<"qdmulh_predicated", 0>;
+  defm vqrdmulhq : VectorVectorArithmetic<"qrdmulh_predicated", 0>;
+}
 
 let params = T.Poly, overrideKindLetter = "p" in {
   defm vmullbq_poly : DblVectorVectorArithmetic<"mull_poly_predicated", (u32 
0)>;
@@ -594,7 +599,7 @@ let params = T.Int in {
   defm vshlq: IntrinsicMX
-   $v, $sh, $pred, $inactive), "_n">;
+   $v, $sh, $pred, $inactive), 1, "_n">;
 
   let pnt = PNT_NType in {
 def vshrq_n: Intrinsic
- $v, $sh, (unsignedflag Scalar), $pred, $inactive), "_n">;
+ $v, $sh, (unsignedflag Scalar), $pred, $inactive), 1, "_n">;
   }
 }
 

diff  --git a/clang/include/clang/Basic/arm_mve_defs.td 
b/clang/include/clang/Basic/arm_mve_defs.td
index 03472fb47b6c..939d5eb0cd6b 100644
--- a/clang/include/clang/Basic/arm_mve_defs.td
+++ b/clang/include/clang/Basic/arm_mve_defs.td
@@ -440,6 +440,7 @@ class NameOverride {
 // A wrapper to define both _m and _x versions of a predicated
 // intrinsic.
 multiclass IntrinsicMX {
   // The _m variant takes an initial parameter called $inactive, which
@@ -449,15 +450,17 @@ multiclass IntrinsicMX;
 
-  // The _x variant leaves off that parameter, and simply uses an
-  // undef value of the same type.
-  def "_x" # nameSuffix:
- Intrinsic {
-// Allow overriding of the polymorphic name type, because
-// sometimes the _m and _x variants polymorph 
diff erently
-// (typically because the type of the inactive parameter can be
-// used as a disambiguator if it's present).
-let pnt = pnt_x;
+  foreach unusedVar = !if(!eq(wantXVariant, 1), [1], []) in {
+// The _x variant leaves off that parameter, and simply uses an
+// undef value of the same type.
+def "_x" # nameSuffix:
+   Intrinsic {
+  // Allow overriding of the polymorphic name type, because
+  // sometimes the _m and _x variants polymorph 
diff erently
+  // (typical

Re: [PATCH] D71466: [ARM][MVE][Intrinsics] remove extraneous intrinsics.

2019-12-13 Thread Mark Murray via cfe-commits 
Hi

Sorry about the breakage; a commit crossed my build/check/push run, and I was 
testing a fix when your revert came.

M

On 13/12/2019, 16:24, "Dmitri Gribenko via Phabricator" 
 wrote:

gribozavr2 added a comment.

I reverted this change in 34536db7bbe0b8c5f8ffa70df307312b451aca2e 
. This 
change didn't compile: 
http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/20462. Please 
always run `ninja check-all` before pushing.


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[clang] a2cd460 - [ARM][MVE][Intrinsics] All vqdmulhq/vqrdmulhq tests should be for signed numbers.

2019-12-13 Thread Mark Murray via cfe-commits 

Author: Mark Murray
Date: 2019-12-13T17:29:59Z
New Revision: a2cd4600ec6710f3218f071128e2a81edd23a2b2

URL: 
https://github.com/llvm/llvm-project/commit/a2cd4600ec6710f3218f071128e2a81edd23a2b2
DIFF: 
https://github.com/llvm/llvm-project/commit/a2cd4600ec6710f3218f071128e2a81edd23a2b2.diff

LOG: [ARM][MVE][Intrinsics] All vqdmulhq/vqrdmulhq tests should be for signed 
numbers.

Fix broken tests. I can't yet explain how they worked locally pre-commit.

Added: 


Modified: 
clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
llvm/test/CodeGen/Thumb2/mve-intrinsics/vqdmulhq.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/vqrdmulhq.ll

Removed: 




diff  --git a/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c 
b/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
index 05e890e40078..eb7e0a0afdf3 100644
--- a/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
+++ b/clang/test/CodeGen/arm-mve-intrinsics/vqdmulhq.c
@@ -4,17 +4,17 @@
 
 #include 
 
-// CHECK-LABEL: @test_vqdmulhq_u8(
+// CHECK-LABEL: @test_vqdmulhq_s8(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = call <16 x i8> 
@llvm.arm.mve.vqdmulh.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
 // CHECK-NEXT:ret <16 x i8> [[TMP0]]
 //
-uint8x16_t test_vqdmulhq_u8(uint8x16_t a, uint8x16_t b)
+int8x16_t test_vqdmulhq_s8(int8x16_t a, int8x16_t b)
 {
 #ifdef POLYMORPHIC
 return vqdmulhq(a, b);
 #else /* POLYMORPHIC */
-return vqdmulhq_u8(a, b);
+return vqdmulhq_s8(a, b);
 #endif /* POLYMORPHIC */
 }
 
@@ -32,17 +32,17 @@ int16x8_t test_vqdmulhq_s16(int16x8_t a, int16x8_t b)
 #endif /* POLYMORPHIC */
 }
 
-// CHECK-LABEL: @test_vqdmulhq_u32(
+// CHECK-LABEL: @test_vqdmulhq_s32(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vqdmulh.v4i32(<4 
x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
 // CHECK-NEXT:ret <4 x i32> [[TMP0]]
 //
-uint32x4_t test_vqdmulhq_u32(uint32x4_t a, uint32x4_t b)
+int32x4_t test_vqdmulhq_s32(int32x4_t a, int32x4_t b)
 {
 #ifdef POLYMORPHIC
 return vqdmulhq(a, b);
 #else /* POLYMORPHIC */
-return vqdmulhq_u32(a, b);
+return vqdmulhq_s32(a, b);
 #endif /* POLYMORPHIC */
 }
 
@@ -62,19 +62,19 @@ int8x16_t test_vqdmulhq_m_s8(int8x16_t inactive, int8x16_t 
a, int8x16_t b, mve_p
 #endif /* POLYMORPHIC */
 }
 
-// CHECK-LABEL: @test_vqdmulhq_m_u16(
+// CHECK-LABEL: @test_vqdmulhq_m_s16(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 // CHECK-NEXT:[[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 
[[TMP0]])
 // CHECK-NEXT:[[TMP2:%.*]] = call <8 x i16> 
@llvm.arm.mve.qdmulh.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> 
[[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
 // CHECK-NEXT:ret <8 x i16> [[TMP2]]
 //
-uint16x8_t test_vqdmulhq_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t 
b, mve_pred16_t p)
+int16x8_t test_vqdmulhq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, 
mve_pred16_t p)
 {
 #ifdef POLYMORPHIC
 return vqdmulhq_m(inactive, a, b, p);
 #else /* POLYMORPHIC */
-return vqdmulhq_m_u16(inactive, a, b, p);
+return vqdmulhq_m_s16(inactive, a, b, p);
 #endif /* POLYMORPHIC */
 }
 

diff  --git a/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c 
b/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
index 4916faead32c..27b7efd31014 100644
--- a/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
+++ b/clang/test/CodeGen/arm-mve-intrinsics/vqrdmulhq.c
@@ -4,17 +4,17 @@
 
 #include 
 
-// CHECK-LABEL: @test_vqrdmulhq_u8(
+// CHECK-LABEL: @test_vqrdmulhq_s8(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = call <16 x i8> 
@llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
 // CHECK-NEXT:ret <16 x i8> [[TMP0]]
 //
-uint8x16_t test_vqrdmulhq_u8(uint8x16_t a, uint8x16_t b)
+int8x16_t test_vqrdmulhq_s8(int8x16_t a, int8x16_t b)
 {
 #ifdef POLYMORPHIC
 return vqrdmulhq(a, b);
 #else /* POLYMORPHIC */
-return vqrdmulhq_u8(a, b);
+return vqrdmulhq_s8(a, b);
 #endif /* POLYMORPHIC */
 }
 
@@ -32,17 +32,17 @@ int16x8_t test_vqrdmulhq_s16(int16x8_t a, int16x8_t b)
 #endif /* POLYMORPHIC */
 }
 
-// CHECK-LABEL: @test_vqrdmulhq_u32(
+// CHECK-LABEL: @test_vqrdmulhq_s32(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = call <4 x i32> 
@llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
 // CHECK-NEXT:ret <4 x i32> [[TMP0]]
 //
-uint32x4_t test_vqrdmulhq_u32(uint32x4_t a, uint32x4_t b)
+int32x4_t test_vqrdmulhq_s32(int32x4_t a, int32x4_t b)
 {
 #ifdef POLYMORPHIC
 return vqrdmulhq(a, b);
 #else /* POLYMORPHIC */
-return vqrdmulhq_u32(a, b);
+return vqrdmulhq_s32(a, b);
 #endif /* POLYMORPHIC */
 }
 
@@ -62,19 +62,19 @@ int8x16_t test_vqrdmulhq_m_s8(int8x16_t inactive, int8x16_t 
a, int8x16_t b, mve_
 #endif /* POLYMORPHIC */
 }
 
-// CHECK-LABEL: @test_vqrdmulhq_m

Re: [PATCH] D71466: [ARM][MVE][Intrinsics] remove extraneous intrinsics.

2019-12-13 Thread Mark Murray via cfe-commits 
Hi

I've committed a fix.

M

On 13/12/2019, 17:38, "Nico Weber via Phabricator"  
wrote:

thakis added a comment.

This breaks tests: http://45.33.8.238/mac/4132/step_7.txt

Please take a look and revert if it takes a while to fix.


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[clang] b10a0eb - [ARM][MVE][Intrinsics] Take abs() of VMINNMAQ, VMAXNMAQ intrinsics' first arguments.

2020-01-20 Thread Mark Murray via cfe-commits 

Author: Mark Murray
Date: 2020-01-20T14:33:26Z
New Revision: b10a0eb04adfc4186cc6198cf8231358b2b04d89

URL: 
https://github.com/llvm/llvm-project/commit/b10a0eb04adfc4186cc6198cf8231358b2b04d89
DIFF: 
https://github.com/llvm/llvm-project/commit/b10a0eb04adfc4186cc6198cf8231358b2b04d89.diff

LOG: [ARM][MVE][Intrinsics] Take abs() of VMINNMAQ, VMAXNMAQ intrinsics' first 
arguments.

Summary: Fix VMINNMAQ, VMAXNMAQ intrinsics; BOTH arguments have the absolute 
values taken.

Reviewers: dmgreen, simon_tatham

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D72830

Added: 


Modified: 
clang/include/clang/Basic/arm_mve.td
clang/test/CodeGen/arm-mve-intrinsics/vmaxnmaq.c
clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c
llvm/lib/Target/ARM/ARMInstrMVE.td
llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxnmaq.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/vminnmaq.ll

Removed: 




diff  --git a/clang/include/clang/Basic/arm_mve.td 
b/clang/include/clang/Basic/arm_mve.td
index a348713b2aa3..d28f97390614 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -307,10 +307,12 @@ let params = T.Float in {
  (IRIntBase<"maxnum", [Vector]> $a, $b)>;
   def vminnmaq: Intrinsic
-   $a, (IRIntBase<"fabs", [Vector]> $b))>;
+   (IRIntBase<"fabs", [Vector]> $a),
+   (IRIntBase<"fabs", [Vector]> $b))>;
   def vmaxnmaq: Intrinsic
-   $a, (IRIntBase<"fabs", [Vector]> $b))>;
+   (IRIntBase<"fabs", [Vector]> $a),
+   (IRIntBase<"fabs", [Vector]> $b))>;
 }
 
 def vpselq: Intrinsic @llvm.fabs.v8f16(<8 x 
half> [[B:%.*]])
-// CHECK-NEXT:[[TMP1:%.*]] = tail call <8 x half> @llvm.maxnum.v8f16(<8 x 
half> [[A:%.*]], <8 x half> [[TMP0]])
-// CHECK-NEXT:ret <8 x half> [[TMP1]]
+// CHECK-NEXT:[[TMP0:%.*]] = tail call <8 x half> @llvm.fabs.v8f16(<8 x 
half> [[A:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call <8 x half> @llvm.fabs.v8f16(<8 x 
half> [[B:%.*]])
+// CHECK-NEXT:[[TMP2:%.*]] = tail call <8 x half> @llvm.maxnum.v8f16(<8 x 
half> [[TMP0]], <8 x half> [[TMP1]])
+// CHECK-NEXT:ret <8 x half> [[TMP2]]
 //
 float16x8_t test_vmaxnmaq_f16(float16x8_t a, float16x8_t b)
 {
@@ -21,9 +22,10 @@ float16x8_t test_vmaxnmaq_f16(float16x8_t a, float16x8_t b)
 
 // CHECK-LABEL: @test_vmaxnmaq_f32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call <4 x float> @llvm.fabs.v4f32(<4 x 
float> [[B:%.*]])
-// CHECK-NEXT:[[TMP1:%.*]] = tail call <4 x float> @llvm.maxnum.v4f32(<4 x 
float> [[A:%.*]], <4 x float> [[TMP0]])
-// CHECK-NEXT:ret <4 x float> [[TMP1]]
+// CHECK-NEXT:[[TMP0:%.*]] = tail call <4 x float> @llvm.fabs.v4f32(<4 x 
float> [[A:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call <4 x float> @llvm.fabs.v4f32(<4 x 
float> [[B:%.*]])
+// CHECK-NEXT:[[TMP2:%.*]] = tail call <4 x float> @llvm.maxnum.v4f32(<4 x 
float> [[TMP0]], <4 x float> [[TMP1]])
+// CHECK-NEXT:ret <4 x float> [[TMP2]]
 //
 float32x4_t test_vmaxnmaq_f32(float32x4_t a, float32x4_t b)
 {

diff  --git a/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c 
b/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c
index e16ede06f691..955e8feab52a 100644
--- a/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c
+++ b/clang/test/CodeGen/arm-mve-intrinsics/vminnmaq.c
@@ -6,9 +6,10 @@
 
 // CHECK-LABEL: @test_vminnmaq_f16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call <8 x half> @llvm.fabs.v8f16(<8 x 
half> [[B:%.*]])
-// CHECK-NEXT:[[TMP1:%.*]] = tail call <8 x half> @llvm.minnum.v8f16(<8 x 
half> [[A:%.*]], <8 x half> [[TMP0]])
-// CHECK-NEXT:ret <8 x half> [[TMP1]]
+// CHECK-NEXT:[[TMP0:%.*]] = tail call <8 x half> @llvm.fabs.v8f16(<8 x 
half> [[A:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call <8 x half> @llvm.fabs.v8f16(<8 x 
half> [[B:%.*]])
+// CHECK-NEXT:[[TMP2:%.*]] = tail call <8 x half> @llvm.minnum.v8f16(<8 x 
half> [[TMP0]], <8 x half> [[TMP1]])
+// CHECK-NEXT:ret <8 x half> [[TMP2]]
 //
 float16x8_t test_vminnmaq_f16(float16x8_t a, float16x8_t b)
 {
@@ -21,9 +22,10 @@ float16x8_t test_vminnmaq_f16(float16x8_t a, float16x8_t b)
 
 // CHECK-LABEL: @test_vminnmaq_f32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call <4 x float> @llvm.fabs.v4f32(<4 x 
float> [[B:%.*]])
-// CHECK-NEXT:[[TMP1:%.*]] = tail call <4 x float> @llvm.minnum.v4f32(<4 x 
float> [[A:%.*]], <4 x float> [[TMP0]])
-// CHECK-NEXT:ret <4 x float> [[TMP1]]
+// CHECK-NEXT:[[TMP0:%.*]] = tail call <4 x float> @llvm.fabs.v4f32(<4 x 
float> [[A:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call <4 x float> @llvm.fabs.v4f32(<4 x 
float> [[B:%.*]

[clang] 5abfecc - [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM

2020-12-29 Thread Mark Murray via cfe-commits 

Author: Mark Murray
Date: 2020-12-29T10:18:59Z
New Revision: 5abfeccf10bcbc0d673ece21ddd8d4ac4a0e7594

URL: 
https://github.com/llvm/llvm-project/commit/5abfeccf10bcbc0d673ece21ddd8d4ac4a0e7594
DIFF: 
https://github.com/llvm/llvm-project/commit/5abfeccf10bcbc0d673ece21ddd8d4ac4a0e7594.diff

LOG: [ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM

This patch upstreams support for the Armv8-a Cortex-A78C
processor for AArch64 and ARM.

In detail:

Adding cortex-a78c as cpu option for aarch64 and arm targets in clang
Adding Cortex-A78C CPU name and ProcessorModel in llvm
Details of the CPU can be found here:
https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78c

Added: 


Modified: 
clang/test/Driver/aarch64-cpus.c
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/ARMTargetParser.def
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMSubtarget.cpp
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/unittests/Support/TargetParserTest.cpp

Removed: 




diff  --git a/clang/test/Driver/aarch64-cpus.c 
b/clang/test/Driver/aarch64-cpus.c
index 283660b321b3..7ac2473915e8 100644
--- a/clang/test/Driver/aarch64-cpus.c
+++ b/clang/test/Driver/aarch64-cpus.c
@@ -183,6 +183,8 @@
 // CORTEXX1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x1"
 // RUN: %clang -target aarch64 -mcpu=cortex-a78  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXA78 %s
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
+// RUN: %clang -target aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
+// CORTEX-A78C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a78c"
 // RUN: %clang -target aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
 // NEOVERSE-V1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-v1"
 
@@ -475,6 +477,12 @@
 // MCPU-MTUNE-THUNDERX2T99: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-cpu" "thunderx2t99"
 // MCPU-MTUNE-THUNDERX3T110: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" 
"-target-cpu" "thunderx3t110"
 
+// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a78c -### -c %s 2>&1 
| FileCheck -check-prefix=CHECK-CORTEX-A78C %s
+// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a78c 
-mfpu=crypto-neon-fp-armv8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-A78C-MFPU %s
+// CHECK-CORTEX-A78C: "-cc1"{{.*}} "-triple" "armv8.2a-{{.*}} "-target-cpu" 
"cortex-a78c"
+// CHECK-CORTEX-A78C-MFPU: "-cc1"{{.*}} "-target-feature" "+fp-armv8"
+// CHECK-CORTEX-A78C-MFPU: "-target-feature" "+crypto"
+
 // RUN: %clang -target aarch64 -march=armv8.1a -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A %s
 // RUN: %clang -target aarch64 -march=armv8.1-a -### -c %s 2>&1 | FileCheck 
-check-prefix=GENERICV81A %s
 // RUN: %clang -target aarch64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1 
| FileCheck -check-prefix=GENERICV81A %s

diff  --git a/llvm/include/llvm/Support/AArch64TargetParser.def 
b/llvm/include/llvm/Support/AArch64TargetParser.def
index 97172730e364..f1a5bf734a13 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -147,6 +147,9 @@ AARCH64_CPU_NAME("cortex-a77", ARMV8_2A, 
FK_CRYPTO_NEON_FP_ARMV8, false,
 AARCH64_CPU_NAME("cortex-a78", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
  (AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC 
|
   AArch64::AEK_SSBS))
+AARCH64_CPU_NAME("cortex-a78c", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC 
|
+  AArch64::AEK_SSBS))
 AARCH64_CPU_NAME("cortex-r82", ARMV8R, FK_CRYPTO_NEON_FP_ARMV8, false,
  (AArch64::AEK_LSE))
 AARCH64_CPU_NAME("cortex-x1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,

diff  --git a/llvm/include/llvm/Support/ARMTargetParser.def 
b/llvm/include/llvm/Support/ARMTargetParser.def
index 76341a051dbf..37cf0a93bb04 100644
--- a/llvm/include/llvm/Support/ARMTargetParser.def
+++ b/llvm/include/llvm/Support/ARMTargetParser.def
@@ -300,8 +300,10 @@ ARM_CPU_NAME("cortex-a76ae", ARMV8_2A, 
FK_CRYPTO_NEON_FP_ARMV8, false,
 (ARM::AEK_FP16 | ARM::AEK_DOTPROD))
 ARM_CPU_NAME("cortex-a77", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
 (ARM::AEK_FP16 | ARM::AEK_DOTPROD))
-ARM_CPU_NAME("cortex-a78",ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ARM_CPU_NAME("cortex-a78", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
  (ARM::AEK_FP16 | ARM::AEK_DOTPROD))
+ARM_CPU_NAME("cortex-a78c", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ ARM::AEK_FP16 | ARM::AEK_DOTPROD)
 ARM_CPU_NAME("cortex-x1", ARMV8_2A, FK_CRYPTO_NE

[clang] af7cce2 - [AArch64] Add +pauth archictecture option, allowing the v8.3a pointer authentication extension.

2021-01-08 Thread Mark Murray via cfe-commits 

Author: Mark Murray
Date: 2021-01-08T13:21:11Z
New Revision: af7cce2fa4d19c3cd09607e1d6ea2e0847cc55b7

URL: 
https://github.com/llvm/llvm-project/commit/af7cce2fa4d19c3cd09607e1d6ea2e0847cc55b7
DIFF: 
https://github.com/llvm/llvm-project/commit/af7cce2fa4d19c3cd09607e1d6ea2e0847cc55b7.diff

LOG: [AArch64] Add +pauth archictecture option, allowing the v8.3a pointer 
authentication extension.

Differential Revision: https://reviews.llvm.org/D94083

Added: 


Modified: 
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/unittests/Support/TargetParserTest.cpp

Removed: 




diff  --git a/clang/lib/Basic/Targets/AArch64.cpp 
b/clang/lib/Basic/Targets/AArch64.cpp
index c1abe8e9f75b..d03bca9cfd90 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -510,6 +510,8 @@ bool 
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
   HasMTE = true;
 if (Feature == "+tme")
   HasTME = true;
+if (Feature == "+pauth")
+  HasPAuth = true;
 if (Feature == "+i8mm")
   HasMatMul = true;
 if (Feature == "+bf16")

diff  --git a/clang/lib/Basic/Targets/AArch64.h 
b/clang/lib/Basic/Targets/AArch64.h
index bd576680077e..5f24ab6a4d61 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -36,6 +36,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public 
TargetInfo {
   bool HasFP16FML;
   bool HasMTE;
   bool HasTME;
+  bool HasPAuth;
   bool HasLS64;
   bool HasMatMul;
   bool HasSVE2;

diff  --git a/llvm/include/llvm/Support/AArch64TargetParser.def 
b/llvm/include/llvm/Support/AArch64TargetParser.def
index f1a5bf734a13..38cc2e753740 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -108,6 +108,7 @@ AARCH64_ARCH_EXT_NAME("f64mm",AArch64::AEK_F64MM,   
"+f64mm", "-f64m
 AARCH64_ARCH_EXT_NAME("tme",  AArch64::AEK_TME, "+tme",   
"-tme")
 AARCH64_ARCH_EXT_NAME("ls64", AArch64::AEK_LS64,"+ls64",  
"-ls64")
 AARCH64_ARCH_EXT_NAME("brbe", AArch64::AEK_BRBE,"+brbe",  
"-brbe")
+AARCH64_ARCH_EXT_NAME("pauth",AArch64::AEK_PAUTH,   "+pauth", 
"-pauth")
 #undef AARCH64_ARCH_EXT_NAME
 
 #ifndef AARCH64_CPU_NAME

diff  --git a/llvm/include/llvm/Support/AArch64TargetParser.h 
b/llvm/include/llvm/Support/AArch64TargetParser.h
index a3c9c6a30483..35827517d7fc 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.h
+++ b/llvm/include/llvm/Support/AArch64TargetParser.h
@@ -64,6 +64,7 @@ enum ArchExtKind : uint64_t {
   AEK_F64MM =   1ULL << 32,
   AEK_LS64 =1ULL << 33,
   AEK_BRBE =1ULL << 34,
+  AEK_PAUTH =   1ULL << 35,
 };
 
 enum class ArchKind {

diff  --git a/llvm/lib/Support/AArch64TargetParser.cpp 
b/llvm/lib/Support/AArch64TargetParser.cpp
index 62761177c8c2..be595e83dbef 100644
--- a/llvm/lib/Support/AArch64TargetParser.cpp
+++ b/llvm/lib/Support/AArch64TargetParser.cpp
@@ -102,6 +102,8 @@ bool AArch64::getExtensionFeatures(uint64_t Extensions,
 Features.push_back("+rcpc");
   if (Extensions & AEK_BRBE)
 Features.push_back("+brbe");
+  if (Extensions & AEK_PAUTH)
+Features.push_back("+pauth");
 
   return true;
 }

diff  --git a/llvm/lib/Target/AArch64/AArch64.td 
b/llvm/lib/Target/AArch64/AArch64.td
index 2be006bb647f..1f1bf0ac1657 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -261,8 +261,8 @@ def FeatureDotProd : SubtargetFeature<
 "dotprod", "HasDotProd", "true",
 "Enable dot product support">;
 
-def FeaturePA : SubtargetFeature<
-"pa", "HasPA", "true",
+def FeaturePAuth : SubtargetFeature<
+"pauth", "HasPAuth", "true",
 "Enable v8.3-A Pointer Authentication extension">;
 
 def FeatureJS : SubtargetFeature<
@@ -438,7 +438,7 @@ def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", 
"true",
   FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
 
 def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
-  "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA,
+  "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth,
   FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
 
 def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
@@ -471,7 +471,7 @@ def Has

[clang] 7d4a8bc - [AArch64] Add +flagm archictecture option, allowing the v8.4a flag modification extension.

2021-01-08 Thread Mark Murray via cfe-commits 

Author: Mark Murray
Date: 2021-01-08T13:21:12Z
New Revision: 7d4a8bc417bf75b5e4034674a4255173d0089e68

URL: 
https://github.com/llvm/llvm-project/commit/7d4a8bc417bf75b5e4034674a4255173d0089e68
DIFF: 
https://github.com/llvm/llvm-project/commit/7d4a8bc417bf75b5e4034674a4255173d0089e68.diff

LOG: [AArch64] Add +flagm archictecture option, allowing the v8.4a flag 
modification extension.

Differential Revision: https://reviews.llvm.org/D94081

Added: 


Modified: 
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/test/MC/AArch64/armv8.4a-flag.s
llvm/unittests/Support/TargetParserTest.cpp

Removed: 




diff  --git a/clang/lib/Basic/Targets/AArch64.cpp 
b/clang/lib/Basic/Targets/AArch64.cpp
index d03bca9cfd90..312c822ebb05 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -520,6 +520,8 @@ bool 
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
   HasLSE = true;
 if (Feature == "+ls64")
   HasLS64 = true;
+if (Feature == "+flagm")
+  HasFlagM = true;
   }
 
   setDataLayout();

diff  --git a/clang/lib/Basic/Targets/AArch64.h 
b/clang/lib/Basic/Targets/AArch64.h
index 5f24ab6a4d61..2809fbce9c88 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -47,6 +47,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public 
TargetInfo {
   bool HasMatmulFP64;
   bool HasMatmulFP32;
   bool HasLSE;
+  bool HasFlagM;
 
   llvm::AArch64::ArchKind ArchKind;
 

diff  --git a/llvm/include/llvm/Support/AArch64TargetParser.def 
b/llvm/include/llvm/Support/AArch64TargetParser.def
index 38cc2e753740..5f36b0eecff9 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -109,6 +109,7 @@ AARCH64_ARCH_EXT_NAME("tme",  AArch64::AEK_TME, 
"+tme",   "-tme"
 AARCH64_ARCH_EXT_NAME("ls64", AArch64::AEK_LS64,"+ls64",  
"-ls64")
 AARCH64_ARCH_EXT_NAME("brbe", AArch64::AEK_BRBE,"+brbe",  
"-brbe")
 AARCH64_ARCH_EXT_NAME("pauth",AArch64::AEK_PAUTH,   "+pauth", 
"-pauth")
+AARCH64_ARCH_EXT_NAME("flagm",AArch64::AEK_FLAGM,   "+flagm", 
"-flagm")
 #undef AARCH64_ARCH_EXT_NAME
 
 #ifndef AARCH64_CPU_NAME

diff  --git a/llvm/include/llvm/Support/AArch64TargetParser.h 
b/llvm/include/llvm/Support/AArch64TargetParser.h
index 35827517d7fc..7c9e245e3889 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.h
+++ b/llvm/include/llvm/Support/AArch64TargetParser.h
@@ -65,6 +65,7 @@ enum ArchExtKind : uint64_t {
   AEK_LS64 =1ULL << 33,
   AEK_BRBE =1ULL << 34,
   AEK_PAUTH =   1ULL << 35,
+  AEK_FLAGM =   1ULL << 36,
 };
 
 enum class ArchKind {

diff  --git a/llvm/lib/Support/AArch64TargetParser.cpp 
b/llvm/lib/Support/AArch64TargetParser.cpp
index be595e83dbef..503a7bd49d15 100644
--- a/llvm/lib/Support/AArch64TargetParser.cpp
+++ b/llvm/lib/Support/AArch64TargetParser.cpp
@@ -104,6 +104,8 @@ bool AArch64::getExtensionFeatures(uint64_t Extensions,
 Features.push_back("+brbe");
   if (Extensions & AEK_PAUTH)
 Features.push_back("+pauth");
+  if (Extensions & AEK_FLAGM)
+Features.push_back("+flagm");
 
   return true;
 }

diff  --git a/llvm/lib/Target/AArch64/AArch64.td 
b/llvm/lib/Target/AArch64/AArch64.td
index 1f1bf0ac1657..002efd700cc2 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -316,8 +316,8 @@ def FeatureTLB_RMI : SubtargetFeature<
 "tlb-rmi", "HasTLB_RMI", "true",
 "Enable v8.4-A TLB Range and Maintenance Instructions">;
 
-def FeatureFMI : SubtargetFeature<
-"fmi", "HasFMI", "true",
+def FeatureFlagM : SubtargetFeature<
+"flagm", "HasFlagM", "true",
 "Enable v8.4-A Flag Manipulation Instructions">;
 
 // 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
@@ -445,7 +445,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", 
"true",
   "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
   FeatureNV, FeatureMPAM, FeatureDIT,
   FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI,
-  FeatureFMI, FeatureRCPC_IMMO]>;
+  FeatureFlagM, FeatureRCPC_IMMO]>;
 
 def HasV8_5aOps : SubtargetFeature<
   "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
@@ -474,7 +474,7 @@ def HasV8_0rOps : SubtargetFeature<
   FeaturePAuth, FeatureRCPC,
   //v8.4
   FeatureDotProd, FeatureFP16FML, FeatureTRACEV8_4,
-  FeatureTLB_RMI, FeatureFMI, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO,
+  FeatureTLB_RMI, FeatureFlagM, FeatureDIT, Feature

[libcxx] [libcxxabi] [libunwind] [runtimes] Always define cxx_shared, cxx_static & other targets (PR #80007)

2024-10-11 Thread Mark Murray via cfe-commits 

MarkMurrayARM wrote:

Hi - is this being worked on? We are still seeing build failures that look like
```
-- ABI list file not generated for configuration 
aarch64-none-elf.libcxxabi.v2.unstable.exceptions.nonew, `check-cxx-abilist` 
will not be available.
-- Configuring done
-- Generating done
CMake Error:
  Running

   '/usr/bin/ninja' '-C' 
'/home/marmur02/oss/LLVM-embedded-toolchain-for-Arm/build/libcxx_libcxxabi_libunwind/aarch64a_exn_rtti/src/libcxx_libcxxabi_libunwind_aarch64a_exn_rtti-build'
 '-t' 'recompact'

  failed with:
   ninja: error: build.ninja:524: multiple rules generate lib/libunwind.a [-w 
dupbuild=err]
```
... which don't happen with this change locally backed out.

https://github.com/llvm/llvm-project/pull/80007
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[libcxx] [libcxxabi] [libunwind] [runtimes] Always define cxx_shared, cxx_static & other targets (PR #80007)

2024-10-11 Thread Mark Murray via cfe-commits 

MarkMurrayARM wrote:

NM - fixed in our builds.


https://github.com/llvm/llvm-project/pull/80007
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