[PATCH] D50144: Add Windows support for the GNUstep Objective-C ABI V2.

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added inline comments.



Comment at: lib/CodeGen/CGObjCGNU.cpp:3542
+  allSelectors.push_back(entry.first);
+std::sort(allSelectors.begin(), allSelectors.end());
 

Please use llvm::sort instead of std::sort. See 
https://llvm.org/docs/CodingStandards.html#beware-of-non-deterministic-sorting-order-of-equal-elements.


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[PATCH] D50488: [Analyzer] Checker for non-determinism caused by sorting of pointer-like keys

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: NoQ, george.karpenkov, whisperity.
Herald added subscribers: mikhail.ramalho, a.sidorin, rnkovacs, szepet, 
xazax.hun, mgorny.

Repository:
  rC Clang

https://reviews.llvm.org/D50488

Files:
  include/clang/StaticAnalyzer/Checkers/Checkers.td
  lib/StaticAnalyzer/Checkers/CMakeLists.txt
  lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
  test/Analysis/ptr-sort.cpp

Index: test/Analysis/ptr-sort.cpp
===
--- /dev/null
+++ test/Analysis/ptr-sort.cpp
@@ -0,0 +1,19 @@
+// RUN: %clang_analyze_cc1 -analyzer-checker=alpha.nondeterminism.PointerSorting %s -analyzer-output=text -verify
+
+#include "Inputs/system-header-simulator-cxx.h"
+
+namespace std {
+  template
+  void sort(RandomAccessIterator first, RandomAccessIterator last);
+}
+
+void PointerSorting() {
+  int a = 1, b = 2;
+
+  std::vector V1 = {a, b};
+  std::sort(V1.begin(), V1.end()); // no-warning
+
+  std::vector V2 = {&a, &b};
+  std::sort(V2.begin(), V2.end()); // expected-warning {{Non-deterministic sorting of pointer-like keys}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Non-deterministic sorting of pointer-like keys}} [alpha.nondeterminism.PointerSorting]
+}
Index: lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
===
--- /dev/null
+++ lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
@@ -0,0 +1,123 @@
+//=== PointerSortingChecker.cpp - Pointer Sorting Checker ---*- C++ -*---=//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+//
+// This file defines PointerSortingChecker, a builtin checker that checks for
+// non-determinism caused by sorting of pointer-like keys.
+//
+//===--===//
+
+#include "ClangSACheckers.h"
+#include "clang/AST/StmtVisitor.h"
+#include "clang/StaticAnalyzer/Core/BugReporter/BugType.h"
+#include "clang/StaticAnalyzer/Core/Checker.h"
+#include "clang/StaticAnalyzer/Core/PathSensitive/AnalysisManager.h"
+
+#define DEBUG_TYPE "check-pointer-sort"
+
+using namespace clang;
+using namespace ento;
+
+namespace {
+
+// PointerSortingVisitor class.
+class PointerSortingVisitor : public StmtVisitor {
+  BugReporter &BR;
+  const CheckerBase *Checker;
+  AnalysisDeclContext* AC;
+
+private:
+  void reportPointerSortingDiagnostic(CallExpr *CE);
+
+public:
+  PointerSortingVisitor(BugReporter &br,
+const CheckerBase *checker,
+AnalysisDeclContext *ac)
+  : BR(br), Checker(checker), AC(ac) {}
+  void VisitStmt(Stmt *S) { VisitChildren(S); }
+  void VisitChildren(Stmt *S);
+  void VisitCallExpr(CallExpr *CE);
+};
+}
+
+void PointerSortingVisitor::VisitChildren(Stmt *S) {
+  for (Stmt *Child : S->children())
+if (Child)
+  Visit(Child);
+}
+
+void PointerSortingVisitor::reportPointerSortingDiagnostic(CallExpr *CE) {
+  SmallString<64> buf;
+  llvm::raw_svector_ostream os(buf);
+  os << "Non-deterministic sorting of pointer-like keys";
+  const char *BugType = "Pointer Sorting";
+
+  SmallVector ranges;
+  ranges.push_back(CE->getSourceRange());
+
+  PathDiagnosticLocation CELoc =
+PathDiagnosticLocation::createBegin(CE, BR.getSourceManager(), AC);
+  BR.EmitBasicReport(AC->getDecl(), Checker, BugType,
+ "Non-determinism", os.str(), CELoc, ranges);
+}
+
+// VisitCallExpr - This looks for calls to std::sort for containers with
+// pointer-like keys.
+void PointerSortingVisitor::VisitCallExpr(CallExpr *CE) {
+  // FIXME: Currently we only report std::sort which uses the default comparator
+  // to sort a container with pointer-like keys.
+  if (CE->getNumArgs() != 2)
+return;
+
+  const FunctionDecl *FD = CE->getDirectCallee();
+  if (!FD)
+return;
+
+  if (!AnalysisDeclContext::isInStdNamespace(FD))
+return;
+
+  IdentifierInfo *II = FD->getIdentifier();
+  if (!II)
+return;
+
+  if (!II->getName().equals("sort"))
+return;
+
+  const QualType IterTy = CE->getArg(0)->getType();
+  const RecordDecl *RD =
+IterTy->getUnqualifiedDesugaredType()->getAsCXXRecordDecl();
+
+  if (RD->field_empty())
+return;
+
+  const FieldDecl *I = *RD->field_begin();
+  if (!I->getType()->getPointeeType()->isPointerType())
+return;
+
+  reportPointerSortingDiagnostic(CE);
+}
+
+//===--===//
+// PointerSortingChecker
+//===--===//
+
+namespace {
+class PointerSortingChecker : public Checker {
+public:
+  void checkASTCodeBody(const Decl *D,
+AnalysisManager& mgr,
+BugReport

[PATCH] D50559: [gnu-objc] Make selector order deterministic.

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

Does the error show up if you build llvm with -DLLVM_REVERSE_ITERATION:ON?

  LLVM_REVERSE_ITERATION:BOOL
  If enabled, all supported unordered llvm containers would be iterated in 
reverse order. This is useful for uncovering non-determinism caused by 
iteration of unordered containers.


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[PATCH] D50488: [Analyzer] Checker for non-determinism caused by sorting of pointer-like keys

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

Thanks for all your review comments. I will try to address them soon.

Meanwhile, I have started an email thread on the general problem of writing 
checkers/sanitizers to detect non-deterministic behaviors. See 
http://lists.llvm.org/pipermail/llvm-dev/2018-August/125191.html.

The background for this is that I had already added support in LLVM to uncover 
2 types of non-deterministic behaviors: iteration of unordered containers and 
sorting of keys with same values. But that is only for LLVM code, not user 
code. I now wanted to write checkers so that we could detect non-deterministic 
behavior in user code. It would be great if the reviewers here could chip-in 
with comments/suggestions for this. Thanks!


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[PATCH] D50559: [gnu-objc] Make selector order deterministic.

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

In https://reviews.llvm.org/D50559#1195787, @bmwiedemann wrote:

>   got a build failure with this patch added onto 6.0.1


You may have to add:

  #include "llvm/ADT/STLExtras.h"


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[PATCH] D50488: [Analyzer] Checker for non-determinism caused by sorting of pointer-like keys

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 161152.
mgrang added a comment.

Changed patch to use AST Matchers.


https://reviews.llvm.org/D50488

Files:
  include/clang/StaticAnalyzer/Checkers/Checkers.td
  lib/StaticAnalyzer/Checkers/CMakeLists.txt
  lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
  test/Analysis/ptr-sort.cpp

Index: test/Analysis/ptr-sort.cpp
===
--- /dev/null
+++ test/Analysis/ptr-sort.cpp
@@ -0,0 +1,28 @@
+// RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.nondeterminism.PointerSorting %s -analyzer-output=text -verify
+
+#include "Inputs/system-header-simulator-cxx.h"
+namespace std {
+  template
+  void sort (RandomIt first, RandomIt last);
+
+  template
+  void sort (RandomIt first, RandomIt last, Compare comp);
+}
+using namespace std;
+
+void PointerSorting() {
+  int a = 1, b = 2;
+
+  std::vector V1 = {a, b};
+  std::sort(V1.begin(), V1.end()); // no-warning
+
+  std::vector V2 = {&a, &b};
+
+  std::sort(V2.begin(), V2.end(), true); // no-warning
+
+  std::sort(V2.begin(), V2.end()); // expected-warning {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+
+  sort(V2.begin(), V2.end()); // expected-warning {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+}
Index: lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
===
--- /dev/null
+++ lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
@@ -0,0 +1,93 @@
+//===-- PointerSortingChecker.cpp -===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+//
+// This file defines PointerSortingChecker which checks for non-determinism
+// caused due to sorting container with pointer-like elements.
+//
+//===--===//
+
+#include "ClangSACheckers.h"
+#include "clang/ASTMatchers/ASTMatchFinder.h"
+#include "clang/StaticAnalyzer/Core/BugReporter/BugReporter.h"
+#include "clang/StaticAnalyzer/Core/BugReporter/BugType.h"
+#include "clang/StaticAnalyzer/Core/Checker.h"
+#include "clang/StaticAnalyzer/Core/PathSensitive/AnalysisManager.h"
+
+using namespace clang;
+using namespace ento;
+using namespace ast_matchers;
+
+namespace {
+
+// ID of a node at which the diagnostic would be emitted.
+const char *WarnAtNode = "sort";
+
+class PointerSortingChecker : public Checker {
+public:
+  void checkASTCodeBody(const Decl *D,
+AnalysisManager &AM,
+BugReporter &BR) const;
+};
+
+static void emitDiagnostics(const BoundNodes &Match, const Decl *D,
+BugReporter &BR, AnalysisManager &AM,
+const PointerSortingChecker *Checker) {
+  auto *ADC = AM.getAnalysisDeclContext(D);
+
+  const auto *MarkedStmt = Match.getNodeAs(WarnAtNode);
+  assert(MarkedStmt);
+
+  auto Range = MarkedStmt->getSourceRange();
+  auto Location = PathDiagnosticLocation::createBegin(MarkedStmt,
+  BR.getSourceManager(),
+  ADC);
+  std::string Diagnostics;
+  llvm::raw_string_ostream OS(Diagnostics);
+  OS << "Sorting pointer-like keys can result in non-deterministic ordering";
+
+  BR.EmitBasicReport(ADC->getDecl(), Checker,
+ "Sorting of pointer-like keys", "Non-determinism",
+ OS.str(), Location, Range);
+}
+
+auto callsName(const char *FunctionName) -> decltype(callee(functionDecl())) {
+  return callee(functionDecl(hasName(FunctionName)));
+}
+
+auto matchSortWithPointers() -> decltype(decl()) {
+  auto PointsToPointerM = hasType(cxxRecordDecl(has(
+fieldDecl(hasType(
+  pointsTo(pointerType())
+))
+  )));
+
+  auto SortFuncM = stmt(callExpr(allOf(
+ callsName("std::sort"),
+ argumentCountIs(2),
+ hasArgument(0, PointsToPointerM)))
+   ).bind(WarnAtNode);
+
+  return decl(forEachDescendant(SortFuncM));
+}
+
+void PointerSortingChecker::checkASTCodeBody(const Decl *D,
+ AnalysisManager &AM,
+ BugReporter &BR) const {
+  auto MatcherM = matchSortW

[PATCH] D50488: [Analyzer] Checker for non-determinism caused by sorting of pointer-like keys

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

This was my first time using AST matchers so it took me a while to figure out 
how exactly to get this right. clang-query helped a lot. Backspace seems to be 
a problem with clang-query though.


https://reviews.llvm.org/D50488



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[PATCH] D50488: [Analyzer] Checker for non-determinism caused by sorting of pointer-like keys

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 161165.
mgrang edited the summary of this revision.
mgrang added a comment.

Added checks for more algorithms: stable_sort, is_sorted, partial_sort, 
partition, stable_partition, nth_element.


https://reviews.llvm.org/D50488

Files:
  include/clang/StaticAnalyzer/Checkers/Checkers.td
  lib/StaticAnalyzer/Checkers/CMakeLists.txt
  lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
  test/Analysis/ptr-sort.cpp

Index: test/Analysis/ptr-sort.cpp
===
--- /dev/null
+++ test/Analysis/ptr-sort.cpp
@@ -0,0 +1,57 @@
+// RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.nondeterminism.PointerSorting %s -analyzer-output=text -verify
+
+#include "Inputs/system-header-simulator-cxx.h"
+namespace std {
+  template
+  bool is_sorted(ForwardIt first, ForwardIt last);
+
+  template 
+  void nth_element(RandomIt first, RandomIt nth, RandomIt last);
+
+  template
+  void partial_sort(RandomIt first, RandomIt middle, RandomIt last);
+
+  template
+  void sort (RandomIt first, RandomIt last);
+
+  template
+  void stable_sort(RandomIt first, RandomIt last);
+
+  template
+  BidirIt partition(BidirIt first, BidirIt last, UnaryPredicate p);
+
+  template
+  BidirIt stable_partition(BidirIt first, BidirIt last, UnaryPredicate p);
+}
+
+bool f (int x) { return true; }
+bool g (int *x) { return true; }
+
+void PointerSorting() {
+  int a = 1, b = 2, c = 3;
+  std::vector V1 = {a, b};
+  std::vector V2 = {&a, &b};
+
+  std::is_sorted(V1.begin(), V1.end());// no-warning
+  std::nth_element(V1.begin(), V1.begin() + 1, V1.end());  // no-warning
+  std::partial_sort(V1.begin(), V1.begin() + 1, V1.end()); // no-warning
+  std::sort(V1.begin(), V1.end()); // no-warning
+  std::stable_sort(V1.begin(), V1.end());  // no-warning
+  std::partition(V1.begin(), V1.end(), f); // no-warning
+  std::stable_partition(V1.begin(), V1.end(), g);  // no-warning
+
+  std::is_sorted(V2.begin(), V2.end()); // expected-warning {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::nth_element(V2.begin(), V2.begin() + 1, V2.end()); // expected-warning {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::partial_sort(V2.begin(), V2.begin() + 1, V2.end()); // expected-warning {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::sort(V2.begin(), V2.end()); // expected-warning {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::stable_sort(V2.begin(), V2.end()); // expected-warning {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::partition(V2.begin(), V2.end(), f); // expected-warning {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::stable_partition(V2.begin(), V2.end(), g); // expected-warning {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like keys can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+}
Index: lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
===
--- /dev/null
+++ lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
@@ -0,0 +1,110 @@
+//===-- PointerSortingChecker.cpp -===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+//
+// This file defines PointerSortingChecker which checks for non-determinism
+// caused due to sorting containers with pointer-like elements.
+//
+//===--

[PATCH] D50488: [Analyzer] Checker for non-determinism caused by sorting of pointer-like keys

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

In https://reviews.llvm.org/D50488#1203876, @Szelethus wrote:

> I think testcases for non-class iterator objects would be valuable.


Thanks @Szelethus. Yes, as you correctly pointed out this would not match 
non-class iterator objects.

This is my first time with ASTMatchers and I am not sure how to get the 
value_type from hasType (I don't see a matcher for value_types in 
ASTMatchers.h). Would I end up using a visitor for that? If yes, then maybe the 
entire check for pointer types needs to be done via visitors? Sorry for the 
newbie questions :)


https://reviews.llvm.org/D50488



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[PATCH] D50488: [Analyzer] Checker for non-determinism caused by sorting of pointer-like keys

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added inline comments.



Comment at: lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp:72-76
+  auto IteratesPointerKeysM = hasType(cxxRecordDecl(has(
+fieldDecl(hasType(hasCanonicalType(
+  pointsTo(hasCanonicalType(pointerType()))
+)))
+  )));

Szelethus wrote:
> Szelethus wrote:
> > I'm not a matcher-expert, but here we go:
> > 
> > As I understand it, you're matching iterator objects that wrap a pointer to 
> > pointer. Would it match this case?:
> > 
> > ```
> > void fill(int **IntPointerArray);
> > 
> > int main() {
> >   int *IntPointerArray[20]; // or a simple int array
> >   fill(IntPointerArray);
> > 
> >   std::sort(IntPointerArray, IntPointerArray + 20);
> > }
> > ```
> > `int**` is an [[ 
> > https://en.cppreference.com/w/cpp/named_req/RandomAccessIterator | 
> > RandomAccessIterator ]], but is not a `CXXRecordDecl`. As I mentioned 
> > earlier, it might be worth taking a look at `hasType`, and attempt to 
> > acquire `value_type`, as it is required for STL algorithms (it could be in 
> > a base class as well). `value_type` is also predefined through 
> > `std::iterator_traits` for pointer iterators like `int**`.
> Also, this could lead to false positives, as iterators may store pointers to 
> pointers that don't compare memory addresses. And it could maybe cause false 
> negatives, if the `value_type` is a pointer type but the elements are stored 
> in wrappers.
> 
> As I understand it.
Yes, I will try to fine tune the heuristic in subsequent patches. I have noted 
the false-positives in the FIXME.


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[PATCH] D47196: [Time-report ](2): Recursive timers in Clang

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added inline comments.



Comment at: include/clang/Frontend/Utils.h:369
+  llvm::CreateInfoOutputFile();
+  std::sort(FrontendTimes.begin(), FrontendTimes.end(), SortName);
+  using FTPIterator = typename std::vector::iterator;

Please use llvm::sort instead of std::sort. See 
https://llvm.org/docs/CodingStandards.html#beware-of-non-deterministic-sorting-order-of-equal-elements.



Comment at: include/clang/Frontend/Utils.h:389
+  }
+  std::sort(FinalTimes.begin(), FinalTimes.end(), ftimeSort2);
+  double TimeThreshold =

Same here.


https://reviews.llvm.org/D47196



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[PATCH] D46822: [RISCV] Add driver for riscv32-unknown-elf baremetal target

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang accepted this revision.
mgrang added a comment.
This revision is now accepted and ready to land.

LGTM.




Comment at: lib/Driver/ToolChains/Gnu.cpp:1885
+ "riscv64-unknown-linux-gnu",
+ "riscv32-unknown-elf"};
 

Alphabetically riscv32-unknown-elf should be the first in the list of triples.


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https://reviews.llvm.org/D46822



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[PATCH] D47474: Implement cpu_dispatch/cpu_specific Multiversioning

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added inline comments.



Comment at: lib/Sema/SemaDecl.cpp:9440
+  // Sort order doesn't matter, it just needs to be consistent.
+  std::sort(NewParsed.Features.begin(), NewParsed.Features.end());
 

Please use llvm::sort instead of std::sort. See 
https://llvm.org/docs/CodingStandards.html#beware-of-non-deterministic-sorting-order-of-equal-elements.



Comment at: lib/Sema/SemaDecl.cpp:9526
+NewParsed = NewTA->parse();
+std::sort(NewParsed.Features.begin(), NewParsed.Features.end());
   }

Please use llvm::sort instead of std::sort. See 
https://llvm.org/docs/CodingStandards.html#beware-of-non-deterministic-sorting-order-of-equal-elements.


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[PATCH] D36111: [COFF, ARM64] Add MS builtins __dmb, __dsb, __isb

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

In https://reviews.llvm.org/D36111#894604, @mstorsjo wrote:

> @mgrang, did you ever get to completing this? I've got a need for this now 
> (only `__dmb` so far), and if you don't have time, I can try to finish it.


Sorry, I never got to complete this as I moved to other priorities. I do not 
think I have cycles to do this now. Please feel free to take over this patch :)


https://reviews.llvm.org/D36111



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[PATCH] D38821: [COFF, ARM64] Add MS builtins __dmb, __dsb, __isb

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

LGTM.


https://reviews.llvm.org/D38821



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[PATCH] D51204: [COFF, ARM64] Add MS intrinsics: __getReg, _ReadStatusReg, _WriteStatusReg

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, compnerd, mstorsjo, haripul, TomTan.
Herald added a reviewer: javed.absar.
Herald added subscribers: chrib, kristof.beyls.

Added declarations for the intrinsics in arm64intr.h. These are defined in MSVC 
libs and are needed for
certain spec2000 benchmarks.


Repository:
  rC Clang

https://reviews.llvm.org/D51204

Files:
  lib/Headers/arm64intr.h
  test/CodeGen/arm64-microsoft-intrinsics.c


Index: test/CodeGen/arm64-microsoft-intrinsics.c
===
--- test/CodeGen/arm64-microsoft-intrinsics.c
+++ test/CodeGen/arm64-microsoft-intrinsics.c
@@ -59,3 +59,19 @@
 
 // CHECK-MSVC: @llvm.aarch64.hint(i32 5)
 // CHECK-LINUX: error: implicit declaration of function '__sevl'
+
+unsigned __int64 check__getReg(void) {
+  return __getReg(1);
+}
+// CHECK-MSVC: call i32 bitcast (i32 (...)* @__getReg to i32 (i32)*)(i32 1)
+
+__int64 check_ReadStatusReg(void) {
+  return _ReadStatusReg(1);
+}
+// CHECK-MSVC: call i32 bitcast (i32 (...)* @_ReadStatusReg to i32 (i32)*)(i32 
1)
+
+void check_WriteStatusReg(void) {
+  __int64 x;
+  _WriteStatusReg(1, x);
+}
+// CHECK-MSVC: call i32 bitcast (i32 (...)* @_WriteStatusReg to i32 (i32, 
i64)*)(i32 1, i64 %0)
Index: lib/Headers/arm64intr.h
===
--- lib/Headers/arm64intr.h
+++ lib/Headers/arm64intr.h
@@ -45,5 +45,9 @@
   _ARM64_BARRIER_OSHLD = 0x1
 } _ARM64INTR_BARRIER_TYPE;
 
+unsigned __int64 __getReg(int);
+__int64 _ReadStatusReg(int);
+void _WriteStatusReg(int, __int64);
+
 #endif /* __ARM64INTR_H */
 #endif /* _MSC_VER */


Index: test/CodeGen/arm64-microsoft-intrinsics.c
===
--- test/CodeGen/arm64-microsoft-intrinsics.c
+++ test/CodeGen/arm64-microsoft-intrinsics.c
@@ -59,3 +59,19 @@
 
 // CHECK-MSVC: @llvm.aarch64.hint(i32 5)
 // CHECK-LINUX: error: implicit declaration of function '__sevl'
+
+unsigned __int64 check__getReg(void) {
+  return __getReg(1);
+}
+// CHECK-MSVC: call i32 bitcast (i32 (...)* @__getReg to i32 (i32)*)(i32 1)
+
+__int64 check_ReadStatusReg(void) {
+  return _ReadStatusReg(1);
+}
+// CHECK-MSVC: call i32 bitcast (i32 (...)* @_ReadStatusReg to i32 (i32)*)(i32 1)
+
+void check_WriteStatusReg(void) {
+  __int64 x;
+  _WriteStatusReg(1, x);
+}
+// CHECK-MSVC: call i32 bitcast (i32 (...)* @_WriteStatusReg to i32 (i32, i64)*)(i32 1, i64 %0)
Index: lib/Headers/arm64intr.h
===
--- lib/Headers/arm64intr.h
+++ lib/Headers/arm64intr.h
@@ -45,5 +45,9 @@
   _ARM64_BARRIER_OSHLD = 0x1
 } _ARM64INTR_BARRIER_TYPE;
 
+unsigned __int64 __getReg(int);
+__int64 _ReadStatusReg(int);
+void _WriteStatusReg(int, __int64);
+
 #endif /* __ARM64INTR_H */
 #endif /* _MSC_VER */
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[PATCH] D51204: [COFF, ARM64] Add MS intrinsics: __getReg, _ReadStatusReg, _WriteStatusReg

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 162431.
mgrang edited the summary of this revision.

https://reviews.llvm.org/D51204

Files:
  lib/Headers/intrin.h
  test/Headers/arm64-ms-intrin.cpp


Index: test/Headers/arm64-ms-intrin.cpp
===
--- /dev/null
+++ test/Headers/arm64-ms-intrin.cpp
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple arm64-windows -S -emit-llvm -o - %s \
+// RUN: -fms-compatibility -fms-compatibility-version=17.00 \
+// RUN: -isystem %S/Inputs/include 2>&1 | FileCheck %s
+
+#include 
+
+unsigned __int64 check__getReg() {
+  return __getReg(1);
+}
+// CHECK: call i64 @__getReg(i32 1)
+
+__int64 check_ReadStatusReg() {
+  return _ReadStatusReg(1);
+}
+// CHECK: call i64 @_ReadStatusReg(i32 1)
+
+void check_WriteStatusReg() {
+  __int64 x;
+  _WriteStatusReg(1, x);
+}
+// CHECK: call void @_WriteStatusReg(i32 1, i64 %0)
Index: lib/Headers/intrin.h
===
--- lib/Headers/intrin.h
+++ lib/Headers/intrin.h
@@ -865,6 +865,15 @@
 #endif
 
 
/**\
+|* MS AArch64 specific
+\**/
+#if defined(__aarch64__)
+unsigned __int64 __getReg(int);
+__int64 _ReadStatusReg(int);
+void _WriteStatusReg(int, __int64);
+#endif
+
+/**\
 |* Privileged intrinsics
 
\**/
 #if defined(__i386__) || defined(__x86_64__)


Index: test/Headers/arm64-ms-intrin.cpp
===
--- /dev/null
+++ test/Headers/arm64-ms-intrin.cpp
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple arm64-windows -S -emit-llvm -o - %s \
+// RUN: -fms-compatibility -fms-compatibility-version=17.00 \
+// RUN: -isystem %S/Inputs/include 2>&1 | FileCheck %s
+
+#include 
+
+unsigned __int64 check__getReg() {
+  return __getReg(1);
+}
+// CHECK: call i64 @__getReg(i32 1)
+
+__int64 check_ReadStatusReg() {
+  return _ReadStatusReg(1);
+}
+// CHECK: call i64 @_ReadStatusReg(i32 1)
+
+void check_WriteStatusReg() {
+  __int64 x;
+  _WriteStatusReg(1, x);
+}
+// CHECK: call void @_WriteStatusReg(i32 1, i64 %0)
Index: lib/Headers/intrin.h
===
--- lib/Headers/intrin.h
+++ lib/Headers/intrin.h
@@ -865,6 +865,15 @@
 #endif
 
 /**\
+|* MS AArch64 specific
+\**/
+#if defined(__aarch64__)
+unsigned __int64 __getReg(int);
+__int64 _ReadStatusReg(int);
+void _WriteStatusReg(int, __int64);
+#endif
+
+/**\
 |* Privileged intrinsics
 \**/
 #if defined(__i386__) || defined(__x86_64__)
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[PATCH] D51204: [COFF, ARM64] Add MS intrinsics: __getReg, _ReadStatusReg, _WriteStatusReg

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

Thanks @mstorsjo. I have addressed your comments.


https://reviews.llvm.org/D51204



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[PATCH] D50488: [Analyzer] Checker for non-determinism caused by sorting of pointer-like keys

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 163876.
mgrang added a comment.

Addressed comments.


https://reviews.llvm.org/D50488

Files:
  include/clang/StaticAnalyzer/Checkers/Checkers.td
  lib/StaticAnalyzer/Checkers/CMakeLists.txt
  lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
  test/Analysis/ptr-sort.cpp

Index: test/Analysis/ptr-sort.cpp
===
--- /dev/null
+++ test/Analysis/ptr-sort.cpp
@@ -0,0 +1,57 @@
+// RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.nondeterminism.PointerSorting %s -analyzer-output=text -verify
+
+#include "Inputs/system-header-simulator-cxx.h"
+namespace std {
+  template
+  bool is_sorted(ForwardIt first, ForwardIt last);
+
+  template 
+  void nth_element(RandomIt first, RandomIt nth, RandomIt last);
+
+  template
+  void partial_sort(RandomIt first, RandomIt middle, RandomIt last);
+
+  template
+  void sort (RandomIt first, RandomIt last);
+
+  template
+  void stable_sort(RandomIt first, RandomIt last);
+
+  template
+  BidirIt partition(BidirIt first, BidirIt last, UnaryPredicate p);
+
+  template
+  BidirIt stable_partition(BidirIt first, BidirIt last, UnaryPredicate p);
+}
+
+bool f (int x) { return true; }
+bool g (int *x) { return true; }
+
+void PointerSorting() {
+  int a = 1, b = 2, c = 3;
+  std::vector V1 = {a, b};
+  std::vector V2 = {&a, &b};
+
+  std::is_sorted(V1.begin(), V1.end());// no-warning
+  std::nth_element(V1.begin(), V1.begin() + 1, V1.end());  // no-warning
+  std::partial_sort(V1.begin(), V1.begin() + 1, V1.end()); // no-warning
+  std::sort(V1.begin(), V1.end()); // no-warning
+  std::stable_sort(V1.begin(), V1.end());  // no-warning
+  std::partition(V1.begin(), V1.end(), f); // no-warning
+  std::stable_partition(V1.begin(), V1.end(), g);  // no-warning
+
+  std::is_sorted(V2.begin(), V2.end()); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::nth_element(V2.begin(), V2.begin() + 1, V2.end()); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::partial_sort(V2.begin(), V2.begin() + 1, V2.end()); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::sort(V2.begin(), V2.end()); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::stable_sort(V2.begin(), V2.end()); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::partition(V2.begin(), V2.end(), f); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::stable_partition(V2.begin(), V2.end(), g); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+}
Index: lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
===
--- /dev/null
+++ lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
@@ -0,0 +1,110 @@
+//===-- PointerSortingChecker.cpp -===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+//
+// This file defines PointerSortingChecker which checks for non-determinism
+// caused due to sorting containers with pointer-like elements.
+//
+//===--===//
+
+#include "ClangSACheckers.h"
+#include "clang/ASTMatchers/ASTMatchFinder.h

[PATCH] D50488: [Analyzer] Checker for non-determinism caused by sorting of pointer-like elements

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

In https://reviews.llvm.org/D50488#1222837, @whisperity wrote:

>




> I'm not sure if we discussed, has this checker been tried on some in-the-wild 
> examples? To see if there are some real findings or crashes?
>  There is a good selection of projects here in this tool: 
> https://github.com/Xazax-hun/csa-testbench.

Thanks @whisperity for pointing me to the Static Analyzer tests. I will run the 
checker on it and report my findings here.


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[PATCH] D50488: [Analyzer] Checker for non-determinism caused by sorting of pointer-like elements

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

In https://reviews.llvm.org/D50488#1207398, @Szelethus wrote:

> In https://reviews.llvm.org/D50488#1204655, @mgrang wrote:
>
> > This is my first time with ASTMatchers and I am not sure how to get the 
> > value_type from hasType (I don't see a matcher for value_types in 
> > ASTMatchers.h). Would I end up using a visitor for that? If yes, then maybe 
> > the entire check for pointer types needs to be done via visitors? Sorry for 
> > the newbie questions :)
>
>
> I played around for a bit, my `clang-query` is a little out of date, but 
> here's what I found: You can match `typedef`s with `typedefDecl()`, and 
> `using` by `typeAliasDecl()`, and then add `hasName("value_type")` as a 
> parameter. As to how to check whether a type has any of these, I'm a little 
> unsure myself, but you could use `hasDescendant`, and narrow down the matches.
>
> I'm not sure whether this checks inherited type declarations, and it sure 
> doesn't check template specializations of `std::iterator_traits`, but it is a 
> good start :) I'll revisit this when I have a little more time on my hand.


I played around a lot with clang-query in the past week but I haven't been able 
to match typedefDecl with hasName("value_type"). Here are some matchers I tried:

  match callExpr(allOf (callee(functionDecl(hasName("std::sort"))), 
hasArgument(0,  
stmt(hasDescendant(expr(hasType(typedefType(hasDeclaration(typedefNameDecl(hasName("value_type")))
  
  match callExpr(allOf (callee(functionDecl(hasName("std::sort"))), 
hasArgument(0,
hasDescendant(expr(hasType(typedefType(hasDeclaration(typedefDecl(matchesName(".*value.*"))
  
  match callExpr(allOf (callee(functionDecl(hasName("std::sort"))), 
hasArgument(0,
hasDescendant(declRefExpr(to(fieldDecl(hasName("value_type"))

Here's the AST dump for the IntPointerArray example:

  FunctionDecl 0x639e958 <../../tst/s.cpp:5:1, line:10:1> line:5:5 main 'int ()'
  `-CompoundStmt 0x639f1d0 
|-DeclStmt 0x639ead0 
| `-VarDecl 0x639ea70  col:8 used IntPointerArray 'int *[20]'
|-CallExpr 0x639ebd0  'void'
| |-ImplicitCastExpr 0x639ebb8  'void (*)(int **)' 

| | `-DeclRefExpr 0x639eb68  'void (int **)' lvalue Function 
0x639e890 'fill' 'void (int **)'
| `-ImplicitCastExpr 0x639ec00  'int **' 
|   `-DeclRefExpr 0x639eb40  'int *[20]' lvalue Var 0x639ea70 
'IntPointerArray' 'int *[20]'
`-CallExpr 0x639f180  'void'
  |-ImplicitCastExpr 0x639f168  'void (*)(int **, int **)' 

  | `-DeclRefExpr 0x639f0d0  'void (int **, int **)' lvalue 
Function 0x639efd0 'sort' 'void (int **, int **)' (FunctionTemplate 0x638dd18 
'sort')
  |-ImplicitCastExpr 0x639f1b8  'int **' 
  | `-DeclRefExpr 0x639ec98  'int *[20]' lvalue Var 0x639ea70 
'IntPointerArray' 'int *[20]'
  `-BinaryOperator 0x639ed20  'int **' '+'
|-ImplicitCastExpr 0x639ed08  'int **' 
| `-DeclRefExpr 0x639ecc0  'int *[20]' lvalue Var 0x639ea70 
'IntPointerArray' 'int *[20]'
`-IntegerLiteral 0x639ece8  'int' 20


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[PATCH] D50488: [Analyzer] Checker for non-determinism caused by sorting of pointer-like elements

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

In https://reviews.llvm.org/D50488#1224480, @martong wrote:

> From this little information I have hear are my thoughts:
>
> > match callExpr(allOf (callee(functionDecl(hasName("std::sort"))), 
> > hasArgument(0,
> > hasDescendant(declRefExpr(to(fieldDecl(hasName("value_type"))
>
> I think this is a good direction, but keep in mind that `value_type` is a 
> typedef, thus you should use the `typedefNameDecl` matcher instead of the 
> `fieldDecl`.


Thanks @martong Yes, I tried another matcher with typedefNameDecl which also 
did not match:

  match callExpr(allOf (callee(functionDecl(hasName("std::sort"))), 
hasArgument(0, 
stmt(hasDescendant(expr(hasType(typedefType(hasDeclaration(typedefNameDecl(hasName("value_type")))



> (Also if I understand correctly then this is good that this matcher does not 
> match in case of the `intPointerArray` example, because the array does not 
> have any member at all ...)

How then do you think I should try matching the IntPointerArray example? I am 
now leaning towards not doing this via AST Matchers as I am not sure if I can 
easily match more complex cases.


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[PATCH] D50488: [Analyzer] Checker for non-determinism caused by sorting of pointer-like elements

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 164086.
mgrang added a comment.

Enabled checker only for C++.


https://reviews.llvm.org/D50488

Files:
  include/clang/StaticAnalyzer/Checkers/Checkers.td
  lib/StaticAnalyzer/Checkers/CMakeLists.txt
  lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
  test/Analysis/ptr-sort.cpp

Index: test/Analysis/ptr-sort.cpp
===
--- /dev/null
+++ test/Analysis/ptr-sort.cpp
@@ -0,0 +1,57 @@
+// RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.nondeterminism.PointerSorting %s -analyzer-output=text -verify
+
+#include "Inputs/system-header-simulator-cxx.h"
+namespace std {
+  template
+  bool is_sorted(ForwardIt first, ForwardIt last);
+
+  template 
+  void nth_element(RandomIt first, RandomIt nth, RandomIt last);
+
+  template
+  void partial_sort(RandomIt first, RandomIt middle, RandomIt last);
+
+  template
+  void sort (RandomIt first, RandomIt last);
+
+  template
+  void stable_sort(RandomIt first, RandomIt last);
+
+  template
+  BidirIt partition(BidirIt first, BidirIt last, UnaryPredicate p);
+
+  template
+  BidirIt stable_partition(BidirIt first, BidirIt last, UnaryPredicate p);
+}
+
+bool f (int x) { return true; }
+bool g (int *x) { return true; }
+
+void PointerSorting() {
+  int a = 1, b = 2, c = 3;
+  std::vector V1 = {a, b};
+  std::vector V2 = {&a, &b};
+
+  std::is_sorted(V1.begin(), V1.end());// no-warning
+  std::nth_element(V1.begin(), V1.begin() + 1, V1.end());  // no-warning
+  std::partial_sort(V1.begin(), V1.begin() + 1, V1.end()); // no-warning
+  std::sort(V1.begin(), V1.end()); // no-warning
+  std::stable_sort(V1.begin(), V1.end());  // no-warning
+  std::partition(V1.begin(), V1.end(), f); // no-warning
+  std::stable_partition(V1.begin(), V1.end(), g);  // no-warning
+
+  std::is_sorted(V2.begin(), V2.end()); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::nth_element(V2.begin(), V2.begin() + 1, V2.end()); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::partial_sort(V2.begin(), V2.begin() + 1, V2.end()); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::sort(V2.begin(), V2.end()); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::stable_sort(V2.begin(), V2.end()); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::partition(V2.begin(), V2.end(), f); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  std::stable_partition(V2.begin(), V2.end(), g); // expected-warning {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+  // expected-note@-1 {{Sorting pointer-like elements can result in non-deterministic ordering}} [alpha.nondeterminism.PointerSorting]
+}
Index: lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
===
--- /dev/null
+++ lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp
@@ -0,0 +1,114 @@
+//===-- PointerSortingChecker.cpp -===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+//
+// This file defines PointerSortingChecker which checks for non-determinism
+// caused due to sorting containers with pointer-like elements.
+//
+//===--===//
+
+#include "ClangSACheckers.h"
+#include "clang/ASTMatchers/ASTMat

[PATCH] D48862: [OpenEmbedded] Fix lib paths for OpenEmbedded targets

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 157106.
mgrang added a comment.

Thanks @rsmith. I have addressed your comments.


https://reviews.llvm.org/D48862

Files:
  lib/Driver/ToolChains/Gnu.cpp
  lib/Driver/ToolChains/Linux.cpp
  
test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/include/c++/6.3.0/backward/.keep
  
test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/aarch64-oe-linux/6.3.0/crtbegin.o
  
test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/aarch64-oe-linux/6.3.0/crtend.o
  test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/crt1.o
  test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/crti.o
  test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/crtn.o
  
test/Driver/Inputs/openembedded_arm_linux_tree/usr/include/c++/6.3.0/backward/.keep
  
test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/arm-oe-linux-gnueabi/6.3.0/crtbegin.o
  
test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/arm-oe-linux-gnueabi/6.3.0/crtend.o
  test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/crt1.o
  test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/crti.o
  test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/crtn.o
  test/Driver/linux-header-search.cpp
  test/Driver/linux-ld.c

Index: test/Driver/linux-ld.c
===
--- test/Driver/linux-ld.c
+++ test/Driver/linux-ld.c
@@ -1792,3 +1792,38 @@
 // CHECK-LD-RHLE7-DTS: Selected GCC installation: [[GCC_INSTALL:[[SYSROOT]]/lib/gcc/x86_64-redhat-linux/7]]
 // CHECK-LD-RHEL7-DTS-NOT: /usr/bin/ld
 // CHECK-LD-RHLE7-DTS: [[GCC_INSTALL]/../../../bin/ld
+
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=arm-oe-linux-gnueabi \
+// RUN: --sysroot=%S/Inputs/openembedded_arm_linux_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-OE-ARM %s
+
+// CHECK-OE-ARM: "-cc1" "-triple" "armv4t-oe-linux-gnueabi"
+// CHECK-OE-ARM: ld{{.*}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-OE-ARM: "-m" "armelf_linux_eabi" "-dynamic-linker"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/../../../lib/crt1.o"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/../../../lib/crti.o"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/crtbegin.o"
+// CHECK-OE-ARM: "-L[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0"
+// CHECK-OE-ARM: "-L[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi"
+// CHECK-OE-ARM: "-L[[SYSROOT]]/usr/lib"
+// CHECK-OE-ARM: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/crtend.o"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/../../../lib/crtn.o"
+
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=aarch64-oe-linux \
+// RUN: --sysroot=%S/Inputs/openembedded_aarch64_linux_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-OE-AARCH64 %s
+
+// CHECK-OE-AARCH64: "-cc1" "-triple" "aarch64-oe-linux"
+// CHECK-OE-AARCH64: ld{{.*}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-OE-AARCH64: "-m" "aarch64linux" "-dynamic-linker"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0/../../../lib64/crt1.o"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0/../../../lib64/crti.o"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0/crtbegin.o"
+// CHECK-OE-AARCH64: "-L[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0"
+// CHECK-OE-AARCH64: "-L[[SYSROOT]]/usr/lib64"
+// CHECK-OE-AARCH64: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0/crtend.o"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0/../../../lib64/crtn.o"
Index: test/Driver/linux-header-search.cpp
===
--- test/Driver/linux-header-search.cpp
+++ test/Driver/linux-header-search.cpp
@@ -493,3 +493,25 @@
 // CHECK-DEBIAN-SPARC64: "-internal-externc-isystem" "[[SYSROOT]]/usr/include/sparc64-linux-gnu"
 // CHECK-DEBIAN-SPARC64: "-internal-externc-isystem" "[[SYSROOT]]/include"
 // CHECK-DEBIAN-SPARC64: "-internal-externc-isystem" "[[SYSROOT]]/usr/include"
+
+// Check header search on ARM OpenEmbedded.
+// RUN: %clang -no-canonical-prefixes %s -### -fsyntax-only 2>&1 \
+// RUN: -target arm-oe-linux-gnueabi \
+// RUN: --sysroot=%S/Inputs/openembedded_arm_linux_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-OE-ARM %s
+
+// CHECK-OE-ARM: "{{[^"]*}}clang{{[^"]*}}" "-cc1"
+// CHECK-OE-ARM: "-isysroot" "[[SYSROOT:[^"]+]]"
+// CHECK-OE-ARM: "-internal-isystem" "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/../../../include/c++/6.3.0"
+// CHECK-OE-ARM: "-internal-isystem" "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/../../../include/c++/6.3.0/backward"
+
+// Check header search on AArch64 OpenEmbedded.
+// RUN: %clang -no-canoni

[PATCH] D48862: [OpenEmbedded] Fix lib paths for OpenEmbedded targets

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 157391.
mgrang added a comment.

Rebased patch and fixed unit test on Windows.


https://reviews.llvm.org/D48862

Files:
  lib/Driver/ToolChains/Gnu.cpp
  lib/Driver/ToolChains/Linux.cpp
  
test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/include/c++/6.3.0/backward/.keep
  
test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/aarch64-oe-linux/6.3.0/crtbegin.o
  
test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/aarch64-oe-linux/6.3.0/crtend.o
  test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/crt1.o
  test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/crti.o
  test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/crtn.o
  
test/Driver/Inputs/openembedded_arm_linux_tree/usr/include/c++/6.3.0/backward/.keep
  
test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/arm-oe-linux-gnueabi/6.3.0/crtbegin.o
  
test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/arm-oe-linux-gnueabi/6.3.0/crtend.o
  test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/crt1.o
  test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/crti.o
  test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/crtn.o
  test/Driver/linux-header-search.cpp
  test/Driver/linux-ld.c

Index: test/Driver/linux-ld.c
===
--- test/Driver/linux-ld.c
+++ test/Driver/linux-ld.c
@@ -1813,4 +1813,40 @@
 // CHECK-LD-AMI: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed"
 // CHECK-LD-AMI: "-lc"
 // CHECK-LD-AMI: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed"
-//
+
+// Check whether the OpenEmbedded ARM libs are added correctly.
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=arm-oe-linux-gnueabi \
+// RUN: --sysroot=%S/Inputs/openembedded_arm_linux_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-OE-ARM %s
+
+// CHECK-OE-ARM: "-cc1" "-triple" "armv4t-oe-linux-gnueabi"
+// CHECK-OE-ARM: ld{{.*}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-OE-ARM: "-m" "armelf_linux_eabi" "-dynamic-linker"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/../../../lib{{/|}}crt1.o"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/../../../lib{{/|}}crti.o"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0{{/|}}crtbegin.o"
+// CHECK-OE-ARM: "-L[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0"
+// CHECK-OE-ARM: "-L[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi"
+// CHECK-OE-ARM: "-L[[SYSROOT]]/usr/lib"
+// CHECK-OE-ARM: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0{{/|}}crtend.o"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/../../../lib{{/|}}crtn.o"
+
+// Check whether the OpenEmbedded AArch64 libs are added correctly.
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=aarch64-oe-linux \
+// RUN: --sysroot=%S/Inputs/openembedded_aarch64_linux_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-OE-AARCH64 %s
+
+// CHECK-OE-AARCH64: "-cc1" "-triple" "aarch64-oe-linux"
+// CHECK-OE-AARCH64: ld{{.*}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-OE-AARCH64: "-m" "aarch64linux" "-dynamic-linker"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0/../../../lib64{{/|}}crt1.o"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0/../../../lib64{{/|}}crti.o"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0{{/|}}crtbegin.o"
+// CHECK-OE-AARCH64: "-L[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0"
+// CHECK-OE-AARCH64: "-L[[SYSROOT]]/usr/lib64"
+// CHECK-OE-AARCH64: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0{{/|}}crtend.o"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0/../../../lib64{{/|}}crtn.o"
Index: test/Driver/linux-header-search.cpp
===
--- test/Driver/linux-header-search.cpp
+++ test/Driver/linux-header-search.cpp
@@ -493,3 +493,25 @@
 // CHECK-DEBIAN-SPARC64: "-internal-externc-isystem" "[[SYSROOT]]/usr/include/sparc64-linux-gnu"
 // CHECK-DEBIAN-SPARC64: "-internal-externc-isystem" "[[SYSROOT]]/include"
 // CHECK-DEBIAN-SPARC64: "-internal-externc-isystem" "[[SYSROOT]]/usr/include"
+
+// Check header search on OpenEmbedded ARM.
+// RUN: %clang -no-canonical-prefixes %s -### -fsyntax-only 2>&1 \
+// RUN: -target arm-oe-linux-gnueabi \
+// RUN: --sysroot=%S/Inputs/openembedded_arm_linux_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-OE-ARM %s
+
+// CHECK-OE-ARM: "{{[^"]*}}clang{{[^"]*}}" "-cc1"
+// CHECK-OE-ARM: "-isysroot" "[[SYSROOT:[^"]+]]"
+// CHECK-OE-ARM: "-internal-isystem" "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/../../../include/c++/6.3.0"
+// CHECK-OE-ARM: "-

[PATCH] D48862: [OpenEmbedded] Fix lib paths for OpenEmbedded targets

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

@rsmith Could you please take a look at the updated patch? I would like to 
commit this. Thanks.


https://reviews.llvm.org/D48862



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[PATCH] D48862: [OpenEmbedded] Fix lib paths for OpenEmbedded targets

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

I would commit this today unless there any comments. Thanks.


https://reviews.llvm.org/D48862



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[PATCH] D48862: [OpenEmbedded] Fix lib paths for OpenEmbedded targets

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL338294: [OpenEmbedded] Fix lib paths for OpenEmbedded 
targets (authored by mgrang, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D48862?vs=157391&id=158049#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D48862

Files:
  cfe/trunk/lib/Driver/ToolChains/Gnu.cpp
  cfe/trunk/lib/Driver/ToolChains/Linux.cpp
  
cfe/trunk/test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/include/c++/6.3.0/backward/.keep
  
cfe/trunk/test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/aarch64-oe-linux/6.3.0/crtbegin.o
  
cfe/trunk/test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/aarch64-oe-linux/6.3.0/crtend.o
  cfe/trunk/test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/crt1.o
  cfe/trunk/test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/crti.o
  cfe/trunk/test/Driver/Inputs/openembedded_aarch64_linux_tree/usr/lib64/crtn.o
  
cfe/trunk/test/Driver/Inputs/openembedded_arm_linux_tree/usr/include/c++/6.3.0/backward/.keep
  
cfe/trunk/test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/arm-oe-linux-gnueabi/6.3.0/crtbegin.o
  
cfe/trunk/test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/arm-oe-linux-gnueabi/6.3.0/crtend.o
  cfe/trunk/test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/crt1.o
  cfe/trunk/test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/crti.o
  cfe/trunk/test/Driver/Inputs/openembedded_arm_linux_tree/usr/lib/crtn.o
  cfe/trunk/test/Driver/linux-header-search.cpp
  cfe/trunk/test/Driver/linux-ld.c

Index: cfe/trunk/test/Driver/linux-ld.c
===
--- cfe/trunk/test/Driver/linux-ld.c
+++ cfe/trunk/test/Driver/linux-ld.c
@@ -1813,4 +1813,40 @@
 // CHECK-LD-AMI: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed"
 // CHECK-LD-AMI: "-lc"
 // CHECK-LD-AMI: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed"
-//
+
+// Check whether the OpenEmbedded ARM libs are added correctly.
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=arm-oe-linux-gnueabi \
+// RUN: --sysroot=%S/Inputs/openembedded_arm_linux_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-OE-ARM %s
+
+// CHECK-OE-ARM: "-cc1" "-triple" "armv4t-oe-linux-gnueabi"
+// CHECK-OE-ARM: ld{{.*}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-OE-ARM: "-m" "armelf_linux_eabi" "-dynamic-linker"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/../../../lib{{/|}}crt1.o"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/../../../lib{{/|}}crti.o"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0{{/|}}crtbegin.o"
+// CHECK-OE-ARM: "-L[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0"
+// CHECK-OE-ARM: "-L[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi"
+// CHECK-OE-ARM: "-L[[SYSROOT]]/usr/lib"
+// CHECK-OE-ARM: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0{{/|}}crtend.o"
+// CHECK-OE-ARM: "[[SYSROOT]]/usr/lib/arm-oe-linux-gnueabi/6.3.0/../../../lib{{/|}}crtn.o"
+
+// Check whether the OpenEmbedded AArch64 libs are added correctly.
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=aarch64-oe-linux \
+// RUN: --sysroot=%S/Inputs/openembedded_aarch64_linux_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-OE-AARCH64 %s
+
+// CHECK-OE-AARCH64: "-cc1" "-triple" "aarch64-oe-linux"
+// CHECK-OE-AARCH64: ld{{.*}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-OE-AARCH64: "-m" "aarch64linux" "-dynamic-linker"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0/../../../lib64{{/|}}crt1.o"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0/../../../lib64{{/|}}crti.o"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0{{/|}}crtbegin.o"
+// CHECK-OE-AARCH64: "-L[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0"
+// CHECK-OE-AARCH64: "-L[[SYSROOT]]/usr/lib64"
+// CHECK-OE-AARCH64: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0{{/|}}crtend.o"
+// CHECK-OE-AARCH64: "[[SYSROOT]]/usr/lib64/aarch64-oe-linux/6.3.0/../../../lib64{{/|}}crtn.o"
Index: cfe/trunk/test/Driver/linux-header-search.cpp
===
--- cfe/trunk/test/Driver/linux-header-search.cpp
+++ cfe/trunk/test/Driver/linux-header-search.cpp
@@ -493,3 +493,25 @@
 // CHECK-DEBIAN-SPARC64: "-internal-externc-isystem" "[[SYSROOT]]/usr/include/sparc64-linux-gnu"
 // CHECK-DEBIAN-SPARC64: "-internal-externc-isystem" "[[SYSROOT]]/include"
 // CHECK-DEBIAN-SPARC64: "-internal-externc-isystem" "[[SYSROOT]]/usr/include"
+
+// Check header search on OpenEmbedded ARM.
+// RUN: %clang -no-ca

[PATCH] D50029: [COFF, ARM64] Enable SEH for ARM64 Windows

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, mstorsjo, ssijaric, haripul, TomTan.
Herald added subscribers: chrib, kristof.beyls.

Repository:
  rC Clang

https://reviews.llvm.org/D50029

Files:
  include/clang/Basic/TargetInfo.h
  test/CodeGen/exceptions-seh-finally.c
  test/CodeGen/exceptions-seh.c


Index: test/CodeGen/exceptions-seh.c
===
--- test/CodeGen/exceptions-seh.c
+++ test/CodeGen/exceptions-seh.c
@@ -6,6 +6,8 @@
 // RUN: | FileCheck %s --check-prefix=X86-GNU
 // RUN: %clang_cc1 %s -triple x86_64-pc-windows-gnu -fms-extensions -emit-llvm 
-o - \
 // RUN: | FileCheck %s --check-prefix=X64-GNU
+// RUN: %clang_cc1 %s -triple aarch64-windows -fms-extensions -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefix=X64-GNU
 
 void try_body(int numerator, int denominator, int *myres) {
   *myres = numerator / denominator;
Index: test/CodeGen/exceptions-seh-finally.c
===
--- test/CodeGen/exceptions-seh-finally.c
+++ test/CodeGen/exceptions-seh-finally.c
@@ -1,5 +1,6 @@
 // RUN: %clang_cc1 %s -triple x86_64-pc-win32 -fms-extensions -emit-llvm -o - 
| FileCheck %s
 // RUN: %clang_cc1 %s -triple i686-pc-win32 -fms-extensions -emit-llvm -o - | 
FileCheck %s
+// RUN: %clang_cc1 %s -triple aarch64-windows -fms-extensions -emit-llvm -o - 
| FileCheck %s
 
 void abort(void) __attribute__((noreturn));
 void might_crash(void);
Index: include/clang/Basic/TargetInfo.h
===
--- include/clang/Basic/TargetInfo.h
+++ include/clang/Basic/TargetInfo.h
@@ -1139,7 +1139,8 @@
   bool isSEHTrySupported() const {
 return getTriple().isOSWindows() &&
(getTriple().getArch() == llvm::Triple::x86 ||
-getTriple().getArch() == llvm::Triple::x86_64);
+getTriple().getArch() == llvm::Triple::x86_64 ||
+getTriple().getArch() == llvm::Triple::aarch64);
   }
 
   /// Return true if {|} are normal characters in the asm string.


Index: test/CodeGen/exceptions-seh.c
===
--- test/CodeGen/exceptions-seh.c
+++ test/CodeGen/exceptions-seh.c
@@ -6,6 +6,8 @@
 // RUN: | FileCheck %s --check-prefix=X86-GNU
 // RUN: %clang_cc1 %s -triple x86_64-pc-windows-gnu -fms-extensions -emit-llvm -o - \
 // RUN: | FileCheck %s --check-prefix=X64-GNU
+// RUN: %clang_cc1 %s -triple aarch64-windows -fms-extensions -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefix=X64-GNU
 
 void try_body(int numerator, int denominator, int *myres) {
   *myres = numerator / denominator;
Index: test/CodeGen/exceptions-seh-finally.c
===
--- test/CodeGen/exceptions-seh-finally.c
+++ test/CodeGen/exceptions-seh-finally.c
@@ -1,5 +1,6 @@
 // RUN: %clang_cc1 %s -triple x86_64-pc-win32 -fms-extensions -emit-llvm -o - | FileCheck %s
 // RUN: %clang_cc1 %s -triple i686-pc-win32 -fms-extensions -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 %s -triple aarch64-windows -fms-extensions -emit-llvm -o - | FileCheck %s
 
 void abort(void) __attribute__((noreturn));
 void might_crash(void);
Index: include/clang/Basic/TargetInfo.h
===
--- include/clang/Basic/TargetInfo.h
+++ include/clang/Basic/TargetInfo.h
@@ -1139,7 +1139,8 @@
   bool isSEHTrySupported() const {
 return getTriple().isOSWindows() &&
(getTriple().getArch() == llvm::Triple::x86 ||
-getTriple().getArch() == llvm::Triple::x86_64);
+getTriple().getArch() == llvm::Triple::x86_64 ||
+getTriple().getArch() == llvm::Triple::aarch64);
   }
 
   /// Return true if {|} are normal characters in the asm string.
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[PATCH] D50029: [COFF, ARM64] Enable SEH for ARM64 Windows

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added inline comments.



Comment at: test/CodeGen/exceptions-seh.c:10
+// RUN: %clang_cc1 %s -triple aarch64-windows -fms-extensions -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefix=X64-GNU
 

Is it OK to re-use the X64-GNU check prefix here or should I create one called 
X64-MS?


Repository:
  rC Clang

https://reviews.llvm.org/D50029



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[PATCH] D50029: [COFF, ARM64] Enable SEH for ARM64 Windows

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 158147.
mgrang added a comment.

Addressed comments.


https://reviews.llvm.org/D50029

Files:
  include/clang/Basic/TargetInfo.h
  test/CodeGen/exceptions-seh-finally.c
  test/CodeGen/exceptions-seh.c


Index: test/CodeGen/exceptions-seh.c
===
--- test/CodeGen/exceptions-seh.c
+++ test/CodeGen/exceptions-seh.c
@@ -2,6 +2,8 @@
 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=X64
 // RUN: %clang_cc1 %s -triple i686-pc-win32 -fms-extensions -emit-llvm -o - \
 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=X86
+// RUN: %clang_cc1 %s -triple aarch64-windows -fms-extensions -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefixes=CHECK,ARM64
 // RUN: %clang_cc1 %s -triple i686-pc-windows-gnu -fms-extensions -emit-llvm 
-o - \
 // RUN: | FileCheck %s --check-prefix=X86-GNU
 // RUN: %clang_cc1 %s -triple x86_64-pc-windows-gnu -fms-extensions -emit-llvm 
-o - \
@@ -29,12 +31,14 @@
 
 // CHECK-LABEL: define dso_local i32 @safe_div(i32 %numerator, i32 
%denominator, i32* %res)
 // X64-SAME:  personality i8* bitcast (i32 (...)* @__C_specific_handler to 
i8*)
+// ARM64-SAME:personality i8* bitcast (i32 (...)* @__C_specific_handler to 
i8*)
 // X86-SAME:  personality i8* bitcast (i32 (...)* @_except_handler3 to i8*)
 // CHECK: invoke void @try_body(i32 %{{.*}}, i32 %{{.*}}, i32* %{{.*}}) 
#[[NOINLINE:[0-9]+]]
 // CHECK:   to label %{{.*}} unwind label %[[catchpad:[^ ]*]]
 //
 // CHECK: [[catchpad]]
 // X64: %[[padtoken:[^ ]*]] = catchpad within %{{[^ ]*}} [i8* null]
+// ARM64: %[[padtoken:[^ ]*]] = catchpad within %{{[^ ]*}} [i8* null]
 // X86: %[[padtoken:[^ ]*]] = catchpad within %{{[^ ]*}} [i8* bitcast (i32 ()* 
@"?filt$0@0@safe_div@@" to i8*)]
 // CHECK-NEXT: catchret from %[[padtoken]] to label %[[except:[^ ]*]]
 //
@@ -76,8 +80,10 @@
 
 // CHECK-LABEL: define dso_local i32 @filter_expr_capture()
 // X64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+// ARM64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to 
i8*)
 // X86-SAME: personality i8* bitcast (i32 (...)* @_except_handler3 to i8*)
 // X64: call void (...) @llvm.localescape(i32* %[[r:[^ ,]*]])
+// ARM64: call void (...) @llvm.localescape(i32* %[[r:[^ ,]*]])
 // X86: call void (...) @llvm.localescape(i32* %[[r:[^ ,]*]], i32* %[[code:[^ 
,]*]])
 // CHECK: store i32 42, i32* %[[r]]
 // CHECK: invoke void @j() #[[NOINLINE]]
@@ -92,6 +98,10 @@
 // X64: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %frame_pointer)
 // X64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture 
to i8*), i8* %[[fp]], i32 0)
 //
+// ARM64-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"(i8* 
%exception_pointers, i8* %frame_pointer)
+// ARM64: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 
()* @filter_expr_capture to i8*), i8* %frame_pointer)
+// ARM64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %[[fp]], i32 0)
+//
 // X86-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"()
 // X86: %[[ebp:[^ ]*]] = call i8* @llvm.frameaddress(i32 1)
 // X86: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %[[ebp]])
@@ -116,6 +126,7 @@
 }
 // CHECK-LABEL: define dso_local i32 @nested_try()
 // X64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+// ARM64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to 
i8*)
 // X86-SAME: personality i8* bitcast (i32 (...)* @_except_handler3 to i8*)
 // CHECK: store i32 42, i32* %[[r:[^ ,]*]]
 // CHECK: invoke void @j() #[[NOINLINE]]
@@ -176,6 +187,7 @@
 }
 // CHECK-LABEL: define dso_local i32 @basic_finally(i32 %g)
 // X64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+// ARM64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to 
i8*)
 // X86-SAME: personality i8* bitcast (i32 (...)* @_except_handler3 to i8*)
 // CHECK: %[[g_addr:[^ ]*]] = alloca i32, align 4
 // CHECK: call void (...) @llvm.localescape(i32* %[[g_addr]])
@@ -275,6 +287,8 @@
 // CHECK: catchret from %[[pad]]
 // X64: %[[code:[^ ]*]] = call i32 @llvm.eh.exceptioncode(token %[[pad]])
 // X64: store i32 %[[code]], i32* %[[code_slot]]
+// ARM64: %[[code:[^ ]*]] = call i32 @llvm.eh.exceptioncode(token %[[pad]])
+// ARM64: store i32 %[[code]], i32* %[[code_slot]]
 // CHECK: %[[ret1:[^ ]*]] = load i32, i32* %[[code_slot]]
 // CHECK: store i32 %[[ret1]], i32* %[[ret_slot]]
 // CHECK: %[[ret2:[^ ]*]] = load i32, i32* %[[ret_slot]]
Index: test/CodeGen/exceptions-seh-finally.c
===
--- test/CodeGen/exceptions-seh-finally.c
+++ test/CodeGen/exceptions-seh-finally.c
@@ -1,5 +1,6 @@
 // RUN: %clang_cc1 %s -triple x86_64-pc-win32 -fms-extensions

[PATCH] D50029: [COFF, ARM64] Enable SEH for ARM64 Windows

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL338405: [COFF, ARM64] Enable SEH for ARM64 Windows (authored 
by mgrang, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D50029?vs=158147&id=158320#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D50029

Files:
  cfe/trunk/include/clang/Basic/TargetInfo.h
  cfe/trunk/test/CodeGen/exceptions-seh-finally.c
  cfe/trunk/test/CodeGen/exceptions-seh.c


Index: cfe/trunk/test/CodeGen/exceptions-seh.c
===
--- cfe/trunk/test/CodeGen/exceptions-seh.c
+++ cfe/trunk/test/CodeGen/exceptions-seh.c
@@ -2,6 +2,8 @@
 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=X64
 // RUN: %clang_cc1 %s -triple i686-pc-win32 -fms-extensions -emit-llvm -o - \
 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=X86
+// RUN: %clang_cc1 %s -triple aarch64-windows -fms-extensions -emit-llvm -o - \
+// RUN: | FileCheck %s --check-prefixes=CHECK,ARM64
 // RUN: %clang_cc1 %s -triple i686-pc-windows-gnu -fms-extensions -emit-llvm 
-o - \
 // RUN: | FileCheck %s --check-prefix=X86-GNU
 // RUN: %clang_cc1 %s -triple x86_64-pc-windows-gnu -fms-extensions -emit-llvm 
-o - \
@@ -29,12 +31,14 @@
 
 // CHECK-LABEL: define dso_local i32 @safe_div(i32 %numerator, i32 
%denominator, i32* %res)
 // X64-SAME:  personality i8* bitcast (i32 (...)* @__C_specific_handler to 
i8*)
+// ARM64-SAME:personality i8* bitcast (i32 (...)* @__C_specific_handler to 
i8*)
 // X86-SAME:  personality i8* bitcast (i32 (...)* @_except_handler3 to i8*)
 // CHECK: invoke void @try_body(i32 %{{.*}}, i32 %{{.*}}, i32* %{{.*}}) 
#[[NOINLINE:[0-9]+]]
 // CHECK:   to label %{{.*}} unwind label %[[catchpad:[^ ]*]]
 //
 // CHECK: [[catchpad]]
 // X64: %[[padtoken:[^ ]*]] = catchpad within %{{[^ ]*}} [i8* null]
+// ARM64: %[[padtoken:[^ ]*]] = catchpad within %{{[^ ]*}} [i8* null]
 // X86: %[[padtoken:[^ ]*]] = catchpad within %{{[^ ]*}} [i8* bitcast (i32 ()* 
@"?filt$0@0@safe_div@@" to i8*)]
 // CHECK-NEXT: catchret from %[[padtoken]] to label %[[except:[^ ]*]]
 //
@@ -76,8 +80,10 @@
 
 // CHECK-LABEL: define dso_local i32 @filter_expr_capture()
 // X64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+// ARM64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to 
i8*)
 // X86-SAME: personality i8* bitcast (i32 (...)* @_except_handler3 to i8*)
 // X64: call void (...) @llvm.localescape(i32* %[[r:[^ ,]*]])
+// ARM64: call void (...) @llvm.localescape(i32* %[[r:[^ ,]*]])
 // X86: call void (...) @llvm.localescape(i32* %[[r:[^ ,]*]], i32* %[[code:[^ 
,]*]])
 // CHECK: store i32 42, i32* %[[r]]
 // CHECK: invoke void @j() #[[NOINLINE]]
@@ -92,6 +98,10 @@
 // X64: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %frame_pointer)
 // X64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture 
to i8*), i8* %[[fp]], i32 0)
 //
+// ARM64-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"(i8* 
%exception_pointers, i8* %frame_pointer)
+// ARM64: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 
()* @filter_expr_capture to i8*), i8* %frame_pointer)
+// ARM64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %[[fp]], i32 0)
+//
 // X86-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"()
 // X86: %[[ebp:[^ ]*]] = call i8* @llvm.frameaddress(i32 1)
 // X86: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %[[ebp]])
@@ -116,6 +126,7 @@
 }
 // CHECK-LABEL: define dso_local i32 @nested_try()
 // X64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+// ARM64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to 
i8*)
 // X86-SAME: personality i8* bitcast (i32 (...)* @_except_handler3 to i8*)
 // CHECK: store i32 42, i32* %[[r:[^ ,]*]]
 // CHECK: invoke void @j() #[[NOINLINE]]
@@ -176,6 +187,7 @@
 }
 // CHECK-LABEL: define dso_local i32 @basic_finally(i32 %g)
 // X64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
+// ARM64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to 
i8*)
 // X86-SAME: personality i8* bitcast (i32 (...)* @_except_handler3 to i8*)
 // CHECK: %[[g_addr:[^ ]*]] = alloca i32, align 4
 // CHECK: call void (...) @llvm.localescape(i32* %[[g_addr]])
@@ -275,6 +287,8 @@
 // CHECK: catchret from %[[pad]]
 // X64: %[[code:[^ ]*]] = call i32 @llvm.eh.exceptioncode(token %[[pad]])
 // X64: store i32 %[[code]], i32* %[[code_slot]]
+// ARM64: %[[code:[^ ]*]] = call i32 @llvm.eh.exceptioncode(token %[[pad]])
+// ARM64: store i32 %[[code]], i32* %[[code_slot]]
 // CHECK: %[[ret1:[^ ]*]] = load i32, i32* %[[code_slot]]
 // CHECK: store i32 %[[ret1]], i32* %[[ret_slot]]
 // CHECK: %[[ret2:[^ ]*]] = load 

[PATCH] D50123: [OpenEmbedded] Explicitly specify -stdlib and -rtlib in tests

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang accepted this revision.
mgrang added a comment.
This revision is now accepted and ready to land.

LGTM.


Repository:
  rC Clang

https://reviews.llvm.org/D50123



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[PATCH] D50152: [CodeGen] Merge equivalent block copy/helper functions

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added inline comments.



Comment at: lib/CodeGen/CGBlocks.cpp:1593
+  // Sort the captures by offset.
+  std::sort(ManagedCaptures.begin(), ManagedCaptures.end());
 }

Please use llvm::sort instead of std::sort. See 
https://llvm.org/docs/CodingStandards.html#beware-of-non-deterministic-sorting-order-of-equal-elements


Repository:
  rC Clang

https://reviews.llvm.org/D50152



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[PATCH] D50218: [OpenMP] Encode offload target triples into comdat key for offload initialization code

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

Please add some unit tests.




Comment at: lib/CodeGen/CGOpenMPRuntime.cpp:3830
+  RegFnNameParts.push_back(Device.getTriple());
+std::sort(RegFnNameParts.begin() + 2, RegFnNameParts.end());
+std::string Descriptor = getName(RegFnNameParts);

Please use llvm::sort instead of std::sort. See 
https://llvm.org/docs/CodingStandards.html#beware-of-non-deterministic-sorting-order-of-equal-elements.


Repository:
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https://reviews.llvm.org/D50218



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[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: asb, kito-cheng, apazos.
Herald added subscribers: cfe-commits, niosHD, sabuasal, jordy.potman.lists, 
simoncook, johnrusso, rbar, aheejin, jgravelle-google, sbc100, sdardis, 
dschuff, jfb.

If the flag -fuse-int128 is passed, it will enable support for __int128_t and 
uint128_t types.
This flag can then be used to build compiler-rt for RISCV32.


Repository:
  rC Clang

https://reviews.llvm.org/D43105

Files:
  include/clang/Basic/LangOptions.def
  include/clang/Basic/TargetInfo.h
  include/clang/Driver/Options.td
  lib/Basic/Targets/Mips.h
  lib/Basic/Targets/RISCV.h
  lib/Basic/Targets/WebAssembly.h
  lib/Basic/Targets/X86.h
  lib/CodeGen/SwiftCallingConv.cpp
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  lib/Frontend/InitPreprocessor.cpp
  lib/Sema/Sema.cpp
  lib/Sema/SemaOverload.cpp
  lib/Sema/SemaType.cpp
  test/Driver/types.c

Index: test/Driver/types.c
===
--- /dev/null
+++ test/Driver/types.c
@@ -0,0 +1,14 @@
+// Check whether __int128_t and __uint128_t are supported.
+
+// RUN: not %clang -c --target=riscv32-unknown-linux-gnu %s \
+// RUN: 2>&1 | FileCheck %s
+
+// RUN: %clang -c --target=riscv32-unknown-linux-gnu %s -fuse-int128
+
+void a() {
+  __int128_t s;
+  __uint128_t t;
+}
+
+// CHECK: error: use of undeclared identifier '__int128_t'
+// CHECK: error: use of undeclared identifier '__uint128_t'
Index: lib/Sema/SemaType.cpp
===
--- lib/Sema/SemaType.cpp
+++ lib/Sema/SemaType.cpp
@@ -1385,7 +1385,7 @@
 break;
   }
   case DeclSpec::TST_int128:
-if (!S.Context.getTargetInfo().hasInt128Type())
+if (!S.Context.getTargetInfo().hasInt128Type(S.getLangOpts()))
   S.Diag(DS.getTypeSpecTypeLoc(), diag::err_type_unsupported)
 << "__int128";
 if (DS.getTypeSpecSign() == DeclSpec::TSS_unsigned)
Index: lib/Sema/SemaOverload.cpp
===
--- lib/Sema/SemaOverload.cpp
+++ lib/Sema/SemaOverload.cpp
@@ -7680,12 +7680,12 @@
 ArithmeticTypes.push_back(S.Context.IntTy);
 ArithmeticTypes.push_back(S.Context.LongTy);
 ArithmeticTypes.push_back(S.Context.LongLongTy);
-if (S.Context.getTargetInfo().hasInt128Type())
+if (S.Context.getTargetInfo().hasInt128Type(S.getLangOpts()))
   ArithmeticTypes.push_back(S.Context.Int128Ty);
 ArithmeticTypes.push_back(S.Context.UnsignedIntTy);
 ArithmeticTypes.push_back(S.Context.UnsignedLongTy);
 ArithmeticTypes.push_back(S.Context.UnsignedLongLongTy);
-if (S.Context.getTargetInfo().hasInt128Type())
+if (S.Context.getTargetInfo().hasInt128Type(S.getLangOpts()))
   ArithmeticTypes.push_back(S.Context.UnsignedInt128Ty);
 LastPromotedIntegralType = ArithmeticTypes.size();
 LastPromotedArithmeticType = ArithmeticTypes.size();
Index: lib/Sema/Sema.cpp
===
--- lib/Sema/Sema.cpp
+++ lib/Sema/Sema.cpp
@@ -196,7 +196,7 @@
 return;
 
   // Initialize predefined 128-bit integer types, if needed.
-  if (Context.getTargetInfo().hasInt128Type()) {
+  if (Context.getTargetInfo().hasInt128Type(getLangOpts())) {
 // If either of the 128-bit integer types are unavailable to name lookup,
 // define them now.
 DeclarationName Int128 = &Context.Idents.get("__int128_t");
Index: lib/Frontend/InitPreprocessor.cpp
===
--- lib/Frontend/InitPreprocessor.cpp
+++ lib/Frontend/InitPreprocessor.cpp
@@ -778,7 +778,7 @@
TI.getTypeWidth(TI.getWCharType()), TI, Builder);
   DefineTypeSizeof("__SIZEOF_WINT_T__",
TI.getTypeWidth(TI.getWIntType()), TI, Builder);
-  if (TI.hasInt128Type())
+  if (TI.hasInt128Type(LangOpts))
 DefineTypeSizeof("__SIZEOF_INT128__", 128, TI, Builder);
 
   DefineType("__INTMAX_TYPE__", TI.getIntMaxType(), Builder);
@@ -1048,7 +1048,7 @@
   Builder.defineMacro("__IMAGE_SUPPORT__");
   }
 
-  if (TI.hasInt128Type() && LangOpts.CPlusPlus && LangOpts.GNUMode) {
+  if (TI.hasInt128Type(LangOpts) && LangOpts.CPlusPlus && LangOpts.GNUMode) {
 // For each extended integer type, g++ defines a macro mapping the
 // index of the type (0 in this case) in some list of extended types
 // to the type.
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -2343,6 +2343,7 @@
   Opts.HalfArgsAndReturns = Args.hasArg(OPT_fallow_half_arguments_and_returns)
 | Opts.NativeHalfArgsAndReturns;
   Opts.GNUAsm = !Args.hasArg(OPT_fno_gnu_inline_asm);
+  Opts.UseInt128 = Args.hasArg(OPT_fuse_int128);
 
   // __declspec is enabled by default for the PS4 by the driver, and also
   // enabled for Microsoft 

[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

Related compiler-rt patch: https://reviews.llvm.org/D43106


Repository:
  rC Clang

https://reviews.llvm.org/D43105



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[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 134745.
mgrang edited the summary of this revision.

Repository:
  rC Clang

https://reviews.llvm.org/D43105

Files:
  include/clang/Basic/TargetInfo.h
  include/clang/Basic/TargetOptions.h
  include/clang/Driver/Options.td
  lib/Basic/Targets/Mips.h
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/Driver/types.c

Index: test/Driver/types.c
===
--- /dev/null
+++ test/Driver/types.c
@@ -0,0 +1,15 @@
+// Check whether __int128_t and __uint128_t are supported.
+
+// RUN: not %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: 2>&1 | FileCheck %s
+
+// RUN: %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: -fforce-enable-int128
+
+void a() {
+  __int128_t s;
+  __uint128_t t;
+}
+
+// CHECK: error: use of undeclared identifier '__int128_t'
+// CHECK: error: use of undeclared identifier '__uint128_t'
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -2765,6 +2765,7 @@
   if (Opts.Triple.empty())
 Opts.Triple = llvm::sys::getDefaultTargetTriple();
   Opts.OpenCLExtensionsAsWritten = Args.getAllArgValues(OPT_cl_ext_EQ);
+  Opts.ForceEnableInt128 = Args.hasArg(OPT_fforce_enable_int128);
 }
 
 bool CompilerInvocation::CreateFromArgs(CompilerInvocation &Res,
Index: lib/Driver/ToolChains/Clang.cpp
===
--- lib/Driver/ToolChains/Clang.cpp
+++ lib/Driver/ToolChains/Clang.cpp
@@ -4725,6 +4725,9 @@
 }
   }
 
+  if (Args.hasArg(options::OPT_fforce_enable_int128))
+CmdArgs.push_back("-fforce-enable-int128");
+
   // Finally add the compile command to the compilation.
   if (Args.hasArg(options::OPT__SLASH_fallback) &&
   Output.getType() == types::TY_Object &&
Index: lib/Basic/Targets/Mips.h
===
--- lib/Basic/Targets/Mips.h
+++ lib/Basic/Targets/Mips.h
@@ -387,7 +387,9 @@
 return llvm::makeArrayRef(NewABIRegAliases);
   }
 
-  bool hasInt128Type() const override { return ABI == "n32" || ABI == "n64"; }
+  bool hasInt128Type() const override {
+return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
+  }
 
   bool validateTarget(DiagnosticsEngine &Diags) const override;
 };
Index: include/clang/Driver/Options.td
===
--- include/clang/Driver/Options.td
+++ include/clang/Driver/Options.td
@@ -839,6 +839,8 @@
 def fjump_tables : Flag<["-"], "fjump-tables">, Group;
 def fno_jump_tables : Flag<["-"], "fno-jump-tables">, Group, Flags<[CC1Option]>,
   HelpText<"Do not use jump tables for lowering switches">;
+def fforce_enable_int128 : Flag<["-"], "fforce-enable-int128">, Group,
+  Flags<[CC1Option]>, HelpText<"Enable support for int128_t type">;
 
 // Begin sanitizer flags. These should all be core options exposed in all driver
 // modes.
Index: include/clang/Basic/TargetOptions.h
===
--- include/clang/Basic/TargetOptions.h
+++ include/clang/Basic/TargetOptions.h
@@ -60,6 +60,9 @@
   /// \brief The list of OpenCL extensions to enable or disable, as written on
   /// the command line.
   std::vector OpenCLExtensionsAsWritten;
+
+  /// \brief If given, enables support for __int128_t and __uint128_t types.
+  bool ForceEnableInt128;
 };
 
 }  // end namespace clang
Index: include/clang/Basic/TargetInfo.h
===
--- include/clang/Basic/TargetInfo.h
+++ include/clang/Basic/TargetInfo.h
@@ -358,7 +358,7 @@
 
   /// \brief Determine whether the __int128 type is supported on this target.
   virtual bool hasInt128Type() const {
-return getPointerWidth(0) >= 64;
+return (getPointerWidth(0) >= 64) || getTargetOpts().ForceEnableInt128;
   } // FIXME
 
   /// \brief Determine whether the __float128 type is supported on this target.
___
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[PATCH] D43105: [RISCV] Enable __int128_t and uint128_t through clang flag

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 135112.
mgrang added a comment.

Updated patch to add -fno version of the flag -fforce-enable-int128.


Repository:
  rC Clang

https://reviews.llvm.org/D43105

Files:
  include/clang/Basic/TargetInfo.h
  include/clang/Basic/TargetOptions.h
  include/clang/Driver/Options.td
  lib/Basic/Targets/Mips.h
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/Driver/types.c

Index: test/Driver/types.c
===
--- /dev/null
+++ test/Driver/types.c
@@ -0,0 +1,18 @@
+// Check whether __int128_t and __uint128_t are supported.
+
+// RUN: not %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: 2>&1 | FileCheck %s
+
+// RUN: %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: -fno-force-enable-int128 -fforce-enable-int128
+
+// RUN: not %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: -fforce-enable-int128 -fno-force-enable-int128
+
+void a() {
+  __int128_t s;
+  __uint128_t t;
+}
+
+// CHECK: error: use of undeclared identifier '__int128_t'
+// CHECK: error: use of undeclared identifier '__uint128_t'
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -2765,6 +2765,7 @@
   if (Opts.Triple.empty())
 Opts.Triple = llvm::sys::getDefaultTargetTriple();
   Opts.OpenCLExtensionsAsWritten = Args.getAllArgValues(OPT_cl_ext_EQ);
+  Opts.ForceEnableInt128 = Args.hasArg(OPT_fforce_enable_int128);
 }
 
 bool CompilerInvocation::CreateFromArgs(CompilerInvocation &Res,
Index: lib/Driver/ToolChains/Clang.cpp
===
--- lib/Driver/ToolChains/Clang.cpp
+++ lib/Driver/ToolChains/Clang.cpp
@@ -4725,6 +4725,12 @@
 }
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_fforce_enable_int128,
+   options::OPT_fno_force_enable_int128)) {
+if (A->getOption().matches(options::OPT_fforce_enable_int128))
+  CmdArgs.push_back("-fforce-enable-int128");
+  }
+
   // Finally add the compile command to the compilation.
   if (Args.hasArg(options::OPT__SLASH_fallback) &&
   Output.getType() == types::TY_Object &&
Index: lib/Basic/Targets/Mips.h
===
--- lib/Basic/Targets/Mips.h
+++ lib/Basic/Targets/Mips.h
@@ -387,7 +387,9 @@
 return llvm::makeArrayRef(NewABIRegAliases);
   }
 
-  bool hasInt128Type() const override { return ABI == "n32" || ABI == "n64"; }
+  bool hasInt128Type() const override {
+return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
+  }
 
   bool validateTarget(DiagnosticsEngine &Diags) const override;
 };
Index: include/clang/Driver/Options.td
===
--- include/clang/Driver/Options.td
+++ include/clang/Driver/Options.td
@@ -839,6 +839,12 @@
 def fjump_tables : Flag<["-"], "fjump-tables">, Group;
 def fno_jump_tables : Flag<["-"], "fno-jump-tables">, Group, Flags<[CC1Option]>,
   HelpText<"Do not use jump tables for lowering switches">;
+def fforce_enable_int128 : Flag<["-"], "fforce-enable-int128">,
+  Group, Flags<[CC1Option]>,
+  HelpText<"Enable support for int128_t type">;
+def fno_force_enable_int128 : Flag<["-"], "fno-force-enable-int128">,
+  Group, Flags<[CC1Option]>,
+  HelpText<"Disable support for int128_t type">;
 
 // Begin sanitizer flags. These should all be core options exposed in all driver
 // modes.
Index: include/clang/Basic/TargetOptions.h
===
--- include/clang/Basic/TargetOptions.h
+++ include/clang/Basic/TargetOptions.h
@@ -60,6 +60,9 @@
   /// \brief The list of OpenCL extensions to enable or disable, as written on
   /// the command line.
   std::vector OpenCLExtensionsAsWritten;
+
+  /// \brief If given, enables support for __int128_t and __uint128_t types.
+  bool ForceEnableInt128;
 };
 
 }  // end namespace clang
Index: include/clang/Basic/TargetInfo.h
===
--- include/clang/Basic/TargetInfo.h
+++ include/clang/Basic/TargetInfo.h
@@ -358,7 +358,7 @@
 
   /// \brief Determine whether the __int128 type is supported on this target.
   virtual bool hasInt128Type() const {
-return getPointerWidth(0) >= 64;
+return (getPointerWidth(0) >= 64) || getTargetOpts().ForceEnableInt128;
   } // FIXME
 
   /// \brief Determine whether the __float128 type is supported on this target.
___
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[PATCH] D43105: [RISCV] Enable __int128_t and __uint128_t through clang flag

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 135493.
mgrang retitled this revision from "[RISCV] Enable __int128_t and uint128_t 
through clang flag" to "[RISCV] Enable __int128_t and __uint128_t through clang 
flag".
mgrang edited the summary of this revision.

Repository:
  rC Clang

https://reviews.llvm.org/D43105

Files:
  include/clang/Basic/TargetInfo.h
  include/clang/Basic/TargetOptions.h
  include/clang/Driver/Options.td
  lib/Basic/Targets/Mips.h
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/CodeGen/riscv32-abi.c
  test/Driver/types.c
  test/Preprocessor/init.c

Index: test/Preprocessor/init.c
===
--- test/Preprocessor/init.c
+++ test/Preprocessor/init.c
@@ -10210,6 +10210,11 @@
 // RISCV32-LINUX: #define linux 1
 // RISCV32-LINUX: #define unix 1
 
+// RUN: %clang_cc1 -E -dM -ffreestanding \
+// RUN: -triple=riscv32 -fforce-enable-int128 < /dev/null \
+// RUN:   | FileCheck -match-full-lines -check-prefix=RISCV32-INT128 %s
+// RISCV32-INT128: #define __SIZEOF_INT128__ 16
+
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=riscv64 < /dev/null \
 // RUN:   | FileCheck -match-full-lines -check-prefix=RISCV64 %s
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=riscv64-unknown-linux < /dev/null \
Index: test/Driver/types.c
===
--- /dev/null
+++ test/Driver/types.c
@@ -0,0 +1,18 @@
+// Check whether __int128_t and __uint128_t are supported.
+
+// RUN: not %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: 2>&1 | FileCheck %s
+
+// RUN: %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: -fno-force-enable-int128 -fforce-enable-int128
+
+// RUN: not %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: -fforce-enable-int128 -fno-force-enable-int128
+
+void a() {
+  __int128_t s;
+  __uint128_t t;
+}
+
+// CHECK: error: use of undeclared identifier '__int128_t'
+// CHECK: error: use of undeclared identifier '__uint128_t'
Index: test/CodeGen/riscv32-abi.c
===
--- test/CodeGen/riscv32-abi.c
+++ test/CodeGen/riscv32-abi.c
@@ -421,3 +421,10 @@
 
   return ret;
 }
+
+// RUN: %clang_cc1 -triple riscv32 -fforce-enable-int128 \
+// RUN: -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-FORCEINT128-LABEL
+#ifdef __SIZEOF_INT128__
+// CHECK-FORCEINT128-LABEL: define i128 @f_scalar_5(i128 %x)
+__int128_t f_scalar_5(__int128_t x) { return x; }
+#endif
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -2765,6 +2765,7 @@
   if (Opts.Triple.empty())
 Opts.Triple = llvm::sys::getDefaultTargetTriple();
   Opts.OpenCLExtensionsAsWritten = Args.getAllArgValues(OPT_cl_ext_EQ);
+  Opts.ForceEnableInt128 = Args.hasArg(OPT_fforce_enable_int128);
 }
 
 bool CompilerInvocation::CreateFromArgs(CompilerInvocation &Res,
Index: lib/Driver/ToolChains/Clang.cpp
===
--- lib/Driver/ToolChains/Clang.cpp
+++ lib/Driver/ToolChains/Clang.cpp
@@ -4725,6 +4725,12 @@
 }
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_fforce_enable_int128,
+   options::OPT_fno_force_enable_int128)) {
+if (A->getOption().matches(options::OPT_fforce_enable_int128))
+  CmdArgs.push_back("-fforce-enable-int128");
+  }
+
   // Finally add the compile command to the compilation.
   if (Args.hasArg(options::OPT__SLASH_fallback) &&
   Output.getType() == types::TY_Object &&
Index: lib/Basic/Targets/Mips.h
===
--- lib/Basic/Targets/Mips.h
+++ lib/Basic/Targets/Mips.h
@@ -387,7 +387,9 @@
 return llvm::makeArrayRef(NewABIRegAliases);
   }
 
-  bool hasInt128Type() const override { return ABI == "n32" || ABI == "n64"; }
+  bool hasInt128Type() const override {
+return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
+  }
 
   bool validateTarget(DiagnosticsEngine &Diags) const override;
 };
Index: include/clang/Driver/Options.td
===
--- include/clang/Driver/Options.td
+++ include/clang/Driver/Options.td
@@ -839,6 +839,12 @@
 def fjump_tables : Flag<["-"], "fjump-tables">, Group;
 def fno_jump_tables : Flag<["-"], "fno-jump-tables">, Group, Flags<[CC1Option]>,
   HelpText<"Do not use jump tables for lowering switches">;
+def fforce_enable_int128 : Flag<["-"], "fforce-enable-int128">,
+  Group, Flags<[CC1Option]>,
+  HelpText<"Enable support for int128_t type">;
+def fno_force_enable_int128 : Flag<["-"], "fno-force-enable-int128">,
+  Group, Flags<[CC1Option]>,
+  HelpText<"Disable support for int128_t type">;
 
 // Begin sanitizer flags. These should all be core options exposed in all dri

[PATCH] D43105: [RISCV] Enable __int128_t and __uint128_t through clang flag

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

Added tests for ABI lowering and preprocessor defines as per comments.


Repository:
  rC Clang

https://reviews.llvm.org/D43105



___
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[PATCH] D43105: [RISCV] Enable __int128_t and __uint128_t through clang flag

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 135540.
mgrang added a comment.

Thanks @asb. I have addressed your comments.


Repository:
  rC Clang

https://reviews.llvm.org/D43105

Files:
  include/clang/Basic/TargetInfo.h
  include/clang/Basic/TargetOptions.h
  include/clang/Driver/Options.td
  lib/Basic/Targets/Mips.h
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/CodeGen/riscv32-abi.c
  test/Driver/types.c
  test/Preprocessor/init.c

Index: test/Preprocessor/init.c
===
--- test/Preprocessor/init.c
+++ test/Preprocessor/init.c
@@ -10007,6 +10007,9 @@
 // RUN:   | FileCheck -match-full-lines -check-prefix=RISCV32 %s
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=riscv32-unknown-linux < /dev/null \
 // RUN:   | FileCheck -match-full-lines -check-prefixes=RISCV32,RISCV32-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=riscv32 \
+// RUN: -fforce-enable-int128 < /dev/null | FileCheck -match-full-lines \
+// RUN: -check-prefixes=RISCV32,RISCV32-INT128 %s
 // RISCV32: #define _ILP32 1
 // RISCV32: #define __ATOMIC_ACQUIRE 2
 // RISCV32: #define __ATOMIC_ACQ_REL 4
@@ -10136,6 +10139,7 @@
 // RISCV32: #define __SIG_ATOMIC_WIDTH__ 32
 // RISCV32: #define __SIZEOF_DOUBLE__ 8
 // RISCV32: #define __SIZEOF_FLOAT__ 4
+// RISCV32-INT128: #define __SIZEOF_INT128__ 16
 // RISCV32: #define __SIZEOF_INT__ 4
 // RISCV32: #define __SIZEOF_LONG_DOUBLE__ 16
 // RISCV32: #define __SIZEOF_LONG_LONG__ 8
Index: test/Driver/types.c
===
--- /dev/null
+++ test/Driver/types.c
@@ -0,0 +1,18 @@
+// Check whether __int128_t and __uint128_t are supported.
+
+// RUN: not %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: 2>&1 | FileCheck %s
+
+// RUN: %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: -fno-force-enable-int128 -fforce-enable-int128
+
+// RUN: not %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: -fforce-enable-int128 -fno-force-enable-int128
+
+void a() {
+  __int128_t s;
+  __uint128_t t;
+}
+
+// CHECK: error: use of undeclared identifier '__int128_t'
+// CHECK: error: use of undeclared identifier '__uint128_t'
Index: test/CodeGen/riscv32-abi.c
===
--- test/CodeGen/riscv32-abi.c
+++ test/CodeGen/riscv32-abi.c
@@ -1,4 +1,6 @@
 // RUN: %clang_cc1 -triple riscv32 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -fforce-enable-int128 %s -o - \
+// RUN: | FileCheck %s -check-prefix=CHECK-FORCEINT128
 
 #include 
 #include 
@@ -24,6 +26,11 @@
 // CHECK-LABEL: define i64 @f_scalar_4(i64 %x)
 int64_t f_scalar_4(int64_t x) { return x; }
 
+#ifdef __SIZEOF_INT128__
+// CHECK-FORCEINT128-LABEL: define i128 @f_scalar_5(i128 %x)
+__int128_t f_scalar_5(__int128_t x) { return x; }
+#endif
+
 // CHECK-LABEL: define float @f_fp_scalar_1(float %x)
 float f_fp_scalar_1(float x) { return x; }
 
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -2765,6 +2765,7 @@
   if (Opts.Triple.empty())
 Opts.Triple = llvm::sys::getDefaultTargetTriple();
   Opts.OpenCLExtensionsAsWritten = Args.getAllArgValues(OPT_cl_ext_EQ);
+  Opts.ForceEnableInt128 = Args.hasArg(OPT_fforce_enable_int128);
 }
 
 bool CompilerInvocation::CreateFromArgs(CompilerInvocation &Res,
Index: lib/Driver/ToolChains/Clang.cpp
===
--- lib/Driver/ToolChains/Clang.cpp
+++ lib/Driver/ToolChains/Clang.cpp
@@ -4725,6 +4725,12 @@
 }
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_fforce_enable_int128,
+   options::OPT_fno_force_enable_int128)) {
+if (A->getOption().matches(options::OPT_fforce_enable_int128))
+  CmdArgs.push_back("-fforce-enable-int128");
+  }
+
   // Finally add the compile command to the compilation.
   if (Args.hasArg(options::OPT__SLASH_fallback) &&
   Output.getType() == types::TY_Object &&
Index: lib/Basic/Targets/Mips.h
===
--- lib/Basic/Targets/Mips.h
+++ lib/Basic/Targets/Mips.h
@@ -387,7 +387,9 @@
 return llvm::makeArrayRef(NewABIRegAliases);
   }
 
-  bool hasInt128Type() const override { return ABI == "n32" || ABI == "n64"; }
+  bool hasInt128Type() const override {
+return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
+  }
 
   bool validateTarget(DiagnosticsEngine &Diags) const override;
 };
Index: include/clang/Driver/Options.td
===
--- include/clang/Driver/Options.td
+++ include/clang/Driver/Options.td
@@ -839,6 +839,12 @@
 def fjump_tables : Flag<["-"], "fjump-tables">, Group;
 def fno_jump_tables : Flag<["-"], "fno-jump-

[PATCH] D43105: [RISCV] Enable __int128_t and __uint128_t through clang flag

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 135553.

Repository:
  rC Clang

https://reviews.llvm.org/D43105

Files:
  include/clang/Basic/TargetInfo.h
  include/clang/Basic/TargetOptions.h
  include/clang/Driver/Options.td
  lib/Basic/Targets/Mips.h
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/CodeGen/riscv32-abi.c
  test/Driver/types.c
  test/Preprocessor/init.c

Index: test/Preprocessor/init.c
===
--- test/Preprocessor/init.c
+++ test/Preprocessor/init.c
@@ -10007,6 +10007,9 @@
 // RUN:   | FileCheck -match-full-lines -check-prefix=RISCV32 %s
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=riscv32-unknown-linux < /dev/null \
 // RUN:   | FileCheck -match-full-lines -check-prefixes=RISCV32,RISCV32-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=riscv32 \
+// RUN: -fforce-enable-int128 < /dev/null | FileCheck -match-full-lines \
+// RUN: -check-prefixes=RISCV32,RISCV32-INT128 %s
 // RISCV32: #define _ILP32 1
 // RISCV32: #define __ATOMIC_ACQUIRE 2
 // RISCV32: #define __ATOMIC_ACQ_REL 4
@@ -10136,6 +10139,7 @@
 // RISCV32: #define __SIG_ATOMIC_WIDTH__ 32
 // RISCV32: #define __SIZEOF_DOUBLE__ 8
 // RISCV32: #define __SIZEOF_FLOAT__ 4
+// RISCV32-INT128: #define __SIZEOF_INT128__ 16
 // RISCV32: #define __SIZEOF_INT__ 4
 // RISCV32: #define __SIZEOF_LONG_DOUBLE__ 16
 // RISCV32: #define __SIZEOF_LONG_LONG__ 8
Index: test/Driver/types.c
===
--- /dev/null
+++ test/Driver/types.c
@@ -0,0 +1,18 @@
+// Check whether __int128_t and __uint128_t are supported.
+
+// RUN: not %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: 2>&1 | FileCheck %s
+
+// RUN: %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: -fno-force-enable-int128 -fforce-enable-int128
+
+// RUN: not %clang -c --target=riscv32-unknown-linux-gnu -fsyntax-only %s \
+// RUN: -fforce-enable-int128 -fno-force-enable-int128
+
+void a() {
+  __int128_t s;
+  __uint128_t t;
+}
+
+// CHECK: error: use of undeclared identifier '__int128_t'
+// CHECK: error: use of undeclared identifier '__uint128_t'
Index: test/CodeGen/riscv32-abi.c
===
--- test/CodeGen/riscv32-abi.c
+++ test/CodeGen/riscv32-abi.c
@@ -1,4 +1,6 @@
 // RUN: %clang_cc1 -triple riscv32 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -fforce-enable-int128 %s -o - \
+// RUN: | FileCheck %s -check-prefixes=CHECK,CHECK-FORCEINT128
 
 #include 
 #include 
@@ -24,6 +26,11 @@
 // CHECK-LABEL: define i64 @f_scalar_4(i64 %x)
 int64_t f_scalar_4(int64_t x) { return x; }
 
+#ifdef __SIZEOF_INT128__
+// CHECK-FORCEINT128-LABEL: define i128 @f_scalar_5(i128 %x)
+__int128_t f_scalar_5(__int128_t x) { return x; }
+#endif
+
 // CHECK-LABEL: define float @f_fp_scalar_1(float %x)
 float f_fp_scalar_1(float x) { return x; }
 
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -2765,6 +2765,7 @@
   if (Opts.Triple.empty())
 Opts.Triple = llvm::sys::getDefaultTargetTriple();
   Opts.OpenCLExtensionsAsWritten = Args.getAllArgValues(OPT_cl_ext_EQ);
+  Opts.ForceEnableInt128 = Args.hasArg(OPT_fforce_enable_int128);
 }
 
 bool CompilerInvocation::CreateFromArgs(CompilerInvocation &Res,
Index: lib/Driver/ToolChains/Clang.cpp
===
--- lib/Driver/ToolChains/Clang.cpp
+++ lib/Driver/ToolChains/Clang.cpp
@@ -4725,6 +4725,12 @@
 }
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_fforce_enable_int128,
+   options::OPT_fno_force_enable_int128)) {
+if (A->getOption().matches(options::OPT_fforce_enable_int128))
+  CmdArgs.push_back("-fforce-enable-int128");
+  }
+
   // Finally add the compile command to the compilation.
   if (Args.hasArg(options::OPT__SLASH_fallback) &&
   Output.getType() == types::TY_Object &&
Index: lib/Basic/Targets/Mips.h
===
--- lib/Basic/Targets/Mips.h
+++ lib/Basic/Targets/Mips.h
@@ -387,7 +387,9 @@
 return llvm::makeArrayRef(NewABIRegAliases);
   }
 
-  bool hasInt128Type() const override { return ABI == "n32" || ABI == "n64"; }
+  bool hasInt128Type() const override {
+return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
+  }
 
   bool validateTarget(DiagnosticsEngine &Diags) const override;
 };
Index: include/clang/Driver/Options.td
===
--- include/clang/Driver/Options.td
+++ include/clang/Driver/Options.td
@@ -839,6 +839,12 @@
 def fjump_tables : Flag<["-"], "fjump-tables">, Group;
 def fno_jump_tables : Flag<["-"], "fno-jump-tables">, Group, Flags<[CC1Option]>,
   HelpText<"Do not use ju

[PATCH] D43105: [RISCV] Enable __int128_t and __uint128_t through clang flag

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL326045: [RISCV] Enable __int128_t and __uint128_t through 
clang flag (authored by mgrang, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D43105?vs=135553&id=135807#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D43105

Files:
  cfe/trunk/include/clang/Basic/TargetInfo.h
  cfe/trunk/include/clang/Basic/TargetOptions.h
  cfe/trunk/include/clang/Driver/Options.td
  cfe/trunk/lib/Basic/Targets/Mips.h
  cfe/trunk/lib/Driver/ToolChains/Clang.cpp
  cfe/trunk/lib/Frontend/CompilerInvocation.cpp
  cfe/trunk/test/CodeGen/riscv32-abi.c
  cfe/trunk/test/Driver/types.c
  cfe/trunk/test/Preprocessor/init.c

Index: cfe/trunk/lib/Driver/ToolChains/Clang.cpp
===
--- cfe/trunk/lib/Driver/ToolChains/Clang.cpp
+++ cfe/trunk/lib/Driver/ToolChains/Clang.cpp
@@ -4750,6 +4750,12 @@
 }
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_fforce_enable_int128,
+   options::OPT_fno_force_enable_int128)) {
+if (A->getOption().matches(options::OPT_fforce_enable_int128))
+  CmdArgs.push_back("-fforce-enable-int128");
+  }
+
   // Finally add the compile command to the compilation.
   if (Args.hasArg(options::OPT__SLASH_fallback) &&
   Output.getType() == types::TY_Object &&
Index: cfe/trunk/lib/Basic/Targets/Mips.h
===
--- cfe/trunk/lib/Basic/Targets/Mips.h
+++ cfe/trunk/lib/Basic/Targets/Mips.h
@@ -392,7 +392,9 @@
 return llvm::makeArrayRef(NewABIRegAliases);
   }
 
-  bool hasInt128Type() const override { return ABI == "n32" || ABI == "n64"; }
+  bool hasInt128Type() const override {
+return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
+  }
 
   bool validateTarget(DiagnosticsEngine &Diags) const override;
 };
Index: cfe/trunk/lib/Frontend/CompilerInvocation.cpp
===
--- cfe/trunk/lib/Frontend/CompilerInvocation.cpp
+++ cfe/trunk/lib/Frontend/CompilerInvocation.cpp
@@ -2781,6 +2781,7 @@
   if (Opts.Triple.empty())
 Opts.Triple = llvm::sys::getDefaultTargetTriple();
   Opts.OpenCLExtensionsAsWritten = Args.getAllArgValues(OPT_cl_ext_EQ);
+  Opts.ForceEnableInt128 = Args.hasArg(OPT_fforce_enable_int128);
 }
 
 bool CompilerInvocation::CreateFromArgs(CompilerInvocation &Res,
Index: cfe/trunk/include/clang/Driver/Options.td
===
--- cfe/trunk/include/clang/Driver/Options.td
+++ cfe/trunk/include/clang/Driver/Options.td
@@ -849,6 +849,12 @@
 def fjump_tables : Flag<["-"], "fjump-tables">, Group;
 def fno_jump_tables : Flag<["-"], "fno-jump-tables">, Group, Flags<[CC1Option]>,
   HelpText<"Do not use jump tables for lowering switches">;
+def fforce_enable_int128 : Flag<["-"], "fforce-enable-int128">,
+  Group, Flags<[CC1Option]>,
+  HelpText<"Enable support for int128_t type">;
+def fno_force_enable_int128 : Flag<["-"], "fno-force-enable-int128">,
+  Group, Flags<[CC1Option]>,
+  HelpText<"Disable support for int128_t type">;
 
 // Begin sanitizer flags. These should all be core options exposed in all driver
 // modes.
Index: cfe/trunk/include/clang/Basic/TargetOptions.h
===
--- cfe/trunk/include/clang/Basic/TargetOptions.h
+++ cfe/trunk/include/clang/Basic/TargetOptions.h
@@ -60,6 +60,9 @@
   /// \brief The list of OpenCL extensions to enable or disable, as written on
   /// the command line.
   std::vector OpenCLExtensionsAsWritten;
+
+  /// \brief If given, enables support for __int128_t and __uint128_t types.
+  bool ForceEnableInt128;
 };
 
 }  // end namespace clang
Index: cfe/trunk/include/clang/Basic/TargetInfo.h
===
--- cfe/trunk/include/clang/Basic/TargetInfo.h
+++ cfe/trunk/include/clang/Basic/TargetInfo.h
@@ -358,7 +358,7 @@
 
   /// \brief Determine whether the __int128 type is supported on this target.
   virtual bool hasInt128Type() const {
-return getPointerWidth(0) >= 64;
+return (getPointerWidth(0) >= 64) || getTargetOpts().ForceEnableInt128;
   } // FIXME
 
   /// \brief Determine whether the __float128 type is supported on this target.
Index: cfe/trunk/test/CodeGen/riscv32-abi.c
===
--- cfe/trunk/test/CodeGen/riscv32-abi.c
+++ cfe/trunk/test/CodeGen/riscv32-abi.c
@@ -1,4 +1,6 @@
 // RUN: %clang_cc1 -triple riscv32 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -fforce-enable-int128 %s -o - \
+// RUN: | FileCheck %s -check-prefixes=CHECK,CHECK-FORCEINT128
 
 #include 
 #include 
@@ -24,6 +26,11 @@
 // CHECK-LABEL: define i64 @f_scalar_4(i64 %x)
 int64_t f_scalar_4(int64_t x) { return x; }
 
+#ifdef __SIZE

[PATCH] D43105: [RISCV] Enable __int128_t and __uint128_t through clang flag

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

After addressing comments, I have now committed this patch. Thanks for all the 
reviews!


Repository:
  rC Clang

https://reviews.llvm.org/D43105



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[PATCH] D33926: [clang] Remove double semicolons. NFC.

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added a project: clang-c.

https://reviews.llvm.org/D33926

Files:
  lib/AST/Type.cpp
  lib/Sema/SemaType.cpp


Index: lib/Sema/SemaType.cpp
===
--- lib/Sema/SemaType.cpp
+++ lib/Sema/SemaType.cpp
@@ -3367,7 +3367,7 @@
 if (auto objcClass = type->getAs()) {
   if (objcClass->getInterface()->getIdentifier() == S.getNSErrorIdent()) {
 if (numNormalPointers == 2 && numTypeSpecifierPointers < 2)
-  return PointerDeclaratorKind::NSErrorPointerPointer;;
+  return PointerDeclaratorKind::NSErrorPointerPointer;
   }
 
   break;
Index: lib/AST/Type.cpp
===
--- lib/AST/Type.cpp
+++ lib/AST/Type.cpp
@@ -1344,7 +1344,7 @@
   } else if (getAs()) {
 ASTContext &ctx = dc->getParentASTContext();
 objectType = ctx.getObjCObjectType(ctx.ObjCBuiltinIdTy, { }, { })
-   ->castAs();;
+   ->castAs();
   } else {
 objectType = getAs();
   }


Index: lib/Sema/SemaType.cpp
===
--- lib/Sema/SemaType.cpp
+++ lib/Sema/SemaType.cpp
@@ -3367,7 +3367,7 @@
 if (auto objcClass = type->getAs()) {
   if (objcClass->getInterface()->getIdentifier() == S.getNSErrorIdent()) {
 if (numNormalPointers == 2 && numTypeSpecifierPointers < 2)
-  return PointerDeclaratorKind::NSErrorPointerPointer;;
+  return PointerDeclaratorKind::NSErrorPointerPointer;
   }
 
   break;
Index: lib/AST/Type.cpp
===
--- lib/AST/Type.cpp
+++ lib/AST/Type.cpp
@@ -1344,7 +1344,7 @@
   } else if (getAs()) {
 ASTContext &ctx = dc->getParentASTContext();
 objectType = ctx.getObjCObjectType(ctx.ObjCBuiltinIdTy, { }, { })
-   ->castAs();;
+   ->castAs();
   } else {
 objectType = getAs();
   }
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[PATCH] D33926: [clang] Remove double semicolons. NFC.

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL304823: [clang] Remove double semicolons. NFC. (authored by 
mgrang).

Changed prior to commit:
  https://reviews.llvm.org/D33926?vs=101506&id=101604#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D33926

Files:
  cfe/trunk/lib/AST/Type.cpp
  cfe/trunk/lib/Sema/SemaType.cpp


Index: cfe/trunk/lib/AST/Type.cpp
===
--- cfe/trunk/lib/AST/Type.cpp
+++ cfe/trunk/lib/AST/Type.cpp
@@ -1344,7 +1344,7 @@
   } else if (getAs()) {
 ASTContext &ctx = dc->getParentASTContext();
 objectType = ctx.getObjCObjectType(ctx.ObjCBuiltinIdTy, { }, { })
-   ->castAs();;
+   ->castAs();
   } else {
 objectType = getAs();
   }
Index: cfe/trunk/lib/Sema/SemaType.cpp
===
--- cfe/trunk/lib/Sema/SemaType.cpp
+++ cfe/trunk/lib/Sema/SemaType.cpp
@@ -3367,7 +3367,7 @@
 if (auto objcClass = type->getAs()) {
   if (objcClass->getInterface()->getIdentifier() == S.getNSErrorIdent()) {
 if (numNormalPointers == 2 && numTypeSpecifierPointers < 2)
-  return PointerDeclaratorKind::NSErrorPointerPointer;;
+  return PointerDeclaratorKind::NSErrorPointerPointer;
   }
 
   break;


Index: cfe/trunk/lib/AST/Type.cpp
===
--- cfe/trunk/lib/AST/Type.cpp
+++ cfe/trunk/lib/AST/Type.cpp
@@ -1344,7 +1344,7 @@
   } else if (getAs()) {
 ASTContext &ctx = dc->getParentASTContext();
 objectType = ctx.getObjCObjectType(ctx.ObjCBuiltinIdTy, { }, { })
-   ->castAs();;
+   ->castAs();
   } else {
 objectType = getAs();
   }
Index: cfe/trunk/lib/Sema/SemaType.cpp
===
--- cfe/trunk/lib/Sema/SemaType.cpp
+++ cfe/trunk/lib/Sema/SemaType.cpp
@@ -3367,7 +3367,7 @@
 if (auto objcClass = type->getAs()) {
   if (objcClass->getInterface()->getIdentifier() == S.getNSErrorIdent()) {
 if (numNormalPointers == 2 && numTypeSpecifierPointers < 2)
-  return PointerDeclaratorKind::NSErrorPointerPointer;;
+  return PointerDeclaratorKind::NSErrorPointerPointer;
   }
 
   break;
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[PATCH] D44229: Don't use -pie in relocatable link.

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added inline comments.



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:311
+  if (Args.hasArg(options::OPT_shared) || Args.hasArg(options::OPT_static) ||
+  Args.hasArg(options::OPT_r))
 return false;

We also need to check for -Wl,-r and -Xlinker -r options.


https://reviews.llvm.org/D44229



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[PATCH] D44362: [clang] Change std::sort to llvm::sort in response to r327219

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rsmith, rnk, chandlerc.
mgrang added a project: clang.
Herald added a subscriber: klimek.

r327219 added wrappers to std::sort which randomly shuffle the container before 
sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of 
std::sort.


Repository:
  rC Clang

https://reviews.llvm.org/D44362

Files:
  include/clang-c/Index.h
  include/clang/Basic/Attr.td
  include/clang/Serialization/ContinuousRangeMap.h
  lib/AST/ASTContext.cpp
  lib/AST/ItaniumMangle.cpp
  lib/AST/VTableBuilder.cpp
  lib/ASTMatchers/Dynamic/Parser.cpp
  lib/Analysis/LiveVariables.cpp
  lib/Basic/VirtualFileSystem.cpp
  lib/CodeGen/CGVTables.cpp
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/Driver.cpp
  lib/Format/FormatTokenLexer.cpp
  lib/Format/WhitespaceManager.cpp
  lib/Frontend/CompilerInvocation.cpp
  lib/Frontend/DiagnosticRenderer.cpp
  lib/Sema/AnalysisBasedWarnings.cpp
  lib/Sema/SemaDecl.cpp
  lib/Sema/SemaDeclAttr.cpp
  lib/Sema/SemaLookup.cpp
  lib/Sema/SemaOverload.cpp
  lib/Sema/SemaType.cpp
  lib/Serialization/ASTReader.cpp
  lib/Serialization/ASTReaderDecl.cpp
  lib/Serialization/ASTWriter.cpp
  lib/StaticAnalyzer/Checkers/PaddingChecker.cpp
  lib/StaticAnalyzer/Core/BugReporter.cpp
  lib/StaticAnalyzer/Core/CheckerRegistry.cpp
  lib/Tooling/ASTDiff/ASTDiff.cpp
  lib/Tooling/Core/Replacement.cpp
  tools/diagtool/DiagTool.cpp
  tools/libclang/CIndex.cpp
  unittests/Basic/VirtualFileSystemTest.cpp
  utils/TableGen/ClangAttrEmitter.cpp
  utils/TableGen/ClangDiagnosticsEmitter.cpp
  utils/TableGen/ClangOptionDocEmitter.cpp
  utils/TableGen/NeonEmitter.cpp

Index: utils/TableGen/NeonEmitter.cpp
===
--- utils/TableGen/NeonEmitter.cpp
+++ utils/TableGen/NeonEmitter.cpp
@@ -2007,7 +2007,7 @@
 }
   }
 
-  std::sort(NewTypeSpecs.begin(), NewTypeSpecs.end());
+  llvm::sort(NewTypeSpecs.begin(), NewTypeSpecs.end());
   NewTypeSpecs.erase(std::unique(NewTypeSpecs.begin(), NewTypeSpecs.end()),
 		 NewTypeSpecs.end());
   auto &Entry = IntrinsicMap[Name];
Index: utils/TableGen/ClangOptionDocEmitter.cpp
===
--- utils/TableGen/ClangOptionDocEmitter.cpp
+++ utils/TableGen/ClangOptionDocEmitter.cpp
@@ -111,25 +111,25 @@
 
   auto DocumentationForOption = [&](Record *R) -> DocumentedOption {
 auto &A = Aliases[R];
-std::sort(A.begin(), A.end(), CompareByName);
+llvm::sort(A.begin(), A.end(), CompareByName);
 return {R, std::move(A)};
   };
 
   std::function DocumentationForGroup =
   [&](Record *R) -> Documentation {
 Documentation D;
 
 auto &Groups = GroupsInGroup[R];
-std::sort(Groups.begin(), Groups.end(), CompareByLocation);
+llvm::sort(Groups.begin(), Groups.end(), CompareByLocation);
 for (Record *G : Groups) {
   D.Groups.emplace_back();
   D.Groups.back().Group = G;
   Documentation &Base = D.Groups.back();
   Base = DocumentationForGroup(G);
 }
 
 auto &Options = OptionsInGroup[R];
-std::sort(Options.begin(), Options.end(), CompareByName);
+llvm::sort(Options.begin(), Options.end(), CompareByName);
 for (Record *O : Options)
   D.Options.push_back(DocumentationForOption(O));
 
Index: utils/TableGen/ClangDiagnosticsEmitter.cpp
===
--- utils/TableGen/ClangDiagnosticsEmitter.cpp
+++ utils/TableGen/ClangDiagnosticsEmitter.cpp
@@ -207,9 +207,9 @@
   E = SortedGroups.end();
I != E; ++I) {
 MutableArrayRef GroupDiags = (*I)->DiagsInGroup;
-std::sort(GroupDiags.begin(), GroupDiags.end(), beforeThanCompare);
+llvm::sort(GroupDiags.begin(), GroupDiags.end(), beforeThanCompare);
   }
-  std::sort(SortedGroups.begin(), SortedGroups.end(), beforeThanCompareGroups);
+  llvm::sort(SortedGroups.begin(), SortedGroups.end(), beforeThanCompareGroups);
 
   // Warn about the same group being used anonymously in multiple places.
   for (SmallVectorImpl::const_iterator I = SortedGroups.begin(),
@@ -863,7 +863,7 @@
 Index.push_back(RecordIndexElement(R));
   }
 
-  std::sort(Index.begin(), Index.end(),
+  llvm::sort(Index.begin(), Index.end(),
 [](const RecordIndexElement &Lhs,
const RecordIndexElement &Rhs) { return Lhs.Name < Rhs.Name; });
 
@@ -1212,7 +1212,7 @@
   Records.getAllDerivedDefinitions("Diagnostic");
   std::vector DiagGroups =
   Records.getAllDerivedDefinitions("DiagGroup");
-  std::sort(DiagGroups.begin(), DiagGroups.end(), diagGroupBeforeByName);
+  llvm::sort(DiagGroups.begin(), DiagGroups.end(), diagGroupBeforeByName);
 
   DiagGroupParentMap DGParentMap(Records);
 
@@ -1231,9 +1231,9 @@
   DiagsInPed

[PATCH] D44362: [clang] Change std::sort to llvm::sort in response to r327219

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 137966.
mgrang added a comment.

Fixed indentation.


Repository:
  rC Clang

https://reviews.llvm.org/D44362

Files:
  include/clang/Basic/Attr.td
  include/clang/Serialization/ContinuousRangeMap.h
  lib/AST/ASTContext.cpp
  lib/AST/ItaniumMangle.cpp
  lib/AST/VTableBuilder.cpp
  lib/ASTMatchers/Dynamic/Parser.cpp
  lib/Analysis/LiveVariables.cpp
  lib/Basic/VirtualFileSystem.cpp
  lib/CodeGen/CGVTables.cpp
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/Driver.cpp
  lib/Format/FormatTokenLexer.cpp
  lib/Format/WhitespaceManager.cpp
  lib/Frontend/CompilerInvocation.cpp
  lib/Frontend/DiagnosticRenderer.cpp
  lib/Sema/AnalysisBasedWarnings.cpp
  lib/Sema/SemaDecl.cpp
  lib/Sema/SemaDeclAttr.cpp
  lib/Sema/SemaLookup.cpp
  lib/Sema/SemaOverload.cpp
  lib/Sema/SemaType.cpp
  lib/Serialization/ASTReader.cpp
  lib/Serialization/ASTReaderDecl.cpp
  lib/Serialization/ASTWriter.cpp
  lib/StaticAnalyzer/Checkers/PaddingChecker.cpp
  lib/StaticAnalyzer/Core/BugReporter.cpp
  lib/StaticAnalyzer/Core/CheckerRegistry.cpp
  lib/Tooling/ASTDiff/ASTDiff.cpp
  lib/Tooling/Core/Replacement.cpp
  tools/diagtool/DiagTool.cpp
  tools/libclang/CIndex.cpp
  unittests/Basic/VirtualFileSystemTest.cpp
  utils/TableGen/ClangAttrEmitter.cpp
  utils/TableGen/ClangDiagnosticsEmitter.cpp
  utils/TableGen/ClangOptionDocEmitter.cpp
  utils/TableGen/NeonEmitter.cpp

Index: utils/TableGen/NeonEmitter.cpp
===
--- utils/TableGen/NeonEmitter.cpp
+++ utils/TableGen/NeonEmitter.cpp
@@ -2007,7 +2007,7 @@
 }
   }
 
-  std::sort(NewTypeSpecs.begin(), NewTypeSpecs.end());
+  llvm::sort(NewTypeSpecs.begin(), NewTypeSpecs.end());
   NewTypeSpecs.erase(std::unique(NewTypeSpecs.begin(), NewTypeSpecs.end()),
 		 NewTypeSpecs.end());
   auto &Entry = IntrinsicMap[Name];
Index: utils/TableGen/ClangOptionDocEmitter.cpp
===
--- utils/TableGen/ClangOptionDocEmitter.cpp
+++ utils/TableGen/ClangOptionDocEmitter.cpp
@@ -111,25 +111,25 @@
 
   auto DocumentationForOption = [&](Record *R) -> DocumentedOption {
 auto &A = Aliases[R];
-std::sort(A.begin(), A.end(), CompareByName);
+llvm::sort(A.begin(), A.end(), CompareByName);
 return {R, std::move(A)};
   };
 
   std::function DocumentationForGroup =
   [&](Record *R) -> Documentation {
 Documentation D;
 
 auto &Groups = GroupsInGroup[R];
-std::sort(Groups.begin(), Groups.end(), CompareByLocation);
+llvm::sort(Groups.begin(), Groups.end(), CompareByLocation);
 for (Record *G : Groups) {
   D.Groups.emplace_back();
   D.Groups.back().Group = G;
   Documentation &Base = D.Groups.back();
   Base = DocumentationForGroup(G);
 }
 
 auto &Options = OptionsInGroup[R];
-std::sort(Options.begin(), Options.end(), CompareByName);
+llvm::sort(Options.begin(), Options.end(), CompareByName);
 for (Record *O : Options)
   D.Options.push_back(DocumentationForOption(O));
 
Index: utils/TableGen/ClangDiagnosticsEmitter.cpp
===
--- utils/TableGen/ClangDiagnosticsEmitter.cpp
+++ utils/TableGen/ClangDiagnosticsEmitter.cpp
@@ -207,9 +207,9 @@
   E = SortedGroups.end();
I != E; ++I) {
 MutableArrayRef GroupDiags = (*I)->DiagsInGroup;
-std::sort(GroupDiags.begin(), GroupDiags.end(), beforeThanCompare);
+llvm::sort(GroupDiags.begin(), GroupDiags.end(), beforeThanCompare);
   }
-  std::sort(SortedGroups.begin(), SortedGroups.end(), beforeThanCompareGroups);
+  llvm::sort(SortedGroups.begin(), SortedGroups.end(), beforeThanCompareGroups);
 
   // Warn about the same group being used anonymously in multiple places.
   for (SmallVectorImpl::const_iterator I = SortedGroups.begin(),
@@ -863,9 +863,10 @@
 Index.push_back(RecordIndexElement(R));
   }
 
-  std::sort(Index.begin(), Index.end(),
-[](const RecordIndexElement &Lhs,
-   const RecordIndexElement &Rhs) { return Lhs.Name < Rhs.Name; });
+  llvm::sort(Index.begin(), Index.end(),
+ [](const RecordIndexElement &Lhs, const RecordIndexElement &Rhs) {
+   return Lhs.Name < Rhs.Name;
+});
 
   for (unsigned i = 0, e = Index.size(); i != e; ++i) {
 const RecordIndexElement &R = Index[i];
@@ -1212,7 +1213,7 @@
   Records.getAllDerivedDefinitions("Diagnostic");
   std::vector DiagGroups =
   Records.getAllDerivedDefinitions("DiagGroup");
-  std::sort(DiagGroups.begin(), DiagGroups.end(), diagGroupBeforeByName);
+  llvm::sort(DiagGroups.begin(), DiagGroups.end(), diagGroupBeforeByName);
 
   DiagGroupParentMap DGParentMap(Records);
 
@@ -1231,10 +1232,10 @@
   DiagsInPedanticSet.end());
 RecordVec GroupsInPedantic(GroupsInPedanticSet.begin(),
GroupsInPedanticSe

[PATCH] D44362: [clang] Change std::sort to llvm::sort in response to r327219

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

Ping for reviews please.


Repository:
  rC Clang

https://reviews.llvm.org/D44362



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[PATCH] D48132: [COFF] Add ARM64 intrinsics: __yield, __wfe, __wfi, __sev, __sevl

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: mstorsjo, compnerd.
Herald added a reviewer: javed.absar.
Herald added subscribers: chrib, kristof.beyls.

These intrinsics result in hint instructions. They are provided here for MSVC 
ARM64 compatibility.


Repository:
  rC Clang

https://reviews.llvm.org/D48132

Files:
  include/clang/Basic/BuiltinsAArch64.def
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGen/arm64-microsoft-intrinsics.c


Index: test/CodeGen/arm64-microsoft-intrinsics.c
===
--- test/CodeGen/arm64-microsoft-intrinsics.c
+++ test/CodeGen/arm64-microsoft-intrinsics.c
@@ -24,3 +24,38 @@
 
 // CHECK-MSVC: @llvm.aarch64.isb(i32 0)
 // CHECK-LINUX: error: implicit declaration of function '__isb'
+
+void check__yield(void) {
+  __yield();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 1)
+// CHECK-LINUX: error: implicit declaration of function '__yield'
+
+void check__wfe(void) {
+  __wfe();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 2)
+// CHECK-LINUX: error: implicit declaration of function '__wfe'
+
+void check__wfi(void) {
+  __wfi();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 3)
+// CHECK-LINUX: error: implicit declaration of function '__wfi'
+
+void check__sev(void) {
+  __sev();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 4)
+// CHECK-LINUX: error: implicit declaration of function '__sev'
+
+void check__sevl(void) {
+  __sevl();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 5)
+// CHECK-LINUX: error: implicit declaration of function '__sevl'
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -6362,18 +6362,23 @@
 HintID = 0;
 break;
   case AArch64::BI__builtin_arm_yield:
+  case AArch64::BI__yield:
 HintID = 1;
 break;
   case AArch64::BI__builtin_arm_wfe:
+  case AArch64::BI__wfe:
 HintID = 2;
 break;
   case AArch64::BI__builtin_arm_wfi:
+  case AArch64::BI__wfi:
 HintID = 3;
 break;
   case AArch64::BI__builtin_arm_sev:
+  case AArch64::BI__sev:
 HintID = 4;
 break;
   case AArch64::BI__builtin_arm_sevl:
+  case AArch64::BI__sevl:
 HintID = 5;
 break;
   }
Index: include/clang/Basic/BuiltinsAArch64.def
===
--- include/clang/Basic/BuiltinsAArch64.def
+++ include/clang/Basic/BuiltinsAArch64.def
@@ -65,9 +65,15 @@
 BUILTIN(__builtin_arm_wsr64, "vcC*LUi", "nc")
 BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
 
+// MSVC
 LANGBUILTIN(__dmb, "vUi", "nc", ALL_MS_LANGUAGES)
 LANGBUILTIN(__dsb, "vUi", "nc", ALL_MS_LANGUAGES)
 LANGBUILTIN(__isb, "vUi", "nc", ALL_MS_LANGUAGES)
+LANGBUILTIN(__yield, "v", "",   ALL_MS_LANGUAGES)
+LANGBUILTIN(__wfe,   "v", "",   ALL_MS_LANGUAGES)
+LANGBUILTIN(__wfi,   "v", "",   ALL_MS_LANGUAGES)
+LANGBUILTIN(__sev,   "v", "",   ALL_MS_LANGUAGES)
+LANGBUILTIN(__sevl,  "v", "",   ALL_MS_LANGUAGES)
 
 // MSVC intrinsics for volatile but non-acquire/release loads and stores
 LANGBUILTIN(__iso_volatile_load8,   "ccCD*", "n", ALL_MS_LANGUAGES)


Index: test/CodeGen/arm64-microsoft-intrinsics.c
===
--- test/CodeGen/arm64-microsoft-intrinsics.c
+++ test/CodeGen/arm64-microsoft-intrinsics.c
@@ -24,3 +24,38 @@
 
 // CHECK-MSVC: @llvm.aarch64.isb(i32 0)
 // CHECK-LINUX: error: implicit declaration of function '__isb'
+
+void check__yield(void) {
+  __yield();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 1)
+// CHECK-LINUX: error: implicit declaration of function '__yield'
+
+void check__wfe(void) {
+  __wfe();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 2)
+// CHECK-LINUX: error: implicit declaration of function '__wfe'
+
+void check__wfi(void) {
+  __wfi();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 3)
+// CHECK-LINUX: error: implicit declaration of function '__wfi'
+
+void check__sev(void) {
+  __sev();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 4)
+// CHECK-LINUX: error: implicit declaration of function '__sev'
+
+void check__sevl(void) {
+  __sevl();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 5)
+// CHECK-LINUX: error: implicit declaration of function '__sevl'
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -6362,18 +6362,23 @@
 HintID = 0;
 break;
   case AArch64::BI__builtin_arm_yield:
+  case AArch64::BI__yield:
 HintID = 1;
 break;
   case AArch64::BI__builtin_arm_wfe:
+  case AArch64::BI__wfe:
 HintID = 2;
 break;
   case AArch64::BI__builtin_arm_wfi:
+  case AArch64::BI__wfi:
 HintID = 3;
 break;
   case AArch64::BI__builtin_arm_sev:
+  case AArch64::BI__sev:
 HintID = 4;
 break;
   case AArch64::BI__builtin_arm_sevl:
+  case AArch64::BI__sevl:
 HintID = 5;
 break;
   }
Index: include/clang/Basic/BuiltinsAArch64.def

[PATCH] D48132: [COFF] Add ARM64 intrinsics: __yield, __wfe, __wfi, __sev, __sevl

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL334639: [COFF] Add ARM64 intrinsics: __yield, __wfe, __wfi, 
__sev, __sevl (authored by mgrang, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D48132?vs=151186&id=151218#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D48132

Files:
  cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
  cfe/trunk/lib/CodeGen/CGBuiltin.cpp
  cfe/trunk/test/CodeGen/arm64-microsoft-intrinsics.c


Index: cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
===
--- cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
+++ cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
@@ -65,9 +65,15 @@
 BUILTIN(__builtin_arm_wsr64, "vcC*LUi", "nc")
 BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
 
+// MSVC
 LANGBUILTIN(__dmb, "vUi", "nc", ALL_MS_LANGUAGES)
 LANGBUILTIN(__dsb, "vUi", "nc", ALL_MS_LANGUAGES)
 LANGBUILTIN(__isb, "vUi", "nc", ALL_MS_LANGUAGES)
+LANGBUILTIN(__yield, "v", "",   ALL_MS_LANGUAGES)
+LANGBUILTIN(__wfe,   "v", "",   ALL_MS_LANGUAGES)
+LANGBUILTIN(__wfi,   "v", "",   ALL_MS_LANGUAGES)
+LANGBUILTIN(__sev,   "v", "",   ALL_MS_LANGUAGES)
+LANGBUILTIN(__sevl,  "v", "",   ALL_MS_LANGUAGES)
 
 // MSVC intrinsics for volatile but non-acquire/release loads and stores
 LANGBUILTIN(__iso_volatile_load8,   "ccCD*", "n", ALL_MS_LANGUAGES)
Index: cfe/trunk/test/CodeGen/arm64-microsoft-intrinsics.c
===
--- cfe/trunk/test/CodeGen/arm64-microsoft-intrinsics.c
+++ cfe/trunk/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -24,3 +24,38 @@
 
 // CHECK-MSVC: @llvm.aarch64.isb(i32 0)
 // CHECK-LINUX: error: implicit declaration of function '__isb'
+
+void check__yield(void) {
+  __yield();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 1)
+// CHECK-LINUX: error: implicit declaration of function '__yield'
+
+void check__wfe(void) {
+  __wfe();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 2)
+// CHECK-LINUX: error: implicit declaration of function '__wfe'
+
+void check__wfi(void) {
+  __wfi();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 3)
+// CHECK-LINUX: error: implicit declaration of function '__wfi'
+
+void check__sev(void) {
+  __sev();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 4)
+// CHECK-LINUX: error: implicit declaration of function '__sev'
+
+void check__sevl(void) {
+  __sevl();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 5)
+// CHECK-LINUX: error: implicit declaration of function '__sevl'
Index: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
===
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp
@@ -6362,18 +6362,23 @@
 HintID = 0;
 break;
   case AArch64::BI__builtin_arm_yield:
+  case AArch64::BI__yield:
 HintID = 1;
 break;
   case AArch64::BI__builtin_arm_wfe:
+  case AArch64::BI__wfe:
 HintID = 2;
 break;
   case AArch64::BI__builtin_arm_wfi:
+  case AArch64::BI__wfi:
 HintID = 3;
 break;
   case AArch64::BI__builtin_arm_sev:
+  case AArch64::BI__sev:
 HintID = 4;
 break;
   case AArch64::BI__builtin_arm_sevl:
+  case AArch64::BI__sevl:
 HintID = 5;
 break;
   }


Index: cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
===
--- cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
+++ cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
@@ -65,9 +65,15 @@
 BUILTIN(__builtin_arm_wsr64, "vcC*LUi", "nc")
 BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
 
+// MSVC
 LANGBUILTIN(__dmb, "vUi", "nc", ALL_MS_LANGUAGES)
 LANGBUILTIN(__dsb, "vUi", "nc", ALL_MS_LANGUAGES)
 LANGBUILTIN(__isb, "vUi", "nc", ALL_MS_LANGUAGES)
+LANGBUILTIN(__yield, "v", "",   ALL_MS_LANGUAGES)
+LANGBUILTIN(__wfe,   "v", "",   ALL_MS_LANGUAGES)
+LANGBUILTIN(__wfi,   "v", "",   ALL_MS_LANGUAGES)
+LANGBUILTIN(__sev,   "v", "",   ALL_MS_LANGUAGES)
+LANGBUILTIN(__sevl,  "v", "",   ALL_MS_LANGUAGES)
 
 // MSVC intrinsics for volatile but non-acquire/release loads and stores
 LANGBUILTIN(__iso_volatile_load8,   "ccCD*", "n", ALL_MS_LANGUAGES)
Index: cfe/trunk/test/CodeGen/arm64-microsoft-intrinsics.c
===
--- cfe/trunk/test/CodeGen/arm64-microsoft-intrinsics.c
+++ cfe/trunk/test/CodeGen/arm64-microsoft-intrinsics.c
@@ -24,3 +24,38 @@
 
 // CHECK-MSVC: @llvm.aarch64.isb(i32 0)
 // CHECK-LINUX: error: implicit declaration of function '__isb'
+
+void check__yield(void) {
+  __yield();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 1)
+// CHECK-LINUX: error: implicit declaration of function '__yield'
+
+void check__wfe(void) {
+  __wfe();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 2)
+// CHECK-LINUX: error: implicit declaration of function '__wfe'
+
+void check__wfi(void) {
+  __wfi();
+}
+
+// CHECK-MSVC: @llvm.aarch64.hint(i32 3)
+// CHECK-LINUX: erro

[PATCH] D53115: [COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, compnerd, mstorsjo, efriedma, TomTan, haripul.
Herald added a reviewer: javed.absar.
Herald added subscribers: chrib, kristof.beyls.

Repository:
  rC Clang

https://reviews.llvm.org/D53115

Files:
  include/clang/Basic/BuiltinsAArch64.def
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/intrin.h
  test/CodeGen/arm64-microsoft-status-reg.cpp

Index: test/CodeGen/arm64-microsoft-status-reg.cpp
===
--- /dev/null
+++ test/CodeGen/arm64-microsoft-status-reg.cpp
@@ -0,0 +1,117 @@
+// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm -S \
+// RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM
+
+// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm \
+// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR
+
+// From winnt.h
+#define ARM64_SYSREG(op0, op1, crn, crm, op2) \
+( ((op0 & 1) << 14) | \
+  ((op1 & 7) << 11) | \
+  ((crn & 15) << 7) | \
+  ((crm & 15) << 3) | \
+  ((op2 & 7) << 0) )
+
+#define ARM64_CNTVCTARM64_SYSREG(3,3,14, 0,2)  // Generic Timer counter register
+#define ARM64_PMCCNTR_EL0   ARM64_SYSREG(3,3, 9,13,0)  // Cycle Count Register [CP15_PMCCNTR]
+#define ARM64_PMSELR_EL0ARM64_SYSREG(3,3, 9,12,5)  // Event Counter Selection Register [CP15_PMSELR]
+#define ARM64_PMXEVCNTR_EL0 ARM64_SYSREG(3,3, 9,13,2)  // Event Count Register [CP15_PMXEVCNTR]
+#define ARM64_PMXEVCNTRn_EL0(n) ARM64_SYSREG(3,3,14, 8+((n)/8), (n)%8)// Direct Event Count Register [n/a]
+#define ARM64_TPIDR_EL0 ARM64_SYSREG(3,3,13, 0,2)  // Thread ID Register, User Read/Write [CP15_TPIDRURW]
+#define ARM64_TPIDRRO_EL0   ARM64_SYSREG(3,3,13, 0,3)  // Thread ID Register, User Read Only [CP15_TPIDRURO]
+#define ARM64_TPIDR_EL1 ARM64_SYSREG(3,0,13, 0,4)  // Thread ID Register, Privileged Only [CP15_TPIDRPRW]
+
+void check_ReadWriteStatusReg(int v) {
+  int ret;
+  ret = _ReadStatusReg(ARM64_CNTVCT);
+// CHECK-ASM: mrs x8, CNTVCT_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMCCNTR_EL0);
+// CHECK-ASM: mrs x8, PMCCNTR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMSELR_EL0);
+// CHECK-ASM: mrs x8, PMSELR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD4:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTR_EL0);
+// CHECK-ASM: mrs x8, PMXEVCNTR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD5:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(0));
+// CHECK-ASM: mrs x8, PMEVCNTR0_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD6:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(1));
+// CHECK-ASM: mrs x8, PMEVCNTR1_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD7:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(30));
+// CHECK-ASM: mrs x8, PMEVCNTR30_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD8:.*]])
+
+  ret = _ReadStatusReg(ARM64_TPIDR_EL0);
+// CHECK-ASM: mrs x8, TPIDR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD9:.*]])
+
+  ret = _ReadStatusReg(ARM64_TPIDRRO_EL0);
+// CHECK-ASM: mrs x8, TPIDRRO_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD10:.*]])
+
+  ret = _ReadStatusReg(ARM64_TPIDR_EL1);
+// CHECK-ASM: mrs x8, TPIDR_EL1
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD11:.*]])
+
+
+  _WriteStatusReg(ARM64_CNTVCT, v);
+// CHECK-ASM: msr S3_3_C14_C0_2, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMCCNTR_EL0, v);
+// CHECK-ASM: msr PMCCNTR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMSELR_EL0, v);
+// CHECK-ASM: msr PMSELR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTR_EL0, v);
+// CHECK-ASM: msr PMXEVCNTR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(0), v);
+// CHECK-ASM: msr PMEVCNTR0_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(1), v);
+// CHECK-ASM: msr PMEVCNTR1_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD7:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(30), v);
+// CHECK-ASM: msr PMEVCNTR30_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD8:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_TPIDR_EL0, v);
+// CHECK-ASM: msr TPIDR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD9:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_TPIDRRO_EL0, v);
+// CHECK-ASM: msr TPIDRRO_EL0, 

[PATCH] D53115: [COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

_ReadStatusReg and _WriteStatusReg intrinsics take ARM64_REGNO as input. These 
are defined in https://www.codemachine.com/downloads/win10/winnt.h.
LLVM already has intrinsics to read/write status regs: 
__builtin_arm_rsr/__builtin_arm_wsr. But these take the string concatenation of 
the byte repesentation of a register (like "1:2:3:4:5"). So I convert 
ARM64_REGNO to this string format and invoke read_register/write_register 
intrinsics.


Repository:
  rC Clang

https://reviews.llvm.org/D53115



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[PATCH] D53115: [COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added inline comments.



Comment at: test/CodeGen/arm64-microsoft-status-reg.cpp:1
+// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm -S \
+// RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM

I had to create a new test file here as the existing file 
arm64-microsoft-intrinsics.cpp has a check for metadata and it seems I cannot 
have 2 different tests checking different metadata in the same test file.

If I understand correctly, when trying to match the metadata for one test the 
lit parser reaches the end of the generated IR and then cannot go up again to 
match the other checks.


Repository:
  rC Clang

https://reviews.llvm.org/D53115



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[PATCH] D53115: [COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 169127.

https://reviews.llvm.org/D53115

Files:
  include/clang/Basic/BuiltinsAArch64.def
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/intrin.h
  lib/Sema/SemaChecking.cpp
  test/CodeGen/arm64-microsoft-status-reg.cpp
  test/Sema/builtins-microsoft-arm64.c

Index: test/Sema/builtins-microsoft-arm64.c
===
--- test/Sema/builtins-microsoft-arm64.c
+++ test/Sema/builtins-microsoft-arm64.c
@@ -7,3 +7,9 @@
   __getReg(-1); // expected-error-re {{argument value {{.*}} is outside the valid range}}
   __getReg(32); // expected-error-re {{argument value {{.*}} is outside the valid range}}
 }
+
+void check_ReadWriteStatusReg(int v) {
+  int x;
+  _ReadStatusReg(x); // expected-error {{argument to '_ReadStatusReg' must be a constant integer}}
+  _WriteStatusReg(x, v); // expected-error {{argument to '_WriteStatusReg' must be a constant integer}}
+}
Index: test/CodeGen/arm64-microsoft-status-reg.cpp
===
--- /dev/null
+++ test/CodeGen/arm64-microsoft-status-reg.cpp
@@ -0,0 +1,117 @@
+// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm -S \
+// RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM
+
+// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm \
+// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR
+
+// From winnt.h
+#define ARM64_SYSREG(op0, op1, crn, crm, op2) \
+( ((op0 & 1) << 14) | \
+  ((op1 & 7) << 11) | \
+  ((crn & 15) << 7) | \
+  ((crm & 15) << 3) | \
+  ((op2 & 7) << 0) )
+
+#define ARM64_CNTVCTARM64_SYSREG(3,3,14, 0,2)  // Generic Timer counter register
+#define ARM64_PMCCNTR_EL0   ARM64_SYSREG(3,3, 9,13,0)  // Cycle Count Register [CP15_PMCCNTR]
+#define ARM64_PMSELR_EL0ARM64_SYSREG(3,3, 9,12,5)  // Event Counter Selection Register [CP15_PMSELR]
+#define ARM64_PMXEVCNTR_EL0 ARM64_SYSREG(3,3, 9,13,2)  // Event Count Register [CP15_PMXEVCNTR]
+#define ARM64_PMXEVCNTRn_EL0(n) ARM64_SYSREG(3,3,14, 8+((n)/8), (n)%8)// Direct Event Count Register [n/a]
+#define ARM64_TPIDR_EL0 ARM64_SYSREG(3,3,13, 0,2)  // Thread ID Register, User Read/Write [CP15_TPIDRURW]
+#define ARM64_TPIDRRO_EL0   ARM64_SYSREG(3,3,13, 0,3)  // Thread ID Register, User Read Only [CP15_TPIDRURO]
+#define ARM64_TPIDR_EL1 ARM64_SYSREG(3,0,13, 0,4)  // Thread ID Register, Privileged Only [CP15_TPIDRPRW]
+
+void check_ReadWriteStatusReg(int v) {
+  int ret;
+  ret = _ReadStatusReg(ARM64_CNTVCT);
+// CHECK-ASM: mrs x8, CNTVCT_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMCCNTR_EL0);
+// CHECK-ASM: mrs x8, PMCCNTR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMSELR_EL0);
+// CHECK-ASM: mrs x8, PMSELR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD4:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTR_EL0);
+// CHECK-ASM: mrs x8, PMXEVCNTR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD5:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(0));
+// CHECK-ASM: mrs x8, PMEVCNTR0_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD6:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(1));
+// CHECK-ASM: mrs x8, PMEVCNTR1_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD7:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(30));
+// CHECK-ASM: mrs x8, PMEVCNTR30_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD8:.*]])
+
+  ret = _ReadStatusReg(ARM64_TPIDR_EL0);
+// CHECK-ASM: mrs x8, TPIDR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD9:.*]])
+
+  ret = _ReadStatusReg(ARM64_TPIDRRO_EL0);
+// CHECK-ASM: mrs x8, TPIDRRO_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD10:.*]])
+
+  ret = _ReadStatusReg(ARM64_TPIDR_EL1);
+// CHECK-ASM: mrs x8, TPIDR_EL1
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD11:.*]])
+
+
+  _WriteStatusReg(ARM64_CNTVCT, v);
+// CHECK-ASM: msr S3_3_C14_C0_2, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMCCNTR_EL0, v);
+// CHECK-ASM: msr PMCCNTR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMSELR_EL0, v);
+// CHECK-ASM: msr PMSELR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTR_EL0, v);
+// CHECK-ASM: msr PMXEVCNTR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(0), v);
+// CHECK-ASM: msr PMEVCNTR0_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(1)

[PATCH] D53115: [COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 170133.

https://reviews.llvm.org/D53115

Files:
  include/clang/Basic/BuiltinsAArch64.def
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/intrin.h
  lib/Sema/SemaChecking.cpp
  test/CodeGen/arm64-microsoft-status-reg.cpp
  test/Sema/builtins-microsoft-arm64.c

Index: test/Sema/builtins-microsoft-arm64.c
===
--- test/Sema/builtins-microsoft-arm64.c
+++ test/Sema/builtins-microsoft-arm64.c
@@ -7,3 +7,9 @@
   __getReg(-1); // expected-error-re {{argument value {{.*}} is outside the valid range}}
   __getReg(32); // expected-error-re {{argument value {{.*}} is outside the valid range}}
 }
+
+void check_ReadWriteStatusReg(int v) {
+  int x;
+  _ReadStatusReg(x); // expected-error {{argument to '_ReadStatusReg' must be a constant integer}}
+  _WriteStatusReg(x, v); // expected-error {{argument to '_WriteStatusReg' must be a constant integer}}
+}
Index: test/CodeGen/arm64-microsoft-status-reg.cpp
===
--- /dev/null
+++ test/CodeGen/arm64-microsoft-status-reg.cpp
@@ -0,0 +1,117 @@
+// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm -S \
+// RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM
+
+// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm \
+// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR
+
+// From winnt.h
+#define ARM64_SYSREG(op0, op1, crn, crm, op2) \
+( ((op0 & 1) << 14) | \
+  ((op1 & 7) << 11) | \
+  ((crn & 15) << 7) | \
+  ((crm & 15) << 3) | \
+  ((op2 & 7) << 0) )
+
+#define ARM64_CNTVCTARM64_SYSREG(3,3,14, 0,2)  // Generic Timer counter register
+#define ARM64_PMCCNTR_EL0   ARM64_SYSREG(3,3, 9,13,0)  // Cycle Count Register [CP15_PMCCNTR]
+#define ARM64_PMSELR_EL0ARM64_SYSREG(3,3, 9,12,5)  // Event Counter Selection Register [CP15_PMSELR]
+#define ARM64_PMXEVCNTR_EL0 ARM64_SYSREG(3,3, 9,13,2)  // Event Count Register [CP15_PMXEVCNTR]
+#define ARM64_PMXEVCNTRn_EL0(n) ARM64_SYSREG(3,3,14, 8+((n)/8), (n)%8)// Direct Event Count Register [n/a]
+#define ARM64_TPIDR_EL0 ARM64_SYSREG(3,3,13, 0,2)  // Thread ID Register, User Read/Write [CP15_TPIDRURW]
+#define ARM64_TPIDRRO_EL0   ARM64_SYSREG(3,3,13, 0,3)  // Thread ID Register, User Read Only [CP15_TPIDRURO]
+#define ARM64_TPIDR_EL1 ARM64_SYSREG(3,0,13, 0,4)  // Thread ID Register, Privileged Only [CP15_TPIDRPRW]
+
+void check_ReadWriteStatusReg(int v) {
+  int ret;
+  ret = _ReadStatusReg(ARM64_CNTVCT);
+// CHECK-ASM: mrs x8, CNTVCT_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMCCNTR_EL0);
+// CHECK-ASM: mrs x8, PMCCNTR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMSELR_EL0);
+// CHECK-ASM: mrs x8, PMSELR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD4:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTR_EL0);
+// CHECK-ASM: mrs x8, PMXEVCNTR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD5:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(0));
+// CHECK-ASM: mrs x8, PMEVCNTR0_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD6:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(1));
+// CHECK-ASM: mrs x8, PMEVCNTR1_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD7:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(30));
+// CHECK-ASM: mrs x8, PMEVCNTR30_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD8:.*]])
+
+  ret = _ReadStatusReg(ARM64_TPIDR_EL0);
+// CHECK-ASM: mrs x8, TPIDR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD9:.*]])
+
+  ret = _ReadStatusReg(ARM64_TPIDRRO_EL0);
+// CHECK-ASM: mrs x8, TPIDRRO_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD10:.*]])
+
+  ret = _ReadStatusReg(ARM64_TPIDR_EL1);
+// CHECK-ASM: mrs x8, TPIDR_EL1
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD11:.*]])
+
+
+  _WriteStatusReg(ARM64_CNTVCT, v);
+// CHECK-ASM: msr S3_3_C14_C0_2, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMCCNTR_EL0, v);
+// CHECK-ASM: msr PMCCNTR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMSELR_EL0, v);
+// CHECK-ASM: msr PMSELR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTR_EL0, v);
+// CHECK-ASM: msr PMXEVCNTR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(0), v);
+// CHECK-ASM: msr PMEVCNTR0_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(1)

[PATCH] D53115: [COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg intrinsics

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC344765: [COFF, ARM64] Add _ReadStatusReg and_WriteStatusReg 
intrinsics (authored by mgrang, committed by ).

Repository:
  rC Clang

https://reviews.llvm.org/D53115

Files:
  include/clang/Basic/BuiltinsAArch64.def
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/intrin.h
  lib/Sema/SemaChecking.cpp
  test/CodeGen/arm64-microsoft-status-reg.cpp
  test/Sema/builtins-microsoft-arm64.c

Index: test/CodeGen/arm64-microsoft-status-reg.cpp
===
--- test/CodeGen/arm64-microsoft-status-reg.cpp
+++ test/CodeGen/arm64-microsoft-status-reg.cpp
@@ -0,0 +1,117 @@
+// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm -S \
+// RUN: -o - %s | FileCheck %s -check-prefix CHECK-ASM
+
+// RUN: %clang_cc1 -triple arm64-windows -fms-compatibility -emit-llvm \
+// RUN: -o - %s | FileCheck %s -check-prefix CHECK-IR
+
+// From winnt.h
+#define ARM64_SYSREG(op0, op1, crn, crm, op2) \
+( ((op0 & 1) << 14) | \
+  ((op1 & 7) << 11) | \
+  ((crn & 15) << 7) | \
+  ((crm & 15) << 3) | \
+  ((op2 & 7) << 0) )
+
+#define ARM64_CNTVCTARM64_SYSREG(3,3,14, 0,2)  // Generic Timer counter register
+#define ARM64_PMCCNTR_EL0   ARM64_SYSREG(3,3, 9,13,0)  // Cycle Count Register [CP15_PMCCNTR]
+#define ARM64_PMSELR_EL0ARM64_SYSREG(3,3, 9,12,5)  // Event Counter Selection Register [CP15_PMSELR]
+#define ARM64_PMXEVCNTR_EL0 ARM64_SYSREG(3,3, 9,13,2)  // Event Count Register [CP15_PMXEVCNTR]
+#define ARM64_PMXEVCNTRn_EL0(n) ARM64_SYSREG(3,3,14, 8+((n)/8), (n)%8)// Direct Event Count Register [n/a]
+#define ARM64_TPIDR_EL0 ARM64_SYSREG(3,3,13, 0,2)  // Thread ID Register, User Read/Write [CP15_TPIDRURW]
+#define ARM64_TPIDRRO_EL0   ARM64_SYSREG(3,3,13, 0,3)  // Thread ID Register, User Read Only [CP15_TPIDRURO]
+#define ARM64_TPIDR_EL1 ARM64_SYSREG(3,0,13, 0,4)  // Thread ID Register, Privileged Only [CP15_TPIDRPRW]
+
+void check_ReadWriteStatusReg(int v) {
+  int ret;
+  ret = _ReadStatusReg(ARM64_CNTVCT);
+// CHECK-ASM: mrs x8, CNTVCT_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMCCNTR_EL0);
+// CHECK-ASM: mrs x8, PMCCNTR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMSELR_EL0);
+// CHECK-ASM: mrs x8, PMSELR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD4:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTR_EL0);
+// CHECK-ASM: mrs x8, PMXEVCNTR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD5:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(0));
+// CHECK-ASM: mrs x8, PMEVCNTR0_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD6:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(1));
+// CHECK-ASM: mrs x8, PMEVCNTR1_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD7:.*]])
+
+  ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(30));
+// CHECK-ASM: mrs x8, PMEVCNTR30_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD8:.*]])
+
+  ret = _ReadStatusReg(ARM64_TPIDR_EL0);
+// CHECK-ASM: mrs x8, TPIDR_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD9:.*]])
+
+  ret = _ReadStatusReg(ARM64_TPIDRRO_EL0);
+// CHECK-ASM: mrs x8, TPIDRRO_EL0
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD10:.*]])
+
+  ret = _ReadStatusReg(ARM64_TPIDR_EL1);
+// CHECK-ASM: mrs x8, TPIDR_EL1
+// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD11:.*]])
+
+
+  _WriteStatusReg(ARM64_CNTVCT, v);
+// CHECK-ASM: msr S3_3_C14_C0_2, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMCCNTR_EL0, v);
+// CHECK-ASM: msr PMCCNTR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMSELR_EL0, v);
+// CHECK-ASM: msr PMSELR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTR_EL0, v);
+// CHECK-ASM: msr PMXEVCNTR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(0), v);
+// CHECK-ASM: msr PMEVCNTR0_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(1), v);
+// CHECK-ASM: msr PMEVCNTR1_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD7:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_PMXEVCNTRn_EL0(30), v);
+// CHECK-ASM: msr PMEVCNTR30_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD8:.*]], i64 {{%.*}})
+
+  _WriteStatusReg(ARM64_TPIDR_EL0, v);
+// CHECK-ASM: msr TPIDR_EL0, x8
+// CHECK-IR: call void @llvm.write_register.i64(meta

[PATCH] D53541: [COFF, ARM64] Add aarch64_seh_recoverfp intrinsic

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, compnerd, mstorsjo, TomTan, efriedma.
Herald added subscribers: chrib, kristof.beyls, javed.absar.

This patch mimics X86 behavior and add aarch64_seh_recoverfp similar to 
x86_seh_recoverfp.
This patch is needed by https://reviews.llvm.org/D53540.


Repository:
  rC Clang

https://reviews.llvm.org/D53541

Files:
  lib/CodeGen/CGException.cpp
  test/CodeGen/exceptions-seh.c


Index: test/CodeGen/exceptions-seh.c
===
--- test/CodeGen/exceptions-seh.c
+++ test/CodeGen/exceptions-seh.c
@@ -99,7 +99,7 @@
 // X64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture 
to i8*), i8* %[[fp]], i32 0)
 //
 // ARM64-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"(i8* 
%exception_pointers, i8* %frame_pointer)
-// ARM64: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 
()* @filter_expr_capture to i8*), i8* %frame_pointer)
+// ARM64: %[[fp:[^ ]*]] = call i8* @llvm.aarch64.seh.recoverfp(i8* bitcast 
(i32 ()* @filter_expr_capture to i8*), i8* %frame_pointer)
 // ARM64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %[[fp]], i32 0)
 //
 // X86-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"()
Index: lib/CodeGen/CGException.cpp
===
--- lib/CodeGen/CGException.cpp
+++ lib/CodeGen/CGException.cpp
@@ -1777,6 +1777,8 @@
 // frame pointer of the parent function. We only need to do this in 
filters,
 // since finally funclets recover the parent FP for us.
 llvm::Function *RecoverFPIntrin =
+CGM.getTarget().getTriple().getArch() == llvm::Triple::aarch64 ?
+CGM.getIntrinsic(llvm::Intrinsic::aarch64_seh_recoverfp) :
 CGM.getIntrinsic(llvm::Intrinsic::x86_seh_recoverfp);
 llvm::Constant *ParentI8Fn =
 llvm::ConstantExpr::getBitCast(ParentCGF.CurFn, Int8PtrTy);


Index: test/CodeGen/exceptions-seh.c
===
--- test/CodeGen/exceptions-seh.c
+++ test/CodeGen/exceptions-seh.c
@@ -99,7 +99,7 @@
 // X64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %[[fp]], i32 0)
 //
 // ARM64-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"(i8* %exception_pointers, i8* %frame_pointer)
-// ARM64: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %frame_pointer)
+// ARM64: %[[fp:[^ ]*]] = call i8* @llvm.aarch64.seh.recoverfp(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %frame_pointer)
 // ARM64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %[[fp]], i32 0)
 //
 // X86-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"()
Index: lib/CodeGen/CGException.cpp
===
--- lib/CodeGen/CGException.cpp
+++ lib/CodeGen/CGException.cpp
@@ -1777,6 +1777,8 @@
 // frame pointer of the parent function. We only need to do this in filters,
 // since finally funclets recover the parent FP for us.
 llvm::Function *RecoverFPIntrin =
+CGM.getTarget().getTriple().getArch() == llvm::Triple::aarch64 ?
+CGM.getIntrinsic(llvm::Intrinsic::aarch64_seh_recoverfp) :
 CGM.getIntrinsic(llvm::Intrinsic::x86_seh_recoverfp);
 llvm::Constant *ParentI8Fn =
 llvm::ConstantExpr::getBitCast(ParentCGF.CurFn, Int8PtrTy);
___
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[PATCH] D56463: [SEH] Pass the frame pointer from SEH finally to finally functions

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added inline comments.



Comment at: lib/CodeGen/CGException.cpp:1635
+else {
+  llvm::Value *LocalAddrFn = 
CGM.getIntrinsic(llvm::Intrinsic::localaddress);
+  FP = CGF.Builder.CreateCall(LocalAddrFn);

80 char limit.


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56463/new/

https://reviews.llvm.org/D56463



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[PATCH] D53541: [COFF, ARM64] Do not emit x86_seh_recoverfp intrinsic

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 181333.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D53541/new/

https://reviews.llvm.org/D53541

Files:
  lib/CodeGen/CGException.cpp
  test/CodeGen/exceptions-seh.c


Index: test/CodeGen/exceptions-seh.c
===
--- test/CodeGen/exceptions-seh.c
+++ test/CodeGen/exceptions-seh.c
@@ -99,8 +99,7 @@
 // X64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture 
to i8*), i8* %[[fp]], i32 0)
 //
 // ARM64-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"(i8* 
%exception_pointers, i8* %frame_pointer)
-// ARM64: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 
()* @filter_expr_capture to i8*), i8* %frame_pointer)
-// ARM64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %[[fp]], i32 0)
+// ARM64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %frame_pointer, i32 0)
 //
 // X86-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"()
 // X86: %[[ebp:[^ ]*]] = call i8* @llvm.frameaddress(i32 1)
Index: lib/CodeGen/CGException.cpp
===
--- lib/CodeGen/CGException.cpp
+++ lib/CodeGen/CGException.cpp
@@ -1783,7 +1783,8 @@
   }
 
   llvm::Value *ParentFP = EntryFP;
-  if (IsFilter) {
+  if (IsFilter &&
+  CGM.getTarget().getTriple().getArch() != llvm::Triple::aarch64) {
 // Given whatever FP the runtime provided us in EntryFP, recover the true
 // frame pointer of the parent function. We only need to do this in 
filters,
 // since finally funclets recover the parent FP for us.


Index: test/CodeGen/exceptions-seh.c
===
--- test/CodeGen/exceptions-seh.c
+++ test/CodeGen/exceptions-seh.c
@@ -99,8 +99,7 @@
 // X64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %[[fp]], i32 0)
 //
 // ARM64-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"(i8* %exception_pointers, i8* %frame_pointer)
-// ARM64: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %frame_pointer)
-// ARM64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %[[fp]], i32 0)
+// ARM64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %frame_pointer, i32 0)
 //
 // X86-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"()
 // X86: %[[ebp:[^ ]*]] = call i8* @llvm.frameaddress(i32 1)
Index: lib/CodeGen/CGException.cpp
===
--- lib/CodeGen/CGException.cpp
+++ lib/CodeGen/CGException.cpp
@@ -1783,7 +1783,8 @@
   }
 
   llvm::Value *ParentFP = EntryFP;
-  if (IsFilter) {
+  if (IsFilter &&
+  CGM.getTarget().getTriple().getArch() != llvm::Triple::aarch64) {
 // Given whatever FP the runtime provided us in EntryFP, recover the true
 // frame pointer of the parent function. We only need to do this in filters,
 // since finally funclets recover the parent FP for us.
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[PATCH] D56620: [COFF, ARM64] Include stdlib.h in arm64intr.h

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, efriedma, ssijaric, TomTan, haripul.
Herald added subscribers: kristof.beyls, javed.absar.

We mimic x86 behavior which includes stdlib.h in x86intr.h.


Repository:
  rC Clang

https://reviews.llvm.org/D56620

Files:
  lib/Headers/arm64intr.h


Index: lib/Headers/arm64intr.h
===
--- lib/Headers/arm64intr.h
+++ lib/Headers/arm64intr.h
@@ -26,6 +26,10 @@
 #include_next 
 #else
 
+#if __STDC_HOSTED__
+#include 
+#endif
+
 #ifndef __ARM64INTR_H
 #define __ARM64INTR_H
 


Index: lib/Headers/arm64intr.h
===
--- lib/Headers/arm64intr.h
+++ lib/Headers/arm64intr.h
@@ -26,6 +26,10 @@
 #include_next 
 #else
 
+#if __STDC_HOSTED__
+#include 
+#endif
+
 #ifndef __ARM64INTR_H
 #define __ARM64INTR_H
 
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[PATCH] D56620: [COFF, ARM64] Include stdlib.h in arm64intr.h

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

In D56620#1354979 , @efriedma wrote:

> Have you verified this matches MSVC?  (IIRC the only reason we include 
> stdlib.h on x86 is so we can define _mm_malloc.)


I don't see MSVC intrin.h including stdlib.h. So I guess I will just declare 
the required intrinsics.


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[PATCH] D56620: [COFF, ARM64] Declare intrinsics: __nop, _byteswap_[short/long/uint64]

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 181390.
mgrang retitled this revision from "[COFF, ARM64] Include stdlib.h in 
arm64intr.h" to "[COFF, ARM64] Declare intrinsics: __nop, 
_byteswap_[short/long/uint64]".
mgrang edited the summary of this revision.

CHANGES SINCE LAST ACTION
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Files:
  lib/Headers/intrin.h


Index: lib/Headers/intrin.h
===
--- lib/Headers/intrin.h
+++ lib/Headers/intrin.h
@@ -563,6 +563,10 @@
 long _InterlockedAdd(long volatile *Addend, long Value);
 int _ReadStatusReg(int);
 void _WriteStatusReg(int, int);
+unsigned short _byteswap_ushort (unsigned short val);
+unsigned long _byteswap_ulong (unsigned long val);
+unsigned __int64 _byteswap_uint64 (unsigned __int64 val);
+void __nop();
 #endif
 
 
/**\


Index: lib/Headers/intrin.h
===
--- lib/Headers/intrin.h
+++ lib/Headers/intrin.h
@@ -563,6 +563,10 @@
 long _InterlockedAdd(long volatile *Addend, long Value);
 int _ReadStatusReg(int);
 void _WriteStatusReg(int, int);
+unsigned short _byteswap_ushort (unsigned short val);
+unsigned long _byteswap_ulong (unsigned long val);
+unsigned __int64 _byteswap_uint64 (unsigned __int64 val);
+void __nop();
 #endif
 
 /**\
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[PATCH] D56620: [COFF, ARM64] Declare intrinsics: __nop, _byteswap_[ushort/ulong/uint64]

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

I have implemented __nop intrinsics in https://reviews.llvm.org/D56620


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[PATCH] D56671: [COFF, ARM64] Add __nop intrinsic

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, efriedma, TomTan, haripul, ssijaric.
Herald added subscribers: kristof.beyls, javed.absar.

Repository:
  rC Clang

https://reviews.llvm.org/D56671

Files:
  lib/Headers/intrin.h
  test/Headers/ms-arm64-intrin.cpp


Index: test/Headers/ms-arm64-intrin.cpp
===
--- /dev/null
+++ test/Headers/ms-arm64-intrin.cpp
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -triple arm64-windows \
+// RUN: -fms-compatibility -fms-compatibility-version=17.00 \
+// RUN: -ffreestanding -fsyntax-only -Werror \
+// RUN: -isystem %S/Inputs/include %s -S -o - 2>&1 | FileCheck %s
+
+// REQUIRES: aarch64-registered-target
+
+#include 
+
+void f() {
+// CHECK: nop
+  __nop();
+}
Index: lib/Headers/intrin.h
===
--- lib/Headers/intrin.h
+++ lib/Headers/intrin.h
@@ -549,6 +549,9 @@
 __halt(void) {
   __asm__ volatile ("hlt");
 }
+#endif
+
+#if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__)
 static __inline__ void __DEFAULT_FN_ATTRS
 __nop(void) {
   __asm__ volatile ("nop");


Index: test/Headers/ms-arm64-intrin.cpp
===
--- /dev/null
+++ test/Headers/ms-arm64-intrin.cpp
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -triple arm64-windows \
+// RUN: -fms-compatibility -fms-compatibility-version=17.00 \
+// RUN: -ffreestanding -fsyntax-only -Werror \
+// RUN: -isystem %S/Inputs/include %s -S -o - 2>&1 | FileCheck %s
+
+// REQUIRES: aarch64-registered-target
+
+#include 
+
+void f() {
+// CHECK: nop
+  __nop();
+}
Index: lib/Headers/intrin.h
===
--- lib/Headers/intrin.h
+++ lib/Headers/intrin.h
@@ -549,6 +549,9 @@
 __halt(void) {
   __asm__ volatile ("hlt");
 }
+#endif
+
+#if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__)
 static __inline__ void __DEFAULT_FN_ATTRS
 __nop(void) {
   __asm__ volatile ("nop");
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[PATCH] D56685: [COFF, ARM64] Declare __byteswap intrinsics

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, efriedma, ssijaric, TomTan, haripul.
Herald added subscribers: kristof.beyls, javed.absar.

Repository:
  rC Clang

https://reviews.llvm.org/D56685

Files:
  lib/Headers/arm64intr.h
  test/Headers/ms-arm64-intrin.cpp


Index: test/Headers/ms-arm64-intrin.cpp
===
--- test/Headers/ms-arm64-intrin.cpp
+++ test/Headers/ms-arm64-intrin.cpp
@@ -3,6 +3,11 @@
 // RUN: -ffreestanding -fsyntax-only -Werror \
 // RUN: -isystem %S/Inputs/include %s -S -o - 2>&1 | FileCheck %s
 
+// RUN: %clang_cc1 -triple arm64-windows \
+// RUN: -fms-compatibility -fms-compatibility-version=17.00 \
+// RUN: -ffreestanding -fsyntax-only -Werror \
+// RUN: -isystem %S/Inputs/include %s -S -o - -emit-llvm 2>&1 | FileCheck %s 
--check-prefix CHECK-IR
+
 // REQUIRES: aarch64-registered-target
 
 #include 
@@ -11,3 +16,66 @@
 // CHECK: nop
   __nop();
 }
+
+unsigned short check_byteswap_ushort_1() {
+// CHECK-IR: ret i16 256
+  return _byteswap_ushort(1);
+}
+unsigned short check_byteswap_ushort_2() {
+// CHECK-IR: ret i16 512
+  return _byteswap_ushort(2);
+}
+unsigned short check_byteswap_ushort_3() {
+// CHECK-IR: ret i16 768
+  return _byteswap_ushort(3);
+}
+unsigned short check_byteswap_ushort_4() {
+// CHECK-IR: ret i16 1024
+  return _byteswap_ushort(4);
+}
+unsigned short check_byteswap_ushort_5() {
+// CHECK-IR: ret i16 1280
+  return _byteswap_ushort(5);
+}
+
+unsigned long check_byteswap_ulong_1() {
+// CHECK-IR: ret i32 16777216
+  return _byteswap_ulong(1);
+}
+unsigned long check_byteswap_ulong_2() {
+// CHECK-IR: ret i32 33554432
+  return _byteswap_ulong(2);
+}
+unsigned long check_byteswap_ulong_3() {
+// CHECK-IR: ret i32 50331648
+  return _byteswap_ulong(3);
+}
+unsigned long check_byteswap_ulong_4() {
+// CHECK-IR: ret i32 67108864
+  return _byteswap_ulong(4);
+}
+unsigned long check_byteswap_ulong_5() {
+// CHECK-IR: ret i32 83886080
+  return _byteswap_ulong(5);
+}
+
+unsigned __int64 check_byteswap_uint64_1() {
+// CHECK-IR: ret i64 72057594037927936
+  return _byteswap_uint64(1);
+}
+unsigned __int64 check_byteswap_uint64_2() {
+// CHECK-IR: ret i64 144115188075855872
+  return _byteswap_uint64(2);
+}
+unsigned __int64 check_byteswap_uint64_3() {
+// CHECK-IR: ret i64 216172782113783808
+  return _byteswap_uint64(3);
+}
+unsigned __int64 check_byteswap_uint64_4() {
+// CHECK-IR: ret i64 288230376151711744
+  return _byteswap_uint64(4);
+}
+unsigned __int64 check_byteswap_uint64_5() {
+// CHECK-IR: ret i64 360287970189639680
+  return _byteswap_uint64(5);
+}
Index: lib/Headers/arm64intr.h
===
--- lib/Headers/arm64intr.h
+++ lib/Headers/arm64intr.h
@@ -45,5 +45,9 @@
   _ARM64_BARRIER_OSHLD = 0x1
 } _ARM64INTR_BARRIER_TYPE;
 
+#define _byteswap_ushort __builtin_bswap16
+#define _byteswap_ulong  __builtin_bswap32
+#define _byteswap_uint64 __builtin_bswap64
+
 #endif /* __ARM64INTR_H */
 #endif /* _MSC_VER */


Index: test/Headers/ms-arm64-intrin.cpp
===
--- test/Headers/ms-arm64-intrin.cpp
+++ test/Headers/ms-arm64-intrin.cpp
@@ -3,6 +3,11 @@
 // RUN: -ffreestanding -fsyntax-only -Werror \
 // RUN: -isystem %S/Inputs/include %s -S -o - 2>&1 | FileCheck %s
 
+// RUN: %clang_cc1 -triple arm64-windows \
+// RUN: -fms-compatibility -fms-compatibility-version=17.00 \
+// RUN: -ffreestanding -fsyntax-only -Werror \
+// RUN: -isystem %S/Inputs/include %s -S -o - -emit-llvm 2>&1 | FileCheck %s --check-prefix CHECK-IR
+
 // REQUIRES: aarch64-registered-target
 
 #include 
@@ -11,3 +16,66 @@
 // CHECK: nop
   __nop();
 }
+
+unsigned short check_byteswap_ushort_1() {
+// CHECK-IR: ret i16 256
+  return _byteswap_ushort(1);
+}
+unsigned short check_byteswap_ushort_2() {
+// CHECK-IR: ret i16 512
+  return _byteswap_ushort(2);
+}
+unsigned short check_byteswap_ushort_3() {
+// CHECK-IR: ret i16 768
+  return _byteswap_ushort(3);
+}
+unsigned short check_byteswap_ushort_4() {
+// CHECK-IR: ret i16 1024
+  return _byteswap_ushort(4);
+}
+unsigned short check_byteswap_ushort_5() {
+// CHECK-IR: ret i16 1280
+  return _byteswap_ushort(5);
+}
+
+unsigned long check_byteswap_ulong_1() {
+// CHECK-IR: ret i32 16777216
+  return _byteswap_ulong(1);
+}
+unsigned long check_byteswap_ulong_2() {
+// CHECK-IR: ret i32 33554432
+  return _byteswap_ulong(2);
+}
+unsigned long check_byteswap_ulong_3() {
+// CHECK-IR: ret i32 50331648
+  return _byteswap_ulong(3);
+}
+unsigned long check_byteswap_ulong_4() {
+// CHECK-IR: ret i32 67108864
+  return _byteswap_ulong(4);
+}
+unsigned long check_byteswap_ulong_5() {
+// CHECK-IR: ret i32 83886080
+  return _byteswap_ulong(5);
+}
+
+unsigned __int64 check_byteswap_uint64_1() {
+// CHECK-IR: ret i64 72057594037927936
+  return _byteswap_uint64(1);
+}
+unsigned __int64 check_byteswap_uint64_2() {
+// CHECK-IR: ret i64 144115188075855872
+  return _byteswap

[PATCH] D56620: [COFF, ARM64] Declare intrinsics: __nop, _byteswap_[ushort/ulong/uint64]

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang abandoned this revision.
mgrang added a comment.

_bytswap intrinsics are added in D56685 . 
Abandoning this patch.


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[PATCH] D56671: [COFF, ARM64] Add __nop intrinsic

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL351135: [COFF, ARM64] Add __nop intrinsic (authored by 
mgrang, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D56671?vs=181578&id=181659#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
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Files:
  cfe/trunk/lib/Headers/intrin.h
  cfe/trunk/test/Headers/ms-arm64-intrin.cpp


Index: cfe/trunk/lib/Headers/intrin.h
===
--- cfe/trunk/lib/Headers/intrin.h
+++ cfe/trunk/lib/Headers/intrin.h
@@ -549,6 +549,9 @@
 __halt(void) {
   __asm__ volatile ("hlt");
 }
+#endif
+
+#if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__)
 static __inline__ void __DEFAULT_FN_ATTRS
 __nop(void) {
   __asm__ volatile ("nop");
Index: cfe/trunk/test/Headers/ms-arm64-intrin.cpp
===
--- cfe/trunk/test/Headers/ms-arm64-intrin.cpp
+++ cfe/trunk/test/Headers/ms-arm64-intrin.cpp
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -triple arm64-windows \
+// RUN: -fms-compatibility -fms-compatibility-version=17.00 \
+// RUN: -ffreestanding -fsyntax-only -Werror \
+// RUN: -isystem %S/Inputs/include %s -S -o - 2>&1 | FileCheck %s
+
+// REQUIRES: aarch64-registered-target
+
+#include 
+
+void f() {
+// CHECK: nop
+  __nop();
+}


Index: cfe/trunk/lib/Headers/intrin.h
===
--- cfe/trunk/lib/Headers/intrin.h
+++ cfe/trunk/lib/Headers/intrin.h
@@ -549,6 +549,9 @@
 __halt(void) {
   __asm__ volatile ("hlt");
 }
+#endif
+
+#if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__)
 static __inline__ void __DEFAULT_FN_ATTRS
 __nop(void) {
   __asm__ volatile ("nop");
Index: cfe/trunk/test/Headers/ms-arm64-intrin.cpp
===
--- cfe/trunk/test/Headers/ms-arm64-intrin.cpp
+++ cfe/trunk/test/Headers/ms-arm64-intrin.cpp
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -triple arm64-windows \
+// RUN: -fms-compatibility -fms-compatibility-version=17.00 \
+// RUN: -ffreestanding -fsyntax-only -Werror \
+// RUN: -isystem %S/Inputs/include %s -S -o - 2>&1 | FileCheck %s
+
+// REQUIRES: aarch64-registered-target
+
+#include 
+
+void f() {
+// CHECK: nop
+  __nop();
+}
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[PATCH] D56685: [COFF, ARM64] Add __byteswap intrinsics

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 181671.
mgrang retitled this revision from "[COFF, ARM64] Declare __byteswap 
intrinsics" to "[COFF, ARM64] Add __byteswap intrinsics".

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56685/new/

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Files:
  lib/Headers/intrin.h
  test/Headers/ms-arm64-intrin.cpp


Index: test/Headers/ms-arm64-intrin.cpp
===
--- test/Headers/ms-arm64-intrin.cpp
+++ test/Headers/ms-arm64-intrin.cpp
@@ -1,9 +1,15 @@
+// REQUIRES: aarch64-registered-target
+
 // RUN: %clang_cc1 -triple arm64-windows \
 // RUN: -fms-compatibility -fms-compatibility-version=17.00 \
 // RUN: -ffreestanding -fsyntax-only -Werror \
 // RUN: -isystem %S/Inputs/include %s -S -o - 2>&1 | FileCheck %s
 
-// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple arm64-windows -O1 \
+// RUN: -fms-compatibility -fms-compatibility-version=17.00 \
+// RUN: -ffreestanding -fsyntax-only -Werror \
+// RUN: -isystem %S/Inputs/include %s -S -o - -emit-llvm 2>&1 \
+// RUN: | FileCheck %s --check-prefix CHECK-IR
 
 #include 
 
@@ -11,3 +17,18 @@
 // CHECK: nop
   __nop();
 }
+
+unsigned short check_byteswap_ushort(unsigned short val) {
+// CHECK-IR: call i16 @llvm.bswap.i16(i16 %val)
+  return _byteswap_ushort(val);
+}
+
+unsigned long check_byteswap_ulong(unsigned long val) {
+// CHECK-IR: call i32 @llvm.bswap.i32(i32 %val)
+  return _byteswap_ulong(val);
+}
+
+unsigned __int64 check_byteswap_uint64(unsigned __int64 val) {
+// CHECK-IR: call i64 @llvm.bswap.i64(i64 %val)
+  return _byteswap_uint64(val);
+}
Index: lib/Headers/intrin.h
===
--- lib/Headers/intrin.h
+++ lib/Headers/intrin.h
@@ -566,6 +566,16 @@
 long _InterlockedAdd(long volatile *Addend, long Value);
 int _ReadStatusReg(int);
 void _WriteStatusReg(int, int);
+
+static inline unsigned short _byteswap_ushort (unsigned short val) {
+  return __builtin_bswap16(val);
+}
+static inline unsigned long _byteswap_ulong (unsigned long val) {
+  return __builtin_bswap32(val);
+}
+static inline unsigned __int64 _byteswap_uint64 (unsigned __int64 val) {
+  return __builtin_bswap64(val);
+}
 #endif
 
 
/**\


Index: test/Headers/ms-arm64-intrin.cpp
===
--- test/Headers/ms-arm64-intrin.cpp
+++ test/Headers/ms-arm64-intrin.cpp
@@ -1,9 +1,15 @@
+// REQUIRES: aarch64-registered-target
+
 // RUN: %clang_cc1 -triple arm64-windows \
 // RUN: -fms-compatibility -fms-compatibility-version=17.00 \
 // RUN: -ffreestanding -fsyntax-only -Werror \
 // RUN: -isystem %S/Inputs/include %s -S -o - 2>&1 | FileCheck %s
 
-// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple arm64-windows -O1 \
+// RUN: -fms-compatibility -fms-compatibility-version=17.00 \
+// RUN: -ffreestanding -fsyntax-only -Werror \
+// RUN: -isystem %S/Inputs/include %s -S -o - -emit-llvm 2>&1 \
+// RUN: | FileCheck %s --check-prefix CHECK-IR
 
 #include 
 
@@ -11,3 +17,18 @@
 // CHECK: nop
   __nop();
 }
+
+unsigned short check_byteswap_ushort(unsigned short val) {
+// CHECK-IR: call i16 @llvm.bswap.i16(i16 %val)
+  return _byteswap_ushort(val);
+}
+
+unsigned long check_byteswap_ulong(unsigned long val) {
+// CHECK-IR: call i32 @llvm.bswap.i32(i32 %val)
+  return _byteswap_ulong(val);
+}
+
+unsigned __int64 check_byteswap_uint64(unsigned __int64 val) {
+// CHECK-IR: call i64 @llvm.bswap.i64(i64 %val)
+  return _byteswap_uint64(val);
+}
Index: lib/Headers/intrin.h
===
--- lib/Headers/intrin.h
+++ lib/Headers/intrin.h
@@ -566,6 +566,16 @@
 long _InterlockedAdd(long volatile *Addend, long Value);
 int _ReadStatusReg(int);
 void _WriteStatusReg(int, int);
+
+static inline unsigned short _byteswap_ushort (unsigned short val) {
+  return __builtin_bswap16(val);
+}
+static inline unsigned long _byteswap_ulong (unsigned long val) {
+  return __builtin_bswap32(val);
+}
+static inline unsigned __int64 _byteswap_uint64 (unsigned __int64 val) {
+  return __builtin_bswap64(val);
+}
 #endif
 
 /**\
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[PATCH] D56685: [COFF, ARM64] Add __byteswap intrinsics

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang marked an inline comment as done.
mgrang added a comment.

Verified that this compiles when both intrin.h and stdlib.h from the Microsoft 
SDK are included, in either order.


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[PATCH] D56685: [COFF, ARM64] Add __byteswap intrinsics

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 181679.

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Files:
  lib/Headers/intrin.h
  test/Headers/ms-arm64-intrin.cpp


Index: test/Headers/ms-arm64-intrin.cpp
===
--- test/Headers/ms-arm64-intrin.cpp
+++ test/Headers/ms-arm64-intrin.cpp
@@ -1,13 +1,29 @@
-// RUN: %clang_cc1 -triple arm64-windows \
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple arm64-windows -O1 \
 // RUN: -fms-compatibility -fms-compatibility-version=17.00 \
 // RUN: -ffreestanding -fsyntax-only -Werror \
-// RUN: -isystem %S/Inputs/include %s -S -o - 2>&1 | FileCheck %s
-
-// REQUIRES: aarch64-registered-target
+// RUN: -isystem %S/Inputs/include %s -S -o - -emit-llvm 2>&1 \
+// RUN: | FileCheck %s
 
 #include 
 
-void f() {
-// CHECK: nop
+void check_nop() {
+// CHECK: "nop"
   __nop();
 }
+
+unsigned short check_byteswap_ushort(unsigned short val) {
+// CHECK: call i16 @llvm.bswap.i16(i16 %val)
+  return _byteswap_ushort(val);
+}
+
+unsigned long check_byteswap_ulong(unsigned long val) {
+// CHECK: call i32 @llvm.bswap.i32(i32 %val)
+  return _byteswap_ulong(val);
+}
+
+unsigned __int64 check_byteswap_uint64(unsigned __int64 val) {
+// CHECK: call i64 @llvm.bswap.i64(i64 %val)
+  return _byteswap_uint64(val);
+}
Index: lib/Headers/intrin.h
===
--- lib/Headers/intrin.h
+++ lib/Headers/intrin.h
@@ -566,6 +566,16 @@
 long _InterlockedAdd(long volatile *Addend, long Value);
 int _ReadStatusReg(int);
 void _WriteStatusReg(int, int);
+
+static inline unsigned short _byteswap_ushort (unsigned short val) {
+  return __builtin_bswap16(val);
+}
+static inline unsigned long _byteswap_ulong (unsigned long val) {
+  return __builtin_bswap32(val);
+}
+static inline unsigned __int64 _byteswap_uint64 (unsigned __int64 val) {
+  return __builtin_bswap64(val);
+}
 #endif
 
 
/**\


Index: test/Headers/ms-arm64-intrin.cpp
===
--- test/Headers/ms-arm64-intrin.cpp
+++ test/Headers/ms-arm64-intrin.cpp
@@ -1,13 +1,29 @@
-// RUN: %clang_cc1 -triple arm64-windows \
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple arm64-windows -O1 \
 // RUN: -fms-compatibility -fms-compatibility-version=17.00 \
 // RUN: -ffreestanding -fsyntax-only -Werror \
-// RUN: -isystem %S/Inputs/include %s -S -o - 2>&1 | FileCheck %s
-
-// REQUIRES: aarch64-registered-target
+// RUN: -isystem %S/Inputs/include %s -S -o - -emit-llvm 2>&1 \
+// RUN: | FileCheck %s
 
 #include 
 
-void f() {
-// CHECK: nop
+void check_nop() {
+// CHECK: "nop"
   __nop();
 }
+
+unsigned short check_byteswap_ushort(unsigned short val) {
+// CHECK: call i16 @llvm.bswap.i16(i16 %val)
+  return _byteswap_ushort(val);
+}
+
+unsigned long check_byteswap_ulong(unsigned long val) {
+// CHECK: call i32 @llvm.bswap.i32(i32 %val)
+  return _byteswap_ulong(val);
+}
+
+unsigned __int64 check_byteswap_uint64(unsigned __int64 val) {
+// CHECK: call i64 @llvm.bswap.i64(i64 %val)
+  return _byteswap_uint64(val);
+}
Index: lib/Headers/intrin.h
===
--- lib/Headers/intrin.h
+++ lib/Headers/intrin.h
@@ -566,6 +566,16 @@
 long _InterlockedAdd(long volatile *Addend, long Value);
 int _ReadStatusReg(int);
 void _WriteStatusReg(int, int);
+
+static inline unsigned short _byteswap_ushort (unsigned short val) {
+  return __builtin_bswap16(val);
+}
+static inline unsigned long _byteswap_ulong (unsigned long val) {
+  return __builtin_bswap32(val);
+}
+static inline unsigned __int64 _byteswap_uint64 (unsigned __int64 val) {
+  return __builtin_bswap64(val);
+}
 #endif
 
 /**\
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[PATCH] D56685: [COFF, ARM64] Add __byteswap intrinsics

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC351147: [COFF, ARM64] Add __byteswap intrinsics (authored by 
mgrang, committed by ).

Repository:
  rC Clang

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Files:
  lib/Headers/intrin.h
  test/Headers/ms-arm64-intrin.cpp


Index: test/Headers/ms-arm64-intrin.cpp
===
--- test/Headers/ms-arm64-intrin.cpp
+++ test/Headers/ms-arm64-intrin.cpp
@@ -1,13 +1,29 @@
-// RUN: %clang_cc1 -triple arm64-windows \
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple arm64-windows -O1 \
 // RUN: -fms-compatibility -fms-compatibility-version=17.00 \
 // RUN: -ffreestanding -fsyntax-only -Werror \
-// RUN: -isystem %S/Inputs/include %s -S -o - 2>&1 | FileCheck %s
-
-// REQUIRES: aarch64-registered-target
+// RUN: -isystem %S/Inputs/include %s -S -o - -emit-llvm 2>&1 \
+// RUN: | FileCheck %s
 
 #include 
 
-void f() {
-// CHECK: nop
+void check_nop() {
+// CHECK: "nop"
   __nop();
 }
+
+unsigned short check_byteswap_ushort(unsigned short val) {
+// CHECK: call i16 @llvm.bswap.i16(i16 %val)
+  return _byteswap_ushort(val);
+}
+
+unsigned long check_byteswap_ulong(unsigned long val) {
+// CHECK: call i32 @llvm.bswap.i32(i32 %val)
+  return _byteswap_ulong(val);
+}
+
+unsigned __int64 check_byteswap_uint64(unsigned __int64 val) {
+// CHECK: call i64 @llvm.bswap.i64(i64 %val)
+  return _byteswap_uint64(val);
+}
Index: lib/Headers/intrin.h
===
--- lib/Headers/intrin.h
+++ lib/Headers/intrin.h
@@ -566,6 +566,16 @@
 long _InterlockedAdd(long volatile *Addend, long Value);
 int _ReadStatusReg(int);
 void _WriteStatusReg(int, int);
+
+static inline unsigned short _byteswap_ushort (unsigned short val) {
+  return __builtin_bswap16(val);
+}
+static inline unsigned long _byteswap_ulong (unsigned long val) {
+  return __builtin_bswap32(val);
+}
+static inline unsigned __int64 _byteswap_uint64 (unsigned __int64 val) {
+  return __builtin_bswap64(val);
+}
 #endif
 
 
/**\


Index: test/Headers/ms-arm64-intrin.cpp
===
--- test/Headers/ms-arm64-intrin.cpp
+++ test/Headers/ms-arm64-intrin.cpp
@@ -1,13 +1,29 @@
-// RUN: %clang_cc1 -triple arm64-windows \
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple arm64-windows -O1 \
 // RUN: -fms-compatibility -fms-compatibility-version=17.00 \
 // RUN: -ffreestanding -fsyntax-only -Werror \
-// RUN: -isystem %S/Inputs/include %s -S -o - 2>&1 | FileCheck %s
-
-// REQUIRES: aarch64-registered-target
+// RUN: -isystem %S/Inputs/include %s -S -o - -emit-llvm 2>&1 \
+// RUN: | FileCheck %s
 
 #include 
 
-void f() {
-// CHECK: nop
+void check_nop() {
+// CHECK: "nop"
   __nop();
 }
+
+unsigned short check_byteswap_ushort(unsigned short val) {
+// CHECK: call i16 @llvm.bswap.i16(i16 %val)
+  return _byteswap_ushort(val);
+}
+
+unsigned long check_byteswap_ulong(unsigned long val) {
+// CHECK: call i32 @llvm.bswap.i32(i32 %val)
+  return _byteswap_ulong(val);
+}
+
+unsigned __int64 check_byteswap_uint64(unsigned __int64 val) {
+// CHECK: call i64 @llvm.bswap.i64(i64 %val)
+  return _byteswap_uint64(val);
+}
Index: lib/Headers/intrin.h
===
--- lib/Headers/intrin.h
+++ lib/Headers/intrin.h
@@ -566,6 +566,16 @@
 long _InterlockedAdd(long volatile *Addend, long Value);
 int _ReadStatusReg(int);
 void _WriteStatusReg(int, int);
+
+static inline unsigned short _byteswap_ushort (unsigned short val) {
+  return __builtin_bswap16(val);
+}
+static inline unsigned long _byteswap_ulong (unsigned long val) {
+  return __builtin_bswap32(val);
+}
+static inline unsigned __int64 _byteswap_uint64 (unsigned __int64 val) {
+  return __builtin_bswap64(val);
+}
 #endif
 
 /**\
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[PATCH] D53541: [COFF, ARM64] Do not emit x86_seh_recoverfp intrinsic

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

In D53541#1356904 , @rnk wrote:

> In D53541#1353251 , @mgrang wrote:
>
> > > What about the three stack pointer case of stack realignment plus a 
> > > dynamic alloca? Typically this is the case where recoverfp is necessary.
> >
> > @rnk Sorry, I missed your comment earlier. I am not sure what scenario the 
> > three stack pointer case is. Could you please give me a test case for it?
>
>
> I think you just need a local variable with an alignment greater than the ABI 
> provides, something like:
>
>   struct Foo {
> Foo();
> int x, y, z;
>   };
>   int filter(int);
>   void may_throw();
>   void seh_byval(int n) {
> Foo __declspec(align(32)) o;
> __try {
>   may_throw();
> } __except(filter(o.x)) {
> }
>   }
>


We seem to be generating the same code as MSVC. Here's my test case:

  struct Foo {
void (*ptr)();
int x, y, z;
  };
  
  int filter(int);
  void may_throw();
  void seh_byval(int n) {
struct Foo __declspec(align(32)) o;
__try {
  may_throw();
} __except(filter(o.x)) {
}
  }

MSVC:

  |seh_byval$filt$0| PROC
  stp fp,lr,[sp,#-0x10]!
  mov fp,x1
  |$LN5@seh_byval$|
  ldr x8,[fp,#0x10]
  ldr w0,[x8,#8]
  bl  filter
  nop
  |$LN7@seh_byval$|
  ldp fp,lr,[sp],#0x10
  ret

LLVM:

  .seh_proc "?filt$0@0@seh_byval@@"
  ; %bb.0:; %entry
  movzx8, #:abs_g1_s:.Lseh_byval$frame_escape_0
  movkx8, #:abs_g0_nc:.Lseh_byval$frame_escape_0
  add x8, x1, x8
  ldr w0, [x8, #8]
  b   filter


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[PATCH] D53541: [COFF, ARM64] Do not emit x86_seh_recoverfp intrinsic

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

In D53541#1358210 , @rnk wrote:

> I can't compile the example you gave yet because I haven't applied your 
> patches locally, but this is the "three stack pointer" case that I have in 
> mind:
>
>   struct Foo {
> void (*ptr)();
> int x, y, z;
>   };
>  
>   void escape(void *);
>   void large_align(int a0, int a1, int a2, int a3, int a4, int a5, int a6, 
> int a7,
>int stackarg) {
> struct Foo __declspec(align(32)) alignedlocal;
> alignedlocal.x = 42;
> int vla[a0];
> escape(&alignedlocal);
> vla[0] = stackarg;
> escape(&vla[0]);
>   }
>
>
> This is LLVM's generated code:
>
>   "?large_align@@YAXH@Z": ; @"?large_align@@YAXH@Z"
>   .seh_proc "?large_align@@YAXH@Z"
>   ; %bb.0:; %entry
>   stp x21, x22, [sp, #-48]!   ; 16-byte Folded Spill
>   stp x19, x20, [sp, #16] ; 16-byte Folded Spill
>   stp x29, x30, [sp, #32] ; 16-byte Folded Spill
>   add x29, sp, #32; =32
>   sub x9, sp, #48 ; =48
>   and sp, x9, #0xffe0
>   mov x19, sp
>   mov w8, #42
>   str w8, [x19, #8]
>   mov w8, w0
>   ldr w22, [x29, #16]
>   lsl x8, x8, #2
>   add x8, x8, #15 ; =15
>   lsr x15, x8, #4
>   mov x21, sp
>   bl  __chkstk
>   mov x8, sp
>   sub x20, x8, x15, lsl #4
>   mov sp, x20
>   add x0, x19, #0 ; =0
>   bl  "?escape@@YAXPEAX@Z"
>   mov x0, x20
>   str w22, [x20]
>   bl  "?escape@@YAXPEAX@Z"
>   mov sp, x21
>   sub sp, x29, #32; =32
>   ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
>   ldp x19, x20, [sp, #16] ; 16-byte Folded Reload
>   ldp x21, x22, [sp], #48 ; 16-byte Folded Reload
>   ret
>
>
> I see three pointers used to address the stack:
>
> - sp: to address vla
> - x19: to address locals, the so-called "base" pointer
> - x29: to address parameters on the stack, looks like the traditional FP, 
> points to FP+LR pair as well
>
>   At least for x86, the unwind info doesn't describe X19, it just describes 
> X29, since that's what you need to restore CSRs and find the parent stack 
> frame. We saw that the Windows EH runtime passes in some value based on the 
> unwind info. For x86, it was just whatever EBP held, so recoverfp simply 
> aligns that value forward to recover the base pointer (ESI) and then uses 
> that to recover locals. For x64, the runtime passes in the value of RSP after 
> the prologue ends, so we adjust it by the "parent frame offset" to get back 
> the value we put in RBP. It looks like for x64 we never handled the case I'm 
> asking you about, because this program doesn't print the right value: ``` 
> #include  struct Foo { void (*ptr)(); int x, y, z; }; int filter(int 
> n) { printf("o.x: %d\n", n); return 1; } void may_throw() { __builtin_trap(); 
> } int main() { struct Foo __declspec(align(32)) o; o.x = 42; __try { 
> may_throw(); } __except(filter(o.x)) { } } ```
>
>   I get "o.x: 0" instead of 42. I bet we can find something about that in 
> bugzilla somewhere. =/
>
>   So, hopefully that explains the intended purpose of 
> `llvm.x86.seh.recoverfp`, and why we might need to generalize it into 
> something non-x86 specific. Maybe `llvm.eh.recoverfp`. Let me know if I can 
> clarify anything else.


@rnk Thanks a lot for the clarification. Yes, I see o.x: 0 instead of 42. 
Supporting this case would mean implementing recoverfp as well as support 
generating the correct parent frame offset for arm64 windows. Do you think this 
can be done in a follow-up patch? So this patch and D53540 
 would add the basic support for SEH and we 
can go fix corner/more complex cases in follow-up patches. There are also 
several more comprehensive test cases in 
https://github.com/Microsoft/windows_seh_tests which we plan to address next.


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[PATCH] D56748: [EH] Rename llvm.x86.seh.recoverfp intrinsic to llvm.eh.recoverfp

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, efriedma.

This is the clang counterpart to D56747 .


Repository:
  rC Clang

https://reviews.llvm.org/D56748

Files:
  lib/CodeGen/CGException.cpp
  test/CodeGen/exceptions-seh.c
  test/CodeGenCXX/exceptions-seh-filter-captures.cpp


Index: test/CodeGenCXX/exceptions-seh-filter-captures.cpp
===
--- test/CodeGenCXX/exceptions-seh-filter-captures.cpp
+++ test/CodeGenCXX/exceptions-seh-filter-captures.cpp
@@ -21,7 +21,7 @@
 // CHECK: invoke void @might_crash()
 
 // CHECK-LABEL: define internal i32 @"?filt$0@0@test_freefunc@@"(i8* 
%exception_pointers, i8* %frame_pointer)
-// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (void 
(i32)* @test_freefunc to i8*), i8* %frame_pointer)
+// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.eh.recoverfp(i8* bitcast (void (i32)* 
@test_freefunc to i8*), i8* %frame_pointer)
 // CHECK: %[[p1_i8:[^ ]*]] = call i8* @llvm.localrecover(i8* bitcast (void 
(i32)* @test_freefunc to i8*), i8* %[[fp]], i32 0)
 // CHECK: %[[p1_ptr:[^ ]*]] = bitcast i8* %[[p1_i8]] to i32*
 // CHECK: %[[l1_i8:[^ ]*]] = call i8* @llvm.localrecover(i8* bitcast (void 
(i32)* @test_freefunc to i8*), i8* %[[fp]], i32 1)
@@ -51,7 +51,7 @@
 // CHECK: invoke void @might_crash()
 
 // CHECK-LABEL: define internal i32 @"?filt$0@0@test_method@S@@"(i8* 
%exception_pointers, i8* %frame_pointer)
-// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (void 
(%struct.S*)* @"?test_method@S@@QEAAXXZ" to i8*), i8* %frame_pointer)
+// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.eh.recoverfp(i8* bitcast (void 
(%struct.S*)* @"?test_method@S@@QEAAXXZ" to i8*), i8* %frame_pointer)
 // CHECK: %[[l1_i8:[^ ]*]] = call i8* @llvm.localrecover(i8* bitcast (void 
(%struct.S*)* @"?test_method@S@@QEAAXXZ" to i8*), i8* %[[fp]], i32 0)
 // CHECK: %[[l1_ptr:[^ ]*]] = bitcast i8* %[[l1_i8]] to i32*
 // CHECK: %[[l1:[^ ]*]] = load i32, i32* %[[l1_ptr]]
@@ -76,7 +76,7 @@
 // CHECK: invoke void @might_crash()
 
 // CHECK-LABEL: define internal i32 
@"?filt$0@0@?R@?0??test_lambda@@YAXXZ@"(i8* %exception_pointers, i8* 
%frame_pointer)
-// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (void 
(%class.anon*)* @"??R@?0??test_lambda@@YAXXZ@QEBA@XZ" to i8*), i8* 
%frame_pointer)
+// CHECK: %[[fp:[^ ]*]] = call i8* @llvm.eh.recoverfp(i8* bitcast (void 
(%class.anon*)* @"??R@?0??test_lambda@@YAXXZ@QEBA@XZ" to i8*), i8* 
%frame_pointer)
 // CHECK: %[[l2_i8:[^ ]*]] = call i8* @llvm.localrecover(i8* bitcast (void 
(%class.anon*)* @"??R@?0??test_lambda@@YAXXZ@QEBA@XZ" to i8*), i8* 
%[[fp]], i32 0)
 // CHECK: %[[l2_ptr:[^ ]*]] = bitcast i8* %[[l2_i8]] to i32*
 // CHECK: %[[l2:[^ ]*]] = load i32, i32* %[[l2_ptr]]
Index: test/CodeGen/exceptions-seh.c
===
--- test/CodeGen/exceptions-seh.c
+++ test/CodeGen/exceptions-seh.c
@@ -52,7 +52,7 @@
 //
 // X86-LABEL: define internal i32 @"?filt$0@0@safe_div@@"()
 // X86: %[[ebp:[^ ]*]] = call i8* @llvm.frameaddress(i32 1)
-// X86: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 
(i32, i32, i32*)* @safe_div to i8*), i8* %[[ebp]])
+// X86: %[[fp:[^ ]*]] = call i8* @llvm.eh.recoverfp(i8* bitcast (i32 (i32, 
i32, i32*)* @safe_div to i8*), i8* %[[ebp]])
 // X86: call i8* @llvm.localrecover(i8* bitcast (i32 (i32, i32, i32*)* 
@safe_div to i8*), i8* %[[fp]], i32 0)
 // X86: load i8*, i8**
 // X86: load i32*, i32**
@@ -95,16 +95,16 @@
 // CHECK: ret i32 %[[rv]]
 
 // X64-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"(i8* 
%exception_pointers, i8* %frame_pointer)
-// X64: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %frame_pointer)
+// X64: %[[fp:[^ ]*]] = call i8* @llvm.eh.recoverfp(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %frame_pointer)
 // X64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture 
to i8*), i8* %[[fp]], i32 0)
 //
 // ARM64-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"(i8* 
%exception_pointers, i8* %frame_pointer)
-// ARM64: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 
()* @filter_expr_capture to i8*), i8* %frame_pointer)
+// ARM64: %[[fp:[^ ]*]] = call i8* @llvm.eh.recoverfp(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %frame_pointer)
 // ARM64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %[[fp]], i32 0)
 //
 // X86-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"()
 // X86: %[[ebp:[^ ]*]] = call i8* @llvm.frameaddress(i32 1)
-// X86: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %[[ebp]])
+// X86: %[[fp:[^ ]*]] = call i8* @llvm.eh.recoverfp(i8* bitcast (i32 ()* 
@filter_expr_capture to i8*), i8* %[[ebp]])
 // X86: call i8* @llvm.localrecover(i8* bitcast (i32 ()*

[PATCH] D53541: [COFF, ARM64] Do not emit x86_seh_recoverfp intrinsic

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

I have renamed llvm.x86.seh.recoverfp intrinsic to llvm.eh.recoverfp in D56747 
 and D56748 .


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[PATCH] D53541: [COFF, ARM64] Do not emit x86_seh_recoverfp intrinsic

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang abandoned this revision.
mgrang added a comment.

I have added a default lowering for llvm.eh.recoverfp in D53540 
. So this patch is no longer needed.


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[PATCH] D53541: [COFF, ARM64] Support SEH for ARM64 Windows

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 171994.
mgrang retitled this revision from "[COFF, ARM64] Add aarch64_seh_recoverfp 
intrinsic" to "[COFF, ARM64] Support SEH for ARM64 Windows".
mgrang edited the summary of this revision.
mgrang added a comment.

Updated the patch with the following changes:

1. Emit llvm.x86.seh.recoverfp only for non-aarch64 targets. For aarch64 
windows, the parent fp is always passed in x1. So we don't need a separate 
instrinsic to recover the fp.

2. Enable SEH exceptions by default for ARM64 windows. If exceptions are not 
enabled then function which may raise an exception are by default marked as 
"nounwind".

3. Removed ARM64 specific tests from exceptions-seh.c. I will push more 
comprehensive tests for ARM64 SEH soon.


https://reviews.llvm.org/D53541

Files:
  lib/CodeGen/CGException.cpp
  lib/Driver/ToolChains/Clang.cpp
  test/CodeGen/exceptions-seh.c

Index: test/CodeGen/exceptions-seh.c
===
--- test/CodeGen/exceptions-seh.c
+++ test/CodeGen/exceptions-seh.c
@@ -2,8 +2,6 @@
 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=X64
 // RUN: %clang_cc1 %s -triple i686-pc-win32 -fms-extensions -emit-llvm -o - \
 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=X86
-// RUN: %clang_cc1 %s -triple aarch64-windows -fms-extensions -emit-llvm -o - \
-// RUN: | FileCheck %s --check-prefixes=CHECK,ARM64
 // RUN: %clang_cc1 %s -triple i686-pc-windows-gnu -fms-extensions -emit-llvm -o - \
 // RUN: | FileCheck %s --check-prefix=X86-GNU
 // RUN: %clang_cc1 %s -triple x86_64-pc-windows-gnu -fms-extensions -emit-llvm -o - \
@@ -31,14 +29,12 @@
 
 // CHECK-LABEL: define dso_local i32 @safe_div(i32 %numerator, i32 %denominator, i32* %res)
 // X64-SAME:  personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
-// ARM64-SAME:personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
 // X86-SAME:  personality i8* bitcast (i32 (...)* @_except_handler3 to i8*)
 // CHECK: invoke void @try_body(i32 %{{.*}}, i32 %{{.*}}, i32* %{{.*}}) #[[NOINLINE:[0-9]+]]
 // CHECK:   to label %{{.*}} unwind label %[[catchpad:[^ ]*]]
 //
 // CHECK: [[catchpad]]
 // X64: %[[padtoken:[^ ]*]] = catchpad within %{{[^ ]*}} [i8* null]
-// ARM64: %[[padtoken:[^ ]*]] = catchpad within %{{[^ ]*}} [i8* null]
 // X86: %[[padtoken:[^ ]*]] = catchpad within %{{[^ ]*}} [i8* bitcast (i32 ()* @"?filt$0@0@safe_div@@" to i8*)]
 // CHECK-NEXT: catchret from %[[padtoken]] to label %[[except:[^ ]*]]
 //
@@ -80,10 +76,8 @@
 
 // CHECK-LABEL: define dso_local i32 @filter_expr_capture()
 // X64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
-// ARM64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
 // X86-SAME: personality i8* bitcast (i32 (...)* @_except_handler3 to i8*)
 // X64: call void (...) @llvm.localescape(i32* %[[r:[^ ,]*]])
-// ARM64: call void (...) @llvm.localescape(i32* %[[r:[^ ,]*]])
 // X86: call void (...) @llvm.localescape(i32* %[[r:[^ ,]*]], i32* %[[code:[^ ,]*]])
 // CHECK: store i32 42, i32* %[[r]]
 // CHECK: invoke void @j() #[[NOINLINE]]
@@ -98,10 +92,6 @@
 // X64: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %frame_pointer)
 // X64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %[[fp]], i32 0)
 //
-// ARM64-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"(i8* %exception_pointers, i8* %frame_pointer)
-// ARM64: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %frame_pointer)
-// ARM64: call i8* @llvm.localrecover(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %[[fp]], i32 0)
-//
 // X86-LABEL: define internal i32 @"?filt$0@0@filter_expr_capture@@"()
 // X86: %[[ebp:[^ ]*]] = call i8* @llvm.frameaddress(i32 1)
 // X86: %[[fp:[^ ]*]] = call i8* @llvm.x86.seh.recoverfp(i8* bitcast (i32 ()* @filter_expr_capture to i8*), i8* %[[ebp]])
@@ -126,7 +116,6 @@
 }
 // CHECK-LABEL: define dso_local i32 @nested_try()
 // X64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
-// ARM64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
 // X86-SAME: personality i8* bitcast (i32 (...)* @_except_handler3 to i8*)
 // CHECK: store i32 42, i32* %[[r:[^ ,]*]]
 // CHECK: invoke void @j() #[[NOINLINE]]
@@ -187,7 +176,6 @@
 }
 // CHECK-LABEL: define dso_local i32 @basic_finally(i32 %g)
 // X64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
-// ARM64-SAME: personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*)
 // X86-SAME: personality i8* bitcast (i32 (...)* @_except_handler3 to i8*)
 // CHECK: %[[g_addr:[^ ]*]] = alloca i32, align 4
 // CHECK: call void (...) @llvm.localescape(i32* %[[g_addr]])
@@ -287,8 +275,6 @@
 // CHECK: catchret from %[[pad]]
 // X64: %[[code:[^ ]*]] = call i32 @llvm.eh.exceptionc

[PATCH] D53684: [COFF, ARM64] Change setjmp for AArch64 Windows to use Intrinsic.sponentry

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL345792: [COFF, ARM64] Change setjmp for AArch64 Windows to 
use Intrinsic.sponentry (authored by mgrang, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D53684?vs=172033&id=172045#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D53684

Files:
  cfe/trunk/lib/CodeGen/CGBuiltin.cpp
  cfe/trunk/test/CodeGen/ms-setjmp.c


Index: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
===
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp
@@ -711,8 +711,11 @@
   } else {
 Name = SJKind == MSVCSetJmpKind::_setjmp ? "_setjmp" : "_setjmpex";
 Arg1Ty = CGF.Int8PtrTy;
-Arg1 = 
CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(Intrinsic::frameaddress),
-  llvm::ConstantInt::get(CGF.Int32Ty, 0));
+if (CGF.getTarget().getTriple().getArch() == llvm::Triple::aarch64) {
+  Arg1 = 
CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(Intrinsic::sponentry));
+} else
+  Arg1 = 
CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(Intrinsic::frameaddress),
+llvm::ConstantInt::get(CGF.Int32Ty, 0));
   }
 
   // Mark the call site and declaration with ReturnsTwice.
Index: cfe/trunk/test/CodeGen/ms-setjmp.c
===
--- cfe/trunk/test/CodeGen/ms-setjmp.c
+++ cfe/trunk/test/CodeGen/ms-setjmp.c
@@ -25,7 +25,7 @@
   // X64-NEXT:  ret i32 %[[call]]
 
   // AARCH64-LABEL: define dso_local i32 @test_setjmp
-  // AARCH64:   %[[addr:.*]] = call i8* @llvm.frameaddress(i32 0)
+  // AARCH64:   %[[addr:.*]] = call i8* @llvm.sponentry()
   // AARCH64:   %[[call:.*]] = call i32 @_setjmpex(i8* getelementptr 
inbounds ([1 x i8], [1 x i8]* @jb, i32 0, i32 0), i8* %[[addr]])
   // AARCH64-NEXT:  ret i32 %[[call]]
 }
@@ -38,7 +38,7 @@
   // X64-NEXT:  ret i32 %[[call]]
 
   // AARCH64-LABEL: define dso_local i32 @test_setjmpex
-  // AARCH64:   %[[addr:.*]] = call i8* @llvm.frameaddress(i32 0)
+  // AARCH64:   %[[addr:.*]] = call i8* @llvm.sponentry()
   // AARCH64:   %[[call:.*]] = call i32 @_setjmpex(i8* getelementptr 
inbounds ([1 x i8], [1 x i8]* @jb, i32 0, i32 0), i8* %[[addr]])
   // AARCH64-NEXT:  ret i32 %[[call]]
 }


Index: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
===
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp
@@ -711,8 +711,11 @@
   } else {
 Name = SJKind == MSVCSetJmpKind::_setjmp ? "_setjmp" : "_setjmpex";
 Arg1Ty = CGF.Int8PtrTy;
-Arg1 = CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(Intrinsic::frameaddress),
-  llvm::ConstantInt::get(CGF.Int32Ty, 0));
+if (CGF.getTarget().getTriple().getArch() == llvm::Triple::aarch64) {
+  Arg1 = CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(Intrinsic::sponentry));
+} else
+  Arg1 = CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(Intrinsic::frameaddress),
+llvm::ConstantInt::get(CGF.Int32Ty, 0));
   }
 
   // Mark the call site and declaration with ReturnsTwice.
Index: cfe/trunk/test/CodeGen/ms-setjmp.c
===
--- cfe/trunk/test/CodeGen/ms-setjmp.c
+++ cfe/trunk/test/CodeGen/ms-setjmp.c
@@ -25,7 +25,7 @@
   // X64-NEXT:  ret i32 %[[call]]
 
   // AARCH64-LABEL: define dso_local i32 @test_setjmp
-  // AARCH64:   %[[addr:.*]] = call i8* @llvm.frameaddress(i32 0)
+  // AARCH64:   %[[addr:.*]] = call i8* @llvm.sponentry()
   // AARCH64:   %[[call:.*]] = call i32 @_setjmpex(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @jb, i32 0, i32 0), i8* %[[addr]])
   // AARCH64-NEXT:  ret i32 %[[call]]
 }
@@ -38,7 +38,7 @@
   // X64-NEXT:  ret i32 %[[call]]
 
   // AARCH64-LABEL: define dso_local i32 @test_setjmpex
-  // AARCH64:   %[[addr:.*]] = call i8* @llvm.frameaddress(i32 0)
+  // AARCH64:   %[[addr:.*]] = call i8* @llvm.sponentry()
   // AARCH64:   %[[call:.*]] = call i32 @_setjmpex(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @jb, i32 0, i32 0), i8* %[[addr]])
   // AARCH64-NEXT:  ret i32 %[[call]]
 }
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[PATCH] D53960: [COFF, ARM64] Implement llvm.addressofreturnaddress intrinsic

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, mstorsjo, efriedma, TomTan.
Herald added subscribers: chrib, kristof.beyls, javed.absar.

Repository:
  rC Clang

https://reviews.llvm.org/D53960

Files:
  include/clang/Basic/BuiltinsAArch64.def
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGen/ms-intrinsics.c


Index: test/CodeGen/ms-intrinsics.c
===
--- test/CodeGen/ms-intrinsics.c
+++ test/CodeGen/ms-intrinsics.c
@@ -137,7 +137,7 @@
 // CHECK: = tail call i8* @llvm.returnaddress(i32 0)
 // CHECK: ret i8*
 
-#if defined(__i386__) || defined(__x86_64__)
+#if defined(__i386__) || defined(__x86_64__) || defined (__aarch64__)
 void *test_AddressOfReturnAddress() {
   return _AddressOfReturnAddress();
 }
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -6740,6 +6740,11 @@
 return Builder.CreateCall(F, { Metadata, ArgValue });
   }
 
+  if (BuiltinID == AArch64::BI_AddressOfReturnAddress) {
+llvm::Value *F = CGM.getIntrinsic(Intrinsic::addressofreturnaddress);
+return Builder.CreateCall(F);
+  }
+
   // Find out if any arguments are required to be integer constant
   // expressions.
   unsigned ICEArguments = 0;
Index: include/clang/Basic/BuiltinsAArch64.def
===
--- include/clang/Basic/BuiltinsAArch64.def
+++ include/clang/Basic/BuiltinsAArch64.def
@@ -103,6 +103,7 @@
 TARGET_HEADER_BUILTIN(_InterlockedIncrement64,   "LLiLLiD*","nh", 
"intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedOr64,  "LLiLLiD*LLi", "nh", 
"intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedXor64, "LLiLLiD*LLi", "nh", 
"intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_AddressOfReturnAddress,   "v*",  "nh", 
"intrin.h", ALL_MS_LANGUAGES, "")
 
 TARGET_HEADER_BUILTIN(_ReadWriteBarrier, "v", "nh", "intrin.h", 
ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(__getReg, "ULLii", "nh", "intrin.h", ALL_MS_LANGUAGES, 
"")


Index: test/CodeGen/ms-intrinsics.c
===
--- test/CodeGen/ms-intrinsics.c
+++ test/CodeGen/ms-intrinsics.c
@@ -137,7 +137,7 @@
 // CHECK: = tail call i8* @llvm.returnaddress(i32 0)
 // CHECK: ret i8*
 
-#if defined(__i386__) || defined(__x86_64__)
+#if defined(__i386__) || defined(__x86_64__) || defined (__aarch64__)
 void *test_AddressOfReturnAddress() {
   return _AddressOfReturnAddress();
 }
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -6740,6 +6740,11 @@
 return Builder.CreateCall(F, { Metadata, ArgValue });
   }
 
+  if (BuiltinID == AArch64::BI_AddressOfReturnAddress) {
+llvm::Value *F = CGM.getIntrinsic(Intrinsic::addressofreturnaddress);
+return Builder.CreateCall(F);
+  }
+
   // Find out if any arguments are required to be integer constant
   // expressions.
   unsigned ICEArguments = 0;
Index: include/clang/Basic/BuiltinsAArch64.def
===
--- include/clang/Basic/BuiltinsAArch64.def
+++ include/clang/Basic/BuiltinsAArch64.def
@@ -103,6 +103,7 @@
 TARGET_HEADER_BUILTIN(_InterlockedIncrement64,   "LLiLLiD*","nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedOr64,  "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedXor64, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_AddressOfReturnAddress,   "v*",  "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 
 TARGET_HEADER_BUILTIN(_ReadWriteBarrier, "v", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(__getReg, "ULLii", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
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[PATCH] D53998: [COFF, ARM64] Change setjmp for AArch64 Windows to use Intrinsic.sponentry

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang accepted this revision.
mgrang added a comment.
This revision is now accepted and ready to land.

Since this is the same as https://reviews.llvm.org/D53684, we can go ahead and 
close this.


Repository:
  rC Clang

https://reviews.llvm.org/D53998



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[PATCH] D53998: [COFF, ARM64] Change setjmp for AArch64 Windows to use Intrinsic.sponentry

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL346024: [COFF, ARM64] Change setjmp for AArch64 Windows to 
use Intrinsic.sponentry (authored by mgrang, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D53998?vs=172238&id=172404#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D53998

Files:
  cfe/trunk/lib/CodeGen/CGBuiltin.cpp
  cfe/trunk/test/CodeGen/ms-setjmp.c


Index: cfe/trunk/test/CodeGen/ms-setjmp.c
===
--- cfe/trunk/test/CodeGen/ms-setjmp.c
+++ cfe/trunk/test/CodeGen/ms-setjmp.c
@@ -25,7 +25,7 @@
   // X64-NEXT:  ret i32 %[[call]]
 
   // AARCH64-LABEL: define dso_local i32 @test_setjmp
-  // AARCH64:   %[[addr:.*]] = call i8* @llvm.frameaddress(i32 0)
+  // AARCH64:   %[[addr:.*]] = call i8* @llvm.sponentry()
   // AARCH64:   %[[call:.*]] = call i32 @_setjmpex(i8* getelementptr 
inbounds ([1 x i8], [1 x i8]* @jb, i32 0, i32 0), i8* %[[addr]])
   // AARCH64-NEXT:  ret i32 %[[call]]
 }
@@ -38,7 +38,7 @@
   // X64-NEXT:  ret i32 %[[call]]
 
   // AARCH64-LABEL: define dso_local i32 @test_setjmpex
-  // AARCH64:   %[[addr:.*]] = call i8* @llvm.frameaddress(i32 0)
+  // AARCH64:   %[[addr:.*]] = call i8* @llvm.sponentry()
   // AARCH64:   %[[call:.*]] = call i32 @_setjmpex(i8* getelementptr 
inbounds ([1 x i8], [1 x i8]* @jb, i32 0, i32 0), i8* %[[addr]])
   // AARCH64-NEXT:  ret i32 %[[call]]
 }
Index: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
===
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp
@@ -711,8 +711,11 @@
   } else {
 Name = SJKind == MSVCSetJmpKind::_setjmp ? "_setjmp" : "_setjmpex";
 Arg1Ty = CGF.Int8PtrTy;
-Arg1 = 
CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(Intrinsic::frameaddress),
-  llvm::ConstantInt::get(CGF.Int32Ty, 0));
+if (CGF.getTarget().getTriple().getArch() == llvm::Triple::aarch64) {
+  Arg1 = 
CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(Intrinsic::sponentry));
+} else
+  Arg1 = 
CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(Intrinsic::frameaddress),
+llvm::ConstantInt::get(CGF.Int32Ty, 0));
   }
 
   // Mark the call site and declaration with ReturnsTwice.


Index: cfe/trunk/test/CodeGen/ms-setjmp.c
===
--- cfe/trunk/test/CodeGen/ms-setjmp.c
+++ cfe/trunk/test/CodeGen/ms-setjmp.c
@@ -25,7 +25,7 @@
   // X64-NEXT:  ret i32 %[[call]]
 
   // AARCH64-LABEL: define dso_local i32 @test_setjmp
-  // AARCH64:   %[[addr:.*]] = call i8* @llvm.frameaddress(i32 0)
+  // AARCH64:   %[[addr:.*]] = call i8* @llvm.sponentry()
   // AARCH64:   %[[call:.*]] = call i32 @_setjmpex(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @jb, i32 0, i32 0), i8* %[[addr]])
   // AARCH64-NEXT:  ret i32 %[[call]]
 }
@@ -38,7 +38,7 @@
   // X64-NEXT:  ret i32 %[[call]]
 
   // AARCH64-LABEL: define dso_local i32 @test_setjmpex
-  // AARCH64:   %[[addr:.*]] = call i8* @llvm.frameaddress(i32 0)
+  // AARCH64:   %[[addr:.*]] = call i8* @llvm.sponentry()
   // AARCH64:   %[[call:.*]] = call i32 @_setjmpex(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @jb, i32 0, i32 0), i8* %[[addr]])
   // AARCH64-NEXT:  ret i32 %[[call]]
 }
Index: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
===
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp
@@ -711,8 +711,11 @@
   } else {
 Name = SJKind == MSVCSetJmpKind::_setjmp ? "_setjmp" : "_setjmpex";
 Arg1Ty = CGF.Int8PtrTy;
-Arg1 = CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(Intrinsic::frameaddress),
-  llvm::ConstantInt::get(CGF.Int32Ty, 0));
+if (CGF.getTarget().getTriple().getArch() == llvm::Triple::aarch64) {
+  Arg1 = CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(Intrinsic::sponentry));
+} else
+  Arg1 = CGF.Builder.CreateCall(CGF.CGM.getIntrinsic(Intrinsic::frameaddress),
+llvm::ConstantInt::get(CGF.Int32Ty, 0));
   }
 
   // Mark the call site and declaration with ReturnsTwice.
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54046: [COFF, ARM64] Implement InterlockedExchange*_* builtins

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, mstorsjo, efriedma, TomTan.
Herald added subscribers: kristina, jfb, chrib, kristof.beyls, javed.absar.

Windows SDK needs these intrinsics to be proper builtins.  This is second in a 
series of patches to move intrinsic defintions out of intrin.h.


Repository:
  rC Clang

https://reviews.llvm.org/D54046

Files:
  include/clang/Basic/BuiltinsAArch64.def
  include/clang/Basic/BuiltinsARM.def
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/intrin.h
  test/CodeGen/ms-intrinsics.c

Index: test/CodeGen/ms-intrinsics.c
===
--- test/CodeGen/ms-intrinsics.c
+++ test/CodeGen/ms-intrinsics.c
@@ -698,6 +698,90 @@
 // CHECK-ARM-ARM64:   ret i64 [[RESULT:%[0-9]+]]
 // CHECK-ARM-ARM64: }
 
+char test_InterlockedExchange8_acq(char volatile *value, char mask) {
+  return _InterlockedExchange8_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedExchange8_acq(i8*{{[a-z_ ]*}}%value, i8{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xchg i8* %value, i8 %mask acquire
+// CHECK-ARM-ARM64:   ret i8 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+char test_InterlockedExchange8_rel(char volatile *value, char mask) {
+  return _InterlockedExchange8_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedExchange8_rel(i8*{{[a-z_ ]*}}%value, i8{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xchg i8* %value, i8 %mask release
+// CHECK-ARM-ARM64:   ret i8 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+char test_InterlockedExchange8_nf(char volatile *value, char mask) {
+  return _InterlockedExchange8_nf(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedExchange8_nf(i8*{{[a-z_ ]*}}%value, i8{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xchg i8* %value, i8 %mask monotonic
+// CHECK-ARM-ARM64:   ret i8 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+short test_InterlockedExchange16_acq(short volatile *value, short mask) {
+  return _InterlockedExchange16_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedExchange16_acq(i16*{{[a-z_ ]*}}%value, i16{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xchg i16* %value, i16 %mask acquire
+// CHECK-ARM-ARM64:   ret i16 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+short test_InterlockedExchange16_rel(short volatile *value, short mask) {
+  return _InterlockedExchange16_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedExchange16_rel(i16*{{[a-z_ ]*}}%value, i16{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xchg i16* %value, i16 %mask release
+// CHECK-ARM-ARM64:   ret i16 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+short test_InterlockedExchange16_nf(short volatile *value, short mask) {
+  return _InterlockedExchange16_nf(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedExchange16_nf(i16*{{[a-z_ ]*}}%value, i16{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xchg i16* %value, i16 %mask monotonic
+// CHECK-ARM-ARM64:   ret i16 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+long test_InterlockedExchange_acq(long volatile *value, long mask) {
+  return _InterlockedExchange_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedExchange_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xchg i32* %value, i32 %mask acquire
+// CHECK-ARM-ARM64:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+long test_InterlockedExchange_rel(long volatile *value, long mask) {
+  return _InterlockedExchange_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedExchange_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xchg i32* %value, i32 %mask release
+// CHECK-ARM-ARM64:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+long test_InterlockedExchange_nf(long volatile *value, long mask) {
+  return _InterlockedExchange_nf(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedExchange_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xchg i32* %value, i32 %mask monotonic
+// CHECK-ARM-ARM64:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+__int64 test_InterlockedExchange64_acq(__int64 volatile *value, __int64 mask) {
+  return _InterlockedExchange64_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedExchange64_acq(i64*{{[a-z_ ]*}}%value, i64{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xchg i64* %value, i64 %mask acquire
+// CHECK-ARM-ARM64:   ret i64 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+__int64 test_InterlockedExchange64_rel(__int64 volatile *value, __int64 mask) {
+  return _InterlockedExchange64_re

[PATCH] D54046: [COFF, ARM64] Implement InterlockedExchange*_* builtins

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL346044: [COFF, ARM64] Implement InterlockedExchange*_* 
builtins (authored by mgrang, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D54046?vs=172425&id=172432#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D54046

Files:
  cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
  cfe/trunk/include/clang/Basic/BuiltinsARM.def
  cfe/trunk/lib/CodeGen/CGBuiltin.cpp
  cfe/trunk/lib/Headers/intrin.h
  cfe/trunk/test/CodeGen/ms-intrinsics.c

Index: cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
===
--- cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
+++ cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
@@ -117,6 +117,19 @@
 TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64_nf, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 
+TARGET_HEADER_BUILTIN(_InterlockedExchange8_acq,  "ccD*c",   "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange8_nf,   "ccD*c",   "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange8_rel,  "ccD*c",   "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange16_acq, "ssD*s",   "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange16_nf,  "ssD*s",   "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange16_rel, "ssD*s",   "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange_acq,   "LiLiD*Li","nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange_nf,"LiLiD*Li","nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange_rel,   "LiLiD*Li","nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange64_acq, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange64_nf,  "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+
 TARGET_HEADER_BUILTIN(_ReadWriteBarrier, "v", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(__getReg, "ULLii", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_ReadStatusReg,  "ii",  "nh", "intrin.h", ALL_MS_LANGUAGES, "")
Index: cfe/trunk/include/clang/Basic/BuiltinsARM.def
===
--- cfe/trunk/include/clang/Basic/BuiltinsARM.def
+++ cfe/trunk/include/clang/Basic/BuiltinsARM.def
@@ -243,6 +243,19 @@
 TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedExchangeAdd64_nf, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 
+TARGET_HEADER_BUILTIN(_InterlockedExchange8_acq,  "ccD*c",   "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange8_nf,   "ccD*c",   "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange8_rel,  "ccD*c",   "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange16_acq, "ssD*s",   "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange16_nf,  "ssD*s",   "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange16_rel, "ssD*s",   "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange_acq,   "LiLiD*Li","nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange_nf,"LiLiD*Li","nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange_rel,   "LiLiD*Li","nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange64_acq, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange64_nf,  "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedExchange64_rel, "LLiLLiD*LLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
+
 #undef BUILTIN
 #undef LANGBUILTIN
 #undef TARGET_HEADER_BUILTIN
Index: cfe/trunk/test/CodeGen/ms-intrinsics.c
===
--- cfe/trunk/test/CodeGen/ms-intrinsics.c
+++ cfe/trunk/test/CodeGen/ms-intrinsics.c
@@ -698,6 +698,90 @@
 // CHECK-ARM-ARM64:   ret i64 [[RESULT:%[0-9]+]]
 // CHECK-ARM-ARM64: }
 
+char test_InterlockedExchange8_acq(char volatile *value, char mask) {
+  return _InterlockedExchange8_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedExchange8_acq(i8*{{[a-z_ ]*}}%value, i8{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xchg i

[PATCH] D54062: [COFF, ARM64] Implement InterlockedCompareExchange*_* builtins

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, efriedma, mstorsjo, TomTan.
Herald added subscribers: kristina, jfb, chrib, kristof.beyls, javed.absar.

This is third in a series of patches to move intrinsic definitions out of 
intrin.h.


Repository:
  rC Clang

https://reviews.llvm.org/D54062

Files:
  include/clang/Basic/BuiltinsAArch64.def
  include/clang/Basic/BuiltinsARM.def
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/intrin.h
  test/CodeGen/ms-intrinsics.c

Index: test/CodeGen/ms-intrinsics.c
===
--- test/CodeGen/ms-intrinsics.c
+++ test/CodeGen/ms-intrinsics.c
@@ -782,6 +782,114 @@
 // CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xchg i64* %value, i64 %mask monotonic
 // CHECK-ARM-ARM64:   ret i64 [[RESULT:%[0-9]+]]
 // CHECK-ARM-ARM64: }
+
+char test_InterlockedCompareExchange8_acq(char volatile *Destination, char Exchange, char Comperand) {
+  return _InterlockedCompareExchange8_acq(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedCompareExchange8_acq(i8*{{[a-z_ ]*}}%Destination, i8{{[a-z_ ]*}}%Exchange, i8{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i8* %Destination, i8 %Comperand, i8 %Exchange acquire acquire
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i8, i1 } [[TMP]], 0
+// CHECK-ARM-ARM64: ret i8 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+char test_InterlockedCompareExchange8_rel(char volatile *Destination, char Exchange, char Comperand) {
+  return _InterlockedCompareExchange8_rel(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedCompareExchange8_rel(i8*{{[a-z_ ]*}}%Destination, i8{{[a-z_ ]*}}%Exchange, i8{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i8* %Destination, i8 %Comperand, i8 %Exchange release monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i8, i1 } [[TMP]], 0
+// CHECK-ARM-ARM64: ret i8 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+char test_InterlockedCompareExchange8_nf(char volatile *Destination, char Exchange, char Comperand) {
+  return _InterlockedCompareExchange8_nf(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedCompareExchange8_nf(i8*{{[a-z_ ]*}}%Destination, i8{{[a-z_ ]*}}%Exchange, i8{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i8* %Destination, i8 %Comperand, i8 %Exchange monotonic monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i8, i1 } [[TMP]], 0
+// CHECK-ARM-ARM64: ret i8 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedCompareExchange16_acq(short volatile *Destination, short Exchange, short Comperand) {
+  return _InterlockedCompareExchange16_acq(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedCompareExchange16_acq(i16*{{[a-z_ ]*}}%Destination, i16{{[a-z_ ]*}}%Exchange, i16{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i16* %Destination, i16 %Comperand, i16 %Exchange acquire acquire
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i16, i1 } [[TMP]], 0
+// CHECK-ARM-ARM64: ret i16 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedCompareExchange16_rel(short volatile *Destination, short Exchange, short Comperand) {
+  return _InterlockedCompareExchange16_rel(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedCompareExchange16_rel(i16*{{[a-z_ ]*}}%Destination, i16{{[a-z_ ]*}}%Exchange, i16{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i16* %Destination, i16 %Comperand, i16 %Exchange release monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i16, i1 } [[TMP]], 0
+// CHECK-ARM-ARM64: ret i16 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedCompareExchange16_nf(short volatile *Destination, short Exchange, short Comperand) {
+  return _InterlockedCompareExchange16_nf(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedCompareExchange16_nf(i16*{{[a-z_ ]*}}%Destination, i16{{[a-z_ ]*}}%Exchange, i16{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i16* %Destination, i16 %Comperand, i16 %Exchange monotonic monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i16, i1 } [[TMP]], 0
+// CHECK-ARM-ARM64: ret i16 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedCompareExchange_acq(long volatile *Destination, long Exchange, long Comperand) {
+  return _InterlockedCompareExchange_acq(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedCompareExchange_acq(i32*{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i32* %Destination, i32 %Comperand, i32 %Exchange acquire acquire
+// CHECK-

[PATCH] D54063: [COFF, ARM64] Implement InterlockedOr*_* builtins

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, efriedma, mstorsjo, TomTan.
Herald added subscribers: kristina, jfb, chrib, kristof.beyls, javed.absar.

This is fourth in a series of patches to move intrinsic defintions out of 
intrin.h.


Repository:
  rC Clang

https://reviews.llvm.org/D54063

Files:
  include/clang/Basic/BuiltinsAArch64.def
  include/clang/Basic/BuiltinsARM.def
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/intrin.h
  test/CodeGen/ms-intrinsics.c

Index: test/CodeGen/ms-intrinsics.c
===
--- test/CodeGen/ms-intrinsics.c
+++ test/CodeGen/ms-intrinsics.c
@@ -890,6 +890,102 @@
 // CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i64, i1 } [[TMP]], 0
 // CHECK-ARM-ARM64: ret i64 [[RESULT]]
 // CHECK-ARM-ARM64: }
+
+char test_InterlockedOr8_acq(char volatile *value, char mask) {
+  return _InterlockedOr8_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedOr8_acq(i8*{{[a-z_ ]*}}%value, i8{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw or i8* %value, i8 %mask acquire
+// CHECK-ARM-ARM64:   ret i8 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+char test_InterlockedOr8_rel(char volatile *value, char mask) {
+  return _InterlockedOr8_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedOr8_rel(i8*{{[a-z_ ]*}}%value, i8{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw or i8* %value, i8 %mask release
+// CHECK-ARM-ARM64:   ret i8 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+char test_InterlockedOr8_nf(char volatile *value, char mask) {
+  return _InterlockedOr8_nf(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedOr8_nf(i8*{{[a-z_ ]*}}%value, i8{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw or i8* %value, i8 %mask monotonic
+// CHECK-ARM-ARM64:   ret i8 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedOr16_acq(short volatile *value, short mask) {
+  return _InterlockedOr16_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedOr16_acq(i16*{{[a-z_ ]*}}%value, i16{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw or i16* %value, i16 %mask acquire
+// CHECK-ARM-ARM64:   ret i16 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedOr16_rel(short volatile *value, short mask) {
+  return _InterlockedOr16_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedOr16_rel(i16*{{[a-z_ ]*}}%value, i16{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw or i16* %value, i16 %mask release
+// CHECK-ARM-ARM64:   ret i16 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedOr16_nf(short volatile *value, short mask) {
+  return _InterlockedOr16_nf(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedOr16_nf(i16*{{[a-z_ ]*}}%value, i16{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw or i16* %value, i16 %mask monotonic
+// CHECK-ARM-ARM64:   ret i16 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedOr_acq(long volatile *value, long mask) {
+  return _InterlockedOr_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedOr_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw or i32* %value, i32 %mask acquire
+// CHECK-ARM-ARM64:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedOr_rel(long volatile *value, long mask) {
+  return _InterlockedOr_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedOr_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw or i32* %value, i32 %mask release
+// CHECK-ARM-ARM64:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedOr_nf(long volatile *value, long mask) {
+  return _InterlockedOr_nf(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedOr_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw or i32* %value, i32 %mask monotonic
+// CHECK-ARM-ARM64:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+__int64 test_InterlockedOr64_acq(__int64 volatile *value, __int64 mask) {
+  return _InterlockedOr64_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedOr64_acq(i64*{{[a-z_ ]*}}%value, i64{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw or i64* %value, i64 %mask acquire
+// CHECK-ARM-ARM64:   ret i64 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+__int64 test_InterlockedOr64_rel(__int64 volatile *value, __int64 mask) {
+  return _InterlockedOr64_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedOr64_rel(i64*{{[a-z_ ]*}}%value, i64{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = ato

[PATCH] D54065: [COFF, ARM64] Implement InterlockedXor*_* builtins

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, efriedma, mstorsjo, TomTan.
Herald added subscribers: kristina, jfb, chrib, kristof.beyls, javed.absar.

This is fifth in a series of patches to move intrinsic defintions out of 
intrin.h.


Repository:
  rC Clang

https://reviews.llvm.org/D54065

Files:
  CodeGen/CGBuiltin.cpp
  CodeGen/ms-intrinsics.c
  Headers/intrin.h
  clang/Basic/BuiltinsAArch64.def
  clang/Basic/BuiltinsARM.def

Index: CodeGen/ms-intrinsics.c
===
--- CodeGen/ms-intrinsics.c
+++ CodeGen/ms-intrinsics.c
@@ -986,6 +986,102 @@
 // CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw or i64* %value, i64 %mask monotonic
 // CHECK-ARM-ARM64:   ret i64 [[RESULT:%[0-9]+]]
 // CHECK-ARM-ARM64: }
+
+char test_InterlockedXor8_acq(char volatile *value, char mask) {
+  return _InterlockedXor8_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedXor8_acq(i8*{{[a-z_ ]*}}%value, i8{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xor i8* %value, i8 %mask acquire
+// CHECK-ARM-ARM64:   ret i8 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+char test_InterlockedXor8_rel(char volatile *value, char mask) {
+  return _InterlockedXor8_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedXor8_rel(i8*{{[a-z_ ]*}}%value, i8{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xor i8* %value, i8 %mask release
+// CHECK-ARM-ARM64:   ret i8 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+char test_InterlockedXor8_nf(char volatile *value, char mask) {
+  return _InterlockedXor8_nf(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedXor8_nf(i8*{{[a-z_ ]*}}%value, i8{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xor i8* %value, i8 %mask monotonic
+// CHECK-ARM-ARM64:   ret i8 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedXor16_acq(short volatile *value, short mask) {
+  return _InterlockedXor16_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedXor16_acq(i16*{{[a-z_ ]*}}%value, i16{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xor i16* %value, i16 %mask acquire
+// CHECK-ARM-ARM64:   ret i16 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedXor16_rel(short volatile *value, short mask) {
+  return _InterlockedXor16_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedXor16_rel(i16*{{[a-z_ ]*}}%value, i16{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xor i16* %value, i16 %mask release
+// CHECK-ARM-ARM64:   ret i16 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedXor16_nf(short volatile *value, short mask) {
+  return _InterlockedXor16_nf(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedXor16_nf(i16*{{[a-z_ ]*}}%value, i16{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xor i16* %value, i16 %mask monotonic
+// CHECK-ARM-ARM64:   ret i16 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedXor_acq(long volatile *value, long mask) {
+  return _InterlockedXor_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedXor_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xor i32* %value, i32 %mask acquire
+// CHECK-ARM-ARM64:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedXor_rel(long volatile *value, long mask) {
+  return _InterlockedXor_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedXor_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xor i32* %value, i32 %mask release
+// CHECK-ARM-ARM64:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedXor_nf(long volatile *value, long mask) {
+  return _InterlockedXor_nf(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedXor_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xor i32* %value, i32 %mask monotonic
+// CHECK-ARM-ARM64:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+__int64 test_InterlockedXor64_acq(__int64 volatile *value, __int64 mask) {
+  return _InterlockedXor64_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedXor64_acq(i64*{{[a-z_ ]*}}%value, i64{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xor i64* %value, i64 %mask acquire
+// CHECK-ARM-ARM64:   ret i64 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+__int64 test_InterlockedXor64_rel(__int64 volatile *value, __int64 mask) {
+  return _InterlockedXor64_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedXor64_rel(i64*{{[a-z_ ]*}}%value, i64{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RE

[PATCH] D54066: [COFF, ARM64] Implement InterlockedAnd*_* builtins

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, efriedma, mstorsjo, TomTan.
Herald added subscribers: kristina, jfb, chrib, kristof.beyls, javed.absar.

This is sixth in a series of patches to move intrinsic definitions out of 
intrin.h.


Repository:
  rC Clang

https://reviews.llvm.org/D54066

Files:
  CodeGen/CGBuiltin.cpp
  CodeGen/ms-intrinsics.c
  Headers/intrin.h
  clang/Basic/BuiltinsAArch64.def
  clang/Basic/BuiltinsARM.def

Index: CodeGen/ms-intrinsics.c
===
--- CodeGen/ms-intrinsics.c
+++ CodeGen/ms-intrinsics.c
@@ -1082,6 +1082,102 @@
 // CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xor i64* %value, i64 %mask monotonic
 // CHECK-ARM-ARM64:   ret i64 [[RESULT:%[0-9]+]]
 // CHECK-ARM-ARM64: }
+
+char test_InterlockedAnd8_acq(char volatile *value, char mask) {
+  return _InterlockedAnd8_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedAnd8_acq(i8*{{[a-z_ ]*}}%value, i8{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw and i8* %value, i8 %mask acquire
+// CHECK-ARM-ARM64:   ret i8 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+char test_InterlockedAnd8_rel(char volatile *value, char mask) {
+  return _InterlockedAnd8_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedAnd8_rel(i8*{{[a-z_ ]*}}%value, i8{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw and i8* %value, i8 %mask release
+// CHECK-ARM-ARM64:   ret i8 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+char test_InterlockedAnd8_nf(char volatile *value, char mask) {
+  return _InterlockedAnd8_nf(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedAnd8_nf(i8*{{[a-z_ ]*}}%value, i8{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw and i8* %value, i8 %mask monotonic
+// CHECK-ARM-ARM64:   ret i8 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedAnd16_acq(short volatile *value, short mask) {
+  return _InterlockedAnd16_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedAnd16_acq(i16*{{[a-z_ ]*}}%value, i16{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw and i16* %value, i16 %mask acquire
+// CHECK-ARM-ARM64:   ret i16 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedAnd16_rel(short volatile *value, short mask) {
+  return _InterlockedAnd16_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedAnd16_rel(i16*{{[a-z_ ]*}}%value, i16{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw and i16* %value, i16 %mask release
+// CHECK-ARM-ARM64:   ret i16 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedAnd16_nf(short volatile *value, short mask) {
+  return _InterlockedAnd16_nf(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedAnd16_nf(i16*{{[a-z_ ]*}}%value, i16{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw and i16* %value, i16 %mask monotonic
+// CHECK-ARM-ARM64:   ret i16 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedAnd_acq(long volatile *value, long mask) {
+  return _InterlockedAnd_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedAnd_acq(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw and i32* %value, i32 %mask acquire
+// CHECK-ARM-ARM64:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedAnd_rel(long volatile *value, long mask) {
+  return _InterlockedAnd_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedAnd_rel(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw and i32* %value, i32 %mask release
+// CHECK-ARM-ARM64:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedAnd_nf(long volatile *value, long mask) {
+  return _InterlockedAnd_nf(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedAnd_nf(i32*{{[a-z_ ]*}}%value, i32{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw and i32* %value, i32 %mask monotonic
+// CHECK-ARM-ARM64:   ret i32 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+__int64 test_InterlockedAnd64_acq(__int64 volatile *value, __int64 mask) {
+  return _InterlockedAnd64_acq(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedAnd64_acq(i64*{{[a-z_ ]*}}%value, i64{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw and i64* %value, i64 %mask acquire
+// CHECK-ARM-ARM64:   ret i64 [[RESULT:%[0-9]+]]
+// CHECK-ARM-ARM64: }
+
+__int64 test_InterlockedAnd64_rel(__int64 volatile *value, __int64 mask) {
+  return _InterlockedAnd64_rel(value, mask);
+}
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedAnd64_rel(i64*{{[a-z_ ]*}}%value, i64{{[a-z_ ]*}}%mask){{.*}}{
+// CHECK-ARM-ARM64:   

[PATCH] D54067: [COFF, ARM64] Implement InterlockedIncrement*_* builtins

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, efriedma, mstorsjo, TomTan.
Herald added subscribers: kristina, jfb, chrib, kristof.beyls, javed.absar.

This is seventh in a series of patches to move intrinsic definitions out of 
intrin.h.


Repository:
  rC Clang

https://reviews.llvm.org/D54067

Files:
  CodeGen/CGBuiltin.cpp
  CodeGen/ms-intrinsics.c
  Headers/intrin.h
  clang/Basic/BuiltinsAArch64.def
  clang/Basic/BuiltinsARM.def

Index: CodeGen/ms-intrinsics.c
===
--- CodeGen/ms-intrinsics.c
+++ CodeGen/ms-intrinsics.c
@@ -1178,6 +1178,87 @@
 // CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw and i64* %value, i64 %mask monotonic
 // CHECK-ARM-ARM64:   ret i64 [[RESULT:%[0-9]+]]
 // CHECK-ARM-ARM64: }
+
+short test_InterlockedIncrement16_acq(short volatile *Addend) {
+  return _InterlockedIncrement16_acq(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedIncrement16_acq(i16*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add i16* %Addend, i16 1 acquire
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i16 [[TMP]], 1
+// CHECK-ARM-ARM64: ret i16 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedIncrement16_rel(short volatile *Addend) {
+  return _InterlockedIncrement16_rel(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedIncrement16_rel(i16*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add i16* %Addend, i16 1 release
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i16 [[TMP]], 1
+// CHECK-ARM-ARM64: ret i16 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedIncrement16_nf(short volatile *Addend) {
+  return _InterlockedIncrement16_nf(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedIncrement16_nf(i16*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add i16* %Addend, i16 1 monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i16 [[TMP]], 1
+// CHECK-ARM-ARM64: ret i16 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedIncrement_acq(long volatile *Addend) {
+  return _InterlockedIncrement_acq(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedIncrement_acq(i32*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add i32* %Addend, i32 1 acquire
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1
+// CHECK-ARM-ARM64: ret i32 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedIncrement_rel(long volatile *Addend) {
+  return _InterlockedIncrement_rel(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedIncrement_rel(i32*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add i32* %Addend, i32 1 release
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1
+// CHECK-ARM-ARM64: ret i32 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedIncrement_nf(long volatile *Addend) {
+  return _InterlockedIncrement_nf(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedIncrement_nf(i32*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add i32* %Addend, i32 1 monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1
+// CHECK-ARM-ARM64: ret i32 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+__int64 test_InterlockedIncrement64_acq(__int64 volatile *Addend) {
+  return _InterlockedIncrement64_acq(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedIncrement64_acq(i64*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add i64* %Addend, i64 1 acquire
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i64 [[TMP]], 1
+// CHECK-ARM-ARM64: ret i64 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+__int64 test_InterlockedIncrement64_rel(__int64 volatile *Addend) {
+  return _InterlockedIncrement64_rel(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedIncrement64_rel(i64*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add i64* %Addend, i64 1 release
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i64 [[TMP]], 1
+// CHECK-ARM-ARM64: ret i64 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+__int64 test_InterlockedIncrement64_nf(__int64 volatile *Addend) {
+  return _InterlockedIncrement64_nf(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedIncrement64_nf(i64*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add i64* %Addend, i64 1 monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i64 [[TMP]], 1
+// CHECK-ARM-ARM64: ret i64 [[RESULT]]
+// CHECK-ARM-ARM64: }
 #endif
 
 #if !defined(__aarch64__)
Index: Headers/intrin.h
===
--- Headers/intrin.h
+++ Headers/intrin.h
@@ -346,42 +346,15 @@
 |* Interlocked Increment
 \**/
 #if defined(__arm__) || defined(__aarch64__)
-static __inline__ short __DEFAULT_FN_ATTRS
-_InterlockedI

[PATCH] D54068: [COFF, ARM64] Implement InterlockedDecrement*_* builtins

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, efriedma, mstorsjo, TomTan.
Herald added subscribers: kristina, jfb, chrib, kristof.beyls, javed.absar.

This is eight in a series of patches to move intrinsic definitions out of 
intrin.h.


Repository:
  rC Clang

https://reviews.llvm.org/D54068

Files:
  CodeGen/CGBuiltin.cpp
  CodeGen/ms-intrinsics.c
  Headers/intrin.h
  clang/Basic/BuiltinsAArch64.def
  clang/Basic/BuiltinsARM.def

Index: CodeGen/ms-intrinsics.c
===
--- CodeGen/ms-intrinsics.c
+++ CodeGen/ms-intrinsics.c
@@ -1259,6 +1259,87 @@
 // CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i64 [[TMP]], 1
 // CHECK-ARM-ARM64: ret i64 [[RESULT]]
 // CHECK-ARM-ARM64: }
+
+short test_InterlockedDecrement16_acq(short volatile *Addend) {
+  return _InterlockedDecrement16_acq(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedDecrement16_acq(i16*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub i16* %Addend, i16 1 acquire
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i16 [[TMP]], -1
+// CHECK-ARM-ARM64: ret i16 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedDecrement16_rel(short volatile *Addend) {
+  return _InterlockedDecrement16_rel(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedDecrement16_rel(i16*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub i16* %Addend, i16 1 release
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i16 [[TMP]], -1
+// CHECK-ARM-ARM64: ret i16 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedDecrement16_nf(short volatile *Addend) {
+  return _InterlockedDecrement16_nf(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedDecrement16_nf(i16*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub i16* %Addend, i16 1 monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i16 [[TMP]], -1
+// CHECK-ARM-ARM64: ret i16 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedDecrement_acq(long volatile *Addend) {
+  return _InterlockedDecrement_acq(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedDecrement_acq(i32*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub i32* %Addend, i32 1 acquire
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1
+// CHECK-ARM-ARM64: ret i32 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedDecrement_rel(long volatile *Addend) {
+  return _InterlockedDecrement_rel(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedDecrement_rel(i32*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub i32* %Addend, i32 1 release
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1
+// CHECK-ARM-ARM64: ret i32 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedDecrement_nf(long volatile *Addend) {
+  return _InterlockedDecrement_nf(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedDecrement_nf(i32*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub i32* %Addend, i32 1 monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i32 [[TMP]], -1
+// CHECK-ARM-ARM64: ret i32 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+__int64 test_InterlockedDecrement64_acq(__int64 volatile *Addend) {
+  return _InterlockedDecrement64_acq(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedDecrement64_acq(i64*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub i64* %Addend, i64 1 acquire
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i64 [[TMP]], -1
+// CHECK-ARM-ARM64: ret i64 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+__int64 test_InterlockedDecrement64_rel(__int64 volatile *Addend) {
+  return _InterlockedDecrement64_rel(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedDecrement64_rel(i64*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub i64* %Addend, i64 1 release
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i64 [[TMP]], -1
+// CHECK-ARM-ARM64: ret i64 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+__int64 test_InterlockedDecrement64_nf(__int64 volatile *Addend) {
+  return _InterlockedDecrement64_nf(Addend);
+}
+// CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedDecrement64_nf(i64*{{[a-z_ ]*}}%Addend){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub i64* %Addend, i64 1 monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = add i64 [[TMP]], -1
+// CHECK-ARM-ARM64: ret i64 [[RESULT]]
+// CHECK-ARM-ARM64: }
 #endif
 
 #if !defined(__aarch64__)
Index: Headers/intrin.h
===
--- Headers/intrin.h
+++ Headers/intrin.h
@@ -360,42 +360,15 @@
 |* Interlocked Decrement
 \**/
 #if defined(__arm__) || defined(__aarch64__)
-static __inline__ short __DEFAULT_FN_ATTRS
-_InterlockedDecrement16_acq(short volatile *_V

[PATCH] D54062: [COFF, ARM64] Implement InterlockedCompareExchange*_* builtins

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added inline comments.



Comment at: include/clang/Basic/BuiltinsARM.def:270
+TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_nf,  "LLiLLiD*LLiLLi", 
"nh", "intrin.h", ALL_MS_LANGUAGES, "")
+TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_rel, "LLiLLiD*LLiLLi", 
"nh", "intrin.h", ALL_MS_LANGUAGES, "")
+

rnk wrote:
> Given how much duplication there is, I think we need to have some kind of 
> BuiltinsMSVC.def that contains a list of all the interlocked builitin 
> families, like this:
> ```
> INTERLOCKED_BUILTIN(_InterlockedCompareExchange)
> INTERLOCKED_BUILTIN(_InterlockedOr)
> INTERLOCKED_BUILTIN(_InterlockedAnd)
> ```
> We'd include this file here, with INTERLOCKED_BUILTIN defined as:
> ```
> #define INTERLOCKED_BUILTIN(Op) \
>   TARGET_HEADER_BUILTIN(Op##8_acq, "ccD*cc", "nh", "intrin.h", 
> ALL_MS_LANGUAGES, "") \
>   TARGET_HEADER_BUILTIN(Op##8_nf, "ccD*cc", "nh", "intrin.h", 
> ALL_MS_LANGUAGES, "") \
> ...
> ```
> That'll stamp out the enums that we need, and then we can reuse the .def file 
> to reduce duplication in the switch/case below.
> 
> Every op is basically 16 operations: {8, 16, 32, 64} X {seq_cst, rel, acq, nf}
> 
> I'm not sure what to do about the ones that overlap with x86.
Thanks Reid. Yes, I think we can certainly cleanup further. That being said, 
can we get these patches committed first and then cleanup in a follow-up patch?


Repository:
  rC Clang

https://reviews.llvm.org/D54062



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[PATCH] D54062: [COFF, ARM64] Implement InterlockedCompareExchange*_* builtins

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang updated this revision to Diff 172675.

https://reviews.llvm.org/D54062

Files:
  include/clang/Basic/BuiltinsAArch64.def
  include/clang/Basic/BuiltinsARM.def
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/intrin.h
  test/CodeGen/ms-intrinsics.c

Index: test/CodeGen/ms-intrinsics.c
===
--- test/CodeGen/ms-intrinsics.c
+++ test/CodeGen/ms-intrinsics.c
@@ -782,6 +782,114 @@
 // CHECK-ARM-ARM64:   [[RESULT:%[0-9]+]] = atomicrmw xchg i64* %value, i64 %mask monotonic
 // CHECK-ARM-ARM64:   ret i64 [[RESULT:%[0-9]+]]
 // CHECK-ARM-ARM64: }
+
+char test_InterlockedCompareExchange8_acq(char volatile *Destination, char Exchange, char Comperand) {
+  return _InterlockedCompareExchange8_acq(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedCompareExchange8_acq(i8*{{[a-z_ ]*}}%Destination, i8{{[a-z_ ]*}}%Exchange, i8{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i8* %Destination, i8 %Comperand, i8 %Exchange acquire acquire
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i8, i1 } [[TMP]], 0
+// CHECK-ARM-ARM64: ret i8 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+char test_InterlockedCompareExchange8_rel(char volatile *Destination, char Exchange, char Comperand) {
+  return _InterlockedCompareExchange8_rel(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedCompareExchange8_rel(i8*{{[a-z_ ]*}}%Destination, i8{{[a-z_ ]*}}%Exchange, i8{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i8* %Destination, i8 %Comperand, i8 %Exchange release monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i8, i1 } [[TMP]], 0
+// CHECK-ARM-ARM64: ret i8 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+char test_InterlockedCompareExchange8_nf(char volatile *Destination, char Exchange, char Comperand) {
+  return _InterlockedCompareExchange8_nf(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i8 @test_InterlockedCompareExchange8_nf(i8*{{[a-z_ ]*}}%Destination, i8{{[a-z_ ]*}}%Exchange, i8{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i8* %Destination, i8 %Comperand, i8 %Exchange monotonic monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i8, i1 } [[TMP]], 0
+// CHECK-ARM-ARM64: ret i8 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedCompareExchange16_acq(short volatile *Destination, short Exchange, short Comperand) {
+  return _InterlockedCompareExchange16_acq(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedCompareExchange16_acq(i16*{{[a-z_ ]*}}%Destination, i16{{[a-z_ ]*}}%Exchange, i16{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i16* %Destination, i16 %Comperand, i16 %Exchange acquire acquire
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i16, i1 } [[TMP]], 0
+// CHECK-ARM-ARM64: ret i16 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedCompareExchange16_rel(short volatile *Destination, short Exchange, short Comperand) {
+  return _InterlockedCompareExchange16_rel(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedCompareExchange16_rel(i16*{{[a-z_ ]*}}%Destination, i16{{[a-z_ ]*}}%Exchange, i16{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i16* %Destination, i16 %Comperand, i16 %Exchange release monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i16, i1 } [[TMP]], 0
+// CHECK-ARM-ARM64: ret i16 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+short test_InterlockedCompareExchange16_nf(short volatile *Destination, short Exchange, short Comperand) {
+  return _InterlockedCompareExchange16_nf(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedCompareExchange16_nf(i16*{{[a-z_ ]*}}%Destination, i16{{[a-z_ ]*}}%Exchange, i16{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i16* %Destination, i16 %Comperand, i16 %Exchange monotonic monotonic
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i16, i1 } [[TMP]], 0
+// CHECK-ARM-ARM64: ret i16 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedCompareExchange_acq(long volatile *Destination, long Exchange, long Comperand) {
+  return _InterlockedCompareExchange_acq(Destination, Exchange, Comperand);
+}
+// CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedCompareExchange_acq(i32*{{[a-z_ ]*}}%Destination, i32{{[a-z_ ]*}}%Exchange, i32{{[a-z_ ]*}}%Comperand){{.*}}{
+// CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = cmpxchg volatile i32* %Destination, i32 %Comperand, i32 %Exchange acquire acquire
+// CHECK-ARM-ARM64: [[RESULT:%[0-9]+]] = extractvalue { i32, i1 } [[TMP]], 0
+// CHECK-ARM-ARM64: ret i32 [[RESULT]]
+// CHECK-ARM-ARM64: }
+
+long test_InterlockedCompareExchange_rel(long volatile *Destination, long Exchange, long Comper

[PATCH] D54062: [COFF, ARM64] Implement InterlockedCompareExchange*_* builtins

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC346189: [COFF, ARM64] Implement 
InterlockedCompareExchange*_* builtins (authored by mgrang, committed by ).

Repository:
  rC Clang

https://reviews.llvm.org/D54062

Files:
  include/clang/Basic/BuiltinsAArch64.def
  include/clang/Basic/BuiltinsARM.def
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/intrin.h
  test/CodeGen/ms-intrinsics.c

Index: lib/Headers/intrin.h
===
--- lib/Headers/intrin.h
+++ lib/Headers/intrin.h
@@ -621,90 +621,30 @@
 |* Interlocked Compare Exchange
 \**/
 #if defined(__arm__) || defined(__aarch64__)
-static __inline__ char __DEFAULT_FN_ATTRS
-_InterlockedCompareExchange8_acq(char volatile *_Destination,
- char _Exchange, char _Comparand) {
-  __atomic_compare_exchange(_Destination, &_Comparand, &_Exchange, 0,
-__ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
-  return _Comparand;
-}
-static __inline__ char __DEFAULT_FN_ATTRS
-_InterlockedCompareExchange8_nf(char volatile *_Destination,
- char _Exchange, char _Comparand) {
-  __atomic_compare_exchange(_Destination, &_Comparand, &_Exchange, 0,
-__ATOMIC_SEQ_CST, __ATOMIC_RELAXED);
-  return _Comparand;
-}
-static __inline__ char __DEFAULT_FN_ATTRS
-_InterlockedCompareExchange8_rel(char volatile *_Destination,
- char _Exchange, char _Comparand) {
-  __atomic_compare_exchange(_Destination, &_Comparand, &_Exchange, 0,
-__ATOMIC_SEQ_CST, __ATOMIC_RELEASE);
-  return _Comparand;
-}
-static __inline__ short __DEFAULT_FN_ATTRS
-_InterlockedCompareExchange16_acq(short volatile *_Destination,
-  short _Exchange, short _Comparand) {
-  __atomic_compare_exchange(_Destination, &_Comparand, &_Exchange, 0,
-__ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
-  return _Comparand;
-}
-static __inline__ short __DEFAULT_FN_ATTRS
-_InterlockedCompareExchange16_nf(short volatile *_Destination,
-  short _Exchange, short _Comparand) {
-  __atomic_compare_exchange(_Destination, &_Comparand, &_Exchange, 0,
-__ATOMIC_SEQ_CST, __ATOMIC_RELAXED);
-  return _Comparand;
-}
-static __inline__ short __DEFAULT_FN_ATTRS
-_InterlockedCompareExchange16_rel(short volatile *_Destination,
-  short _Exchange, short _Comparand) {
-  __atomic_compare_exchange(_Destination, &_Comparand, &_Exchange, 0,
-__ATOMIC_SEQ_CST, __ATOMIC_RELEASE);
-  return _Comparand;
-}
-static __inline__ long __DEFAULT_FN_ATTRS
-_InterlockedCompareExchange_acq(long volatile *_Destination,
-  long _Exchange, long _Comparand) {
-  __atomic_compare_exchange(_Destination, &_Comparand, &_Exchange, 0,
-__ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
-  return _Comparand;
-}
-static __inline__ long __DEFAULT_FN_ATTRS
-_InterlockedCompareExchange_nf(long volatile *_Destination,
-  long _Exchange, long _Comparand) {
-  __atomic_compare_exchange(_Destination, &_Comparand, &_Exchange, 0,
-__ATOMIC_SEQ_CST, __ATOMIC_RELAXED);
-  return _Comparand;
-}
-static __inline__ long __DEFAULT_FN_ATTRS
-_InterlockedCompareExchange_rel(long volatile *_Destination,
-  long _Exchange, long _Comparand) {
-  __atomic_compare_exchange(_Destination, &_Comparand, &_Exchange, 0,
-__ATOMIC_SEQ_CST, __ATOMIC_RELEASE);
-  return _Comparand;
-}
-static __inline__ __int64 __DEFAULT_FN_ATTRS
-_InterlockedCompareExchange64_acq(__int64 volatile *_Destination,
-  __int64 _Exchange, __int64 _Comparand) {
-  __atomic_compare_exchange(_Destination, &_Comparand, &_Exchange, 0,
-__ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
-  return _Comparand;
-}
-static __inline__ __int64 __DEFAULT_FN_ATTRS
-_InterlockedCompareExchange64_nf(__int64 volatile *_Destination,
-  __int64 _Exchange, __int64 _Comparand) {
-  __atomic_compare_exchange(_Destination, &_Comparand, &_Exchange, 0,
-__ATOMIC_SEQ_CST, __ATOMIC_RELAXED);
-  return _Comparand;
-}
-static __inline__ __int64 __DEFAULT_FN_ATTRS
-_InterlockedCompareExchange64_rel(__int64 volatile *_Destination,
-  __int64 _Exchange, __int64 _Comparand) {
-  __atomic_compare_exchange(_Destination, &_Comparand, &_Exchange, 0,
-__ATOMIC_SEQ_CST, __ATOMIC_RELEASE);
-  return _Comparand;
-}
+char _InterlockedCompareExchange8_acq(char volatile *_Destination,
+ char _Exchange, char _Comparand);
+char _InterlockedCompareExchange8_nf(char volatile *_De

[PATCH] D54065: [COFF, ARM64] Implement InterlockedXor*_* builtins

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC346191: [COFF, ARM64] Implement InterlockedXor*_* builtins 
(authored by mgrang, committed by ).
Herald added subscribers: aheejin, dschuff.

Changed prior to commit:
  https://reviews.llvm.org/D54065?vs=172480&id=172686#toc

Repository:
  rC Clang

https://reviews.llvm.org/D54065

Files:
  CodeGen/CGBuiltin.cpp
  CodeGen/ms-intrinsics.c
  Headers/intrin.h
  clang/Basic/BuiltinsAArch64.def
  clang/Basic/BuiltinsARM.def
  include/clang/Basic/BuiltinsAArch64.def
  include/clang/Basic/BuiltinsARM.def
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/intrin.h
  test/CodeGen/ms-intrinsics.c



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[PATCH] D54816: [RISCV] Mark unit tests as "requires: riscv-registered-target"

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: asb, apazos.
Herald added subscribers: jocewei, PkmX, rkruppe, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar.

Some of these tests break if the RISCV backend has not been built.


Repository:
  rC Clang

https://reviews.llvm.org/D54816

Files:
  Driver/riscv-abi.c
  Driver/riscv-arch.c
  Driver/riscv-features.c
  Driver/riscv-gnutools.c
  Driver/riscv32-toolchain.c
  Driver/riscv64-toolchain.c


Index: Driver/riscv64-toolchain.c
===
--- Driver/riscv64-toolchain.c
+++ Driver/riscv64-toolchain.c
@@ -1,3 +1,5 @@
+// REQUIRES: riscv-registered-target
+
 // A basic clang -cc1 command-line, and simple environment check.
 
 // RUN: %clang %s -### -no-canonical-prefixes -target riscv64 2>&1 | FileCheck 
-check-prefix=CC1 %s
Index: Driver/riscv32-toolchain.c
===
--- Driver/riscv32-toolchain.c
+++ Driver/riscv32-toolchain.c
@@ -1,3 +1,5 @@
+// REQUIRES: riscv-registered-target
+
 // A basic clang -cc1 command-line, and simple environment check.
 
 // RUN: %clang %s -### -no-canonical-prefixes -target riscv32 2>&1 | FileCheck 
-check-prefix=CC1 %s
Index: Driver/riscv-gnutools.c
===
--- Driver/riscv-gnutools.c
+++ Driver/riscv-gnutools.c
@@ -1,3 +1,5 @@
+// REQUIRES: riscv-registered-target
+
 // Check gnutools are invoked with propagated values for -mabi and -march.
 
 // RUN: %clang -target riscv32 -fno-integrated-as %s -###  -c \
Index: Driver/riscv-features.c
===
--- Driver/riscv-features.c
+++ Driver/riscv-features.c
@@ -1,3 +1,5 @@
+// REQUIRES: riscv-registered-target
+
 // RUN: %clang -target riscv32-unknown-elf -### %s -fsyntax-only 2>&1 | 
FileCheck %s
 // RUN: %clang -target riscv64-unknown-elf -### %s -fsyntax-only 2>&1 | 
FileCheck %s
 
Index: Driver/riscv-arch.c
===
--- Driver/riscv-arch.c
+++ Driver/riscv-arch.c
@@ -1,3 +1,5 @@
+// REQUIRES: riscv-registered-target
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck %s
 // RUN: %clang -target riscv32-unknown-elf -march=rv32im -### %s \
Index: Driver/riscv-abi.c
===
--- Driver/riscv-abi.c
+++ Driver/riscv-abi.c
@@ -1,3 +1,5 @@
+// REQUIRES: riscv-registered-target
+
 // RUN: %clang -target riscv32-unknown-elf %s -### -o %t.o 2>&1 \
 // RUN:   | FileCheck -check-prefix=CHECK-ILP32 %s
 // RUN: %clang -target riscv32-unknown-elf %s -### -o %t.o -mabi=ilp32 2>&1 \


Index: Driver/riscv64-toolchain.c
===
--- Driver/riscv64-toolchain.c
+++ Driver/riscv64-toolchain.c
@@ -1,3 +1,5 @@
+// REQUIRES: riscv-registered-target
+
 // A basic clang -cc1 command-line, and simple environment check.
 
 // RUN: %clang %s -### -no-canonical-prefixes -target riscv64 2>&1 | FileCheck -check-prefix=CC1 %s
Index: Driver/riscv32-toolchain.c
===
--- Driver/riscv32-toolchain.c
+++ Driver/riscv32-toolchain.c
@@ -1,3 +1,5 @@
+// REQUIRES: riscv-registered-target
+
 // A basic clang -cc1 command-line, and simple environment check.
 
 // RUN: %clang %s -### -no-canonical-prefixes -target riscv32 2>&1 | FileCheck -check-prefix=CC1 %s
Index: Driver/riscv-gnutools.c
===
--- Driver/riscv-gnutools.c
+++ Driver/riscv-gnutools.c
@@ -1,3 +1,5 @@
+// REQUIRES: riscv-registered-target
+
 // Check gnutools are invoked with propagated values for -mabi and -march.
 
 // RUN: %clang -target riscv32 -fno-integrated-as %s -###  -c \
Index: Driver/riscv-features.c
===
--- Driver/riscv-features.c
+++ Driver/riscv-features.c
@@ -1,3 +1,5 @@
+// REQUIRES: riscv-registered-target
+
 // RUN: %clang -target riscv32-unknown-elf -### %s -fsyntax-only 2>&1 | FileCheck %s
 // RUN: %clang -target riscv64-unknown-elf -### %s -fsyntax-only 2>&1 | FileCheck %s
 
Index: Driver/riscv-arch.c
===
--- Driver/riscv-arch.c
+++ Driver/riscv-arch.c
@@ -1,3 +1,5 @@
+// REQUIRES: riscv-registered-target
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck %s
 // RUN: %clang -target riscv32-unknown-elf -march=rv32im -### %s \
Index: Driver/riscv-abi.c
===
--- Driver/riscv-abi.c
+++ Driver/riscv-abi.c
@@ -1,3 +1,5 @@
+// REQUIRES: riscv-registered-target
+
 // RUN: %clang -target riscv32-unknown-elf %s -### -o %t.o 

[PATCH] D54816: [RISCV] Mark unit tests as "requires: riscv-registered-target"

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang added a comment.

Ping for reviews please.


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54816/new/

https://reviews.llvm.org/D54816



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[PATCH] D54816: [RISCV] Mark unit tests as "requires: riscv-registered-target"

[Mandeep Singh Grang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL347688: [RISCV] Mark unit tests as "requires: 
riscv-registered-target" (authored by mgrang, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D54816?vs=174988&id=175541#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54816/new/

https://reviews.llvm.org/D54816

Files:
  cfe/trunk/Driver/riscv-abi.c
  cfe/trunk/Driver/riscv-arch.c
  cfe/trunk/Driver/riscv-features.c
  cfe/trunk/Driver/riscv-gnutools.c
  cfe/trunk/Driver/riscv32-toolchain.c
  cfe/trunk/Driver/riscv64-toolchain.c
  cfe/trunk/test/Driver/riscv-abi.c
  cfe/trunk/test/Driver/riscv-arch.c
  cfe/trunk/test/Driver/riscv-features.c
  cfe/trunk/test/Driver/riscv-gnutools.c
  cfe/trunk/test/Driver/riscv32-toolchain.c
  cfe/trunk/test/Driver/riscv64-toolchain.c

Index: cfe/trunk/Driver/riscv-features.c
===
--- cfe/trunk/Driver/riscv-features.c
+++ cfe/trunk/Driver/riscv-features.c
@@ -0,0 +1,15 @@
+// REQUIRES: riscv-registered-target
+
+// RUN: %clang -target riscv32-unknown-elf -### %s -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -### %s -fsyntax-only 2>&1 | FileCheck %s
+
+// CHECK: fno-signed-char
+
+// RUN: %clang -target riscv32-unknown-elf -### %s -mrelax 2>&1 | FileCheck %s -check-prefix=RELAX
+// RUN: %clang -target riscv32-unknown-elf -### %s -mno-relax 2>&1 | FileCheck %s -check-prefix=NO-RELAX
+// RUN: %clang -target riscv32-unknown-elf -### %s 2>&1 | FileCheck %s -check-prefix=DEFAULT
+
+// RELAX: "-target-feature" "+relax"
+// NO-RELAX: "-target-feature" "-relax"
+// DEFAULT-NOT: "-target-feature" "+relax"
+// DEFAULT-NOT: "-target-feature" "-relax"
Index: cfe/trunk/Driver/riscv-arch.c
===
--- cfe/trunk/Driver/riscv-arch.c
+++ cfe/trunk/Driver/riscv-arch.c
@@ -0,0 +1,319 @@
+// REQUIRES: riscv-registered-target
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32im -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ima -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imaf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imafd -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ic -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imc -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imac -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imafc -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32imafdc -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ia -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iaf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iafd -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iac -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iafc -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iafdc -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32g -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32-unknown-elf -march=rv32gc -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64i -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64im -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64ima -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imaf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imafd -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64ic -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imc -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64-unknown-elf -march=rv64imac -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
+// RUN: %c

[PATCH] D55229: [COFF, ARM64] Make -flto-visibility-public-std a driver and cc1 flag

[Mandeep Singh Grang via Phabricator via cfe-commits]

mgrang created this revision.
mgrang added reviewers: rnk, mstorsjo, efriedma, TomTan.
Herald added subscribers: dexonsmith, kristof.beyls, inglorion, javed.absar, 
mehdi_amini.

Clang currently imports certain functions (like __imp__CxxThrowException) even 
when statically linking.
Whereas MSVC statically links them (like __CxxThrowException). In clang, 
function linkage is controlled via /MT 
flag which is a clang-cl flag. This flag gets expanded to 
-flto-visibility-public-std which is a -cc1 option.
So from clang driver there is no way to statically link these functions. This 
patch makes -flto-visibility-public-std a
 driver flag which can be used to control function linkage.


Repository:
  rC Clang

https://reviews.llvm.org/D55229

Files:
  CodeGen/arm64-microsoft-symbol-linkage.cpp
  Driver/ToolChains/Clang.cpp
  clang/Driver/CC1Options.td
  clang/Driver/Options.td


Index: CodeGen/arm64-microsoft-symbol-linkage.cpp
===
--- /dev/null
+++ CodeGen/arm64-microsoft-symbol-linkage.cpp
@@ -0,0 +1,29 @@
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clangxx -target aarch64-windows \
+// RUN: -fcxx-exceptions -emit-obj -c -o - %s \
+// RUN: | llvm-objdump -syms - 2>&1 | FileCheck %s --check-prefix LINK-DYN
+
+// RUN: %clangxx -target aarch64-windows -flto-visibility-public-std \
+// RUN: -fcxx-exceptions -emit-obj -c -o - %s \
+// RUN: | llvm-objdump -syms - 2>&1 | FileCheck %s --check-prefix LINK-STAT
+
+void foo1() { throw 1; }
+// CHECK-LABEL: foo1
+// LINK-DYN: __imp__CxxThrowException
+// LINK-STAT-NOT: __imp__CxxThrowException
+
+void bar();
+void foo2() noexcept(true) { bar(); }
+// CHECK-LABEL: foo2
+// LINK-DYN: __imp___std_terminate
+// LINK-STAT-NOT: __imp___std_terminate
+
+struct A {};
+struct B { virtual void f(); };
+struct C : A, virtual B {};
+struct T {};
+T *foo3() { return dynamic_cast((C *)0); }
+// CHECK-LABEL: foo3
+// LINK-DYN: __imp___RTDynamicCast
+// LINK-STAT-NOT: __imp___RTDynamicCast
Index: Driver/ToolChains/Clang.cpp
===
--- Driver/ToolChains/Clang.cpp
+++ Driver/ToolChains/Clang.cpp
@@ -5210,6 +5210,9 @@
TC.useIntegratedAs()))
 CmdArgs.push_back("-faddrsig");
 
+  if (Args.hasArg(options::OPT_flto_visibility_public_std))
+CmdArgs.push_back("-flto-visibility-public-std");
+
   // Finally add the compile command to the compilation.
   if (Args.hasArg(options::OPT__SLASH_fallback) &&
   Output.getType() == types::TY_Object &&
Index: clang/Driver/Options.td
===
--- clang/Driver/Options.td
+++ clang/Driver/Options.td
@@ -825,6 +825,9 @@
 def fcreate_profile : Flag<["-"], "fcreate-profile">, Group;
 def fcxx_exceptions: Flag<["-"], "fcxx-exceptions">, Group,
   HelpText<"Enable C++ exceptions">, Flags<[CC1Option]>;
+def flto_visibility_public_std:
+Flag<["-"], "flto-visibility-public-std">, Group, 
Flags<[CC1Option]>,
+HelpText<"Use public LTO visibility for classes in std and stdext 
namespaces">;
 def fcxx_modules : Flag <["-"], "fcxx-modules">, Group,
   Flags<[DriverOption]>;
 def fdebug_pass_arguments : Flag<["-"], "fdebug-pass-arguments">, 
Group;
Index: clang/Driver/CC1Options.td
===
--- clang/Driver/CC1Options.td
+++ clang/Driver/CC1Options.td
@@ -345,9 +345,6 @@
 def fprofile_instrument_use_path_EQ :
 Joined<["-"], "fprofile-instrument-use-path=">,
 HelpText<"Specify the profile path in PGO use compilation">;
-def flto_visibility_public_std:
-Flag<["-"], "flto-visibility-public-std">,
-HelpText<"Use public LTO visibility for classes in std and stdext 
namespaces">;
 def flto_unit: Flag<["-"], "flto-unit">,
 HelpText<"Emit IR to support LTO unit features (CFI, whole program vtable 
opt)">;
 def fno_lto_unit: Flag<["-"], "fno-lto-unit">;


Index: CodeGen/arm64-microsoft-symbol-linkage.cpp
===
--- /dev/null
+++ CodeGen/arm64-microsoft-symbol-linkage.cpp
@@ -0,0 +1,29 @@
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clangxx -target aarch64-windows \
+// RUN: -fcxx-exceptions -emit-obj -c -o - %s \
+// RUN: | llvm-objdump -syms - 2>&1 | FileCheck %s --check-prefix LINK-DYN
+
+// RUN: %clangxx -target aarch64-windows -flto-visibility-public-std \
+// RUN: -fcxx-exceptions -emit-obj -c -o - %s \
+// RUN: | llvm-objdump -syms - 2>&1 | FileCheck %s --check-prefix LINK-STAT
+
+void foo1() { throw 1; }
+// CHECK-LABEL: foo1
+// LINK-DYN: __imp__CxxThrowException
+// LINK-STAT-NOT: __imp__CxxThrowException
+
+void bar();
+void foo2() noexcept(true) { bar(); }
+// CHECK-LABEL: foo2
+// LINK-DYN: __imp___std_terminate
+// LINK-STAT-NOT: __imp___std_terminate
+
+struct A {};
+struct B { virtual void f(); };
+struct C : A, virtual B {};
+struct T {};
+T *foo3() { return dynamic_cast((C *)0); }
+// CH