[PATCH] D132285: [Clang][LoongArch] Implement ABI lowering

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

ping.


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[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining created this revision.
SixWeining added reviewers: xen0n, xry111, MaskRay, rengolin.
Herald added subscribers: StephenFan, krytarowski, mgorny.
Herald added a project: All.
SixWeining requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

With the initial support added, clang can compile simple .c
to executable file for loongarch64. For example:

$ cat main.c
int main() {

  return 0;

}
$ clang --target=loongarch64-linux-gnu --gcc-toolchain=xxx --sysroot=xxx main.c

Currently gcc toolchain and sysroot can be found here:
https://github.com/loongson/build-tools/releases/download/2022.05.29/loongarch64-clfs-5.0-cross-tools-gcc-glibc.tar.xz

Reference: https://github.com/loongson/LoongArch-Documentation
The last commit hash (main branch) is:
99016636af64d02dee05e39974d4c1e55875c45b

Note loongarch32 is not fully tested because there is no reference
gcc toolchain yet.

Depends on D130239 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130255

Files:
  clang/lib/Basic/CMakeLists.txt
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Clang.h
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/bin/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/include/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64d/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64f/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64s/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/bin/ld
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib64/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib64/.keep
  clang/test/Driver/frame-pointer.c
  clang/test/Driver/loongarch-abi.c
  clang/test/Driver/loongarch64-toolchain.c
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- /dev/null
+++ clang/test/Preprocessor/init-loongarch.c
@@ -0,0 +1,641 @@
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 < /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA32 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32-unknown-linux < /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA32,LA32-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 \
+// RUN: -fforce-enable-int128 < /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA32,LA32-INT128 %s
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 < /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA64 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64-unknown-linux < /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA64,LA64-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 \
+// RUN: -fforce-enable-int128 < /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA64,LA64-INT128 %s
+
+ Note that common macros are tested in init.c, such as __VERSION__. So they're not listed here.
+
+// LA32: #define _ILP32 1
+// LA32: #define __ATOMIC_ACQUIRE 2
+// LA32: #define __ATOMIC_ACQ_REL 4
+// LA32: #define __ATOMIC_CONSUME 1
+// LA32: #define __ATOMIC_RELAXED 0
+// LA32: #define __ATOMIC_RELEASE 3
+// LA32: #define __ATOMIC_SEQ_CST 5
+// LA32: #define __BIGGEST_ALIGNMENT__ 16
+// LA32: #define __BITINT_MAXWIDTH__ 128
+// LA32: #define __BOOL_WIDTH__ 8
+// LA32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// LA32: #define __CHAR16_TYPE__ unsigned short
+// LA32: #define __CHAR32_TYPE__ unsigned int
+// LA32: #define __CHAR_BIT__ 8
+// LA32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_INT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LLONG

[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 446688.
SixWeining marked 3 inline comments as done.
SixWeining added a comment.

Address @rengolin's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130255/new/

https://reviews.llvm.org/D130255

Files:
  clang/lib/Basic/CMakeLists.txt
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Clang.h
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/bin/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/include/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64d/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64f/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64s/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/bin/ld
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib64/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib64/.keep
  clang/test/Driver/frame-pointer.c
  clang/test/Driver/loongarch-abi-error.c
  clang/test/Driver/loongarch-abi.c
  clang/test/Driver/loongarch64-toolchain.c
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- /dev/null
+++ clang/test/Preprocessor/init-loongarch.c
@@ -0,0 +1,641 @@
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 < /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA32 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32-unknown-linux < /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA32,LA32-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 \
+// RUN: -fforce-enable-int128 < /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA32,LA32-INT128 %s
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 < /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA64 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64-unknown-linux < /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA64,LA64-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 \
+// RUN: -fforce-enable-int128 < /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA64,LA64-INT128 %s
+
+ Note that common macros are tested in init.c, such as __VERSION__. So they're not listed here.
+
+// LA32: #define _ILP32 1
+// LA32: #define __ATOMIC_ACQUIRE 2
+// LA32: #define __ATOMIC_ACQ_REL 4
+// LA32: #define __ATOMIC_CONSUME 1
+// LA32: #define __ATOMIC_RELAXED 0
+// LA32: #define __ATOMIC_RELEASE 3
+// LA32: #define __ATOMIC_SEQ_CST 5
+// LA32: #define __BIGGEST_ALIGNMENT__ 16
+// LA32: #define __BITINT_MAXWIDTH__ 128
+// LA32: #define __BOOL_WIDTH__ 8
+// LA32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// LA32: #define __CHAR16_TYPE__ unsigned short
+// LA32: #define __CHAR32_TYPE__ unsigned int
+// LA32: #define __CHAR_BIT__ 8
+// LA32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_INT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 1
+// LA32: #define __DBL_DECIMAL_DIG__ 17
+// LA32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// LA32: #define __DBL_DIG__ 15
+// LA32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// LA32: #define __DBL_HAS_DENORM__ 1
+// LA32: #define __DBL_HAS_INFINITY__ 1
+// LA32: #define __DBL_HAS_QUIET_NAN__ 1
+// LA32: #define __DBL_MANT_DIG__ 53
+// LA32: #define __DBL_MAX_10_EXP__ 308
+// LA32: #define __DBL_MAX_EXP__ 1024
+// LA32: #define __DBL_MAX__ 1.7976931348623157e+308
+// LA32: #define __DBL_MIN

[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D130255#3668436 , @rengolin wrote:

> This looks great, thanks!
>
> Exciting that we can finally go all the way from C source to LoongArch binary.
>
> The changes look good to me, other than a few nits. But please wait for a day 
> or two for other people to review on their own time.

Thanks, Renato.

Because relocation hasn't been added to the backend, complex code (e.g. with 
function call) can't been compiled currently.
But at least, as you said,  we finally go all the way from C source to 
LoongArch binary. This is a start and further implementation will be added 
later.




Comment at: clang/lib/Basic/Targets/LoongArch.h:69
+// TODO: select appropriate ABI.
+ABI = "ilp32d";
+  }

rengolin wrote:
> nit: this should use `setABI`. Right now, there's no difference, but once the 
> function does more (like setting other ABI flags), you won't need to change 
> it here. Same for the 64-bit version.
Thanks. No problem.



Comment at: clang/lib/Driver/ToolChains/Arch/LoongArch.h:25
+} // end namespace loongarch
+} // namespace tools
+} // end namespace driver

rengolin wrote:
> nit: comment mismatch "end"
Thanks.



Comment at: clang/test/Driver/loongarch-abi.c:41
+
+// CHECK-LA32-LP64S: error: unknown target ABI 'lp64s'
+// CHECK-LA32-LP64F: error: unknown target ABI 'lp64f'

rengolin wrote:
> please, split between pass and error by adding a new `loongarch-abi-error.c` 
> and adding the `error` tests to it.
Thanks. No problem.


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[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 446705.
SixWeining marked 9 inline comments as done.
SixWeining added a comment.

Address @MaskRay's comments. Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130255/new/

https://reviews.llvm.org/D130255

Files:
  clang/lib/Basic/CMakeLists.txt
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Clang.h
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/bin/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/include/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64d/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64f/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64s/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/bin/ld
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib64/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib64/.keep
  clang/test/Driver/frame-pointer.c
  clang/test/Driver/loongarch-abi-error.c
  clang/test/Driver/loongarch-abi.c
  clang/test/Driver/loongarch64-toolchain.c
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- /dev/null
+++ clang/test/Preprocessor/init-loongarch.c
@@ -0,0 +1,641 @@
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA32 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA32,LA32-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA32,LA32-INT128 %s
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA64 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA64,LA64-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA64,LA64-INT128 %s
+
+ Note that common macros are tested in init.c, such as __VERSION__. So they're not listed here.
+
+// LA32: #define _ILP32 1
+// LA32: #define __ATOMIC_ACQUIRE 2
+// LA32-NEXT: #define __ATOMIC_ACQ_REL 4
+// LA32-NEXT: #define __ATOMIC_CONSUME 1
+// LA32-NEXT: #define __ATOMIC_RELAXED 0
+// LA32-NEXT: #define __ATOMIC_RELEASE 3
+// LA32-NEXT: #define __ATOMIC_SEQ_CST 5
+// LA32: #define __BIGGEST_ALIGNMENT__ 16
+// LA32: #define __BITINT_MAXWIDTH__ 128
+// LA32: #define __BOOL_WIDTH__ 8
+// LA32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// LA32: #define __CHAR16_TYPE__ unsigned short
+// LA32: #define __CHAR32_TYPE__ unsigned int
+// LA32: #define __CHAR_BIT__ 8
+// LA32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_INT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 1
+// LA32: #define __DBL_DECIMAL_DIG__ 17
+// LA32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// LA32: #define __DBL_DIG__ 15
+// LA32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// LA32: #define __DBL_HAS_DENORM__ 1
+// LA32: #define __DBL_HAS_INFINITY__ 1
+// LA32: #define __DBL_HAS_QUIET_NAN__ 1
+// LA32: #define __DBL_MANT_DIG__ 53
+// LA32: #define __DBL_MAX_10_EXP__ 308
+// LA32: #define __DBL_MAX_EXP__ 1024
+// LA32: #define __DBL_MAX__ 1.7976931348623157e+308
+// LA3

[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining added inline comments.



Comment at: clang/lib/Basic/Targets/LoongArch.cpp:26
+  // TODO: To be implemented in future.
+  return ArrayRef();
+}

MaskRay wrote:
> `return {}`
Thanks.


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[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 446736.
SixWeining added a comment.

rebase


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Basic/CMakeLists.txt
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Clang.h
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/bin/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/include/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64d/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64f/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64s/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/bin/ld
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib64/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib64/.keep
  clang/test/Driver/frame-pointer.c
  clang/test/Driver/loongarch-abi-error.c
  clang/test/Driver/loongarch-abi.c
  clang/test/Driver/loongarch64-toolchain.c
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- /dev/null
+++ clang/test/Preprocessor/init-loongarch.c
@@ -0,0 +1,641 @@
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA32 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA32,LA32-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA32,LA32-INT128 %s
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA64 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA64,LA64-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA64,LA64-INT128 %s
+
+ Note that common macros are tested in init.c, such as __VERSION__. So they're not listed here.
+
+// LA32: #define _ILP32 1
+// LA32: #define __ATOMIC_ACQUIRE 2
+// LA32-NEXT: #define __ATOMIC_ACQ_REL 4
+// LA32-NEXT: #define __ATOMIC_CONSUME 1
+// LA32-NEXT: #define __ATOMIC_RELAXED 0
+// LA32-NEXT: #define __ATOMIC_RELEASE 3
+// LA32-NEXT: #define __ATOMIC_SEQ_CST 5
+// LA32: #define __BIGGEST_ALIGNMENT__ 16
+// LA32: #define __BITINT_MAXWIDTH__ 128
+// LA32: #define __BOOL_WIDTH__ 8
+// LA32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// LA32: #define __CHAR16_TYPE__ unsigned short
+// LA32: #define __CHAR32_TYPE__ unsigned int
+// LA32: #define __CHAR_BIT__ 8
+// LA32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_INT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 1
+// LA32: #define __DBL_DECIMAL_DIG__ 17
+// LA32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// LA32: #define __DBL_DIG__ 15
+// LA32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// LA32: #define __DBL_HAS_DENORM__ 1
+// LA32: #define __DBL_HAS_INFINITY__ 1
+// LA32: #define __DBL_HAS_QUIET_NAN__ 1
+// LA32: #define __DBL_MANT_DIG__ 53
+// LA32: #define __DBL_MAX_10_EXP__ 308
+// LA32: #define __DBL_MAX_EXP__ 1024
+// LA32: #define __DBL_MAX__ 1.7976931348623157e+308
+// LA32: #define __DBL_MIN_10_EXP__ (-307)
+// LA32: #define __DBL_MIN_EXP__ (-10

[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 447248.
SixWeining marked 5 inline comments as done.
SixWeining added a comment.

Continue to address @MaskRay's comments: LLVM_LIBRARY_VISIBILITY ...


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130255/new/

https://reviews.llvm.org/D130255

Files:
  clang/lib/Basic/CMakeLists.txt
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Clang.h
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/bin/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/include/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64d/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64f/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64s/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/bin/ld
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib64/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib64/.keep
  clang/test/Driver/frame-pointer.c
  clang/test/Driver/loongarch-abi-error.c
  clang/test/Driver/loongarch-abi.c
  clang/test/Driver/loongarch-toolchain.c
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- /dev/null
+++ clang/test/Preprocessor/init-loongarch.c
@@ -0,0 +1,641 @@
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA32 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA32,LA32-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA32,LA32-INT128 %s
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA64 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA64,LA64-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA64,LA64-INT128 %s
+
+ Note that common macros are tested in init.c, such as __VERSION__. So they're not listed here.
+
+// LA32: #define _ILP32 1
+// LA32: #define __ATOMIC_ACQUIRE 2
+// LA32-NEXT: #define __ATOMIC_ACQ_REL 4
+// LA32-NEXT: #define __ATOMIC_CONSUME 1
+// LA32-NEXT: #define __ATOMIC_RELAXED 0
+// LA32-NEXT: #define __ATOMIC_RELEASE 3
+// LA32-NEXT: #define __ATOMIC_SEQ_CST 5
+// LA32: #define __BIGGEST_ALIGNMENT__ 16
+// LA32: #define __BITINT_MAXWIDTH__ 128
+// LA32: #define __BOOL_WIDTH__ 8
+// LA32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// LA32: #define __CHAR16_TYPE__ unsigned short
+// LA32: #define __CHAR32_TYPE__ unsigned int
+// LA32: #define __CHAR_BIT__ 8
+// LA32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_INT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 1
+// LA32: #define __DBL_DECIMAL_DIG__ 17
+// LA32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// LA32: #define __DBL_DIG__ 15
+// LA32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// LA32: #define __DBL_HAS_DENORM__ 1
+// LA32: #define __DBL_HAS_INFINITY__ 1
+// LA32: #define __DBL_HAS_QUIET_NAN__ 1
+// LA32: #define __DBL_MANT_DIG__ 53
+// LA32: #define __DBL_MAX_10_EXP__ 308
+// LA32: #define __DBL_MAX_EXP__ 1024
+// LA32: #define __DBL_MAX__ 1

[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining added inline comments.



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:2226
 
+  static const char *const LoongArch64LibDirs[] = {"/lib64", "/lib"};
+  static const char *const LoongArch64Triples[] = {

MaskRay wrote:
> I don't know which of /lib64, /lib has been used. For purity, I'd hope that 
> we just have /lib, no multilib style /lib64
I also don't know the actual usage of /lib64 but I just tried and it works fine 
if I remove /lib64.



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:2478
+  // TODO: Handle loongarch32.
+  case llvm::Triple::loongarch64:
+LibDirs.append(begin(LoongArch64LibDirs), end(LoongArch64LibDirs));

MaskRay wrote:
> Just add loongarch32 in this patch. It is trivial
But I don't know how to handle loongarch32 because there isn't a loongarch32 
gcc toolchain available yet.



Comment at: clang/test/Driver/loongarch64-toolchain.c:20
+// C-LA64-LINUX-MULTI-LP64D: "-dynamic-linker" 
"/lib64/ld-linux-loongarch-lp64d.so.1"
+// C-LA64-LINUX-MULTI-LP64D: 
"{{.*}}/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/crtbegin.o"
+// C-LA64-LINUX-MULTI-LP64D: 
"-L{{.*}}/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0"

MaskRay wrote:
> Not using NEXT is somewhat brittle.
> 
> Perhaps add `loongarch-toolchain.c` instead. `riscv*-toolchain.c` are not 
> good examples to follow. You may check out linux-cross.cpp
Thanks.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining added inline comments.



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:2226
 
+  static const char *const LoongArch64LibDirs[] = {"/lib64", "/lib"};
+  static const char *const LoongArch64Triples[] = {

xry111 wrote:
> SixWeining wrote:
> > MaskRay wrote:
> > > I don't know which of /lib64, /lib has been used. For purity, I'd hope 
> > > that we just have /lib, no multilib style /lib64
> > I also don't know the actual usage of /lib64 but I just tried and it works 
> > fine if I remove /lib64.
> I don't like `lib64` too.  But for LoongArch LP64D, the path to ELF 
> interpreter is hard coded `/lib64/ld-linux-loongarch-lp64d.so.1` and it seems 
> too late to change it.  And LoongArch GCC installs libstdc++ etc. for LP64D 
> into $PREFIX/lib64 by default (like x86_64).
> 
> As a distro (LFS) maintainer: we are already hacking GCC code to get rid of 
> `/usr/lib64`.
Thanks for the quick reply. So I should keep the /lib64 here?


Repository:
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[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 447304.
SixWeining added a comment.

keep /lib64


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130255/new/

https://reviews.llvm.org/D130255

Files:
  clang/lib/Basic/CMakeLists.txt
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Clang.h
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/bin/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/include/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64d/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64f/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64s/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/bin/ld
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib64/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib64/.keep
  clang/test/Driver/frame-pointer.c
  clang/test/Driver/loongarch-abi-error.c
  clang/test/Driver/loongarch-abi.c
  clang/test/Driver/loongarch-toolchain.c
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- /dev/null
+++ clang/test/Preprocessor/init-loongarch.c
@@ -0,0 +1,641 @@
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA32 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA32,LA32-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA32,LA32-INT128 %s
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA64 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA64,LA64-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA64,LA64-INT128 %s
+
+ Note that common macros are tested in init.c, such as __VERSION__. So they're not listed here.
+
+// LA32: #define _ILP32 1
+// LA32: #define __ATOMIC_ACQUIRE 2
+// LA32-NEXT: #define __ATOMIC_ACQ_REL 4
+// LA32-NEXT: #define __ATOMIC_CONSUME 1
+// LA32-NEXT: #define __ATOMIC_RELAXED 0
+// LA32-NEXT: #define __ATOMIC_RELEASE 3
+// LA32-NEXT: #define __ATOMIC_SEQ_CST 5
+// LA32: #define __BIGGEST_ALIGNMENT__ 16
+// LA32: #define __BITINT_MAXWIDTH__ 128
+// LA32: #define __BOOL_WIDTH__ 8
+// LA32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// LA32: #define __CHAR16_TYPE__ unsigned short
+// LA32: #define __CHAR32_TYPE__ unsigned int
+// LA32: #define __CHAR_BIT__ 8
+// LA32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_INT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 1
+// LA32: #define __DBL_DECIMAL_DIG__ 17
+// LA32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// LA32: #define __DBL_DIG__ 15
+// LA32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// LA32: #define __DBL_HAS_DENORM__ 1
+// LA32: #define __DBL_HAS_INFINITY__ 1
+// LA32: #define __DBL_HAS_QUIET_NAN__ 1
+// LA32: #define __DBL_MANT_DIG__ 53
+// LA32: #define __DBL_MAX_10_EXP__ 308
+// LA32: #define __DBL_MAX_EXP__ 1024
+// LA32: #define __DBL_MAX__ 1.7976931348623157e+308
+// LA32: #define __DBL_MIN_10_EXP__ (-307)
+// LA32: #define __DBL_MIN_EXP__ (

[PATCH] D114505: [clang][unittests]Fix a clang unittest linking issue

[Lu Weining via Phabricator via cfe-commits]

SixWeining created this revision.
SixWeining added reviewers: cfe-commits, dexonsmith.
Herald added a subscriber: mgorny.
SixWeining requested review of this revision.
Herald added a project: clang.

Currently the clang/unittests/Basic/CMakeLists.txt links LLVMTestingSupport in 
an incorrect way that would cause `ninja check-clang` failing with a linking 
error like below:
/usr/bin/ld: 
tools/clang/unittests/Basic/CMakeFiles/BasicTests.dir/FileManagerTest.cpp.o: in 
function `(anonymous 
namespace)::FileManagerTest_getBypassFile_Test::TestBody()':
FileManagerTest.cpp:(.text._ZN12_GLOBAL__N_134FileManagerTest_getBypassFile_Test8TestBodyEv+0x3a3):
 undefined reference to `llvm::detail::TakeError(llvm::Error)'

This patch changes the linking method of LLVMTestingSupport from 
clang_target_link_libraries to target_link_libraries just like other tests do.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D114505

Files:
  clang/unittests/Basic/CMakeLists.txt


Index: clang/unittests/Basic/CMakeLists.txt
===
--- clang/unittests/Basic/CMakeLists.txt
+++ clang/unittests/Basic/CMakeLists.txt
@@ -18,5 +18,9 @@
   clangAST
   clangBasic
   clangLex
-  LLVMTestingSupport
   )
+
+target_link_libraries(BasicTests
+  PRIVATE
+  LLVMTestingSupport
+)


Index: clang/unittests/Basic/CMakeLists.txt
===
--- clang/unittests/Basic/CMakeLists.txt
+++ clang/unittests/Basic/CMakeLists.txt
@@ -18,5 +18,9 @@
   clangAST
   clangBasic
   clangLex
-  LLVMTestingSupport
   )
+
+target_link_libraries(BasicTests
+  PRIVATE
+  LLVMTestingSupport
+)
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[PATCH] D114505: [clang][unittests] Fix a clang unittest linking issue

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 389650.
SixWeining retitled this revision from "[clang][unittests]Fix a clang 
unittest linking issue" to "[clang][unittests] Fix a clang unittest linking 
issue".
SixWeining edited the summary of this revision.
SixWeining added a comment.
Herald added a subscriber: pengfei.

Modify the summary to be more descriptive.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114505/new/

https://reviews.llvm.org/D114505

Files:
  clang/unittests/Basic/CMakeLists.txt


Index: clang/unittests/Basic/CMakeLists.txt
===
--- clang/unittests/Basic/CMakeLists.txt
+++ clang/unittests/Basic/CMakeLists.txt
@@ -18,5 +18,9 @@
   clangAST
   clangBasic
   clangLex
-  LLVMTestingSupport
   )
+
+target_link_libraries(BasicTests
+  PRIVATE
+  LLVMTestingSupport
+)


Index: clang/unittests/Basic/CMakeLists.txt
===
--- clang/unittests/Basic/CMakeLists.txt
+++ clang/unittests/Basic/CMakeLists.txt
@@ -18,5 +18,9 @@
   clangAST
   clangBasic
   clangLex
-  LLVMTestingSupport
   )
+
+target_link_libraries(BasicTests
+  PRIVATE
+  LLVMTestingSupport
+)
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[PATCH] D114505: [clang][unittests] Fix a clang unittest linking issue

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 389696.
SixWeining added a comment.

diff1 and diff2 are the same, but diff1 build pass while diff2 build fail. So 
weird. Just reupload the patch to have a try. Sorry for the noise.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114505/new/

https://reviews.llvm.org/D114505

Files:
  clang/unittests/Basic/CMakeLists.txt


Index: clang/unittests/Basic/CMakeLists.txt
===
--- clang/unittests/Basic/CMakeLists.txt
+++ clang/unittests/Basic/CMakeLists.txt
@@ -18,5 +18,9 @@
   clangAST
   clangBasic
   clangLex
-  LLVMTestingSupport
   )
+
+target_link_libraries(BasicTests
+  PRIVATE
+  LLVMTestingSupport
+)


Index: clang/unittests/Basic/CMakeLists.txt
===
--- clang/unittests/Basic/CMakeLists.txt
+++ clang/unittests/Basic/CMakeLists.txt
@@ -18,5 +18,9 @@
   clangAST
   clangBasic
   clangLex
-  LLVMTestingSupport
   )
+
+target_link_libraries(BasicTests
+  PRIVATE
+  LLVMTestingSupport
+)
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[PATCH] D136146: [Clang][LoongArch] Handle -march/-m{single,double,soft}-float/-mfpu options

[Lu Weining via Phabricator via cfe-commits]

SixWeining created this revision.
SixWeining added reviewers: xen0n, xry111, MaskRay, wangleiat, gonglingqin.
Herald added subscribers: StephenFan, atanasyan, hiraditya, arichardson, 
sdardis.
Herald added a project: All.
SixWeining requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch adds options -march, -msingle-float, -mdouble-float,
-msoft-float and -mfpu for LoongArch.

Clang options `msingle_float` and `mdouble_float` are moved from
`m_mips_Features_Group` to `m_Group` because now more than targets use
them.

Reference:
https://github.com/loongson/LoongArch-Documentation/blob/main/docs/LoongArch-toolchain-conventions-EN.adoc

TODO: add -mtune.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136146

Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/loongarch-default-features.c
  clang/test/Driver/loongarch-march-error.c
  clang/test/Driver/loongarch-march.c
  clang/test/Driver/loongarch-mdouble-float.c
  clang/test/Driver/loongarch-mfpu-error.c
  clang/test/Driver/loongarch-mfpu.c
  clang/test/Driver/loongarch-msingle-float.c
  clang/test/Driver/loongarch-msoft-float.c
  llvm/include/llvm/Support/LoongArchTargetParser.def
  llvm/include/llvm/Support/LoongArchTargetParser.h
  llvm/lib/Support/CMakeLists.txt
  llvm/lib/Support/LoongArchTargetParser.cpp

Index: llvm/lib/Support/LoongArchTargetParser.cpp
===
--- /dev/null
+++ llvm/lib/Support/LoongArchTargetParser.cpp
@@ -0,0 +1,53 @@
+//==-- LoongArch64TargetParser - Parser for LoongArch64 features --*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements a target parser to recognise LoongArch hardware features
+// such as CPU/ARCH and extension names.
+//
+//===--===//
+
+#include "llvm/Support/LoongArchTargetParser.h"
+#include "llvm/ADT/StringSwitch.h"
+
+using namespace llvm;
+using namespace llvm::LoongArch;
+
+const FeatureInfo AllFeatures[] = {
+#define LOONGARCH_FEATURE(NAME, KIND) {NAME, KIND},
+#include "llvm/Support/LoongArchTargetParser.def"
+};
+
+const ArchInfo AllArchs[] = {
+#define LOONGARCH_ARCH(NAME, KIND, FEATURES)   \
+  {NAME, LoongArch::ArchKind::KIND, FEATURES},
+#include "llvm/Support/LoongArchTargetParser.def"
+};
+
+LoongArch::ArchKind LoongArch::parseArch(StringRef Arch) {
+  for (const auto A : AllArchs) {
+if (A.Name == Arch)
+  return A.Kind;
+  }
+
+  return LoongArch::ArchKind::AK_INVALID;
+}
+
+bool LoongArch::getArchFeatures(StringRef Arch,
+std::vector &Features) {
+  for (const auto A : AllArchs) {
+if (A.Name == Arch) {
+  for (const auto F : AllFeatures) {
+if ((A.Features & F.Kind) == F.Kind && F.Kind != FK_INVALID) {
+  Features.push_back(F.Name);
+}
+  }
+  return true;
+}
+  }
+  return false;
+}
Index: llvm/lib/Support/CMakeLists.txt
===
--- llvm/lib/Support/CMakeLists.txt
+++ llvm/lib/Support/CMakeLists.txt
@@ -188,6 +188,7 @@
   LineIterator.cpp
   Locale.cpp
   LockFileManager.cpp
+  LoongArchTargetParser.cpp
   LowLevelType.cpp
   ManagedStatic.cpp
   MathExtras.cpp
Index: llvm/include/llvm/Support/LoongArchTargetParser.h
===
--- /dev/null
+++ llvm/include/llvm/Support/LoongArchTargetParser.h
@@ -0,0 +1,74 @@
+//==-- LoongArch64TargetParser - Parser for LoongArch64 features --*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements a target parser to recognise LoongArch hardware features
+// such as CPU/ARCH and extension names.
+//
+//===--===//
+
+#ifndef LLVM_SUPPORT_LOONGARCHTARGETPARSER_H
+#define LLVM_SUPPORT_LOONGARCHTARGETPARSER_H
+
+#include "llvm/ADT/Triple.h"
+#include 
+
+namespace llvm {
+class StringRef;
+
+namespace LoongArch {
+
+enum FeatureKind : uint32_t {
+  FK_INVALID = 0,
+  FK_NONE = 1,
+
+  // 64-bit ISA is available.
+  FK_64BIT = 1 << 1,
+
+  // Single-pr

[PATCH] D136413: [Clang][LoongArch] Define more LoongArch specific built-in macros

[Lu Weining via Phabricator via cfe-commits]

SixWeining created this revision.
SixWeining added reviewers: xen0n, xry111, MaskRay, tangyouling, wangleiat, 
gonglingqin.
Herald added a subscriber: StephenFan.
Herald added a project: All.
SixWeining requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Define below macros accroding to LoongArch toolchain conventions [1].

__loongarch_grlen
__loongarch_frlen
__loongarch_lp64
__loongarch_hard_float
__loongarch_soft_float
__loongarch_single_float
__loongarch_double_float

Note:

1. __loongarch__ has been defined in earlier patch.
2. __loongarch_arch is not defined because I don't know how TargetInfo

can get the arch name specified by -march.

3. __loongarch_tune will be defined in future.

[1] 
https://loongson.github.io/LoongArch-Documentation/LoongArch-toolchain-conventions-EN.html

Depends on D136146 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136413

Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- clang/test/Preprocessor/init-loongarch.c
+++ clang/test/Preprocessor/init-loongarch.c
@@ -639,3 +639,83 @@
 // LA64-LINUX: #define __unix__ 1
 // LA64-LINUX: #define linux 1
 // LA64-LINUX: #define unix 1
+
+
+/// Check various macros prefixed with "__loongarch_" in different cases.
+/// "__loongarch__"" is not listed here as it has been checked above.
+
+// RUN: %clang --target=loongarch32 -mdouble-float -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA32-DOUBLE %s
+// RUN: %clang --target=loongarch32 -mfpu=64 -mabi=ilp32d -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA32-DOUBLE %s
+// LA32-DOUBLE: __loongarch_double_float 1
+// LA32-DOUBLE: __loongarch_frlen 64
+// LA32-DOUBLE: __loongarch_grlen 32
+// LA32-DOUBLE: __loongarch_hard_float 1
+// LA32-DOUBLE-NOT: __loongarch_lp64
+// LA32-DOUBLE-NOT: __loongarch_single_float
+// LA32-DOUBLE-NOT: __loongarch_soft_float
+
+// RUN: %clang --target=loongarch32 -msingle-float -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA32-SINGLE %s
+// RUN: %clang --target=loongarch32 -mfpu=32 -mabi=ilp32f -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA32-SINGLE %s
+// LA32-SINGLE-NOT: __loongarch_double_float
+// LA32-SINGLE: __loongarch_frlen 32
+// LA32-SINGLE: __loongarch_grlen 32
+// LA32-SINGLE: __loongarch_hard_float 1
+// LA32-SINGLE-NOT: __loongarch_lp64
+// LA32-SINGLE: __loongarch_single_float 1
+// LA32-SINGLE-NOT: __loongarch_soft_float
+
+// RUN: %clang --target=loongarch32 -msoft-float -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA32-SOFT %s
+// RUN: %clang --target=loongarch32 -mfpu=0 -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA32-SOFT %s
+// RUN: %clang --target=loongarch32 -mfpu=none -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA32-SOFT %s
+// LA32-SOFT-NOT: __loongarch_double_float
+// LA32-SOFT: __loongarch_frlen 0
+// LA32-SOFT: __loongarch_grlen 32
+// LA32-SOFT-NOT: __loongarch_hard_float
+// LA32-SOFT-NOT: __loongarch_lp64
+// LA32-SOFT-NOT: __loongarch_single_float
+// LA32-SOFT: __loongarch_soft_float 1
+
+// RUN: %clang --target=loongarch64 -mdouble-float -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA64-DOUBLE %s
+// RUN: %clang --target=loongarch64 -mfpu=64 -mabi=lp64d -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA64-DOUBLE %s
+// LA64-DOUBLE: __loongarch_double_float 1
+// LA64-DOUBLE: __loongarch_frlen 64
+// LA64-DOUBLE: __loongarch_grlen 64
+// LA64-DOUBLE: __loongarch_hard_float 1
+// LA64-DOUBLE: __loongarch_lp64 1
+// LA64-DOUBLE-NOT: __loongarch_single_float
+// LA64-DOUBLE-NOT: __loongarch_soft_float
+
+// RUN: %clang --target=loongarch64 -msingle-float -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA64-SINGLE %s
+// RUN: %clang --target=loongarch64 -mfpu=32 -mabi=lp64f -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA64-SINGLE %s
+// LA64-SINGLE-NOT: __loongarch_double_float
+// LA64-SINGLE: __loongarch_frlen 32
+// LA64-SINGLE: __loongarch_grlen 64
+// LA64-SINGLE: __loongarch_hard_float 1
+// LA64-SINGLE: __loongarch_lp64 1
+// LA64-SINGLE: __loongarch_single_float 1
+// LA64-SINGLE-NOT: __loongarch_soft_float
+
+// RUN: %clang --target=loongarch64 -msoft-float -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA64-SOFT %s
+// RUN: %clang --target=loongarch64 -mfpu=0 -mabi=lp64s -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA64-SOFT %s
+// RUN: %clang --target=loongarch64 -mfpu=none -mabi=lp64s -x c -E -dM %s -o - \
+// RUN:   | FileCheck --check-prefix=LA64-SOFT %s
+// LA64-SOFT-NOT: __loongarch_double_float
+// LA64-SOFT: __loongarch_frlen 0
+// LA64-SOFT: __loongarch_grlen 64
+// LA64-SOFT-NOT: __loongarch_hard_flo

[PATCH] D136413: [Clang][LoongArch] Define more LoongArch specific built-in macros

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D136413#3873216 , @xry111 wrote:

> Do we support `--target=loongarch64 -mabi=ilp32d` or `-mfpu=64 -mabi=lp64s` 
> combinations now?  If true I think we'll need test cases for such 
> combinations.

For `--target=loongarch64 -mabi=ilp32d`, I'm not sure about this. The ABI 
document doesn't clearly describe this. But in current llvm implementation, it 
is NOT supported. In 
`clang/lib/Basic/Targets/LoongArch.h:LoongArch64TargetInfo:setABI`:

  bool setABI(const std::string &Name) override {
if (Name == "lp64d" || Name == "lp64f" || Name == "lp64s") {
  ABI = Name;
  return true;
}
return false;
  }

For `-mfpu=64 -mabi=lp64s`, I think it is valid and I will add some tests. 
Similarly, `-mfpu=32 -mabi=lp64s`.

How about `-mfpu=64 -mabi=lp64f`?


Repository:
  rG LLVM Github Monorepo

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[PATCH] D136413: [Clang][LoongArch] Define more LoongArch specific built-in macros

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 469472.
SixWeining added a comment.

Add tests for more `-mfpu` and `-mabi` combinations.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136413/new/

https://reviews.llvm.org/D136413

Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- clang/test/Preprocessor/init-loongarch.c
+++ clang/test/Preprocessor/init-loongarch.c
@@ -639,3 +639,143 @@
 // LA64-LINUX: #define __unix__ 1
 // LA64-LINUX: #define linux 1
 // LA64-LINUX: #define unix 1
+
+
+/// Check various macros prefixed with "__loongarch_" in different cases.
+/// "__loongarch__"" is not listed here as it has been checked above.
+
+// RUN: %clang --target=loongarch32 -mfpu=64 -mabi=ilp32d -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU64-ILP32D %s
+// RUN: %clang --target=loongarch32 -mdouble-float -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU64-ILP32D %s
+// LA32-FPU64-ILP32D: __loongarch_double_float 1
+// LA32-FPU64-ILP32D-NEXT: __loongarch_frlen 64
+// LA32-FPU64-ILP32D-NEXT: __loongarch_grlen 32
+// LA32-FPU64-ILP32D-NEXT: __loongarch_hard_float 1
+// LA32-FPU64-ILP32D-NOT: __loongarch_lp64
+// LA32-FPU64-ILP32D-NOT: __loongarch_single_float
+// LA32-FPU64-ILP32D-NOT: __loongarch_soft_float
+
+// RUN: %clang --target=loongarch32 -mfpu=64 -mabi=ilp32f -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU64-ILP32F %s
+// LA32-FPU64-ILP32F-NOT: __loongarch_double_float
+// LA32-FPU64-ILP32F: __loongarch_frlen 64
+// LA32-FPU64-ILP32F-NEXT: __loongarch_grlen 32
+// LA32-FPU64-ILP32F-NEXT: __loongarch_hard_float 1
+// LA32-FPU64-ILP32F-NOT: __loongarch_lp64
+// LA32-FPU64-ILP32F-NEXT: __loongarch_single_float 1
+// LA32-FPU64-ILP32F-NOT: __loongarch_soft_float
+
+// RUN: %clang --target=loongarch32 -mfpu=64 -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU64-ILP32S %s
+// LA32-FPU64-ILP32S-NOT: __loongarch_double_float
+// LA32-FPU64-ILP32S: __loongarch_frlen 64
+// LA32-FPU64-ILP32S-NEXT: __loongarch_grlen 32
+// LA32-FPU64-ILP32S-NOT: __loongarch_hard_float
+// LA32-FPU64-ILP32S-NOT: __loongarch_lp64
+// LA32-FPU64-ILP32S-NOT: __loongarch_single_float
+// LA32-FPU64-ILP32S-NEXT: __loongarch_soft_float 1
+
+// RUN: %clang --target=loongarch32 -mfpu=32 -mabi=ilp32f -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU32-ILP32F %s
+// RUN: %clang --target=loongarch32 -msingle-float -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU32-ILP32F %s
+// LA32-FPU32-ILP32F-NOT: __loongarch_double_float
+// LA32-FPU32-ILP32F: __loongarch_frlen 32
+// LA32-FPU32-ILP32F-NEXT: __loongarch_grlen 32
+// LA32-FPU32-ILP32F-NEXT: __loongarch_hard_float 1
+// LA32-FPU32-ILP32F-NOT: __loongarch_lp64
+// LA32-FPU32-ILP32F-NEXT: __loongarch_single_float 1
+// LA32-FPU32-ILP32F-NOT: __loongarch_soft_float
+
+// RUN: %clang --target=loongarch32 -mfpu=32 -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU32-ILP32S %s
+// LA32-FPU32-ILP32S-NOT: __loongarch_double_float
+// LA32-FPU32-ILP32S: __loongarch_frlen 32
+// LA32-FPU32-ILP32S-NEXT: __loongarch_grlen 32
+// LA32-FPU32-ILP32S-NOT: __loongarch_hard_float
+// LA32-FPU32-ILP32S-NOT: __loongarch_lp64
+// LA32-FPU32-ILP32S-NOT: __loongarch_single_float
+// LA32-FPU32-ILP32S-NEXT: __loongarch_soft_float 1
+
+// RUN: %clang --target=loongarch32 -mfpu=0 -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU0-ILP32S %s
+// RUN: %clang --target=loongarch32 -mfpu=none -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU0-ILP32S %s
+// RUN: %clang --target=loongarch32 -msoft-float -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU0-ILP32S %s
+// LA32-FPU0-ILP32S-NOT: __loongarch_double_float
+// LA32-FPU0-ILP32S: __loongarch_frlen 0
+// LA32-FPU0-ILP32S-NEXT: __loongarch_grlen 32
+// LA32-FPU0-ILP32S-NOT: __loongarch_hard_float
+// LA32-FPU0-ILP32S-NOT: __loongarch_lp64
+// LA32-FPU0-ILP32S-NOT: __loongarch_single_float
+// LA32-FPU0-ILP32S-NEXT: __loongarch_soft_float 1
+
+// RUN: %clang --target=loongarch64 -mfpu=64 -mabi=lp64d -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA64-FPU64-LP64D %s
+// RUN: %clang --target=loongarch64 -mdouble-float -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA64-FPU64-LP64D %s
+// LA64-FPU64-LP64D: __loongarch_double_float 1
+// LA64-FPU64-LP64D-NEXT: __loongarch_frlen 64
+// LA64-FPU64-LP64D-NEXT: __loongarch_grlen 64
+// LA64-FPU

[PATCH] D136413: [Clang][LoongArch] Define more LoongArch specific built-in macros

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

> I've formatted the patch summary for you. Please familiarize yourself with 
> Markdown syntax so next time your rendering would look better.

Thanks. Got it.

> For minimum churn and hassle, I'm afraid we have to add it for now. I didn't 
> realize [[ 
> https://github.com/loongson/LoongArch-Documentation/pull/28#discussion_r917367794
>  | it's the equivalent of `__mips64` ]] until too much software has been 
> ported with it...

OK.


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[PATCH] D136413: [Clang][LoongArch] Define more LoongArch specific built-in macros

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 469497.
SixWeining added a comment.

Define `__loongarch64` which is equal to `__loongarch_grlen == 64`.


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Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- clang/test/Preprocessor/init-loongarch.c
+++ clang/test/Preprocessor/init-loongarch.c
@@ -322,6 +322,7 @@
 // LA32-LINUX: #define __gnu_linux__ 1
 // LA32-LINUX: #define __linux 1
 // LA32-LINUX: #define __linux__ 1
+// LA32-NOT: #define __loongarch64 1
 // LA32: #define __loongarch__ 1
 // LA32-LINUX: #define __unix 1
 // LA32-LINUX: #define __unix__ 1
@@ -634,8 +635,149 @@
 // LA64-LINUX: #define __gnu_linux__ 1
 // LA64-LINUX: #define __linux 1
 // LA64-LINUX: #define __linux__ 1
+// LA64: #define __loongarch64 1
 // LA64: #define __loongarch__ 1
 // LA64-LINUX: #define __unix 1
 // LA64-LINUX: #define __unix__ 1
 // LA64-LINUX: #define linux 1
 // LA64-LINUX: #define unix 1
+
+
+/// Check various macros prefixed with "__loongarch_" in different cases.
+/// "__loongarch__"" is not listed here as it has been checked above.
+
+// RUN: %clang --target=loongarch32 -mfpu=64 -mabi=ilp32d -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU64-ILP32D %s
+// RUN: %clang --target=loongarch32 -mdouble-float -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU64-ILP32D %s
+// LA32-FPU64-ILP32D: __loongarch_double_float 1
+// LA32-FPU64-ILP32D-NEXT: __loongarch_frlen 64
+// LA32-FPU64-ILP32D-NEXT: __loongarch_grlen 32
+// LA32-FPU64-ILP32D-NEXT: __loongarch_hard_float 1
+// LA32-FPU64-ILP32D-NOT: __loongarch_lp64
+// LA32-FPU64-ILP32D-NOT: __loongarch_single_float
+// LA32-FPU64-ILP32D-NOT: __loongarch_soft_float
+
+// RUN: %clang --target=loongarch32 -mfpu=64 -mabi=ilp32f -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU64-ILP32F %s
+// LA32-FPU64-ILP32F-NOT: __loongarch_double_float
+// LA32-FPU64-ILP32F: __loongarch_frlen 64
+// LA32-FPU64-ILP32F-NEXT: __loongarch_grlen 32
+// LA32-FPU64-ILP32F-NEXT: __loongarch_hard_float 1
+// LA32-FPU64-ILP32F-NOT: __loongarch_lp64
+// LA32-FPU64-ILP32F-NEXT: __loongarch_single_float 1
+// LA32-FPU64-ILP32F-NOT: __loongarch_soft_float
+
+// RUN: %clang --target=loongarch32 -mfpu=64 -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU64-ILP32S %s
+// LA32-FPU64-ILP32S-NOT: __loongarch_double_float
+// LA32-FPU64-ILP32S: __loongarch_frlen 64
+// LA32-FPU64-ILP32S-NEXT: __loongarch_grlen 32
+// LA32-FPU64-ILP32S-NOT: __loongarch_hard_float
+// LA32-FPU64-ILP32S-NOT: __loongarch_lp64
+// LA32-FPU64-ILP32S-NOT: __loongarch_single_float
+// LA32-FPU64-ILP32S-NEXT: __loongarch_soft_float 1
+
+// RUN: %clang --target=loongarch32 -mfpu=32 -mabi=ilp32f -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU32-ILP32F %s
+// RUN: %clang --target=loongarch32 -msingle-float -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU32-ILP32F %s
+// LA32-FPU32-ILP32F-NOT: __loongarch_double_float
+// LA32-FPU32-ILP32F: __loongarch_frlen 32
+// LA32-FPU32-ILP32F-NEXT: __loongarch_grlen 32
+// LA32-FPU32-ILP32F-NEXT: __loongarch_hard_float 1
+// LA32-FPU32-ILP32F-NOT: __loongarch_lp64
+// LA32-FPU32-ILP32F-NEXT: __loongarch_single_float 1
+// LA32-FPU32-ILP32F-NOT: __loongarch_soft_float
+
+// RUN: %clang --target=loongarch32 -mfpu=32 -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU32-ILP32S %s
+// LA32-FPU32-ILP32S-NOT: __loongarch_double_float
+// LA32-FPU32-ILP32S: __loongarch_frlen 32
+// LA32-FPU32-ILP32S-NEXT: __loongarch_grlen 32
+// LA32-FPU32-ILP32S-NOT: __loongarch_hard_float
+// LA32-FPU32-ILP32S-NOT: __loongarch_lp64
+// LA32-FPU32-ILP32S-NOT: __loongarch_single_float
+// LA32-FPU32-ILP32S-NEXT: __loongarch_soft_float 1
+
+// RUN: %clang --target=loongarch32 -mfpu=0 -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU0-ILP32S %s
+// RUN: %clang --target=loongarch32 -mfpu=none -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU0-ILP32S %s
+// RUN: %clang --target=loongarch32 -msoft-float -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU0-ILP32S %s
+// LA32-FPU0-ILP32S-NOT: __loongarch_double_float
+// LA32-FPU0-ILP32S: __loongarch_frlen 0
+// LA32-FPU0-ILP32S-NEXT: __loongarch_grlen 32
+// LA32-FPU0-ILP32S-NOT: __loongarch_hard_float
+// LA32-FPU0-ILP32S-NOT: __loongarch_lp64
+// LA32-FPU0-ILP32S-NOT: __loongarch_single_float
+// LA32-FPU0-ILP32S-NEXT

[PATCH] D136436: [Clang][LoongArch] Add register alias handling without `$` prefix

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

How about the asm code in `.s`? Do we need to support `addi.d a0, a1, a2`?


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[PATCH] D136436: [Clang][LoongArch] Add register alias handling without `$` prefix

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D136436#3873987 , @xen0n wrote:

> In D136436#3873949 , @SixWeining 
> wrote:
>
>> How about the asm code in `.s`? Do we need to support `addi.d a0, a1, a2`?
>
> For the assembler part of this support, I think we need to coordinate with 
> the GNU toolchain maintainers of LoongArch port (Chenghua, Zhensong and Lulu 
> I think). Maybe raising an issue on the LoongArch documentation repo 
>  would help.
>
> For the GCC part, consistency is of course welcomed, and I think the Loongson 
> maintainers or @xry111 could just submit the respective support.

Well. To be honest, I'd like to keep only one form but not both. Seems other 
archs only support one form? If we support both, will it make people confused?  
Is mixed form allowed (`fmadd.d fa0, $fa0, f0, $f0`) ?


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[PATCH] D136835: [Clang][LoongArch] Support inline asm constraint 'J'

[Lu Weining via Phabricator via cfe-commits]

SixWeining created this revision.
SixWeining added reviewers: xen0n, xry111, MaskRay, wangleiat, gonglingqin.
Herald added subscribers: StephenFan, hiraditya.
Herald added a project: All.
SixWeining requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

'J' is defined in GCC [1] but not documented [2] while Linux [3] has
already used it in LoongArch port.

[1]: 
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/loongarch/constraints.md#L61
[2]: https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html
[3]: 
https://github.com/torvalds/linux/blob/master/arch/loongarch/include/asm/cmpxchg.h#L19


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136835

Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll


Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
===
--- llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
@@ -58,6 +58,17 @@
   ret void
 }
 
+define void @constraint_J() nounwind {
+; CHECK-LABEL: constraint_J:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:#APP
+; CHECK-NEXT:addi.w $a0, $a0, 0
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret
+  tail call void asm sideeffect "addi.w $$a0, $$a0, $0", "J"(i32 0)
+  ret void
+}
+
 define void @constraint_K() nounwind {
 ; CHECK-LABEL: constraint_K:
 ; CHECK:   # %bb.0:
Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
===
--- llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
@@ -17,6 +17,12 @@
   ret void
 }
 
+define void @constraint_J() {
+; CHECK: error: value out of range for constraint 'J'
+  tail call void asm sideeffect "addi.w $$a0, $$a0, $$0", "J"(i32 1)
+  ret void
+}
+
 define void @constraint_K() {
 ; CHECK: error: value out of range for constraint 'K'
   tail call void asm sideeffect "andi.w $$a0, $$a0, $0", "K"(i32 4096)
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -2169,6 +2169,7 @@
   return C_RegisterClass;
 case 'l':
 case 'I':
+case 'J':
 case 'K':
   return C_Immediate;
 case 'k':
@@ -2272,6 +2273,13 @@
   DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getGRLenVT()));
   }
   return;
+case 'J':
+  // Validate & create an integer zero operand.
+  if (auto *C = dyn_cast(Op))
+if (C->getZExtValue() == 0)
+  Ops.push_back(
+  DAG.getTargetConstant(0, SDLoc(Op), Subtarget.getGRLenVT()));
+  return;
 case 'K':
   // Validate & create a 12-bit unsigned immediate operand.
   if (auto *C = dyn_cast(Op)) {
Index: clang/test/CodeGen/LoongArch/inline-asm-constraints.c
===
--- clang/test/CodeGen/LoongArch/inline-asm-constraints.c
+++ clang/test/CodeGen/LoongArch/inline-asm-constraints.c
@@ -43,6 +43,12 @@
   asm volatile ("" :: "I"(-2048));
 }
 
+void test_J(void) {
+// CHECK-LABEL: define{{.*}} void @test_J()
+// CHECK: call void asm sideeffect "", "J"(i32 0)
+  asm volatile ("" :: "J"(0));
+}
+
 void test_K(void) {
 // CHECK-LABEL: define{{.*}} void @test_K()
 // CHECK: call void asm sideeffect "", "K"(i32 4095)
Index: clang/lib/Basic/Targets/LoongArch.cpp
===
--- clang/lib/Basic/Targets/LoongArch.cpp
+++ clang/lib/Basic/Targets/LoongArch.cpp
@@ -88,6 +88,10 @@
 // A signed 12-bit constant (for arithmetic instructions).
 Info.setRequiresImmediate(-2048, 2047);
 return true;
+  case 'J':
+// Integer zero.
+Info.setRequiresImmediate(0);
+return true;
   case 'K':
 // An unsigned 12-bit constant (for logic instructions).
 Info.setRequiresImmediate(0, 4095);


Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
===
--- llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
@@ -58,6 +58,17 @@
   ret void
 }
 
+define void @constraint_J() nounwind {
+; CHECK-LABEL: constraint_J:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:#APP
+; CHECK-NEXT:addi.w $a0, $a0, 0
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret
+  tail call void asm sideeffect "addi.w $$a0, $$a0, $0", "J"(i32 0)
+  ret void
+}
+
 define void @constraint_K() nounwind {
 ; CHECK-LABEL: constraint_K:
 ; CHECK:   #

[PATCH] D136835: [Clang][LoongArch] Support inline asm constraint 'J'

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 471135.
SixWeining added a comment.

Add missing comment.


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Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
===
--- llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
@@ -58,6 +58,17 @@
   ret void
 }
 
+define void @constraint_J() nounwind {
+; CHECK-LABEL: constraint_J:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:#APP
+; CHECK-NEXT:addi.w $a0, $a0, 0
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret
+  tail call void asm sideeffect "addi.w $$a0, $$a0, $0", "J"(i32 0)
+  ret void
+}
+
 define void @constraint_K() nounwind {
 ; CHECK-LABEL: constraint_K:
 ; CHECK:   # %bb.0:
Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
===
--- llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
@@ -17,6 +17,12 @@
   ret void
 }
 
+define void @constraint_J() {
+; CHECK: error: value out of range for constraint 'J'
+  tail call void asm sideeffect "addi.w $$a0, $$a0, $$0", "J"(i32 1)
+  ret void
+}
+
 define void @constraint_K() {
 ; CHECK: error: value out of range for constraint 'K'
   tail call void asm sideeffect "andi.w $$a0, $$a0, $0", "K"(i32 4096)
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -2155,6 +2155,7 @@
   //   offset that is suitable for use in instructions with the same
   //   addressing mode as st.w and ld.w.
   // 'I':  A signed 12-bit constant (for arithmetic instructions).
+  // 'J':  Integer zero.
   // 'K':  An unsigned 12-bit constant (for logic instructions).
   // "ZB": An address that is held in a general-purpose register. The offset is
   //   zero.
@@ -2169,6 +2170,7 @@
   return C_RegisterClass;
 case 'l':
 case 'I':
+case 'J':
 case 'K':
   return C_Immediate;
 case 'k':
@@ -2272,6 +2274,13 @@
   DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getGRLenVT()));
   }
   return;
+case 'J':
+  // Validate & create an integer zero operand.
+  if (auto *C = dyn_cast(Op))
+if (C->getZExtValue() == 0)
+  Ops.push_back(
+  DAG.getTargetConstant(0, SDLoc(Op), Subtarget.getGRLenVT()));
+  return;
 case 'K':
   // Validate & create a 12-bit unsigned immediate operand.
   if (auto *C = dyn_cast(Op)) {
Index: clang/test/CodeGen/LoongArch/inline-asm-constraints.c
===
--- clang/test/CodeGen/LoongArch/inline-asm-constraints.c
+++ clang/test/CodeGen/LoongArch/inline-asm-constraints.c
@@ -43,6 +43,12 @@
   asm volatile ("" :: "I"(-2048));
 }
 
+void test_J(void) {
+// CHECK-LABEL: define{{.*}} void @test_J()
+// CHECK: call void asm sideeffect "", "J"(i32 0)
+  asm volatile ("" :: "J"(0));
+}
+
 void test_K(void) {
 // CHECK-LABEL: define{{.*}} void @test_K()
 // CHECK: call void asm sideeffect "", "K"(i32 4095)
Index: clang/lib/Basic/Targets/LoongArch.cpp
===
--- clang/lib/Basic/Targets/LoongArch.cpp
+++ clang/lib/Basic/Targets/LoongArch.cpp
@@ -88,6 +88,10 @@
 // A signed 12-bit constant (for arithmetic instructions).
 Info.setRequiresImmediate(-2048, 2047);
 return true;
+  case 'J':
+// Integer zero.
+Info.setRequiresImmediate(0);
+return true;
   case 'K':
 // An unsigned 12-bit constant (for logic instructions).
 Info.setRequiresImmediate(0, 4095);
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[PATCH] D136841: [LoongArch] Support inline asm operand modifier 'z'

[Lu Weining via Phabricator via cfe-commits]

SixWeining created this revision.
SixWeining added reviewers: xen0n, xry111, MaskRay, wangleiat, gonglingqin.
Herald added subscribers: StephenFan, pengfei, hiraditya.
Herald added a project: All.
SixWeining requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Print $zero register if operand is zero, otherwise print it normally.

Clang is highly compatible [1] with GCC inline assembly extensions,
allowing the same set of constraints, modifiers and operands as GCC
inline assembly. This patch tries to make it compatible regarding
LoongArch specific operand modifiers.

GCC supports many modifiers [2], but it seems that only x86 and msp430
are documented [3][4]. I don't know if any other modifiers are being
used except the 'z' in Linux [5].

[1]: https://clang.llvm.org/compatibility.html#inline-asm
[2]: 
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/loongarch/loongarch.cc#L4884-L4911
[3]: https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#x86Operandmodifiers
[4]: https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#msp430Operandmodifiers
[5]: 
https://github.com/torvalds/linux/blob/master/arch/loongarch/include/asm/cmpxchg.h#L17


Repository:
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https://reviews.llvm.org/D136841

Files:
  clang/test/CodeGen/LoongArch/inline-asm-operand-modifiers.c
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/test/CodeGen/LoongArch/inline-asm-operand-modidiers.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-operand-modidiers.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-operand-modidiers.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s
+
+define i32 @modifier_z_zero(i32 %a) nounwind {
+; CHECK-LABEL: modifier_z_zero:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:#APP
+; CHECK-NEXT:add.w $a0, $a0, $zero
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret
+  %1 = tail call i32 asm "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 %a, i32 0)
+  ret i32 %1
+}
+
+define i32 @modifier_z_nonzero(i32 %a) nounwind {
+; CHECK-LABEL: modifier_z_nonzero:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:#APP
+; CHECK-NEXT:addi.w $a0, $a0, 1
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, ${2:z}", "=r,r,ri"(i32 %a, i32 1)
+  ret i32 %1
+}
Index: llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
===
--- llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
+++ llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
@@ -47,24 +47,38 @@
   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
 return false;
 
-  // TODO: handle other extra codes if we have.
-  if (!ExtraCode) {
-const MachineOperand &MO = MI->getOperand(OpNo);
-switch (MO.getType()) {
-case MachineOperand::MO_Immediate:
-  OS << MO.getImm();
-  return false;
-case MachineOperand::MO_Register:
-  OS << '$' << LoongArchInstPrinter::getRegisterName(MO.getReg());
-  return false;
-case MachineOperand::MO_GlobalAddress:
-  PrintSymbolOperand(MO, OS);
-  return false;
+  const MachineOperand &MO = MI->getOperand(OpNo);
+  if (ExtraCode && ExtraCode[0]) {
+if (ExtraCode[1] != 0)
+  return true; // Unknown modifier.
+
+switch (ExtraCode[0]) {
 default:
-  llvm_unreachable("not implemented");
+  return true; // Unknown modifier.
+case 'z':  // Print $zero register if zero, regular printing otherwise.
+  if (MO.isImm() && MO.getImm() == 0) {
+OS << '$' << LoongArchInstPrinter::getRegisterName(LoongArch::R0);
+return false;
+  }
+  break;
+  // TODO: handle other extra codes if we have.
 }
   }
 
+  switch (MO.getType()) {
+  case MachineOperand::MO_Immediate:
+OS << MO.getImm();
+return false;
+  case MachineOperand::MO_Register:
+OS << '$' << LoongArchInstPrinter::getRegisterName(MO.getReg());
+return false;
+  case MachineOperand::MO_GlobalAddress:
+PrintSymbolOperand(MO, OS);
+return false;
+  default:
+llvm_unreachable("not implemented");
+  }
+
   return true;
 }
 
Index: clang/test/CodeGen/LoongArch/inline-asm-operand-modifiers.c
===
--- /dev/null
+++ clang/test/CodeGen/LoongArch/inline-asm-operand-modifiers.c
@@ -0,0 +1,25 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple loongarch32 -O2 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple loongarch64 -O2 -emit-llvm %s -o - | FileCheck %s
+
+/// Test LoongArch specific operand modifiers (i.e. operand codes).
+
+// CHECK-LABEL: @test_z_zero(
+// CHECK-NEXT:  entry:
+// CHECK-

[PATCH] D136436: [Clang][LoongArch] Add register alias handling without `$` prefix

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D136436#3881382 , @MaskRay wrote:

> In D136436#3876684 , @SixWeining 
> wrote:
>
>> In D136436#3873987 , @xen0n wrote:
>>
>>> In D136436#3873949 , @SixWeining 
>>> wrote:
>>>
 How about the asm code in `.s`? Do we need to support `addi.d a0, a1, a2`?
>>>
>>> For the assembler part of this support, I think we need to coordinate with 
>>> the GNU toolchain maintainers of LoongArch port (Chenghua, Zhensong and 
>>> Lulu I think). Maybe raising an issue on the LoongArch documentation repo 
>>>  would help.
>>>
>>> For the GCC part, consistency is of course welcomed, and I think the 
>>> Loongson maintainers or @xry111 could just submit the respective support.
>>
>> Well. To be honest, I'd like to keep only one form but not both. Seems other 
>> archs only support one form? If we support both, will it make people 
>> confused?  Is mixed form allowed (`fmadd.d fa0, $fa0, f0, $fcc0`) ?
>
> Having just one form will be nice.

@tangyouling Considering that `$`  is well supported by both gcc and llvm, we 
should adandon this patch?


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[PATCH] D136841: [LoongArch] Support inline asm operand modifier 'z'

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 471729.
SixWeining added a comment.

Fix nit.


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Files:
  clang/test/CodeGen/LoongArch/inline-asm-operand-modifiers.c
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/test/CodeGen/LoongArch/inline-asm-operand-modidiers.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-operand-modidiers.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-operand-modidiers.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s
+
+define i32 @modifier_z_zero(i32 %a) nounwind {
+; CHECK-LABEL: modifier_z_zero:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:#APP
+; CHECK-NEXT:add.w $a0, $a0, $zero
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret
+  %1 = tail call i32 asm "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 %a, i32 0)
+  ret i32 %1
+}
+
+define i32 @modifier_z_nonzero(i32 %a) nounwind {
+; CHECK-LABEL: modifier_z_nonzero:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:#APP
+; CHECK-NEXT:addi.w $a0, $a0, 1
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, ${2:z}", "=r,r,ri"(i32 %a, i32 1)
+  ret i32 %1
+}
Index: llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
===
--- llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
+++ llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
@@ -47,24 +47,38 @@
   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
 return false;
 
-  // TODO: handle other extra codes if we have.
-  if (!ExtraCode) {
-const MachineOperand &MO = MI->getOperand(OpNo);
-switch (MO.getType()) {
-case MachineOperand::MO_Immediate:
-  OS << MO.getImm();
-  return false;
-case MachineOperand::MO_Register:
-  OS << '$' << LoongArchInstPrinter::getRegisterName(MO.getReg());
-  return false;
-case MachineOperand::MO_GlobalAddress:
-  PrintSymbolOperand(MO, OS);
-  return false;
+  const MachineOperand &MO = MI->getOperand(OpNo);
+  if (ExtraCode && ExtraCode[0]) {
+if (ExtraCode[1] != 0)
+  return true; // Unknown modifier.
+
+switch (ExtraCode[0]) {
 default:
-  llvm_unreachable("not implemented");
+  return true; // Unknown modifier.
+case 'z':  // Print $zero register if zero, regular printing otherwise.
+  if (MO.isImm() && MO.getImm() == 0) {
+OS << '$' << LoongArchInstPrinter::getRegisterName(LoongArch::R0);
+return false;
+  }
+  break;
+  // TODO: handle other extra codes if any.
 }
   }
 
+  switch (MO.getType()) {
+  case MachineOperand::MO_Immediate:
+OS << MO.getImm();
+return false;
+  case MachineOperand::MO_Register:
+OS << '$' << LoongArchInstPrinter::getRegisterName(MO.getReg());
+return false;
+  case MachineOperand::MO_GlobalAddress:
+PrintSymbolOperand(MO, OS);
+return false;
+  default:
+llvm_unreachable("not implemented");
+  }
+
   return true;
 }
 
Index: clang/test/CodeGen/LoongArch/inline-asm-operand-modifiers.c
===
--- /dev/null
+++ clang/test/CodeGen/LoongArch/inline-asm-operand-modifiers.c
@@ -0,0 +1,25 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple loongarch32 -O2 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple loongarch64 -O2 -emit-llvm %s -o - | FileCheck %s
+
+/// Test LoongArch specific operand modifiers (i.e. operand codes).
+
+// CHECK-LABEL: @test_z_zero(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 asm sideeffect "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 [[A:%.*]], i32 0) #[[ATTR1]], !srcloc !4
+// CHECK-NEXT:ret void
+//
+void test_z_zero(int a) {
+  int tmp;
+  asm volatile ("add.w %0, %1, %z2" : "=r" (tmp) : "r" (a), "ri" (0));
+}
+
+// CHECK-LABEL: @test_z_nonzero(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 asm sideeffect "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 [[A:%.*]], i32 1) #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret void
+//
+void test_z_nonzero(int a) {
+  int tmp;
+  asm volatile ("add.w %0, %1, %z2" : "=r" (tmp) : "r" (a), "ri" (1));
+}
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[PATCH] D136841: [LoongArch] Support inline asm operand modifier 'z'

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D136841#3893966 , @xen0n wrote:

> Ah. There's a typo in the name of the testcase file...

:(-


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[PATCH] D136841: [LoongArch] Support inline asm operand modifier 'z'

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 471730.
SixWeining added a comment.

Fix testcase file name.


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Files:
  clang/test/CodeGen/LoongArch/inline-asm-operand-modifiers.c
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/test/CodeGen/LoongArch/inline-asm-operand-modifiers.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-operand-modifiers.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-operand-modifiers.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s
+
+define i32 @modifier_z_zero(i32 %a) nounwind {
+; CHECK-LABEL: modifier_z_zero:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:#APP
+; CHECK-NEXT:add.w $a0, $a0, $zero
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret
+  %1 = tail call i32 asm "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 %a, i32 0)
+  ret i32 %1
+}
+
+define i32 @modifier_z_nonzero(i32 %a) nounwind {
+; CHECK-LABEL: modifier_z_nonzero:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:#APP
+; CHECK-NEXT:addi.w $a0, $a0, 1
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, ${2:z}", "=r,r,ri"(i32 %a, i32 1)
+  ret i32 %1
+}
Index: llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
===
--- llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
+++ llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
@@ -47,24 +47,38 @@
   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
 return false;
 
-  // TODO: handle other extra codes if we have.
-  if (!ExtraCode) {
-const MachineOperand &MO = MI->getOperand(OpNo);
-switch (MO.getType()) {
-case MachineOperand::MO_Immediate:
-  OS << MO.getImm();
-  return false;
-case MachineOperand::MO_Register:
-  OS << '$' << LoongArchInstPrinter::getRegisterName(MO.getReg());
-  return false;
-case MachineOperand::MO_GlobalAddress:
-  PrintSymbolOperand(MO, OS);
-  return false;
+  const MachineOperand &MO = MI->getOperand(OpNo);
+  if (ExtraCode && ExtraCode[0]) {
+if (ExtraCode[1] != 0)
+  return true; // Unknown modifier.
+
+switch (ExtraCode[0]) {
 default:
-  llvm_unreachable("not implemented");
+  return true; // Unknown modifier.
+case 'z':  // Print $zero register if zero, regular printing otherwise.
+  if (MO.isImm() && MO.getImm() == 0) {
+OS << '$' << LoongArchInstPrinter::getRegisterName(LoongArch::R0);
+return false;
+  }
+  break;
+  // TODO: handle other extra codes if any.
 }
   }
 
+  switch (MO.getType()) {
+  case MachineOperand::MO_Immediate:
+OS << MO.getImm();
+return false;
+  case MachineOperand::MO_Register:
+OS << '$' << LoongArchInstPrinter::getRegisterName(MO.getReg());
+return false;
+  case MachineOperand::MO_GlobalAddress:
+PrintSymbolOperand(MO, OS);
+return false;
+  default:
+llvm_unreachable("not implemented");
+  }
+
   return true;
 }
 
Index: clang/test/CodeGen/LoongArch/inline-asm-operand-modifiers.c
===
--- /dev/null
+++ clang/test/CodeGen/LoongArch/inline-asm-operand-modifiers.c
@@ -0,0 +1,25 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple loongarch32 -O2 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple loongarch64 -O2 -emit-llvm %s -o - | FileCheck %s
+
+/// Test LoongArch specific operand modifiers (i.e. operand codes).
+
+// CHECK-LABEL: @test_z_zero(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 asm sideeffect "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 [[A:%.*]], i32 0) #[[ATTR1]], !srcloc !4
+// CHECK-NEXT:ret void
+//
+void test_z_zero(int a) {
+  int tmp;
+  asm volatile ("add.w %0, %1, %z2" : "=r" (tmp) : "r" (a), "ri" (0));
+}
+
+// CHECK-LABEL: @test_z_nonzero(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 asm sideeffect "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 [[A:%.*]], i32 1) #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret void
+//
+void test_z_nonzero(int a) {
+  int tmp;
+  asm volatile ("add.w %0, %1, %z2" : "=r" (tmp) : "r" (a), "ri" (1));
+}
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[PATCH] D136835: [Clang][LoongArch] Support inline asm constraint 'J'

[Lu Weining via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGcd0174aacb73: [Clang][LoongArch] Support inline asm 
constraint 'J' (authored by SixWeining).

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Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
===
--- llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
@@ -58,6 +58,17 @@
   ret void
 }
 
+define void @constraint_J() nounwind {
+; CHECK-LABEL: constraint_J:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:#APP
+; CHECK-NEXT:addi.w $a0, $a0, 0
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret
+  tail call void asm sideeffect "addi.w $$a0, $$a0, $0", "J"(i32 0)
+  ret void
+}
+
 define void @constraint_K() nounwind {
 ; CHECK-LABEL: constraint_K:
 ; CHECK:   # %bb.0:
Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
===
--- llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
@@ -17,6 +17,12 @@
   ret void
 }
 
+define void @constraint_J() {
+; CHECK: error: value out of range for constraint 'J'
+  tail call void asm sideeffect "addi.w $$a0, $$a0, $$0", "J"(i32 1)
+  ret void
+}
+
 define void @constraint_K() {
 ; CHECK: error: value out of range for constraint 'K'
   tail call void asm sideeffect "andi.w $$a0, $$a0, $0", "K"(i32 4096)
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -2184,6 +2184,7 @@
   //   offset that is suitable for use in instructions with the same
   //   addressing mode as st.w and ld.w.
   // 'I':  A signed 12-bit constant (for arithmetic instructions).
+  // 'J':  Integer zero.
   // 'K':  An unsigned 12-bit constant (for logic instructions).
   // "ZB": An address that is held in a general-purpose register. The offset is
   //   zero.
@@ -2198,6 +2199,7 @@
   return C_RegisterClass;
 case 'l':
 case 'I':
+case 'J':
 case 'K':
   return C_Immediate;
 case 'k':
@@ -2301,6 +2303,13 @@
   DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getGRLenVT()));
   }
   return;
+case 'J':
+  // Validate & create an integer zero operand.
+  if (auto *C = dyn_cast(Op))
+if (C->getZExtValue() == 0)
+  Ops.push_back(
+  DAG.getTargetConstant(0, SDLoc(Op), Subtarget.getGRLenVT()));
+  return;
 case 'K':
   // Validate & create a 12-bit unsigned immediate operand.
   if (auto *C = dyn_cast(Op)) {
Index: clang/test/CodeGen/LoongArch/inline-asm-constraints.c
===
--- clang/test/CodeGen/LoongArch/inline-asm-constraints.c
+++ clang/test/CodeGen/LoongArch/inline-asm-constraints.c
@@ -43,6 +43,12 @@
   asm volatile ("" :: "I"(-2048));
 }
 
+void test_J(void) {
+// CHECK-LABEL: define{{.*}} void @test_J()
+// CHECK: call void asm sideeffect "", "J"(i32 0)
+  asm volatile ("" :: "J"(0));
+}
+
 void test_K(void) {
 // CHECK-LABEL: define{{.*}} void @test_K()
 // CHECK: call void asm sideeffect "", "K"(i32 4095)
Index: clang/lib/Basic/Targets/LoongArch.cpp
===
--- clang/lib/Basic/Targets/LoongArch.cpp
+++ clang/lib/Basic/Targets/LoongArch.cpp
@@ -88,6 +88,10 @@
 // A signed 12-bit constant (for arithmetic instructions).
 Info.setRequiresImmediate(-2048, 2047);
 return true;
+  case 'J':
+// Integer zero.
+Info.setRequiresImmediate(0);
+return true;
   case 'K':
 // An unsigned 12-bit constant (for logic instructions).
 Info.setRequiresImmediate(0, 4095);
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[PATCH] D136413: [Clang][LoongArch] Define more LoongArch specific built-in macros

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D136413#3895369 , @xen0n wrote:

> Amended the patch summary a little for grammatical fixes and mentioning 
> `__loongarch64` too.

Thanks.

BTW, this patch depends on D136146 . Could 
you help to have a look? :)


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[PATCH] D136841: [LoongArch] Support inline asm operand modifier 'z'

[Lu Weining via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe415cb1d61e7: [LoongArch] Support inline asm operand 
modifier 'z' (authored by SixWeining).

Changed prior to commit:
  https://reviews.llvm.org/D136841?vs=471730&id=471892#toc

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Files:
  clang/test/CodeGen/LoongArch/inline-asm-operand-modifiers.c
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/test/CodeGen/LoongArch/inline-asm-operand-modifiers.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-operand-modifiers.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-operand-modifiers.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s
+
+define i32 @modifier_z_zero(i32 %a) nounwind {
+; CHECK-LABEL: modifier_z_zero:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:#APP
+; CHECK-NEXT:add.w $a0, $a0, $zero
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret
+  %1 = tail call i32 asm "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 %a, i32 0)
+  ret i32 %1
+}
+
+define i32 @modifier_z_nonzero(i32 %a) nounwind {
+; CHECK-LABEL: modifier_z_nonzero:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:#APP
+; CHECK-NEXT:addi.w $a0, $a0, 1
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, ${2:z}", "=r,r,ri"(i32 %a, i32 1)
+  ret i32 %1
+}
Index: llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
===
--- llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
+++ llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
@@ -47,24 +47,38 @@
   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
 return false;
 
-  // TODO: handle other extra codes if we have.
-  if (!ExtraCode) {
-const MachineOperand &MO = MI->getOperand(OpNo);
-switch (MO.getType()) {
-case MachineOperand::MO_Immediate:
-  OS << MO.getImm();
-  return false;
-case MachineOperand::MO_Register:
-  OS << '$' << LoongArchInstPrinter::getRegisterName(MO.getReg());
-  return false;
-case MachineOperand::MO_GlobalAddress:
-  PrintSymbolOperand(MO, OS);
-  return false;
+  const MachineOperand &MO = MI->getOperand(OpNo);
+  if (ExtraCode && ExtraCode[0]) {
+if (ExtraCode[1] != 0)
+  return true; // Unknown modifier.
+
+switch (ExtraCode[0]) {
 default:
-  llvm_unreachable("not implemented");
+  return true; // Unknown modifier.
+case 'z':  // Print $zero register if zero, regular printing otherwise.
+  if (MO.isImm() && MO.getImm() == 0) {
+OS << '$' << LoongArchInstPrinter::getRegisterName(LoongArch::R0);
+return false;
+  }
+  break;
+  // TODO: handle other extra codes if any.
 }
   }
 
+  switch (MO.getType()) {
+  case MachineOperand::MO_Immediate:
+OS << MO.getImm();
+return false;
+  case MachineOperand::MO_Register:
+OS << '$' << LoongArchInstPrinter::getRegisterName(MO.getReg());
+return false;
+  case MachineOperand::MO_GlobalAddress:
+PrintSymbolOperand(MO, OS);
+return false;
+  default:
+llvm_unreachable("not implemented");
+  }
+
   return true;
 }
 
Index: clang/test/CodeGen/LoongArch/inline-asm-operand-modifiers.c
===
--- /dev/null
+++ clang/test/CodeGen/LoongArch/inline-asm-operand-modifiers.c
@@ -0,0 +1,25 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple loongarch32 -O2 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple loongarch64 -O2 -emit-llvm %s -o - | FileCheck %s
+
+/// Test LoongArch specific operand modifiers (i.e. operand codes).
+
+// CHECK-LABEL: @test_z_zero(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 asm sideeffect "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 [[A:%.*]], i32 0) #[[ATTR1:[0-9]+]], !srcloc !2
+// CHECK-NEXT:ret void
+//
+void test_z_zero(int a) {
+  int tmp;
+  asm volatile ("add.w %0, %1, %z2" : "=r" (tmp) : "r" (a), "ri" (0));
+}
+
+// CHECK-LABEL: @test_z_nonzero(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 asm sideeffect "add.w $0, $1, ${2:z}", "=r,r,ri"(i32 [[A:%.*]], i32 1) #[[ATTR1]], !srcloc !3
+// CHECK-NEXT:ret void
+//
+void test_z_nonzero(int a) {
+  int tmp;
+  asm volatile ("add.w %0, %1, %z2" : "=r" (tmp) : "r" (a), "ri" (1));
+}
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[PATCH] D136436: [Clang][LoongArch] Add register alias handling without `$` prefix

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D136436#3898392 , @tangyouling 
wrote:

> Is it acceptable to add the `non-prefix $`? if not, an alternative fix for 
> the build failure is to add the `prefix $` in 
> sanitizer_syscall_linux_loongarch64.inc

People have different opinions. This may need long time to discuss and decide 
(maybe in a broader place). So currently it's better to modify 
`sanitizer_syscall_linux_loongarch64.inc` I think.


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[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 452897.
SixWeining added a comment.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130255/new/

https://reviews.llvm.org/D130255

Files:
  clang/lib/Basic/CMakeLists.txt
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Clang.h
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/bin/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/include/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64d/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64f/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64s/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/bin/ld
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib64/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib64/.keep
  clang/test/Driver/frame-pointer.c
  clang/test/Driver/loongarch-abi-error.c
  clang/test/Driver/loongarch-abi.c
  clang/test/Driver/loongarch-toolchain.c
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- /dev/null
+++ clang/test/Preprocessor/init-loongarch.c
@@ -0,0 +1,641 @@
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA32 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA32,LA32-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA32,LA32-INT128 %s
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA64 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA64,LA64-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA64,LA64-INT128 %s
+
+ Note that common macros are tested in init.c, such as __VERSION__. So they're not listed here.
+
+// LA32: #define _ILP32 1
+// LA32: #define __ATOMIC_ACQUIRE 2
+// LA32-NEXT: #define __ATOMIC_ACQ_REL 4
+// LA32-NEXT: #define __ATOMIC_CONSUME 1
+// LA32-NEXT: #define __ATOMIC_RELAXED 0
+// LA32-NEXT: #define __ATOMIC_RELEASE 3
+// LA32-NEXT: #define __ATOMIC_SEQ_CST 5
+// LA32: #define __BIGGEST_ALIGNMENT__ 16
+// LA32: #define __BITINT_MAXWIDTH__ 128
+// LA32: #define __BOOL_WIDTH__ 8
+// LA32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// LA32: #define __CHAR16_TYPE__ unsigned short
+// LA32: #define __CHAR32_TYPE__ unsigned int
+// LA32: #define __CHAR_BIT__ 8
+// LA32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_INT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 1
+// LA32: #define __DBL_DECIMAL_DIG__ 17
+// LA32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// LA32: #define __DBL_DIG__ 15
+// LA32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// LA32: #define __DBL_HAS_DENORM__ 1
+// LA32: #define __DBL_HAS_INFINITY__ 1
+// LA32: #define __DBL_HAS_QUIET_NAN__ 1
+// LA32: #define __DBL_MANT_DIG__ 53
+// LA32: #define __DBL_MAX_10_EXP__ 308
+// LA32: #define __DBL_MAX_EXP__ 1024
+// LA32: #define __DBL_MAX__ 1.7976931348623157e+308
+// LA32: #define __DBL_MIN_10_EXP__ (-307)
+// LA32: #define __DBL_MIN_EXP__ (-1021

[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 454179.
SixWeining added a comment.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130255/new/

https://reviews.llvm.org/D130255

Files:
  clang/lib/Basic/CMakeLists.txt
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Clang.h
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/bin/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/include/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64d/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64f/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64s/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/bin/ld
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib64/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib64/.keep
  clang/test/Driver/frame-pointer.c
  clang/test/Driver/loongarch-abi-error.c
  clang/test/Driver/loongarch-abi.c
  clang/test/Driver/loongarch-toolchain.c
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- /dev/null
+++ clang/test/Preprocessor/init-loongarch.c
@@ -0,0 +1,641 @@
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA32 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA32,LA32-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch32 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA32,LA32-INT128 %s
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA64 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA64,LA64-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=loongarch64 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA64,LA64-INT128 %s
+
+ Note that common macros are tested in init.c, such as __VERSION__. So they're not listed here.
+
+// LA32: #define _ILP32 1
+// LA32: #define __ATOMIC_ACQUIRE 2
+// LA32-NEXT: #define __ATOMIC_ACQ_REL 4
+// LA32-NEXT: #define __ATOMIC_CONSUME 1
+// LA32-NEXT: #define __ATOMIC_RELAXED 0
+// LA32-NEXT: #define __ATOMIC_RELEASE 3
+// LA32-NEXT: #define __ATOMIC_SEQ_CST 5
+// LA32: #define __BIGGEST_ALIGNMENT__ 16
+// LA32: #define __BITINT_MAXWIDTH__ 128
+// LA32: #define __BOOL_WIDTH__ 8
+// LA32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// LA32: #define __CHAR16_TYPE__ unsigned short
+// LA32: #define __CHAR32_TYPE__ unsigned int
+// LA32: #define __CHAR_BIT__ 8
+// LA32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_INT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 1
+// LA32: #define __DBL_DECIMAL_DIG__ 17
+// LA32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// LA32: #define __DBL_DIG__ 15
+// LA32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// LA32: #define __DBL_HAS_DENORM__ 1
+// LA32: #define __DBL_HAS_INFINITY__ 1
+// LA32: #define __DBL_HAS_QUIET_NAN__ 1
+// LA32: #define __DBL_MANT_DIG__ 53
+// LA32: #define __DBL_MAX_10_EXP__ 308
+// LA32: #define __DBL_MAX_EXP__ 1024
+// LA32: #define __DBL_MAX__ 1.7976931348623157e+308
+// LA32: #define __DBL_MIN_10_EXP__ (-307)
+// LA32: #define __DBL_MIN_EXP__ (-1021

[PATCH] D132285: [LoongArch] Implement ABI lowering

[Lu Weining via Phabricator via cfe-commits]

SixWeining created this revision.
SixWeining added reviewers: xen0n, MaskRay, xry111, wangleiat.
Herald added subscribers: luke957, mstorsjo, StephenFan, luismarques, 
s.egerton, PkmX, simoncook, arichardson.
Herald added a project: All.
SixWeining requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead.
Herald added a project: clang.

Reuse most of RISCV's implementation with several exceptions:

On RISCV, integer scalars passed in registers have signext/zeroext
when promoted, but are anyext if passed on the stack. This is defined
in early RISCV ABI specification. But after this change [1], integers
should also be signext/zeroext if passed on the stack. So I think
RISCV's ABI lowering should be updated [2].

In LoongArch ABI spec, we can see that integer scalars narrower than
GRLEN bits are zero/sign-extended no matter passed in registers or on
the stack.

There is another difference worth mentioning is that `char` is signed
by default on LoongArch while it is unsigned on RISCV.

This patch also adds `_BitInt` type support to LoongArch and handle it
in LoongArchABIInfo::classifyArgumentType.

[1] 
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/cec39a064ee0e5b0129973fffab7e3ad1710498f
[2] https://github.com/llvm/llvm-project/issues/57261

Depends on D130255 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D132285

Files:
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/LoongArch/abi-lp64d.c
  clang/test/CodeGen/ext-int-cc.c
  clang/test/CodeGenCXX/LoongArch/abi-lp64d-struct-inherit.cpp

Index: clang/test/CodeGenCXX/LoongArch/abi-lp64d-struct-inherit.cpp
===
--- /dev/null
+++ clang/test/CodeGenCXX/LoongArch/abi-lp64d-struct-inherit.cpp
@@ -0,0 +1,95 @@
+// RUN: %clang_cc1 -triple loongarch64 -target-feature +f -target-feature +d -target-abi lp64d \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+
+#include 
+
+/// Ensure that fields inherited from a parent struct are treated in the same
+/// way as fields directly in the child for the purposes of LoongArch ABI rules.
+
+struct parent1_int32_s {
+  int32_t i1;
+};
+
+struct child1_int32_s : parent1_int32_s {
+  int32_t i2;
+};
+
+// CHECK-LABEL: define{{.*}} i64 @_Z30int32_int32_struct_inheritance14child1_int32_s(i64 %a.coerce)
+struct child1_int32_s int32_int32_struct_inheritance(struct child1_int32_s a) {
+  return a;
+}
+
+struct parent2_int32_s {
+  int32_t i1;
+};
+
+struct child2_float_s : parent2_int32_s {
+  float f1;
+};
+
+// CHECK-LABEL: define{{.*}} { i32, float } @_Z30int32_float_struct_inheritance14child2_float_s(i32 %0, float %1)
+struct child2_float_s int32_float_struct_inheritance(struct child2_float_s a) {
+  return a;
+}
+
+struct parent3_float_s {
+  float f1;
+};
+
+struct child3_int64_s : parent3_float_s {
+  int64_t i1;
+};
+
+// CHECK-LABEL: define{{.*}} { float, i64 } @_Z30float_int64_struct_inheritance14child3_int64_s(float %0, i64 %1)
+struct child3_int64_s float_int64_struct_inheritance(struct child3_int64_s a) {
+  return a;
+}
+
+struct parent4_double_s {
+  double d1;
+};
+
+struct child4_double_s : parent4_double_s {
+  double d1;
+};
+
+// CHECK-LABEL: define{{.*}} { double, double } @_Z32double_double_struct_inheritance15child4_double_s(double %0, double %1)
+struct child4_double_s double_double_struct_inheritance(struct child4_double_s a) {
+  return a;
+}
+
+/// When virtual inheritance is used, the resulting struct isn't eligible for
+/// passing in registers.
+
+struct parent5_virtual_s {
+  int32_t i1;
+};
+
+struct child5_virtual_s : virtual parent5_virtual_s {
+  float f1;
+};
+
+// CHECK-LABEL: define{{.*}} void @_ZN16child5_virtual_sC1EOS_(ptr noundef nonnull align 8 dereferenceable(12) %this, ptr noundef nonnull align 8 dereferenceable(12) %0)
+struct child5_virtual_s int32_float_virtual_struct_inheritance(struct child5_virtual_s a) {
+  return a;
+}
+
+/// Check for correct lowering in the presence of diamond inheritance.
+
+struct parent6_float_s {
+  float f1;
+};
+
+struct child6a_s : parent6_float_s {
+};
+
+struct child6b_s : parent6_float_s {
+};
+
+struct grandchild_6_s : child6a_s, child6b_s {
+};
+
+// CHECK-LABEL: define{{.*}} { float, float } @_Z38float_float_diamond_struct_inheritance14grandchild_6_s(float %0, float %1)
+struct grandchild_6_s float_float_diamond_struct_inheritance(struct grandchild_6_s a) {
+  return a;
+}
Index: clang/test/CodeGen/ext-int-cc.c
===
--- clang/test/CodeGen/ext-int-cc.c
+++ clang/test/CodeGen/ext-int-cc.c
@@ -27,6 +27,8 @@
 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple arm64_32-apple-ios -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64
 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple arm64_32-apple-ios -target-abi darwin

[PATCH] D132285: [LoongArch] Implement ABI lowering

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D132285#3736922 , @xry111 wrote:

> Are cases like
>
>   struct x { double a; __int128 : 0; double b;};
>   double f(struct x x) { return x.a + x.b; }
>
> handled properly?  AFAIK RISC-V clang currently does not handle it correctly:
>
> https://godbolt.org/z/rvM99zbqc (GCC handles it properly)
> https://godbolt.org/z/sWY5vs5ce (Clang does not handle it properly)
>
> Note that we rectified the ABI to match the behavior of RISC-V GCC 
> deliberately (https://gcc.gnu.org/r12-8294) but I didn't rewrite the document 
> because the behavior is not easy to describe with my poor English.

Thanks. Since current ABI doesn’t document the behavior of zero-bit fields so I 
pay less attention to this case. Let me check it later.


Repository:
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[PATCH] D132285: [LoongArch] Implement ABI lowering

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 454276.
SixWeining added a comment.

Ignore zero-width bit fields and add a test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132285/new/

https://reviews.llvm.org/D132285

Files:
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/LoongArch/abi-lp64d.c
  clang/test/CodeGen/ext-int-cc.c
  clang/test/CodeGenCXX/LoongArch/abi-lp64d-struct-inherit.cpp

Index: clang/test/CodeGenCXX/LoongArch/abi-lp64d-struct-inherit.cpp
===
--- /dev/null
+++ clang/test/CodeGenCXX/LoongArch/abi-lp64d-struct-inherit.cpp
@@ -0,0 +1,95 @@
+// RUN: %clang_cc1 -triple loongarch64 -target-feature +f -target-feature +d -target-abi lp64d \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+
+#include 
+
+/// Ensure that fields inherited from a parent struct are treated in the same
+/// way as fields directly in the child for the purposes of LoongArch ABI rules.
+
+struct parent1_int32_s {
+  int32_t i1;
+};
+
+struct child1_int32_s : parent1_int32_s {
+  int32_t i2;
+};
+
+// CHECK-LABEL: define{{.*}} i64 @_Z30int32_int32_struct_inheritance14child1_int32_s(i64 %a.coerce)
+struct child1_int32_s int32_int32_struct_inheritance(struct child1_int32_s a) {
+  return a;
+}
+
+struct parent2_int32_s {
+  int32_t i1;
+};
+
+struct child2_float_s : parent2_int32_s {
+  float f1;
+};
+
+// CHECK-LABEL: define{{.*}} { i32, float } @_Z30int32_float_struct_inheritance14child2_float_s(i32 %0, float %1)
+struct child2_float_s int32_float_struct_inheritance(struct child2_float_s a) {
+  return a;
+}
+
+struct parent3_float_s {
+  float f1;
+};
+
+struct child3_int64_s : parent3_float_s {
+  int64_t i1;
+};
+
+// CHECK-LABEL: define{{.*}} { float, i64 } @_Z30float_int64_struct_inheritance14child3_int64_s(float %0, i64 %1)
+struct child3_int64_s float_int64_struct_inheritance(struct child3_int64_s a) {
+  return a;
+}
+
+struct parent4_double_s {
+  double d1;
+};
+
+struct child4_double_s : parent4_double_s {
+  double d1;
+};
+
+// CHECK-LABEL: define{{.*}} { double, double } @_Z32double_double_struct_inheritance15child4_double_s(double %0, double %1)
+struct child4_double_s double_double_struct_inheritance(struct child4_double_s a) {
+  return a;
+}
+
+/// When virtual inheritance is used, the resulting struct isn't eligible for
+/// passing in registers.
+
+struct parent5_virtual_s {
+  int32_t i1;
+};
+
+struct child5_virtual_s : virtual parent5_virtual_s {
+  float f1;
+};
+
+// CHECK-LABEL: define{{.*}} void @_ZN16child5_virtual_sC1EOS_(ptr noundef nonnull align 8 dereferenceable(12) %this, ptr noundef nonnull align 8 dereferenceable(12) %0)
+struct child5_virtual_s int32_float_virtual_struct_inheritance(struct child5_virtual_s a) {
+  return a;
+}
+
+/// Check for correct lowering in the presence of diamond inheritance.
+
+struct parent6_float_s {
+  float f1;
+};
+
+struct child6a_s : parent6_float_s {
+};
+
+struct child6b_s : parent6_float_s {
+};
+
+struct grandchild_6_s : child6a_s, child6b_s {
+};
+
+// CHECK-LABEL: define{{.*}} { float, float } @_Z38float_float_diamond_struct_inheritance14grandchild_6_s(float %0, float %1)
+struct grandchild_6_s float_float_diamond_struct_inheritance(struct grandchild_6_s a) {
+  return a;
+}
Index: clang/test/CodeGen/ext-int-cc.c
===
--- clang/test/CodeGen/ext-int-cc.c
+++ clang/test/CodeGen/ext-int-cc.c
@@ -27,6 +27,8 @@
 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple arm64_32-apple-ios -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64
 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple arm64_32-apple-ios -target-abi darwinpcs -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64DARWIN
 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple arm -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=ARM
+// RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple loongarch64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=LA64
+// RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple loongarch32 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=LA32
 
 // Make sure 128 and 64 bit versions are passed like integers.
 void ParamPassing(_BitInt(128) b, _BitInt(64) c) {}
@@ -57,6 +59,8 @@
 // AARCH64: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
 // AARCH64DARWIN: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
 // ARM: define{{.*}} arm_aapcscc void @ParamPassing(i128* byval(i128) align 8 %{{.+}}, i64 %{{.+}})
+// LA64: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
+// LA32: define{{.*}} void @ParamPassing(i128* %{{.+}}, i64 %{{.+}})
 
 void ParamPassing2(_BitInt(127) b, _BitInt(63

[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 454346.
SixWeining added a comment.

`-triple=` to `-triple `


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130255/new/

https://reviews.llvm.org/D130255

Files:
  clang/lib/Basic/CMakeLists.txt
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Clang.h
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/bin/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/include/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64d/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64f/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64s/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/bin/ld
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib64/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib64/.keep
  clang/test/Driver/frame-pointer.c
  clang/test/Driver/loongarch-abi-error.c
  clang/test/Driver/loongarch-abi.c
  clang/test/Driver/loongarch-toolchain.c
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- /dev/null
+++ clang/test/Preprocessor/init-loongarch.c
@@ -0,0 +1,641 @@
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch32 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA32 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch32-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA32,LA32-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch32 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA32,LA32-INT128 %s
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch64 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA64 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch64-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA64,LA64-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch64 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA64,LA64-INT128 %s
+
+ Note that common macros are tested in init.c, such as __VERSION__. So they're not listed here.
+
+// LA32: #define _ILP32 1
+// LA32: #define __ATOMIC_ACQUIRE 2
+// LA32-NEXT: #define __ATOMIC_ACQ_REL 4
+// LA32-NEXT: #define __ATOMIC_CONSUME 1
+// LA32-NEXT: #define __ATOMIC_RELAXED 0
+// LA32-NEXT: #define __ATOMIC_RELEASE 3
+// LA32-NEXT: #define __ATOMIC_SEQ_CST 5
+// LA32: #define __BIGGEST_ALIGNMENT__ 16
+// LA32: #define __BITINT_MAXWIDTH__ 128
+// LA32: #define __BOOL_WIDTH__ 8
+// LA32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// LA32: #define __CHAR16_TYPE__ unsigned short
+// LA32: #define __CHAR32_TYPE__ unsigned int
+// LA32: #define __CHAR_BIT__ 8
+// LA32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_INT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 1
+// LA32: #define __DBL_DECIMAL_DIG__ 17
+// LA32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// LA32: #define __DBL_DIG__ 15
+// LA32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// LA32: #define __DBL_HAS_DENORM__ 1
+// LA32: #define __DBL_HAS_INFINITY__ 1
+// LA32: #define __DBL_HAS_QUIET_NAN__ 1
+// LA32: #define __DBL_MANT_DIG__ 53
+// LA32: #define __DBL_MAX_10_EXP__ 308
+// LA32: #define __DBL_MAX_EXP__ 1024
+// LA32: #define __DBL_MAX__ 1.7976931348623157e+308
+// LA32: #define __DBL_MIN_10_EXP__ (-307)
+// LA32: #define __DB

[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 454446.
SixWeining added a comment.

Use `-fsyntax-only`; `-check-prefix` to `--check-prefix`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130255/new/

https://reviews.llvm.org/D130255

Files:
  clang/lib/Basic/CMakeLists.txt
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Clang.h
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/bin/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/include/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64d/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64f/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64s/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/bin/ld
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib64/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib64/.keep
  clang/test/Driver/frame-pointer.c
  clang/test/Driver/loongarch-abi-error.c
  clang/test/Driver/loongarch-abi.c
  clang/test/Driver/loongarch-toolchain.c
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- /dev/null
+++ clang/test/Preprocessor/init-loongarch.c
@@ -0,0 +1,641 @@
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch32 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA32 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch32-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA32,LA32-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch32 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA32,LA32-INT128 %s
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch64 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA64 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch64-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA64,LA64-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch64 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA64,LA64-INT128 %s
+
+ Note that common macros are tested in init.c, such as __VERSION__. So they're not listed here.
+
+// LA32: #define _ILP32 1
+// LA32: #define __ATOMIC_ACQUIRE 2
+// LA32-NEXT: #define __ATOMIC_ACQ_REL 4
+// LA32-NEXT: #define __ATOMIC_CONSUME 1
+// LA32-NEXT: #define __ATOMIC_RELAXED 0
+// LA32-NEXT: #define __ATOMIC_RELEASE 3
+// LA32-NEXT: #define __ATOMIC_SEQ_CST 5
+// LA32: #define __BIGGEST_ALIGNMENT__ 16
+// LA32: #define __BITINT_MAXWIDTH__ 128
+// LA32: #define __BOOL_WIDTH__ 8
+// LA32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// LA32: #define __CHAR16_TYPE__ unsigned short
+// LA32: #define __CHAR32_TYPE__ unsigned int
+// LA32: #define __CHAR_BIT__ 8
+// LA32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_INT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 1
+// LA32: #define __DBL_DECIMAL_DIG__ 17
+// LA32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// LA32: #define __DBL_DIG__ 15
+// LA32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// LA32: #define __DBL_HAS_DENORM__ 1
+// LA32: #define __DBL_HAS_INFINITY__ 1
+// LA32: #define __DBL_HAS_QUIET_NAN__ 1
+// LA32: #define __DBL_MANT_DIG__ 53
+// LA32: #define __DBL_MAX_10_EXP__ 308
+// LA32: #define __DBL_MAX_EXP__ 1024
+// LA32: #define __DBL_MAX__ 1.7976931348623157e+308
+// LA32: #define __DBL_MIN_10_EX

[PATCH] D130255: [Clang][LoongArch] Add initial LoongArch target and driver support

[Lu Weining via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG15b65bcd6519: [Clang][LoongArch] Add initial LoongArch 
target and driver support (authored by SixWeining).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130255/new/

https://reviews.llvm.org/D130255

Files:
  clang/lib/Basic/CMakeLists.txt
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Clang.h
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/bin/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/include/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64d/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64f/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/base/lp64s/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/lib/gcc/loongarch64-unknown-linux-gnu/12.1.0/crtbegin.o
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/bin/ld
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib/.keep
  
clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/loongarch64-unknown-linux-gnu/lib64/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib/.keep
  clang/test/Driver/Inputs/multilib_loongarch_linux_sdk/sysroot/usr/lib64/.keep
  clang/test/Driver/frame-pointer.c
  clang/test/Driver/loongarch-abi-error.c
  clang/test/Driver/loongarch-abi.c
  clang/test/Driver/loongarch-toolchain.c
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- /dev/null
+++ clang/test/Preprocessor/init-loongarch.c
@@ -0,0 +1,641 @@
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch32 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA32 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch32-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA32,LA32-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch32 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA32,LA32-INT128 %s
+
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch64 /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefix=LA64 %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch64-unknown-linux /dev/null \
+// RUN:   | FileCheck --match-full-lines --check-prefixes=LA64,LA64-LINUX %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple loongarch64 \
+// RUN: -fforce-enable-int128 /dev/null | FileCheck --match-full-lines \
+// RUN: --check-prefixes=LA64,LA64-INT128 %s
+
+ Note that common macros are tested in init.c, such as __VERSION__. So they're not listed here.
+
+// LA32: #define _ILP32 1
+// LA32: #define __ATOMIC_ACQUIRE 2
+// LA32-NEXT: #define __ATOMIC_ACQ_REL 4
+// LA32-NEXT: #define __ATOMIC_CONSUME 1
+// LA32-NEXT: #define __ATOMIC_RELAXED 0
+// LA32-NEXT: #define __ATOMIC_RELEASE 3
+// LA32-NEXT: #define __ATOMIC_SEQ_CST 5
+// LA32: #define __BIGGEST_ALIGNMENT__ 16
+// LA32: #define __BITINT_MAXWIDTH__ 128
+// LA32: #define __BOOL_WIDTH__ 8
+// LA32: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
+// LA32: #define __CHAR16_TYPE__ unsigned short
+// LA32: #define __CHAR32_TYPE__ unsigned int
+// LA32: #define __CHAR_BIT__ 8
+// LA32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_INT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LONG_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 1
+// LA32: #define __DBL_DECIMAL_DIG__ 17
+// LA32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
+// LA32: #define __DBL_DIG__ 15
+// LA32: #define __DBL_EPSILON__ 2.2204460492503131e-16
+// LA32: #define __DBL_HAS_DENORM__ 1
+// LA32: #define __DBL_HAS_INFINITY__ 1
+// LA32: #define __DBL_HAS_QUIET_NAN__ 1
+// LA32: #define __DBL_MANT_DIG__ 53
+// LA32: #define __DBL_MAX_10_EXP__ 308
+// LA32: #define __DBL_MAX_EXP__ 1024
+// LA32: #define __DBL

[PATCH] D132285: [LoongArch] Implement ABI lowering

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.



In D132285#3739568 , @xry111 wrote:

> In D132285#3737855 , @SixWeining 
> wrote:
>
>> Ignore zero-width bit fields and add a test.
>
> Thanks!  There is a GCC test (https://gcc.gnu.org/r12-7951) which can be used 
> to test if there is any ABI incompatibility between GCC and Clang, but I 
> guess it's not possible to run it at the early development stage of Clang.  
> Maybe we can run it later.

Thanks. Let me add a test for zero size arrays.

And, with the parent revison D130255  landed, 
we can compile `.c` programs to loongarch executables now. But currently since 
the `f` and `d` target feaures  can not been passed to clang cc1 yet, we may 
manually pass them to clang cc1 to generate floating-point instructions. For 
example:

  $ clang --target=loongarch64-unknown-linux-gnu --gcc-toolchain=xxx 
--sysroot=xxx -Xclang -target-feature -Xclang +f main.c


Repository:
  rG LLVM Github Monorepo

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[PATCH] D132285: [LoongArch] Implement ABI lowering

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 454705.
SixWeining added a comment.

Add a test for struct with zero size arrays.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132285/new/

https://reviews.llvm.org/D132285

Files:
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/LoongArch/abi-lp64d.c
  clang/test/CodeGen/ext-int-cc.c
  clang/test/CodeGenCXX/LoongArch/abi-lp64d-struct-inherit.cpp

Index: clang/test/CodeGenCXX/LoongArch/abi-lp64d-struct-inherit.cpp
===
--- /dev/null
+++ clang/test/CodeGenCXX/LoongArch/abi-lp64d-struct-inherit.cpp
@@ -0,0 +1,95 @@
+// RUN: %clang_cc1 -triple loongarch64 -target-feature +f -target-feature +d -target-abi lp64d \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+
+#include 
+
+/// Ensure that fields inherited from a parent struct are treated in the same
+/// way as fields directly in the child for the purposes of LoongArch ABI rules.
+
+struct parent1_int32_s {
+  int32_t i1;
+};
+
+struct child1_int32_s : parent1_int32_s {
+  int32_t i2;
+};
+
+// CHECK-LABEL: define{{.*}} i64 @_Z30int32_int32_struct_inheritance14child1_int32_s(i64 %a.coerce)
+struct child1_int32_s int32_int32_struct_inheritance(struct child1_int32_s a) {
+  return a;
+}
+
+struct parent2_int32_s {
+  int32_t i1;
+};
+
+struct child2_float_s : parent2_int32_s {
+  float f1;
+};
+
+// CHECK-LABEL: define{{.*}} { i32, float } @_Z30int32_float_struct_inheritance14child2_float_s(i32 %0, float %1)
+struct child2_float_s int32_float_struct_inheritance(struct child2_float_s a) {
+  return a;
+}
+
+struct parent3_float_s {
+  float f1;
+};
+
+struct child3_int64_s : parent3_float_s {
+  int64_t i1;
+};
+
+// CHECK-LABEL: define{{.*}} { float, i64 } @_Z30float_int64_struct_inheritance14child3_int64_s(float %0, i64 %1)
+struct child3_int64_s float_int64_struct_inheritance(struct child3_int64_s a) {
+  return a;
+}
+
+struct parent4_double_s {
+  double d1;
+};
+
+struct child4_double_s : parent4_double_s {
+  double d1;
+};
+
+// CHECK-LABEL: define{{.*}} { double, double } @_Z32double_double_struct_inheritance15child4_double_s(double %0, double %1)
+struct child4_double_s double_double_struct_inheritance(struct child4_double_s a) {
+  return a;
+}
+
+/// When virtual inheritance is used, the resulting struct isn't eligible for
+/// passing in registers.
+
+struct parent5_virtual_s {
+  int32_t i1;
+};
+
+struct child5_virtual_s : virtual parent5_virtual_s {
+  float f1;
+};
+
+// CHECK-LABEL: define{{.*}} void @_ZN16child5_virtual_sC1EOS_(ptr noundef nonnull align 8 dereferenceable(12) %this, ptr noundef nonnull align 8 dereferenceable(12) %0)
+struct child5_virtual_s int32_float_virtual_struct_inheritance(struct child5_virtual_s a) {
+  return a;
+}
+
+/// Check for correct lowering in the presence of diamond inheritance.
+
+struct parent6_float_s {
+  float f1;
+};
+
+struct child6a_s : parent6_float_s {
+};
+
+struct child6b_s : parent6_float_s {
+};
+
+struct grandchild_6_s : child6a_s, child6b_s {
+};
+
+// CHECK-LABEL: define{{.*}} { float, float } @_Z38float_float_diamond_struct_inheritance14grandchild_6_s(float %0, float %1)
+struct grandchild_6_s float_float_diamond_struct_inheritance(struct grandchild_6_s a) {
+  return a;
+}
Index: clang/test/CodeGen/ext-int-cc.c
===
--- clang/test/CodeGen/ext-int-cc.c
+++ clang/test/CodeGen/ext-int-cc.c
@@ -27,6 +27,8 @@
 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple arm64_32-apple-ios -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64
 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple arm64_32-apple-ios -target-abi darwinpcs -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64DARWIN
 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple arm -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=ARM
+// RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple loongarch64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=LA64
+// RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple loongarch32 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=LA32
 
 // Make sure 128 and 64 bit versions are passed like integers.
 void ParamPassing(_BitInt(128) b, _BitInt(64) c) {}
@@ -57,6 +59,8 @@
 // AARCH64: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
 // AARCH64DARWIN: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
 // ARM: define{{.*}} arm_aapcscc void @ParamPassing(i128* byval(i128) align 8 %{{.+}}, i64 %{{.+}})
+// LA64: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
+// LA32: define{{.*}} void @ParamPassing(i128* %{{.+}}, i64 %{{.+}})
 
 void ParamPassing2(_BitInt(127) b, _BitInt(63

[PATCH] D132285: [Clang][LoongArch] Implement ABI lowering

[Lu Weining via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7d88a05cc01c: [Clang][LoongArch] Implement ABI lowering 
(authored by SixWeining).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D132285/new/

https://reviews.llvm.org/D132285

Files:
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/LoongArch/abi-lp64d.c
  clang/test/CodeGen/ext-int-cc.c
  clang/test/CodeGenCXX/LoongArch/abi-lp64d-struct-inherit.cpp

Index: clang/test/CodeGenCXX/LoongArch/abi-lp64d-struct-inherit.cpp
===
--- /dev/null
+++ clang/test/CodeGenCXX/LoongArch/abi-lp64d-struct-inherit.cpp
@@ -0,0 +1,95 @@
+// RUN: %clang_cc1 -triple loongarch64 -target-feature +f -target-feature +d -target-abi lp64d \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+
+#include 
+
+/// Ensure that fields inherited from a parent struct are treated in the same
+/// way as fields directly in the child for the purposes of LoongArch ABI rules.
+
+struct parent1_int32_s {
+  int32_t i1;
+};
+
+struct child1_int32_s : parent1_int32_s {
+  int32_t i2;
+};
+
+// CHECK-LABEL: define{{.*}} i64 @_Z30int32_int32_struct_inheritance14child1_int32_s(i64 %a.coerce)
+struct child1_int32_s int32_int32_struct_inheritance(struct child1_int32_s a) {
+  return a;
+}
+
+struct parent2_int32_s {
+  int32_t i1;
+};
+
+struct child2_float_s : parent2_int32_s {
+  float f1;
+};
+
+// CHECK-LABEL: define{{.*}} { i32, float } @_Z30int32_float_struct_inheritance14child2_float_s(i32 %0, float %1)
+struct child2_float_s int32_float_struct_inheritance(struct child2_float_s a) {
+  return a;
+}
+
+struct parent3_float_s {
+  float f1;
+};
+
+struct child3_int64_s : parent3_float_s {
+  int64_t i1;
+};
+
+// CHECK-LABEL: define{{.*}} { float, i64 } @_Z30float_int64_struct_inheritance14child3_int64_s(float %0, i64 %1)
+struct child3_int64_s float_int64_struct_inheritance(struct child3_int64_s a) {
+  return a;
+}
+
+struct parent4_double_s {
+  double d1;
+};
+
+struct child4_double_s : parent4_double_s {
+  double d1;
+};
+
+// CHECK-LABEL: define{{.*}} { double, double } @_Z32double_double_struct_inheritance15child4_double_s(double %0, double %1)
+struct child4_double_s double_double_struct_inheritance(struct child4_double_s a) {
+  return a;
+}
+
+/// When virtual inheritance is used, the resulting struct isn't eligible for
+/// passing in registers.
+
+struct parent5_virtual_s {
+  int32_t i1;
+};
+
+struct child5_virtual_s : virtual parent5_virtual_s {
+  float f1;
+};
+
+// CHECK-LABEL: define{{.*}} void @_ZN16child5_virtual_sC1EOS_(ptr noundef nonnull align 8 dereferenceable(12) %this, ptr noundef nonnull align 8 dereferenceable(12) %0)
+struct child5_virtual_s int32_float_virtual_struct_inheritance(struct child5_virtual_s a) {
+  return a;
+}
+
+/// Check for correct lowering in the presence of diamond inheritance.
+
+struct parent6_float_s {
+  float f1;
+};
+
+struct child6a_s : parent6_float_s {
+};
+
+struct child6b_s : parent6_float_s {
+};
+
+struct grandchild_6_s : child6a_s, child6b_s {
+};
+
+// CHECK-LABEL: define{{.*}} { float, float } @_Z38float_float_diamond_struct_inheritance14grandchild_6_s(float %0, float %1)
+struct grandchild_6_s float_float_diamond_struct_inheritance(struct grandchild_6_s a) {
+  return a;
+}
Index: clang/test/CodeGen/ext-int-cc.c
===
--- clang/test/CodeGen/ext-int-cc.c
+++ clang/test/CodeGen/ext-int-cc.c
@@ -27,6 +27,8 @@
 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple arm64_32-apple-ios -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64
 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple arm64_32-apple-ios -target-abi darwinpcs -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=AARCH64DARWIN
 // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple arm -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=ARM
+// RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple loongarch64 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=LA64
+// RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -triple loongarch32 -O3 -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s --check-prefixes=LA32
 
 // Make sure 128 and 64 bit versions are passed like integers.
 void ParamPassing(_BitInt(128) b, _BitInt(64) c) {}
@@ -57,6 +59,8 @@
 // AARCH64: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
 // AARCH64DARWIN: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
 // ARM: define{{.*}} arm_aapcscc void @ParamPassing(i128* byval(i128) align 8 %{{.+}}, i64 %{{.+}})
+// LA64: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
+// LA32: define{{.*}} void @ParamPassing(i128* %{{.+}}, i64 %{{.+

[PATCH] D134157: [LoongArch] Add inline asm support for constraints f/l/I/K

[Lu Weining via Phabricator via cfe-commits]

SixWeining created this revision.
SixWeining added reviewers: xen0n, MaskRay, xry111, rengolin, myhsu, wangleiat, 
gonglingqin.
Herald added subscribers: StephenFan, JDevlieghere, hiraditya.
Herald added a project: All.
SixWeining requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch adds support for constraints `f`, `l`, `I`, `K` according
to [1]. The remain constraints (`k`, `m`, `ZB`, `ZC`) will be added
later as they are a little more complex than the others.
f: A floating-point register (if available).
l: A signed 16-bit constant.
I: A signed 12-bit constant (for arithmetic instructions).
K: An unsigned 12-bit constant (for logic instructions).

For now, no need to support register alias (e.g. `$a0`) in llvm as
clang will correctly decode the usage of register name aliases into
their official names. And AFAIK, the not yet upstreamed `rustc` for
LoongArch will always use official register names (e.g. `$r4`).

[1] https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134157

Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/test/CodeGen/LoongArch/inline-asm-constraints-error.c
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  clang/test/CodeGen/LoongArch/inline-asm-gcc-regs-error.c
  clang/test/CodeGen/LoongArch/inline-asm-gcc-regs.c
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/test/CodeGen/LoongArch/inline-asm-clobbers.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-f.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names-f-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names-f.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-reg-names.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-reg-names.ll
@@ -0,0 +1,109 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s \
+; RUN:   | FileCheck --check-prefix=LA32 %s
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s \
+; RUN:   | FileCheck --check-prefix=LA64 %s
+
+;; These test that we can use architectural names ($r*) refer to registers in
+;; inline asm constraint lists. In each case, the named register should be used
+;; for the source register of the `addi.w`. It is very likely that `$a0` will
+;; be chosen as the designation register, but this is left to the compiler to
+;; choose.
+;;
+;; Parenthesised registers in comments are the other aliases for this register.
+
+;; NOTE: This test has to pass in 0 to the inline asm, because that's the only
+;; value `$r0` (`$zero`) can take.
+define i32 @register_r0() nounwind {
+; LA32-LABEL: register_r0:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $zero, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r0:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $zero, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, 0", "=r,{$r0}"(i32 0)
+  ret i32 %1
+}
+
+define i32 @register_r4(i32 %a) nounwind {
+; LA32-LABEL: register_r4:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $a0, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r4:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $a0, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, 1", "=r,{$r4}"(i32 %a)
+  ret i32 %1
+}
+
+;; NOTE: This test uses `$r22` (`$s9`, `$fp`) as an input, so it should be saved.
+define i32 @register_r22(i32 %a) nounwind {
+; LA32-LABEL: register_r22:
+; LA32:   # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:st.w $fp, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:move $fp, $a0
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $fp, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ld.w $fp, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r22:
+; LA64:   # %bb.0:
+; LA64-NEXT:addi.d $sp, $sp, -16
+; LA64-NEXT:st.d $fp, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:move $fp, $a0
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $fp, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ld.d $fp, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT:addi.d $sp, $sp, 16
+; LA64-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, 1", "=r,{$r22}"(i32 %a)
+  ret i32 %1
+}
+
+;; 

[PATCH] D134157: [LoongArch] Add inline asm support for constraints f/l/I/K

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 462139.
SixWeining added a comment.

Use double dashes for --mtriple.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134157/new/

https://reviews.llvm.org/D134157

Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/test/CodeGen/LoongArch/inline-asm-constraints-error.c
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  clang/test/CodeGen/LoongArch/inline-asm-gcc-regs-error.c
  clang/test/CodeGen/LoongArch/inline-asm-gcc-regs.c
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/test/CodeGen/LoongArch/inline-asm-clobbers.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-f.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names-f-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names-f.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-reg-names.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-reg-names.ll
@@ -0,0 +1,109 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s \
+; RUN:   | FileCheck --check-prefix=LA32 %s
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s \
+; RUN:   | FileCheck --check-prefix=LA64 %s
+
+;; These test that we can use architectural names ($r*) refer to registers in
+;; inline asm constraint lists. In each case, the named register should be used
+;; for the source register of the `addi.w`. It is very likely that `$a0` will
+;; be chosen as the designation register, but this is left to the compiler to
+;; choose.
+;;
+;; Parenthesised registers in comments are the other aliases for this register.
+
+;; NOTE: This test has to pass in 0 to the inline asm, because that's the only
+;; value `$r0` (`$zero`) can take.
+define i32 @register_r0() nounwind {
+; LA32-LABEL: register_r0:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $zero, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r0:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $zero, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, 0", "=r,{$r0}"(i32 0)
+  ret i32 %1
+}
+
+define i32 @register_r4(i32 %a) nounwind {
+; LA32-LABEL: register_r4:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $a0, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r4:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $a0, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, 1", "=r,{$r4}"(i32 %a)
+  ret i32 %1
+}
+
+;; NOTE: This test uses `$r22` (`$s9`, `$fp`) as an input, so it should be saved.
+define i32 @register_r22(i32 %a) nounwind {
+; LA32-LABEL: register_r22:
+; LA32:   # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:st.w $fp, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:move $fp, $a0
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $fp, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ld.w $fp, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r22:
+; LA64:   # %bb.0:
+; LA64-NEXT:addi.d $sp, $sp, -16
+; LA64-NEXT:st.d $fp, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:move $fp, $a0
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $fp, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ld.d $fp, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT:addi.d $sp, $sp, 16
+; LA64-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, 1", "=r,{$r22}"(i32 %a)
+  ret i32 %1
+}
+
+;; NOTE: This test uses `$r31` (`$s8`) as an input, so it should be saved.
+define i32 @register_r31(i32 %a) nounwind {
+; LA32-LABEL: register_r31:
+; LA32:   # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:st.w $s8, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:move $s8, $a0
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $s8, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ld.w $s8, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r31:
+; LA64:   # %bb.0:
+; LA64-NEXT:addi.d $sp, $sp, -16
+; LA64-NEXT:st.d $s8, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:move $s8, $a0
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $s8, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ld.d $s8, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT:addi.d $sp, $sp, 16
+; LA64-NEXT:ret
+  %1 = tail call i32 as

[PATCH] D134157: [LoongArch] Add inline asm support for constraints f/l/I/K

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D134157#3805855 , @xen0n wrote:

> I don't know if the clang changes should be split into its own commit (or the 
> title of this commit amended to mention `[Clang]` but I don't know if this is 
> appropriate), but the rest looks reasonable.

Yes, I ever thought about spliting the patches into 2 (clang+llvm). But I 
finally decide to use a single one becuse I think this may help others a bit to 
understand how these inline asm(constrainsts, ...) are used and translated from 
frontend to backend.


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[PATCH] D134157: [Clang][LoongArch] Add inline asm support for constraints f/l/I/K

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 462388.
SixWeining added a comment.

Address @rengolin's comments.

1. Clip the '$' from original constraint string and match table-gen'd names.
2. Delete unnecessary check prefix in tests.


Repository:
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Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/test/CodeGen/LoongArch/inline-asm-constraints-error.c
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  clang/test/CodeGen/LoongArch/inline-asm-gcc-regs-error.c
  clang/test/CodeGen/LoongArch/inline-asm-gcc-regs.c
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/test/CodeGen/LoongArch/inline-asm-clobbers.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-f.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names-f-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names-f.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-reg-names.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-reg-names.ll
@@ -0,0 +1,109 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s \
+; RUN:   | FileCheck --check-prefix=LA32 %s
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s \
+; RUN:   | FileCheck --check-prefix=LA64 %s
+
+;; These test that we can use architectural names ($r*) refer to registers in
+;; inline asm constraint lists. In each case, the named register should be used
+;; for the source register of the `addi.w`. It is very likely that `$a0` will
+;; be chosen as the designation register, but this is left to the compiler to
+;; choose.
+;;
+;; Parenthesised registers in comments are the other aliases for this register.
+
+;; NOTE: This test has to pass in 0 to the inline asm, because that's the only
+;; value `$r0` (`$zero`) can take.
+define i32 @register_r0() nounwind {
+; LA32-LABEL: register_r0:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $zero, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r0:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $zero, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, 0", "=r,{$r0}"(i32 0)
+  ret i32 %1
+}
+
+define i32 @register_r4(i32 %a) nounwind {
+; LA32-LABEL: register_r4:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $a0, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r4:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $a0, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, 1", "=r,{$r4}"(i32 %a)
+  ret i32 %1
+}
+
+;; NOTE: This test uses `$r22` (`$s9`, `$fp`) as an input, so it should be saved.
+define i32 @register_r22(i32 %a) nounwind {
+; LA32-LABEL: register_r22:
+; LA32:   # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:st.w $fp, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:move $fp, $a0
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $fp, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ld.w $fp, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r22:
+; LA64:   # %bb.0:
+; LA64-NEXT:addi.d $sp, $sp, -16
+; LA64-NEXT:st.d $fp, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:move $fp, $a0
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $fp, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ld.d $fp, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT:addi.d $sp, $sp, 16
+; LA64-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, 1", "=r,{$r22}"(i32 %a)
+  ret i32 %1
+}
+
+;; NOTE: This test uses `$r31` (`$s8`) as an input, so it should be saved.
+define i32 @register_r31(i32 %a) nounwind {
+; LA32-LABEL: register_r31:
+; LA32:   # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:st.w $s8, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:move $s8, $a0
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $s8, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ld.w $s8, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r31:
+; LA64:   # %bb.0:
+; LA64-NEXT:addi.d $sp, $sp, -16
+; LA64-NEXT:st.d $s8, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:move $s8, $a0
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $s8, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ld

[PATCH] D134157: [Clang][LoongArch] Add inline asm support for constraints f/l/I/K

[Lu Weining via Phabricator via cfe-commits]

SixWeining added inline comments.



Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp:1958
+  // constraints while the official register name is prefixed with a '$'.
+  // So we manually select general purpose registers here.
+  // For now, no need to support ABI names (e.g. `$a0`) as clang will correctly

rengolin wrote:
> Can't you just clip the `$`, upper-case and match against some table-gen'd 
> names?
Yes, it can reduce much code. Thanks.



Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp:2064
+uint64_t CVal = C->getSExtValue();
+if (isInt<16>(CVal))
+  Ops.push_back(

rengolin wrote:
> Shouldn't this break if the constant isn't in the right type? What happens if 
> it isn't? 
> 
> It seems it just doesn't append the operand and return. Wouldn't that just 
> break the op's format?
> 
> On Arm, the logic is simpler:
>  - Iterate through all constraints, validating the input
>  - If valie, set the Result and append to the Op at the end
>  - Otherwise bail and let `TargetLowering::LowerAsmOperandForConstraint` 
> handle it.
If the constant isn't in the right type, SelectionDAGBuilder will emit an 
error. There is a test 
`llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll` checking this.
```
// CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
   8987   if (OpInfo.ConstraintType == TargetLowering::C_Immediate ||
   8988   OpInfo.ConstraintType == TargetLowering::C_Other) {
   8989 std::vector Ops;
   8990 TLI.LowerAsmOperandForConstraint(InOperandVal, 
OpInfo.ConstraintCode,
   8991   Ops, DAG);
   8992 if (Ops.empty()) {
   8993   if (OpInfo.ConstraintType == TargetLowering::C_Immediate)
   8994 if (isa(InOperandVal)) {
   8995   emitInlineAsmError(Call, "value out of range for 
constraint '" +
   8996Twine(OpInfo.ConstraintCode) 
+ "'");
   8997   return;
   8998 }
```


For arm/aarch64, if the input is invalid, the function also directly return.
```
// AArch64ISelLowering.cpp
   9583 case 'K':
   9584   if (AArch64_AM::isLogicalImmediate(CVal, 32))
   9585 break;
   9586   return;
   9587 case 'L':
   9588   if (AArch64_AM::isLogicalImmediate(CVal, 64))
   9589 break;
   9590   return;
```

For LoongArch, `TargetLowering::LowerAsmOperandForConstraint` is only called 
when the constraint is not one of `l/I/K`.



Comment at: llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll:5
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs --no-integrated-as < 
%s \
+; RUN:   | FileCheck --check-prefix=LA64 %s
+

rengolin wrote:
> I'm not seeing differences between LA32 and LA64, is splitting the CHECK 
> lines really necessary?
> 
> On some other tests, too...
Yes. Let me remove them. Thanks.


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[PATCH] D134157: [Clang][LoongArch] Add inline asm support for constraints f/l/I/K

[Lu Weining via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG394f30919a02: [Clang][LoongArch] Add inline asm support for 
constraints f/l/I/K (authored by SixWeining).

Repository:
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Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/test/CodeGen/LoongArch/inline-asm-constraints-error.c
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  clang/test/CodeGen/LoongArch/inline-asm-gcc-regs-error.c
  clang/test/CodeGen/LoongArch/inline-asm-gcc-regs.c
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/test/CodeGen/LoongArch/inline-asm-clobbers.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-f.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names-f-error.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names-f.ll
  llvm/test/CodeGen/LoongArch/inline-asm-reg-names.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-reg-names.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-reg-names.ll
@@ -0,0 +1,109 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s \
+; RUN:   | FileCheck --check-prefix=LA32 %s
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s \
+; RUN:   | FileCheck --check-prefix=LA64 %s
+
+;; These test that we can use architectural names ($r*) refer to registers in
+;; inline asm constraint lists. In each case, the named register should be used
+;; for the source register of the `addi.w`. It is very likely that `$a0` will
+;; be chosen as the designation register, but this is left to the compiler to
+;; choose.
+;;
+;; Parenthesised registers in comments are the other aliases for this register.
+
+;; NOTE: This test has to pass in 0 to the inline asm, because that's the only
+;; value `$r0` (`$zero`) can take.
+define i32 @register_r0() nounwind {
+; LA32-LABEL: register_r0:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $zero, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r0:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $zero, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, 0", "=r,{$r0}"(i32 0)
+  ret i32 %1
+}
+
+define i32 @register_r4(i32 %a) nounwind {
+; LA32-LABEL: register_r4:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $a0, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r4:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $a0, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, 1", "=r,{$r4}"(i32 %a)
+  ret i32 %1
+}
+
+;; NOTE: This test uses `$r22` (`$s9`, `$fp`) as an input, so it should be saved.
+define i32 @register_r22(i32 %a) nounwind {
+; LA32-LABEL: register_r22:
+; LA32:   # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:st.w $fp, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:move $fp, $a0
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $fp, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ld.w $fp, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r22:
+; LA64:   # %bb.0:
+; LA64-NEXT:addi.d $sp, $sp, -16
+; LA64-NEXT:st.d $fp, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:move $fp, $a0
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $fp, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ld.d $fp, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT:addi.d $sp, $sp, 16
+; LA64-NEXT:ret
+  %1 = tail call i32 asm "addi.w $0, $1, 1", "=r,{$r22}"(i32 %a)
+  ret i32 %1
+}
+
+;; NOTE: This test uses `$r31` (`$s8`) as an input, so it should be saved.
+define i32 @register_r31(i32 %a) nounwind {
+; LA32-LABEL: register_r31:
+; LA32:   # %bb.0:
+; LA32-NEXT:addi.w $sp, $sp, -16
+; LA32-NEXT:st.w $s8, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:move $s8, $a0
+; LA32-NEXT:#APP
+; LA32-NEXT:addi.w $a0, $s8, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ld.w $s8, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:addi.w $sp, $sp, 16
+; LA32-NEXT:ret
+;
+; LA64-LABEL: register_r31:
+; LA64:   # %bb.0:
+; LA64-NEXT:addi.d $sp, $sp, -16
+; LA64-NEXT:st.d $s8, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:move $s8, $a0
+; LA64-NEXT:#APP
+; LA64-NEXT:addi.w $a0, $s8, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ld.d $s8, $sp, 8 # 8-byte Folded R

[PATCH] D134638: [Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC

[Lu Weining via Phabricator via cfe-commits]

SixWeining created this revision.
SixWeining added reviewers: xen0n, xry111, MaskRay, rengolin, wangleiat, 
gonglingqin.
Herald added subscribers: StephenFan, hiraditya.
Herald added a project: All.
SixWeining requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

k: A memory operand whose address is formed by a base register and
(optionally scaled) index register.

m: A memory operand whose address is formed by a base register and
offset that is suitable for use in instructions with the same
addressing mode as st.w and ld.w.

ZB: An address that is held in a general-purpose register. The offset
is zero.

ZC: A memory operand whose address is formed by a base register and
offset that is suitable for use in instructions with the same
addressing mode as ll.w and sc.w.


Repository:
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https://reviews.llvm.org/D134638

Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  llvm/include/llvm/IR/InlineAsm.h
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZB.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-k.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
+
+define i32 @m_offset_neg_2049(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2049:
+; LA32:   # %bb.0:
+; LA32-NEXT:lu12i.w $a1, -1
+; LA32-NEXT:ori $a1, $a1, 2047
+; LA32-NEXT:add.w $a0, $a0, $a1
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2049:
+; LA64:   # %bb.0:
+; LA64-NEXT:lu12i.w $a1, -1
+; LA64-NEXT:ori $a1, $a1, 2047
+; LA64-NEXT:add.d $a0, $a0, $a1
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2049
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2048:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -2048
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2048:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -2048
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2048
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_1:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_1:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -1
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_0(ptr %p) nounwind {
+; LA32-LABEL: m_offset_0:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_0:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %p)
+  ret i32 %1
+}
+
+define i32 @m_offset_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_1:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_1:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 1
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_2047(ptr %p) nounwind {
+; LA32-LABEL: m_offset_2047:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 2047
+; LA32-NEXT:#NO

[PATCH] D134638: [Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 463395.
SixWeining marked 4 inline comments as done.
SixWeining added a comment.

Address comments from @rengolin and @MaskRay. Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134638/new/

https://reviews.llvm.org/D134638

Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  llvm/include/llvm/IR/InlineAsm.h
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZB.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-k.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
+
+define i32 @m_offset_neg_2049(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2049:
+; LA32:   # %bb.0:
+; LA32-NEXT:lu12i.w $a1, -1
+; LA32-NEXT:ori $a1, $a1, 2047
+; LA32-NEXT:add.w $a0, $a0, $a1
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2049:
+; LA64:   # %bb.0:
+; LA64-NEXT:lu12i.w $a1, -1
+; LA64-NEXT:ori $a1, $a1, 2047
+; LA64-NEXT:add.d $a0, $a0, $a1
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2049
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2048:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -2048
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2048:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -2048
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2048
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_1:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_1:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -1
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_0(ptr %p) nounwind {
+; LA32-LABEL: m_offset_0:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_0:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %p)
+  ret i32 %1
+}
+
+define i32 @m_offset_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_1:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_1:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 1
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_2047(ptr %p) nounwind {
+; LA32-LABEL: m_offset_2047:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 2047
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_2047:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 2047
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 2047
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_2048:
+; LA32:   # %bb.0:
+; LA32-NEXT:ori $a1, $zero, 2048
+; LA32-NEXT:add.w $a0, $a0, $a1
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:re

[PATCH] D134638: [Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC

[Lu Weining via Phabricator via cfe-commits]

SixWeining added inline comments.



Comment at: clang/lib/Basic/Targets/LoongArch.cpp:117
+// parsing.
+R = std::string("^") + std::string(Constraint, 2);
+Constraint++;

MaskRay wrote:
> First `std::string` can be omitted
Thanks.



Comment at: llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp:76
+  // TODO: handle extra code.
+  if (!ExtraCode) {
+const MachineOperand &BaseMO = MI->getOperand(OpNo);

rengolin wrote:
> NIT: Use early exit.
> 
> if (ExtraCode)
>   return false;
Thanks. But we should return `true` but not `false`.



Comment at: llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll:16
+;
+; LA64-LABEL: ZC_offset_neg_32769:
+; LA64:   # %bb.0:

rengolin wrote:
> Same comment as before, these CHECK lines look identical for both targets...
Unfortunately this is not the case becuase different instructions like 
`add.w`/`add.d` are used by LA32 and LA64 respectively.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D134638: [Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 463404.
SixWeining added a comment.

Handle k and ZB in llvm/include/llvm/IR/InlineAsm.h::getMemConstraintName and 
add relevant tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134638/new/

https://reviews.llvm.org/D134638

Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  llvm/include/llvm/IR/InlineAsm.h
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZB.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-k.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
+
+define i32 @m_offset_neg_2049(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2049:
+; LA32:   # %bb.0:
+; LA32-NEXT:lu12i.w $a1, -1
+; LA32-NEXT:ori $a1, $a1, 2047
+; LA32-NEXT:add.w $a0, $a0, $a1
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2049:
+; LA64:   # %bb.0:
+; LA64-NEXT:lu12i.w $a1, -1
+; LA64-NEXT:ori $a1, $a1, 2047
+; LA64-NEXT:add.d $a0, $a0, $a1
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2049
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2048:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -2048
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2048:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -2048
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2048
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_1:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_1:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -1
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_0(ptr %p) nounwind {
+; LA32-LABEL: m_offset_0:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_0:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %p)
+  ret i32 %1
+}
+
+define i32 @m_offset_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_1:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_1:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 1
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_2047(ptr %p) nounwind {
+; LA32-LABEL: m_offset_2047:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 2047
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_2047:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 2047
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 2047
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_2048:
+; LA32:   # %bb.0:
+; LA32-NEXT:ori $a1, $zero, 2048
+; LA32-NEXT:add.w $a0, $a0, $a1
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:re

[PATCH] D134638: [Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 463408.
SixWeining added a comment.

Remove the first line "Assertions" in inline-asm-constraint-ZB.ll as it is not 
autogenerated.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134638/new/

https://reviews.llvm.org/D134638

Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  llvm/include/llvm/IR/InlineAsm.h
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZB.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-k.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
+
+define i32 @m_offset_neg_2049(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2049:
+; LA32:   # %bb.0:
+; LA32-NEXT:lu12i.w $a1, -1
+; LA32-NEXT:ori $a1, $a1, 2047
+; LA32-NEXT:add.w $a0, $a0, $a1
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2049:
+; LA64:   # %bb.0:
+; LA64-NEXT:lu12i.w $a1, -1
+; LA64-NEXT:ori $a1, $a1, 2047
+; LA64-NEXT:add.d $a0, $a0, $a1
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2049
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2048:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -2048
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2048:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -2048
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2048
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_1:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_1:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -1
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_0(ptr %p) nounwind {
+; LA32-LABEL: m_offset_0:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_0:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %p)
+  ret i32 %1
+}
+
+define i32 @m_offset_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_1:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_1:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 1
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_2047(ptr %p) nounwind {
+; LA32-LABEL: m_offset_2047:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 2047
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_2047:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 2047
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 2047
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_2048:
+; LA32:   # %bb.0:
+; LA32-NEXT:ori $a1, $zero, 2048
+; LA32-NEXT:add.w $a0, $a0, $a1
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;

[PATCH] D134638: [Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC

[Lu Weining via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb7baddc7557e: [Clang][LoongArch] Add inline asm support for 
constraints k/m/ZB/ZC (authored by SixWeining).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134638/new/

https://reviews.llvm.org/D134638

Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  llvm/include/llvm/IR/InlineAsm.h
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZB.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-k.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll

Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
+
+define i32 @m_offset_neg_2049(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2049:
+; LA32:   # %bb.0:
+; LA32-NEXT:lu12i.w $a1, -1
+; LA32-NEXT:ori $a1, $a1, 2047
+; LA32-NEXT:add.w $a0, $a0, $a1
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2049:
+; LA64:   # %bb.0:
+; LA64-NEXT:lu12i.w $a1, -1
+; LA64-NEXT:ori $a1, $a1, 2047
+; LA64-NEXT:add.d $a0, $a0, $a1
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2049
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2048:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -2048
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2048:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -2048
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2048
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_1:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_1:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -1
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_0(ptr %p) nounwind {
+; LA32-LABEL: m_offset_0:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_0:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %p)
+  ret i32 %1
+}
+
+define i32 @m_offset_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_1:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_1:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 1
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_2047(ptr %p) nounwind {
+; LA32-LABEL: m_offset_2047:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 2047
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_2047:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 2047
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 2047
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_2048:
+; LA32:   # %bb.0:
+; LA32-NEXT:ori $a1, $zero, 2048
+; LA32-NEXT:add.w $a0, $a0, $a1
+; LA32-NEXT:#AP

[PATCH] D134638: [Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 463815.
SixWeining added a comment.
Herald added a subscriber: pengfei.

The flag in the INLINEASM SDNode in llvm/test/CodeGen/X86/callbr-asm-kill.mir 
is updated because enum `Constraint_k` is added before `Constraint_m`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134638/new/

https://reviews.llvm.org/D134638

Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  llvm/include/llvm/IR/InlineAsm.h
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZB.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-k.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
  llvm/test/CodeGen/X86/callbr-asm-kill.mir

Index: llvm/test/CodeGen/X86/callbr-asm-kill.mir
===
--- llvm/test/CodeGen/X86/callbr-asm-kill.mir
+++ llvm/test/CodeGen/X86/callbr-asm-kill.mir
@@ -67,7 +67,7 @@
   ; CHECK-NEXT:   CALL64pcrel32 target-flags(x86-plt) @foo, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp
   ; CHECK-NEXT:   ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
   ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gr64 = COPY [[MOV64rm]]
-  ; CHECK-NEXT:   INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 196654 /* mem:m */, killed [[MOV64rm]], 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
+  ; CHECK-NEXT:   INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 262190 /* mem:m */, killed [[MOV64rm]], 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
   ; CHECK-NEXT:   JMP_1 %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2.end:
@@ -87,7 +87,7 @@
 $rdi = COPY killed %0
 CALL64pcrel32 target-flags(x86-plt) @foo, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp
 ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
-INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 196654 /* mem:m */, %1, 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
+INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 262190 /* mem:m */, %1, 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
 JMP_1 %bb.2
 
   bb.2.end:
Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
+
+define i32 @m_offset_neg_2049(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2049:
+; LA32:   # %bb.0:
+; LA32-NEXT:lu12i.w $a1, -1
+; LA32-NEXT:ori $a1, $a1, 2047
+; LA32-NEXT:add.w $a0, $a0, $a1
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2049:
+; LA64:   # %bb.0:
+; LA64-NEXT:lu12i.w $a1, -1
+; LA64-NEXT:ori $a1, $a1, 2047
+; LA64-NEXT:add.d $a0, $a0, $a1
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2049
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2048:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -2048
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2048:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -2048
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2048
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_1:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_1:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -1
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:  

[PATCH] D134638: [Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D134638#3822926 , @MaskRay wrote:

> `Constraint_k` somehow broke AArch64 and X86 inlineasm. Please run at least 
> `check-llvm check-clang` for generic changes which may have farreaching 
> effects to other targets.

Sorry for that. I have fix it. The fail is casued by a hard coded INLINEASM 
SDNode flag. I have updated it. Thanks.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D134638/new/

https://reviews.llvm.org/D134638

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[PATCH] D134638: [Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 463847.
SixWeining added a comment.
Herald added subscribers: kosarev, kerbowa, jvesely.

update CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll and 
CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134638/new/

https://reviews.llvm.org/D134638

Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  llvm/include/llvm/IR/InlineAsm.h
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZB.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-k.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
  llvm/test/CodeGen/X86/callbr-asm-kill.mir

Index: llvm/test/CodeGen/X86/callbr-asm-kill.mir
===
--- llvm/test/CodeGen/X86/callbr-asm-kill.mir
+++ llvm/test/CodeGen/X86/callbr-asm-kill.mir
@@ -67,7 +67,7 @@
   ; CHECK-NEXT:   CALL64pcrel32 target-flags(x86-plt) @foo, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp
   ; CHECK-NEXT:   ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
   ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gr64 = COPY [[MOV64rm]]
-  ; CHECK-NEXT:   INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 196654 /* mem:m */, killed [[MOV64rm]], 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
+  ; CHECK-NEXT:   INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 262190 /* mem:m */, killed [[MOV64rm]], 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
   ; CHECK-NEXT:   JMP_1 %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2.end:
@@ -87,7 +87,7 @@
 $rdi = COPY killed %0
 CALL64pcrel32 target-flags(x86-plt) @foo, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp
 ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
-INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 196654 /* mem:m */, %1, 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
+INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 262190 /* mem:m */, %1, 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
 JMP_1 %bb.2
 
   bb.2.end:
Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
+
+define i32 @m_offset_neg_2049(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2049:
+; LA32:   # %bb.0:
+; LA32-NEXT:lu12i.w $a1, -1
+; LA32-NEXT:ori $a1, $a1, 2047
+; LA32-NEXT:add.w $a0, $a0, $a1
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2049:
+; LA64:   # %bb.0:
+; LA64-NEXT:lu12i.w $a1, -1
+; LA64-NEXT:ori $a1, $a1, 2047
+; LA64-NEXT:add.d $a0, $a0, $a1
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2049
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2048:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -2048
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2048:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -2048
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2048
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_1(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_1:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -1
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_1:
+; L

[PATCH] D134638: [Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D134638#3823379 , @xen0n wrote:

> The previous test results (with some of my WIP patches but unrelated to this) 
> before the fix:
>
>   Failed Tests (6):
> LLVM :: CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
> LLVM :: CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
> LLVM :: CodeGen/Generic/vector.ll
> LLVM :: CodeGen/PowerPC/2007-11-19-VectorSplitting.ll
> LLVM :: CodeGen/X86/callbr-asm-kill.mir
> LLVM :: DebugInfo/Generic/missing-abstract-variable.ll
>
> Sure enough it was caught by my native build with all targets enabled, anyway 
> it's important to at least enable the "big" targets such as X86 and AArch64 
> when configuring the local dev env. ;-)

Thanks for the tip. Just now I enabled all official targets and LoongArch and 
find 2 more fail tests (for same reason) for AArch64 and AMDGPU. I have fixed 
them and updated the patch.

Sorry again...


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[PATCH] D134638: [Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

A polite ping...


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[PATCH] D135526: [clang][LoongArch] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for LoongArch

[Lu Weining via Phabricator via cfe-commits]

SixWeining accepted this revision.
SixWeining added inline comments.



Comment at: clang/test/CodeGen/LoongArch/atomics.c:2
+// RUN: %clang_cc1 -triple loongarch32 -O1 -emit-llvm %s -o - \
+// RUN:   | FileCheck %s -check-prefix=LA32
+// RUN: %clang_cc1 -triple loongarch64 -O1 -emit-llvm %s -o - \

Nit: --



Comment at: clang/test/CodeGen/LoongArch/atomics.c:4
+// RUN: %clang_cc1 -triple loongarch64 -O1 -emit-llvm %s -o - \
+// RUN:   | FileCheck %s -check-prefix=LA64
+

ditto


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[PATCH] D135526: [clang][LoongArch] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for LoongArch

[Lu Weining via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6547565e7bdc: [clang][LoongArch] Set MaxAtomicInlineWidth 
and MaxAtomicPromoteWidth for… (authored by wangleiat, committed by SixWeining).

Repository:
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Files:
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/CodeGen/LoongArch/atomics.c


Index: clang/test/CodeGen/LoongArch/atomics.c
===
--- /dev/null
+++ clang/test/CodeGen/LoongArch/atomics.c
@@ -0,0 +1,45 @@
+// RUN: %clang_cc1 -triple loongarch32 -O1 -emit-llvm %s -o - \
+// RUN:   | FileCheck %s --check-prefix=LA32
+// RUN: %clang_cc1 -triple loongarch64 -O1 -emit-llvm %s -o - \
+// RUN:   | FileCheck %s --check-prefix=LA64
+
+/// This test demonstrates that MaxAtomicInlineWidth is set appropriately.
+
+#include 
+#include 
+
+void test_i8_atomics(_Atomic(int8_t) * a, int8_t b) {
+  // LA32: load atomic i8, ptr %a seq_cst, align 1
+  // LA32: store atomic i8 %b, ptr %a seq_cst, align 1
+  // LA32: atomicrmw add ptr %a, i8 %b seq_cst
+  // LA64: load atomic i8, ptr %a seq_cst, align 1
+  // LA64: store atomic i8 %b, ptr %a seq_cst, align 1
+  // LA64: atomicrmw add ptr %a, i8 %b seq_cst
+  __c11_atomic_load(a, memory_order_seq_cst);
+  __c11_atomic_store(a, b, memory_order_seq_cst);
+  __c11_atomic_fetch_add(a, b, memory_order_seq_cst);
+}
+
+void test_i32_atomics(_Atomic(int32_t) * a, int32_t b) {
+  // LA32: load atomic i32, ptr %a seq_cst, align 4
+  // LA32: store atomic i32 %b, ptr %a seq_cst, align 4
+  // LA32: atomicrmw add ptr %a, i32 %b seq_cst
+  // LA64: load atomic i32, ptr %a seq_cst, align 4
+  // LA64: store atomic i32 %b, ptr %a seq_cst, align 4
+  // LA64: atomicrmw add ptr %a, i32 %b seq_cst
+  __c11_atomic_load(a, memory_order_seq_cst);
+  __c11_atomic_store(a, b, memory_order_seq_cst);
+  __c11_atomic_fetch_add(a, b, memory_order_seq_cst);
+}
+
+void test_i64_atomics(_Atomic(int64_t) * a, int64_t b) {
+  // LA32: call i64 @__atomic_load_8
+  // LA32: call void @__atomic_store_8
+  // LA32: call i64 @__atomic_fetch_add_8
+  // LA64: load atomic i64, ptr %a seq_cst, align 8
+  // LA64: store atomic i64 %b, ptr %a seq_cst, align 8
+  // LA64: atomicrmw add ptr %a, i64 %b seq_cst
+  __c11_atomic_load(a, memory_order_seq_cst);
+  __c11_atomic_store(a, b, memory_order_seq_cst);
+  __c11_atomic_fetch_add(a, b, memory_order_seq_cst);
+}
Index: clang/lib/Basic/Targets/LoongArch.h
===
--- clang/lib/Basic/Targets/LoongArch.h
+++ clang/lib/Basic/Targets/LoongArch.h
@@ -79,6 +79,9 @@
 }
 return false;
   }
+  void setMaxAtomicWidth() override {
+MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
+  }
 };
 
 class LLVM_LIBRARY_VISIBILITY LoongArch64TargetInfo
@@ -100,6 +103,9 @@
 }
 return false;
   }
+  void setMaxAtomicWidth() override {
+MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+  }
 };
 } // end namespace targets
 } // end namespace clang


Index: clang/test/CodeGen/LoongArch/atomics.c
===
--- /dev/null
+++ clang/test/CodeGen/LoongArch/atomics.c
@@ -0,0 +1,45 @@
+// RUN: %clang_cc1 -triple loongarch32 -O1 -emit-llvm %s -o - \
+// RUN:   | FileCheck %s --check-prefix=LA32
+// RUN: %clang_cc1 -triple loongarch64 -O1 -emit-llvm %s -o - \
+// RUN:   | FileCheck %s --check-prefix=LA64
+
+/// This test demonstrates that MaxAtomicInlineWidth is set appropriately.
+
+#include 
+#include 
+
+void test_i8_atomics(_Atomic(int8_t) * a, int8_t b) {
+  // LA32: load atomic i8, ptr %a seq_cst, align 1
+  // LA32: store atomic i8 %b, ptr %a seq_cst, align 1
+  // LA32: atomicrmw add ptr %a, i8 %b seq_cst
+  // LA64: load atomic i8, ptr %a seq_cst, align 1
+  // LA64: store atomic i8 %b, ptr %a seq_cst, align 1
+  // LA64: atomicrmw add ptr %a, i8 %b seq_cst
+  __c11_atomic_load(a, memory_order_seq_cst);
+  __c11_atomic_store(a, b, memory_order_seq_cst);
+  __c11_atomic_fetch_add(a, b, memory_order_seq_cst);
+}
+
+void test_i32_atomics(_Atomic(int32_t) * a, int32_t b) {
+  // LA32: load atomic i32, ptr %a seq_cst, align 4
+  // LA32: store atomic i32 %b, ptr %a seq_cst, align 4
+  // LA32: atomicrmw add ptr %a, i32 %b seq_cst
+  // LA64: load atomic i32, ptr %a seq_cst, align 4
+  // LA64: store atomic i32 %b, ptr %a seq_cst, align 4
+  // LA64: atomicrmw add ptr %a, i32 %b seq_cst
+  __c11_atomic_load(a, memory_order_seq_cst);
+  __c11_atomic_store(a, b, memory_order_seq_cst);
+  __c11_atomic_fetch_add(a, b, memory_order_seq_cst);
+}
+
+void test_i64_atomics(_Atomic(int64_t) * a, int64_t b) {
+  // LA32: call i64 @__atomic_load_8
+  // LA32: call void @__atomic_store_8
+  // LA32: call i64 @__atomic_fetch_add_8
+  // LA64: load atomic i64, ptr %a seq_cst, align 8

[PATCH] D135526: [clang][LoongArch] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for LoongArch

[Lu Weining via Phabricator via cfe-commits]

SixWeining reopened this revision.
SixWeining added a comment.
This revision is now accepted and ready to land.

This breaks test: Preprocessor/init-loongarch.c


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[PATCH] D134638: [Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC

[Lu Weining via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG42b70793a1df: Reland "[Clang][LoongArch] Add inline asm 
support for constraints k/m/ZB/ZC" (authored by SixWeining).

Changed prior to commit:
  https://reviews.llvm.org/D134638?vs=463847&id=466778#toc

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/CodeGen/LoongArch/inline-asm-constraints.c
  llvm/include/llvm/IR/InlineAsm.h
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
  llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZB.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-ZC.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-k.ll
  llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
  llvm/test/CodeGen/X86/callbr-asm-kill.mir

Index: llvm/test/CodeGen/X86/callbr-asm-kill.mir
===
--- llvm/test/CodeGen/X86/callbr-asm-kill.mir
+++ llvm/test/CodeGen/X86/callbr-asm-kill.mir
@@ -67,7 +67,7 @@
   ; CHECK-NEXT:   CALL64pcrel32 target-flags(x86-plt) @foo, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp
   ; CHECK-NEXT:   ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
   ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gr64 = COPY [[MOV64rm]]
-  ; CHECK-NEXT:   INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 196654 /* mem:m */, killed [[MOV64rm]], 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
+  ; CHECK-NEXT:   INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 262190 /* mem:m */, killed [[MOV64rm]], 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
   ; CHECK-NEXT:   JMP_1 %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2.end:
@@ -87,7 +87,7 @@
 $rdi = COPY killed %0
 CALL64pcrel32 target-flags(x86-plt) @foo, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp
 ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
-INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 196654 /* mem:m */, %1, 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
+INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 262190 /* mem:m */, %1, 1, $noreg, 0, $noreg, 13 /* imm */, blockaddress(@test1, %ir-block.loop)
 JMP_1 %bb.2
 
   bb.2.end:
Index: llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/inline-asm-constraint-m.ll
@@ -0,0 +1,145 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
+
+define i32 @m_offset_neg_2049(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2049:
+; LA32:   # %bb.0:
+; LA32-NEXT:lu12i.w $a1, -1
+; LA32-NEXT:ori $a1, $a1, 2047
+; LA32-NEXT:add.w $a0, $a0, $a1
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, 0
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2049:
+; LA64:   # %bb.0:
+; LA64-NEXT:lu12i.w $a1, -1
+; LA64-NEXT:ori $a1, $a1, 2047
+; LA64-NEXT:add.d $a0, $a0, $a1
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, 0
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2049
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_2048(ptr %p) nounwind {
+; LA32-LABEL: m_offset_neg_2048:
+; LA32:   # %bb.0:
+; LA32-NEXT:#APP
+; LA32-NEXT:ld.w $a0, $a0, -2048
+; LA32-NEXT:#NO_APP
+; LA32-NEXT:ret
+;
+; LA64-LABEL: m_offset_neg_2048:
+; LA64:   # %bb.0:
+; LA64-NEXT:#APP
+; LA64-NEXT:ld.w $a0, $a0, -2048
+; LA64-NEXT:#NO_APP
+; LA64-NEXT:ret
+  %1 = getelementptr inbounds i8, ptr %p, i32 -2048
+  %2 = call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
+define i32 @m_offset_neg_1(ptr %p) nounwind {
+; LA32-LABE

[PATCH] D135526: [clang][LoongArch] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for LoongArch

[Lu Weining via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdefe7c07f0db: Reland "[clang][LoongArch] Set 
MaxAtomicInlineWidth and MaxAtomicPromoteWidth… (authored by wangleiat, 
committed by SixWeining).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135526/new/

https://reviews.llvm.org/D135526

Files:
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/CodeGen/LoongArch/atomics.c
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- clang/test/Preprocessor/init-loongarch.c
+++ clang/test/Preprocessor/init-loongarch.c
@@ -30,16 +30,16 @@
 // LA32: #define __CHAR16_TYPE__ unsigned short
 // LA32: #define __CHAR32_TYPE__ unsigned int
 // LA32: #define __CHAR_BIT__ 8
-// LA32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 1
-// LA32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 1
-// LA32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 1
-// LA32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 1
-// LA32: #define __CLANG_ATOMIC_INT_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 2
+// LA32: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 2
+// LA32: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 2
+// LA32: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 2
+// LA32: #define __CLANG_ATOMIC_INT_LOCK_FREE 2
 // LA32: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1
-// LA32: #define __CLANG_ATOMIC_LONG_LOCK_FREE 1
-// LA32: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 1
-// LA32: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 1
-// LA32: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 1
+// LA32: #define __CLANG_ATOMIC_LONG_LOCK_FREE 2
+// LA32: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 2
+// LA32: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 2
+// LA32: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 2
 // LA32: #define __DBL_DECIMAL_DIG__ 17
 // LA32: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
 // LA32: #define __DBL_DIG__ 15
@@ -70,17 +70,17 @@
 // LA32: #define __FLT_MIN_EXP__ (-125)
 // LA32: #define __FLT_MIN__ 1.17549435e-38F
 // LA32: #define __FLT_RADIX__ 2
-// LA32: #define __GCC_ATOMIC_BOOL_LOCK_FREE 1
-// LA32: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 1
-// LA32: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 1
-// LA32: #define __GCC_ATOMIC_CHAR_LOCK_FREE 1
-// LA32: #define __GCC_ATOMIC_INT_LOCK_FREE 1
+// LA32: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// LA32: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// LA32: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// LA32: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// LA32: #define __GCC_ATOMIC_INT_LOCK_FREE 2
 // LA32: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
-// LA32: #define __GCC_ATOMIC_LONG_LOCK_FREE 1
-// LA32: #define __GCC_ATOMIC_POINTER_LOCK_FREE 1
-// LA32: #define __GCC_ATOMIC_SHORT_LOCK_FREE 1
+// LA32: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// LA32: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// LA32: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
 // LA32: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
-// LA32: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 1
+// LA32: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // LA32: #define __ILP32__ 1
 // LA32: #define __INT16_C_SUFFIX__
 // LA32: #define __INT16_FMTd__ "hd"
@@ -342,16 +342,16 @@
 // LA64: #define __CHAR16_TYPE__ unsigned short
 // LA64: #define __CHAR32_TYPE__ unsigned int
 // LA64: #define __CHAR_BIT__ 8
-// LA64: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 1
-// LA64: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 1
-// LA64: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 1
-// LA64: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 1
-// LA64: #define __CLANG_ATOMIC_INT_LOCK_FREE 1
-// LA64: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1
-// LA64: #define __CLANG_ATOMIC_LONG_LOCK_FREE 1
-// LA64: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 1
-// LA64: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 1
-// LA64: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 1
+// LA64: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 2
+// LA64: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 2
+// LA64: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 2
+// LA64: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 2
+// LA64: #define __CLANG_ATOMIC_INT_LOCK_FREE 2
+// LA64: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 2
+// LA64: #define __CLANG_ATOMIC_LONG_LOCK_FREE 2
+// LA64: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 2
+// LA64: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 2
+// LA64: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 2
 // LA64: #define __DBL_DECIMAL_DIG__ 17
 // LA64: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324
 // LA64: #define __DBL_DIG__ 15
@@ -382,17 +382,17 @@
 // LA64: #define __FLT_MIN_EXP__ (-125)
 // LA64: #define __FLT_MIN__ 1.17549435e-38F
 // LA64: #define __FLT_RADIX__ 2
-// LA64: #define __GCC_ATOMIC_BOOL_LOCK_FREE 1
-// LA64: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 1
-// LA64: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 1
-// LA64: #define __GCC_ATOMIC_CHAR_LOCK_FREE 1
-// LA64: #define __GCC_ATOMIC_INT_LOCK_FREE 1
-// LA64: #define 

[PATCH] D139915: [Clang][LoongArch] Add intrinsic for asrtle, asrtgt, lddir, ldpte and cpucfg

[Lu Weining via Phabricator via cfe-commits]

SixWeining accepted this revision.
SixWeining added a comment.
This revision is now accepted and ready to land.

LGTM except a small nit.




Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.h:91
   IOCSRWR_D,
+
+  CPUCFG,

Better to leave some comment like line 82?


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[PATCH] D139987: [Clang][LoongArch] Add intrinsic for rdtime_d, rdtimeh_w and rdtimel_w

[Lu Weining via Phabricator via cfe-commits]

SixWeining added inline comments.



Comment at: clang/lib/Headers/larchintrin.h:17-20
+typedef struct drdtime {
+  unsigned long dvalue;
+  unsigned long dtimeid;
+} __drdtime_t;

Should be moved into the belowing `#if __loongarch_grlen == 64`.


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[PATCH] D139987: [Clang][LoongArch] Add intrinsic for rdtime_d, rdtimeh_w and rdtimel_w

[Lu Weining via Phabricator via cfe-commits]

SixWeining accepted this revision.
SixWeining added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D140690: [compiler-rt][dfsan] Enable loongarch64 and add test support

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D140690#4017693 , @browneee wrote:

> Who will use DFSan on loongarch64?
>
> Who will maintain DFSan on loongarch64?
>
> Is there a loongarch64 buildbot?

Hi @browneee, I'm the co-author of this patch. Thanks for your comments.

> Who will use DFSan on loongarch64?

Currently nobody uses it as loongarch is a pretty new arch which is expected to 
graduate from experimental before llvm 16 release. (But I think there may be 
potential users of DFSan in future.) The motivation of this change is to make 
loongarch64 support as more compiler-rt components as possible. We notice that 
DFSan is a work in progress 
, currently 
under development for x86_64 Linux. So maybe we can defer the change until 
DFSan development is finished and there is a use case on loongarch64?

> Who will maintain DFSan on loongarch64?

Loongson (https://www.loongson.cn/EN) can maintain it.

> Is there a loongarch64 buildbot?

Yes, there is one: https://lab.llvm.org/staging/#/builders/236.


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[PATCH] D140727: [XRay] Add initial support for loongarch64

[Lu Weining via Phabricator via cfe-commits]

SixWeining created this revision.
SixWeining added reviewers: MaskRay, xen0n, xry111.
Herald added subscribers: Enna1, StephenFan, hiraditya, dberris.
Herald added a project: All.
SixWeining requested review of this revision.
Herald added projects: clang, Sanitizers, LLVM.
Herald added subscribers: llvm-commits, Sanitizers, cfe-commits.

Only support patching FunctionEntry/FunctionExit/FunctionTailExit for now.

Currently version 0 (which uses absolute address) is used because
LoongArch doesn't have a single 64bit PC-relative reloction type like
32bit version R_LARCH_32_PCREL.
Perhaps we can use a pair of relocations (R_LARCH_ADD64/R_LARCH_SUB64)
as replacement but that needs some changes to the backend.

Depends on D140725 


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Files:
  clang/lib/Driver/XRayArgs.cpp
  compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
  compiler-rt/lib/xray/CMakeLists.txt
  compiler-rt/lib/xray/xray_interface.cpp
  compiler-rt/lib/xray/xray_loongarch64.cpp
  compiler-rt/lib/xray/xray_trampoline_loongarch64.S
  compiler-rt/lib/xray/xray_tsc.h
  compiler-rt/test/xray/TestCases/Posix/always-never-instrument.cpp
  compiler-rt/test/xray/TestCases/Posix/arg1-arg0-logging.cpp
  compiler-rt/test/xray/TestCases/Posix/arg1-logger.cpp
  compiler-rt/test/xray/TestCases/Posix/arg1-logging-implicit-this.cpp
  compiler-rt/test/xray/TestCases/Posix/basic-filtering.cpp
  compiler-rt/test/xray/TestCases/Posix/c-test.cpp
  compiler-rt/test/xray/TestCases/Posix/clang-no-xray-instrument.cpp
  compiler-rt/test/xray/TestCases/Posix/fdr-mode-inmemory.cpp
  compiler-rt/test/xray/TestCases/Posix/fdr-mode-multiple.cpp
  compiler-rt/test/xray/TestCases/Posix/fdr-single-thread.cpp
  compiler-rt/test/xray/TestCases/Posix/fdr-thread-order.cpp
  compiler-rt/test/xray/TestCases/Posix/profiling-multi-threaded.cpp
  compiler-rt/test/xray/TestCases/Posix/profiling-single-threaded.cpp
  compiler-rt/test/xray/TestCases/Posix/quiet-start.cpp
  llvm/lib/CodeGen/XRayInstrumentation.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
  llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
  llvm/lib/Target/LoongArch/LoongArchSubtarget.h
  llvm/lib/XRay/InstrumentationMap.cpp
  llvm/test/CodeGen/LoongArch/xray-attribute-instrumentation.ll

Index: llvm/test/CodeGen/LoongArch/xray-attribute-instrumentation.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/xray-attribute-instrumentation.ll
@@ -0,0 +1,71 @@
+; RUN: llc --mtriple=loongarch64 %s -o - | FileCheck %s
+; RUN: llc --mtriple=loongarch64 -filetype=obj %s -o %t
+; RUN: llvm-readobj -r %t | FileCheck %s --check-prefix=RELOC
+
+define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always" {
+; CHECK-LABEL: foo:
+; CHECK-LABEL: .Lfunc_begin0:
+; CHECK:   .p2align 2
+; CHECK-LABEL: .Lxray_sled_begin0:
+; CHECK-NEXT:  b .Lxray_sled_end0
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-LABEL: .Lxray_sled_end0:
+  ret i32 0
+; CHECK-LABEL: .Lxray_sled_begin1:
+; CHECK-NEXT:  b .Lxray_sled_end1
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT: .Lxray_sled_end1:
+; CHECK-NEXT:  ret
+; CHECK-NEXT: .Lfunc_end0:
+}
+
+; CHECK-LABEL: .section xray_instr_map
+; CHECK-NEXT: .Lxray_sleds_start0:
+; CHECK-NEXT: .dword .Lxray_sled_begin0
+; CHECK-NEXT: .dword foo
+; CHECK-NEXT: .byte 0x00
+; CHECK-NEXT: .byte 0x01
+; CHECK-NEXT: .byte 0x00
+; CHECK-NEXT: .space 13
+; CHECK-NEXT: .dword .Lxray_sled_begin1
+; CHECK-NEXT: .dword foo
+; CHECK-NEXT: .byte 0x01
+; CHECK-NEXT: .byte 0x01
+; CHECK-NEXT: .byte 0x00
+; CHECK-NEXT: .space 13
+; CHECK-NEXT: .Lxray_sleds_end0:
+
+; CHECK-LABEL:  .section xray_fn_idx
+; CHECK:  .dword .Lxray_sleds_start0
+; CHECK-NEXT: .dword .Lxray_sleds_end0
+
+; RELOC:  Section ([[#]]) .relaxray_instr_map {
+; RELOC-NEXT:   0x0 R_LARCH_64 .text 0x0
+; RELOC-NEXT:   0x8 R_LARCH_64 foo 0x0
+; RELOC-NEXT:   0x20 R_LARCH_64 .text 0x34
+; RELOC-NEXT:   0x28 R_LARCH_64 foo 0x0
+; RELOC-NEXT: }
+; RELOC-NEXT: Section ([[#]]) .relaxray_fn_idx {
+; RELOC-NEXT:   0x0 R_LARCH_64 xray_instr_map 0x0
+; RELOC-NEXT:   0x8 R_LARCH_64 xray_instr_map 0x40
+; RELOC-NEXT: }
Index: llvm/lib/XRay/InstrumentationMap.cpp
===
--- llvm/lib/XRay/InstrumentationMap.cpp
+++ llvm/lib/XRay/InstrumentationMap.cpp
@@ -60,6 +60,7 @@
   // Find the section named "xray_instr_map".
   if ((!ObjFile.getBinary()->isELF() && !O

[PATCH] D140727: [XRay] Add initial support for loongarch64

[Lu Weining via Phabricator via cfe-commits]

SixWeining planned changes to this revision.
SixWeining added a comment.

D140725  is abandoned. Let me defer this 
change until we support 64bit PC-relative relocation for `SymA - SymB`.


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[PATCH] D140527: [LoongArch] Add intrinsics for CACOP instruction

[Lu Weining via Phabricator via cfe-commits]

SixWeining accepted this revision.
SixWeining added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D141070: [LoongArch] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros

[Lu Weining via Phabricator via cfe-commits]

SixWeining accepted this revision.
SixWeining added a comment.

This matches LoongArch gcc's  behavior.  So LGTM. Thanks.


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[PATCH] D136146: [Clang][LoongArch] Handle -march/-m{single,double,soft}-float/-mfpu options

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

Sorry for the late reply.

Should we choose not to implement the `-mfpu=` option which is not mandatory?




Comment at: clang/lib/Driver/ToolChains/Arch/LoongArch.cpp:31
+ options::OPT_msingle_float,
+ options::OPT_msoft_float)) {
+if (A->getOption().matches(options::OPT_mdouble_float))

MaskRay wrote:
> This is strange. Other architectures using -msoft-float makes it orthogonal 
> to -mdouble-float...
> 
> Instead of having -mdouble-float/-msingle-float, can you just use 
> -mfloat-abi=?
Sorry for the late reply.

Similar to @xry111's explanation below, `-m{double,single,soft}-float` are 
different from `-mfpu={64,32,0,none}`.

`-m{double,single,soft}-float` affect both codegen-ed instructions and the ABI 
while `-mfpu={64,32,0,none}` only affect the codegen-ed instructions.

That is to say:
* `-mdouble-float` implies `-mfpu=64` and `-mabi={lp64d,ilp32d}`;
* `-msingle-float` implies `-mfpu=32` and `-mabi={lp64f,ilp32f}`;
* `-msoft-float` implies `-mfpu={0,none}` and `-mabi={lp64s,ilp32s}`.

The `-mfpu={64,32,0,none}` clang option is like the `--mattr=+{d,f}` llc 
option. And the `-mabi=` clang option is like the `--target-abi=` llc option.

But I have to admit this introduce some complexity to clang implementation 
because we have to take care of the order these options appear on the command 
line.  The doc says:
> As a general rule, the effect of all LoongArch-specific compiler options that 
> are given for one compiler invocation should be as if they are processed in 
> the order they appear on the command line. The only exception to this rule is 
> -m*-float: their configuration of floating-point instruction set and calling 
> convention will not be changed by subsequent options other than -m*-float.




Comment at: clang/lib/Driver/ToolChains/Arch/LoongArch.cpp:44
 
+  // Select abi based on -mfpu=xx.
+  if (const Arg *A = Args.getLastArg(options::OPT_mfpu_EQ)) {

xry111 wrote:
> MaskRay wrote:
> > It's better to stick with just one canonical spelling. Is there time to 
> > remove support for one set of options? When `-mfpu=64 -msoft-float` is 
> > specified, is a -Wunused-command-line-argument warning expected?
> According to the doc, the semantics of -mfpu=64 and -mdouble-float are not 
> exactly same.  `-mfpu=64 -mabi=lp64s` will allow the compiler to generate 
> 64-bit floating-point instructions but keep LP64S calling convention.  
> `-mdouble-float -mabi=lp64s` will be same as `-mdouble-float -mabi=lp64d` 
> (with a warning emitted, maybe).
The doc says that the implementation of `-mfpu` is not mandatory. So maybe we 
can choose not to implement it? But I'm not sure whether it has been used by 
any programs.

> -mdouble-float -mabi=lp64s will be same as -mdouble-float -mabi=lp64d (with a 
> warning emitted, maybe).
Yes, I think so. GCC indeed emits a warning. We also should emit one.



Comment at: clang/test/Driver/loongarch-march-error.c:1
+// RUN: not %clang --target=loongarch64 -march=loongarch -fsyntax-only %s 2>&1 
\
+// RUN:   | FileCheck --check-prefix=LOONGARCH %s

MaskRay wrote:
> The more common style is to place `|` in the end. The idea is that even 
> without `\`, after typing the first line in a shell, it will wait for the 
> second line.
OK. But seems both styles are used in the code base. -;)



Comment at: clang/test/Driver/loongarch-march.c:12
+// CC1-LOONGARCH64: "-target-feature" "+64bit"
+// CC1-LOONGARCH64-SAME: {{^}} "-target-feature" "+f"
+// CC1-LOONGARCH64-SAME: {{^}} "-target-feature" "+d"

MaskRay wrote:
> Check target-feature options on one line
OK.



Comment at: llvm/lib/Support/LoongArchTargetParser.cpp:46
+if ((A.Features & F.Kind) == F.Kind && F.Kind != FK_INVALID) {
+  Features.push_back(F.Name);
+}

MaskRay wrote:
> delete braces
OK.


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[PATCH] D137316: [Clang][LoongArch] Implement __builtin_loongarch_crc_w_d_w builtin and add diagnostics

[Lu Weining via Phabricator via cfe-commits]

SixWeining added inline comments.



Comment at: llvm/include/llvm/IR/IntrinsicsLoongArch.td:54
+def int_loongarch_crc_w_d_w : Intrinsic<[llvm_i32_ty],
+[llvm_i64_ty, llvm_i32_ty], []>;
 } // TargetPrefix = "loongarch"

Unnecessary.


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[PATCH] D136906: [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin

[Lu Weining via Phabricator via cfe-commits]

SixWeining added inline comments.



Comment at: llvm/include/llvm/IR/IntrinsicsLoongArch.td:39
+
+def int_loongarch_dbar : Intrinsic<[], [llvm_i32_ty], []>;
 } // TargetPrefix = "loongarch"

Seems this arg is unnecessary because the defalut value is `[]`.


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[PATCH] D136906: [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin

[Lu Weining via Phabricator via cfe-commits]

SixWeining accepted this revision.
SixWeining added a comment.
This revision is now accepted and ready to land.

LGTM but let's wait others.


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[PATCH] D137316: [Clang][LoongArch] Implement __builtin_loongarch_crc_w_d_w builtin and add diagnostics

[Lu Weining via Phabricator via cfe-commits]

SixWeining accepted this revision.
SixWeining added a comment.
This revision is now accepted and ready to land.

LGTM except 2 nits. And let's wait others.




Comment at: clang/lib/Basic/Targets/LoongArch.cpp:174
+const std::vector &FeaturesVec) const {
+
+  if (getTriple().getArch() == llvm::Triple::loongarch64)

Delete blank line.



Comment at: clang/lib/Sema/SemaChecking.cpp:3677
+ CallExpr *TheCall) {
+
+  switch (BuiltinID) {

Delete blank line.


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[PATCH] D136146: [Clang][LoongArch] Handle -march/-m{single,double,soft}-float/-mfpu options

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 473627.
SixWeining added a comment.

Add test for warning: argument unused during compilation. And address other 
comments from @MaskRay.


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Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/loongarch-default-features.c
  clang/test/Driver/loongarch-march-error.c
  clang/test/Driver/loongarch-march.c
  clang/test/Driver/loongarch-mdouble-float.c
  clang/test/Driver/loongarch-mfpu-error.c
  clang/test/Driver/loongarch-mfpu.c
  clang/test/Driver/loongarch-msingle-float.c
  clang/test/Driver/loongarch-msoft-float.c
  llvm/include/llvm/Support/LoongArchTargetParser.def
  llvm/include/llvm/Support/LoongArchTargetParser.h
  llvm/lib/Support/CMakeLists.txt
  llvm/lib/Support/LoongArchTargetParser.cpp

Index: llvm/lib/Support/LoongArchTargetParser.cpp
===
--- /dev/null
+++ llvm/lib/Support/LoongArchTargetParser.cpp
@@ -0,0 +1,49 @@
+//==-- LoongArch64TargetParser - Parser for LoongArch64 features --*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements a target parser to recognise LoongArch hardware features
+// such as CPU/ARCH and extension names.
+//
+//===--===//
+
+#include "llvm/Support/LoongArchTargetParser.h"
+#include "llvm/ADT/StringSwitch.h"
+
+using namespace llvm;
+using namespace llvm::LoongArch;
+
+const FeatureInfo AllFeatures[] = {
+#define LOONGARCH_FEATURE(NAME, KIND) {NAME, KIND},
+#include "llvm/Support/LoongArchTargetParser.def"
+};
+
+const ArchInfo AllArchs[] = {
+#define LOONGARCH_ARCH(NAME, KIND, FEATURES)   \
+  {NAME, LoongArch::ArchKind::KIND, FEATURES},
+#include "llvm/Support/LoongArchTargetParser.def"
+};
+
+LoongArch::ArchKind LoongArch::parseArch(StringRef Arch) {
+  for (const auto A : AllArchs)
+if (A.Name == Arch)
+  return A.Kind;
+
+  return LoongArch::ArchKind::AK_INVALID;
+}
+
+bool LoongArch::getArchFeatures(StringRef Arch,
+std::vector &Features) {
+  for (const auto A : AllArchs)
+if (A.Name == Arch) {
+  for (const auto F : AllFeatures)
+if ((A.Features & F.Kind) == F.Kind && F.Kind != FK_INVALID)
+  Features.push_back(F.Name);
+  return true;
+}
+  return false;
+}
Index: llvm/lib/Support/CMakeLists.txt
===
--- llvm/lib/Support/CMakeLists.txt
+++ llvm/lib/Support/CMakeLists.txt
@@ -187,6 +187,7 @@
   LineIterator.cpp
   Locale.cpp
   LockFileManager.cpp
+  LoongArchTargetParser.cpp
   LowLevelType.cpp
   ManagedStatic.cpp
   MathExtras.cpp
Index: llvm/include/llvm/Support/LoongArchTargetParser.h
===
--- /dev/null
+++ llvm/include/llvm/Support/LoongArchTargetParser.h
@@ -0,0 +1,74 @@
+//==-- LoongArch64TargetParser - Parser for LoongArch64 features --*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements a target parser to recognise LoongArch hardware features
+// such as CPU/ARCH and extension names.
+//
+//===--===//
+
+#ifndef LLVM_SUPPORT_LOONGARCHTARGETPARSER_H
+#define LLVM_SUPPORT_LOONGARCHTARGETPARSER_H
+
+#include "llvm/ADT/Triple.h"
+#include 
+
+namespace llvm {
+class StringRef;
+
+namespace LoongArch {
+
+enum FeatureKind : uint32_t {
+  FK_INVALID = 0,
+  FK_NONE = 1,
+
+  // 64-bit ISA is available.
+  FK_64BIT = 1 << 1,
+
+  // Single-precision floating-point instructions are available.
+  FK_FP32 = 1 << 2,
+
+  // Double-precision floating-point instructions are available.
+  FK_FP64 = 1 << 3,
+
+  // Loongson SIMD Extension is available.
+  FK_LSX = 1 << 4,
+
+  // Loongson Advanced SIMD Extension is available.
+  FK_LASX = 1 << 5,
+
+  // Loongson Binary Translation Extension is available.
+  FK_LBT = 1 << 6,
+
+  // Loongson Virtualization Extension is available.
+  FK_LVZ = 1 << 7,
+};
+
+struct FeatureInfo {
+  StringRef Name;
+  FeatureKind Kind;
+};
+

[PATCH] D136906: [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin

[Lu Weining via Phabricator via cfe-commits]

SixWeining added inline comments.



Comment at: llvm/test/CodeGen/LoongArch/intrinsic-error.ll:10
+
+declare void @llvm.loongarch.dbar(i32)

It's better to add a test that immediate is out of range.


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[PATCH] D136146: [Clang][LoongArch] Handle -march/-m{single,double,soft}-float/-mfpu options

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 474414.
SixWeining added a comment.

Revise the `err_drv_loongarch_invalid_mfpu_EQ` diagnostic info. Add necessary 
braces.


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Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/loongarch-default-features.c
  clang/test/Driver/loongarch-march-error.c
  clang/test/Driver/loongarch-march.c
  clang/test/Driver/loongarch-mdouble-float.c
  clang/test/Driver/loongarch-mfpu-error.c
  clang/test/Driver/loongarch-mfpu.c
  clang/test/Driver/loongarch-msingle-float.c
  clang/test/Driver/loongarch-msoft-float.c
  llvm/include/llvm/Support/LoongArchTargetParser.def
  llvm/include/llvm/Support/LoongArchTargetParser.h
  llvm/lib/Support/CMakeLists.txt
  llvm/lib/Support/LoongArchTargetParser.cpp

Index: llvm/lib/Support/LoongArchTargetParser.cpp
===
--- /dev/null
+++ llvm/lib/Support/LoongArchTargetParser.cpp
@@ -0,0 +1,50 @@
+//==-- LoongArch64TargetParser - Parser for LoongArch64 features --*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements a target parser to recognise LoongArch hardware features
+// such as CPU/ARCH and extension names.
+//
+//===--===//
+
+#include "llvm/Support/LoongArchTargetParser.h"
+#include "llvm/ADT/StringSwitch.h"
+
+using namespace llvm;
+using namespace llvm::LoongArch;
+
+const FeatureInfo AllFeatures[] = {
+#define LOONGARCH_FEATURE(NAME, KIND) {NAME, KIND},
+#include "llvm/Support/LoongArchTargetParser.def"
+};
+
+const ArchInfo AllArchs[] = {
+#define LOONGARCH_ARCH(NAME, KIND, FEATURES)   \
+  {NAME, LoongArch::ArchKind::KIND, FEATURES},
+#include "llvm/Support/LoongArchTargetParser.def"
+};
+
+LoongArch::ArchKind LoongArch::parseArch(StringRef Arch) {
+  for (const auto A : AllArchs)
+if (A.Name == Arch)
+  return A.Kind;
+
+  return LoongArch::ArchKind::AK_INVALID;
+}
+
+bool LoongArch::getArchFeatures(StringRef Arch,
+std::vector &Features) {
+  for (const auto A : AllArchs) {
+if (A.Name == Arch) {
+  for (const auto F : AllFeatures)
+if ((A.Features & F.Kind) == F.Kind && F.Kind != FK_INVALID)
+  Features.push_back(F.Name);
+  return true;
+}
+  }
+  return false;
+}
Index: llvm/lib/Support/CMakeLists.txt
===
--- llvm/lib/Support/CMakeLists.txt
+++ llvm/lib/Support/CMakeLists.txt
@@ -187,6 +187,7 @@
   LineIterator.cpp
   Locale.cpp
   LockFileManager.cpp
+  LoongArchTargetParser.cpp
   LowLevelType.cpp
   ManagedStatic.cpp
   MathExtras.cpp
Index: llvm/include/llvm/Support/LoongArchTargetParser.h
===
--- /dev/null
+++ llvm/include/llvm/Support/LoongArchTargetParser.h
@@ -0,0 +1,74 @@
+//==-- LoongArch64TargetParser - Parser for LoongArch64 features --*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements a target parser to recognise LoongArch hardware features
+// such as CPU/ARCH and extension names.
+//
+//===--===//
+
+#ifndef LLVM_SUPPORT_LOONGARCHTARGETPARSER_H
+#define LLVM_SUPPORT_LOONGARCHTARGETPARSER_H
+
+#include "llvm/ADT/Triple.h"
+#include 
+
+namespace llvm {
+class StringRef;
+
+namespace LoongArch {
+
+enum FeatureKind : uint32_t {
+  FK_INVALID = 0,
+  FK_NONE = 1,
+
+  // 64-bit ISA is available.
+  FK_64BIT = 1 << 1,
+
+  // Single-precision floating-point instructions are available.
+  FK_FP32 = 1 << 2,
+
+  // Double-precision floating-point instructions are available.
+  FK_FP64 = 1 << 3,
+
+  // Loongson SIMD Extension is available.
+  FK_LSX = 1 << 4,
+
+  // Loongson Advanced SIMD Extension is available.
+  FK_LASX = 1 << 5,
+
+  // Loongson Binary Translation Extension is available.
+  FK_LBT = 1 << 6,
+
+  // Loongson Virtualization Extension is available.
+  FK_LVZ = 1 << 7,
+};
+
+struct FeatureInfo {
+  StringRef Name;
+  FeatureKind Kind;
+};
+
+enum c

[PATCH] D136146: [Clang][LoongArch] Handle -march/-m{single,double,soft}-float/-mfpu options

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

This change was pushed yesterday, but it's not the last diff. I will submit a 
follow-up change as soon as possible.


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[PATCH] D137809: [LoongArch] Add immediate operand validity check for __builtin_loongarch_dbar

[Lu Weining via Phabricator via cfe-commits]

SixWeining added inline comments.



Comment at: clang/test/CodeGen/LoongArch/intrinsic-error.c:11
+void dbar() {
+  return __builtin_loongarch_dbar(32768); // expected-error {{argument value 
32768 is outside the valid range [0, 32767]}}
+}

Also check lower bound.


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[PATCH] D138094: [LoongArch] Add intrinsics for ibar, break and syscall

[Lu Weining via Phabricator via cfe-commits]

SixWeining added inline comments.



Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp:603
   case Intrinsic::loongarch_dbar: {
-SDValue Op0 = Op.getOperand(0);
-SDValue Op2 = Op.getOperand(2);
-if (!isa(Op2)) {
-  DAG.getContext()->emitError("argument to '__builtin_loongarch_dbar' must 
"
-  "be a constant integer");
-  return Op.getOperand(0);
-}
+Name = "__builtin_loongarch_dbar";
 unsigned Imm = cast(Op2)->getZExtValue();

This string can be inlined into line 606. Then line 595 can be removed.


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[PATCH] D138094: [LoongArch] Add intrinsics for ibar, break and syscall

[Lu Weining via Phabricator via cfe-commits]

SixWeining accepted this revision.
SixWeining added a comment.
This revision is now accepted and ready to land.

LGTM but let's wait for others.


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[PATCH] D142688: [Clang][Driver] Handle LoongArch multiarch tuples

[Lu Weining via Phabricator via cfe-commits]

SixWeining added inline comments.



Comment at: clang/lib/Driver/ToolChains/Linux.cpp:41
 /// so we provide a rough mapping here.
 std::string Linux::getMultiarchTriple(const Driver &D,
   const llvm::Triple &TargetTriple,

Missing test. Perhaps add some in `clang/test/Driver/linux-ld.c` and 
`clang/test/Driver/linux-header-search.cpp`? Or postpone this change until 
loongarch is upstreamed to Debian?



Comment at: clang/lib/Driver/ToolChains/Linux.cpp:93
+
+if (TargetTriple.isGNUEnvironment()) {
+  Libc = "gnu";

Should only check `{GNU|GNUF32|GNUF64}`?



Comment at: clang/lib/Driver/ToolChains/Linux.cpp:95
+  Libc = "gnu";
+} else if (TargetTriple.isMusl()) {
+  Libc = "musl";

Should only check `Triple::Musl`?


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[PATCH] D139686: [lsan] Add lsan support for loongarch64

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

LGTM. Is there any objection?


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[PATCH] D139686: [lsan] Add lsan support for loongarch64

[Lu Weining via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG3a58e11961d8: [lsan] Add lsan support for loongarch64 
(authored by tangyouling, committed by SixWeining).

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Files:
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/fsanitize.c
  compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
  compiler-rt/lib/lsan/lsan_common.cpp
  compiler-rt/lib/lsan/lsan_common.h
  compiler-rt/test/asan/lit.cfg.py
  compiler-rt/test/lsan/TestCases/swapcontext.cpp
  compiler-rt/test/lsan/TestCases/use_registers.cpp
  compiler-rt/test/lsan/lit.common.cfg.py

Index: compiler-rt/test/lsan/lit.common.cfg.py
===
--- compiler-rt/test/lsan/lit.common.cfg.py
+++ compiler-rt/test/lsan/lit.common.cfg.py
@@ -74,9 +74,9 @@
 config.substitutions.append( ("%clangxx_lsan ", build_invocation(clang_lsan_cxxflags)) )
 
 # LeakSanitizer tests are currently supported on
-# Android{aarch64, x86, x86_64}, x86-64 Linux, PowerPC64 Linux, arm Linux, mips64 Linux, s390x Linux and x86_64 Darwin.
+# Android{aarch64, x86, x86_64}, x86-64 Linux, PowerPC64 Linux, arm Linux, mips64 Linux, s390x Linux, loongarch64 Linux and x86_64 Darwin.
 supported_android = config.android and config.target_arch in ['x86_64', 'i386', 'aarch64'] and 'android-thread-properties-api' in config.available_features
-supported_linux = (not config.android) and config.host_os == 'Linux' and config.host_arch in ['aarch64', 'x86_64', 'ppc64', 'ppc64le', 'mips64', 'riscv64', 'arm', 'armhf', 'armv7l', 's390x']
+supported_linux = (not config.android) and config.host_os == 'Linux' and config.host_arch in ['aarch64', 'x86_64', 'ppc64', 'ppc64le', 'mips64', 'riscv64', 'arm', 'armhf', 'armv7l', 's390x', 'loongarch64']
 supported_darwin = config.host_os == 'Darwin' and config.target_arch in ['x86_64']
 supported_netbsd = config.host_os == 'NetBSD' and config.target_arch in ['x86_64', 'i386']
 if not (supported_android or supported_linux or supported_darwin or supported_netbsd):
Index: compiler-rt/test/lsan/TestCases/use_registers.cpp
===
--- compiler-rt/test/lsan/TestCases/use_registers.cpp
+++ compiler-rt/test/lsan/TestCases/use_registers.cpp
@@ -43,6 +43,8 @@
   "mov x14, %0"
   :
   : "r"(p));
+#elif defined(__loongarch_lp64)
+  asm("move $s8, %0" : : "r"(p));
 #elif defined(__powerpc__)
   asm("mr 30, %0"
   :
Index: compiler-rt/test/lsan/TestCases/swapcontext.cpp
===
--- compiler-rt/test/lsan/TestCases/swapcontext.cpp
+++ compiler-rt/test/lsan/TestCases/swapcontext.cpp
@@ -5,7 +5,7 @@
 // RUN: %env_lsan_opts= %run %t 2>&1
 // RUN: %env_lsan_opts= not %run %t foo 2>&1 | FileCheck %s
 // Missing 'getcontext' and 'makecontext' on Android.
-// UNSUPPORTED: target={{(arm|aarch64|powerpc64).*}},android
+// UNSUPPORTED: target={{(arm|aarch64|loongarch64|powerpc64).*}},android
 
 #include "sanitizer_common/sanitizer_ucontext.h"
 #include 
Index: compiler-rt/test/asan/lit.cfg.py
===
--- compiler-rt/test/asan/lit.cfg.py
+++ compiler-rt/test/asan/lit.cfg.py
@@ -202,7 +202,7 @@
 
 # Turn on leak detection on 64-bit Linux.
 leak_detection_android = config.android and 'android-thread-properties-api' in config.available_features and (config.target_arch in ['x86_64', 'i386', 'i686', 'aarch64'])
-leak_detection_linux = (config.host_os == 'Linux') and (not config.android) and (config.target_arch in ['x86_64', 'i386', 'riscv64'])
+leak_detection_linux = (config.host_os == 'Linux') and (not config.android) and (config.target_arch in ['x86_64', 'i386', 'riscv64', 'loongarch64'])
 leak_detection_mac = (config.host_os == 'Darwin') and (config.apple_platform == 'osx')
 leak_detection_netbsd = (config.host_os == 'NetBSD') and (config.target_arch in ['x86_64', 'i386'])
 if leak_detection_android or leak_detection_linux or leak_detection_mac or leak_detection_netbsd:
Index: compiler-rt/lib/lsan/lsan_common.h
===
--- compiler-rt/lib/lsan/lsan_common.h
+++ compiler-rt/lib/lsan/lsan_common.h
@@ -43,6 +43,8 @@
 #  define CAN_SANITIZE_LEAKS 1
 #elif defined(__arm__) && SANITIZER_LINUX
 #  define CAN_SANITIZE_LEAKS 1
+#elif SANITIZER_LOONGARCH64 && SANITIZER_LINUX
+#  define CAN_SANITIZE_LEAKS 1
 #elif SANITIZER_RISCV64 && SANITIZER_LINUX
 #  define CAN_SANITIZE_LEAKS 1
 #elif SANITIZER_NETBSD || SANITIZER_FUCHSIA
Index: compiler-rt/lib/lsan/lsan_common.cpp
===
--- compiler-rt/lib/lsan/lsan_common.cpp
+++ compiler-rt/lib/lsan/lsan_common.cpp
@@ -277,6 +277,9 @@
 #  elif defined(__aarch64__)
   // Accept up to 48 bit VMA.
   return ((p >> 48) == 

[PATCH] D141750: [docs] Add llvm & clang release notes for LoongArch

[Lu Weining via Phabricator via cfe-commits]

SixWeining created this revision.
SixWeining added reviewers: rengolin, MaskRay, tstellar, xen0n, xry111, 
wangleiat, lrzlin, tangyouling, lh03061238.
Herald added subscribers: yaneury, supersymetrie, Chia-hungDuan, cryptoad.
Herald added a project: All.
SixWeining requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

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Files:
  clang/docs/ReleaseNotes.rst
  llvm/docs/ReleaseNotes.rst


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -47,6 +47,8 @@
is not a constant in coroutines. This decision may cause unnecessary
performance regressions and we plan to fix it in later versions.
 
+*  The LoongArch target is promoted to "official" (see below for more details).
+
 * ...
 
 Update on required toolchains to build LLVM
@@ -154,6 +156,19 @@
 
 * ...
 
+Changes to the LoongArch Backend
+---
+
+* The LoongArch target is no longer "experimental"! It's now built by default,
+  rather than needing to be enabled with 
``LLVM_EXPERIMENTAL_TARGETS_TO_BUILD``.
+
+* The backend has full codegen support for the base (both integer and
+  floating-point) instruction set and it conforms to psABI v2. Testing has been
+  performed with Linux, including native compilation of a large corpus of Linux
+  applications.
+
+* Support GHC calling convention.
+
 Changes to the MIPS Backend
 ---
 
@@ -279,9 +294,13 @@
 Changes to LLDB
 -
 
+* Initial support for debugging Linux LoongArch 64-bit binaries.
+
 Changes to Sanitizers
 -
 
+* Many Sanitizers (asan, fuzzer, lsan, safestack, scudo, tsan, ubsan) have
+  support for Linux LoongArch 64-bit variant. Some of them may be rudimentary.
 
 Other Changes
 -
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -798,6 +798,19 @@
 - Clang now supports CUDA SDK up to 11.8
 - Added support for targeting sm_{87,89,90} GPUs.
 
+LoongArch Support in Clang
+---
+- Clang now supports LoongArch. Along with the backend, clang is able to build 
a
+  large corpus of Linux applications. Test-suite 100% pass.
+- Support basic option ``-march=`` which is used to select the target
+  architecture, i.e. the basic set of ISA modules to be enabled. Possible 
values
+  are ``loongarch64`` and ``la464``.
+- Support basic option ``-mabi=`` which is used select the base ABI type.
+  Possible values are ``lp64d``, ``lp64f``, ``lp64s``, ``ilp32d``, ``ilp32f``
+  and ``ilp32s``.
+- Support extended options: ``-msoft-float``, ``-msingle-float``, 
``-mdouble-float`` and `mfpu=``.
+  See `LoongArch toolchain conventions 
`_.
+
 RISC-V Support in Clang
 ---
 - ``sifive-7-rv32`` and ``sifive-7-rv64`` are no longer supported for 
``-mcpu``.


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -47,6 +47,8 @@
is not a constant in coroutines. This decision may cause unnecessary
performance regressions and we plan to fix it in later versions.
 
+*  The LoongArch target is promoted to "official" (see below for more details).
+
 * ...
 
 Update on required toolchains to build LLVM
@@ -154,6 +156,19 @@
 
 * ...
 
+Changes to the LoongArch Backend
+---
+
+* The LoongArch target is no longer "experimental"! It's now built by default,
+  rather than needing to be enabled with ``LLVM_EXPERIMENTAL_TARGETS_TO_BUILD``.
+
+* The backend has full codegen support for the base (both integer and
+  floating-point) instruction set and it conforms to psABI v2. Testing has been
+  performed with Linux, including native compilation of a large corpus of Linux
+  applications.
+
+* Support GHC calling convention.
+
 Changes to the MIPS Backend
 ---
 
@@ -279,9 +294,13 @@
 Changes to LLDB
 -
 
+* Initial support for debugging Linux LoongArch 64-bit binaries.
+
 Changes to Sanitizers
 -
 
+* Many Sanitizers (asan, fuzzer, lsan, safestack, scudo, tsan, ubsan) have
+  support for Linux LoongArch 64-bit variant. Some of them may be rudimentary.
 
 Other Changes
 -
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -798,6 +798,19 @@
 - Clang now supports CUDA SDK up to 11.8
 - Added support for targeting sm_{87,89,90} GPUs.
 
+LoongArch Support in Clang
+---
+- Cla

[PATCH] D141750: [docs] Add llvm & clang release notes for LoongArch

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

I'm not sure if there is any format issue. Is there any way to verify? e.g. how 
to generate .html like https://llvm.org/docs/ReleaseNotes.html?


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[PATCH] D141750: [docs] Add llvm & clang release notes for LoongArch

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D141750#4053469 , @SixWeining 
wrote:

> I'm not sure if there is any format issue. Is there any way to verify? e.g. 
> how to generate .html like https://llvm.org/docs/ReleaseNotes.html?

Now I find it: `llvm/docs/README.txt`.


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[PATCH] D141750: [docs] Add llvm & clang release notes for LoongArch

[Lu Weining via Phabricator via cfe-commits]

SixWeining updated this revision to Diff 489204.
SixWeining added a comment.

Fix the issue "Title underline too short" reported by sphinx-build.


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Files:
  clang/docs/ReleaseNotes.rst
  llvm/docs/ReleaseNotes.rst


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -47,6 +47,8 @@
is not a constant in coroutines. This decision may cause unnecessary
performance regressions and we plan to fix it in later versions.
 
+*  The LoongArch target is promoted to "official" (see below for more details).
+
 * ...
 
 Update on required toolchains to build LLVM
@@ -154,6 +156,19 @@
 
 * ...
 
+Changes to the LoongArch Backend
+
+
+* The LoongArch target is no longer "experimental"! It's now built by default,
+  rather than needing to be enabled with 
``LLVM_EXPERIMENTAL_TARGETS_TO_BUILD``.
+
+* The backend has full codegen support for the base (both integer and
+  floating-point) instruction set and it conforms to psABI v2. Testing has been
+  performed with Linux, including native compilation of a large corpus of Linux
+  applications.
+
+* Support GHC calling convention.
+
 Changes to the MIPS Backend
 ---
 
@@ -279,9 +294,13 @@
 Changes to LLDB
 -
 
+* Initial support for debugging Linux LoongArch 64-bit binaries.
+
 Changes to Sanitizers
 -
 
+* Many Sanitizers (asan, fuzzer, lsan, safestack, scudo, tsan, ubsan) have
+  support for Linux LoongArch 64-bit variant. Some of them may be rudimentary.
 
 Other Changes
 -
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -798,6 +798,19 @@
 - Clang now supports CUDA SDK up to 11.8
 - Added support for targeting sm_{87,89,90} GPUs.
 
+LoongArch Support in Clang
+--
+- Clang now supports LoongArch. Along with the backend, clang is able to build 
a
+  large corpus of Linux applications. Test-suite 100% pass.
+- Support basic option ``-march=`` which is used to select the target
+  architecture, i.e. the basic set of ISA modules to be enabled. Possible 
values
+  are ``loongarch64`` and ``la464``.
+- Support basic option ``-mabi=`` which is used select the base ABI type.
+  Possible values are ``lp64d``, ``lp64f``, ``lp64s``, ``ilp32d``, ``ilp32f``
+  and ``ilp32s``.
+- Support extended options: ``-msoft-float``, ``-msingle-float``, 
``-mdouble-float`` and ``mfpu=``.
+  See `LoongArch toolchain conventions 
`_.
+
 RISC-V Support in Clang
 ---
 - ``sifive-7-rv32`` and ``sifive-7-rv64`` are no longer supported for 
``-mcpu``.


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -47,6 +47,8 @@
is not a constant in coroutines. This decision may cause unnecessary
performance regressions and we plan to fix it in later versions.
 
+*  The LoongArch target is promoted to "official" (see below for more details).
+
 * ...
 
 Update on required toolchains to build LLVM
@@ -154,6 +156,19 @@
 
 * ...
 
+Changes to the LoongArch Backend
+
+
+* The LoongArch target is no longer "experimental"! It's now built by default,
+  rather than needing to be enabled with ``LLVM_EXPERIMENTAL_TARGETS_TO_BUILD``.
+
+* The backend has full codegen support for the base (both integer and
+  floating-point) instruction set and it conforms to psABI v2. Testing has been
+  performed with Linux, including native compilation of a large corpus of Linux
+  applications.
+
+* Support GHC calling convention.
+
 Changes to the MIPS Backend
 ---
 
@@ -279,9 +294,13 @@
 Changes to LLDB
 -
 
+* Initial support for debugging Linux LoongArch 64-bit binaries.
+
 Changes to Sanitizers
 -
 
+* Many Sanitizers (asan, fuzzer, lsan, safestack, scudo, tsan, ubsan) have
+  support for Linux LoongArch 64-bit variant. Some of them may be rudimentary.
 
 Other Changes
 -
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -798,6 +798,19 @@
 - Clang now supports CUDA SDK up to 11.8
 - Added support for targeting sm_{87,89,90} GPUs.
 
+LoongArch Support in Clang
+--
+- Clang now supports LoongArch. Along with the backend, clang is able to build a
+  large corpus of Linux applications. Test-suite 100% pass.
+- Support basic optio

[PATCH] D141750: [docs] Add llvm & clang release notes for LoongArch

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D141750#4053473 , @MaskRay wrote:

>   pip3 install --user recommonmark sphinx # sphinx-automodapi for lldb
>   
>   cmake ...
>   
>   ninja ... docs-llvm-html

Thanks.


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[PATCH] D141785: [Clang][LoongArch] Implement patchable function entry

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

Does anyone know why `patchable-function-entry` is not documented in 
https://llvm.org/docs/LangRef.html#function-attributes?




Comment at: llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp:150
+  .getAsInteger(10, Num))
+return false;
+  AP.emitNops(Num);

Seems should return `true`? Consider when verifier is disabled.

How about handling `PATCHABLE_FUNCTION_ENTER` in `LoongArchAsmPrinter.cpp` like 
D140727?


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[PATCH] D141750: [docs] Add llvm & clang release notes for LoongArch

[Lu Weining via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG64582189b3fc: [docs] Add llvm & clang release notes for 
LoongArch (authored by SixWeining).

Changed prior to commit:
  https://reviews.llvm.org/D141750?vs=489204&id=489773#toc

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Files:
  clang/docs/ReleaseNotes.rst
  llvm/docs/ReleaseNotes.rst


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -47,6 +47,8 @@
is not a constant in coroutines. This decision may cause unnecessary
performance regressions and we plan to fix it in later versions.
 
+*  The LoongArch target is promoted to "official" (see below for more details).
+
 * ...
 
 Update on required toolchains to build LLVM
@@ -154,6 +156,19 @@
 
 * ...
 
+Changes to the LoongArch Backend
+
+
+* The LoongArch target is no longer "experimental"! It's now built by default,
+  rather than needing to be enabled with 
``LLVM_EXPERIMENTAL_TARGETS_TO_BUILD``.
+
+* The backend has full codegen support for the base (both integer and
+  floating-point) instruction set and it conforms to psABI v2. Testing has been
+  performed with Linux, including native compilation of a large corpus of Linux
+  applications.
+
+* Support GHC calling convention.
+
 Changes to the MIPS Backend
 ---
 
@@ -279,9 +294,13 @@
 Changes to LLDB
 -
 
+* Initial support for debugging Linux LoongArch 64-bit binaries.
+
 Changes to Sanitizers
 -
 
+* Many Sanitizers (asan, fuzzer, lsan, safestack, scudo, tsan, ubsan) have
+  support for Linux LoongArch 64-bit variant. Some of them may be rudimentary.
 
 Other Changes
 -
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -802,6 +802,19 @@
 - Clang now supports CUDA SDK up to 11.8
 - Added support for targeting sm_{87,89,90} GPUs.
 
+LoongArch Support in Clang
+--
+- Clang now supports LoongArch. Along with the backend, clang is able to build 
a
+  large corpus of Linux applications. Test-suite 100% pass.
+- Support basic option ``-march=`` which is used to select the target
+  architecture, i.e. the basic set of ISA modules to be enabled. Possible 
values
+  are ``loongarch64`` and ``la464``.
+- Support basic option ``-mabi=`` which is used to select the base ABI type.
+  Possible values are ``lp64d``, ``lp64f``, ``lp64s``, ``ilp32d``, ``ilp32f``
+  and ``ilp32s``.
+- Support extended options: ``-msoft-float``, ``-msingle-float``, 
``-mdouble-float`` and ``mfpu=``.
+  See `LoongArch toolchain conventions 
`_.
+
 RISC-V Support in Clang
 ---
 - ``sifive-7-rv32`` and ``sifive-7-rv64`` are no longer supported for 
``-mcpu``.


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -47,6 +47,8 @@
is not a constant in coroutines. This decision may cause unnecessary
performance regressions and we plan to fix it in later versions.
 
+*  The LoongArch target is promoted to "official" (see below for more details).
+
 * ...
 
 Update on required toolchains to build LLVM
@@ -154,6 +156,19 @@
 
 * ...
 
+Changes to the LoongArch Backend
+
+
+* The LoongArch target is no longer "experimental"! It's now built by default,
+  rather than needing to be enabled with ``LLVM_EXPERIMENTAL_TARGETS_TO_BUILD``.
+
+* The backend has full codegen support for the base (both integer and
+  floating-point) instruction set and it conforms to psABI v2. Testing has been
+  performed with Linux, including native compilation of a large corpus of Linux
+  applications.
+
+* Support GHC calling convention.
+
 Changes to the MIPS Backend
 ---
 
@@ -279,9 +294,13 @@
 Changes to LLDB
 -
 
+* Initial support for debugging Linux LoongArch 64-bit binaries.
+
 Changes to Sanitizers
 -
 
+* Many Sanitizers (asan, fuzzer, lsan, safestack, scudo, tsan, ubsan) have
+  support for Linux LoongArch 64-bit variant. Some of them may be rudimentary.
 
 Other Changes
 -
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -802,6 +802,19 @@
 - Clang now supports CUDA SDK up to 11.8
 - Added support for targeting sm_{87,89,90} GPUs.
 
+LoongArch Support in Clang
+-

[PATCH] D155824: [LoongArch] Support -march=native and -mtune=

[Lu Weining via Phabricator via cfe-commits]

SixWeining created this revision.
SixWeining added reviewers: xen0n, xry111, hev, wangleiat.
Herald added a subscriber: hiraditya.
Herald added a project: All.
SixWeining requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, MaskRay.
Herald added projects: clang, LLVM.

As described in [1][2], `-mtune=` is used to select the type of target
microarchitecture, defaults to the value of `-march`. The set of
possible values should be a superset of `-march` values. Currently
possible values of `-march=` and `-mtune=` are `native`, `loongarch64`
and `la464`.

D136146  has supported 
`-march={loongarch64,la464}` and this patch adds
support for `-march=native` and `-mtune=`.

A new ProcessorModel called `loongarch64` is defined in LoongArch.td
to support `-mtune=loongarch64`.

`llvm::sys::getHostCPUName()` returns `generic` on unknown or future
LoongArch CPUs, e.g. the not yet added `la664`, leading to
`llvm::LoongArch::isValidArchName()` failing to parse the arch name.
In this case, use `loongarch64` as the default arch name for 64-bit
CPUs.

And these two preprocessor macros are defined:

- __loongarch_arch
- __loongarch_tune

[1]: 
https://github.com/loongson/LoongArch-Documentation/blob/2023.04.20/docs/LoongArch-toolchain-conventions-EN.adoc
[2]: 
https://github.com/loongson/la-softdev-convention/blob/v0.1/la-softdev-convention.adoc


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Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/loongarch-mtune-error.c
  clang/test/Driver/loongarch-mtune.c
  clang/test/Preprocessor/init-loongarch.c
  llvm/include/llvm/TargetParser/LoongArchTargetParser.h
  llvm/lib/Target/LoongArch/LoongArch.td
  llvm/lib/TargetParser/LoongArchTargetParser.cpp
  llvm/test/CodeGen/LoongArch/cpus-invalid.ll
  llvm/test/CodeGen/LoongArch/cpus.ll

Index: llvm/test/CodeGen/LoongArch/cpus.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/cpus.ll
@@ -0,0 +1,20 @@
+;; This tests that llc accepts all valid LoongArch CPUs.
+;; Note the 'generic' names have been tested in cpu-name-generic.ll.
+
+; RUN: llc < %s --mtriple=loongarch64 --mcpu=loongarch64 2>&1 | FileCheck %s
+; RUN: llc < %s --mtriple=loongarch64 --mcpu=la464 2>&1 | FileCheck %s
+; RUN: llc < %s --mtriple=loongarch64 2>&1 | FileCheck %s
+
+; CHECK-NOT: {{.*}} is not a recognized processor for this target
+
+define void @f() {
+  ret void
+}
+
+define void @tune_cpu_loongarch64() "tune-cpu"="loongarch64" {
+  ret void
+}
+
+define void @tune_cpu_la464() "tune-cpu"="la464" {
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/cpus-invalid.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/cpus-invalid.ll
@@ -0,0 +1,7 @@
+; RUN: llc < %s --mtriple=loongarch64 --mattr=+64bit --mcpu=invalidcpu 2>&1 | FileCheck %s
+
+; CHECK: {{.*}} is not a recognized processor for this target
+
+define void @f() {
+  ret void
+}
Index: llvm/lib/TargetParser/LoongArchTargetParser.cpp
===
--- llvm/lib/TargetParser/LoongArchTargetParser.cpp
+++ llvm/lib/TargetParser/LoongArchTargetParser.cpp
@@ -16,6 +16,9 @@
 using namespace llvm;
 using namespace llvm::LoongArch;
 
+StringRef Arch;
+StringRef TuneCPU;
+
 const FeatureInfo AllFeatures[] = {
 #define LOONGARCH_FEATURE(NAME, KIND) {NAME, KIND},
 #include "llvm/TargetParser/LoongArchTargetParser.def"
@@ -46,3 +49,25 @@
   }
   return false;
 }
+
+bool LoongArch::isValidTuneCPUName(StringRef TuneCPU) {
+  return isValidArchName(TuneCPU);
+}
+
+void LoongArch::fillValidTuneCPUList(SmallVectorImpl &Values) {
+  for (const auto A : AllArchs)
+Values.emplace_back(A.Name);
+}
+
+StringRef LoongArch::getDefaultArch(bool Is64Bit) {
+  // TODO: use a real 32-bit arch name.
+  return Is64Bit ? "loongarch64" : "";
+}
+
+void LoongArch::setArch(StringRef Name) { Arch = Name; }
+
+StringRef LoongArch::getArch() { return Arch; }
+
+void LoongArch::setTuneCPU(StringRef Name) { TuneCPU = Name; }
+
+StringRef LoongArch::getTuneCPU() { return TuneCPU; }
Index: llvm/lib/Target/LoongArch/LoongArch.td
===
--- llvm/lib/Target/LoongArch/LoongArch.td
+++ llvm/lib/Target/LoongArch/LoongArch.td
@@ -117,6 +117,11 @@
 def : ProcessorModel<"generic-la32", NoSchedModel, [Feature32Bit]>;
 def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit, FeatureUAL]>;
 
+// Generic 64-bit processor with double-precision floating-point support.
+def : ProcessorModel<"loongarch64", NoSchedModel, [Feature64Bit,
+   FeatureUAL,
+   FeatureBasicD]>;
+
 // Support gene

[PATCH] D155824: [LoongArch] Support -march=native and -mtune=

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

In D155824#4518597 , @xry111 wrote:

> Do we need to convert Xuerui's label alignment change to use the -mtune 
> framework?

How to set the numbers if `TuneCPU` is empty? If there is no differences among 
`empty`, `loongarch64` and `la464`, seems it's better to do this until we 
support other uarchs, e.g. `la[236]64`.

Just like the `TODO` in D148622 :

  63   // TODO: Check TuneCPU and override defaults (that are for LA464) once we
  64   // support optimizing for more uarchs.


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[PATCH] D154931: [LoongArch] Support InlineAsm for LSX and LASX

[Lu Weining via Phabricator via cfe-commits]

SixWeining added inline comments.



Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp:56
 addRegisterClass(MVT::f64, &LoongArch::FPR64RegClass);
+  if (Subtarget.hasExtLSX()) {
+for (auto VT : {MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32,

useless brace



Comment at: llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll:40
+
+;; The lower 64-bit of the vector register '$xr31' is same as the
+;; floating-point register '$f31' ('$fs7'). And '$f31' ('$fs7')

`overlapped with` is more accurate.


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[PATCH] D155824: [LoongArch] Support -march=native and -mtune=

[Lu Weining via Phabricator via cfe-commits]

SixWeining added a comment.

> In GCC I added the numbers for "loongarch64" and "la464" although they are 
> the same, and GCC does not have "empty".  But yes we can do things later here.

Ah, I just realize `TuneCPU` is always not empty because:

  27 LoongArchSubtarget &LoongArchSubtarget::initializeSubtargetDependencies(
  28 const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
  29 StringRef ABIName) {
  30   bool Is64Bit = TT.isArch64Bit();
  31   if (CPU.empty() || CPU == "generic")
  32 CPU = Is64Bit ? "generic-la64" : "generic-la32"; // empty CPU will be 
converted to generic-la{64,32}
  33 
  34   if (TuneCPU.empty())
  35 TuneCPU = CPU; // empty TuneCPU will be converted to CPU, so TuneCPU 
is not empty when we all initializeProperties below
  36 
  37   ParseSubtargetFeatures(CPU, TuneCPU, FS);
  38   initializeProperties(TuneCPU);

So, the problem is how to set numbers for `generic-la{64,32}` ? Currenly if we 
directly use `clang hello.c`, `TuneCPU` is `generic-la64`.


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