r340595 - [RISCV] RISC-V using -fuse-init-array by default
Author: kito
Date: Thu Aug 23 20:05:08 2018
New Revision: 340595
URL: http://llvm.org/viewvc/llvm-project?rev=340595&view=rev
Log:
[RISCV] RISC-V using -fuse-init-array by default
Reviewers: asb, apazos, mgrang
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D50043
Modified:
cfe/trunk/lib/Driver/ToolChains/Gnu.cpp
cfe/trunk/test/Driver/riscv32-toolchain.c
Modified: cfe/trunk/lib/Driver/ToolChains/Gnu.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Gnu.cpp?rev=340595&r1=340594&r2=340595&view=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Gnu.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Gnu.cpp Thu Aug 23 20:05:08 2018
@@ -2554,7 +2554,9 @@ void Generic_ELF::addClangTargetOptions(
getTriple().getOS() == llvm::Triple::NaCl ||
(getTriple().getVendor() == llvm::Triple::MipsTechnologies &&
!getTriple().hasEnvironment()) ||
- getTriple().getOS() == llvm::Triple::Solaris;
+ getTriple().getOS() == llvm::Triple::Solaris ||
+ getTriple().getArch() == llvm::Triple::riscv32 ||
+ getTriple().getArch() == llvm::Triple::riscv64;
if (DriverArgs.hasFlag(options::OPT_fuse_init_array,
options::OPT_fno_use_init_array, UseInitArrayDefault))
Modified: cfe/trunk/test/Driver/riscv32-toolchain.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/riscv32-toolchain.c?rev=340595&r1=340594&r2=340595&view=diff
==
--- cfe/trunk/test/Driver/riscv32-toolchain.c (original)
+++ cfe/trunk/test/Driver/riscv32-toolchain.c Thu Aug 23 20:05:08 2018
@@ -9,6 +9,7 @@
// RUN: --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
// RUN: | FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32 %s
+// C-RV32-BAREMETAL-ILP32: "-fuse-init-array"
// C-RV32-BAREMETAL-ILP32:
"{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
// C-RV32-BAREMETAL-ILP32:
"--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
// C-RV32-BAREMETAL-ILP32:
"{{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf/lib{{/|}}crt0.o"
@@ -24,6 +25,7 @@
// RUN: --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
// RUN: | FileCheck -check-prefix=CXX-RV32-BAREMETAL-ILP32 %s
+// CXX-RV32-BAREMETAL-ILP32: "-fuse-init-array"
// CXX-RV32-BAREMETAL-ILP32: "-internal-isystem"
"{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/include/c++{{/|}}8.0.1"
// CXX-RV32-BAREMETAL-ILP32:
"{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
// CXX-RV32-BAREMETAL-ILP32:
"--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
@@ -40,6 +42,7 @@
// RUN: --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
// RUN: | FileCheck -check-prefix=C-RV32-LINUX-MULTI-ILP32 %s
+// C-RV32-LINUX-MULTI-ILP32: "-fuse-init-array"
// C-RV32-LINUX-MULTI-ILP32:
"{{.*}}/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/../../../../riscv64-unknown-linux-gnu/bin{{/|}}ld"
// C-RV32-LINUX-MULTI-ILP32:
"--sysroot={{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot"
// C-RV32-LINUX-MULTI-ILP32: "-m" "elf32lriscv"
@@ -55,6 +58,7 @@
// RUN: --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
// RUN: | FileCheck -check-prefix=C-RV32-LINUX-MULTI-ILP32D %s
+// C-RV32-LINUX-MULTI-ILP32D: "-fuse-init-array"
// C-RV32-LINUX-MULTI-ILP32D:
"{{.*}}/Inputs/multilib_riscv_linux_sdk/lib/gcc/riscv64-unknown-linux-gnu/7.2.0/../../../../riscv64-unknown-linux-gnu/bin{{/|}}ld"
// C-RV32-LINUX-MULTI-ILP32D:
"--sysroot={{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot"
// C-RV32-LINUX-MULTI-ILP32D: "-m" "elf32lriscv"
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r372078 - [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly
Author: kito
Date: Tue Sep 17 01:09:56 2019
New Revision: 372078
URL: http://llvm.org/viewvc/llvm-project?rev=372078&view=rev
Log:
[RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly
RISC-V LLVM was only implement small/medlow code model, so it defined
__riscv_cmodel_medlow directly without check.
Now, we have medium/medany code model in RISC-V back-end, it should
define according the actually code model.
Reviewed By: lewis-revill
Differential Revision: https://reviews.llvm.org/D67065
Added:
cfe/trunk/test/Preprocessor/riscv-cmodel.c
Modified:
cfe/trunk/lib/Basic/Targets/RISCV.cpp
Modified: cfe/trunk/lib/Basic/Targets/RISCV.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/RISCV.cpp?rev=372078&r1=372077&r2=372078&view=diff
==
--- cfe/trunk/lib/Basic/Targets/RISCV.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/RISCV.cpp Tue Sep 17 01:09:56 2019
@@ -88,8 +88,14 @@ void RISCVTargetInfo::getTargetDefines(c
Builder.defineMacro("__riscv");
bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");
- // TODO: modify when more code models are supported.
- Builder.defineMacro("__riscv_cmodel_medlow");
+ StringRef CodeModel = getTargetOpts().CodeModel;
+ if (CodeModel == "default")
+CodeModel = "small";
+
+ if (CodeModel == "small")
+Builder.defineMacro("__riscv_cmodel_medlow");
+ else if (CodeModel == "medium")
+Builder.defineMacro("__riscv_cmodel_medany");
StringRef ABIName = getABI();
if (ABIName == "ilp32f" || ABIName == "lp64f")
Added: cfe/trunk/test/Preprocessor/riscv-cmodel.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/riscv-cmodel.c?rev=372078&view=auto
==
--- cfe/trunk/test/Preprocessor/riscv-cmodel.c (added)
+++ cfe/trunk/test/Preprocessor/riscv-cmodel.c Tue Sep 17 01:09:56 2019
@@ -0,0 +1,20 @@
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -mcmodel=small -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -mcmodel=small -o - | FileCheck --check-prefix=CHECK-MEDLOW %s
+
+// CHECK-MEDLOW: #define __riscv_cmodel_medlow 1
+// CHECK-MEDLOW-NOT: __riscv_cmodel_medany
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
+// RUN: -mcmodel=medium -o - | FileCheck --check-prefix=CHECK-MEDANY %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
+// RUN: -mcmodel=medium -o - | FileCheck --check-prefix=CHECK-MEDANY %s
+
+// CHECK-MEDANY: #define __riscv_cmodel_medany 1
+// CHECK-MEDANY-NOT: __riscv_cmodel_medlow
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r372080 - [RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow
Author: kito Date: Tue Sep 17 01:19:17 2019 New Revision: 372080 URL: http://llvm.org/viewvc/llvm-project?rev=372080&view=rev Log: [RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow RISC-V GCC use -mcmodel=medany and -mcmodel=medlow, but LLVM use -mcmodel=small and -mcmodel=medium. Add those two option aliases for provide same user interface between GCC and LLVM. Reviewed By: lenary Differential Revision: https://reviews.llvm.org/D67066 Modified: cfe/trunk/include/clang/Driver/Options.td cfe/trunk/test/Preprocessor/riscv-cmodel.c Modified: cfe/trunk/include/clang/Driver/Options.td URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=372080&r1=372079&r2=372080&view=diff == --- cfe/trunk/include/clang/Driver/Options.td (original) +++ cfe/trunk/include/clang/Driver/Options.td Tue Sep 17 01:19:17 2019 @@ -2177,6 +2177,12 @@ def msave_restore : Flag<["-"], "msave-r HelpText<"Enable using library calls for save and restore">; def mno_save_restore : Flag<["-"], "mno-save-restore">, Group, HelpText<"Disable using library calls for save and restore">; +def mcmodel_EQ_medlow : Flag<["-"], "mcmodel=medlow">, Group, + Flags<[CC1Option]>, Alias, AliasArgs<["small"]>, + HelpText<"Equivalent to -mcmodel=small, compatible with RISC-V gcc.">; +def mcmodel_EQ_medany : Flag<["-"], "mcmodel=medany">, Group, + Flags<[CC1Option]>, Alias, AliasArgs<["medium"]>, + HelpText<"Equivalent to -mcmodel=medium, compatible with RISC-V gcc.">; def munaligned_access : Flag<["-"], "munaligned-access">, Group, HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64 only)">; Modified: cfe/trunk/test/Preprocessor/riscv-cmodel.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/riscv-cmodel.c?rev=372080&r1=372079&r2=372080&view=diff == --- cfe/trunk/test/Preprocessor/riscv-cmodel.c (original) +++ cfe/trunk/test/Preprocessor/riscv-cmodel.c Tue Sep 17 01:19:17 2019 @@ -8,6 +8,11 @@ // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \ // RUN: -mcmodel=small -o - | FileCheck --check-prefix=CHECK-MEDLOW %s +// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \ +// RUN: -mcmodel=medlow -o - | FileCheck --check-prefix=CHECK-MEDLOW %s +// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \ +// RUN: -mcmodel=medlow -o - | FileCheck --check-prefix=CHECK-MEDLOW %s + // CHECK-MEDLOW: #define __riscv_cmodel_medlow 1 // CHECK-MEDLOW-NOT: __riscv_cmodel_medany @@ -16,5 +21,10 @@ // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \ // RUN: -mcmodel=medium -o - | FileCheck --check-prefix=CHECK-MEDANY %s +// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \ +// RUN: -mcmodel=medany -o - | FileCheck --check-prefix=CHECK-MEDANY %s +// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \ +// RUN: -mcmodel=medany -o - | FileCheck --check-prefix=CHECK-MEDANY %s + // CHECK-MEDANY: #define __riscv_cmodel_medany 1 // CHECK-MEDANY-NOT: __riscv_cmodel_medlow ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] Remove experimental from Vector Crypto extensions (PR #69000)
@@ -106,6 +106,8 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zdinx", RISCVExtensionVersion{1, 0}},
+{"zexperimental", RISCVExtensionVersion{1, 0}},
+
kito-cheng wrote:
I guess we don't really need this dummy extension in RISCVISAInfo?
https://github.com/llvm/llvm-project/pull/69000
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[clang] [clang] Enable --gcc-install-dir for RISCV baremetal toolchains (PR #71803)
https://github.com/kito-cheng approved this pull request. Checked with `Generic_GCC::GCCInstallationDetector::init` to make sure clang will use that to search gcc toolchain, so LGTM. https://github.com/llvm/llvm-project/pull/71803 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Add vundefine intrinsics for tuple types (PR #70354)
@@ -7,534 +7,2189 @@
#include
-// CHECK-RV64-LABEL: define dso_local
@test_vundefined_f16mf4
-// CHECK-RV64-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-LABEL: define dso_local
@test_vundefined_f16mf4(
+// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT:ret poison
//
-vfloat16mf4_t test_vundefined_f16mf4() {
- return __riscv_vundefined_f16mf4();
-}
+vfloat16mf4_t test_vundefined_f16mf4() { return __riscv_vundefined_f16mf4(); }
kito-cheng wrote:
Why this format changed here? it seems unrelated to this patch?
https://github.com/llvm/llvm-project/pull/70354
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[clang] [Clang][RISCV] Add vundefine intrinsics for tuple types (PR #70354)
@@ -1,4 +1,4 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 3
kito-cheng wrote:
Does this cause those changes?
```diff
-// CHECK-RV64-LABEL: define dso_local
@test_vundefined_f16mf4
-// CHECK-RV64-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-LABEL: define dso_local
@test_vundefined_f16mf4(
+// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
```
https://github.com/llvm/llvm-project/pull/70354
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[clang] [Clang][RISCV] Add vundefine intrinsics for tuple types (PR #70354)
https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/70354 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)
kito-cheng wrote: short version: GCC isn't change. long version: GCC's configure script isn't change, it's configure script in riscv-gnu-toolchain But I don't have strong opinion on this change since I believe user should explicitly specify that, otherwise it's really to screw up to select multi-lib or portability issue between different compilers. https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)
@@ -693,6 +693,13 @@ def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, AssemblerPredicate<(all_of FeatureStdExtZimop), "'Zimop' (May-Be-Operations)">; +def FeatureStdExtZcmop : SubtargetFeature<"experimental-zcmop", "HasStdExtZcmop", "true", + "'Zcmop' (Compressed May-Be-Operations)", + [FeatureStdExtZca]>; kito-cheng wrote: My understanding for those terminology on RISC-V ISA spec is: imply == depend == require See comment from Krste and Andrew in this issue: https://github.com/riscv/riscv-v-spec/issues/723#issuecomment-922153867 https://github.com/llvm/llvm-project/pull/76395 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add B extension (PR #76893)
kito-cheng wrote: I would suggest set it as 0.1 rather than 1.0, and I gonna to ask Ved to add version info as well... https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add B extension (PR #76893)
kito-cheng wrote: And forgot to say: thanks for raise this issue! I didn't aware b extension is back again until this PR created. https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add B extension (PR #76893)
kito-cheng wrote: Issue created at riscv-b: https://github.com/riscv/riscv-b/issues/3 https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
kito-cheng wrote: Hmmm, RISC-V ISA is growth after https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257 again, I mean...we have zfinx and zdinx, which is also valid combination with rv32e/rv64e, so we may need to revise ilp32e ABI again on the psABI side, but my intention is not to block this PR. Anyway, I think we could track that on psABI repo, and we...already has an old issue to track that: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/269 https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)
kito-cheng wrote: @wangpc-pp did you have interested on helping psABI side? it would be great if you can help since I suspect I don't have enough bandwidth to deal with that soon. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -463,7 +464,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult &LR,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult &LR,
IdentifierInfo *II,
Preprocessor &PP) {
- StringRef Name = II->getName();
+ StringRef Name = II->getName().substr(8);
kito-cheng wrote:
What's the magic number of 8?
https://github.com/llvm/llvm-project/pull/77487
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[clang] 1b8cde9 - [RISCV][NFC] Move static global variables into static variable in function.
Author: Kito Cheng
Date: 2022-06-30T10:30:01+08:00
New Revision: 1b8cde9b633841c7199b345132423dd3d6bdf3e7
URL:
https://github.com/llvm/llvm-project/commit/1b8cde9b633841c7199b345132423dd3d6bdf3e7
DIFF:
https://github.com/llvm/llvm-project/commit/1b8cde9b633841c7199b345132423dd3d6bdf3e7.diff
LOG: [RISCV][NFC] Move static global variables into static variable in function.
It's violate coding guideline in LLVM coding standard[1], because the the
initialization order is nondeterministic and that might increase the launch
time of programs.
However these variables are only used to cache query result, so we can move
these variables into the function,, that which resolve both issue: 1.
initialized in deterministic order, 2. Initialized that when the first time
used.
[1] https://llvm.org/docs/CodingStandards.html#do-not-use-static-constructors
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D128726
Added:
Modified:
clang/lib/Support/RISCVVIntrinsicUtils.cpp
Removed:
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 0d7ca0ed0f1fa..d4d3f22c93279 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -31,10 +31,6 @@ const PrototypeDescriptor PrototypeDescriptor::VL =
const PrototypeDescriptor PrototypeDescriptor::Vector =
PrototypeDescriptor(BaseTypeModifier::Vector);
-// Concat BasicType, LMUL and Proto as key
-static std::unordered_map LegalTypes;
-static std::set IllegalTypes;
-
//===--===//
// Type implementation
//===--===//
@@ -822,6 +818,9 @@ static uint64_t computeRVVTypeHashValue(BasicType BT, int
Log2LMUL,
Optional RVVType::computeType(BasicType BT, int Log2LMUL,
PrototypeDescriptor Proto) {
+ // Concat BasicType, LMUL and Proto as key
+ static std::unordered_map LegalTypes;
+ static std::set IllegalTypes;
uint64_t Idx = computeRVVTypeHashValue(BT, Log2LMUL, Proto);
// Search first
auto It = LegalTypes.find(Idx);
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[clang] ad57e10 - [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support
Author: Kito Cheng
Date: 2022-03-28T14:35:28+08:00
New Revision: ad57e10dbca2fdeff1448afc0aa1cf23d6df8736
URL:
https://github.com/llvm/llvm-project/commit/ad57e10dbca2fdeff1448afc0aa1cf23d6df8736
DIFF:
https://github.com/llvm/llvm-project/commit/ad57e10dbca2fdeff1448afc0aa1cf23d6df8736.diff
LOG: [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support
This patch is split from https://reviews.llvm.org/D111617, we need those
stuffs on clang, so must moving those stuff to llvm/Support.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D121984
Added:
llvm/include/llvm/Support/RISCVVIntrinsicUtils.h
llvm/lib/Support/RISCVVIntrinsicUtils.cpp
Modified:
clang/utils/TableGen/RISCVVEmitter.cpp
llvm/lib/Support/CMakeLists.txt
Removed:
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp
b/clang/utils/TableGen/RISCVVEmitter.cpp
index f26b1189c1e97..accced0292f0e 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,211 +20,15 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/Twine.h"
+#include "llvm/Support/RISCVVIntrinsicUtils.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include
using namespace llvm;
-using BasicType = char;
-using VScaleVal = Optional;
+using namespace llvm::RISCV;
namespace {
-
-// Exponential LMUL
-struct LMULType {
- int Log2LMUL;
- LMULType(int Log2LMUL);
- // Return the C/C++ string representation of LMUL
- std::string str() const;
- Optional getScale(unsigned ElementBitwidth) const;
- void MulLog2LMUL(int Log2LMUL);
- LMULType &operator*=(uint32_t RHS);
-};
-
-// This class is compact representation of a valid and invalid RVVType.
-class RVVType {
- enum ScalarTypeKind : uint32_t {
-Void,
-Size_t,
-Ptr
diff _t,
-UnsignedLong,
-SignedLong,
-Boolean,
-SignedInteger,
-UnsignedInteger,
-Float,
-Invalid,
- };
- BasicType BT;
- ScalarTypeKind ScalarType = Invalid;
- LMULType LMUL;
- bool IsPointer = false;
- // IsConstant indices are "int", but have the constant expression.
- bool IsImmediate = false;
- // Const qualifier for pointer to const object or object of const type.
- bool IsConstant = false;
- unsigned ElementBitwidth = 0;
- VScaleVal Scale = 0;
- bool Valid;
-
- std::string BuiltinStr;
- std::string ClangBuiltinStr;
- std::string Str;
- std::string ShortStr;
-
-public:
- RVVType() : RVVType(BasicType(), 0, StringRef()) {}
- RVVType(BasicType BT, int Log2LMUL, StringRef prototype);
-
- // Return the string representation of a type, which is an encoded string for
- // passing to the BUILTIN() macro in Builtins.def.
- const std::string &getBuiltinStr() const { return BuiltinStr; }
-
- // Return the clang builtin type for RVV vector type which are used in the
- // riscv_vector.h header file.
- const std::string &getClangBuiltinStr() const { return ClangBuiltinStr; }
-
- // Return the C/C++ string representation of a type for use in the
- // riscv_vector.h header file.
- const std::string &getTypeStr() const { return Str; }
-
- // Return the short name of a type for C/C++ name suffix.
- const std::string &getShortStr() {
-// Not all types are used in short name, so compute the short name by
-// demanded.
-if (ShortStr.empty())
- initShortStr();
-return ShortStr;
- }
-
- bool isValid() const { return Valid; }
- bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
- bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
- bool isVector(unsigned Width) const {
-return isVector() && ElementBitwidth == Width;
- }
- bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
- bool isSignedInteger() const {
-return ScalarType == ScalarTypeKind::SignedInteger;
- }
- bool isFloatVector(unsigned Width) const {
-return isVector() && isFloat() && ElementBitwidth == Width;
- }
- bool isFloat(unsigned Width) const {
-return isFloat() && ElementBitwidth == Width;
- }
-
-private:
- // Verify RVV vector type and set Valid.
- bool verifyType() const;
-
- // Creates a type based on basic types of TypeRange
- void applyBasicType();
-
- // Applies a prototype modifier to the current type. The result maybe an
- // invalid type.
- void applyModifier(StringRef prototype);
-
- // Compute and record a string for legal type.
- void initBuiltinStr();
- // Compute and record a builtin RVV vector type string.
- void initClangBuiltinStr();
- // Compute and record a type string for used in the header.
- void initTypeStr();
- // Compute and record a short name of a type for C/C++ name suffix.
- void initShortStr();
-};
-
-using RVVTypePtr = RVVType *;
-using RVVTypes = std::vector;
-using RISCVPredefinedMacroT = uint8_t;
-
-enum RISCVPredefinedMacro : RISCVPredefined
[clang] 7a5cb15 - [RISCV] Lazily add RVV C intrinsics.
Author: Kito Cheng
Date: 2022-07-26T15:47:47+08:00
New Revision: 7a5cb15ea6facd82756adafae76d60f36a0b60fd
URL:
https://github.com/llvm/llvm-project/commit/7a5cb15ea6facd82756adafae76d60f36a0b60fd
DIFF:
https://github.com/llvm/llvm-project/commit/7a5cb15ea6facd82756adafae76d60f36a0b60fd.diff
LOG: [RISCV] Lazily add RVV C intrinsics.
Leverage the method OpenCL uses that adds C intrinsics when the lookup
failed. There is no need to define C intrinsics in the header file any
more. It could help to avoid the large header file to speed up the
compilation of RVV source code. Besides that, only the C intrinsics used
by the users will be added into the declaration table.
This patch is based on https://reviews.llvm.org/D103228 and inspired by
OpenCL implementation.
### Experimental Results
TL;DR:
- Binary size of clang increase ~200k, which is +0.07% for debug build and
+0.13% for release build.
- Single file compilation speed up ~33x for debug build and ~8.5x for release
build
- Regression time reduce ~10% (`ninja check-all`, enable all targets)
Header size change
```
| size | LoC |
--
Before | 4,434,725 | 69,749 |
After | 6,140 | 162 |
```
Single File Compilation Time
Testcase:
```
#include
vint32m1_t test_vadd_vv_vfloat32m1_t(vint32m1_t op1, vint32m1_t op2, size_t vl)
{
return vadd(op1, op2, vl);
}
```
# Debug build:
Before:
```
real0m19.352s
user0m19.252s
sys 0m0.092s
```
After:
```
real0m0.576s
user0m0.552s
sys 0m0.024s
```
~33x speed up for debug build
# Release build:
Before:
```
real0m0.773s
user0m0.741s
sys 0m0.032s
```
After:
```
real0m0.092s
user0m0.080s
sys 0m0.012s
```
~8.5x speed up for release build
Regression time
Note: the failed case is `tools/llvm-debuginfod-find/debuginfod.test` which is
unrelated to this patch.
# Debug build
Before:
```
Testing Time: 1358.38s
Skipped :11
Unsupported : 446
Passed : 75767
Expectedly Failed: 190
Failed : 1
```
After
```
Testing Time: 1220.29s
Skipped :11
Unsupported : 446
Passed : 75767
Expectedly Failed: 190
Failed : 1
```
# Release build
Before:
```
Testing Time: 381.98s
Skipped :12
Unsupported : 1407
Passed : 74765
Expectedly Failed: 176
Failed : 1
```
After:
```
Testing Time: 346.25s
Skipped :12
Unsupported : 1407
Passed : 74765
Expectedly Failed: 176
Failed : 1
```
Binary size of clang
# Debug build
Before
```
textdata bss dec hex filename
335261851 12726004 552812 348540667 14c64efb
bin/clang
```
After
```
textdata bss dec hex filename
335442803 12798708 552940 348794451 14ca2e53
bin/clang
```
+253K, +0.07% code size
# Release build
Before
```
textdata bss dec hex filename
144123975 8374648 483140 152981763 91e5103 bin/clang
```
After
```
textdata bss dec hex filename
144255762 8447296 483268 153186326 9217016 bin/clang
```
+204K, +0.13%
Authored-by: Kito Cheng
Co-Authored-by: Hsiangkai Wang
Reviewed By: khchen, aaron.ballman
Differential Revision: https://reviews.llvm.org/D111617
Added:
clang/include/clang/Sema/RISCVIntrinsicManager.h
clang/lib/Sema/SemaRISCVVectorLookup.cpp
clang/test/Sema/riscv-bad-intrinsic-pragma.c
clang/test/Sema/riscv-intrinsic-pragma.c
Modified:
clang/include/clang/Basic/CMakeLists.txt
clang/include/clang/Basic/TokenKinds.def
clang/include/clang/Parse/Parser.h
clang/include/clang/Sema/Sema.h
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/Parse/ParsePragma.cpp
clang/lib/Sema/CMakeLists.txt
clang/lib/Sema/Sema.cpp
clang/lib/Sema/SemaLookup.cpp
clang/lib/Support/RISCVVIntrinsicUtils.cpp
clang/utils/TableGen/RISCVVEmitter.cpp
clang/utils/TableGen/TableGen.cpp
clang/utils/TableGen/TableGenBackends.h
Removed:
diff --git a/clang/include/clang/Basic/CMakeLists.txt
b/clang/include/clang/Basic/CMakeLists.txt
index 8cd891385a483..b930842ae8cfd 100644
--- a/clang/include/clang/Basic/CMakeLists.txt
+++ b/clang/include/clang/Basic/CMakeLists.txt
@@ -90,3 +90,6 @@ clang_tablegen(riscv_vector_builtins.inc
-gen-riscv-vector-builtins
clang_tablegen(riscv_vector_builtin_cg.inc -gen-riscv-vector-builtin-codegen
SOURCE riscv_vector.td
TARGET ClangRISCVVectorBuiltinCG)
+clang_tablegen(riscv_vector_builtin_sema.inc -gen-riscv-vector-builtin-sema
+ SOURCE riscv_vector.td
+ TARGET ClangRISCVVectorBuiltinSema)
diff --git a/clang/include/clang/Basic/TokenKinds.def
b/clang/include/clang/Basic/TokenKinds.def
index 7b65a
[clang] fc2d832 - Reland "[RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support"
Author: Kito Cheng
Date: 2022-04-08T15:09:03+08:00
New Revision: fc2d8326ae4d6e05c1aa2db7e7dbd8e759bf4d51
URL:
https://github.com/llvm/llvm-project/commit/fc2d8326ae4d6e05c1aa2db7e7dbd8e759bf4d51
DIFF:
https://github.com/llvm/llvm-project/commit/fc2d8326ae4d6e05c1aa2db7e7dbd8e759bf4d51.diff
LOG: Reland "[RISCV][NFC] Moving RVV intrinsic type related util to
llvm/Support"
Reland Note: We've resolve the circular dependency issue on llvm/lib/Support and
llvm/TableGen.
Differential Revision: https://reviews.llvm.org/D121984
Added:
llvm/include/llvm/Support/RISCVVIntrinsicUtils.h
llvm/lib/Support/RISCVVIntrinsicUtils.cpp
Modified:
clang/utils/TableGen/RISCVVEmitter.cpp
llvm/lib/Support/CMakeLists.txt
Removed:
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp
b/clang/utils/TableGen/RISCVVEmitter.cpp
index f26b1189c1e97..accced0292f0e 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,211 +20,15 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/Twine.h"
+#include "llvm/Support/RISCVVIntrinsicUtils.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include
using namespace llvm;
-using BasicType = char;
-using VScaleVal = Optional;
+using namespace llvm::RISCV;
namespace {
-
-// Exponential LMUL
-struct LMULType {
- int Log2LMUL;
- LMULType(int Log2LMUL);
- // Return the C/C++ string representation of LMUL
- std::string str() const;
- Optional getScale(unsigned ElementBitwidth) const;
- void MulLog2LMUL(int Log2LMUL);
- LMULType &operator*=(uint32_t RHS);
-};
-
-// This class is compact representation of a valid and invalid RVVType.
-class RVVType {
- enum ScalarTypeKind : uint32_t {
-Void,
-Size_t,
-Ptr
diff _t,
-UnsignedLong,
-SignedLong,
-Boolean,
-SignedInteger,
-UnsignedInteger,
-Float,
-Invalid,
- };
- BasicType BT;
- ScalarTypeKind ScalarType = Invalid;
- LMULType LMUL;
- bool IsPointer = false;
- // IsConstant indices are "int", but have the constant expression.
- bool IsImmediate = false;
- // Const qualifier for pointer to const object or object of const type.
- bool IsConstant = false;
- unsigned ElementBitwidth = 0;
- VScaleVal Scale = 0;
- bool Valid;
-
- std::string BuiltinStr;
- std::string ClangBuiltinStr;
- std::string Str;
- std::string ShortStr;
-
-public:
- RVVType() : RVVType(BasicType(), 0, StringRef()) {}
- RVVType(BasicType BT, int Log2LMUL, StringRef prototype);
-
- // Return the string representation of a type, which is an encoded string for
- // passing to the BUILTIN() macro in Builtins.def.
- const std::string &getBuiltinStr() const { return BuiltinStr; }
-
- // Return the clang builtin type for RVV vector type which are used in the
- // riscv_vector.h header file.
- const std::string &getClangBuiltinStr() const { return ClangBuiltinStr; }
-
- // Return the C/C++ string representation of a type for use in the
- // riscv_vector.h header file.
- const std::string &getTypeStr() const { return Str; }
-
- // Return the short name of a type for C/C++ name suffix.
- const std::string &getShortStr() {
-// Not all types are used in short name, so compute the short name by
-// demanded.
-if (ShortStr.empty())
- initShortStr();
-return ShortStr;
- }
-
- bool isValid() const { return Valid; }
- bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
- bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
- bool isVector(unsigned Width) const {
-return isVector() && ElementBitwidth == Width;
- }
- bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
- bool isSignedInteger() const {
-return ScalarType == ScalarTypeKind::SignedInteger;
- }
- bool isFloatVector(unsigned Width) const {
-return isVector() && isFloat() && ElementBitwidth == Width;
- }
- bool isFloat(unsigned Width) const {
-return isFloat() && ElementBitwidth == Width;
- }
-
-private:
- // Verify RVV vector type and set Valid.
- bool verifyType() const;
-
- // Creates a type based on basic types of TypeRange
- void applyBasicType();
-
- // Applies a prototype modifier to the current type. The result maybe an
- // invalid type.
- void applyModifier(StringRef prototype);
-
- // Compute and record a string for legal type.
- void initBuiltinStr();
- // Compute and record a builtin RVV vector type string.
- void initClangBuiltinStr();
- // Compute and record a type string for used in the header.
- void initTypeStr();
- // Compute and record a short name of a type for C/C++ name suffix.
- void initShortStr();
-};
-
-using RVVTypePtr = RVVType *;
-using RVVTypes = std::vector;
-using RISCVPredefinedMacroT = uint8_t;
-
-enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
- Basic = 0,
- V = 1 << 1,
- Zvfh = 1
[clang] f922dbb - Revert "Reland "[RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support""
Author: Kito Cheng
Date: 2022-04-08T16:20:19+08:00
New Revision: f922dbb7923f73bab058d09346a2ec0b40ae3cb2
URL:
https://github.com/llvm/llvm-project/commit/f922dbb7923f73bab058d09346a2ec0b40ae3cb2
DIFF:
https://github.com/llvm/llvm-project/commit/f922dbb7923f73bab058d09346a2ec0b40ae3cb2.diff
LOG: Revert "Reland "[RISCV][NFC] Moving RVV intrinsic type related util to
llvm/Support""
This reverts commit fc2d8326ae4d6e05c1aa2db7e7dbd8e759bf4d51.
Added:
Modified:
clang/utils/TableGen/RISCVVEmitter.cpp
llvm/lib/Support/CMakeLists.txt
Removed:
llvm/include/llvm/Support/RISCVVIntrinsicUtils.h
llvm/lib/Support/RISCVVIntrinsicUtils.cpp
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp
b/clang/utils/TableGen/RISCVVEmitter.cpp
index accced0292f0e..f26b1189c1e97 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -20,15 +20,211 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/Twine.h"
-#include "llvm/Support/RISCVVIntrinsicUtils.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include
using namespace llvm;
-using namespace llvm::RISCV;
+using BasicType = char;
+using VScaleVal = Optional;
namespace {
+
+// Exponential LMUL
+struct LMULType {
+ int Log2LMUL;
+ LMULType(int Log2LMUL);
+ // Return the C/C++ string representation of LMUL
+ std::string str() const;
+ Optional getScale(unsigned ElementBitwidth) const;
+ void MulLog2LMUL(int Log2LMUL);
+ LMULType &operator*=(uint32_t RHS);
+};
+
+// This class is compact representation of a valid and invalid RVVType.
+class RVVType {
+ enum ScalarTypeKind : uint32_t {
+Void,
+Size_t,
+Ptr
diff _t,
+UnsignedLong,
+SignedLong,
+Boolean,
+SignedInteger,
+UnsignedInteger,
+Float,
+Invalid,
+ };
+ BasicType BT;
+ ScalarTypeKind ScalarType = Invalid;
+ LMULType LMUL;
+ bool IsPointer = false;
+ // IsConstant indices are "int", but have the constant expression.
+ bool IsImmediate = false;
+ // Const qualifier for pointer to const object or object of const type.
+ bool IsConstant = false;
+ unsigned ElementBitwidth = 0;
+ VScaleVal Scale = 0;
+ bool Valid;
+
+ std::string BuiltinStr;
+ std::string ClangBuiltinStr;
+ std::string Str;
+ std::string ShortStr;
+
+public:
+ RVVType() : RVVType(BasicType(), 0, StringRef()) {}
+ RVVType(BasicType BT, int Log2LMUL, StringRef prototype);
+
+ // Return the string representation of a type, which is an encoded string for
+ // passing to the BUILTIN() macro in Builtins.def.
+ const std::string &getBuiltinStr() const { return BuiltinStr; }
+
+ // Return the clang builtin type for RVV vector type which are used in the
+ // riscv_vector.h header file.
+ const std::string &getClangBuiltinStr() const { return ClangBuiltinStr; }
+
+ // Return the C/C++ string representation of a type for use in the
+ // riscv_vector.h header file.
+ const std::string &getTypeStr() const { return Str; }
+
+ // Return the short name of a type for C/C++ name suffix.
+ const std::string &getShortStr() {
+// Not all types are used in short name, so compute the short name by
+// demanded.
+if (ShortStr.empty())
+ initShortStr();
+return ShortStr;
+ }
+
+ bool isValid() const { return Valid; }
+ bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
+ bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+ bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+ }
+ bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
+ bool isSignedInteger() const {
+return ScalarType == ScalarTypeKind::SignedInteger;
+ }
+ bool isFloatVector(unsigned Width) const {
+return isVector() && isFloat() && ElementBitwidth == Width;
+ }
+ bool isFloat(unsigned Width) const {
+return isFloat() && ElementBitwidth == Width;
+ }
+
+private:
+ // Verify RVV vector type and set Valid.
+ bool verifyType() const;
+
+ // Creates a type based on basic types of TypeRange
+ void applyBasicType();
+
+ // Applies a prototype modifier to the current type. The result maybe an
+ // invalid type.
+ void applyModifier(StringRef prototype);
+
+ // Compute and record a string for legal type.
+ void initBuiltinStr();
+ // Compute and record a builtin RVV vector type string.
+ void initClangBuiltinStr();
+ // Compute and record a type string for used in the header.
+ void initTypeStr();
+ // Compute and record a short name of a type for C/C++ name suffix.
+ void initShortStr();
+};
+
+using RVVTypePtr = RVVType *;
+using RVVTypes = std::vector;
+using RISCVPredefinedMacroT = uint8_t;
+
+enum RISCVPredefinedMacro : RISCVPredefinedMacroT {
+ Basic = 0,
+ V = 1 << 1,
+ Zvfh = 1 << 2,
+ RV64 = 1 << 3,
+ VectorMaxELen64 = 1 << 4,
+ VectorMaxELenFp32 = 1 <<
[clang] f26c41e - [RISCV] Moving RVV intrinsic type related util to clang/Support
Author: Kito Cheng
Date: 2022-04-20T21:13:13+08:00
New Revision: f26c41e8dd28d86030cd0f5a6e9c11036acea5d2
URL:
https://github.com/llvm/llvm-project/commit/f26c41e8dd28d86030cd0f5a6e9c11036acea5d2
DIFF:
https://github.com/llvm/llvm-project/commit/f26c41e8dd28d86030cd0f5a6e9c11036acea5d2.diff
LOG: [RISCV] Moving RVV intrinsic type related util to clang/Support
We add a new clang library called `clangSupport` for putting those utils which
can be used in clang table-gen and other clang component.
We tried to put that into `llvm/Support`, but actually those stuffs only used
in clang* and clang-tblgen, so I think that might be better to create
`clang/Support`
* clang will used that in https://reviews.llvm.org/D111617.
Reviewed By: khchen, MaskRay, aaron.ballman
Differential Revision: https://reviews.llvm.org/D121984
Added:
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/Support/CMakeLists.txt
clang/lib/Support/RISCVVIntrinsicUtils.cpp
Modified:
clang/lib/CMakeLists.txt
clang/utils/TableGen/CMakeLists.txt
clang/utils/TableGen/RISCVVEmitter.cpp
Removed:
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
new file mode 100644
index 0..1a4947d0c3df3
--- /dev/null
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -0,0 +1,215 @@
+//===--- RISCVVIntrinsicUtils.h - RISC-V Vector Intrinsic Utils -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef CLANG_SUPPORT_RISCVVINTRINSICUTILS_H
+#define CLANG_SUPPORT_RISCVVINTRINSICUTILS_H
+
+#include "llvm/ADT/Optional.h"
+#include "llvm/ADT/StringRef.h"
+#include
+#include
+#include
+
+namespace clang {
+namespace RISCV {
+
+using BasicType = char;
+using VScaleVal = llvm::Optional;
+
+// Exponential LMUL
+struct LMULType {
+ int Log2LMUL;
+ LMULType(int Log2LMUL);
+ // Return the C/C++ string representation of LMUL
+ std::string str() const;
+ llvm::Optional getScale(unsigned ElementBitwidth) const;
+ void MulLog2LMUL(int Log2LMUL);
+ LMULType &operator*=(uint32_t RHS);
+};
+
+// This class is compact representation of a valid and invalid RVVType.
+class RVVType {
+ enum ScalarTypeKind : uint32_t {
+Void,
+Size_t,
+Ptr
diff _t,
+UnsignedLong,
+SignedLong,
+Boolean,
+SignedInteger,
+UnsignedInteger,
+Float,
+Invalid,
+ };
+ BasicType BT;
+ ScalarTypeKind ScalarType = Invalid;
+ LMULType LMUL;
+ bool IsPointer = false;
+ // IsConstant indices are "int", but have the constant expression.
+ bool IsImmediate = false;
+ // Const qualifier for pointer to const object or object of const type.
+ bool IsConstant = false;
+ unsigned ElementBitwidth = 0;
+ VScaleVal Scale = 0;
+ bool Valid;
+
+ std::string BuiltinStr;
+ std::string ClangBuiltinStr;
+ std::string Str;
+ std::string ShortStr;
+
+public:
+ RVVType() : RVVType(BasicType(), 0, llvm::StringRef()) {}
+ RVVType(BasicType BT, int Log2LMUL, llvm::StringRef prototype);
+
+ // Return the string representation of a type, which is an encoded string for
+ // passing to the BUILTIN() macro in Builtins.def.
+ const std::string &getBuiltinStr() const { return BuiltinStr; }
+
+ // Return the clang builtin type for RVV vector type which are used in the
+ // riscv_vector.h header file.
+ const std::string &getClangBuiltinStr() const { return ClangBuiltinStr; }
+
+ // Return the C/C++ string representation of a type for use in the
+ // riscv_vector.h header file.
+ const std::string &getTypeStr() const { return Str; }
+
+ // Return the short name of a type for C/C++ name suffix.
+ const std::string &getShortStr() {
+// Not all types are used in short name, so compute the short name by
+// demanded.
+if (ShortStr.empty())
+ initShortStr();
+return ShortStr;
+ }
+
+ bool isValid() const { return Valid; }
+ bool isScalar() const { return Scale.hasValue() && Scale.getValue() == 0; }
+ bool isVector() const { return Scale.hasValue() && Scale.getValue() != 0; }
+ bool isVector(unsigned Width) const {
+return isVector() && ElementBitwidth == Width;
+ }
+ bool isFloat() const { return ScalarType == ScalarTypeKind::Float; }
+ bool isSignedInteger() const {
+return ScalarType == ScalarTypeKind::SignedInteger;
+ }
+ bool isFloatVector(unsigned Width) const {
+return isVector() && isFloat() && ElementBitwidth == Width;
+ }
+ bool isFloat(unsigned Width) const {
+return isFloat() && ElementBitwidth == Width;
+ }
+
+private:
+ // Verify RVV vector type and set Valid.
+ bool verifyType() const;
+
+ // Creates a type based on basic type
[clang] 02c7de3 - [RISCV] Precommit test for D124509
Author: Kito Cheng
Date: 2022-04-30T11:09:12+08:00
New Revision: 02c7de3a4c32f2456df09df07e473bb95c85529c
URL:
https://github.com/llvm/llvm-project/commit/02c7de3a4c32f2456df09df07e473bb95c85529c
DIFF:
https://github.com/llvm/llvm-project/commit/02c7de3a4c32f2456df09df07e473bb95c85529c.diff
LOG: [RISCV] Precommit test for D124509
Test case to show the wrong code gen for `int16` -> `__fp16` conversion,
clang just emit a load and store without did conversion in the case,
and another case used for demonstrate the code gen change of `__fp16`
-> `int16`.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D124510
Added:
clang/test/CodeGen/RISCV/__fp16-convert.c
Modified:
Removed:
diff --git a/clang/test/CodeGen/RISCV/__fp16-convert.c
b/clang/test/CodeGen/RISCV/__fp16-convert.c
new file mode 100644
index ..cdb17553
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/__fp16-convert.c
@@ -0,0 +1,26 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+__fp16 y;
+short z;
+// CHECK-LABEL: @bar1(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @y, align 2
+// CHECK-NEXT:[[TMP1:%.*]] = call float @llvm.convert.from.fp16.f32(i16
[[TMP0]])
+// CHECK-NEXT:[[CONV:%.*]] = fptosi float [[TMP1]] to i16
+// CHECK-NEXT:store i16 [[CONV]], ptr @z, align 2
+// CHECK-NEXT:ret void
+//
+void bar1(){
+z = y;
+}
+// CHECK-LABEL: @bar2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @z, align 2
+// CHECK-NEXT:store i16 [[TMP0]], ptr @y, align 2
+// CHECK-NEXT:ret void
+//
+void bar2(){
+y = z;
+}
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[clang] 41b951c - [RISCV] Fix int16 -> __fp16 conversion code gen
Author: Kito Cheng
Date: 2022-04-30T11:10:44+08:00
New Revision: 41b951c92931b65c25485b224901d8cb00163b8e
URL:
https://github.com/llvm/llvm-project/commit/41b951c92931b65c25485b224901d8cb00163b8e
DIFF:
https://github.com/llvm/llvm-project/commit/41b951c92931b65c25485b224901d8cb00163b8e.diff
LOG: [RISCV] Fix int16 -> __fp16 conversion code gen
clang emit wrong code sequence for `int16`(`short`) to `__fp16` conversion,
and that should fix the code gen directly is the right way I think,
but I found there is a FIXME comment in clang/Basic/TargetInfo.h say
that's should be removed in future so I think just let swich to using
generic LLVM IR rather than llvm.convert.to.fp16 intrinsics code gen
path is enough.
```
/// Check whether llvm intrinsics such as llvm.convert.to.fp16 should be used
/// to convert to and from __fp16.
/// FIXME: This function should be removed once all targets stop using the
/// conversion intrinsics.
virtual bool useFP16ConversionIntrinsics() const {
return true;
}
```
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D124509
Added:
Modified:
clang/lib/Basic/Targets/RISCV.h
clang/test/CodeGen/RISCV/__fp16-convert.c
Removed:
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index 5331ed4a50aef..7817e6e81e26a 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -96,6 +96,10 @@ class RISCVTargetInfo : public TargetInfo {
DiagnosticsEngine &Diags) override;
bool hasBitIntType() const override { return true; }
+
+ bool useFP16ConversionIntrinsics() const override {
+return false;
+ }
};
class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
public:
diff --git a/clang/test/CodeGen/RISCV/__fp16-convert.c
b/clang/test/CodeGen/RISCV/__fp16-convert.c
index cdb17553a..36c746df7d340 100644
--- a/clang/test/CodeGen/RISCV/__fp16-convert.c
+++ b/clang/test/CodeGen/RISCV/__fp16-convert.c
@@ -6,10 +6,10 @@ __fp16 y;
short z;
// CHECK-LABEL: @bar1(
// CHECK-NEXT: entry:
-// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @y, align 2
-// CHECK-NEXT:[[TMP1:%.*]] = call float @llvm.convert.from.fp16.f32(i16
[[TMP0]])
-// CHECK-NEXT:[[CONV:%.*]] = fptosi float [[TMP1]] to i16
-// CHECK-NEXT:store i16 [[CONV]], ptr @z, align 2
+// CHECK-NEXT:[[TMP0:%.*]] = load half, ptr @y, align 2
+// CHECK-NEXT:[[CONV:%.*]] = fpext half [[TMP0]] to float
+// CHECK-NEXT:[[CONV1:%.*]] = fptosi float [[CONV]] to i16
+// CHECK-NEXT:store i16 [[CONV1]], ptr @z, align 2
// CHECK-NEXT:ret void
//
void bar1(){
@@ -18,7 +18,9 @@ void bar1(){
// CHECK-LABEL: @bar2(
// CHECK-NEXT: entry:
// CHECK-NEXT:[[TMP0:%.*]] = load i16, ptr @z, align 2
-// CHECK-NEXT:store i16 [[TMP0]], ptr @y, align 2
+// CHECK-NEXT:[[CONV:%.*]] = sitofp i16 [[TMP0]] to float
+// CHECK-NEXT:[[CONV1:%.*]] = fptrunc float [[CONV]] to half
+// CHECK-NEXT:store half [[CONV1]], ptr @y, align 2
// CHECK-NEXT:ret void
//
void bar2(){
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[clang] 7ff0bf5 - [RISCV][NFC] Refactor RISC-V vector intrinsic utils.
Author: Kito Cheng
Date: 2022-05-16T15:13:05+08:00
New Revision: 7ff0bf576b841d5418c0fb1c4b94f16c6205e7d9
URL:
https://github.com/llvm/llvm-project/commit/7ff0bf576b841d5418c0fb1c4b94f16c6205e7d9
DIFF:
https://github.com/llvm/llvm-project/commit/7ff0bf576b841d5418c0fb1c4b94f16c6205e7d9.diff
LOG: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.
This patch is preparation for D111617, use class/struct/enum rather than
char/StringRef to present internal information as possible, that provide more
compact way to store those info and also easier to serialize/deserialize.
And also that improve readability of the code, e.g. "v" vs TypeProfile::Vector.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D124730
Added:
Modified:
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/Support/RISCVVIntrinsicUtils.cpp
clang/utils/TableGen/RISCVVEmitter.cpp
Removed:
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 1a4947d0c3df3..f1f06ba60786f 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -9,7 +9,10 @@
#ifndef CLANG_SUPPORT_RISCVVINTRINSICUTILS_H
#define CLANG_SUPPORT_RISCVVINTRINSICUTILS_H
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/BitmaskEnum.h"
#include "llvm/ADT/Optional.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include
#include
@@ -18,9 +21,133 @@
namespace clang {
namespace RISCV {
-using BasicType = char;
using VScaleVal = llvm::Optional;
+// Modifier for vector type.
+enum class VectorTypeModifier : uint8_t {
+ NoModifier,
+ Widening2XVector,
+ Widening4XVector,
+ Widening8XVector,
+ MaskVector,
+ Log2EEW3,
+ Log2EEW4,
+ Log2EEW5,
+ Log2EEW6,
+ FixedSEW8,
+ FixedSEW16,
+ FixedSEW32,
+ FixedSEW64,
+ LFixedLog2LMULN3,
+ LFixedLog2LMULN2,
+ LFixedLog2LMULN1,
+ LFixedLog2LMUL0,
+ LFixedLog2LMUL1,
+ LFixedLog2LMUL2,
+ LFixedLog2LMUL3,
+ SFixedLog2LMULN3,
+ SFixedLog2LMULN2,
+ SFixedLog2LMULN1,
+ SFixedLog2LMUL0,
+ SFixedLog2LMUL1,
+ SFixedLog2LMUL2,
+ SFixedLog2LMUL3,
+};
+
+// Similar to basic type but used to describe what's kind of type related to
+// basic vector type, used to compute type info of arguments.
+enum class BaseTypeModifier : uint8_t {
+ Invalid,
+ Scalar,
+ Vector,
+ Void,
+ SizeT,
+ Ptr
diff ,
+ UnsignedLong,
+ SignedLong,
+};
+
+// Modifier for type, used for both scalar and vector types.
+enum class TypeModifier : uint8_t {
+ NoModifier = 0,
+ Pointer = 1 << 0,
+ Const = 1 << 1,
+ Immediate = 1 << 2,
+ UnsignedInteger = 1 << 3,
+ SignedInteger = 1 << 4,
+ Float = 1 << 5,
+ // LMUL1 should be kind of VectorTypeModifier, but that might come with
+ // Widening2XVector for widening reduction.
+ // However that might require VectorTypeModifier become bitmask rather than
+ // simple enum, so we decide keek LMUL1 in TypeModifier for code size
+ // optimization of clang binary size.
+ LMUL1 = 1 << 6,
+ MaxOffset = 6,
+ LLVM_MARK_AS_BITMASK_ENUM(LMUL1),
+};
+
+// PrototypeDescriptor is used to compute type info of arguments or return
+// value.
+struct PrototypeDescriptor {
+ constexpr PrototypeDescriptor() = default;
+ constexpr PrototypeDescriptor(
+ BaseTypeModifier PT,
+ VectorTypeModifier VTM = VectorTypeModifier::NoModifier,
+ TypeModifier TM = TypeModifier::NoModifier)
+ : PT(static_cast(PT)), VTM(static_cast(VTM)),
+TM(static_cast(TM)) {}
+ constexpr PrototypeDescriptor(uint8_t PT, uint8_t VTM, uint8_t TM)
+ : PT(PT), VTM(VTM), TM(TM) {}
+
+ uint8_t PT = static_cast(BaseTypeModifier::Invalid);
+ uint8_t VTM = static_cast(VectorTypeModifier::NoModifier);
+ uint8_t TM = static_cast(TypeModifier::NoModifier);
+
+ bool operator!=(const PrototypeDescriptor &PD) const {
+return PD.PT != PT || PD.VTM != VTM || PD.TM != TM;
+ }
+ bool operator>(const PrototypeDescriptor &PD) const {
+return !(PD.PT <= PT && PD.VTM <= VTM && PD.TM <= TM);
+ }
+
+ static const PrototypeDescriptor Mask;
+ static const PrototypeDescriptor Vector;
+ static const PrototypeDescriptor VL;
+ static llvm::Optional
+ parsePrototypeDescriptor(llvm::StringRef PrototypeStr);
+};
+
+llvm::SmallVector
+parsePrototypes(llvm::StringRef Prototypes);
+
+// Basic type of vector type.
+enum class BasicType : uint8_t {
+ Unknown = 0,
+ Int8 = 1 << 0,
+ Int16 = 1 << 1,
+ Int32 = 1 << 2,
+ Int64 = 1 << 3,
+ Float16 = 1 << 4,
+ Float32 = 1 << 5,
+ Float64 = 1 << 6,
+ MaxOffset = 6,
+ LLVM_MARK_AS_BITMASK_ENUM(Float64),
+};
+
+// Type of vector type.
+enum ScalarTypeKind : uint8_t {
+ Void,
+ Size_t,
+ Ptr
diff _t,
+ UnsignedLong,
+ SignedLong,
+ Boolean,
+ SignedInteger,
+ UnsignedInteger,
+ Float,
+ Invalid,
+};
+
// Exponential LMUL
struct LMULType {
int Log2LMUL;
@@ -
[clang] 5bc469f - [RISCV][NFC] Fix build issue
Author: Kito Cheng
Date: 2022-05-16T16:00:23+08:00
New Revision: 5bc469fd96192039bafe4bb9f74c85b37f63212e
URL:
https://github.com/llvm/llvm-project/commit/5bc469fd96192039bafe4bb9f74c85b37f63212e
DIFF:
https://github.com/llvm/llvm-project/commit/5bc469fd96192039bafe4bb9f74c85b37f63212e.diff
LOG: [RISCV][NFC] Fix build issue
Added:
Modified:
clang/lib/Support/RISCVVIntrinsicUtils.cpp
Removed:
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index a0ca7b7c5166..9f5c1ffe2022 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -788,8 +788,6 @@ void RVVType::applyFixedLog2LMUL(int Log2LMUL, enum
FixedLMULType Type) {
return;
}
break;
- default:
-llvm_unreachable("Unknown FixedLMULType??");
}
// Update new LMUL
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[clang] 1467e01 - [RISCV][NFC] Rename variable in RISCVVEmitter.cpp
Author: Kito Cheng
Date: 2022-05-18T23:14:29+08:00
New Revision: 1467e01f8f699fa2a69937dd07e51325ba71a93b
URL:
https://github.com/llvm/llvm-project/commit/1467e01f8f699fa2a69937dd07e51325ba71a93b
DIFF:
https://github.com/llvm/llvm-project/commit/1467e01f8f699fa2a69937dd07e51325ba71a93b.diff
LOG: [RISCV][NFC] Rename variable in RISCVVEmitter.cpp
- Use `Overloaded` rather than `Mangled`.
- Use `Prototype` or `Desc` rather than `Seq`, it's not just a string sequence.
- `Prototype` for those PrototypeDescriptor will used to evaluate as argument
type.
- `Desc` for those PrototypeDescriptor will used to evaluate as part of
function name.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D125886
Added:
Modified:
clang/utils/TableGen/RISCVVEmitter.cpp
Removed:
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp
b/clang/utils/TableGen/RISCVVEmitter.cpp
index 49282af3cbe4b..dc6cbcbbf4ed5 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -387,8 +387,8 @@ void RVVEmitter::createRVVIntrinsics(
for (auto *R : RV) {
StringRef Name = R->getValueAsString("Name");
StringRef SuffixProto = R->getValueAsString("Suffix");
-StringRef MangledName = R->getValueAsString("MangledName");
-StringRef MangledSuffixProto = R->getValueAsString("MangledSuffix");
+StringRef OverloadedName = R->getValueAsString("MangledName");
+StringRef OverloadedSuffixProto = R->getValueAsString("MangledSuffix");
StringRef Prototypes = R->getValueAsString("Prototype");
StringRef TypeRange = R->getValueAsString("TypeRange");
bool HasMasked = R->getValueAsBit("HasMasked");
@@ -414,30 +414,30 @@ void RVVEmitter::createRVVIntrinsics(
unsigned NF = R->getValueAsInt("NF");
// Parse prototype and create a list of primitive type with transformers
-// (operand) in ProtoSeq. ProtoSeq[0] is output operand.
-SmallVector ProtoSeq = parsePrototypes(Prototypes);
+// (operand) in Prototype. Prototype[0] is output operand.
+SmallVector Prototype = parsePrototypes(Prototypes);
-SmallVector SuffixProtoSeq =
-parsePrototypes(SuffixProto);
-SmallVector MangledSuffixProtoSeq =
-parsePrototypes(MangledSuffixProto);
+SmallVector SuffixDesc = parsePrototypes(SuffixProto);
+SmallVector OverloadedSuffixDesc =
+parsePrototypes(OverloadedSuffixProto);
// Compute Builtin types
-SmallVector ProtoMaskSeq = ProtoSeq;
+SmallVector MaskedPrototype = Prototype;
if (HasMasked) {
// If HasMaskedOffOperand, insert result type as first input operand.
if (HasMaskedOffOperand) {
if (NF == 1) {
- ProtoMaskSeq.insert(ProtoMaskSeq.begin() + 1, ProtoSeq[0]);
+ MaskedPrototype.insert(MaskedPrototype.begin() + 1, Prototype[0]);
} else {
// Convert
// (void, op0 address, op1 address, ...)
// to
// (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)
- PrototypeDescriptor MaskoffType = ProtoSeq[1];
+ PrototypeDescriptor MaskoffType = Prototype[1];
MaskoffType.TM &= ~static_cast(TypeModifier::Pointer);
for (unsigned I = 0; I < NF; ++I)
-ProtoMaskSeq.insert(ProtoMaskSeq.begin() + NF + 1, MaskoffType);
+MaskedPrototype.insert(MaskedPrototype.begin() + NF + 1,
+ MaskoffType);
}
}
if (HasMaskedOffOperand && NF > 1) {
@@ -446,18 +446,18 @@ void RVVEmitter::createRVVIntrinsics(
// to
// (void, op0 address, op1 address, ..., mask, maskedoff0, maskedoff1,
// ...)
-ProtoMaskSeq.insert(ProtoMaskSeq.begin() + NF + 1,
-PrototypeDescriptor::Mask);
+MaskedPrototype.insert(MaskedPrototype.begin() + NF + 1,
+ PrototypeDescriptor::Mask);
} else {
// If HasMasked, insert PrototypeDescriptor:Mask as first input
operand.
-ProtoMaskSeq.insert(ProtoMaskSeq.begin() + 1,
-PrototypeDescriptor::Mask);
+MaskedPrototype.insert(MaskedPrototype.begin() + 1,
+ PrototypeDescriptor::Mask);
}
}
// If HasVL, append PrototypeDescriptor:VL to last operand
if (HasVL) {
- ProtoSeq.push_back(PrototypeDescriptor::VL);
- ProtoMaskSeq.push_back(PrototypeDescriptor::VL);
+ Prototype.push_back(PrototypeDescriptor::VL);
+ MaskedPrototype.push_back(PrototypeDescriptor::VL);
}
// Create Intrinsics for each type and LMUL.
@@ -465,18 +465,17 @@ void RVVEmitter::createRVVIntrinsics(
for (int Log2LMUL : Log2LMULList) {
BasicType BT = ParseBasicType(I);
Optional Types =
-RVVType::computeTypes(BT, Log2LMUL, NF, ProtoSeq);
+RVVType
[clang] b166aa8 - [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr
Author: Kito Cheng
Date: 2022-05-24T17:24:32+08:00
New Revision: b166aa833e44a5af6d6f39c34b79fe21b443e424
URL:
https://github.com/llvm/llvm-project/commit/b166aa833e44a5af6d6f39c34b79fe21b443e424
DIFF:
https://github.com/llvm/llvm-project/commit/b166aa833e44a5af6d6f39c34b79fe21b443e424.diff
LOG: [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr
This NFC patch is splited from D111617.
Using llvm::ArrayRef rather than llvm::SmallVector, ArrayRef is more generic
interface that could accept both llvm::ArrayRef and llvm::SmallVector.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D125893
Added:
Modified:
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/Support/RISCVVIntrinsicUtils.cpp
Removed:
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 2de7f89f0..0a7186d42c856 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -340,9 +340,9 @@ class RVVIntrinsic {
// Return the type string for a BUILTIN() macro in Builtins.def.
std::string getBuiltinTypeStr() const;
- static std::string getSuffixStr(
- BasicType Type, int Log2LMUL,
- const llvm::SmallVector &PrototypeDescriptors);
+ static std::string
+ getSuffixStr(BasicType Type, int Log2LMUL,
+ llvm::ArrayRef PrototypeDescriptors);
};
} // end namespace RISCV
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 43189f6cf9f50..92d29043f2cc0 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -922,7 +922,7 @@ std::string RVVIntrinsic::getBuiltinTypeStr() const {
std::string RVVIntrinsic::getSuffixStr(
BasicType Type, int Log2LMUL,
-const llvm::SmallVector &PrototypeDescriptors) {
+llvm::ArrayRef PrototypeDescriptors) {
SmallVector SuffixStrs;
for (auto PD : PrototypeDescriptors) {
auto T = RVVType::computeType(Type, Log2LMUL, PD);
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[clang] Revert "[Driver] Default riscv*- triples to -fdebug-default-version=4" (PR #84119)
https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/84119 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Disallow target attribute use in multiversioning (PR #85899)
kito-cheng wrote: Add a testcase like AArch64 https://reviews.llvm.org/D150867 ? https://github.com/llvm/llvm-project/pull/85899 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Driver] Default -msmall-data-limit= to 0 and clean up code (PR #83093)
kito-cheng wrote: There is some discussion in last (2024/2/29) LLVM sync up meeting: We all agree that might not useful in linux target and those platforms disable GP relaxation, like Android and fuchsia; However it's still useful for embedded toolchain, so this change may surprise those embedded toolchain user - cause some code size regression due to this change; although lld NOT default enable GP relaxation and also not implement all GP relaxation (`R_RISCV_PCREL_HI20` + `R_RISCV_PCREL_LO12_I` or `R_RISCV_PCREL_LO12_S` is missing), but user may use GNU linker or proprietary linker, so people would like to keep some case using same default in some case. --- Back to the implementation - yes, GCC is not support `-G` in this case, but why clang support `-G`? it's kinda inherit from the MIPS and Hexagon, they defined `-msmall-data-threshold` and then alias to `-G`, so RISC-V also follow the same convention: `-msmall-data-limit=` is alias to `-G` (that's my understanding after archaeology, although I work with Shiva at that timing but I don't have too much memory about that). > -mcmodel=large doesn't work for RISC-V yet, so the special case is strange. My best guess is that is because @ShivaChen was working for Andes at that timing, and the patch is extracted from downstream source tree and it already has that logic, and no body notice that during review process...:P [1] https://reviews.llvm.org/D57497 https://github.com/llvm/llvm-project/pull/83093 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)
https://github.com/kito-cheng closed https://github.com/llvm/llvm-project/pull/81727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)
https://github.com/kito-cheng commented: Could you add a testcase? https://github.com/llvm/llvm-project/pull/83553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [lld] [llvm] [RISCV] Support .note.gnu.property for enable Zicfiss and Zicfilp extension (PR #77414)
https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/77414 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Add assumptions to vsetvli/vsetvlimax (PR #79975)
kito-cheng wrote: Does it possible to add testcases to demonstrate that can improve optimization? https://github.com/llvm/llvm-project/pull/79975 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Support constraint "s" (PR #80201)
https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/80201 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Support constraint "s" (PR #80201)
@@ -0,0 +1,76 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -relocation-model=static < %s | FileCheck %s
--check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -relocation-model=pic < %s | FileCheck %s
--check-prefix=RV64
+
+@var = external dso_local global i32, align 4
+@a = external global [2 x [2 x i32]], align 4
+
+define dso_local void @test() {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:#APP
+; CHECK-NEXT:# var a+12 test
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:ret{{[l|q]}}
kito-cheng wrote:
I don't see any line check with `CHECK`? maybe you forgot to drop after regen?
https://github.com/llvm/llvm-project/pull/80201
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[llvm] [clang] [RISCV] Support constraint "s" (PR #80201)
https://github.com/kito-cheng approved this pull request. Just one minor comment, otherwise LGTM :) https://github.com/llvm/llvm-project/pull/80201 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Add assumptions to vsetvli/vsetvlimax (PR #79975)
kito-cheng wrote: I guess we need add that at RVVEmitter::createbuilt...@riscvvemitter.cpp? [1] https://github.com/llvm/llvm-project/blob/main/clang/utils/TableGen/RISCVVEmitter.cpp#L418 [2] https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Basic/Builtins.h#L122-L124 [3] https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Basic/BuiltinsARM.def#L32 https://github.com/llvm/llvm-project/pull/79975 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Add assumptions to vsetvli/vsetvlimax (PR #79975)
kito-cheng wrote: Also I guess most of RVV intrinsic could add `const` too, that could help some generic optimization work better like CSE. https://github.com/llvm/llvm-project/pull/79975 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)
kito-cheng wrote: I am working on GCC part[1], and it's still under review, also @bemg is working very closely with me :) [1] https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642151.html https://github.com/llvm/llvm-project/pull/78120 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add B extension (PR #76893)
kito-cheng wrote: It tagged with 0.1 now :) https://github.com/riscv/riscv-b/releases/tag/v0.1 https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Driver] Reject unsupported -mcmodel= (PR #70262)
kito-cheng wrote: LGTM for the RISC-V bits, thanks :) https://github.com/llvm/llvm-project/pull/70262 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] cfa7094 - [RISCV] Add -mtune support
Author: Kito Cheng
Date: 2020-10-16T13:55:08+08:00
New Revision: cfa7094e49cfb7e37a84c0aa57c85c64c0581d17
URL:
https://github.com/llvm/llvm-project/commit/cfa7094e49cfb7e37a84c0aa57c85c64c0581d17
DIFF:
https://github.com/llvm/llvm-project/commit/cfa7094e49cfb7e37a84c0aa57c85c64c0581d17.diff
LOG: [RISCV] Add -mtune support
- The goal of this patch is improve option compatible with RISCV-V GCC,
-mcpu support on GCC side will sent patch in next few days.
- -mtune only affect the pipeline model and non-arch/extension related
target feature, e.g. instruction fusion; in td file it called
TuneFeatures, which is introduced by X86 back-end[1].
- -mtune accept all valid option for -mcpu and extra alias processor
option, e.g. `generic`, `rocket` and `sifive-7-series`, the purpose is
option compatible with RISCV-V GCC.
- Processor alias for -mtune will resolve according the current target arch,
rv32 or rv64, e.g. `rocket` will resolve to `rocket-rv32` or `rocket-rv64`.
- Interaction between -mcpu and -mtune:
* -mtune has higher priority than -mcpu for pipeline model and
TuneFeatures.
[1] https://reviews.llvm.org/D85165
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D89025
Added:
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/Basic/Targets/RISCV.h
clang/lib/Driver/ToolChains/Clang.cpp
clang/test/Driver/riscv-cpus.c
clang/test/Misc/target-invalid-cpu-note.c
llvm/include/llvm/Support/RISCVTargetParser.def
llvm/include/llvm/Support/TargetParser.h
llvm/lib/Support/TargetParser.cpp
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index c896ca3ff95c..ab75ac0a65a3 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2768,7 +2768,7 @@ def module_file_info : Flag<["-"], "module-file-info">,
Flags<[DriverOption,CC1O
HelpText<"Provide information about a particular module file">;
def mthumb : Flag<["-"], "mthumb">, Group;
def mtune_EQ : Joined<["-"], "mtune=">, Group,
- HelpText<"Only supported on X86. Otherwise accepted for compatibility with
GCC.">;
+ HelpText<"Only supported on X86 and RISC-V. Otherwise accepted for
compatibility with GCC.">;
def multi__module : Flag<["-"], "multi_module">;
def multiply__defined__unused : Separate<["-"], "multiply_defined_unused">;
def multiply__defined : Separate<["-"], "multiply_defined">;
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 4ba703c8dd1a..5e17b7d51175 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -178,6 +178,17 @@ void RISCV32TargetInfo::fillValidCPUList(
llvm::RISCV::fillValidCPUArchList(Values, false);
}
+bool RISCV32TargetInfo::isValidTuneCPUName(StringRef Name) const {
+ return llvm::RISCV::checkTuneCPUKind(
+ llvm::RISCV::parseTuneCPUKind(Name, false),
+ /*Is64Bit=*/false);
+}
+
+void RISCV32TargetInfo::fillValidTuneCPUList(
+SmallVectorImpl &Values) const {
+ llvm::RISCV::fillValidTuneCPUArchList(Values, false);
+}
+
bool RISCV64TargetInfo::isValidCPUName(StringRef Name) const {
return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name),
/*Is64Bit=*/true);
@@ -187,3 +198,14 @@ void RISCV64TargetInfo::fillValidCPUList(
SmallVectorImpl &Values) const {
llvm::RISCV::fillValidCPUArchList(Values, true);
}
+
+bool RISCV64TargetInfo::isValidTuneCPUName(StringRef Name) const {
+ return llvm::RISCV::checkTuneCPUKind(
+ llvm::RISCV::parseTuneCPUKind(Name, true),
+ /*Is64Bit=*/true);
+}
+
+void RISCV64TargetInfo::fillValidTuneCPUList(
+SmallVectorImpl &Values) const {
+ llvm::RISCV::fillValidTuneCPUArchList(Values, true);
+}
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index 6db526da4c59..a4e6777a11e2 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -106,6 +106,8 @@ class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public
RISCVTargetInfo {
bool isValidCPUName(StringRef Name) const override;
void fillValidCPUList(SmallVectorImpl &Values) const override;
+ bool isValidTuneCPUName(StringRef Name) const override;
+ void fillValidTuneCPUList(SmallVectorImpl &Values) const override;
void setMaxAtomicWidth() override {
MaxAtomicPromoteWidth = 128;
@@ -133,6 +135,8 @@ class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public
RISCVTargetInfo {
bool isValidCPUName(StringRef Name) const override;
void fillValidCPUList(SmallVectorImpl &Values) const override;
+ bool isValidTuneCPUNam
[clang] 5635d2a - [RISCV] Pass -u to linker correctly.
Author: Kito Cheng
Date: 2021-07-14T14:25:02+08:00
New Revision: 5635d2a56dab6dc64d3a3f185d68f676b81dc736
URL:
https://github.com/llvm/llvm-project/commit/5635d2a56dab6dc64d3a3f185d68f676b81dc736
DIFF:
https://github.com/llvm/llvm-project/commit/5635d2a56dab6dc64d3a3f185d68f676b81dc736.diff
LOG: [RISCV] Pass -u to linker correctly.
`-u` is a linker option used to pretend a symbol is undefined,
this option are common used for forcing archive member extraction.
This option should pass to `ld`, and many other toolchain in Clang
like `tools::gnutools` has pass that too.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D105091
Added:
Modified:
clang/lib/Driver/ToolChains/RISCVToolchain.cpp
clang/test/Driver/riscv-args.c
Removed:
diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
index 0b8c52096933d..075c1dc11b210 100644
--- a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
+++ b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
@@ -184,6 +184,7 @@ void RISCV::Linker::ConstructJob(Compilation &C, const
JobAction &JA,
AddLinkerInputs(ToolChain, Inputs, Args, CmdArgs, JA);
Args.AddAllArgs(CmdArgs, options::OPT_L);
+ Args.AddAllArgs(CmdArgs, options::OPT_u);
ToolChain.AddFilePathLibArgs(Args, CmdArgs);
Args.AddAllArgs(CmdArgs,
{options::OPT_T_Group, options::OPT_e, options::OPT_s,
diff --git a/clang/test/Driver/riscv-args.c b/clang/test/Driver/riscv-args.c
index 7b68df977f7c3..305a50885eade 100644
--- a/clang/test/Driver/riscv-args.c
+++ b/clang/test/Driver/riscv-args.c
@@ -1,7 +1,6 @@
// Check the arguments are correctly passed
// Make sure -T is the last with gcc-toolchain option
-// RUN: %clang -### -target riscv32 \
-// RUN: --gcc-toolchain= -Xlinker --defsym=FOO=10 -T a.lds %s 2>&1 \
+// RUN: %clang -### -target riscv32 --gcc-toolchain= -Xlinker --defsym=FOO=10
-T a.lds -u foo %s 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LD %s
-// CHECK-LD: {{.*}} "--defsym=FOO=10" {{.*}} "-T" "a.lds"
+// CHECK-LD: {{.*}} "--defsym=FOO=10" {{.*}} "-u" "foo" {{.*}} "-T" "a.lds"
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[clang] b46a1b1 - [doc] Fix description of _Float16
Author: Kito Cheng Date: 2021-03-04T14:17:54+08:00 New Revision: b46a1b129f684a230dd680341d198d8b11731812 URL: https://github.com/llvm/llvm-project/commit/b46a1b129f684a230dd680341d198d8b11731812 DIFF: https://github.com/llvm/llvm-project/commit/b46a1b129f684a230dd680341d198d8b11731812.diff LOG: [doc] Fix description of _Float16 According to ISO/IEC TS 18661-3:2015 _FloatN is interchange floating point type, extended floating-point type is _FloatNx. http://www.open-std.org/jtc1/sc22/wg14/www/docs/n2342.pdf Reviewed By: SjoerdMeijer Differential revision: https://reviews.llvm.org/D97759 Added: Modified: clang/docs/LanguageExtensions.rst Removed: diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index 4b82b8a6dbbc..4e25abca656a 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -542,7 +542,7 @@ The behavior of ``__fp16`` is specified by the ARM C Language Extensions (`ACLE Clang uses the ``binary16`` format from IEEE 754-2008 for ``__fp16``, not the ARM alternative format. -``_Float16`` is an extended floating-point type. This means that, just like arithmetic on +``_Float16`` is an interchange floating-point type. This means that, just like arithmetic on ``float`` or ``double``, arithmetic on ``_Float16`` operands is formally performed in the ``_Float16`` type, so that e.g. the result of adding two ``_Float16`` values has type ``_Float16``. The behavior of ``_Float16`` is specified by ISO/IEC TS 18661-3:2015 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] ae116f4 - [RISCV] Drop single letter b extension support
Author: Kito Cheng Date: 2022-10-27T23:53:32+08:00 New Revision: ae116f43ff140edfae166370ab6bc9ae3f556710 URL: https://github.com/llvm/llvm-project/commit/ae116f43ff140edfae166370ab6bc9ae3f556710 DIFF: https://github.com/llvm/llvm-project/commit/ae116f43ff140edfae166370ab6bc9ae3f556710.diff LOG: [RISCV] Drop single letter b extension support It splited into several zb* extensions, and `b` is dropped after 0.93, so it time to retired that as other non-ratified zb* extensions. Currntly clang can accept that with warning: $ clang -target riscv64-elf ~/hello.c -S -march=rv64gcb '+b' is not a recognized feature for this target (ignoring feature) '+b' is not a recognized feature for this target (ignoring feature) '+b' is not a recognized feature for this target (ignoring feature) Reviewed By: asb, luismarques Differential Revision: https://reviews.llvm.org/D136812 Added: Modified: clang/test/Driver/riscv-arch.c llvm/lib/Support/RISCVISAInfo.cpp Removed: diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index 7e86423aa157..cf38a3c07051 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -258,6 +258,11 @@ // RV32-STD: error: invalid arch name 'rv32imqc', // RV32-STD: unsupported standard user-level extension 'q' +// RUN: %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \ +// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s +// RV32-B: error: invalid arch name 'rv32ib', +// RV32-B: unsupported standard user-level extension 'b' + // RUN: %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s // RV32X: error: invalid arch name 'rv32xabc', diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 1a899616ade9..cf773dad47b6 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -602,8 +602,8 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, // The order is OK, then push it into features. // TODO: Use version number when setting target features -// Currently LLVM supports only "mafdcbv". -StringRef SupportedStandardExtension = "mafdcbv"; +// Currently LLVM supports only "mafdcv". +StringRef SupportedStandardExtension = "mafdcv"; if (!SupportedStandardExtension.contains(C)) return createStringError(errc::invalid_argument, "unsupported standard user-level extension '%c'", ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] f4c887c - [RISCV] Add H extension
Author: Kito Cheng
Date: 2023-01-10T09:52:03+08:00
New Revision: f4c887c3a8406d85f4f942c8350f10026994f4d8
URL:
https://github.com/llvm/llvm-project/commit/f4c887c3a8406d85f4f942c8350f10026994f4d8
DIFF:
https://github.com/llvm/llvm-project/commit/f4c887c3a8406d85f4f942c8350f10026994f4d8.diff
LOG: [RISCV] Add H extension
`h` was the prefix of multi-letter extension name, but it become a
extension name in later RISC-V isa spec.
Fortunately we don't have any extension really defined is prefixed
with `h`, so we can just change that.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D136817
Added:
llvm/test/MC/RISCV/rv32h-invalid.s
llvm/test/MC/RISCV/rv32ih-aliases-valid.s
llvm/test/MC/RISCV/rv32ih-valid.s
llvm/test/MC/RISCV/rv64h-invalid.s
llvm/test/MC/RISCV/rv64ih-valid.s
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/priv-valid.s
llvm/test/MC/RISCV/rvi-aliases-valid.s
Removed:
llvm/test/MC/RISCV/priv-aliases-valid.s
llvm/test/MC/RISCV/priv-rv64-valid.s
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index c514ad889d0b2..91ab4219ea344 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -46,6 +46,7 @@
// CHECK-NOT: __riscv_xventanacondops
// CHECK-NOT: __riscv_zcd
// CHECK-NOT: __riscv_zcf
+// CHECK-NOT: __riscv_h
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -449,6 +450,12 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s
// CHECK-SVINVAL-EXT: __riscv_svinval 100{{$}}
+// RUN: %clang -target riscv32 -march=rv32ih -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-H-EXT %s
+// RUN: %clang -target riscv64 -march=rv64ih -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-H-EXT %s
+// CHECK-H-EXT: __riscv_h 100{{$}}
+
// RUN: %clang -target riscv64 -march=rv64ixventanacondops -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
// CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 100{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 25dc17d44c89e..3ba0d887ca77e 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -51,6 +51,7 @@ on support follow.
``C``Supported
``D``Supported
``F``Supported
+ ``H``Assembly Support
``M``Supported
``Svinval`` Assembly Support
``Svnapot`` Assembly Support
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 7a55837aa3f80..d82f337feb534 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -37,7 +37,7 @@ struct RISCVSupportedExtension {
} // end anonymous namespace
-static constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvn";
+static constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvnh";
static const RISCVSupportedExtension SupportedExtensions[] = {
{"i", RISCVExtensionVersion{2, 0}},
@@ -48,6 +48,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"d", RISCVExtensionVersion{2, 0}},
{"c", RISCVExtensionVersion{2, 0}},
+{"h", RISCVExtensionVersion{1, 0}},
+
{"zihintpause", RISCVExtensionVersion{2, 0}},
{"zfhmin", RISCVExtensionVersion{1, 0}},
@@ -284,17 +286,14 @@ static int multiLetterExtensionRank(const std::string
&ExtName) {
case 's':
HighOrder = 0;
break;
- case 'h':
-HighOrder = 1;
-break;
case 'z':
-HighOrder = 2;
+HighOrder = 1;
// `z` extension must be sorted by canonical order of second letter.
// e.g. zmx has higher rank than zax.
LowOrder = singleLetterExtensionRank(ExtName[1]);
break;
case 'x':
-HighOrder = 3;
+HighOrder = 2;
break;
default:
llvm_unreachable("Unknown prefix for multi-char extension");
@@ -611,8 +610,8 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
// The order is OK, then push it into features.
// TODO: Use version number when setting target features
-// Currently LLVM supports only "mafdcv".
-StringRef SupportedStandardExtension = "mafdcv";
+// Currently LLVM supports only "mafdcvh".
+StringRef SupportedStandardExtension = "mafdcvh";
if (!SupportedStandardExtension.contains(C))
return createStringError(errc::invalid_argument,
"unsupported standard user-level extension
'%c'",
diff --git a/llvm/lib/Tar
[clang] f601039 - [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march
Author: Kito Cheng
Date: 2023-01-13T23:58:31+08:00
New Revision: f601039e8165cb2a49c783ccf4aafd1f7b326a63
URL:
https://github.com/llvm/llvm-project/commit/f601039e8165cb2a49c783ccf4aafd1f7b326a63
DIFF:
https://github.com/llvm/llvm-project/commit/f601039e8165cb2a49c783ccf4aafd1f7b326a63.diff
LOG: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march
RISC-V supports `-march`, `-mtune`, and `-mcpu`: `-march` provides the
architecture extension information, `-mtune` provide the pipeline model, and
`-mcpu` provides both.
What's the priority among those options for now(w/o this patch)?
Pipeline model:
- Take from `-mtune` if present.
- Take from `-mcpu` if present
- Use the default pipeline model: `generic-rv32` or `generic-rv64`
Architecture extension has quite complicated behavior now:
- Take union from `-march` and `-mcpu` if both are present.
- Take from `-march` if present.
- Take from `-mcpu` if present.
- Implied from `-mabi` if present.
- Use the default architecture depending on the target triple
We treat `-mcpu`/`-mtune` and `-mcpu`/`-march` differently, and it's
kind of counterintuitive: -march is explicitly specified but ignored.
This patch adjusts the priority between `-mcpu`/`-march`, letting it use
architecture extension information from `-march` if it's present.
So the priority of architecture extension information becomes:
- Take from `-march` if present.
- Take from `-mcpu` if present.
- Implied from `-mabi` if present.
- Use the default architecture depending on the target triple
And this also match what we implement in RISC-V GCC too.
Reviewed By: craig.topper, MaskRay
Differential Revision: https://reviews.llvm.org/D140693
Added:
clang/test/Driver/riscv-march-mcpu-mtune.c
Modified:
clang/docs/ReleaseNotes.rst
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/Driver/riscv-cpus.c
clang/test/Driver/riscv-default-features.c
llvm/include/llvm/Support/RISCVISAInfo.h
llvm/lib/Support/RISCVISAInfo.cpp
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 632862aaa0237..92de83bae01cd 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -803,6 +803,9 @@ RISC-V Support in Clang
- ``sifive-7-rv32`` and ``sifive-7-rv64`` are no longer supported for
``-mcpu``.
Use ``sifive-e76``, ``sifive-s76``, or ``sifive-u74`` instead.
- Native detections via ``-mcpu=native`` and ``-mtune=native`` are supported.
+- Fix interaction of ``-mcpu`` and ``-march``, RISC-V backend will take the
+ architecture extension union of ``-mcpu`` and ``-march`` before, and now will
+ take architecture extensions from ``-march`` if both are given.
X86 Support in Clang
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 5c11064d81d59..4c34c09d55895 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -43,7 +43,8 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
}
(*ISAInfo)->toFeatures(
- Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); });
+ Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
+ /*AddAllExtensions=*/true);
return true;
}
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index eb05569f8bc1d..1753251341b61 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -9,12 +9,14 @@
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-base |
FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-BASE %s
// MCPU-SYNTACORE-SCR1-BASE: "-target-cpu" "syntacore-scr1-base"
-// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c" "-target-feature" "-64bit"
+// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "-64bit"
// MCPU-SYNTACORE-SCR1-BASE: "-target-abi" "ilp32"
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr1-max |
FileCheck -check-prefix=MCPU-SYNTACORE-SCR1-MAX %s
// MCPU-SYNTACORE-SCR1-MAX: "-target-cpu" "syntacore-scr1-max"
-// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c"
"-target-feature" "-64bit"
+// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+m" "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "-64bit"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
// We cannot check much for -mcpu=native, but it should be replaced by a valid
CPU string.
@@ -80,42 +82,48 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 |
FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s
// MCPU-ABI-SIFIVE-S21: "-nostdsysteminc" "-target-cpu" "sifive-s21"
// MCPU-ABI-SIFIVE-S21: "-target-feature" "+m" "-target-feature" "+a"
-// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c" "-target-feature" "+64bit"
+//
[clang] [RISCV] Support floating point VCIX (PR #67094)
@@ -2441,11 +2441,11 @@ define void @test_sf_vc_fvv_se_e16mf4( %vd, ; CHECK-NEXT:sf.vc.fvv 1, v8, v9, fa0 ; CHECK-NEXT:ret entry: - tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1i16.f16.iXLen(iXLen 1, %vd, %vs2, half %fs1, iXLen %vl) + tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1i16.i16.iXLen(iXLen 1, %vd, %vs2, half %fs1, iXLen %vl) kito-cheng wrote: Why changed to `i16`? arguments is half, which `f16` should be the right type? https://github.com/llvm/llvm-project/pull/67094 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Support floating point VCIX (PR #67094)
https://github.com/kito-cheng commented: The target is support LLVM IR part only, we would like to prevent expose that on the C intrinsic level if possible, because that's intentionally to expose vector with unsigned integer only. https://github.com/llvm/llvm-project/pull/67094 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Support floating point VCIX (PR #67094)
https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/67094 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)
@@ -2524,11 +2551,32 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) {
ResultRegIsFlagReg.push_back(IsFlagReg);
llvm::Type *Ty = ConvertTypeForMem(QTy);
+ ResultTruncRegTypes.push_back(Ty);
+
+ // Expressing the type as a structure in inline asm calls will complicate
+ // the current code case, so instead, the return type is set to be a
+ // single scalable vector, then reconstructed with `vector.extract` and
+ // `insertvalue`. The type is derived here, and the reconstruction is
done
+ // under EmitAsmStores.
+ if (QTy->isRVVType() && isa(Ty)) {
+// Flatten the structure into a single ScalableVectorType
+auto *STy = cast(Ty);
+assert(STy->containsHomogeneousScalableVectorTypes() &&
+ isa(STy->getElementType(0)) &&
+ "Dealing with RVV tuple (aggregate with homogeneous scalable "
+ "vectors");
+
+auto *VecTy = cast(STy->getElementType(0));
+
+Ty = llvm::ScalableVectorType::get(VecTy->getScalarType(),
+ STy->getNumElements() *
+ VecTy->getMinNumElements());
kito-cheng wrote:
Does it also work well for some types like `vint32m1x3_t`?
https://github.com/llvm/llvm-project/pull/67018
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[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
kito-cheng wrote:
> I believe that setting up this memory and initializing the SCS reg would fall
> under activate the use of Zicfiss..., but I could be wrong.
That suppose initialize SCS register by kernel, more precisely is user space
will invoke some prctl system call to enable SCS and the kernel will allocate
SCS page and then initialize the SCS register then back to user space.
https://github.com/llvm/llvm-project/pull/68075
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[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)
@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB,
CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
return;
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
+ if (STI.hasFeature(RISCV::FeatureStdExtZicfiss)) {
kito-cheng wrote:
> Do we need an enable other than just the feature being in -march? The shadow
> stack pointer has to be set up when the application starts. Is this done by
> the kernel?
>
> My concern is that if your -mcpu supports Zicfiss, but the kernel doesn't,
> this will generate code that doesn't work.
oh, that's good point...let me check how other target do
https://github.com/llvm/llvm-project/pull/68075
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[clang] [NFC][Clang][RISCV] Remove trailing whitespaces in riscv_vector.td (PR #65762)
https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/65762 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 3fe89be - [clang][RISCV][NFC] Prevent data race in RVVType::computeType
Author: Kito Cheng
Date: 2022-11-23T16:59:19+08:00
New Revision: 3fe89be8015955f2e8403f8b7d7580db13cedb2c
URL:
https://github.com/llvm/llvm-project/commit/3fe89be8015955f2e8403f8b7d7580db13cedb2c
DIFF:
https://github.com/llvm/llvm-project/commit/3fe89be8015955f2e8403f8b7d7580db13cedb2c.diff
LOG: [clang][RISCV][NFC] Prevent data race in RVVType::computeType
Introduce a RVVTypeCache to hold the cache instead of using a local
static variable to maintain a cache.
Also made construct of RVVType to private, make sure that could be only
created by a cache manager.
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D138429
Added:
Modified:
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/Sema/SemaRISCVVectorLookup.cpp
clang/lib/Support/RISCVVIntrinsicUtils.cpp
clang/utils/TableGen/RISCVVEmitter.cpp
Removed:
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 4a8bbc78cdee3..8b9f994a4e31a 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -15,7 +15,9 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include
+#include
#include
+#include
#include
namespace llvm {
@@ -182,9 +184,12 @@ struct LMULType {
class RVVType;
using RVVTypePtr = RVVType *;
using RVVTypes = std::vector;
+class RVVTypeCache;
// This class is compact representation of a valid and invalid RVVType.
class RVVType {
+ friend class RVVTypeCache;
+
BasicType BT;
ScalarTypeKind ScalarType = Invalid;
LMULType LMUL;
@@ -204,10 +209,9 @@ class RVVType {
enum class FixedLMULType { LargerThan, SmallerThan };
-public:
- RVVType() : BT(BasicType::Unknown), LMUL(0), Valid(false) {}
RVVType(BasicType BT, int Log2LMUL, const PrototypeDescriptor &Profile);
+public:
// Return the string representation of a type, which is an encoded string for
// passing to the BUILTIN() macro in Builtins.def.
const std::string &getBuiltinStr() const { return BuiltinStr; }
@@ -275,17 +279,25 @@ class RVVType {
void initTypeStr();
// Compute and record a short name of a type for C/C++ name suffix.
void initShortStr();
+};
+
+// This class is used to manage RVVType, RVVType should only created by this
+// class, also provided thread-safe cache capability.
+class RVVTypeCache {
+private:
+ std::unordered_map LegalTypes;
+ std::set IllegalTypes;
public:
/// Compute output and input types by applying
diff erent config (basic type
/// and LMUL with type transformers). It also record result of type in legal
/// or illegal set to avoid compute the same config again. The result maybe
/// have illegal RVVType.
- static llvm::Optional
+ llvm::Optional
computeTypes(BasicType BT, int Log2LMUL, unsigned NF,
llvm::ArrayRef Prototype);
- static llvm::Optional computeType(BasicType BT, int Log2LMUL,
-PrototypeDescriptor Proto);
+ llvm::Optional computeType(BasicType BT, int Log2LMUL,
+ PrototypeDescriptor Proto);
};
enum PolicyScheme : uint8_t {
@@ -373,7 +385,7 @@ class RVVIntrinsic {
std::string getBuiltinTypeStr() const;
static std::string
- getSuffixStr(BasicType Type, int Log2LMUL,
+ getSuffixStr(RVVTypeCache &TypeCache, BasicType Type, int Log2LMUL,
llvm::ArrayRef PrototypeDescriptors);
static llvm::SmallVector
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 4ab393b89d1b9..85bf11e942b96 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -132,6 +132,7 @@ class RISCVIntrinsicManagerImpl : public
sema::RISCVIntrinsicManager {
private:
Sema &S;
ASTContext &Context;
+ RVVTypeCache TypeCache;
// List of all RVV intrinsic.
std::vector IntrinsicList;
@@ -247,16 +248,16 @@ void RISCVIntrinsicManagerImpl::InitIntrinsicList() {
continue;
Optional Types =
-RVVType::computeTypes(BaseType, Log2LMUL, Record.NF, ProtoSeq);
+TypeCache.computeTypes(BaseType, Log2LMUL, Record.NF, ProtoSeq);
// Ignored to create new intrinsic if there are any illegal types.
if (!Types.has_value())
continue;
-std::string SuffixStr =
-RVVIntrinsic::getSuffixStr(BaseType, Log2LMUL, SuffixProto);
+std::string SuffixStr = RVVIntrinsic::getSuffixStr(
+TypeCache, BaseType, Log2LMUL, SuffixProto);
std::string OverloadedSuffixStr = RVVIntrinsic::getSuffixStr(
-BaseType, Log2LMUL, OverloadedSuffixProto);
+TypeCache, BaseType, Log2LMUL, OverloadedSuffixProto);
// Create non-masked intrinsic.
InitRVVIntrinsic(Rec
[libunwind] 9b488ac - [libunwind][RISC-V] Rewrite testcase with C as possible.
Author: Kito Cheng
Date: 2023-03-15T17:30:16+08:00
New Revision: 9b488ace17e6be64e61bf20f8ddc3eb563848bde
URL:
https://github.com/llvm/llvm-project/commit/9b488ace17e6be64e61bf20f8ddc3eb563848bde
DIFF:
https://github.com/llvm/llvm-project/commit/9b488ace17e6be64e61bf20f8ddc3eb563848bde.diff
LOG: [libunwind][RISC-V] Rewrite testcase with C as possible.
Fix #60472
The testcase is writen in all inline asm but it seems not well
maintained for the CFI directive, of cause we can fix that, but this
patch also contain another issue is it use s0 and s1 without
store/restore.
This patch proposed another way to testing that, use inline asm to
generate dummy def and use, so compiler will generate store/restore for
the vector register, and then generate the CFI directives.
Also check __riscv_vector as the testcase guard, because the testcase
will read vlenb which is only available when V or zve* extensions is
present.
Reviewed By: MaskRay, asb, #libunwind
Differential Revision: https://reviews.llvm.org/D145225
Added:
Modified:
libunwind/test/unwind_scalable_vectors.pass.cpp
Removed:
diff --git a/libunwind/test/unwind_scalable_vectors.pass.cpp
b/libunwind/test/unwind_scalable_vectors.pass.cpp
index 250e2c8fc7b1e..a5c5947c870fd 100644
--- a/libunwind/test/unwind_scalable_vectors.pass.cpp
+++ b/libunwind/test/unwind_scalable_vectors.pass.cpp
@@ -13,30 +13,8 @@
#include
#include
-// Check correct unwinding of frame with VLENB-sized objects (vector
registers):
-// 1. Save return address (ra) in temporary register.
-// 2. Load VLENB (vector length in bytes) and substract it from current stack
-//pointer (sp) - equivalent to one vector register on stack frame.
-// 3. Set DWARF cannonical frame address (CFA) to "sp + vlenb" expresssion so
it
-//can be correctly unwinded.
-// 4. Call stepper() function and check that 2 unwind steps are successful -
-//from stepper() into foo() and from foo() into main().
-// 5. Restore stack pointer and return address.
-__attribute__((naked)) static void foo() {
- __asm__(".cfi_startproc\n"
- "mv s0, ra\n"
- "csrr s1, vlenb\n"
- "sub sp, sp, s1\n"
- "# .cfi_def_cfa_expression sp + vlenb\n"
- ".cfi_escape 0x0f, 0x07, 0x72, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x22\n"
- "call stepper\n"
- "add sp, sp, s1\n"
- "mv ra, s0\n"
- "ret\n"
- ".cfi_endproc\n");
-}
-
-extern "C" void stepper() {
+#ifdef __riscv_vector
+__attribute__((noinline)) extern "C" void stepper() {
unw_cursor_t cursor;
unw_context_t uc;
unw_getcontext(&uc);
@@ -47,4 +25,16 @@ extern "C" void stepper() {
assert(unw_step(&cursor) > 0);
}
+// Check correct unwinding of frame with VLENB-sized objects (vector
registers).
+__attribute__((noinline)) static void foo() {
+ __rvv_int32m1_t v;
+ asm volatile("" : "=vr"(v)); // Dummy inline asm to def v.
+ stepper(); // def-use of v has cross the function, so that
+ // will triger spill/reload to/from the stack.
+ asm volatile("" ::"vr"(v)); // Dummy inline asm to use v.
+}
+
int main() { foo(); }
+#else
+int main() { return 0; }
+#endif
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[clang] be437f3 - [clang][RISCV] Enable -fasynchronous-unwind-tables by default on Linux
Author: Kito Cheng
Date: 2023-03-03T16:13:53+08:00
New Revision: be437f3bb8b657f4d2de4603734f24daa624d204
URL:
https://github.com/llvm/llvm-project/commit/be437f3bb8b657f4d2de4603734f24daa624d204
DIFF:
https://github.com/llvm/llvm-project/commit/be437f3bb8b657f4d2de4603734f24daa624d204.diff
LOG: [clang][RISCV] Enable -fasynchronous-unwind-tables by default on Linux
This could improve user experience for stack unwinding, and also this is
enabled by default by X86 and AArch64 and RISC-V GCC.
Reviewed By: luismarques, MaskRay
Differential Revision: https://reviews.llvm.org/D145164
Added:
Modified:
clang/lib/Driver/ToolChains/Gnu.cpp
clang/test/Driver/riscv-features.c
Removed:
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 3a69a2967462e..24fbdcffc07ba 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2900,6 +2900,8 @@ Generic_GCC::getDefaultUnwindTableLevel(const ArgList
&Args) const {
case llvm::Triple::ppcle:
case llvm::Triple::ppc64:
case llvm::Triple::ppc64le:
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
case llvm::Triple::x86:
case llvm::Triple::x86_64:
return UnwindTableLevel::Asynchronous;
diff --git a/clang/test/Driver/riscv-features.c
b/clang/test/Driver/riscv-features.c
index 37b6f8647d49b..98445b1920301 100644
--- a/clang/test/Driver/riscv-features.c
+++ b/clang/test/Driver/riscv-features.c
@@ -26,7 +26,8 @@
// RUN: %clang --target=riscv64-linux -### %s -fsyntax-only 2>&1 \
// RUN: | FileCheck %s -check-prefix=DEFAULT-LINUX
-// DEFAULT-LINUX: "-target-feature" "+m"
+// DEFAULT-LINUX: "-funwind-tables=2"
+// DEFAULT-LINUX-SAME: "-target-feature" "+m"
// DEFAULT-LINUX-SAME: "-target-feature" "+a"
// DEFAULT-LINUX-SAME: "-target-feature" "+f"
// DEFAULT-LINUX-SAME: "-target-feature" "+d"
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[clang] da4fcb0 - [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple.
Author: Kito Cheng
Date: 2023-04-27T14:46:01+08:00
New Revision: da4fcb0c0b281746067f92d8804c18dbce4269bd
URL:
https://github.com/llvm/llvm-project/commit/da4fcb0c0b281746067f92d8804c18dbce4269bd
DIFF:
https://github.com/llvm/llvm-project/commit/da4fcb0c0b281746067f92d8804c18dbce4269bd.diff
LOG: [RISCV][Driver] Allow the use of CPUs with a different XLEN than the
triple.
Our downstream toolchain release got some issue is we set the default
triple by creating symbolic link of clang like `riscv64-unknown-elf-clang`,
and has lots of multi-lib config including rv32's config.
However when we trying to set arch by a 32 bit CPU like generic-rv32
but got error message below:
error: unsupported argument 'generic-rv32' to option '-mcpu='
`generic-rv32` is listed in the output of `-mcpu=help`, that
might be confusing for user since help message say supported.
So let clang driver also consider -mcpu option during computing
the target triple to archvie that.
Reviewed By: asb, craig.topper
Differential Revision: https://reviews.llvm.org/D148124
Added:
Modified:
clang/lib/Driver/Driver.cpp
clang/test/Driver/riscv-arch.c
clang/test/Driver/riscv-cpus.c
Removed:
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 4c8a83e6ff28a..509191762f8b4 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -12,6 +12,7 @@
#include "ToolChains/AMDGPUOpenMP.h"
#include "ToolChains/AVR.h"
#include "ToolChains/Ananas.h"
+#include "ToolChains/Arch/RISCV.h"
#include "ToolChains/BareMetal.h"
#include "ToolChains/CSKYToolChain.h"
#include "ToolChains/Clang.h"
@@ -689,8 +690,9 @@ static llvm::Triple computeTargetTriple(const Driver &D,
// If target is RISC-V adjust the target triple according to
// provided architecture name
if (Target.isRISCV()) {
-if ((A = Args.getLastArg(options::OPT_march_EQ))) {
- StringRef ArchName = A->getValue();
+if (Args.hasArg(options::OPT_march_EQ) ||
+Args.hasArg(options::OPT_mcpu_EQ)) {
+ StringRef ArchName = tools::riscv::getRISCVArch(Args, Target);
if (ArchName.startswith_insensitive("rv32"))
Target.setArch(llvm::Triple::riscv32);
else if (ArchName.startswith_insensitive("rv64"))
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 4d11db2a5e09a..5b9a45deb06a2 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -355,12 +355,20 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
// RUN: %clang --target=riscv64-unknown-elf -march=rv32i -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RUN: %clang --target=riscv32-unknown-elf -mcpu=generic-rv32 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
+// RUN: %clang --target=riscv64-unknown-elf -mcpu=generic-rv32 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-TARGET %s
// RV32-TARGET: "-triple" "riscv32-unknown-unknown-elf"
// RUN: %clang --target=riscv32-unknown-elf -march=rv64i -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
// RUN: %clang --target=riscv64-unknown-elf -march=rv64i -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RUN: %clang --target=riscv32-unknown-elf -mcpu=generic-rv64 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
+// RUN: %clang --target=riscv64-unknown-elf -mcpu=generic-rv64 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s
// RV64-TARGET: "-triple" "riscv64-unknown-unknown-elf"
// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzfh01p0 -### %s \
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index b107d89773e1c..76325311668d8 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -174,6 +174,3 @@
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
// MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
-
-// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv64 | FileCheck
-check-prefix=MISMATCH-MCPU %s
-// MISMATCH-MCPU: error: cpu 'generic-rv64' does not support rv32
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[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)
kito-cheng wrote: RISC-V GCC has enabled `-fasynchronous-unwind-tables` and `-funwind-tables` by default for Linux target, and disabled by default for baremetal, so generally LGTM since it align the behavior with GCC, but I would like to wait @asb's response. NOTE: The patch[1] is come from SUSE folks, so I assume it's necessary from the distro's point of view. Ref: [1] https://github.com/gcc-mirror/gcc/commit/3cd08f7168c196d7a481b9ed9f4289fd1f14eea8 https://github.com/llvm/llvm-project/pull/81727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames()
const {
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
// CSRs
- "fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
+ "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"
kito-cheng wrote:
`sf.vcix_state`?
https://github.com/llvm/llvm-project/pull/106914
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[clang] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/kito-cheng approved this pull request. LGTM, and I would prefer wait one more LGTM from Craig or Philip *OR* wait one more week to make sure no further comment :) https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [RISCV][compiler-rt] Update __init_riscv_feature_bits prototype (PR #101472)
https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/101472 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
@@ -5554,6 +5554,17 @@ them if they use them.
}];
}
+def RISCVVLSCCDocs : Documentation {
+ let Category = DocCatCallingConvs;
+ let Heading = "riscv::vls_cc, riscv_vls_cc, clang::riscv_vls_cc";
+ let Content = [{
+The ``riscv_vls_cc`` attribute can be applied to a function. Functions
+declared with this attribute will utilize the standard fixed-length vector
+calling convention variant instead of the default calling convention defined by
+the ABI. This variant aims to pass fixed-length vectors via vector registers,
+if possible, rather than through general-purpose registers.}];
kito-cheng wrote:
Yes
https://github.com/llvm/llvm-project/pull/100346
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[clang] [llvm] [RISCV][VLS] Support RISCV VLS calling convention (PR #100346)
@@ -317,38 +323,45 @@ ABIArgInfo
RISCVABIInfo::coerceAndExpandFPCCEligibleStruct(
// Fixed-length RVV vectors are represented as scalable vectors in function
// args/return and must be coerced from fixed vectors.
-ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty) const {
+ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty,
+ unsigned ArgABIVLen) const {
assert(Ty->isVectorType() && "expected vector type!");
const auto *VT = Ty->castAs();
assert(VT->getElementType()->isBuiltinType() && "expected builtin type!");
- auto VScale =
- getContext().getTargetInfo().getVScaleRange(getContext().getLangOpts());
-
unsigned NumElts = VT->getNumElements();
- llvm::Type *EltType;
- if (VT->getVectorKind() == VectorKind::RVVFixedLengthMask) {
-NumElts *= 8;
-EltType = llvm::Type::getInt1Ty(getVMContext());
+ llvm::ScalableVectorType *ResType;
+ llvm::Type *EltType = CGT.ConvertType(VT->getElementType());
+
+ if (ArgABIVLen == 0) {
+// RVV fixed-length vector
+auto VScale =
+
getContext().getTargetInfo().getVScaleRange(getContext().getLangOpts());
+
+if (VT->getVectorKind() == VectorKind::RVVFixedLengthMask) {
+ NumElts *= 8;
+ EltType = llvm::Type::getInt1Ty(getVMContext());
+}
+
+// The MinNumElts is simplified from equation:
+// NumElts / VScale =
+// (EltSize * NumElts / (VScale * RVVBitsPerBlock))
+//* (RVVBitsPerBlock / EltSize)
+ResType = llvm::ScalableVectorType::get(EltType, NumElts / VScale->first);
} else {
-assert(VT->getVectorKind() == VectorKind::RVVFixedLengthData &&
- "Unexpected vector kind");
-EltType = CGT.ConvertType(VT->getElementType());
+// Generic vector
+ResType = llvm::ScalableVectorType::get(
+EltType, NumElts * llvm::RISCV::RVVBitsPerBlock / ArgABIVLen);
kito-cheng wrote:
> Do we need to round up odd number of elements?
> What about Zve32 where isn't a legal type in the backend?
> Does the backend widen that?
> What about vectors of double on Zve64f or Zve64x? Vectors of double and i64
> on Zve32?
Take, this 3 questions should address on the psABI side I think
https://github.com/llvm/llvm-project/pull/100346
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[clang] [RISCV] Disallow target attribute use in multiversioning (PR #85899)
https://github.com/kito-cheng approved this pull request. LGTM :) https://github.com/llvm/llvm-project/pull/85899 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Zimop/Zcmop are ratified (PR #87966)
https://github.com/kito-cheng approved this pull request. LGTM :) https://github.com/llvm/llvm-project/pull/87966 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add B extension (PR #76893)
kito-cheng wrote: It passed public review[1] and merged into riscv-isa-manual[2], so I think it's time to mark it as 1.0 and moving forward :) [1] https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/KetVUCQkfK4/m/Y3Dbd2pvAAAJ?utm_medium=email&utm_source=footer [2] https://github.com/riscv/riscv-isa-manual/commit/cdb25859bcce5a6edbdc34914c1f86f079b3fddd https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add B extension (PR #76893)
kito-cheng wrote: Could you add `B` into CombinedExtsEntry and added a test for that? https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add B extension (PR #76893)
kito-cheng wrote: Jeff told me it's still need wait TSC vote for the ratification, anyway it will ratify this month. https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)
kito-cheng wrote: Could you give few more word on the description to mention we missed that in the vector crpyto intrinsic proposal, and it's fixing but rather than incompatible/breaking change for the intrinsic API? https://github.com/llvm/llvm-project/pull/94318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Update vcpop.v C interface to follow the nameing convention (PR #94318)
https://github.com/kito-cheng approved this pull request. https://github.com/llvm/llvm-project/pull/94318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add B extension (PR #76893)
@@ -920,8 +920,8 @@ void RISCVISAInfo::updateImplication() {
}
static constexpr StringLiteral CombineIntoExts[] = {
-{"zk"},{"zkn"}, {"zks"}, {"zvkn"}, {"zvknc"},
-{"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+{"b"}, {"zk"},{"zkn"}, {"zks"}, {"zvkn"},
kito-cheng wrote:
Remove this from `CombineIntoExts` may cause `__riscv_b` become less useful I
think?
https://github.com/llvm/llvm-project/pull/76893
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[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)
kito-cheng wrote: `llvm/docs/RISCVUsage.rst` need update https://github.com/llvm/llvm-project/pull/88474 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)
@@ -119,6 +119,7 @@ on support follow. ``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) ``Za64rs``Supported (`See note <#riscv-profiles-extensions-note>`__) ``Zacas`` Supported (`See note <#riscv-zacas-note>`__) + ``Zama16b`` Supported kito-cheng wrote: ```suggestion ``Zama16b`` Supported (`See note <#riscv-profiles-extensions-note>`__) ``` https://github.com/llvm/llvm-project/pull/88474 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)
https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/88474 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Support RVV bfloat16 C intrinsics (PR #89354)
kito-cheng wrote: vfncvtbf16.c, vfwcvtbf16.c and vfwmaccbf16.c already in the LLVM repo, so I think those files could removed from this PR? https://github.com/llvm/llvm-project/pull/89354 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Support RVV bfloat16 C intrinsics (PR #89354)
kito-cheng wrote: > Oh, I forgot to remove them. Or do you think they should be moved to bfloat > folder to make them consistent? Remove files from this PR, that should be a separated NFC PR for moving those files, but I am fine to keep those file in same place :) https://github.com/llvm/llvm-project/pull/89354 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Support RVV bfloat16 C intrinsics (PR #89354)
https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/89354 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)
@@ -138,6 +155,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
/// initializeProperties().
RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
+ RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
+
kito-cheng wrote:
I guess it little bit same situation like those macro extensions, so what if
user manually specify all extension present in certain profile? does it will
detect right when invoke `getRISCVProfile`?
https://github.com/llvm/llvm-project/pull/84877
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[clang] [RISCV][FMV] Support target_clones (PR #85786)
kito-cheng wrote:
A test case will crash, missing `+` before `zbc`:
```
__attribute__((target_clones("default", "arch=+zbb,zbc;priority=-1",
"priority=-2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo1(void) { return
2; }
int bar() { return foo1(); }
```
```
$ clang -cc1 -triple riscv64-linux-gnu -target-feature +i -emit-llvm foo.c
clang:
/home/kitoc/llvm-workspace/llvm-project/llvm/lib/TargetParser/RISCVISAInfo.cpp:455:
static llvm::Expected >
llvm::RISCVISAInfo::parseFeatures(unsigned int, const
std::vector >&): Assertion `ExtName.size() > 1
&& (ExtName[0] == '+' || ExtName[0] == '-')' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and
include the crash backtrace, preprocessed source, and associated run script.
Stack dump:
0. Program arguments: ./bin/clang -cc1 -triple riscv64-linux-gnu
-target-feature +i -emit-llvm attr-target-clones-riscv.c
1. attr-target-clones-riscv.c:7:1: current parser token 'int'
2. attr-target-clones-riscv.c:4:130: LLVM IR generation of declaration
'foo1'
3. attr-target-clones-riscv.c:4:130: Generating code for declaration 'foo1'
#0 0x7f4ed63e00d0 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int)
(/scratch/kitoc/llvm-workspace/build-upstream/bin/../lib/libLLVMSupport.so.20.0git+0x1e00d0)
...
#11 0x7f4eda71a854 llvm::RISCVISAInfo::parseFeatures(unsigned int,
std::vector,
std::allocator>, std::allocator, std::allocator>>> const&)
(/scratch/kitoc/llvm-workspace/build-upstream/bin/../lib/libLLVMTargetParser.so.20.0git+0x3d854)
#12 0x7f4ed825b8e0
clang::targets::RISCVTargetInfo::initFeatureMap(llvm::StringMap&, clang::DiagnosticsEngine&, llvm::StringRef,
std::vector,
std::allocator>, std::allocator, std::allocator>>> const&) const
(/scratch/kitoc/llvm-workspace/build-upstream/bin/../lib/libclangBasic.so.20.0git+0x45b8e0)
...
Aborted (core dumped)
```
https://github.com/llvm/llvm-project/pull/85786
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[clang] [Clang][RISCV] Recognize unsupport target feature by supporting... (PR #106495)
@@ -391,7 +391,14 @@ void RISCVTargetInfo::fillValidTuneCPUList(
static void handleFullArchString(StringRef FullArchStr,
std::vector &Features) {
- Features.push_back("__RISCV_TargetAttrNeedOverride");
+
+ // Should be full arch string.
+ if (!FullArchStr.starts_with("rv")) {
+Features.push_back(FullArchStr.str());
kito-cheng wrote:
I am little confused about this part, comment say it should be full arch
string, but the check come with `!`?
https://github.com/llvm/llvm-project/pull/106495
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[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
kito-cheng wrote: I would suggest it should prefix with a vendor prefix, either `sf.vcix_state` or `sifive.vcix_state`, also go `riscv-c-api-doc` or `riscv-toolchain-conventions` :) https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)
kito-cheng wrote: > Do you mean change the current vcix_state register to sf.vcix_state? Yes, because it's SiFive specific register, other vendor may add other status register like VCIX in future, so I would like to add prefix to make sure all further similar stuff will follow same rule if possible https://github.com/llvm/llvm-project/pull/106914 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Work-in-Progress][Clang][RISCV] Create supporting intrinsics around RVV BFloat16 type (PR #72463)
https://github.com/kito-cheng closed https://github.com/llvm/llvm-project/pull/72463 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Work-in-Progress][Clang][RISCV] Create supporting intrinsics around RVV BFloat16 type (PR #72463)
kito-cheng wrote: Done by https://github.com/llvm/llvm-project/pull/71140 https://github.com/llvm/llvm-project/pull/72463 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add -m[no-]scalar-strict-align and -m[no-]vector-strict-align. (PR #95024)
https://github.com/kito-cheng approved this pull request. LGTM :) https://github.com/llvm/llvm-project/pull/95024 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISC-V] Remove experimental for Zicfiss/Zicfilp. (PR #98891)
kito-cheng wrote: `llvm/docs/RISCVUsage.rst` and `llvm/docs/ReleaseNotes.rst` need update :) https://github.com/llvm/llvm-project/pull/98891 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add smstateen extension (PR #90818)
https://github.com/kito-cheng commented: Don't forgot `llvm/docs/RISCVUsage.rst`, otherwise LGTM :P https://github.com/llvm/llvm-project/pull/90818 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Remove unneeded multiply in RISCV CodeGenTypes (PR #92644)
https://github.com/kito-cheng approved this pull request. https://github.com/llvm/llvm-project/pull/92644 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] Introduce `SemaRISCV` (PR #92682)
https://github.com/kito-cheng approved this pull request. LGTM as the original author of `SemaRISCVVectorLookup.cpp` :) It's great to see we can put all RISC-V related stuff within same place rather than many different files. https://github.com/llvm/llvm-project/pull/92682 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] [RISCV] Allow libunwind to build for rv32e (PR #98855)
https://github.com/kito-cheng closed https://github.com/llvm/llvm-project/pull/98855 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 079d136 - [RISCV] Fix the include search path order between sysroot and resource folder
Author: Kito Cheng
Date: 2022-02-21T14:06:47+08:00
New Revision: 079d13668bf1b7f929f1897af90f64caae41c81d
URL:
https://github.com/llvm/llvm-project/commit/079d13668bf1b7f929f1897af90f64caae41c81d
DIFF:
https://github.com/llvm/llvm-project/commit/079d13668bf1b7f929f1897af90f64caae41c81d.diff
LOG: [RISCV] Fix the include search path order between sysroot and resource
folder
Resource folder[1] should include before sysroot[2] in general (Linux clang
toolchain, BareMetal clang toolchain, and GCC using that order), and that
prevent sysroot's header file override resource folder's one, this change is
reference from BareMetal::addclangsystemincludea...@baremetal.cpp[3].
And also fix the behavior of `-nobuiltininc`.
[1] Include path from resource folder is something like this:
`/lib/clang/13.0.0/include/`
[2] Include path from sysroot is something like this:
`/riscv32-unknown-elf/include`
[3]
https://github.com/llvm/llvm-project/blob/llvmorg-13.0.1/clang/lib/Driver/ToolChains/BareMetal.cpp#L193
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D119837
Added:
clang/test/Driver/Inputs/resource_dir/include/.keep
Modified:
clang/lib/Driver/ToolChains/RISCVToolchain.cpp
clang/test/Driver/riscv32-toolchain.c
clang/test/Driver/riscv64-toolchain.c
Removed:
diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
index 714325a2db39e..a63ada0cbb7e4 100644
--- a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
+++ b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
@@ -98,6 +98,12 @@ void RISCVToolChain::AddClangSystemIncludeArgs(const ArgList
&DriverArgs,
if (DriverArgs.hasArg(options::OPT_nostdinc))
return;
+ if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) {
+SmallString<128> Dir(getDriver().ResourceDir);
+llvm::sys::path::append(Dir, "include");
+addSystemInclude(DriverArgs, CC1Args, Dir.str());
+ }
+
if (!DriverArgs.hasArg(options::OPT_nostdlibinc)) {
SmallString<128> Dir(computeSysRoot());
llvm::sys::path::append(Dir, "include");
diff --git a/clang/test/Driver/Inputs/resource_dir/include/.keep
b/clang/test/Driver/Inputs/resource_dir/include/.keep
new file mode 100644
index 0..e69de29bb2d1d
diff --git a/clang/test/Driver/riscv32-toolchain.c
b/clang/test/Driver/riscv32-toolchain.c
index fb262a19a0439..c480a7c00a367 100644
--- a/clang/test/Driver/riscv32-toolchain.c
+++ b/clang/test/Driver/riscv32-toolchain.c
@@ -197,6 +197,20 @@
// C-RV32-RTLIB-COMPILERRT-ILP32: "--start-group" "-lc" "-lgloss"
"--end-group" "{{.*}}libclang_rt.builtins-riscv32.a"
// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtend-riscv32.o"
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
+// RUN: -resource-dir=%s/Inputs/resource_dir 2>&1 \
+// RUN: | FileCheck -check-prefix=RESOURCE-INC %s
+// RESOURCE-INC: "-internal-isystem" "{{.*}}/Inputs/resource_dir/include"
+// RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv32_tree/{{.*}}/riscv32-unknown-elf/include"
+
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
+// RUN: -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
+// RUN: | FileCheck -check-prefix=NO-RESOURCE-INC %s
+// NO-RESOURCE-INC-NOT: "-internal-isystem"
"{{.*}}/Inputs/resource_dir/include"
+// NO-RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv32_tree/{{.*}}/riscv32-unknown-elf/include"
+
// RUN: %clang -target riscv32 %s -emit-llvm -S -o - | FileCheck %s
typedef __builtin_va_list va_list;
diff --git a/clang/test/Driver/riscv64-toolchain.c
b/clang/test/Driver/riscv64-toolchain.c
index 2774e004854c3..91358298ecdd8 100644
--- a/clang/test/Driver/riscv64-toolchain.c
+++ b/clang/test/Driver/riscv64-toolchain.c
@@ -153,6 +153,20 @@
// C-RV64-RTLIB-COMPILERRT-LP64: "--start-group" "-lc" "-lgloss" "--end-group"
"{{.*}}libclang_rt.builtins-riscv64.a"
// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtend-riscv64.o"
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
+// RUN: -resource-dir=%s/Inputs/resource_dir 2>&1 \
+// RUN: | FileCheck -check-prefix=RESOURCE-INC %s
+// RESOURCE-INC: "-internal-isystem" "{{.*}}/Inputs/resource_dir/include"
+// RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv64_tree/{{.*}}/riscv64-unknown-elf/include"
+
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
+// RUN: -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
+// RUN: | FileCheck -check-prefix=NO-RESOURCE-INC %s
+// NO-RESOURCE-INC-NOT: "-internal-isystem" "{{.*}}Inputs/resource_dir/include"
+// NO-RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv64_tree/{{.*}}/
[clang] 0a17ee1 - Revert "[RISCV] Fix the include search path order between sysroot and resource folder"
Author: Kito Cheng
Date: 2022-02-21T14:25:49+08:00
New Revision: 0a17ee1ebe0c3384520ea14fdc1d33e38217341a
URL:
https://github.com/llvm/llvm-project/commit/0a17ee1ebe0c3384520ea14fdc1d33e38217341a
DIFF:
https://github.com/llvm/llvm-project/commit/0a17ee1ebe0c3384520ea14fdc1d33e38217341a.diff
LOG: Revert "[RISCV] Fix the include search path order between sysroot and
resource folder"
This reverts commit 079d13668bf1b7f929f1897af90f64caae41c81d.
Added:
Modified:
clang/lib/Driver/ToolChains/RISCVToolchain.cpp
clang/test/Driver/riscv32-toolchain.c
clang/test/Driver/riscv64-toolchain.c
Removed:
clang/test/Driver/Inputs/resource_dir/include/.keep
diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
index a63ada0cbb7e4..714325a2db39e 100644
--- a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
+++ b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
@@ -98,12 +98,6 @@ void RISCVToolChain::AddClangSystemIncludeArgs(const ArgList
&DriverArgs,
if (DriverArgs.hasArg(options::OPT_nostdinc))
return;
- if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) {
-SmallString<128> Dir(getDriver().ResourceDir);
-llvm::sys::path::append(Dir, "include");
-addSystemInclude(DriverArgs, CC1Args, Dir.str());
- }
-
if (!DriverArgs.hasArg(options::OPT_nostdlibinc)) {
SmallString<128> Dir(computeSysRoot());
llvm::sys::path::append(Dir, "include");
diff --git a/clang/test/Driver/Inputs/resource_dir/include/.keep
b/clang/test/Driver/Inputs/resource_dir/include/.keep
deleted file mode 100644
index e69de29bb2d1d..0
diff --git a/clang/test/Driver/riscv32-toolchain.c
b/clang/test/Driver/riscv32-toolchain.c
index c480a7c00a367..fb262a19a0439 100644
--- a/clang/test/Driver/riscv32-toolchain.c
+++ b/clang/test/Driver/riscv32-toolchain.c
@@ -197,20 +197,6 @@
// C-RV32-RTLIB-COMPILERRT-ILP32: "--start-group" "-lc" "-lgloss"
"--end-group" "{{.*}}libclang_rt.builtins-riscv32.a"
// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtend-riscv32.o"
-// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
-// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
-// RUN: -resource-dir=%s/Inputs/resource_dir 2>&1 \
-// RUN: | FileCheck -check-prefix=RESOURCE-INC %s
-// RESOURCE-INC: "-internal-isystem" "{{.*}}/Inputs/resource_dir/include"
-// RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv32_tree/{{.*}}/riscv32-unknown-elf/include"
-
-// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
-// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
-// RUN: -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
-// RUN: | FileCheck -check-prefix=NO-RESOURCE-INC %s
-// NO-RESOURCE-INC-NOT: "-internal-isystem"
"{{.*}}/Inputs/resource_dir/include"
-// NO-RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv32_tree/{{.*}}/riscv32-unknown-elf/include"
-
// RUN: %clang -target riscv32 %s -emit-llvm -S -o - | FileCheck %s
typedef __builtin_va_list va_list;
diff --git a/clang/test/Driver/riscv64-toolchain.c
b/clang/test/Driver/riscv64-toolchain.c
index 91358298ecdd8..2774e004854c3 100644
--- a/clang/test/Driver/riscv64-toolchain.c
+++ b/clang/test/Driver/riscv64-toolchain.c
@@ -153,20 +153,6 @@
// C-RV64-RTLIB-COMPILERRT-LP64: "--start-group" "-lc" "-lgloss" "--end-group"
"{{.*}}libclang_rt.builtins-riscv64.a"
// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtend-riscv64.o"
-// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
-// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
-// RUN: -resource-dir=%s/Inputs/resource_dir 2>&1 \
-// RUN: | FileCheck -check-prefix=RESOURCE-INC %s
-// RESOURCE-INC: "-internal-isystem" "{{.*}}/Inputs/resource_dir/include"
-// RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv64_tree/{{.*}}/riscv64-unknown-elf/include"
-
-// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
-// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
-// RUN: -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
-// RUN: | FileCheck -check-prefix=NO-RESOURCE-INC %s
-// NO-RESOURCE-INC-NOT: "-internal-isystem" "{{.*}}Inputs/resource_dir/include"
-// NO-RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv64_tree/{{.*}}/riscv64-unknown-elf/include"
-
// RUN: %clang -target riscv64 %s -emit-llvm -S -o - | FileCheck %s
typedef __builtin_va_list va_list;
___
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[clang] 47b1fa5 - [RISCV] Fix the include search path order between sysroot and resource folder (Recommit)
Author: Kito Cheng
Date: 2022-02-21T14:39:43+08:00
New Revision: 47b1fa5fc48821eefefd157ed4af2f2cf3bacef4
URL:
https://github.com/llvm/llvm-project/commit/47b1fa5fc48821eefefd157ed4af2f2cf3bacef4
DIFF:
https://github.com/llvm/llvm-project/commit/47b1fa5fc48821eefefd157ed4af2f2cf3bacef4.diff
LOG: [RISCV] Fix the include search path order between sysroot and resource
folder (Recommit)
Resource folder[1] should include before sysroot[2] in general (Linux clang
toolchain, BareMetal clang toolchain, and GCC using that order), and that
prevent sysroot's header file override resource folder's one, this change is
reference from BareMetal::addclangsystemincludea...@baremetal.cpp[3].
And also fix the behavior of `-nobuiltininc`.
[1] Include path from resource folder is something like this:
`/lib/clang/13.0.0/include/`
[2] Include path from sysroot is something like this:
`/riscv32-unknown-elf/include`
[3]
https://github.com/llvm/llvm-project/blob/llvmorg-13.0.1/clang/lib/Driver/ToolChains/BareMetal.cpp#L193
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D119837
The recommit fixes the Windows build failure due to path issue.
Added:
clang/test/Driver/Inputs/resource_dir/include/.keep
Modified:
clang/lib/Driver/ToolChains/RISCVToolchain.cpp
clang/test/Driver/riscv32-toolchain.c
clang/test/Driver/riscv64-toolchain.c
Removed:
diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
index 714325a2db39e..a63ada0cbb7e4 100644
--- a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
+++ b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
@@ -98,6 +98,12 @@ void RISCVToolChain::AddClangSystemIncludeArgs(const ArgList
&DriverArgs,
if (DriverArgs.hasArg(options::OPT_nostdinc))
return;
+ if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) {
+SmallString<128> Dir(getDriver().ResourceDir);
+llvm::sys::path::append(Dir, "include");
+addSystemInclude(DriverArgs, CC1Args, Dir.str());
+ }
+
if (!DriverArgs.hasArg(options::OPT_nostdlibinc)) {
SmallString<128> Dir(computeSysRoot());
llvm::sys::path::append(Dir, "include");
diff --git a/clang/test/Driver/Inputs/resource_dir/include/.keep
b/clang/test/Driver/Inputs/resource_dir/include/.keep
new file mode 100644
index 0..e69de29bb2d1d
diff --git a/clang/test/Driver/riscv32-toolchain.c
b/clang/test/Driver/riscv32-toolchain.c
index fb262a19a0439..25aaca78dab2c 100644
--- a/clang/test/Driver/riscv32-toolchain.c
+++ b/clang/test/Driver/riscv32-toolchain.c
@@ -197,6 +197,20 @@
// C-RV32-RTLIB-COMPILERRT-ILP32: "--start-group" "-lc" "-lgloss"
"--end-group" "{{.*}}libclang_rt.builtins-riscv32.a"
// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtend-riscv32.o"
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
+// RUN: -resource-dir=%s/Inputs/resource_dir 2>&1 \
+// RUN: | FileCheck -check-prefix=RESOURCE-INC %s
+// RESOURCE-INC: "-internal-isystem"
"{{.*}}/Inputs/resource_dir{{/|}}include"
+// RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv32_tree/{{.*}}/riscv32-unknown-elf{{/|}}include"
+
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
+// RUN: -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
+// RUN: | FileCheck -check-prefix=NO-RESOURCE-INC %s
+// NO-RESOURCE-INC-NOT: "-internal-isystem"
"{{.*}}/Inputs/resource_dir{{/|}}include"
+// NO-RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv32_tree/{{.*}}/riscv32-unknown-elf{{/|}}include"
+
// RUN: %clang -target riscv32 %s -emit-llvm -S -o - | FileCheck %s
typedef __builtin_va_list va_list;
diff --git a/clang/test/Driver/riscv64-toolchain.c
b/clang/test/Driver/riscv64-toolchain.c
index 2774e004854c3..91358298ecdd8 100644
--- a/clang/test/Driver/riscv64-toolchain.c
+++ b/clang/test/Driver/riscv64-toolchain.c
@@ -153,6 +153,20 @@
// C-RV64-RTLIB-COMPILERRT-LP64: "--start-group" "-lc" "-lgloss" "--end-group"
"{{.*}}libclang_rt.builtins-riscv64.a"
// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtend-riscv64.o"
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
+// RUN: -resource-dir=%s/Inputs/resource_dir 2>&1 \
+// RUN: | FileCheck -check-prefix=RESOURCE-INC %s
+// RESOURCE-INC: "-internal-isystem" "{{.*}}/Inputs/resource_dir/include"
+// RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv64_tree/{{.*}}/riscv64-unknown-elf/include"
+
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
+// RUN: -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
+// RUN: | FileCheck -check-prefix=NO-RESOURCE-INC %s
+// NO-RESOURCE-INC-NOT: "-internal-isystem"
[clang] cc27952 - Revert "[RISCV] Fix the include search path order between sysroot and resource folder (Recommit)"
Author: Kito Cheng
Date: 2022-02-21T14:56:58+08:00
New Revision: cc279529e8317301492f9625b6acc9a0bf52db56
URL:
https://github.com/llvm/llvm-project/commit/cc279529e8317301492f9625b6acc9a0bf52db56
DIFF:
https://github.com/llvm/llvm-project/commit/cc279529e8317301492f9625b6acc9a0bf52db56.diff
LOG: Revert "[RISCV] Fix the include search path order between sysroot and
resource folder (Recommit)"
This reverts commit 47b1fa5fc48821eefefd157ed4af2f2cf3bacef4.
Added:
Modified:
clang/lib/Driver/ToolChains/RISCVToolchain.cpp
clang/test/Driver/riscv32-toolchain.c
clang/test/Driver/riscv64-toolchain.c
Removed:
clang/test/Driver/Inputs/resource_dir/include/.keep
diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
index a63ada0cbb7e4..714325a2db39e 100644
--- a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
+++ b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
@@ -98,12 +98,6 @@ void RISCVToolChain::AddClangSystemIncludeArgs(const ArgList
&DriverArgs,
if (DriverArgs.hasArg(options::OPT_nostdinc))
return;
- if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) {
-SmallString<128> Dir(getDriver().ResourceDir);
-llvm::sys::path::append(Dir, "include");
-addSystemInclude(DriverArgs, CC1Args, Dir.str());
- }
-
if (!DriverArgs.hasArg(options::OPT_nostdlibinc)) {
SmallString<128> Dir(computeSysRoot());
llvm::sys::path::append(Dir, "include");
diff --git a/clang/test/Driver/Inputs/resource_dir/include/.keep
b/clang/test/Driver/Inputs/resource_dir/include/.keep
deleted file mode 100644
index e69de29bb2d1d..0
diff --git a/clang/test/Driver/riscv32-toolchain.c
b/clang/test/Driver/riscv32-toolchain.c
index 25aaca78dab2c..fb262a19a0439 100644
--- a/clang/test/Driver/riscv32-toolchain.c
+++ b/clang/test/Driver/riscv32-toolchain.c
@@ -197,20 +197,6 @@
// C-RV32-RTLIB-COMPILERRT-ILP32: "--start-group" "-lc" "-lgloss"
"--end-group" "{{.*}}libclang_rt.builtins-riscv32.a"
// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtend-riscv32.o"
-// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
-// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
-// RUN: -resource-dir=%s/Inputs/resource_dir 2>&1 \
-// RUN: | FileCheck -check-prefix=RESOURCE-INC %s
-// RESOURCE-INC: "-internal-isystem"
"{{.*}}/Inputs/resource_dir{{/|}}include"
-// RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv32_tree/{{.*}}/riscv32-unknown-elf{{/|}}include"
-
-// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
-// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
-// RUN: -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
-// RUN: | FileCheck -check-prefix=NO-RESOURCE-INC %s
-// NO-RESOURCE-INC-NOT: "-internal-isystem"
"{{.*}}/Inputs/resource_dir{{/|}}include"
-// NO-RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv32_tree/{{.*}}/riscv32-unknown-elf{{/|}}include"
-
// RUN: %clang -target riscv32 %s -emit-llvm -S -o - | FileCheck %s
typedef __builtin_va_list va_list;
diff --git a/clang/test/Driver/riscv64-toolchain.c
b/clang/test/Driver/riscv64-toolchain.c
index 91358298ecdd8..2774e004854c3 100644
--- a/clang/test/Driver/riscv64-toolchain.c
+++ b/clang/test/Driver/riscv64-toolchain.c
@@ -153,20 +153,6 @@
// C-RV64-RTLIB-COMPILERRT-LP64: "--start-group" "-lc" "-lgloss" "--end-group"
"{{.*}}libclang_rt.builtins-riscv64.a"
// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtend-riscv64.o"
-// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
-// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
-// RUN: -resource-dir=%s/Inputs/resource_dir 2>&1 \
-// RUN: | FileCheck -check-prefix=RESOURCE-INC %s
-// RESOURCE-INC: "-internal-isystem" "{{.*}}/Inputs/resource_dir/include"
-// RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv64_tree/{{.*}}/riscv64-unknown-elf/include"
-
-// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
-// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
-// RUN: -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
-// RUN: | FileCheck -check-prefix=NO-RESOURCE-INC %s
-// NO-RESOURCE-INC-NOT: "-internal-isystem" "{{.*}}Inputs/resource_dir/include"
-// NO-RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv64_tree/{{.*}}/riscv64-unknown-elf/include"
-
// RUN: %clang -target riscv64 %s -emit-llvm -S -o - | FileCheck %s
typedef __builtin_va_list va_list;
___
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[clang] c1f17b0 - [RISCV] Fix the include search path order between sysroot and resource folder (Recommit again)
Author: Kito Cheng
Date: 2022-02-21T15:25:21+08:00
New Revision: c1f17b0a9ea0d467eaa9589cc28db2787efe3ebf
URL:
https://github.com/llvm/llvm-project/commit/c1f17b0a9ea0d467eaa9589cc28db2787efe3ebf
DIFF:
https://github.com/llvm/llvm-project/commit/c1f17b0a9ea0d467eaa9589cc28db2787efe3ebf.diff
LOG: [RISCV] Fix the include search path order between sysroot and resource
folder (Recommit again)
Resource folder[1] should include before sysroot[2] in general (Linux clang
toolchain, BareMetal clang toolchain, and GCC using that order), and that
prevent sysroot's header file override resource folder's one, this change is
reference from BareMetal::addclangsystemincludea...@baremetal.cpp[3].
And also fix the behavior of `-nobuiltininc`.
[1] Include path from resource folder is something like this:
`/lib/clang/13.0.0/include/`
[2] Include path from sysroot is something like this:
`/riscv32-unknown-elf/include`
[3]
https://github.com/llvm/llvm-project/blob/llvmorg-13.0.1/clang/lib/Driver/ToolChains/BareMetal.cpp#L193
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D119837
The recommit fixes the Windows build failure due to path issue.
Added:
clang/test/Driver/Inputs/resource_dir/include/.keep
Modified:
clang/lib/Driver/ToolChains/RISCVToolchain.cpp
clang/test/Driver/riscv32-toolchain.c
clang/test/Driver/riscv64-toolchain.c
Removed:
diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
index 714325a2db39e..a63ada0cbb7e4 100644
--- a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
+++ b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp
@@ -98,6 +98,12 @@ void RISCVToolChain::AddClangSystemIncludeArgs(const ArgList
&DriverArgs,
if (DriverArgs.hasArg(options::OPT_nostdinc))
return;
+ if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) {
+SmallString<128> Dir(getDriver().ResourceDir);
+llvm::sys::path::append(Dir, "include");
+addSystemInclude(DriverArgs, CC1Args, Dir.str());
+ }
+
if (!DriverArgs.hasArg(options::OPT_nostdlibinc)) {
SmallString<128> Dir(computeSysRoot());
llvm::sys::path::append(Dir, "include");
diff --git a/clang/test/Driver/Inputs/resource_dir/include/.keep
b/clang/test/Driver/Inputs/resource_dir/include/.keep
new file mode 100644
index 0..e69de29bb2d1d
diff --git a/clang/test/Driver/riscv32-toolchain.c
b/clang/test/Driver/riscv32-toolchain.c
index fb262a19a0439..50859aaccd7da 100644
--- a/clang/test/Driver/riscv32-toolchain.c
+++ b/clang/test/Driver/riscv32-toolchain.c
@@ -197,6 +197,20 @@
// C-RV32-RTLIB-COMPILERRT-ILP32: "--start-group" "-lc" "-lgloss"
"--end-group" "{{.*}}libclang_rt.builtins-riscv32.a"
// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtend-riscv32.o"
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
+// RUN: -resource-dir=%s/Inputs/resource_dir 2>&1 \
+// RUN: | FileCheck -check-prefix=RESOURCE-INC %s
+// RESOURCE-INC: "-internal-isystem"
"{{.*}}/Inputs/resource_dir{{/|}}include"
+// RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv32_tree{{.*}}riscv32-unknown-elf{{/|}}include"
+
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
+// RUN: -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
+// RUN: | FileCheck -check-prefix=NO-RESOURCE-INC %s
+// NO-RESOURCE-INC-NOT: "-internal-isystem"
"{{.*}}/Inputs/resource_dir{{/|}}include"
+// NO-RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv32_tree/{{.*}}riscv32-unknown-elf{{/|}}include"
+
// RUN: %clang -target riscv32 %s -emit-llvm -S -o - | FileCheck %s
typedef __builtin_va_list va_list;
diff --git a/clang/test/Driver/riscv64-toolchain.c
b/clang/test/Driver/riscv64-toolchain.c
index 2774e004854c3..59580370c0b34 100644
--- a/clang/test/Driver/riscv64-toolchain.c
+++ b/clang/test/Driver/riscv64-toolchain.c
@@ -153,6 +153,20 @@
// C-RV64-RTLIB-COMPILERRT-LP64: "--start-group" "-lc" "-lgloss" "--end-group"
"{{.*}}libclang_rt.builtins-riscv64.a"
// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtend-riscv64.o"
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
+// RUN: -resource-dir=%s/Inputs/resource_dir 2>&1 \
+// RUN: | FileCheck -check-prefix=RESOURCE-INC %s
+// RESOURCE-INC: "-internal-isystem"
"{{.*}}/Inputs/resource_dir{{/|}}include"
+// RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv64_tree/{{.*}}riscv64-unknown-elf{{/|}}include"
+
+// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
+// RUN: -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
+// RUN: | FileCheck -check-prefix=NO-RESOURCE-INC %s
+// NO-RESOURCE-INC-NOT
[clang] 071a9b7 - [NFC][RISCV] Fix path checking issue if default sysroot is given
Author: Kito Cheng
Date: 2022-02-21T20:43:51+08:00
New Revision: 071a9b751a46205dc276069dfbc0d38582736990
URL:
https://github.com/llvm/llvm-project/commit/071a9b751a46205dc276069dfbc0d38582736990
DIFF:
https://github.com/llvm/llvm-project/commit/071a9b751a46205dc276069dfbc0d38582736990.diff
LOG: [NFC][RISCV] Fix path checking issue if default sysroot is given
Added:
Modified:
clang/test/Driver/riscv32-toolchain.c
clang/test/Driver/riscv64-toolchain.c
Removed:
diff --git a/clang/test/Driver/riscv32-toolchain.c
b/clang/test/Driver/riscv32-toolchain.c
index 50859aaccd7da..5d65a2e0acd36 100644
--- a/clang/test/Driver/riscv32-toolchain.c
+++ b/clang/test/Driver/riscv32-toolchain.c
@@ -198,14 +198,14 @@
// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtend-riscv32.o"
// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
-// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree --sysroot= \
// RUN: -resource-dir=%s/Inputs/resource_dir 2>&1 \
// RUN: | FileCheck -check-prefix=RESOURCE-INC %s
// RESOURCE-INC: "-internal-isystem"
"{{.*}}/Inputs/resource_dir{{/|}}include"
// RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv32_tree{{.*}}riscv32-unknown-elf{{/|}}include"
// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \
-// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree --sysroot= \
// RUN: -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
// RUN: | FileCheck -check-prefix=NO-RESOURCE-INC %s
// NO-RESOURCE-INC-NOT: "-internal-isystem"
"{{.*}}/Inputs/resource_dir{{/|}}include"
diff --git a/clang/test/Driver/riscv64-toolchain.c
b/clang/test/Driver/riscv64-toolchain.c
index 59580370c0b34..deb8d077ea9e7 100644
--- a/clang/test/Driver/riscv64-toolchain.c
+++ b/clang/test/Driver/riscv64-toolchain.c
@@ -154,14 +154,14 @@
// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtend-riscv64.o"
// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
-// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree --sysroot= \
// RUN: -resource-dir=%s/Inputs/resource_dir 2>&1 \
// RUN: | FileCheck -check-prefix=RESOURCE-INC %s
// RESOURCE-INC: "-internal-isystem"
"{{.*}}/Inputs/resource_dir{{/|}}include"
// RESOURCE-INC: "-internal-isystem"
"{{.*}}/basic_riscv64_tree/{{.*}}riscv64-unknown-elf{{/|}}include"
// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \
-// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree \
+// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree --sysroot= \
// RUN: -resource-dir=%s/Inputs/resource_dir -nobuiltininc 2>&1 \
// RUN: | FileCheck -check-prefix=NO-RESOURCE-INC %s
// NO-RESOURCE-INC-NOT: "-internal-isystem"
"{{.*}}Inputs/resource_dir{{/|}}include"
___
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