[PATCH] D49754: Add -m(no-)spe, and e500 CPU definitions and support to clang
kthomsen added a comment.
@vit9696 I'm working since 3 days on that issue, and found nothing...
PPCISelLowering.cpp has 2 functions: LowerVASTART() and LowerVAARG().
LowerVASTART is correctly called (store the GPR to the internal va_list
structure), but LowerVAARG is never called and I don't understand why. The
generated code is exactly what the LowerVAARG source is shown, but it must be
generated somewhere else.
The Problem is the following:
The calling function is correctly placing the double date into a register pair
(r5/r6 or r7/r8). In the function all registers (GPR) are placed on the stack
(by LowerVASTART) and it reserves space for the FPU registers to save (which
SPE don't have and therefore this space is left empty). The va_arg is now
getting the double parameter from that FPU area (it has an offset of 32 to the
GPR space), but not from the GPR space.
I am searching for that code generation. I'm 99% sure LowerVAARG can generate
that code, but 100% sure that LowerVAARG is not called. Therefore, where is the
va_arg loading generated?
My test code:
typedef __builtin_va_list va_list;
double a;
long l = 0;
void pr(char *txt, ...)
{
va_list vp;
__builtin_va_start(vp,txt);
a = __builtin_va_arg(vp,double);
l = __builtin_va_arg(vp,long);
__builtin_va_end(vp);
}
@vit9696 if you like, you can contact me directly, so that we can coordinate
our work on the SPE. thom...@microsys.de
Kei
Repository:
rC Clang
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[PATCH] D49754: Add -m(no-)spe, and e500 CPU definitions and support to clang
kthomsen added a comment. The desired function for this va_arg is not in lib/Target/PowerPC/*.cpp, it is in tools/clang/lib/CodeGen/TargetInfo.cpp , a little bit unexpected to me. PPC32_SVR4_ABIInfo::EmitVAArg() is doing the va_arg handling. For testing, I have added a hasSPE = true and treat the parameter like SoftFloat. It looks good! Now I need to find out, where to get "hasSPE" from. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D49754/new/ https://reviews.llvm.org/D49754 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D49754: Add -m(no-)spe, and e500 CPU definitions and support to clang
kthomsen added a comment.
With this modification for SPE in VAARG, I was now able to compile all OS-9
libraries for SPE and tested them with whetstone. The results of the whetstone
are the same like with a real FPU and they are correctly shown with printf.
Also the performance of CLANG is about 30% better than with my old compiler.
Therefore, the modification in tools/clang/lib/CodeGen/TargetInfo.cpp line 9322
case llvm::Triple::ppc:
return SetCGInfo(
new PPC32TargetCodeGenInfo(Types, (CodeGenOpts.FloatABI == "soft") ||
getTarget().hasFeature("spe")));
case llvm::Triple::ppc64:
Helps to get the va_arg() parameter correctly. We should not rename the
isSoftFloatABI to something else, because this is just one line of code change
compared to >12 lines. Also the naming is still correct and not really
confusing.
Conclusion: the SPE is now at a level, where it can be used completely.
Repository:
rC Clang
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