[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-08 Thread Kamau Bridgeman via cfe-commits 


@@ -1,11 +1,16 @@
-// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s| FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s | FileCheck %s \
+// RUN:   --check-prefix=CHECK-X86
+// RUN: %clang_cc1 -triple ppc64le-linux-gnu -emit-llvm < %s | FileCheck %s \
+// RUN:   --check-prefix=CHECK-PPC
+
+#ifndef __PPC__

kamaub wrote:


why not use `// REQUIRES: x86-registered-target`

https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-08 Thread Kamau Bridgeman via cfe-commits 

https://github.com/kamaub edited https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-08 Thread Kamau Bridgeman via cfe-commits 

https://github.com/kamaub deleted 
https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-08 Thread Kamau Bridgeman via cfe-commits 


@@ -210,6 +210,12 @@ let TargetPrefix = "ppc" in {  // All intrinsics start 
with "llvm.ppc.".
 [llvm_float_ty],
 [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_vararg_ty],
 [IntrNoMem]>;
+  // Load of a value provided by the system library at a fixed address. Used 
for
+  // accessing things like HWCAP word provided by GLIBC.

kamaub wrote:

```suggestion
// This intrinsic is provided to allow back ends to emit load
// instructions that load a value from a fixed address. The
// parameter to the intrinsic is not an address, but an
// immediate index into an enumeration that contains the
// union of all such values available on all back ends.
// An example is the HWCAP/HWCAP2/CPUID words
// provided by GLIBC on PowerPC to allow fast access
// to commonly used parts of AUXV. These are provided
// at a fixed offset into the TCB (accessible through the
// thread pointer).
```
Missing expanded comment from previous round of reviews in 
https://reviews.llvm.org/D152914

https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-08 Thread Kamau Bridgeman via cfe-commits 


@@ -0,0 +1,80 @@
+#ifndef PPC_FEATURE

kamaub wrote:

Missing file description similar to the `head` of 
`clang/include/clang/Basic/Builtins.def`

https://github.com/llvm/llvm-project/pull/68919
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[clang] [Clang] Warn on deprecated specializations used in system headers. (PR #70353)

2023-11-27 Thread Kamau Bridgeman via cfe-commits 

kamaub wrote:

This patch exposes the use of deprecated specializations in the third-party 
Google Test suite built via this buildbot 
https://lab.llvm.org/staging/#/builders/104/builds/106/steps/6/logs/stdio. The 
bot ordinality isn't in staging, it is there temporary while we test and update 
its configuration and intend to move it back to the main server once it builds 
libcxx and libcxxabi cleanly.

Can you provide any insight on how to resolve these warning? Would 
specifying`-Wno-deprecated-declarations>` specified in the gtest 
`CMakeList.txt` appropriate to temporarily handle them until the third-party 
unittest can be updated?

https://github.com/llvm/llvm-project/pull/70353
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[clang] de39566 - [PowerPC] Fix popcntb XL Compat Builtin for 32bit

2021-07-15 Thread Kamau Bridgeman via cfe-commits 

Author: Quinn Pham
Date: 2021-07-15T13:19:47-05:00
New Revision: de3956605a701295c928925a3e5096008a8521ba

URL: 
https://github.com/llvm/llvm-project/commit/de3956605a701295c928925a3e5096008a8521ba
DIFF: 
https://github.com/llvm/llvm-project/commit/de3956605a701295c928925a3e5096008a8521ba.diff

LOG: [PowerPC] Fix popcntb XL Compat Builtin for 32bit

This patch implements the `__popcntb` XL compatibility builtin for 32bit in the 
frontend and backend. This patch also updates tests for `__popcntb` and other 
XL Compat sync related builtins.

Reviewed By: #powerpc, nemanjai, amyk

Differential Revision: https://reviews.llvm.org/D105360

Added: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll

Modified: 
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll

Removed: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll



diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 67f57015e49fd..0635be425e0aa 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15600,6 +15600,12 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
   case PPC::BI__builtin_ppc_ldarx:
   case PPC::BI__builtin_ppc_lwarx:
 return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
+  case PPC::BI__builtin_ppc_popcntb: {
+Value *ArgValue = EmitScalarExpr(E->getArg(0));
+llvm::Type *ArgType = ArgValue->getType();
+Function *F = CGM.getIntrinsic(Intrinsic::ppc_popcntb, {ArgType, ArgType});
+return Builder.CreateCall(F, Ops, "popcntb");
+  }
   }
 }
 

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-sync.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
index 6413f34fbc410..aaf3622a543a2 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
@@ -1,260 +1,471 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
-// RUN:-emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
-// RUN:   -emit-llvm %s -o -  -target-cpu pwr8 | FileCheck %s
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s 
--check-prefix=CHECK-32
+
+extern unsigned long a;
+extern const void *b;
+extern void *c;
 
-void test_popcntb() {
 // CHECK-LABEL: @test_popcntb(
 // CHECK-NEXT:  entry:
- 
-  unsigned long a;
-  unsigned long b = __popcntb(a);
-// CHECK: %1 = call i64 @llvm.ppc.popcntb(i64 %0)
+// CHECK-NEXT:[[TMP0:%.*]] = load i64, i64* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
+// CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 
[[TMP0]])
+// CHECK-NEXT:ret i64 [[POPCNTB]]
+//
+// CHECK-32-LABEL: @test_popcntb(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:[[TMP0:%.*]] = load i32, i32* @a, align 4
+// CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
+// CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 
[[TMP0]])
+// CHECK-32-NEXT:ret i32 [[POPCNTB]]
+//
+unsigned long test_popcntb() {
+  return __popcntb(a);
 }
 
-void test_eieio() {
 // CHECK-LABEL: @test_eieio(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:call void @llvm.ppc.eieio()
+// CHECK-NEXT:ret void
+//
+// CHECK-32-LABEL: @test_eieio(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:call void @llvm.ppc.eieio()
+// CHECK-32-NEXT:ret void
+//
+void test_eieio() {
   __eieio();
-// CHECK: call void @llvm.ppc.eieio()
 }
 
-void test_iospace_eieio() {
 // CHECK-LABEL: @test_iospace_eieio(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:call void @llvm.ppc.iospace.eieio()
+// CHECK-NEXT:ret void
+//
+// CHECK-32-LABEL: @test_iospace_eieio(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:call void @llvm.ppc.iospace.eieio()
+// CHECK-32-NEXT:ret void
+//
+void test_iospace_eieio() {
   __iospace_eieio();
-// CHECK: call void @llvm.ppc.iospace.eieio()
 }
 
-void test_isync() {
 // CHECK-LABEL: @test_isync(
-// CHECK-NEXT: entry:
-
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:call void @llvm.ppc.isync()
+// CHECK-NEXT:ret void
+//
+// CHECK-32-LABEL: @test_isync(
+// CHECK-32-NEXT:  entry:
+// CHECK-32-NEXT:call void

[clang] 0268e12 - [PowerPC] swdiv_nochk Builtins for XL Compat

2021-07-19 Thread Kamau Bridgeman via cfe-commits 

Author: Quinn Pham
Date: 2021-07-19T16:51:10-05:00
New Revision: 0268e123bea5bbfe64c625203cfe3b159e85b2dc

URL: 
https://github.com/llvm/llvm-project/commit/0268e123bea5bbfe64c625203cfe3b159e85b2dc
DIFF: 
https://github.com/llvm/llvm-project/commit/0268e123bea5bbfe64c625203cfe3b159e85b2dc.diff

LOG: [PowerPC] swdiv_nochk Builtins for XL Compat

This patch is in a series of patches to provide builtins for
compatibility with the XL compiler. This patch adds software divide
builtins with no checking. These builtins are each emitted as a fast
fdiv.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D106150

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 1c83c59e1623..a3665e2a7754 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -73,6 +73,8 @@ BUILTIN(__builtin_ppc_fctiw, "dd", "")
 BUILTIN(__builtin_ppc_fctiwz, "dd", "")
 BUILTIN(__builtin_ppc_fctudz, "dd", "")
 BUILTIN(__builtin_ppc_fctuwz, "dd", "")
+BUILTIN(__builtin_ppc_swdiv_nochk, "ddd", "")
+BUILTIN(__builtin_ppc_swdivs_nochk, "fff", "")
 // Compare
 BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "")
 BUILTIN(__builtin_ppc_cmprb, "iCIiii", "")

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 10af8494c44e..e22cbd8a13f7 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -166,6 +166,8 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__fnmsubs", "__builtin_ppc_fnmsubs");
   Builder.defineMacro("__fre", "__builtin_ppc_fre");
   Builder.defineMacro("__fres", "__builtin_ppc_fres");
+  Builder.defineMacro("__swdiv_nochk", "__builtin_ppc_swdiv_nochk");
+  Builder.defineMacro("__swdivs_nochk", "__builtin_ppc_swdivs_nochk");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 7e90751b2647..89e22ab75d4c 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15629,6 +15629,15 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_mtfsf);
 return Builder.CreateCall(F, {Ops[0], Cast}, "");
   }
+
+  case PPC::BI__builtin_ppc_swdiv_nochk:
+  case PPC::BI__builtin_ppc_swdivs_nochk: {
+FastMathFlags FMF = Builder.getFastMathFlags();
+Builder.getFastMathFlags().setFast();
+Value *FDiv = Builder.CreateFDiv(Ops[0], Ops[1], "swdiv_nochk");
+Builder.getFastMathFlags() &= (FMF);
+return FDiv;
+  }
   }
 }
 

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c
new file mode 100644
index ..63ce65b74d1b
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c
@@ -0,0 +1,100 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern double a;
+extern double b;
+extern double c;
+extern float d;
+extern float e;
+extern float f;
+
+// CHECK-LABEL: @test_swdiv_nochk(
+// CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV_NOCHK]]
+//
+double test_swdiv_nochk() {
+  return __swdiv_nochk(a, b);
+}
+
+// CHECK-LABEL: @test_swdivs_nochk(
+// CHECK:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIV_NOCHK]]
+//
+float test_swdivs_nochk() {
+  return __swdivs_nochk(d, e);
+}
+
+// CHECK-LABEL: @test_flags_swdiv_nochk(
+// CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load double, double* @c, align 8
+// CHECK-NEXT:[[ADD:%.*]] = fadd double [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret double [[ADD]]
+//
+double test_flags_swdiv_nochk() {
+  return __swdiv_nochk(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_swdivs_nochk(
+// CHECK:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, alig

[clang] fd855c2 - [PowerPC] Restore FastMathFlags of Builder for Vector FDiv Builtins

2021-07-20 Thread Kamau Bridgeman via cfe-commits 

Author: Quinn Pham
Date: 2021-07-20T09:41:00-05:00
New Revision: fd855c24c72ce01573d726317acaaefc9809d9dc

URL: 
https://github.com/llvm/llvm-project/commit/fd855c24c72ce01573d726317acaaefc9809d9dc
DIFF: 
https://github.com/llvm/llvm-project/commit/fd855c24c72ce01573d726317acaaefc9809d9dc.diff

LOG: [PowerPC] Restore FastMathFlags of Builder for Vector FDiv Builtins

This patch fixes `__builtin_ppc_recipdivf`, `__builtin_ppc_recipdivd`,
`__builtin_ppc_rsqrtf`, and `__builtin_ppc_rsqrtd`. FastMathFlags are
set to fast immediately before emitting these builtins. Now the flags
are restored to their previous values after the builtins are emitted.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D105984

Added: 
clang/test/CodeGen/builtins-ppc-fastmath.c

Modified: 
clang/lib/CodeGen/CGBuiltin.cpp

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index d9958fe527cb..44aabfd47735 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15280,6 +15280,7 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
   case PPC::BI__builtin_ppc_recipdivd:
   case PPC::BI__builtin_ppc_rsqrtf:
   case PPC::BI__builtin_ppc_rsqrtd: {
+FastMathFlags FMF = Builder.getFastMathFlags();
 Builder.getFastMathFlags().setFast();
 llvm::Type *ResultType = ConvertType(E->getType());
 Value *X = EmitScalarExpr(E->getArg(0));
@@ -15287,11 +15288,15 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 if (BuiltinID == PPC::BI__builtin_ppc_recipdivf ||
 BuiltinID == PPC::BI__builtin_ppc_recipdivd) {
   Value *Y = EmitScalarExpr(E->getArg(1));
-  return Builder.CreateFDiv(X, Y, "recipdiv");
+  Value *FDiv = Builder.CreateFDiv(X, Y, "recipdiv");
+  Builder.getFastMathFlags() &= (FMF);
+  return FDiv;
 }
 auto *One = ConstantFP::get(ResultType, 1.0);
 llvm::Function *F = CGM.getIntrinsic(Intrinsic::sqrt, ResultType);
-return Builder.CreateFDiv(One, Builder.CreateCall(F, X), "rsqrt");
+Value *FDiv = Builder.CreateFDiv(One, Builder.CreateCall(F, X), "rsqrt");
+Builder.getFastMathFlags() &= (FMF);
+return FDiv;
   }
   case PPC::BI__builtin_ppc_alignx: {
 ConstantInt *AlignmentCI = cast(Ops[0]);

diff  --git a/clang/test/CodeGen/builtins-ppc-fastmath.c 
b/clang/test/CodeGen/builtins-ppc-fastmath.c
new file mode 100644
index ..5e7aa55715ce
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-fastmath.c
@@ -0,0 +1,70 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern vector float a;
+extern vector float b;
+extern vector float c;
+extern vector double d;
+extern vector double e;
+extern vector double f;
+
+// CHECK-LABEL: @test_flags_recipdivf(
+// CHECK:[[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP3:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[RECIPDIV:%.*]] = fdiv fast <4 x float> [[TMP2]], [[TMP3]]
+// CHECK-NEXT:[[TMP4:%.*]] = load <4 x float>, <4 x float>* @c, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <4 x float> [[RECIPDIV]], [[TMP4]]
+// CHECK-NEXT:ret <4 x float> [[ADD]]
+//
+vector float test_flags_recipdivf() {
+  return __builtin_ppc_recipdivf(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_recipdivd(
+// CHECK:[[TMP0:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP3:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[RECIPDIV:%.*]] = fdiv fast <2 x double> [[TMP2]], [[TMP3]]
+// CHECK-NEXT:[[TMP4:%.*]] = load <2 x double>, <2 x double>* @f, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <2 x double> [[RECIPDIV]], [[TMP4]]
+// CHECK-NEXT:ret <2 x double> [[ADD]]
+//
+vector double test_flags_recipdivd() {
+  return __builtin_ppc_recipdivd(d, e) + f;
+}
+
+// CHECK-LABEL: @test_flags_rsqrtf(
+// CHECK:[[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x

[clang] 59d2ba2 - [PowerPC] Semachecking for XL compat builtin icbt

2021-07-20 Thread Kamau Bridgeman via cfe-commits 

Author: Quinn Pham
Date: 2021-07-20T11:05:22-05:00
New Revision: 59d2ba2a3de976798a82cfd9d66e426907480ecf

URL: 
https://github.com/llvm/llvm-project/commit/59d2ba2a3de976798a82cfd9d66e426907480ecf
DIFF: 
https://github.com/llvm/llvm-project/commit/59d2ba2a3de976798a82cfd9d66e426907480ecf.diff

LOG: [PowerPC] Semachecking for XL compat builtin icbt

This patch is in a series of patches to provide builtins for compatibility with 
the XL compiler.
This patch adds semachecking for an already implemented builtin, `__icbt`. 
`__icbt` is only
valid for Power8 and up.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D105834

Added: 
clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c

Modified: 
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll

Removed: 




diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index e6f79227979dc..1b39393eb5e98 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3433,6 +3433,9 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
 return SemaBuiltinConstantArgPower2(TheCall, 0);
   case PPC::BI__builtin_ppc_rdlam:
 return SemaValueIsRunOfOnes(TheCall, 2);
+  case PPC::BI__builtin_ppc_icbt:
+return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions",
+diag::err_ppc_builtin_only_on_arch, "8");
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
new file mode 100644
index 0..c57302d996005
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
@@ -0,0 +1,33 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
+// RUN: %clang_cc1 -triple powerpc-unknown-aix %s -emit-llvm %s \
+// RUN:   -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
+// RUN: not %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN:   -target-cpu pwr7 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
+// RUN: not %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr7 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
+// RUN: not %clang_cc1 -triple powerpc-unknown-aix %s -emit-llvm %s \
+// RUN:   -target-cpu pwr7 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
+
+extern void *a;
+
+void test_icbt() {
+// CHECK-LABEL: @test_icbt(
+
+  __icbt(a);
+// CHECK-PWR8: call void @llvm.ppc.icbt(i8* %0)
+// CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs
+}
+
+void test_builtin_ppc_icbt() {
+// CHECK-LABEL: @test_builtin_ppc_icbt(
+
+  __builtin_ppc_icbt(a);
+// CHECK-PWR8: call void @llvm.ppc.icbt(i8* %0)
+// CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs
+}

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-sync.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
index 1aeec57151b7c..cd35222ca35ad 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
@@ -1,4 +1,3 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
@@ -14,15 +13,13 @@ extern const void *b;
 extern void *c;
 
 // CHECK-LABEL: @test_popcntb(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = load i64, i64* @a, align 8
+// CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 
[[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_popcntb(
-// CHECK-32-NEXT:  entry:
-// CHECK-32-NEXT:[[TMP0:%.*]] = load i32, i32* @a, align 4
+// CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 
[[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
@@ -32,13 +29,11 @@ unsigned long test_popcntb() {
 }
 
 // CHECK-LABEL: @test_eieio(
-/

[clang] 99639e5 - Enabling the detection of devtoolset-11 toolchain.

2022-05-17 Thread Kamau Bridgeman via cfe-commits 

Author: Kamau Bridgeman
Date: 2022-05-17T07:57:45-05:00
New Revision: 99639e5a3e6e7f3f207128fc3bfd707596d5ba59

URL: 
https://github.com/llvm/llvm-project/commit/99639e5a3e6e7f3f207128fc3bfd707596d5ba59
DIFF: 
https://github.com/llvm/llvm-project/commit/99639e5a3e6e7f3f207128fc3bfd707596d5ba59.diff

LOG: Enabling the detection of devtoolset-11 toolchain.

This patch allows systems to build the llvm-project with the devtoolset-11
toolchain.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D125499

Added: 


Modified: 
clang/lib/Driver/ToolChains/Gnu.cpp

Removed: 




diff  --git a/clang/lib/Driver/ToolChains/Gnu.cpp 
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 183828dcaa734..003a97e2c3ebb 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2150,7 +2150,9 @@ void 
Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes(
   // Non-Solaris is much simpler - most systems just go with "/usr".
   if (SysRoot.empty() && TargetTriple.getOS() == llvm::Triple::Linux) {
 // Yet, still look for RHEL/CentOS devtoolsets and gcc-toolsets.
+Prefixes.push_back("/opt/rh/gcc-toolset-11/root/usr");
 Prefixes.push_back("/opt/rh/gcc-toolset-10/root/usr");
+Prefixes.push_back("/opt/rh/devtoolset-11/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-10/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-9/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-8/root/usr");



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[clang] 8328966 - [PowerPC] Fix to guard fetch and cas 64-bit builtin versions

2021-10-04 Thread Kamau Bridgeman via cfe-commits 

Author: Kamau Bridgeman
Date: 2021-10-04T14:45:36-05:00
New Revision: 83289665200b6b9212e0ff14e274b2c431a2e1fa

URL: 
https://github.com/llvm/llvm-project/commit/83289665200b6b9212e0ff14e274b2c431a2e1fa
DIFF: 
https://github.com/llvm/llvm-project/commit/83289665200b6b9212e0ff14e274b2c431a2e1fa.diff

LOG: [PowerPC] Fix to guard fetch and cas 64-bit builtin versions

The builtins: `__compare_and_swaplp`, `__fetch_and_addlp`,
` __fetch_and_andlp`, `__fetch_and_orlp`, `__fetch_and_swaplp` are
64 bit only. This patch ensures the compiler produces an error in 32 bit mode.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D110824

Added: 


Modified: 
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-error.c

Removed: 




diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 207b28ec5972..a6d26ac65465 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3297,6 +3297,11 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
   case PPC::BI__builtin_ppc_addex:
   case PPC::BI__builtin_darn:
   case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_ppc_compare_and_swaplp:
+  case PPC::BI__builtin_ppc_fetch_and_addlp:
+  case PPC::BI__builtin_ppc_fetch_and_andlp:
+  case PPC::BI__builtin_ppc_fetch_and_orlp:
+  case PPC::BI__builtin_ppc_fetch_and_swaplp:
 return true;
   }
   return false;

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
index f1c577cf846f..9fc218b1de41 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -104,6 +104,25 @@ int test_darn() {
 int test_darn_raw() {
   return __darn_raw(); //expected-error {{this builtin is only available on 
64-bit targets}}
 }
+
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c); // expected-error {{this builtin is 
only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_addlp(long a, long b) {
+  __fetch_and_addlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {
+  __fetch_and_andlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {
+  __fetch_and_orlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_swaplp(unsigned long a, unsigned long b) {
+  __fetch_and_swaplp(&a, b); // expected-error {{this builtin is only 
available on 64-bit targets}}
+}
 #endif
 
 unsigned long test_mfspr(void) {



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[clang] 8737c74 - [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units

2021-10-05 Thread Kamau Bridgeman via cfe-commits 

Author: Kamau Bridgeman
Date: 2021-10-05T07:59:32-05:00
New Revision: 8737c74fab3aee833d85b7d235d2c47ebb4eed2e

URL: 
https://github.com/llvm/llvm-project/commit/8737c74fab3aee833d85b7d235d2c47ebb4eed2e
DIFF: 
https://github.com/llvm/llvm-project/commit/8737c74fab3aee833d85b7d235d2c47ebb4eed2e.diff

LOG: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units

This patch allows the use of __vector_quad and __vector_pair, PPC MMA builtin
types, on all PowerPC 64-bit compilation units. When these types are
made available the builtins that use them automatically become available
so semantic checking for mma and pair vector memop __builtins is also
expanded to ensure these builtin function call are only allowed on
Power10 and new architectures. All related test cases are updated to
ensure test coverage.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D109599

Added: 
clang/test/Sema/ppc-mma-builtins.c
clang/test/Sema/ppc-paired-vector-builtins.c

Modified: 
clang/include/clang/Sema/Sema.h
clang/lib/AST/ASTContext.cpp
clang/lib/Sema/Sema.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/AST/ast-dump-ppc-types.c
clang/test/CodeGen/ppc-mma-types.c
clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
llvm/test/CodeGen/PowerPC/mma-acc-memops.ll

Removed: 




diff  --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index a85e53a9a69e8..0a68f6f71b8e7 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -12705,7 +12705,8 @@ class Sema final {
 int ArgNum, unsigned ExpectedFieldNum,
 bool AllowName);
   bool SemaBuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall);
-  bool SemaBuiltinPPCMMACall(CallExpr *TheCall, const char *TypeDesc);
+  bool SemaBuiltinPPCMMACall(CallExpr *TheCall, unsigned BuiltinID,
+ const char *TypeDesc);
 
   bool CheckPPCMMAType(QualType Type, SourceLocation TypeLoc);
 

diff  --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index e2ebe737fdfdc..d1fd3ce061415 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -1444,13 +1444,10 @@ void ASTContext::InitBuiltinTypes(const TargetInfo 
&Target,
 #include "clang/Basic/AArch64SVEACLETypes.def"
   }
 
-  if (Target.getTriple().isPPC64() &&
-  Target.hasFeature("paired-vector-memops")) {
-if (Target.hasFeature("mma")) {
+  if (Target.getTriple().isPPC64()) {
 #define PPC_VECTOR_MMA_TYPE(Name, Id, Size) \
   InitBuiltinType(Id##Ty, BuiltinType::Id);
 #include "clang/Basic/PPCTypes.def"
-}
 #define PPC_VECTOR_VSX_TYPE(Name, Id, Size) \
 InitBuiltinType(Id##Ty, BuiltinType::Id);
 #include "clang/Basic/PPCTypes.def"

diff  --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index d260a45867e06..cf8dcbb6fc3ef 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -403,13 +403,10 @@ void Sema::Initialize() {
 #include "clang/Basic/AArch64SVEACLETypes.def"
   }
 
-  if (Context.getTargetInfo().getTriple().isPPC64() &&
-  Context.getTargetInfo().hasFeature("paired-vector-memops")) {
-if (Context.getTargetInfo().hasFeature("mma")) {
+  if (Context.getTargetInfo().getTriple().isPPC64()) {
 #define PPC_VECTOR_MMA_TYPE(Name, Id, Size) \
   addImplicitTypedef(#Name, Context.Id##Ty);
 #include "clang/Basic/PPCTypes.def"
-}
 #define PPC_VECTOR_VSX_TYPE(Name, Id, Size) \
 addImplicitTypedef(#Name, Context.Id##Ty);
 #include "clang/Basic/PPCTypes.def"

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index a6d26ac65465d..0ee05c9f09a52 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3521,9 +3521,9 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
   case PPC::BI__builtin_ppc_store8r:
 return SemaFeatureCheck(*this, TheCall, "isa-v206-instructions",
 diag::err_ppc_builtin_only_on_arch, "7");
-#define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
-  case PPC::BI__builtin_##Name: \
-return SemaBuiltinPPCMMACall(TheCall, Types);
+#define CUSTOM_BUILTIN(Name, Intr, Types, Acc) 
\
+  case PPC::BI__builtin_##Name:
\
+return SemaBuiltinPPCMMACall(TheCall, BuiltinID, Types);
 #include "clang/Basic/BuiltinsPPC.def"
   }
   return SemaBuiltinConstantArgRange(TheCall, i, l, u);
@@ -7481,11 +7481,35 @@ bool Sema::SemaBuiltinARMSpecialReg(unsigned BuiltinID, 
CallExpr *TheCall,
 /// Emit an error and return true on failure; return false on success.
 /// TypeStr is a string containing the type descriptor of the value returned by
 /// the builtin and the descriptors of the expected type of the arguments.
-bool Sema::SemaBuiltinPPCMMACall(CallExp

[clang] [PPC][InlineASM] Mark the 'a' constraint as unsupported (PR #96109)

2024-06-19 Thread Kamau Bridgeman via cfe-commits 

https://github.com/kamaub created 
https://github.com/llvm/llvm-project/pull/96109

'a' is an input/ouput constraint for restraining assembly variables
to an indexed or indirect address operand. It previously was marked
as supported but would throw an assertion for unknown constraint type
in the back-end when this test case was compiled. This change marks it
as unsupported until we can add full support for address operands
constraining to the compiler code generation.


>From 87983d169582bc5156220594e0fc4812f424bf75 Mon Sep 17 00:00:00 2001
From: Kamau Bridgeman 
Date: Wed, 19 Jun 2024 14:59:53 -0500
Subject: [PATCH] [PPC][InlineASM] Mark the 'a' constraint as unsupported

'a' is an input/ouput constraint for restraining assembly variables
to an indexed or indirect address operand. It previously was marked
as supported but would throw an assertion for unknown constraint type
in the back-end when this test case was compiled. This change marks it
as unsupported until we can add full support for address operands
constraining to the compiler code generation.
---
 clang/lib/Basic/Targets/PPC.h | 4 +++-
 .../PowerPC/inline-asm-unsupported-constraint-error.c | 8 
 2 files changed, 11 insertions(+), 1 deletion(-)
 create mode 100644 
clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c

diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index fc23c30c68523..e4d6a02386da5 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -305,9 +305,11 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   // asm statements)
   Info.setAllowsMemory();
   break;
-case 'R': // AIX TOC entry
 case 'a': // Address operand that is an indexed or indirect from a
   // register (`p' is preferable for asm statements)
+  // TODO: Add full support for this constraint
+  return false;
+case 'R': // AIX TOC entry
 case 'S': // Constant suitable as a 64-bit mask operand
 case 'T': // Constant suitable as a 32-bit mask operand
 case 'U': // System V Release 4 small data area reference
diff --git 
a/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c 
b/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
new file mode 100644
index 0..457908f016b0c
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -emit-llvm -triple powerpc64le-unknown-unknown -verify %s
+// This test case exist to test marking the 'a' inline assembly constraint as
+// unsupported because powerpc previously marked it as supported.
+int foo(int arg){
+  asm goto ("bc %0,%1,%l[TEST_LABEL]" : : "a"(&&TEST_LABEL) : : TEST_LABEL); 
//expected-error {{invalid input constraint 'a' in asm}}
+  return 0;
+TEST_LABEL: return arg + 1;
+}

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[clang] [PPC][InlineASM] Mark the 'a' constraint as unsupported (PR #96109)

2024-06-21 Thread Kamau Bridgeman via cfe-commits 

https://github.com/kamaub updated 
https://github.com/llvm/llvm-project/pull/96109

>From 87983d169582bc5156220594e0fc4812f424bf75 Mon Sep 17 00:00:00 2001
From: Kamau Bridgeman 
Date: Wed, 19 Jun 2024 14:59:53 -0500
Subject: [PATCH 1/2] [PPC][InlineASM] Mark the 'a' constraint as unsupported

'a' is an input/ouput constraint for restraining assembly variables
to an indexed or indirect address operand. It previously was marked
as supported but would throw an assertion for unknown constraint type
in the back-end when this test case was compiled. This change marks it
as unsupported until we can add full support for address operands
constraining to the compiler code generation.
---
 clang/lib/Basic/Targets/PPC.h | 4 +++-
 .../PowerPC/inline-asm-unsupported-constraint-error.c | 8 
 2 files changed, 11 insertions(+), 1 deletion(-)
 create mode 100644 
clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c

diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index fc23c30c68523..e4d6a02386da5 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -305,9 +305,11 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   // asm statements)
   Info.setAllowsMemory();
   break;
-case 'R': // AIX TOC entry
 case 'a': // Address operand that is an indexed or indirect from a
   // register (`p' is preferable for asm statements)
+  // TODO: Add full support for this constraint
+  return false;
+case 'R': // AIX TOC entry
 case 'S': // Constant suitable as a 64-bit mask operand
 case 'T': // Constant suitable as a 32-bit mask operand
 case 'U': // System V Release 4 small data area reference
diff --git 
a/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c 
b/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
new file mode 100644
index 0..457908f016b0c
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -emit-llvm -triple powerpc64le-unknown-unknown -verify %s
+// This test case exist to test marking the 'a' inline assembly constraint as
+// unsupported because powerpc previously marked it as supported.
+int foo(int arg){
+  asm goto ("bc %0,%1,%l[TEST_LABEL]" : : "a"(&&TEST_LABEL) : : TEST_LABEL); 
//expected-error {{invalid input constraint 'a' in asm}}
+  return 0;
+TEST_LABEL: return arg + 1;
+}

>From 6c3ff4ab36bb565d53dc6bac2577fd0f8c033f6b Mon Sep 17 00:00:00 2001
From: Kamau Bridgeman 
Date: Fri, 21 Jun 2024 13:02:50 -0500
Subject: [PATCH 2/2] Addressing review comment

Adding test case run lines for aix 32 and 64 bit targets.
---
 .../PowerPC/inline-asm-unsupported-constraint-error.c   | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git 
a/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c 
b/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
index 457908f016b0c..ebabc1d90b051 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
@@ -1,8 +1,10 @@
-// RUN: %clang_cc1 -emit-llvm -triple powerpc64le-unknown-unknown -verify %s
+// RUN: %clang_cc1 -emit-llvm -triple powerpc64le-linux-gnu -verify %s
+// RUN: %clang_cc1 -emit-llvm -triple powerpc64-ibm-aix-xcoff -verify %s
+// RUN: %clang_cc1 -emit-llvm -triple powerpc-ibm-aix-xcoff -verify %s
 // This test case exist to test marking the 'a' inline assembly constraint as
 // unsupported because powerpc previously marked it as supported.
 int foo(int arg){
-  asm goto ("bc %0,%1,%l[TEST_LABEL]" : : "a"(&&TEST_LABEL) : : TEST_LABEL); 
//expected-error {{invalid input constraint 'a' in asm}}
+  asm goto ("bc 12,2,%l[TEST_LABEL]" : : "a"(&&TEST_LABEL) : : TEST_LABEL); 
//expected-error {{invalid input constraint 'a' in asm}}
   return 0;
 TEST_LABEL: return arg + 1;
 }

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[clang] [llvm] [mlir] Remove the `x86_mmx` IR type. (PR #98505)

2024-07-25 Thread Kamau Bridgeman via cfe-commits 

kamaub wrote:

The changes made to the if statement in this PR at: 
https://github.com/llvm/llvm-project/commit/dfeb3991fb489a703f631ab0c34b58f80568038d#diff-f58c914c06010d2cd2c1359514ce9b8a4170e8c214eb52dd49ef5b17d391950eR2681
 causes a new `-Werror,-Wunused-but-set-variable` when building llvm-project 
with clang in this buildbot's 2nd stage: 
https://lab.llvm.org/buildbot/#/builders/168/builds/1450/steps/12/logs/stdio, 
please resolve this build failure as soon as possible to bring the bot back to 
green.

https://github.com/llvm/llvm-project/pull/98505
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[clang] 89ec99c - [PowerPC][Builtin] Allowing __rlwnm to accept a variable as a shift parameter

2021-10-13 Thread Kamau Bridgeman via cfe-commits 

Author: Kamau Bridgeman
Date: 2021-10-13T09:40:06-05:00
New Revision: 89ec99c778943151213118f096e8008197c9ba10

URL: 
https://github.com/llvm/llvm-project/commit/89ec99c778943151213118f096e8008197c9ba10
DIFF: 
https://github.com/llvm/llvm-project/commit/89ec99c778943151213118f096e8008197c9ba10.diff

LOG: [PowerPC][Builtin] Allowing __rlwnm to accept a variable as a shift 
parameter

The builtin __rlwnm is currently constrained to accept only constants
for the shift parameter but the instructions emitted for it have no such
constraint, this patch allows the builtins to accept variable shift.

Reviewed By: NeHuang, amyk

Differential Revision: https://reviews.llvm.org/D111229

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 3fa5729fc7d03..f82d455506860 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -117,7 +117,7 @@ BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "")
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
 // Rotate
-BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "")
+BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "")
 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
 // load

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 4d84606290b4e..090fcd985df07 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3432,8 +3432,7 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
   // For __rlwnm, __rlwimi and __rldimi, the last parameter mask must
   // be a constant that represents a contiguous bit field.
   case PPC::BI__builtin_ppc_rlwnm:
-return SemaBuiltinConstantArg(TheCall, 1, Result) ||
-   SemaValueIsRunOfOnes(TheCall, 2);
+return SemaValueIsRunOfOnes(TheCall, 2);
   case PPC::BI__builtin_ppc_rlwimi:
   case PPC::BI__builtin_ppc_rldimi:
 return SemaBuiltinConstantArg(TheCall, 2, Result) ||

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
index 9fc218b1de413..5f57d7575c859 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -41,10 +41,8 @@ void test_builtin_ppc_rlwimi() {
 }
 
 void test_builtin_ppc_rlwnm() {
-  unsigned int shift;
   unsigned int mask;
-  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7); // expected-error 
{{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
-  res = __builtin_ppc_rlwnm(ui, 31, mask);  // expected-error 
{{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
+  unsigned int res = __builtin_ppc_rlwnm(ui, 31, mask);  // 
expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
   res = __builtin_ppc_rlwnm(ui, 31, 0xFF0F0F00);// expected-error 
{{argument 2 value should represent a contiguous bit field}}
 }
 

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
index 5ca7706f422ff..73c2d2cb8aee2 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -56,6 +56,22 @@ void test_builtin_ppc_rlwnm() {
   unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
 }
 
+void test_builtin_ppc_rlwnm2(unsigned int shift) {
+  // CHECK-LABEL: test_builtin_ppc_rlwnm2
+  // CHECK:   %shift.addr = alloca i32, align 4
+  // CHECK-NEXT:  %res = alloca i32, align 4
+  // CHECK-NEXT:  store i32 %shift, i32* %shift.addr, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* %shift.addr, align 4
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 
[[RA]], i32 [[RB]])
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 511
+  // CHECK-NEXT:  store i32 [[RD]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*mask = 0x1FF = 511*/
+  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 0x1FF);
+}
+
 // CHECK-LABEL: @testrotatel4(
 // CHECK: [[TMP:%.*]] = call i32 @llvm.fshl.i32(i32 {{%.*}}, i32 
{{%.*}}, i32 {{%.*}})
 // CHECK-NEXT:ret i32 [[TMP]]



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[clang] [PPC][InlineASM] Mark the 'a' constraint as unsupported (PR #96109)

2024-06-24 Thread Kamau Bridgeman via cfe-commits 

https://github.com/kamaub updated 
https://github.com/llvm/llvm-project/pull/96109

>From 87983d169582bc5156220594e0fc4812f424bf75 Mon Sep 17 00:00:00 2001
From: Kamau Bridgeman 
Date: Wed, 19 Jun 2024 14:59:53 -0500
Subject: [PATCH 1/3] [PPC][InlineASM] Mark the 'a' constraint as unsupported

'a' is an input/ouput constraint for restraining assembly variables
to an indexed or indirect address operand. It previously was marked
as supported but would throw an assertion for unknown constraint type
in the back-end when this test case was compiled. This change marks it
as unsupported until we can add full support for address operands
constraining to the compiler code generation.
---
 clang/lib/Basic/Targets/PPC.h | 4 +++-
 .../PowerPC/inline-asm-unsupported-constraint-error.c | 8 
 2 files changed, 11 insertions(+), 1 deletion(-)
 create mode 100644 
clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c

diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index fc23c30c68523..e4d6a02386da5 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -305,9 +305,11 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   // asm statements)
   Info.setAllowsMemory();
   break;
-case 'R': // AIX TOC entry
 case 'a': // Address operand that is an indexed or indirect from a
   // register (`p' is preferable for asm statements)
+  // TODO: Add full support for this constraint
+  return false;
+case 'R': // AIX TOC entry
 case 'S': // Constant suitable as a 64-bit mask operand
 case 'T': // Constant suitable as a 32-bit mask operand
 case 'U': // System V Release 4 small data area reference
diff --git 
a/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c 
b/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
new file mode 100644
index 0..457908f016b0c
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -emit-llvm -triple powerpc64le-unknown-unknown -verify %s
+// This test case exist to test marking the 'a' inline assembly constraint as
+// unsupported because powerpc previously marked it as supported.
+int foo(int arg){
+  asm goto ("bc %0,%1,%l[TEST_LABEL]" : : "a"(&&TEST_LABEL) : : TEST_LABEL); 
//expected-error {{invalid input constraint 'a' in asm}}
+  return 0;
+TEST_LABEL: return arg + 1;
+}

>From 6c3ff4ab36bb565d53dc6bac2577fd0f8c033f6b Mon Sep 17 00:00:00 2001
From: Kamau Bridgeman 
Date: Fri, 21 Jun 2024 13:02:50 -0500
Subject: [PATCH 2/3] Addressing review comment

Adding test case run lines for aix 32 and 64 bit targets.
---
 .../PowerPC/inline-asm-unsupported-constraint-error.c   | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git 
a/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c 
b/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
index 457908f016b0c..ebabc1d90b051 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
@@ -1,8 +1,10 @@
-// RUN: %clang_cc1 -emit-llvm -triple powerpc64le-unknown-unknown -verify %s
+// RUN: %clang_cc1 -emit-llvm -triple powerpc64le-linux-gnu -verify %s
+// RUN: %clang_cc1 -emit-llvm -triple powerpc64-ibm-aix-xcoff -verify %s
+// RUN: %clang_cc1 -emit-llvm -triple powerpc-ibm-aix-xcoff -verify %s
 // This test case exist to test marking the 'a' inline assembly constraint as
 // unsupported because powerpc previously marked it as supported.
 int foo(int arg){
-  asm goto ("bc %0,%1,%l[TEST_LABEL]" : : "a"(&&TEST_LABEL) : : TEST_LABEL); 
//expected-error {{invalid input constraint 'a' in asm}}
+  asm goto ("bc 12,2,%l[TEST_LABEL]" : : "a"(&&TEST_LABEL) : : TEST_LABEL); 
//expected-error {{invalid input constraint 'a' in asm}}
   return 0;
 TEST_LABEL: return arg + 1;
 }

>From d36eb3e75f3adbc9414b314a6decf12f3adbd8c0 Mon Sep 17 00:00:00 2001
From: Kamau Bridgeman 
Date: Mon, 24 Jun 2024 07:32:06 -0500
Subject: [PATCH 3/3] Addressing review comments.

---
 ...pported-constraint-error.c => inline-asm-constraints-error.c} | 1 -
 1 file changed, 1 deletion(-)
 rename clang/test/CodeGen/PowerPC/{inline-asm-unsupported-constraint-error.c 
=> inline-asm-constraints-error.c} (87%)

diff --git 
a/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c 
b/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c
similarity index 87%
rename from clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
rename to clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c
index ebabc1d90b051..eb443eee40e55 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-unsupported-constraint-error.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c
@@ -1,4 +1,3 @@
-// RUN: %clang_cc1 -emit-llvm -tr

[clang] [PPC][InlineASM] Mark the 'a' constraint as unsupported (PR #96109)

2024-06-24 Thread Kamau Bridgeman via cfe-commits 

https://github.com/kamaub closed https://github.com/llvm/llvm-project/pull/96109
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[clang] [llvm] [WIP] Support the inline asm 'a' constraint on PowerPC (PR #141604)

2025-05-27 Thread Kamau Bridgeman via cfe-commits 

https://github.com/kamaub created 
https://github.com/llvm/llvm-project/pull/141604

This patch adds backend and frontend support for address operand
constraint `a` for GCC style inline assembly. It allows the user
to specify X-FORM addressing mode operations in inline assmebly
without doing a [0 + Reg] index using the y constraint modifier.


>From e4102e3c4ec77e98c9a5efd3c79cd6a7690ba6a1 Mon Sep 17 00:00:00 2001
From: Kamau Bridgeman 
Date: Tue, 27 May 2025 09:39:07 -0400
Subject: [PATCH] [WIP] Support the inline asm 'a' constraint on PowerPC

This patch adds backend and frontend support for address operand
constraint `a` for GCC style inline assembly. It allows the user
to specify X-FORM addressing mode operations in inline assmebly
without doing a [0 + Reg] index using the y constraint modifier.
---
 clang/lib/Basic/Targets/PPC.h |   4 +-
 .../PowerPC/inline-asm-constraints-error.c|  12 +-
 .../CodeGen/PowerPC/inline-asm-constraints.c  |  66 +
 llvm/include/llvm/IR/InlineAsm.h  |   3 +
 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp |   8 ++
 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp   |   1 +
 llvm/lib/Target/PowerPC/PPCISelLowering.cpp   |   2 +
 llvm/lib/Target/PowerPC/PPCISelLowering.h |  16 +--
 .../PowerPC/inline-asm-constraints-error.ll   |  26 
 .../CodeGen/PowerPC/inline-asm-constraints.ll | 127 ++
 10 files changed, 250 insertions(+), 15 deletions(-)
 create mode 100644 clang/test/CodeGen/PowerPC/inline-asm-constraints.c
 create mode 100644 llvm/test/CodeGen/PowerPC/inline-asm-constraints-error.ll
 create mode 100644 llvm/test/CodeGen/PowerPC/inline-asm-constraints.ll

diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 17057cef97a57..76fb24ed40050 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -303,8 +303,8 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   break;
 case 'a': // Address operand that is an indexed or indirect from a
   // register (`p' is preferable for asm statements)
-  // TODO: Add full support for this constraint
-  return false;
+  Info.setAllowsRegister();
+  break;
 case 'R': // AIX TOC entry
 case 'S': // Constant suitable as a 64-bit mask operand
 case 'T': // Constant suitable as a 32-bit mask operand
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c 
b/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c
index 2f35e52fc0b77..c1bb59ee3c22a 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c
@@ -1,9 +1,13 @@
 // RUN: %clang_cc1 -emit-llvm-only -triple powerpc64-ibm-aix-xcoff -verify %s
 // RUN: %clang_cc1 -emit-llvm-only -triple powerpc-ibm-aix-xcoff -verify %s
-// This test case exist to test marking the 'a' inline assembly constraint as
-// unsupported because powerpc previously marked it as supported.
-int foo(int arg){
-  asm goto ("bc 12,2,%l[TEST_LABEL]" : : "a"(&&TEST_LABEL) : : TEST_LABEL); 
//expected-error {{invalid input constraint 'a' in asm}}
+
+ int labelConstraintError(int arg){
+  asm goto ("bc 12,2,%l[TEST_LABEL]" : : "s"(&&TEST_LABEL) : : TEST_LABEL); 
//expected-error {{invalid input constraint 's' in asm}}
   return 0;
 TEST_LABEL: return arg + 1;
 }
+
+char wrongAddrConstraint(char* result) {
+  asm ("stb %1,%0" : "a"(result) : "r"('E') :); //expected-error {{invalid 
output constraint 'a' in asm}}
+  return *result;
+}
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-constraints.c 
b/clang/test/CodeGen/PowerPC/inline-asm-constraints.c
new file mode 100644
index 0..ca5a9ffcee0cc
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/inline-asm-constraints.c
@@ -0,0 +1,66 @@
+// RUN: %clang_cc1 -emit-llvm -triple powerpc64-ibm-aix-xcoff \
+// RUN:   %s -o - | FileCheck %s
+
+char loadAddressAConstrained(char* ptr) {
+// CHECK-LABEL: define{{.*}} i8 @loadAddressAConstrained(ptr noundef %ptr)
+// CHECK:  %1 = call ptr asm "addi $0,$1, 0", "=r,a"(ptr %0)
+  char* result;
+  asm ("addi %0,%1, 0" : "=r"(result) : "a"(ptr) :);
+  return *result;
+}
+
+char loadAddressZyConstrained(char* ptr) {
+// CHECK-LABEL: define{{.*}} i8 @loadAddressZyConstrained(ptr noundef %ptr)
+// CHECK:  %1 = call ptr asm "add $0,${1:y}", "=r,*Z"(ptr elementtype(i8) %0)
+  char* result;
+  asm ("add %0,%y1" : "=r"(result) : "Z"(*ptr) :);
+  return *result;
+}
+
+char xFormRegImmLoadAConstrained(char* ptr) {
+// CHECK-LABEL: define{{.*}} i8 @xFormRegImmLoadAConstrained(ptr noundef %ptr)
+// CHECK:  %1 = call ptr asm "addi $0,$1,$2", "=r,a,I"(ptr %0, i32 1)
+  char* result;
+  asm ("addi %0,%1,%2" : "=r"(result) : "a"(ptr), "I"(1) :);
+  return *result;
+}
+
+char loadIndirectAddressZConstrained(char* ptr) {
+// CHECK-LABEL: define{{.*}} i8 @loadIndirectAddressZConstrained(ptr noundef 
%ptr)
+// CHECK:  %1 = call ptr asm "ld $0,$1", "=r,*Z"(ptr elementtyp

[clang] [llvm] [WIP] Support the inline asm 'a' constraint on PowerPC (PR #141604)

2025-05-27 Thread Kamau Bridgeman via cfe-commits 

kamaub wrote:

This is a draft PR because the type promotion errors occurring in test case 
[llvm/test/CodeGen/PowerPC/inline-asm-constraints-error.ll](https://github.com/llvm/llvm-project/pull/141604/files#diff-becfb4d0b9a7b0638d52047d9458c1b8cd9942a318e2895ad0f448b8bdfd2e40)
 are not being properly handled and need to be resolved and gracefully failed 
before this patch can go in. Otherwise it would be introducing a way to crash 
the compiler.

https://github.com/llvm/llvm-project/pull/141604
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[clang] [llvm] Support the inline asm 'a' constraint on PowerPC (PR #141604)

2025-05-28 Thread Kamau Bridgeman via cfe-commits 

kamaub wrote:

After discussion with the IBM llvm on power team I will separate the type 
promotion error test case file into another patch as the error is only exposed 
by, not caused by this patch.

https://github.com/llvm/llvm-project/pull/141604
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[clang] [llvm] Support the inline asm 'a' constraint on PowerPC (PR #141604)

2025-05-28 Thread Kamau Bridgeman via cfe-commits 

https://github.com/kamaub edited 
https://github.com/llvm/llvm-project/pull/141604
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[clang] [llvm] Support the inline asm 'a' constraint on PowerPC (PR #141604)

2025-05-28 Thread Kamau Bridgeman via cfe-commits 

https://github.com/kamaub updated 
https://github.com/llvm/llvm-project/pull/141604

>From e4102e3c4ec77e98c9a5efd3c79cd6a7690ba6a1 Mon Sep 17 00:00:00 2001
From: Kamau Bridgeman 
Date: Tue, 27 May 2025 09:39:07 -0400
Subject: [PATCH 1/3] [WIP] Support the inline asm 'a' constraint on PowerPC

This patch adds backend and frontend support for address operand
constraint `a` for GCC style inline assembly. It allows the user
to specify X-FORM addressing mode operations in inline assmebly
without doing a [0 + Reg] index using the y constraint modifier.
---
 clang/lib/Basic/Targets/PPC.h |   4 +-
 .../PowerPC/inline-asm-constraints-error.c|  12 +-
 .../CodeGen/PowerPC/inline-asm-constraints.c  |  66 +
 llvm/include/llvm/IR/InlineAsm.h  |   3 +
 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp |   8 ++
 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp   |   1 +
 llvm/lib/Target/PowerPC/PPCISelLowering.cpp   |   2 +
 llvm/lib/Target/PowerPC/PPCISelLowering.h |  16 +--
 .../PowerPC/inline-asm-constraints-error.ll   |  26 
 .../CodeGen/PowerPC/inline-asm-constraints.ll | 127 ++
 10 files changed, 250 insertions(+), 15 deletions(-)
 create mode 100644 clang/test/CodeGen/PowerPC/inline-asm-constraints.c
 create mode 100644 llvm/test/CodeGen/PowerPC/inline-asm-constraints-error.ll
 create mode 100644 llvm/test/CodeGen/PowerPC/inline-asm-constraints.ll

diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 17057cef97a57..76fb24ed40050 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -303,8 +303,8 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   break;
 case 'a': // Address operand that is an indexed or indirect from a
   // register (`p' is preferable for asm statements)
-  // TODO: Add full support for this constraint
-  return false;
+  Info.setAllowsRegister();
+  break;
 case 'R': // AIX TOC entry
 case 'S': // Constant suitable as a 64-bit mask operand
 case 'T': // Constant suitable as a 32-bit mask operand
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c 
b/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c
index 2f35e52fc0b77..c1bb59ee3c22a 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c
@@ -1,9 +1,13 @@
 // RUN: %clang_cc1 -emit-llvm-only -triple powerpc64-ibm-aix-xcoff -verify %s
 // RUN: %clang_cc1 -emit-llvm-only -triple powerpc-ibm-aix-xcoff -verify %s
-// This test case exist to test marking the 'a' inline assembly constraint as
-// unsupported because powerpc previously marked it as supported.
-int foo(int arg){
-  asm goto ("bc 12,2,%l[TEST_LABEL]" : : "a"(&&TEST_LABEL) : : TEST_LABEL); 
//expected-error {{invalid input constraint 'a' in asm}}
+
+ int labelConstraintError(int arg){
+  asm goto ("bc 12,2,%l[TEST_LABEL]" : : "s"(&&TEST_LABEL) : : TEST_LABEL); 
//expected-error {{invalid input constraint 's' in asm}}
   return 0;
 TEST_LABEL: return arg + 1;
 }
+
+char wrongAddrConstraint(char* result) {
+  asm ("stb %1,%0" : "a"(result) : "r"('E') :); //expected-error {{invalid 
output constraint 'a' in asm}}
+  return *result;
+}
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-constraints.c 
b/clang/test/CodeGen/PowerPC/inline-asm-constraints.c
new file mode 100644
index 0..ca5a9ffcee0cc
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/inline-asm-constraints.c
@@ -0,0 +1,66 @@
+// RUN: %clang_cc1 -emit-llvm -triple powerpc64-ibm-aix-xcoff \
+// RUN:   %s -o - | FileCheck %s
+
+char loadAddressAConstrained(char* ptr) {
+// CHECK-LABEL: define{{.*}} i8 @loadAddressAConstrained(ptr noundef %ptr)
+// CHECK:  %1 = call ptr asm "addi $0,$1, 0", "=r,a"(ptr %0)
+  char* result;
+  asm ("addi %0,%1, 0" : "=r"(result) : "a"(ptr) :);
+  return *result;
+}
+
+char loadAddressZyConstrained(char* ptr) {
+// CHECK-LABEL: define{{.*}} i8 @loadAddressZyConstrained(ptr noundef %ptr)
+// CHECK:  %1 = call ptr asm "add $0,${1:y}", "=r,*Z"(ptr elementtype(i8) %0)
+  char* result;
+  asm ("add %0,%y1" : "=r"(result) : "Z"(*ptr) :);
+  return *result;
+}
+
+char xFormRegImmLoadAConstrained(char* ptr) {
+// CHECK-LABEL: define{{.*}} i8 @xFormRegImmLoadAConstrained(ptr noundef %ptr)
+// CHECK:  %1 = call ptr asm "addi $0,$1,$2", "=r,a,I"(ptr %0, i32 1)
+  char* result;
+  asm ("addi %0,%1,%2" : "=r"(result) : "a"(ptr), "I"(1) :);
+  return *result;
+}
+
+char loadIndirectAddressZConstrained(char* ptr) {
+// CHECK-LABEL: define{{.*}} i8 @loadIndirectAddressZConstrained(ptr noundef 
%ptr)
+// CHECK:  %1 = call ptr asm "ld $0,$1", "=r,*Z"(ptr elementtype(i8) %arrayidx)
+  char* result;
+  asm ("ld %0,%1" : "=r"(result) : "Z"(ptr[100]) :);
+  return *result;
+}
+
+char loadIndirectAddressAConstrained(char** ptr, unsigned index) {
+// CHECK-LABEL: define{{.*}} i8 @loadIndirectAddressAConstrained(ptr noundef

[clang] [llvm] Support the inline asm 'a' constraint on PowerPC (PR #141604)

2025-05-28 Thread Kamau Bridgeman via cfe-commits 

https://github.com/kamaub ready_for_review 
https://github.com/llvm/llvm-project/pull/141604
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[clang] [llvm] [WIP] Support the inline asm 'a' constraint on PowerPC (PR #141604)

2025-05-28 Thread Kamau Bridgeman via cfe-commits 

https://github.com/kamaub updated 
https://github.com/llvm/llvm-project/pull/141604

>From e4102e3c4ec77e98c9a5efd3c79cd6a7690ba6a1 Mon Sep 17 00:00:00 2001
From: Kamau Bridgeman 
Date: Tue, 27 May 2025 09:39:07 -0400
Subject: [PATCH 1/2] [WIP] Support the inline asm 'a' constraint on PowerPC

This patch adds backend and frontend support for address operand
constraint `a` for GCC style inline assembly. It allows the user
to specify X-FORM addressing mode operations in inline assmebly
without doing a [0 + Reg] index using the y constraint modifier.
---
 clang/lib/Basic/Targets/PPC.h |   4 +-
 .../PowerPC/inline-asm-constraints-error.c|  12 +-
 .../CodeGen/PowerPC/inline-asm-constraints.c  |  66 +
 llvm/include/llvm/IR/InlineAsm.h  |   3 +
 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp |   8 ++
 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp   |   1 +
 llvm/lib/Target/PowerPC/PPCISelLowering.cpp   |   2 +
 llvm/lib/Target/PowerPC/PPCISelLowering.h |  16 +--
 .../PowerPC/inline-asm-constraints-error.ll   |  26 
 .../CodeGen/PowerPC/inline-asm-constraints.ll | 127 ++
 10 files changed, 250 insertions(+), 15 deletions(-)
 create mode 100644 clang/test/CodeGen/PowerPC/inline-asm-constraints.c
 create mode 100644 llvm/test/CodeGen/PowerPC/inline-asm-constraints-error.ll
 create mode 100644 llvm/test/CodeGen/PowerPC/inline-asm-constraints.ll

diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 17057cef97a57..76fb24ed40050 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -303,8 +303,8 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   break;
 case 'a': // Address operand that is an indexed or indirect from a
   // register (`p' is preferable for asm statements)
-  // TODO: Add full support for this constraint
-  return false;
+  Info.setAllowsRegister();
+  break;
 case 'R': // AIX TOC entry
 case 'S': // Constant suitable as a 64-bit mask operand
 case 'T': // Constant suitable as a 32-bit mask operand
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c 
b/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c
index 2f35e52fc0b77..c1bb59ee3c22a 100644
--- a/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c
+++ b/clang/test/CodeGen/PowerPC/inline-asm-constraints-error.c
@@ -1,9 +1,13 @@
 // RUN: %clang_cc1 -emit-llvm-only -triple powerpc64-ibm-aix-xcoff -verify %s
 // RUN: %clang_cc1 -emit-llvm-only -triple powerpc-ibm-aix-xcoff -verify %s
-// This test case exist to test marking the 'a' inline assembly constraint as
-// unsupported because powerpc previously marked it as supported.
-int foo(int arg){
-  asm goto ("bc 12,2,%l[TEST_LABEL]" : : "a"(&&TEST_LABEL) : : TEST_LABEL); 
//expected-error {{invalid input constraint 'a' in asm}}
+
+ int labelConstraintError(int arg){
+  asm goto ("bc 12,2,%l[TEST_LABEL]" : : "s"(&&TEST_LABEL) : : TEST_LABEL); 
//expected-error {{invalid input constraint 's' in asm}}
   return 0;
 TEST_LABEL: return arg + 1;
 }
+
+char wrongAddrConstraint(char* result) {
+  asm ("stb %1,%0" : "a"(result) : "r"('E') :); //expected-error {{invalid 
output constraint 'a' in asm}}
+  return *result;
+}
diff --git a/clang/test/CodeGen/PowerPC/inline-asm-constraints.c 
b/clang/test/CodeGen/PowerPC/inline-asm-constraints.c
new file mode 100644
index 0..ca5a9ffcee0cc
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/inline-asm-constraints.c
@@ -0,0 +1,66 @@
+// RUN: %clang_cc1 -emit-llvm -triple powerpc64-ibm-aix-xcoff \
+// RUN:   %s -o - | FileCheck %s
+
+char loadAddressAConstrained(char* ptr) {
+// CHECK-LABEL: define{{.*}} i8 @loadAddressAConstrained(ptr noundef %ptr)
+// CHECK:  %1 = call ptr asm "addi $0,$1, 0", "=r,a"(ptr %0)
+  char* result;
+  asm ("addi %0,%1, 0" : "=r"(result) : "a"(ptr) :);
+  return *result;
+}
+
+char loadAddressZyConstrained(char* ptr) {
+// CHECK-LABEL: define{{.*}} i8 @loadAddressZyConstrained(ptr noundef %ptr)
+// CHECK:  %1 = call ptr asm "add $0,${1:y}", "=r,*Z"(ptr elementtype(i8) %0)
+  char* result;
+  asm ("add %0,%y1" : "=r"(result) : "Z"(*ptr) :);
+  return *result;
+}
+
+char xFormRegImmLoadAConstrained(char* ptr) {
+// CHECK-LABEL: define{{.*}} i8 @xFormRegImmLoadAConstrained(ptr noundef %ptr)
+// CHECK:  %1 = call ptr asm "addi $0,$1,$2", "=r,a,I"(ptr %0, i32 1)
+  char* result;
+  asm ("addi %0,%1,%2" : "=r"(result) : "a"(ptr), "I"(1) :);
+  return *result;
+}
+
+char loadIndirectAddressZConstrained(char* ptr) {
+// CHECK-LABEL: define{{.*}} i8 @loadIndirectAddressZConstrained(ptr noundef 
%ptr)
+// CHECK:  %1 = call ptr asm "ld $0,$1", "=r,*Z"(ptr elementtype(i8) %arrayidx)
+  char* result;
+  asm ("ld %0,%1" : "=r"(result) : "Z"(ptr[100]) :);
+  return *result;
+}
+
+char loadIndirectAddressAConstrained(char** ptr, unsigned index) {
+// CHECK-LABEL: define{{.*}} i8 @loadIndirectAddressAConstrained(ptr noundef