[PATCH] D80294: Add support for vmsumudm

[Kamau Bridgeman via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa28e9f120860: [PowerPC] Add support for vmsumudm (authored 
by saghir, committed by kamaub).

Changed prior to commit:
  https://reviews.llvm.org/D80294?vs=265332&id=265790#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstrAltivec.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
  llvm/test/MC/PowerPC/ppc64-encoding-vmx.s


Index: llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
===
--- llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
@@ -366,6 +366,9 @@
 # CHECK-BE: vmsumuhm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x66]
 # CHECK-LE: vmsumuhm 2, 3, 4, 5 # encoding: [0x66,0x21,0x43,0x10]
 vmsumuhm 2, 3, 4, 5
+# CHECK-BE: vmsumudm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x63]
+# CHECK-LE: vmsumudm 2, 3, 4, 5 # encoding: [0x63,0x21,0x43,0x10]
+vmsumudm 2, 3, 4, 5
 # CHECK-BE: vmsumuhs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x67]
 # CHECK-LE: vmsumuhs 2, 3, 4, 5 # encoding: [0x67,0x21,0x43,0x10]
 vmsumuhs 2, 3, 4, 5
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
===
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
@@ -333,6 +333,9 @@
 # CHECK: vmsumuhm 2, 3, 4, 5 
 0x10 0x43 0x21 0x66
 
+# CHECK: vmsumudm 2, 3, 4, 5
+0x10 0x43 0x21 0x63
+
 # CHECK: vmsumuhs 2, 3, 4, 5 
 0x10 0x43 0x21 0x67
 
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
===
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -1362,6 +1362,10 @@
 def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">;
 let Predicates = [HasP9Altivec] in {
 
+// Vector Multiply-Sum
+def VMSUMUDM : VA1a_Int_Ty3<35, "vmsumudm", int_ppc_altivec_vmsumudm,
+v1i128, v2i64, v1i128>;
+
 // i8 element comparisons.
 def VCMPNEB   : VCMP   <  7, "vcmpneb $vD, $vA, $vB"  , v16i8>;
 def VCMPNEB_rec  : VCMPo  <  7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
Index: llvm/lib/Target/PowerPC/P9InstrResources.td
===
--- llvm/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -373,6 +373,7 @@
 VMSUMSHS,
 VMSUMUBM,
 VMSUMUHM,
+VMSUMUDM,
 VMSUMUHS,
 VMULESB,
 VMULESH,
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -495,6 +495,9 @@
   def int_ppc_altivec_vmsumuhm : GCCBuiltin<"__builtin_altivec_vmsumuhm">,
 Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v4i32_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vmsumudm : GCCBuiltin<"__builtin_altivec_vmsumudm">,
+Intrinsic<[llvm_v1i128_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
+   llvm_v1i128_ty], [IntrNoMem]>;
   def int_ppc_altivec_vmsumuhs : GCCBuiltin<"__builtin_altivec_vmsumuhs">,
 Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v4i32_ty], [IntrNoMem]>;


Index: llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
===
--- llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-vmx.s
@@ -366,6 +366,9 @@
 # CHECK-BE: vmsumuhm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x66]
 # CHECK-LE: vmsumuhm 2, 3, 4, 5 # encoding: [0x66,0x21,0x43,0x10]
 vmsumuhm 2, 3, 4, 5
+# CHECK-BE: vmsumudm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x63]
+# CHECK-LE: vmsumudm 2, 3, 4, 5 # encoding: [0x63,0x21,0x43,0x10]
+vmsumudm 2, 3, 4, 5
 # CHECK-BE: vmsumuhs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x67]
 # CHECK-LE: vmsumuhs 2, 3, 4, 5 # encoding: [0x67,0x21,0x43,0x10]
 vmsumuhs 2, 3, 4, 5
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
===
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
@@ -333,6 +333,9 @@
 # CHECK: vmsumuhm 2, 3, 4, 5 
 0x10 0x43 0x21 0x66
 
+# CHECK: vmsumudm 2, 3, 4, 5
+0x10 0x43 0x21 0x63
+
 # CHECK: vmsumuhs 2, 3, 4, 5 
 0x10 0x43 0x21 0x67

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub accepted this revision as: kamaub.
kamaub added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub accepted this revision.
kamaub added a comment.

LGTM


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[PATCH] D85545: [Diagnostics] Diagnose missing comma in string array initialization

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub added a comment.

Hello, sorry but can you please revert this commit and recommit it when you 
have a fix or work around that doesn't break our bots:
It breaks 
http://lab.llvm.org:8011/builders/ppc64le-lld-multistage-test/builds/11228 
which builds with `-Werror`
Please also note that it introduced 103 warnings in 
clang-ppc64le-linux-multistage/builds/13042 



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[PATCH] D85978: [clang-tools-extra] Added missing comma

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub accepted this revision.
kamaub added a comment.
This revision is now accepted and ready to land.

This LGTM


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[PATCH] D122271: [Clang] -Wunused-but-set-variable warning - handle also pre/post unary operators

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub added a comment.

This option appears to incorrectly warn warning that `unsigned NumEntries = 
getNumEntries();` is "set but not used" in llvm/include/llvm/ADT/DenseMap.h:129 
 
and so it is breaking the ppc64le-lld-multistage-test 
 bot. 
This could be because the only use is in an assert which is in a corner case 
maybe?

  const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
  if (std::is_trivially_destructible::value) {
// Use a simpler loop when values don't need destruction.
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P)
  P->getFirst() = EmptyKey;
  } else {
unsigned NumEntries = getNumEntries();
for (BucketT *P = getBuckets(), *E = getBucketsEnd(); P != E; ++P) {
  if (!KeyInfoT::isEqual(P->getFirst(), EmptyKey)) {
if (!KeyInfoT::isEqual(P->getFirst(), TombstoneKey)) {
  P->getSecond().~ValueT();
  --NumEntries;
}
P->getFirst() = EmptyKey;
  }
}
assert(NumEntries == 0 && "Node count imbalance!");
  }

I noticed you were commit NFCI changes to makes sure you did not break any 
builds before reapplying but it appears you missed 
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:3924 
 
which is causing build breaks to both the sanitizer-ppc64be-linux 
 and sanitizer-ppc64le-linux 
 bots. Is there an NFCI planned 
for it by you? If not I'll submit an NFC change myself in a few minutes.


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[PATCH] D122271: [Clang] -Wunused-but-set-variable warning - handle also pre/post unary operators

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub added a comment.

I'm sorry I took so long to notify you but I need to bring these bots back to 
green as soon as possible, they have been broken too long.


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[PATCH] D105360: [PowerPC] Fix popcntb XL Compat Builtin for 32bit

[Kamau Bridgeman via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGde3956605a70: [PowerPC] Fix popcntb XL Compat Builtin for 
32bit (authored by quinnp, committed by kamaub).

Changed prior to commit:
  https://reviews.llvm.org/D105360?vs=358639&id=359063#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/P9InstrResources.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
+++ /dev/null
@@ -1,74 +0,0 @@
-; RUN: llc -verify-machineinstrs -mtriple=powerpcle-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s
-
-define dso_local void @test_builtin_ppc_eieio() #0 {
-; CHECK-LABEL: test_builtin_ppc_eieio
-
-entry:
-  call void @llvm.ppc.eieio()
-; CHECK: ori 2, 2, 0
-; CHECK-NEXT: ori 2, 2, 0
-; CHECK-NEXT: eieio
- 
-  ret void
-}
-
-declare void @llvm.ppc.eieio() #2
-
-define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_eieio
-
-entry:
-  call void @llvm.ppc.iospace.eieio()
-; CHECK: ori 2, 2, 0
-; CHECK-NEXT: ori 2, 2, 0
-; CHECK-NEXT: eieio
- 
-  ret void
-}
-
-declare void @llvm.ppc.iospace.eieio() #2
-
-define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
-
-entry:
-  call void @llvm.ppc.iospace.lwsync()
-; CHECK: lwsync
-
-  ret void
-}
-
-declare void @llvm.ppc.iospace.lwsync() #2
-
-define dso_local void @test_builtin_ppc_iospace_sync() #0 {
-; CHECK-LABEL: test_builtin_ppc_iospace_sync
-
-entry:
-  call void @llvm.ppc.iospace.sync()
-; CHECK: sync
-
-  ret void
-}
-
-declare void @llvm.ppc.iospace.sync() #2
-
-define dso_local void @test_builtin_ppc_icbt() #0 {
-; CHECK-LABEL: test_builtin_ppc_icbt
-
-entry:
-  %a = alloca i8*, align 8
-  %0 = load i8*, i8** %a, align 8
-  call void @llvm.ppc.icbt(i8* %0)
-; CHECK: icbt 0, 0, 3
-
-  ret void
-}
-
-declare void @llvm.ppc.icbt(i8*) #2
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
@@ -0,0 +1,116 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+define dso_local i64 @test_builtin_ppc_popcntb_i64(i64 %a) local_unnamed_addr {
+; CHECK-LABEL: test_builtin_ppc_popcntb_i64:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:popcntb r3, r3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_popcntb_i64:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:popcntb 3, 3
+; CHECK-AIX-NEXT:blr
+entry:
+  %popcntb = tail call i64 @llvm.ppc.popcntb.i64.i64(i64 %a)
+  ret i64 %popcntb
+}
+declare i64 @llvm.ppc.popcntb.i64.i64(i64)
+
+define dso_local void @test_builtin_ppc_eieio() {
+; CHECK-LABEL: test_builtin_ppc_eieio:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:ori r2, r2, 0
+; CHECK-NEXT:ori r2, r2, 0
+; CHECK-NEXT:eieio
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_builtin_ppc_eieio:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:ori 2, 2, 0
+; CHECK-AIX-NEXT:ori 2, 2, 0
+; CHECK-AIX-NEXT:eieio
+; CHECK-AIX-NEXT:blr
+entry:
+  call void @llvm.ppc.eieio()
+  ret void
+}
+declare void @llvm.ppc.eieio()
+
+define dso_local void @test_builtin_ppc_iospace_eieio() {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:ori r2, r2, 0
+; CHECK-NEXT:ori r2, r2, 0
+; CHECK-NEXT:eieio
+; CHECK-NEXT:b

[PATCH] D106150: [PowerPC] swdiv_nochk Builtins for XL Compat

[Kamau Bridgeman via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0268e123bea5: [PowerPC] swdiv_nochk Builtins for XL Compat 
(authored by quinnp, committed by kamaub).

Changed prior to commit:
  https://reviews.llvm.org/D106150?vs=359327&id=359929#toc

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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-swdiv_nochk.c
@@ -0,0 +1,100 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern double a;
+extern double b;
+extern double c;
+extern float d;
+extern float e;
+extern float f;
+
+// CHECK-LABEL: @test_swdiv_nochk(
+// CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV_NOCHK]]
+//
+double test_swdiv_nochk() {
+  return __swdiv_nochk(a, b);
+}
+
+// CHECK-LABEL: @test_swdivs_nochk(
+// CHECK:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIV_NOCHK]]
+//
+float test_swdivs_nochk() {
+  return __swdivs_nochk(d, e);
+}
+
+// CHECK-LABEL: @test_flags_swdiv_nochk(
+// CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load double, double* @c, align 8
+// CHECK-NEXT:[[ADD:%.*]] = fadd double [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret double [[ADD]]
+//
+double test_flags_swdiv_nochk() {
+  return __swdiv_nochk(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_swdivs_nochk(
+// CHECK:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load float, float* @f, align 4
+// CHECK-NEXT:[[ADD:%.*]] = fadd float [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret float [[ADD]]
+//
+float test_flags_swdivs_nochk() {
+  return __swdivs_nochk(d, e) + f;
+}
+
+// CHECK-LABEL: @test_builtin_ppc_swdiv_nochk(
+// CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret double [[SWDIV_NOCHK]]
+//
+double test_builtin_ppc_swdiv_nochk() {
+  return __builtin_ppc_swdiv_nochk(a, b);
+}
+
+// CHECK-LABEL: @test_builtin_ppc_swdivs_nochk(
+// CHECK:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:ret float [[SWDIV_NOCHK]]
+//
+float test_builtin_ppc_swdivs_nochk() {
+  return __builtin_ppc_swdivs_nochk(d, e);
+}
+
+// CHECK-LABEL: @test_flags_builtin_ppc_swdiv_nochk(
+// CHECK:[[TMP0:%.*]] = load double, double* @a, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load double, double* @b, align 8
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast double [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load double, double* @c, align 8
+// CHECK-NEXT:[[ADD:%.*]] = fadd double [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret double [[ADD]]
+//
+double test_flags_builtin_ppc_swdiv_nochk() {
+  return __builtin_ppc_swdiv_nochk(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_builtin_ppc_swdivs_nochk(
+// CHECK:[[TMP0:%.*]] = load float, float* @d, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load float, float* @e, align 4
+// CHECK-NEXT:[[SWDIV_NOCHK:%.*]] = fdiv fast float [[TMP0]], [[TMP1]]
+// CHECK-NEXT:[[TMP2:%.*]] = load float, float* @f, align 4
+// CHECK-NEXT:[[ADD:%.*]] = fadd float [[SWDIV_NOCHK]], [[TMP2]]
+// CHECK-NEXT:ret float [[ADD]]
+//
+float test_flags_builtin_ppc_swdivs_nochk() {
+  return __builtin_ppc_swdivs_nochk(d, e) + f;
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ 

[PATCH] D105984: [PowerPC] Restore FastMathFlags of Builder for Vector FDiv Builtins

[Kamau Bridgeman via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGfd855c24c72c: [PowerPC] Restore FastMathFlags of Builder for 
Vector FDiv Builtins (authored by quinnp, committed by kamaub).

Changed prior to commit:
  https://reviews.llvm.org/D105984?vs=359338&id=360129#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105984/new/

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Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-fastmath.c

Index: clang/test/CodeGen/builtins-ppc-fastmath.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-fastmath.c
@@ -0,0 +1,70 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern vector float a;
+extern vector float b;
+extern vector float c;
+extern vector double d;
+extern vector double e;
+extern vector double f;
+
+// CHECK-LABEL: @test_flags_recipdivf(
+// CHECK:[[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP3:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[RECIPDIV:%.*]] = fdiv fast <4 x float> [[TMP2]], [[TMP3]]
+// CHECK-NEXT:[[TMP4:%.*]] = load <4 x float>, <4 x float>* @c, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <4 x float> [[RECIPDIV]], [[TMP4]]
+// CHECK-NEXT:ret <4 x float> [[ADD]]
+//
+vector float test_flags_recipdivf() {
+  return __builtin_ppc_recipdivf(a, b) + c;
+}
+
+// CHECK-LABEL: @test_flags_recipdivd(
+// CHECK:[[TMP0:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP3:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[RECIPDIV:%.*]] = fdiv fast <2 x double> [[TMP2]], [[TMP3]]
+// CHECK-NEXT:[[TMP4:%.*]] = load <2 x double>, <2 x double>* @f, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <2 x double> [[RECIPDIV]], [[TMP4]]
+// CHECK-NEXT:ret <2 x double> [[ADD]]
+//
+vector double test_flags_recipdivd() {
+  return __builtin_ppc_recipdivd(d, e) + f;
+}
+
+// CHECK-LABEL: @test_flags_rsqrtf(
+// CHECK:[[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, <4 x float>* @a, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP1]])
+// CHECK-NEXT:[[RSQRT:%.*]] = fdiv fast <4 x float> , [[TMP2]]
+// CHECK-NEXT:[[TMP3:%.*]] = load <4 x float>, <4 x float>* @b, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <4 x float> [[RSQRT]], [[TMP3]]
+// CHECK-NEXT:ret <4 x float> [[ADD]]
+//
+vector float test_flags_rsqrtf() {
+  return __builtin_ppc_rsqrtf(a) + b;
+}
+
+// CHECK-LABEL: @test_flags_rsqrtd(
+// CHECK:[[TMP0:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP1:%.*]] = load <2 x double>, <2 x double>* @d, align 16
+// CHECK-NEXT:[[TMP2:%.*]] = call fast <2 x double> @llvm.sqrt.v2f64(<2 x double> [[TMP1]])
+// CHECK-NEXT:[[RSQRT:%.*]] = fdiv fast <2 x double> , [[TMP2]]
+// CHECK-NEXT:[[TMP3:%.*]] = load <2 x double>, <2 x double>* @e, align 16
+// CHECK-NEXT:[[ADD:%.*]] = fadd <2 x double> [[RSQRT]], [[TMP3]]
+// CHECK-NEXT:ret <2 x double> [[ADD]]
+//
+vector double test_flags_rsqrtd() {
+  return __builtin_ppc_rsqrtd(d) + e;
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -15280,6 +15280,7 @@
   case PPC::BI__builtin_ppc_recipdivd:
   case PPC::BI__builtin_ppc_rsqrtf:
   case PPC::BI__builtin_ppc_rsqrtd: {
+FastMathFlags FMF = Builder.getFastMathFlags();
 Builder.getFastMathFlags().setFast();
 llvm::Type *ResultType = ConvertType(E->getType());
 Value *X = EmitScalarExpr(E->getArg(0));
@@ -15287,11 +15288,15 @@
 if (BuiltinID == PPC::BI__builtin_ppc_recipdivf ||
 BuiltinID == PPC::BI__builtin_ppc_recipdivd) {
   Value *Y = EmitScalarExpr(E->getArg(1));
-  return Builder.CreateFDiv(X, Y, "recipdiv");
+  Value *FDiv = Builder.CreateFDiv(X, Y, "recipdiv");
+  Builder.getFastMathFlags() &= (FMF);

[PATCH] D105834: [PowerPC] Semachecking for XL compat builtin icbt

[Kamau Bridgeman via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG59d2ba2a3de9: [PowerPC] Semachecking for XL compat builtin 
icbt (authored by quinnp, committed by kamaub).

Changed prior to commit:
  https://reviews.llvm.org/D105834?vs=359398&id=360165#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
  clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
@@ -94,7 +94,6 @@
 }
 declare void @llvm.ppc.iospace.sync()
 
-; FIXME: __icbt is only valid for pwr8 and up.
 define dso_local void @test_builtin_ppc_icbt() {
 ; CHECK-LABEL: test_builtin_ppc_icbt:
 ; CHECK:   # %bb.0: # %entry
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
@@ -60,18 +60,3 @@
   ret void
 }
 declare void @llvm.ppc.iospace.sync()
-
-; FIXME: __icbt is only valid for pwr8 and up.
-define dso_local void @test_builtin_ppc_icbt() {
-; CHECK-LABEL: test_builtin_ppc_icbt:
-; CHECK:   # %bb.0: # %entry
-; CHECK-NEXT:lwz 3, -8(1)
-; CHECK-NEXT:icbt 0, 0, 3
-; CHECK-NEXT:blr
-entry:
-  %a = alloca i8*, align 8
-  %0 = load i8*, i8** %a, align 8
-  call void @llvm.ppc.icbt(i8* %0)
-  ret void
-}
-declare void @llvm.ppc.icbt(i8*)
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1534,7 +1534,6 @@
 [IntrArgMemOnly, NoCapture>]>;
   def int_ppc_dcbz  : GCCBuiltin<"__builtin_ppc_dcbz">,
   Intrinsic<[], [llvm_ptr_ty], []>;
-// FIXME: __icbt is only valid for pwr8 and up.
   def int_ppc_icbt : GCCBuiltin<"__builtin_ppc_icbt">,
  Intrinsic<[], [llvm_ptr_ty], []>;
   
Index: clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-sync.c
@@ -1,4 +1,3 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
 // RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
@@ -14,15 +13,13 @@
 extern void *c;
 
 // CHECK-LABEL: @test_popcntb(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = load i64, i64* @a, align 8
+// CHECK:[[TMP0:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[TMP1:%.*]] = load i64, i64* @a, align 8
 // CHECK-NEXT:[[POPCNTB:%.*]] = call i64 @llvm.ppc.popcntb.i64.i64(i64 [[TMP0]])
 // CHECK-NEXT:ret i64 [[POPCNTB]]
 //
 // CHECK-32-LABEL: @test_popcntb(
-// CHECK-32-NEXT:  entry:
-// CHECK-32-NEXT:[[TMP0:%.*]] = load i32, i32* @a, align 4
+// CHECK-32:[[TMP0:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[TMP1:%.*]] = load i32, i32* @a, align 4
 // CHECK-32-NEXT:[[POPCNTB:%.*]] = call i32 @llvm.ppc.popcntb.i32.i32(i32 [[TMP0]])
 // CHECK-32-NEXT:ret i32 [[POPCNTB]]
@@ -32,13 +29,11 @@
 }
 
 // CHECK-LABEL: @test_eieio(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:call void @llvm.ppc.eieio()
+// CHECK:call void @llvm.ppc.eieio()
 // CHECK-NEXT:ret void
 //
 // CHECK-32-LABEL: @test_eieio(
-// CHECK-32-NEXT:  entry:
-// CHECK-32-NEXT:call void @llvm.ppc.eieio()
+// CHECK-32:call void @llvm.ppc.eieio()
 // CHECK-32-NEXT:ret void
 //
 void test_eieio() {
@@ -46,13 +41,11 @@
 }
 
 // CHECK-LABEL: @test_iospace_eieio(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:call void @llvm.ppc.iospace.eieio()
+// CHECK:call void @llvm.ppc.iospace.eieio()
 // CHECK-NEXT:ret void
 //
 // CHECK-32-LABEL: @test_iospace_eieio(
-// CHECK-32-NEXT:  entry:
-// CHECK-32-NEXT:call void @llvm.ppc.iospace.eieio()
+// CHECK-32:call void @llvm.ppc.iospace.eieio()
 // CHECK-32-NEXT:ret void
 //
 void test_iospace_eieio() {
@@ -60,13 +53,11 @@
 }
 
 // CHECK-LABEL: @test_isync(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:call void @llvm.ppc.isync()
+// CHECK:call void @llvm.ppc.isync()
 // CHECK-NEXT:ret void
 //
 // CHECK-32-LABEL: @test_isync(
-// CHECK-32-NEXT:  entry:
-// CHECK-32-NEXT:c

[PATCH] D121837: [OpenMP][FIX] Allow device constructors for AMD GPU

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub added a comment.

The test cases added with this commit failed on clang-ppc64be-linux-lnt # 13809 
 could you please 
revert this change, and recommit with the test case corrected? thank you.


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[PATCH] D125499: Enabling the detection of devtoolset-11 toolchain.

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub created this revision.
kamaub added reviewers: phosek, tstellar, nemanjai, lei.
Herald added a project: All.
kamaub requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

This patch allows systems to build the llvm-project with the devtoolset-11
toolchain.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125499

Files:
  clang/lib/Driver/ToolChains/Gnu.cpp


Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2151,6 +2151,7 @@
   if (SysRoot.empty() && TargetTriple.getOS() == llvm::Triple::Linux) {
 // Yet, still look for RHEL/CentOS devtoolsets and gcc-toolsets.
 Prefixes.push_back("/opt/rh/gcc-toolset-10/root/usr");
+Prefixes.push_back("/opt/rh/devtoolset-11/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-10/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-9/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-8/root/usr");


Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2151,6 +2151,7 @@
   if (SysRoot.empty() && TargetTriple.getOS() == llvm::Triple::Linux) {
 // Yet, still look for RHEL/CentOS devtoolsets and gcc-toolsets.
 Prefixes.push_back("/opt/rh/gcc-toolset-10/root/usr");
+Prefixes.push_back("/opt/rh/devtoolset-11/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-10/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-9/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-8/root/usr");
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[PATCH] D125499: Enabling the detection of devtoolset-11 toolchain.

[Kamau Bridgeman via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG99639e5a3e6e: Enabling the detection of devtoolset-11 
toolchain. (authored by kamaub).

Changed prior to commit:
  https://reviews.llvm.org/D125499?vs=429059&id=430013#toc

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp


Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2150,7 +2150,9 @@
   // Non-Solaris is much simpler - most systems just go with "/usr".
   if (SysRoot.empty() && TargetTriple.getOS() == llvm::Triple::Linux) {
 // Yet, still look for RHEL/CentOS devtoolsets and gcc-toolsets.
+Prefixes.push_back("/opt/rh/gcc-toolset-11/root/usr");
 Prefixes.push_back("/opt/rh/gcc-toolset-10/root/usr");
+Prefixes.push_back("/opt/rh/devtoolset-11/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-10/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-9/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-8/root/usr");


Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2150,7 +2150,9 @@
   // Non-Solaris is much simpler - most systems just go with "/usr".
   if (SysRoot.empty() && TargetTriple.getOS() == llvm::Triple::Linux) {
 // Yet, still look for RHEL/CentOS devtoolsets and gcc-toolsets.
+Prefixes.push_back("/opt/rh/gcc-toolset-11/root/usr");
 Prefixes.push_back("/opt/rh/gcc-toolset-10/root/usr");
+Prefixes.push_back("/opt/rh/devtoolset-11/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-10/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-9/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-8/root/usr");
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[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub added a reviewer: kamaub.
kamaub added a comment.

This patch seems almost ready to land to me, I'm just a bit concerned about the 
testing coverage, 
is the little endian testing case suppose to target `pwr7` as the big endian 
test does? The default 
FileCheck line seems redundant to me, did I misunderstand?




Comment at: llvm/test/CodeGen/PowerPC/test-vector-insert.ll:8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s
+

It seems like this run line is redundant, it produces the same assembly as the 
big endian specific line above. Maybe the `-mcpu=pwr7` can be moved to the 
first Little-endian specific run line? That line currently only test the target 
cpu of the test machine.


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[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:3518
+// valid. The argument must be either a 'float' or a 'double'.
+bool Sema::CheckPPCTestDataClassType(CallExpr *TheCall) {
+  QualType ArgType = TheCall->getArg(0)->getType();

lei wrote:
> I don't think this need to be function in the Sema class.  It can just be a 
> static function.
This is a great suggestion, I'm wondering if the function is even needed at all 
though since the code block is quite small and only called once, having it 
inside the case statement seems more readable to me. 


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[PATCH] D110824: [PowerPC] Fix to guard fetch and cas 64-bit builtin versions

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub created this revision.
kamaub added reviewers: PowerPC, nemanjai, lei, amyk, stefanp.
Herald added subscribers: shchenz, kbarton.
kamaub requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

The builtins: `__compare_and_swaplp`, `__fetch_and_addlp`,
` __fetch_and_andlp`, `__fetch_and_orlp`, `__fetch_and_swaplp` are
64 bit only. This patch ensures the compiler produces an error in 32 bit mode.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110824

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fetch-cas-64bit-only-error.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-fetch-cas-64bit-only-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-fetch-cas-64bit-only-error.c
@@ -0,0 +1,24 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr8 \
+// RUN:  -verify %s
+
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c); // expected-error {{this builtin is 
only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_addlp(long a, long b) {
+  __fetch_and_addlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {
+  __fetch_and_andlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {
+  __fetch_and_orlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_swaplp(unsigned long a, unsigned long b) {
+  __fetch_and_swaplp(&a, b); // expected-error {{this builtin is only 
available on 64-bit targets}}
+}
+
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3297,6 +3297,11 @@
   case PPC::BI__builtin_ppc_addex:
   case PPC::BI__builtin_darn:
   case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_ppc_compare_and_swaplp:
+  case PPC::BI__builtin_ppc_fetch_and_addlp:
+  case PPC::BI__builtin_ppc_fetch_and_andlp:
+  case PPC::BI__builtin_ppc_fetch_and_orlp:
+  case PPC::BI__builtin_ppc_fetch_and_swaplp:
 return true;
   }
   return false;


Index: clang/test/CodeGen/builtins-ppc-xlcompat-fetch-cas-64bit-only-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-fetch-cas-64bit-only-error.c
@@ -0,0 +1,24 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr8 \
+// RUN:  -verify %s
+
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_addlp(long a, long b) {
+  __fetch_and_addlp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {
+  __fetch_and_andlp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {
+  __fetch_and_orlp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_swaplp(unsigned long a, unsigned long b) {
+  __fetch_and_swaplp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3297,6 +3297,11 @@
   case PPC::BI__builtin_ppc_addex:
   case PPC::BI__builtin_darn:
   case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_ppc_compare_and_swaplp:
+  case PPC::BI__builtin_ppc_fetch_and_addlp:
+  case PPC::BI__builtin_ppc_fetch_and_andlp:
+  case PPC::BI__builtin_ppc_fetch_and_orlp:
+  case PPC::BI__builtin_ppc_fetch_and_swaplp:
 return true;
   }
   return false;
___
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[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub updated this revision to Diff 376300.
kamaub added a comment.

Rebasing this patch and addressing review comments

An upstream commit removed the need for this patch to modify a few
test cases so it has been rebased to remain up-to-date, also addressing
review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109599/new/

https://reviews.llvm.org/D109599

Files:
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/AST/ast-dump-ppc-types.c
  clang/test/CodeGen/ppc-mma-types.c
  clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
  clang/test/Sema/ppc-mma-builtins.c
  clang/test/Sema/ppc-paired-vector-builtins.c

Index: clang/test/Sema/ppc-paired-vector-builtins.c
===
--- /dev/null
+++ clang/test/Sema/ppc-paired-vector-builtins.c
@@ -0,0 +1,28 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -target-feature -paired-vector-memops -fsyntax-only %s -verify
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr9 \
+// RUN:   -fsyntax-only %s -verify
+
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __vector_pair res;
+  __builtin_vsx_assemble_pair(&res, vc, vc); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+}
+
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __builtin_vsx_disassemble_pair(resp, (__vector_pair*)vpp); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+}
+
+void test3(const __vector_pair *vpp, signed long long offset, const __vector_pair *vp2) {
+  __vector_pair vp = __builtin_vsx_lxvp(offset, vpp); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+  __builtin_vsx_stxvp(vp, offset, vp2); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+}
+
+void test4(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __vector_quad vq = *((__vector_quad *)vqp);
+  __vector_pair vp = *((__vector_pair *)vpp);
+  __builtin_mma_xxmtacc(&vq); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+  *((__vector_quad *)resp) = vq;
+}
+
+
Index: clang/test/Sema/ppc-mma-builtins.c
===
--- /dev/null
+++ clang/test/Sema/ppc-mma-builtins.c
@@ -0,0 +1,33 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -target-feature -mma -fsyntax-only %s -verify
+
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __vector_pair res;
+  __builtin_vsx_assemble_pair(&res, vc, vc);
+}
+
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __builtin_vsx_disassemble_pair(resp, (__vector_pair*)vpp);
+}
+
+void test3(const __vector_pair *vpp, signed long offset, const __vector_pair *vp2) {
+  __vector_pair vp = __builtin_vsx_lxvp(offset, vpp);
+  __builtin_vsx_stxvp(vp, offset, vp2);
+}
+
+void test4(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __vector_quad vq = *((__vector_quad *)vqp);
+  __vector_pair vp = *((__vector_pair *)vpp);
+  __builtin_mma_xxmtacc(&vq); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+  *((__vector_quad *)resp) = vq;
+}
+
+void test5(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __vector_quad vq = *((__vector_quad *)vqp);
+  __vector_pair vp = *((__vector_pair *)vpp);
+  __builtin_mma_pmxvf64ger(&vq, vp, vc, 0, 0); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+  *((__vector_quad *)resp) = vq;
+}
+
+
Index: clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
===
--- clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
+++ clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
@@ -1,4 +1,8 @@
-// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future %s \
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr10 %s \
+// RUN:   -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr9 %s \
+// RUN:   -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr8 %s \
 // RUN:   -emit-llvm -o - | FileCheck %s
 
 // CHECK: _Z2f1Pu13__vector_quad
Index: clang/test/CodeGen/ppc-mma-types.c
===
--- clang/test/CodeGen/ppc-mma-types.c
+++ clang/test/CodeGen/ppc-mma-types.c
@@ -1,5 +1,9 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.p

[PATCH] D110824: [PowerPC] Fix to guard fetch and cas 64-bit builtin versions

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub updated this revision to Diff 376312.
kamaub added a comment.

Rebasing patch to get past intermittent test-suite failure


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110824/new/

https://reviews.llvm.org/D110824

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-fetch-cas-64bit-only-error.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-fetch-cas-64bit-only-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-fetch-cas-64bit-only-error.c
@@ -0,0 +1,24 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr8 \
+// RUN:  -verify %s
+
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c); // expected-error {{this builtin is 
only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_addlp(long a, long b) {
+  __fetch_and_addlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {
+  __fetch_and_andlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {
+  __fetch_and_orlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_swaplp(unsigned long a, unsigned long b) {
+  __fetch_and_swaplp(&a, b); // expected-error {{this builtin is only 
available on 64-bit targets}}
+}
+
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3297,6 +3297,11 @@
   case PPC::BI__builtin_ppc_addex:
   case PPC::BI__builtin_darn:
   case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_ppc_compare_and_swaplp:
+  case PPC::BI__builtin_ppc_fetch_and_addlp:
+  case PPC::BI__builtin_ppc_fetch_and_andlp:
+  case PPC::BI__builtin_ppc_fetch_and_orlp:
+  case PPC::BI__builtin_ppc_fetch_and_swaplp:
 return true;
   }
   return false;


Index: clang/test/CodeGen/builtins-ppc-xlcompat-fetch-cas-64bit-only-error.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-fetch-cas-64bit-only-error.c
@@ -0,0 +1,24 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-cpu pwr8 \
+// RUN:  -verify %s
+
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_addlp(long a, long b) {
+  __fetch_and_addlp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {
+  __fetch_and_andlp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {
+  __fetch_and_orlp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_swaplp(unsigned long a, unsigned long b) {
+  __fetch_and_swaplp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3297,6 +3297,11 @@
   case PPC::BI__builtin_ppc_addex:
   case PPC::BI__builtin_darn:
   case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_ppc_compare_and_swaplp:
+  case PPC::BI__builtin_ppc_fetch_and_addlp:
+  case PPC::BI__builtin_ppc_fetch_and_andlp:
+  case PPC::BI__builtin_ppc_fetch_and_orlp:
+  case PPC::BI__builtin_ppc_fetch_and_swaplp:
 return true;
   }
   return false;
___
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[PATCH] D110824: [PowerPC] Fix to guard fetch and cas 64-bit builtin versions

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub updated this revision to Diff 376962.
kamaub added a comment.

Moving test case to correct file before commiting as request in review comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110824/new/

https://reviews.llvm.org/D110824

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -104,6 +104,25 @@
 int test_darn_raw() {
   return __darn_raw(); //expected-error {{this builtin is only available on 
64-bit targets}}
 }
+
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c); // expected-error {{this builtin is 
only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_addlp(long a, long b) {
+  __fetch_and_addlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {
+  __fetch_and_andlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {
+  __fetch_and_orlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_swaplp(unsigned long a, unsigned long b) {
+  __fetch_and_swaplp(&a, b); // expected-error {{this builtin is only 
available on 64-bit targets}}
+}
 #endif
 
 unsigned long test_mfspr(void) {
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3297,6 +3297,11 @@
   case PPC::BI__builtin_ppc_addex:
   case PPC::BI__builtin_darn:
   case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_ppc_compare_and_swaplp:
+  case PPC::BI__builtin_ppc_fetch_and_addlp:
+  case PPC::BI__builtin_ppc_fetch_and_andlp:
+  case PPC::BI__builtin_ppc_fetch_and_orlp:
+  case PPC::BI__builtin_ppc_fetch_and_swaplp:
 return true;
   }
   return false;


Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -104,6 +104,25 @@
 int test_darn_raw() {
   return __darn_raw(); //expected-error {{this builtin is only available on 64-bit targets}}
 }
+
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_addlp(long a, long b) {
+  __fetch_and_addlp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {
+  __fetch_and_andlp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {
+  __fetch_and_orlp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_swaplp(unsigned long a, unsigned long b) {
+  __fetch_and_swaplp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
 #endif
 
 unsigned long test_mfspr(void) {
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3297,6 +3297,11 @@
   case PPC::BI__builtin_ppc_addex:
   case PPC::BI__builtin_darn:
   case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_ppc_compare_and_swaplp:
+  case PPC::BI__builtin_ppc_fetch_and_addlp:
+  case PPC::BI__builtin_ppc_fetch_and_andlp:
+  case PPC::BI__builtin_ppc_fetch_and_orlp:
+  case PPC::BI__builtin_ppc_fetch_and_swaplp:
 return true;
   }
   return false;
___
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[PATCH] D110824: [PowerPC] Fix to guard fetch and cas 64-bit builtin versions

[Kamau Bridgeman via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG83289665200b: [PowerPC] Fix to guard fetch and cas 64-bit 
builtin versions (authored by kamaub).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110824/new/

https://reviews.llvm.org/D110824

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -104,6 +104,25 @@
 int test_darn_raw() {
   return __darn_raw(); //expected-error {{this builtin is only available on 
64-bit targets}}
 }
+
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c); // expected-error {{this builtin is 
only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_addlp(long a, long b) {
+  __fetch_and_addlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {
+  __fetch_and_andlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {
+  __fetch_and_orlp(&a, b); // expected-error {{this builtin is only available 
on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_swaplp(unsigned long a, unsigned long b) {
+  __fetch_and_swaplp(&a, b); // expected-error {{this builtin is only 
available on 64-bit targets}}
+}
 #endif
 
 unsigned long test_mfspr(void) {
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3297,6 +3297,11 @@
   case PPC::BI__builtin_ppc_addex:
   case PPC::BI__builtin_darn:
   case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_ppc_compare_and_swaplp:
+  case PPC::BI__builtin_ppc_fetch_and_addlp:
+  case PPC::BI__builtin_ppc_fetch_and_andlp:
+  case PPC::BI__builtin_ppc_fetch_and_orlp:
+  case PPC::BI__builtin_ppc_fetch_and_swaplp:
 return true;
   }
   return false;


Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -104,6 +104,25 @@
 int test_darn_raw() {
   return __darn_raw(); //expected-error {{this builtin is only available on 64-bit targets}}
 }
+
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_addlp(long a, long b) {
+  __fetch_and_addlp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {
+  __fetch_and_andlp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {
+  __fetch_and_orlp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+void test_builtin_ppc_fetch_and_swaplp(unsigned long a, unsigned long b) {
+  __fetch_and_swaplp(&a, b); // expected-error {{this builtin is only available on 64-bit targets}}
+}
 #endif
 
 unsigned long test_mfspr(void) {
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3297,6 +3297,11 @@
   case PPC::BI__builtin_ppc_addex:
   case PPC::BI__builtin_darn:
   case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_ppc_compare_and_swaplp:
+  case PPC::BI__builtin_ppc_fetch_and_addlp:
+  case PPC::BI__builtin_ppc_fetch_and_andlp:
+  case PPC::BI__builtin_ppc_fetch_and_orlp:
+  case PPC::BI__builtin_ppc_fetch_and_swaplp:
 return true;
   }
   return false;
___
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[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units

[Kamau Bridgeman via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG8737c74fab3a: [PowerPC][MMA] Allow MMA builtin types in 
pre-P10 compilation units (authored by kamaub).
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D109599?vs=376300&id=377172#toc

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Files:
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/AST/ast-dump-ppc-types.c
  clang/test/CodeGen/ppc-mma-types.c
  clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
  clang/test/Sema/ppc-mma-builtins.c
  clang/test/Sema/ppc-paired-vector-builtins.c
  llvm/test/CodeGen/PowerPC/mma-acc-memops.ll

Index: llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
===
--- llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
+++ llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
@@ -5,6 +5,18 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
 ; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=BE-PAIRED
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
+; RUN:   -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:   | FileCheck %s --check-prefix=LE-PWR9
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
+; RUN:   -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:   | FileCheck %s --check-prefix=LE-PWR8
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
+; RUN:   -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu < %s \
+; RUN:   | FileCheck %s --check-prefix=BE-PWR9
+; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
+; RUN:   -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu < %s \
+; RUN:   | FileCheck %s --check-prefix=BE-PWR8
 
 @f = common dso_local local_unnamed_addr global <512 x i1> zeroinitializer, align 16
 @g = common dso_local local_unnamed_addr global <256 x i1> zeroinitializer, align 16
@@ -35,6 +47,78 @@
 ; BE-PAIRED-NEXT:stxv vs3, 176(r3)
 ; BE-PAIRED-NEXT:stxv vs2, 160(r3)
 ; BE-PAIRED-NEXT:blr
+;
+; LE-PWR9-LABEL: testLdSt:
+; LE-PWR9:   # %bb.0: # %entry
+; LE-PWR9-NEXT:addis r3, r2, f@toc@ha
+; LE-PWR9-NEXT:addi r3, r3, f@toc@l
+; LE-PWR9-NEXT:lxv vs1, 96(r3)
+; LE-PWR9-NEXT:lxv vs0, 64(r3)
+; LE-PWR9-NEXT:lxv vs2, 112(r3)
+; LE-PWR9-NEXT:stxv vs1, 160(r3)
+; LE-PWR9-NEXT:lxv vs1, 80(r3)
+; LE-PWR9-NEXT:stxv vs2, 176(r3)
+; LE-PWR9-NEXT:stxv vs0, 128(r3)
+; LE-PWR9-NEXT:stxv vs1, 144(r3)
+; LE-PWR9-NEXT:blr
+;
+; LE-PWR8-LABEL: testLdSt:
+; LE-PWR8:   # %bb.0: # %entry
+; LE-PWR8-NEXT:addis r3, r2, f@toc@ha
+; LE-PWR8-NEXT:li r4, 96
+; LE-PWR8-NEXT:li r5, 112
+; LE-PWR8-NEXT:addi r3, r3, f@toc@l
+; LE-PWR8-NEXT:lxvd2x vs0, r3, r4
+; LE-PWR8-NEXT:li r4, 64
+; LE-PWR8-NEXT:lxvd2x vs1, r3, r5
+; LE-PWR8-NEXT:li r5, 80
+; LE-PWR8-NEXT:lxvd2x vs2, r3, r4
+; LE-PWR8-NEXT:lxvd2x vs3, r3, r5
+; LE-PWR8-NEXT:li r4, 176
+; LE-PWR8-NEXT:li r5, 160
+; LE-PWR8-NEXT:stxvd2x vs1, r3, r4
+; LE-PWR8-NEXT:li r4, 144
+; LE-PWR8-NEXT:stxvd2x vs0, r3, r5
+; LE-PWR8-NEXT:li r5, 128
+; LE-PWR8-NEXT:stxvd2x vs3, r3, r4
+; LE-PWR8-NEXT:stxvd2x vs2, r3, r5
+; LE-PWR8-NEXT:blr
+;
+; BE-PWR9-LABEL: testLdSt:
+; BE-PWR9:   # %bb.0: # %entry
+; BE-PWR9-NEXT:addis r3, r2, f@toc@ha
+; BE-PWR9-NEXT:addi r3, r3, f@toc@l
+; BE-PWR9-NEXT:lxv vs1, 96(r3)
+; BE-PWR9-NEXT:lxv vs0, 64(r3)
+; BE-PWR9-NEXT:lxv vs2, 112(r3)
+; BE-PWR9-NEXT:stxv vs1, 160(r3)
+; BE-PWR9-NEXT:lxv vs1, 80(r3)
+; BE-PWR9-NEXT:stxv vs2, 176(r3)
+; BE-PWR9-NEXT:stxv vs0, 128(r3)
+; BE-PWR9-NEXT:stxv vs1, 144(r3)
+; BE-PWR9-NEXT:blr
+;
+; BE-PWR8-LABEL: testLdSt:
+; BE-PWR8:   # %bb.0: # %entry
+; BE-PWR8-NEXT:addis r3, r2, f@toc@ha
+; BE-PWR8-NEXT:li r4, 96
+; BE-PWR8-NEXT:li r5, 112
+; BE-PWR8-NEXT:addi r3, r3, f@toc@l
+; BE-PWR8-NEXT:lxvd2x vs0, r3, r4
+; BE-PWR8-NEXT:li r4, 64
+; BE-PWR8-NEXT:lxvd2x vs1, r3, r5
+; BE-PWR8-NEXT:li r5, 80
+; BE-PWR8-NEXT:lxvd2x vs2, r3, r4
+; BE-PWR8-NEXT:lxvd2x vs3, r3, r5
+; BE-PWR8-NEXT:li r4, 176
+; BE-PWR8-NEXT:li r5, 160
+; BE-PWR8-NEXT:stxvd2x vs1, r3, r4
+; BE-PWR8-NEXT:li r4, 144
+; BE-PWR8-NEXT:stxvd2x vs0, r3, r5
+; BE-PWR8-NEXT:li r5, 128
+; BE-PWR8-NEXT:stxvd2x vs3, r3, r4
+; BE-PWR8-NEXT:stxvd2x vs2, r3, r5
+; BE-PWR8-NEXT:blr
 entry:
   %arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 1
   %0 = load <512 x i1>, <512 x i1>* %arrayidx, align 64
@@ -78,6 +162,84 @@
 ; BE-PAIRED-NEXT:stxv vs3, 48(r3)
 ;

[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub marked an inline comment as done.
kamaub added a comment.

Updated an existing test for the backend with pwr8 and pwr9 be/le targets 
during commit


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[PATCH] D113451: [PowerPC] [Clang] Enable Intel intrinsics support on FreeBSD

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub added a comment.

Test case `clang/test/CodeGen/ppc-mm-malloc.c` fails on powerpc BE buildbots 
with this changeset
https://lab.llvm.org/buildbot/#/builders/93/builds/6031
https://lab.llvm.org/buildbot/#/builders/100/builds/10836
https://lab.llvm.org/buildbot/#/builders/52/builds/12719

  *** TEST 'Clang :: CodeGen/ppc-mm-malloc.c' FAILED 

  Script:
  --
  : 'RUN: at line 9';   
/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage1/bin/clang
 -target powerpc64-unknown-linux-gnu -S -emit-llvm 
/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/clang/test/CodeGen/ppc-mm-malloc.c
 -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | 
/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage1/bin/FileCheck
 
/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/clang/test/CodeGen/ppc-mm-malloc.c
  : 'RUN: at line 10';   
/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage1/bin/clang
 -target powerpc64-unknown-freebsd13.0 -S -emit-llvm 
/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/clang/test/CodeGen/ppc-mm-malloc.c
 -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | 
/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage1/bin/FileCheck
 
/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/clang/test/CodeGen/ppc-mm-malloc.c
  --
  Exit Code: 2
  Command Output (stderr):
  --
  In file included from 
/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/clang/test/CodeGen/ppc-mm-malloc.c:12:
  In file included from 
/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage1/lib/clang/14.0.0/include/ppc_wrappers/mm_malloc.h:15:
  In file included from /usr/include/stdlib.h:25:
  In file included from /usr/include/bits/libc-header-start.h:33:
  In file included from /usr/include/features.h:434:
  /usr/include/gnu/stubs.h:14:11: fatal error: 'gnu/stubs-64-v2.h' file not 
found
  # include 
^~~
  1 error generated.
  FileCheck error: '' is empty.
  FileCheck command line:  
/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/stage1/bin/FileCheck
 
/home/buildbots/ppc64be-clang-multistage-test/clang-ppc64be-multistage/llvm/clang/test/CodeGen/ppc-mm-malloc.c
  --
  




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[PATCH] D135245: [clang][Tooling] Move STL recognizer to its own library

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub added a comment.

This change causes a linking failure during the `check-all` testing of 
'clang-tools-extra' on the clang-ppc64le-rhel #22596 
 and 
clang-ppc64le-linux-multistage #23864 
 build bots, please 
address this failure as soon as possible.


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[PATCH] D125499: Enabling the detection of devtoolset-11 toolchain.

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub added a comment.

In D125499#3541689 , @tstellar wrote:

> I'm curious what is your system configuration where this patch actually 
> allows for detection of devtoolset?  I noticed that if clang and gcc are both 
> installed to /usr/, then driver will pick the gcc in /usr/ over the one in 
> /opt/rh/.../

The machine I needed the devtoolset-11 path for is not the same as the current 
bot failure trying to be addressed in https://reviews.llvm.org/D127310 but all 
there isn'y anything special to the configuration, I have 
`/opt/rh/devtoolset-11/root/usr` installed as normal from the yum repositories 
and I had a `check-all` build failure without this patch

  ~/Github/build $ ninja check-all
  [25/1032] Generating ScudoUnitTestsObjects.wrappers_cpp_test.cpp.powerpc64.o
  FAILED: 
projects/compiler-rt/lib/scudo/standalone/tests/ScudoUnitTestsObjects.wrappers_cpp_test.cpp.powerpc64.o
  cd /home/kamaub/Github/build/projects/compiler-rt/lib/scudo/standalone/tests 
&& /home/kamaub/Github/build/./bin/clang -g -Wno-suggest-override 
-DGTEST_NO_LLVM_SUPPORT=1 -DGTEST_HAS_RTTI=0 
-I/home/kamaub/Github/llvm-project/llvm/utils/unittest/googletest/include 
-I/home/kamaub/Github/llvm-project/llvm/utils/unittest/googletest 
-I/home/kamaub/Github/llvm-project/compiler-rt/include 
-I/home/kamaub/Github/llvm-project/compiler-rt/lib 
-I/home/kamaub/Github/llvm-project/compiler-rt/lib/scudo/standalone 
-I/home/kamaub/Github/llvm-project/compiler-rt/lib/scudo/standalone/include 
-DGTEST_HAS_RTTI=0 -g -Wno-mismatched-new-delete -m64 -c -o 
ScudoUnitTestsObjects.wrappers_cpp_test.cpp.powerpc64.o 
/home/kamaub/Github/llvm-project/compiler-rt/lib/scudo/standalone/tests/wrappers_cpp_test.cpp
  
/home/kamaub/Github/llvm-project/compiler-rt/lib/scudo/standalone/tests/wrappers_cpp_test.cpp:118:19:
 error: no member named 'make_unique' in namespace 'std'
  NoTags = std::make_unique();
   ~^
  
/home/kamaub/Github/llvm-project/compiler-rt/lib/scudo/standalone/tests/wrappers_cpp_test.cpp:118:66:
 error: expected '(' for function-style cast or type construction
  NoTags = std::make_unique();
~~~^
  
/home/kamaub/Github/llvm-project/compiler-rt/lib/scudo/standalone/tests/wrappers_cpp_test.cpp:118:68:
 error: expected expression
  NoTags = std::make_unique();
 ^
  3 errors generated.




Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:2156
 Prefixes.push_back("/opt/rh/devtoolset-10/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-9/root/usr");
 Prefixes.push_back("/opt/rh/devtoolset-8/root/usr");

tstellar wrote:
> MaskRay wrote:
> > The detection is wasted every Linux user (even if they don't use 
> > RedHat/Fedora). Some may need to be refactored to detect `/opt/rh` first. 
> > Some ancient devtoolset-* may be deleted now.
> @kamaub Are you planning to address these comments in a follow up change?
@tstellar Sorry I missed this, thank you for pointing it out, I should have 
addressed this in a follow-up chain but I email notifications are not working 
as only saw these comment while taking a look at 
https://reviews.llvm.org/D127310




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[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub added a comment.

Can you add a PowerPC codegen test case for `__attribute__((target(`? All of 
the updated test cases seem to only test `-target-feature`.
The only test case we have for `__attribute((target(` is a sema test 
`./clang/test/Sema/ppc-attr-target-inline.c`.

Converting the deleted `clang/test/Sema/ppc-mma-builtins.c` and 
`clang/test/Sema/ppc-paired-vector-builtins.c` to a codegen test cases
like `clang/test/CodeGen/PowerPC/builtins-ppc-htm.c` using FileCheck seems like 
a nice solution since it would reintroduce the testing
for `+paired-vector-memops,-mma` situations, as well as a for 
`__attribute__((target("no-mma")))`




Comment at: clang/include/clang/Basic/BuiltinsPPC.def:987
+
+UNALIASED_CUSTOM_BUILTIN(mma_assemble_acc, "vW512*", false, "mma")
+UNALIASED_CUSTOM_BUILTIN(mma_disassemble_acc, "vv*W512*", false, "mma")

stefanp wrote:
> Based on the original implementation in `SemaBuiltinPPCMMACall` all of the 
> `mma` builtins also require `paired-vector-memops`. 
> Is this something that we still need?
since we are able to supply a comma separated list as done with 
`TARGET_BUILTIN(__builtin_ppc_compare_exp_uo, "idd", "", 
"isa-v30-instructions,vsx")` @ 
`clang/include/clang/Basic/BuiltinsPPC.def:105`we should definitely also 
specify `paired-vector-memops,mma` for the `[UNALIASED_]CUSTOM_BUILTIN`s 
previously covered under the default case of `SemaBuiltinPPCMMACall()` 


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[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub requested changes to this revision.
kamaub added a comment.
This revision now requires changes to proceed.

Sorry I should have requested changes before for this comment below, but I do 
want these test moved to codegen and expanded, please let me know if anything 
is unclear.

In D143467#4241667 , @kamaub wrote:

> Can you add a PowerPC codegen test case for `__attribute__((target(`? All of 
> the updated test cases seem to only test `-target-feature`.
> The only test case we have for `__attribute((target(` is a sema test 
> `./clang/test/Sema/ppc-attr-target-inline.c`.
>
> Converting the deleted `clang/test/Sema/ppc-mma-builtins.c` and 
> `clang/test/Sema/ppc-paired-vector-builtins.c` to a codegen test cases
> like `clang/test/CodeGen/PowerPC/builtins-ppc-htm.c` using FileCheck seems 
> like a nice solution since it would reintroduce the testing
> for `+paired-vector-memops,-mma` situations, as well as a for 
> `__attribute__((target("no-mma")))`




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[PATCH] D143210: [PowerPC] Include vector bool and pixel when emitting lax warning

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub added a comment.

We may also need an associated test case for the changed behaviour for using 
`areCompatibleVectorTypes()` instead of `areSameVectorElemTypes()`.
The test coverage should display when warnings are emitted now that we account 
for vector bool, vector pixel and type qualifiers.




Comment at: clang/lib/Sema/SemaExpr.cpp:9861
   isLaxVectorConversion(RHSType, LHSType)) {
-if (VecType->getVectorKind() == VectorType::AltiVecVector)
+if (VecType->getVectorKind() == VectorType::AltiVecVector ||
+VecType->getVectorKind() == VectorType::AltiVecBool ||

Is there test coverage for these addition to the if condition?


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[PATCH] D143467: [PowerPC] Add target feature requirement to builtins

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub accepted this revision.
kamaub added a comment.
This revision is now accepted and ready to land.

Hello, sorry for missing you ping and delaying the patch so long just for test 
case adjustments, thank you for addressing them.
Everything LGTM but lei and I had one request that can be made before you 
commit:

Please split the two functions and associated run line from 
ppc-p10-feature-builtins.c into two files named as follows
ppc-p10-mma-builtin-err.c
ppc-p10-paired-vec-memops-builtin-err.c


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[PATCH] D111229: [PowerPC][Builtin] Allowing __rlwnm to accept a variable as a shift parameter

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub created this revision.
kamaub added reviewers: PowerPC, nemanjai, lei, stefanp.
Herald added subscribers: shchenz, kbarton.
kamaub requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

The builtin __rlwnm is currently constrained to accept only constants
for the shift parameter but the instructions emitted for it have no such
constraint, this patch allows the builtins to accept variable shift.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -43,7 +43,7 @@
 void test_builtin_ppc_rlwnm() {
   unsigned int shift;
   unsigned int mask;
-  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7); // expected-error 
{{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
+  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7);
   res = __builtin_ppc_rlwnm(ui, 31, mask);  // expected-error 
{{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
   res = __builtin_ppc_rlwnm(ui, 31, 0xFF0F0F00);// expected-error 
{{argument 2 value should represent a contiguous bit field}}
 }
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3432,8 +3432,7 @@
   // For __rlwnm, __rlwimi and __rldimi, the last parameter mask must
   // be a constant that represents a contiguous bit field.
   case PPC::BI__builtin_ppc_rlwnm:
-return SemaBuiltinConstantArg(TheCall, 1, Result) ||
-   SemaValueIsRunOfOnes(TheCall, 2);
+return SemaValueIsRunOfOnes(TheCall, 2);
   case PPC::BI__builtin_ppc_rlwimi:
   case PPC::BI__builtin_ppc_rldimi:
 return SemaBuiltinConstantArg(TheCall, 2, Result) ||
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -117,7 +117,7 @@
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
 // Rotate
-BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "")
+BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "")
 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
 // load


Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -43,7 +43,7 @@
 void test_builtin_ppc_rlwnm() {
   unsigned int shift;
   unsigned int mask;
-  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7); // expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
+  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7);
   res = __builtin_ppc_rlwnm(ui, 31, mask);  // expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
   res = __builtin_ppc_rlwnm(ui, 31, 0xFF0F0F00);// expected-error {{argument 2 value should represent a contiguous bit field}}
 }
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3432,8 +3432,7 @@
   // For __rlwnm, __rlwimi and __rldimi, the last parameter mask must
   // be a constant that represents a contiguous bit field.
   case PPC::BI__builtin_ppc_rlwnm:
-return SemaBuiltinConstantArg(TheCall, 1, Result) ||
-   SemaValueIsRunOfOnes(TheCall, 2);
+return SemaValueIsRunOfOnes(TheCall, 2);
   case PPC::BI__builtin_ppc_rlwimi:
   case PPC::BI__builtin_ppc_rldimi:
 return SemaBuiltinConstantArg(TheCall, 2, Result) ||
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -117,7 +117,7 @@
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
 // Rotate
-BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "")
+BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "")
 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
 // load
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[PATCH] D110934: [NFC] Update return type of vec_popcnt to vector unsigned.

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub added a comment.

Yeah this LTGM as well.


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[PATCH] D110934: [NFC] Update return type of vec_popcnt to vector unsigned.

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub accepted this revision.
kamaub added a comment.
This revision is now accepted and ready to land.

Yeah this LGTM as well, accidentally commented without accepting a moment 
before.


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[PATCH] D111229: [PowerPC][Builtin] Allowing __rlwnm to accept a variable as a shift parameter

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub updated this revision to Diff 379103.
kamaub added a comment.

Addressing review request to remove unnecessary testing line.


Repository:
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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -41,10 +41,8 @@
 }
 
 void test_builtin_ppc_rlwnm() {
-  unsigned int shift;
   unsigned int mask;
-  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7); // expected-error 
{{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
-  res = __builtin_ppc_rlwnm(ui, 31, mask);  // expected-error 
{{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
+  unsigned int res = __builtin_ppc_rlwnm(ui, 31, mask);  // 
expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
   res = __builtin_ppc_rlwnm(ui, 31, 0xFF0F0F00);// expected-error 
{{argument 2 value should represent a contiguous bit field}}
 }
 
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3432,8 +3432,7 @@
   // For __rlwnm, __rlwimi and __rldimi, the last parameter mask must
   // be a constant that represents a contiguous bit field.
   case PPC::BI__builtin_ppc_rlwnm:
-return SemaBuiltinConstantArg(TheCall, 1, Result) ||
-   SemaValueIsRunOfOnes(TheCall, 2);
+return SemaValueIsRunOfOnes(TheCall, 2);
   case PPC::BI__builtin_ppc_rlwimi:
   case PPC::BI__builtin_ppc_rldimi:
 return SemaBuiltinConstantArg(TheCall, 2, Result) ||
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -117,7 +117,7 @@
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
 // Rotate
-BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "")
+BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "")
 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
 // load


Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -41,10 +41,8 @@
 }
 
 void test_builtin_ppc_rlwnm() {
-  unsigned int shift;
   unsigned int mask;
-  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7); // expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
-  res = __builtin_ppc_rlwnm(ui, 31, mask);  // expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
+  unsigned int res = __builtin_ppc_rlwnm(ui, 31, mask);  // expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
   res = __builtin_ppc_rlwnm(ui, 31, 0xFF0F0F00);// expected-error {{argument 2 value should represent a contiguous bit field}}
 }
 
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3432,8 +3432,7 @@
   // For __rlwnm, __rlwimi and __rldimi, the last parameter mask must
   // be a constant that represents a contiguous bit field.
   case PPC::BI__builtin_ppc_rlwnm:
-return SemaBuiltinConstantArg(TheCall, 1, Result) ||
-   SemaValueIsRunOfOnes(TheCall, 2);
+return SemaValueIsRunOfOnes(TheCall, 2);
   case PPC::BI__builtin_ppc_rlwimi:
   case PPC::BI__builtin_ppc_rldimi:
 return SemaBuiltinConstantArg(TheCall, 2, Result) ||
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -117,7 +117,7 @@
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
 // Rotate
-BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "")
+BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "")
 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
 // load
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[PATCH] D111229: [PowerPC][Builtin] Allowing __rlwnm to accept a variable as a shift parameter

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub updated this revision to Diff 379149.
kamaub added a comment.

Adding shift variable test case to `builtins-ppc-xlcompat-rotate.c` as per
review comment request.


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -56,6 +56,22 @@
   unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
 }
 
+void test_builtin_ppc_rlwnm2(unsigned int shift) {
+  // CHECK-LABEL: test_builtin_ppc_rlwnm2
+  // CHECK:   %shift.addr = alloca i32, align 4
+  // CHECK-NEXT:  %res = alloca i32, align 4
+  // CHECK-NEXT:  store i32 %shift, i32* %shift.addr, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* %shift.addr, align 4
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 
[[RA]], i32 [[RB]])
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 511
+  // CHECK-NEXT:  store i32 [[RD]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*shift = 31, mask = 0x1FF = 511*/
+  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 0x1FF);
+}
+
 // CHECK-LABEL: @testrotatel4(
 // CHECK: [[TMP:%.*]] = call i32 @llvm.fshl.i32(i32 {{%.*}}, i32 
{{%.*}}, i32 {{%.*}})
 // CHECK-NEXT:ret i32 [[TMP]]
Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -41,10 +41,8 @@
 }
 
 void test_builtin_ppc_rlwnm() {
-  unsigned int shift;
   unsigned int mask;
-  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7); // expected-error 
{{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
-  res = __builtin_ppc_rlwnm(ui, 31, mask);  // expected-error 
{{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
+  unsigned int res = __builtin_ppc_rlwnm(ui, 31, mask);  // 
expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
   res = __builtin_ppc_rlwnm(ui, 31, 0xFF0F0F00);// expected-error 
{{argument 2 value should represent a contiguous bit field}}
 }
 
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3432,8 +3432,7 @@
   // For __rlwnm, __rlwimi and __rldimi, the last parameter mask must
   // be a constant that represents a contiguous bit field.
   case PPC::BI__builtin_ppc_rlwnm:
-return SemaBuiltinConstantArg(TheCall, 1, Result) ||
-   SemaValueIsRunOfOnes(TheCall, 2);
+return SemaValueIsRunOfOnes(TheCall, 2);
   case PPC::BI__builtin_ppc_rlwimi:
   case PPC::BI__builtin_ppc_rldimi:
 return SemaBuiltinConstantArg(TheCall, 2, Result) ||
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -117,7 +117,7 @@
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
 // Rotate
-BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "")
+BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "")
 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
 // load


Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -56,6 +56,22 @@
   unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
 }
 
+void test_builtin_ppc_rlwnm2(unsigned int shift) {
+  // CHECK-LABEL: test_builtin_ppc_rlwnm2
+  // CHECK:   %shift.addr = alloca i32, align 4
+  // CHECK-NEXT:  %res = alloca i32, align 4
+  // CHECK-NEXT:  store i32 %shift, i32* %shift.addr, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* %shift.addr, align 4
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 [[RB]])
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 511
+  // CHECK-NEXT:  store i32 [[RD]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*shift = 31, mask = 0x1FF = 511*/
+  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 0x1FF);
+}
+
 // CHECK-LABEL: @testrotatel4(
 // CHECK: [[TMP:%.*]] = call i32 @llvm.fshl.i32(i32 {{%.*}}, i32 {{%.

[PATCH] D111229: [PowerPC][Builtin] Allowing __rlwnm to accept a variable as a shift parameter

[Kamau Bridgeman via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG89ec99c77894: [PowerPC][Builtin] Allowing __rlwnm to accept 
a variable as a shift parameter (authored by kamaub).

Changed prior to commit:
  https://reviews.llvm.org/D111229?vs=379149&id=379375#toc

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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -56,6 +56,22 @@
   unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
 }
 
+void test_builtin_ppc_rlwnm2(unsigned int shift) {
+  // CHECK-LABEL: test_builtin_ppc_rlwnm2
+  // CHECK:   %shift.addr = alloca i32, align 4
+  // CHECK-NEXT:  %res = alloca i32, align 4
+  // CHECK-NEXT:  store i32 %shift, i32* %shift.addr, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* %shift.addr, align 4
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 
[[RA]], i32 [[RB]])
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 511
+  // CHECK-NEXT:  store i32 [[RD]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*mask = 0x1FF = 511*/
+  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 0x1FF);
+}
+
 // CHECK-LABEL: @testrotatel4(
 // CHECK: [[TMP:%.*]] = call i32 @llvm.fshl.i32(i32 {{%.*}}, i32 
{{%.*}}, i32 {{%.*}})
 // CHECK-NEXT:ret i32 [[TMP]]
Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -41,10 +41,8 @@
 }
 
 void test_builtin_ppc_rlwnm() {
-  unsigned int shift;
   unsigned int mask;
-  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 7); // expected-error 
{{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
-  res = __builtin_ppc_rlwnm(ui, 31, mask);  // expected-error 
{{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
+  unsigned int res = __builtin_ppc_rlwnm(ui, 31, mask);  // 
expected-error {{argument to '__builtin_ppc_rlwnm' must be a constant integer}}
   res = __builtin_ppc_rlwnm(ui, 31, 0xFF0F0F00);// expected-error 
{{argument 2 value should represent a contiguous bit field}}
 }
 
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3432,8 +3432,7 @@
   // For __rlwnm, __rlwimi and __rldimi, the last parameter mask must
   // be a constant that represents a contiguous bit field.
   case PPC::BI__builtin_ppc_rlwnm:
-return SemaBuiltinConstantArg(TheCall, 1, Result) ||
-   SemaValueIsRunOfOnes(TheCall, 2);
+return SemaValueIsRunOfOnes(TheCall, 2);
   case PPC::BI__builtin_ppc_rlwimi:
   case PPC::BI__builtin_ppc_rldimi:
 return SemaBuiltinConstantArg(TheCall, 2, Result) ||
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -117,7 +117,7 @@
 BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "")
 BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "")
 // Rotate
-BUILTIN(__builtin_ppc_rlwnm, "UiUiIUiIUi", "")
+BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "")
 BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "")
 BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "")
 // load


Index: clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
@@ -56,6 +56,22 @@
   unsigned int res = __builtin_ppc_rlwnm(ui, 31, 0x1FF);
 }
 
+void test_builtin_ppc_rlwnm2(unsigned int shift) {
+  // CHECK-LABEL: test_builtin_ppc_rlwnm2
+  // CHECK:   %shift.addr = alloca i32, align 4
+  // CHECK-NEXT:  %res = alloca i32, align 4
+  // CHECK-NEXT:  store i32 %shift, i32* %shift.addr, align 4
+  // CHECK-NEXT:  [[RA:%[0-9]+]] = load i32, i32* @ui, align 4
+  // CHECK-NEXT:  [[RB:%[0-9]+]] = load i32, i32* %shift.addr, align 4
+  // CHECK-NEXT:  [[RC:%[0-9]+]] = call i32 @llvm.fshl.i32(i32 [[RA]], i32 [[RA]], i32 [[RB]])
+  // CHECK-NEXT:  [[RD:%[0-9]+]] = and i32 [[RC]], 511
+  // CHECK-NEXT:  store i32 [[RD]], i32* %res, align 4
+  // CHECK-NEXT:  ret void
+
+  /*mask = 0x1FF = 511*/
+  unsigned int res = __builtin_ppc_rlwnm(ui, shift, 0x1FF);
+}
+
 // CHECK-L

[PATCH] D108302: [PowerPC] Fixed the crash due to early if conversion with fixed CR fields.

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub accepted this revision as: kamaub.
kamaub added a comment.

This LGTM, small nit on the comment, but that can be fixed on commit




Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1544
 
+  // If the condition branch uses a physical register, then it cannot be turned
+  // into a select.

nit


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[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub created this revision.
kamaub added reviewers: PowerPC, nemanjai, lei, saghir, stefanp.
Herald added subscribers: steven.zhang, shchenz, kbarton.
kamaub requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This patch allows the use of__vector_quad and __vector_pair, PPC MMA builtin
types, on all PowerPC 64-bit compilation units. When these types are
made available the builtins that use them automatically become available
so semantic checking for mma and pair vector memop __builtins is also
expanded to ensure these builtin function call are only allowed on
Power10 and new architectures. All related test cases are updated to
ensure test coverage.


Repository:
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https://reviews.llvm.org/D109599

Files:
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/AST/ast-dump-ppc-types.c
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/CodeGen/ppc-mma-types.c
  clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
  clang/test/Sema/ppc-pair-mma-types.c

Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -1,5 +1,5 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -target-cpu future %s -verify
+// RUN:   -target-cpu pwr10 %s -verify
 
 // The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
 // can only be declared in functions and a limited number of operations are
Index: clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
===
--- clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
+++ clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
@@ -1,4 +1,8 @@
-// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future %s \
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr10 %s \
+// RUN:   -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr9 %s \
+// RUN:   -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr8 %s \
 // RUN:   -emit-llvm -o - | FileCheck %s
 
 // CHECK: _Z2f1Pu13__vector_quad
Index: clang/test/CodeGen/ppc-mma-types.c
===
--- clang/test/CodeGen/ppc-mma-types.c
+++ clang/test/CodeGen/ppc-mma-types.c
@@ -1,5 +1,9 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future \
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr10 \
+// RUN:   -emit-llvm -O3 -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr9 \
+// RUN:   -emit-llvm -O3 -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr8 \
 // RUN:   -emit-llvm -O3 -o - %s | FileCheck %s
 
 // CHECK-LABEL: @test1(
Index: clang/test/CodeGen/builtins-ppc-pair-mma.c
===
--- clang/test/CodeGen/builtins-ppc-pair-mma.c
+++ clang/test/CodeGen/builtins-ppc-pair-mma.c
@@ -1,5 +1,5 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 -emit-llvm %s -o - | FileCheck %s
 
 // CHECK-LABEL: @test1(
 // CHECK-NEXT:  entry:
Index: clang/test/AST/ast-dump-ppc-types.c
===
--- clang/test/AST/ast-dump-ppc-types.c
+++ clang/test/AST/ast-dump-ppc-types.c
@@ -1,13 +1,9 @@
-// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu future \
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
 // RUN:   -ast-dump -ast-dump-filter __vector %s | FileCheck %s
-// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu future \
-// RUN:   -target-feature -mma -ast-dump %s | FileCheck %s \
-// RUN:   --check-prefix=CHECK-NO-MMA
-// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu future \
-// RUN:   -target-feature -paired-vector-memops -ast-dump %s | FileCheck %s \
-// RUN:   --check-prefix=CHECK-NO-PAIRED
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr9 \
-// RUN:   -ast-dump %s | FileCheck %s --check-prefix=CHECK-PWR9
+// RUN:   -ast-dump -ast-dump-filter __vector %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr8 \
+// RUN:   -ast-dump -ast-dump-filter __vector %s | FileCheck %s
 // RUN: %clang_cc1 -triple x86_64-unknown-unknown -ast-dump %s | FileCheck %s \
 // RUN:   --check-prefix=CHECK-X86_64
 // RUN: %clang_cc1 -triple arm-unkno

[PATCH] D109599: [PowerPC][MMA] Allow MMA builtin types in pre-P10 compilation units

[Kamau Bridgeman via Phabricator via cfe-commits]

kamaub updated this revision to Diff 371954.
kamaub added a comment.

The condition for failing semantic chequing on mma builtins was incorrect,
updating this patch to correctly check the semantics and associated testing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109599/new/

https://reviews.llvm.org/D109599

Files:
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/AST/ast-dump-ppc-types.c
  clang/test/CodeGen/builtins-ppc-pair-mma.c
  clang/test/CodeGen/ppc-mma-types.c
  clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
  clang/test/Sema/ppc-mma-builtins.c
  clang/test/Sema/ppc-pair-mma-types.c
  clang/test/Sema/ppc-paired-vector-builtins.c

Index: clang/test/Sema/ppc-paired-vector-builtins.c
===
--- /dev/null
+++ clang/test/Sema/ppc-paired-vector-builtins.c
@@ -0,0 +1,25 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -target-feature -paired-vector-memops -fsyntax-only %s -verify
+
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __vector_pair res;
+  __builtin_vsx_assemble_pair(&res, vc, vc); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+}
+
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __builtin_vsx_disassemble_pair(resp, (__vector_pair*)vpp); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+}
+
+void test3(const __vector_pair *vpp, signed long long offset, const __vector_pair *vp2) {
+  __vector_pair vp = __builtin_vsx_lxvp(offset, vpp); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+  __builtin_vsx_stxvp(vp, offset, vp2); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+}
+
+void test4(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __vector_quad vq = *((__vector_quad *)vqp);
+  __vector_pair vp = *((__vector_pair *)vpp);
+  __builtin_mma_xxmtacc(&vq); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+  *((__vector_quad *)resp) = vq;
+}
+
+
Index: clang/test/Sema/ppc-pair-mma-types.c
===
--- clang/test/Sema/ppc-pair-mma-types.c
+++ clang/test/Sema/ppc-pair-mma-types.c
@@ -1,5 +1,5 @@
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN:   -target-cpu future %s -verify
+// RUN:   -target-cpu pwr10 %s -verify
 
 // The use of PPC MMA types is strongly restricted. Non-pointer MMA variables
 // can only be declared in functions and a limited number of operations are
Index: clang/test/Sema/ppc-mma-builtins.c
===
--- /dev/null
+++ clang/test/Sema/ppc-mma-builtins.c
@@ -0,0 +1,32 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
+// RUN:   -target-feature -mma -fsyntax-only %s -verify
+
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __vector_pair res;
+  __builtin_vsx_assemble_pair(&res, vc, vc);
+}
+
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __builtin_vsx_disassemble_pair(resp, (__vector_pair*)vpp);
+}
+
+void test3(const __vector_pair *vpp, signed long long offset, const __vector_pair *vp2) {
+  __vector_pair vp = __builtin_vsx_lxvp(offset, vpp);
+  __builtin_vsx_stxvp(vp, offset, vp2);
+}
+
+void test4(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __vector_quad vq = *((__vector_quad *)vqp);
+  __vector_pair vp = *((__vector_pair *)vpp);
+  __builtin_mma_xxmtacc(&vq); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+  *((__vector_quad *)resp) = vq;
+}
+
+void test5(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+  __vector_quad vq = *((__vector_quad *)vqp);
+  __vector_pair vp = *((__vector_pair *)vpp);
+  __builtin_mma_pmxvf64ger(&vq, vp, vc, 0, 0); // expected-error {{this builtin is only valid on POWER10 or later CPUs}}
+  *((__vector_quad *)resp) = vq;
+}
+
+
Index: clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
===
--- clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
+++ clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
@@ -1,4 +1,8 @@
-// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future %s \
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr10 %s \
+// RUN:   -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr9 %s \
+// RUN:   -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu pwr8 %