[clang] 68e07da - [clang][PowerPC] Enable -fstack-clash-protection option for ppc64

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2020-07-05T03:43:56Z
New Revision: 68e07da3e5d5175e24caa309e2b13cb65c8c

URL: 
https://github.com/llvm/llvm-project/commit/68e07da3e5d5175e24caa309e2b13cb65c8c
DIFF: 
https://github.com/llvm/llvm-project/commit/68e07da3e5d5175e24caa309e2b13cb65c8c.diff

LOG: [clang][PowerPC] Enable -fstack-clash-protection option for ppc64

Differential Revision: https://reviews.llvm.org/D81355

Added: 


Modified: 
clang/docs/ReleaseNotes.rst
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Clang.cpp
clang/test/CodeGen/stack-clash-protection.c

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 4d271bfdcd31..d0328b0ef54c 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -94,8 +94,8 @@ New Compiler Flags
 --
 
 - -fstack-clash-protection will provide a protection against the stack clash
-  attack for x86 and s390x architectures through automatic probing of each page
-  of allocated stack.
+  attack for x86, s390x and ppc64 architectures through automatic probing of
+  each page of allocated stack.
 
 - -ffp-exception-behavior={ignore,maytrap,strict} allows the user to specify
   the floating-point exception behavior. The default setting is ``ignore``.

diff  --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 46670eaf423b..858059bacb86 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -343,6 +343,10 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   const char *getFloat128Mangling() const override { return "u9__ieee128"; }
 
   bool hasExtIntType() const override { return true; }
+
+  bool isSPRegName(StringRef RegName) const override {
+return RegName.equals("r1") || RegName.equals("x1");
+  }
 };
 
 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {

diff  --git a/clang/lib/Driver/ToolChains/Clang.cpp 
b/clang/lib/Driver/ToolChains/Clang.cpp
index a2cc84805c9c..e6dd6ce0a95e 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2966,7 +2966,8 @@ static void RenderSCPOptions(const ToolChain &TC, const 
ArgList &Args,
   if (!EffectiveTriple.isOSLinux())
 return;
 
-  if (!EffectiveTriple.isX86() && !EffectiveTriple.isSystemZ())
+  if (!EffectiveTriple.isX86() && !EffectiveTriple.isSystemZ() &&
+  !EffectiveTriple.isPPC64())
 return;
 
   if (Args.hasFlag(options::OPT_fstack_clash_protection,

diff  --git a/clang/test/CodeGen/stack-clash-protection.c 
b/clang/test/CodeGen/stack-clash-protection.c
index eb48da8ff9e9..54699f044ae4 100644
--- a/clang/test/CodeGen/stack-clash-protection.c
+++ b/clang/test/CodeGen/stack-clash-protection.c
@@ -1,6 +1,8 @@
 // Check the correct function attributes are generated
 // RUN: %clang_cc1 -triple x86_64-linux -O0 -S -emit-llvm -o- %s 
-fstack-clash-protection | FileCheck %s
 // RUN: %clang_cc1 -triple s390x-linux-gnu -O0 -S -emit-llvm -o- %s 
-fstack-clash-protection | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-linux-gnu -O0 -S -emit-llvm -o- %s 
-fstack-clash-protection | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-linux-gnu -O0 -S -emit-llvm -o- %s 
-fstack-clash-protection | FileCheck %s
 
 // CHECK: define void @large_stack() #[[A:.*]] {
 void large_stack() {



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[clang-tools-extra] [llvm] [clang] [XCOFF][obj2yaml] support parsing auxiliary symbols for XCOFF (PR #70642)

[Kai Luo via cfe-commits]

@@ -282,45 +282,57 @@ static void auxSymMapping(IO &IO, 
XCOFFYAML::SectAuxEntForStat &AuxSym) {
 
 void MappingTraits>::mapping(
 IO &IO, std::unique_ptr &AuxSym) {
-  assert(!IO.outputting() && "We don't dump aux symbols currently.");
+
+  auto ResetAuxSym = [&](auto *AuxEnt) {
+if (!IO.outputting())
+  AuxSym.reset(AuxEnt);

bzEq wrote:

What if `IO.outputting()` is `true`, will `AuxEnt` be deleted?

https://github.com/llvm/llvm-project/pull/70642
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[llvm] [clang-tools-extra] [clang] [XCOFF][obj2yaml] support parsing auxiliary symbols for XCOFF (PR #70642)

[Kai Luo via cfe-commits]

@@ -282,45 +282,57 @@ static void auxSymMapping(IO &IO, 
XCOFFYAML::SectAuxEntForStat &AuxSym) {
 
 void MappingTraits>::mapping(
 IO &IO, std::unique_ptr &AuxSym) {
-  assert(!IO.outputting() && "We don't dump aux symbols currently.");
+
+  auto ResetAuxSym = [&](auto *AuxEnt) {
+if (!IO.outputting())
+  AuxSym.reset(AuxEnt);

bzEq wrote:

Might use a templated helper function to replace this lambda.
```c++
template
static void ResetAuxSym(IO &IO, std::unique_ptr 
&AuxSym) {
  if (!IO.outputting()) AuxSym.reset(new AuxEntT);
}
```

https://github.com/llvm/llvm-project/pull/70642
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[clang] [PowerPC] Disable float128 on AIX in Clang (PR #67298)

[Kai Luo via cfe-commits]

@@ -52,7 +52,7 @@ bool 
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
   HasDirectMove = true;
 } else if (Feature == "+htm") {
   HasHTM = true;
-} else if (Feature == "+float128") {
+} else if (Feature == "+float128" && !getTriple().isOSAIX()) {

bzEq wrote:

```suggestion
HasFloat128 = !getTriple().isOSAIX();
```

https://github.com/llvm/llvm-project/pull/67298
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[clang] [PowerPC] Disable float128 on AIX in Clang (PR #67298)

[Kai Luo via cfe-commits]

https://github.com/bzEq deleted https://github.com/llvm/llvm-project/pull/67298
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[clang] [PowerPC] Disable float128 on AIX in Clang (PR #67298)

[Kai Luo via cfe-commits]

@@ -52,7 +52,7 @@ bool 
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
   HasDirectMove = true;
 } else if (Feature == "+htm") {
   HasHTM = true;
-} else if (Feature == "+float128") {
+} else if (Feature == "+float128" && !getTriple().isOSAIX()) {
   HasFloat128 = true;

bzEq wrote:

```suggestion
  HasFloat128 = !getTriple().isOSAIX();
```

https://github.com/llvm/llvm-project/pull/67298
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[clang] [PowerPC] Disable float128 on AIX in Clang (PR #67298)

[Kai Luo via cfe-commits]

@@ -52,7 +52,7 @@ bool 
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
   HasDirectMove = true;
 } else if (Feature == "+htm") {
   HasHTM = true;
-} else if (Feature == "+float128") {
+} else if (Feature == "+float128" && !getTriple().isOSAIX()) {

bzEq wrote:

```suggestion
} else if (Feature == "+float128") {
```

https://github.com/llvm/llvm-project/pull/67298
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[clang] [PowerPC] Disable float128 on AIX in Clang (PR #67298)

[Kai Luo via cfe-commits]

https://github.com/bzEq approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/67298
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[libcxx] [libcxxabi] [lld] [compiler-rt] [clang] [llvm] [clang-tools-extra] [libc] [libunwind] [flang] [PowerPC] Combine sub within setcc back to sext (PR #66978)

[Kai Luo via cfe-commits]

@@ -14428,15 +14431,53 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
 // x != 0-y --> x+y != 0
 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
 RHS.hasOneUse()) {
-  SDLoc DL(N);
-  SelectionDAG &DAG = DCI.DAG;
-  EVT VT = N->getValueType(0);
-  EVT OpVT = LHS.getValueType();
   SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
   return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
 }
   }
 
+  if (CC == ISD::SETULT && isa(RHS)) {
+uint64_t RHSVal = cast(RHS)->getZExtValue();
+if (LHS.getOpcode() == ISD::ADD && isa(LHS.getOperand(1))) 
{
+  uint64_t Addend = 
cast(LHS.getOperand(1))->getZExtValue();
+  if (OpVT == MVT::i64) {
+// (a-2^(M-1)) => sext(trunc(a, M), 64)
+uint64_t ShiftVal = ~Addend + 1;
+uint64_t CmpVal = ~RHSVal + 1;
+if (isPowerOf2_64(ShiftVal) && ShiftVal << 1 == CmpVal) {
+  unsigned DestBits = Log2_64(CmpVal);
+  if (DestBits == 8 || DestBits == 16 || DestBits == 32) {
+SDValue Conv = DAG.getSExtOrTrunc(
+DAG.getSExtOrTrunc(LHS.getOperand(0), DL,
+   MVT::getIntegerVT(DestBits)),
+DL, OpVT);
+return DAG.getSetCC(DL, VT, LHS.getOperand(0), Conv, ISD::SETNE);
+  }
+}
+  } else if (OpVT == MVT::i32) {
+if (RHSVal == 0xff00 && Addend == 0xff80) {
+  SDValue Conv = DAG.getSExtOrTrunc(
+  DAG.getSExtOrTrunc(LHS.getOperand(0), DL, MVT::i8), DL, OpVT);
+  return DAG.getSetCC(DL, VT, LHS.getOperand(0), Conv, ISD::SETNE);
+}
+  }
+} else if (LHS.getOpcode() == ISD::SRL &&
+   LHS.getOperand(0).getOpcode() == ISD::ADD &&
+   isa(LHS.getOperand(1)) &&
+   isa(LHS.getOperand(0).getOperand(1))) {
+  if (RHSVal == 65535 &&

bzEq wrote:

```suggestion
  if (RHSVal == 0xff &&
```

https://github.com/llvm/llvm-project/pull/66978
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[libcxx] [libcxxabi] [lld] [compiler-rt] [clang] [llvm] [clang-tools-extra] [libc] [libunwind] [flang] [PowerPC] Combine sub within setcc back to sext (PR #66978)

[Kai Luo via cfe-commits]

https://github.com/bzEq edited https://github.com/llvm/llvm-project/pull/66978
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[libcxx] [libcxxabi] [lld] [compiler-rt] [clang] [llvm] [clang-tools-extra] [libc] [libunwind] [flang] [PowerPC] Combine sub within setcc back to sext (PR #66978)

[Kai Luo via cfe-commits]

@@ -14428,15 +14431,53 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
 // x != 0-y --> x+y != 0
 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
 RHS.hasOneUse()) {
-  SDLoc DL(N);
-  SelectionDAG &DAG = DCI.DAG;
-  EVT VT = N->getValueType(0);
-  EVT OpVT = LHS.getValueType();
   SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
   return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
 }
   }
 
+  if (CC == ISD::SETULT && isa(RHS)) {
+uint64_t RHSVal = cast(RHS)->getZExtValue();
+if (LHS.getOpcode() == ISD::ADD && isa(LHS.getOperand(1))) 
{
+  uint64_t Addend = 
cast(LHS.getOperand(1))->getZExtValue();
+  if (OpVT == MVT::i64) {
+// (a-2^(M-1)) => sext(trunc(a, M), 64)

bzEq wrote:

When is this equation hold?

https://github.com/llvm/llvm-project/pull/66978
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[clang] [Driver][BoundsSafety] Add -fbounds-safety-experimental flag (PR #70480)

[Kai Luo via cfe-commits]

https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/70480

>From 99ec6e055dd32a86bf6d589a6895658dcbe1d7bd Mon Sep 17 00:00:00 2001
From: Yeoul Na 
Date: Fri, 27 Oct 2023 08:34:37 -0700
Subject: [PATCH 1/6] [Driver][BoundsSafety] Add -fbounds-safety-experimental
 flag

-fbounds-safety-experimental is an experimental flag for
-fbounds-safety, which is a bounds-safety extension for C.
-fbounds-safety will require substantial changes across the Clang
codebase. So we introduce this experimental flag is to gate our
incremental patches until we push the essential functionality of
the extension.

-fbounds-safety-experimental currently doesn't do anything but
reporting an error when the flag is used with an unsupported
source language (currently only supports C).
---
 .../clang/Basic/DiagnosticFrontendKinds.td|  3 +++
 clang/include/clang/Basic/LangOptions.def |  2 ++
 clang/include/clang/Driver/Options.td |  8 +++
 clang/lib/Driver/ToolChains/Clang.cpp |  3 +++
 clang/lib/Frontend/CompilerInvocation.cpp | 23 +++
 clang/test/BoundsSafety/Driver/driver.c   |  9 
 .../Frontend/only_c_is_supported.c| 15 
 7 files changed, 63 insertions(+)
 create mode 100644 clang/test/BoundsSafety/Driver/driver.c
 create mode 100644 clang/test/BoundsSafety/Frontend/only_c_is_supported.c

diff --git a/clang/include/clang/Basic/DiagnosticFrontendKinds.td 
b/clang/include/clang/Basic/DiagnosticFrontendKinds.td
index 715e0c0dc8fa84e..edcbbe992377e12 100644
--- a/clang/include/clang/Basic/DiagnosticFrontendKinds.td
+++ b/clang/include/clang/Basic/DiagnosticFrontendKinds.td
@@ -330,6 +330,9 @@ def warn_alias_with_section : Warning<
   "as the %select{aliasee|resolver}2">,
   InGroup;
 
+def error_bounds_safety_lang_not_supported : Error<
+  "bounds safety is only supported for C">;
+
 let CategoryName = "Instrumentation Issue" in {
 def warn_profile_data_out_of_date : Warning<
   "profile data may be out of date: of %0 function%s0, %1 
%plural{1:has|:have}1"
diff --git a/clang/include/clang/Basic/LangOptions.def 
b/clang/include/clang/Basic/LangOptions.def
index c0ea4ecb9806a5b..222812d876a65f8 100644
--- a/clang/include/clang/Basic/LangOptions.def
+++ b/clang/include/clang/Basic/LangOptions.def
@@ -470,6 +470,8 @@ VALUE_LANGOPT(FuchsiaAPILevel, 32, 0, "Fuchsia API level")
 // on large _BitInts.
 BENIGN_VALUE_LANGOPT(MaxBitIntWidth, 32, 128, "Maximum width of a _BitInt")
 
+LANGOPT(BoundsSafety, 1, 0, "Bounds safety extension for C")
+
 LANGOPT(IncrementalExtensions, 1, 0, " True if we want to process statements"
 "on the global scope, ignore EOF token and continue later on (thus "
 "avoid tearing the Lexer and etc. down). Controlled by "
diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 7f3f5125d42e7a9..3eb98c8ee2950a1 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -1732,6 +1732,14 @@ def fswift_async_fp_EQ : Joined<["-"], 
"fswift-async-fp=">,
 NormalizedValues<["Auto", "Always", "Never"]>,
 MarshallingInfoEnum, "Always">;
 
+defm bounds_safety : BoolFOption<
+  "bounds-safety-experimental",
+  LangOpts<"BoundsSafety">, DefaultFalse,
+  PosFlag,
+  NegFlag,
+  BothFlags<[], [ClangOption, CC1Option],
+  " experimental bounds safety extension for C">>;
+
 defm addrsig : BoolFOption<"addrsig",
   CodeGenOpts<"Addrsig">, DefaultFalse,
   PosFlag,
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp 
b/clang/lib/Driver/ToolChains/Clang.cpp
index 43a92adbef64ba8..7482b852fb37958 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -6689,6 +6689,9 @@ void Clang::ConstructJob(Compilation &C, const JobAction 
&JA,
   Args.addOptOutFlag(CmdArgs, options::OPT_fassume_sane_operator_new,
  options::OPT_fno_assume_sane_operator_new);
 
+  Args.addOptInFlag(CmdArgs, options::OPT_fbounds_safety,
+options::OPT_fno_bounds_safety);
+
   // -fblocks=0 is default.
   if (Args.hasFlag(options::OPT_fblocks, options::OPT_fno_blocks,
TC.IsBlocksDefault()) ||
diff --git a/clang/lib/Frontend/CompilerInvocation.cpp 
b/clang/lib/Frontend/CompilerInvocation.cpp
index fd6c250efeda2a8..f785bd504d63a81 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -3618,6 +3618,23 @@ void CompilerInvocationBase::GenerateLangArgs(const 
LangOptions &Opts,
 GenerateArg(Consumer, OPT_frandomize_layout_seed_EQ, Opts.RandstructSeed);
 }
 
+static bool SupportsBoundsSafety(Language Lang) {
+  // Currently, bounds safety is only supported for C. However, it's also
+  // possible to pass assembly files and LLVM IR through Clang, and
+  // those should be trivially supported. This is especially important because
+  // some build systems, like xcbuild and somewhat clumsy Makefiles, will pass
+  // C

[compiler-rt] [clang] [AIX] Undefine __STDC_NO_ATOMICS__ to enable c11 atomics functionality (PR #76025)

[Kai Luo via cfe-commits]

https://github.com/bzEq created https://github.com/llvm/llvm-project/pull/76025

This is copied from https://reviews.llvm.org/D109139.

`__STDC_NO_ATOMICS__` is predefined to indicate clang on AIX doesn't support 
`_Atomic` and not shipped with `stdatomic.h` yet. Actually `_Atomic` is already 
supported. For `stdatomic.h`, clang has implemented one in 
`clang/lib/Headers/stdatomic.h`.

For missing libc implementations,
```
atomic_flag_test_and_set
atomic_flag_test_and_set_explicit
atomic_flag_clear
atomic_flag_clear_explicit
atomic_thread_fence
atomic_signal_fence
```
Provide them via compiler-rt.

>From 326b21d8e822f52733388d411a06cc85109a3208 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Wed, 20 Dec 2023 08:38:40 +
Subject: [PATCH] Undefine __STDC_NO_ATOMICS__ to enable c11 atomics
 functionality

---
 clang/lib/Basic/Targets/OSTargets.h | 4 +---
 clang/test/Preprocessor/init-ppc.c  | 2 --
 compiler-rt/lib/builtins/CMakeLists.txt | 2 +-
 3 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/clang/lib/Basic/Targets/OSTargets.h 
b/clang/lib/Basic/Targets/OSTargets.h
index 342af4bbc42b7b..f76afad947cb7f 100644
--- a/clang/lib/Basic/Targets/OSTargets.h
+++ b/clang/lib/Basic/Targets/OSTargets.h
@@ -645,10 +645,8 @@ class AIXTargetInfo : public OSTargetInfo {
 Builder.defineMacro("__TOS_AIX__");
 Builder.defineMacro("__HOS_AIX__");
 
-if (Opts.C11) {
-  Builder.defineMacro("__STDC_NO_ATOMICS__");
+if (Opts.C11)
   Builder.defineMacro("__STDC_NO_THREADS__");
-}
 
 if (Opts.EnableAIXExtendedAltivecABI)
   Builder.defineMacro("__EXTABI__");
diff --git a/clang/test/Preprocessor/init-ppc.c 
b/clang/test/Preprocessor/init-ppc.c
index 3fb642af9d7420..8cdb2c6d3d350d 100644
--- a/clang/test/Preprocessor/init-ppc.c
+++ b/clang/test/Preprocessor/init-ppc.c
@@ -756,11 +756,9 @@
 // RUN: %clang_cc1 -x c -std=c11 -E -dM -ffreestanding 
-triple=powerpc-ibm-aix7.1.0.0 -fno-signed-char < /dev/null | FileCheck 
-match-full-lines -check-prefix PPC-AIX-STDC %s
 // RUN: %clang_cc1 -x c -std=gnu11 -E -dM -ffreestanding 
-triple=powerpc-ibm-aix7.1.0.0 -fno-signed-char < /dev/null | FileCheck 
-match-full-lines -check-prefix PPC-AIX-STDC %s
 // RUN: %clang_cc1 -x c -std=c17 -E -dM -ffreestanding 
-triple=powerpc-ibm-aix7.1.0.0 -fno-signed-char < /dev/null | FileCheck 
-match-full-lines -check-prefix PPC-AIX-STDC %s
-// PPC-AIX-STDC:#define __STDC_NO_ATOMICS__ 1
 // PPC-AIX-STDC:#define __STDC_NO_THREADS__ 1
 
 // RUN: %clang_cc1 -x c -std=c99 -E -dM -ffreestanding 
-triple=powerpc-ibm-aix7.1.0.0 -fno-signed-char < /dev/null | FileCheck 
-match-full-lines -check-prefix PPC-AIX-STDC-N %s
-// PPC-AIX-STDC-N-NOT:#define __STDC_NO_ATOMICS__ 1
 // PPC-AIX-STDC-N-NOT:#define __STDC_NO_THREADS__ 1
 
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc-ibm-aix7.1.0.0 
-mlong-double-64 < /dev/null | FileCheck -match-full-lines -check-prefix 
PPC-AIX-LD64 %s
diff --git a/compiler-rt/lib/builtins/CMakeLists.txt 
b/compiler-rt/lib/builtins/CMakeLists.txt
index e5b52db175d960..f57cd36eccd453 100644
--- a/compiler-rt/lib/builtins/CMakeLists.txt
+++ b/compiler-rt/lib/builtins/CMakeLists.txt
@@ -243,7 +243,7 @@ if(COMPILER_RT_HAS_ATOMIC_KEYWORD AND NOT 
COMPILER_RT_EXCLUDE_ATOMIC_BUILTIN)
   )
 endif()
 
-if(APPLE)
+if(APPLE OR OS_NAME MATCHES "AIX")
   set(GENERIC_SOURCES
 ${GENERIC_SOURCES}
 atomic_flag_clear.c

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[clang-tools-extra] [compiler-rt] [lldb] [llvm] [libc] [flang] [clang] [GlobalIsel] Combine select of binops (PR #76763)

[Kai Luo via cfe-commits]

Thorsten =?utf-8?q?Schütt?= ,
Thorsten =?utf-8?q?Schütt?= ,
Thorsten =?utf-8?q?Schütt?= 
Message-ID:
In-Reply-To: 


bzEq wrote:

It's also exhausting memory when `llvm-lit 
llvm-project/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll`.
See https://lab.llvm.org/buildbot/#/builders/249/builds/13786.

https://github.com/llvm/llvm-project/pull/76763
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[clang] [PowerPC] Make "ca" aliased to "xer" (PR #77557)

[Kai Luo via cfe-commits]

https://github.com/bzEq created https://github.com/llvm/llvm-project/pull/77557

`ca` is not accepted in clobber list of inline assembly right now. Make `ca` 
aliased to `xer`, so it can be accepted in clobber list.

Fixes #77549.

>From e1caee46dc81e59b8eab0379e200ca2a709801c3 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Wed, 10 Jan 2024 05:29:22 +
Subject: [PATCH 1/2] Alias

---
 clang/lib/Basic/Targets/PPC.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 045c273f03c7a0..fa86d93b141180 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -803,7 +803,7 @@ const TargetInfo::GCCRegAlias 
PPCTargetInfo::GCCRegAliases[] = {
 {{"fr22"}, "f22"}, {{"fr23"}, "f23"},   {{"fr24"}, "f24"},
 {{"fr25"}, "f25"}, {{"fr26"}, "f26"},   {{"fr27"}, "f27"},
 {{"fr28"}, "f28"}, {{"fr29"}, "f29"},   {{"fr30"}, "f30"},
-{{"fr31"}, "f31"}, {{"cc"}, "cr0"},
+{{"fr31"}, "f31"}, {{"cc"}, "cr0"}, {{"ca"},   "xer"},
 };
 
 ArrayRef PPCTargetInfo::getGCCRegAliases() const {

>From aaee97fb9f7bef5ff4e3f845fa29d45e9c7a83b0 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Wed, 10 Jan 2024 05:56:27 +
Subject: [PATCH 2/2] CA aliasing to XER

---
 clang/lib/Basic/Targets/PPC.cpp |  3 +++
 clang/test/CodeGen/ppc-register-names.c | 14 ++
 2 files changed, 17 insertions(+)
 create mode 100644 clang/test/CodeGen/ppc-register-names.c

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index fa86d93b141180..abf685f8883971 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -782,6 +782,9 @@ ArrayRef PPCTargetInfo::getGCCRegNames() 
const {
 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
 // While some of these aliases do map to different registers
 // they still share the same register name.
+// Strictly speaking, "ca" is a subregister of "xer". However
+// currently we don't model other bit fields of "xer", so treat
+// "ca" aliasing to "xer".
 {{"0"}, "r0"}, {{"1", "sp"}, "r1"}, {{"2"}, "r2"},
 {{"3"}, "r3"}, {{"4"}, "r4"},   {{"5"}, "r5"},
 {{"6"}, "r6"}, {{"7"}, "r7"},   {{"8"}, "r8"},
diff --git a/clang/test/CodeGen/ppc-register-names.c 
b/clang/test/CodeGen/ppc-register-names.c
new file mode 100644
index 00..209488c2e5f1ae
--- /dev/null
+++ b/clang/test/CodeGen/ppc-register-names.c
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -target powerpc64le -c %s -mllvm -stop-after=finalize-isel -o - 
| \
+// RUN:   FileCheck %s
+// RUN: %clang -target powerpc64 -c %s -mllvm -stop-after=finalize-isel -o - | 
\
+// RUN:   FileCheck %s
+
+void test_function(void) {
+  asm volatile("":::"ca");
+  asm volatile("":::"xer");
+  // CHECK: call void asm sideeffect "", "~{xer}"()
+  // CHECK: call void asm sideeffect "", "~{xer}"()
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $xer
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $xer
+}

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[clang] [PowerPC] Make "ca" aliased to "xer" (PR #77557)

[Kai Luo via cfe-commits]

https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/77557

>From e1caee46dc81e59b8eab0379e200ca2a709801c3 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Wed, 10 Jan 2024 05:29:22 +
Subject: [PATCH 1/3] Alias

---
 clang/lib/Basic/Targets/PPC.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 045c273f03c7a0..fa86d93b141180 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -803,7 +803,7 @@ const TargetInfo::GCCRegAlias 
PPCTargetInfo::GCCRegAliases[] = {
 {{"fr22"}, "f22"}, {{"fr23"}, "f23"},   {{"fr24"}, "f24"},
 {{"fr25"}, "f25"}, {{"fr26"}, "f26"},   {{"fr27"}, "f27"},
 {{"fr28"}, "f28"}, {{"fr29"}, "f29"},   {{"fr30"}, "f30"},
-{{"fr31"}, "f31"}, {{"cc"}, "cr0"},
+{{"fr31"}, "f31"}, {{"cc"}, "cr0"}, {{"ca"},   "xer"},
 };
 
 ArrayRef PPCTargetInfo::getGCCRegAliases() const {

>From aaee97fb9f7bef5ff4e3f845fa29d45e9c7a83b0 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Wed, 10 Jan 2024 05:56:27 +
Subject: [PATCH 2/3] CA aliasing to XER

---
 clang/lib/Basic/Targets/PPC.cpp |  3 +++
 clang/test/CodeGen/ppc-register-names.c | 14 ++
 2 files changed, 17 insertions(+)
 create mode 100644 clang/test/CodeGen/ppc-register-names.c

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index fa86d93b141180..abf685f8883971 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -782,6 +782,9 @@ ArrayRef PPCTargetInfo::getGCCRegNames() 
const {
 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
 // While some of these aliases do map to different registers
 // they still share the same register name.
+// Strictly speaking, "ca" is a subregister of "xer". However
+// currently we don't model other bit fields of "xer", so treat
+// "ca" aliasing to "xer".
 {{"0"}, "r0"}, {{"1", "sp"}, "r1"}, {{"2"}, "r2"},
 {{"3"}, "r3"}, {{"4"}, "r4"},   {{"5"}, "r5"},
 {{"6"}, "r6"}, {{"7"}, "r7"},   {{"8"}, "r8"},
diff --git a/clang/test/CodeGen/ppc-register-names.c 
b/clang/test/CodeGen/ppc-register-names.c
new file mode 100644
index 00..209488c2e5f1ae
--- /dev/null
+++ b/clang/test/CodeGen/ppc-register-names.c
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -target powerpc64le -c %s -mllvm -stop-after=finalize-isel -o - 
| \
+// RUN:   FileCheck %s
+// RUN: %clang -target powerpc64 -c %s -mllvm -stop-after=finalize-isel -o - | 
\
+// RUN:   FileCheck %s
+
+void test_function(void) {
+  asm volatile("":::"ca");
+  asm volatile("":::"xer");
+  // CHECK: call void asm sideeffect "", "~{xer}"()
+  // CHECK: call void asm sideeffect "", "~{xer}"()
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $xer
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $xer
+}

>From f871c97964ca600ad62f04993b93912203a8cd02 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Wed, 10 Jan 2024 06:08:04 +
Subject: [PATCH 3/3] Adjust comment

---
 clang/lib/Basic/Targets/PPC.cpp | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index abf685f8883971..01f58b57f6096f 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -782,9 +782,8 @@ ArrayRef PPCTargetInfo::getGCCRegNames() 
const {
 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
 // While some of these aliases do map to different registers
 // they still share the same register name.
-// Strictly speaking, "ca" is a subregister of "xer". However
-// currently we don't model other bit fields of "xer", so treat
-// "ca" aliasing to "xer".
+// Strictly speaking, "ca" is a subregister of "xer". However currently we
+// don't model other bit fields of "xer", so treat "ca" aliased to "xer".
 {{"0"}, "r0"}, {{"1", "sp"}, "r1"}, {{"2"}, "r2"},
 {{"3"}, "r3"}, {{"4"}, "r4"},   {{"5"}, "r5"},
 {{"6"}, "r6"}, {{"7"}, "r7"},   {{"8"}, "r8"},
@@ -806,7 +805,7 @@ const TargetInfo::GCCRegAlias 
PPCTargetInfo::GCCRegAliases[] = {
 {{"fr22"}, "f22"}, {{"fr23"}, "f23"},   {{"fr24"}, "f24"},
 {{"fr25"}, "f25"}, {{"fr26"}, "f26"},   {{"fr27"}, "f27"},
 {{"fr28"}, "f28"}, {{"fr29"}, "f29"},   {{"fr30"}, "f30"},
-{{"fr31"}, "f31"}, {{"cc"}, "cr0"}, {{"ca"},   "xer"},
+{{"fr31"}, "f31"}, {{"cc"}, "cr0"}, {{"ca"}, "xer"},
 };
 
 ArrayRef PPCTargetInfo::getGCCRegAliases() const {

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[clang] [PowerPC] Make "ca" aliased to "xer" (PR #77557)

[Kai Luo via cfe-commits]

@@ -782,6 +782,8 @@ ArrayRef PPCTargetInfo::getGCCRegNames() 
const {
 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
 // While some of these aliases do map to different registers
 // they still share the same register name.
+// Strictly speaking, "ca" is a subregister of "xer". However currently we

bzEq wrote:

Maybe a note. I don't think we are modeling other fields like `SO`, `OV` in 
`XER` in the near future.

https://github.com/llvm/llvm-project/pull/77557
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[clang] [PowerPC] Make "ca" aliased to "xer" (PR #77557)

[Kai Luo via cfe-commits]

@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -target powerpc64le -c %s -mllvm -stop-after=finalize-isel -o - 
| \
+// RUN:   FileCheck %s
+// RUN: %clang -target powerpc64 -c %s -mllvm -stop-after=finalize-isel -o - | 
\
+// RUN:   FileCheck %s

bzEq wrote:

Looks `%clang_cc` doesn't accept `-mllvm`.

https://github.com/llvm/llvm-project/pull/77557
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[llvm] [clang] [PowerPC] Make "ca" aliased to "xer" (PR #77557)

[Kai Luo via cfe-commits]

https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/77557

>From e1caee46dc81e59b8eab0379e200ca2a709801c3 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Wed, 10 Jan 2024 05:29:22 +
Subject: [PATCH 1/4] Alias

---
 clang/lib/Basic/Targets/PPC.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 045c273f03c7a0..fa86d93b141180 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -803,7 +803,7 @@ const TargetInfo::GCCRegAlias 
PPCTargetInfo::GCCRegAliases[] = {
 {{"fr22"}, "f22"}, {{"fr23"}, "f23"},   {{"fr24"}, "f24"},
 {{"fr25"}, "f25"}, {{"fr26"}, "f26"},   {{"fr27"}, "f27"},
 {{"fr28"}, "f28"}, {{"fr29"}, "f29"},   {{"fr30"}, "f30"},
-{{"fr31"}, "f31"}, {{"cc"}, "cr0"},
+{{"fr31"}, "f31"}, {{"cc"}, "cr0"}, {{"ca"},   "xer"},
 };
 
 ArrayRef PPCTargetInfo::getGCCRegAliases() const {

>From aaee97fb9f7bef5ff4e3f845fa29d45e9c7a83b0 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Wed, 10 Jan 2024 05:56:27 +
Subject: [PATCH 2/4] CA aliasing to XER

---
 clang/lib/Basic/Targets/PPC.cpp |  3 +++
 clang/test/CodeGen/ppc-register-names.c | 14 ++
 2 files changed, 17 insertions(+)
 create mode 100644 clang/test/CodeGen/ppc-register-names.c

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index fa86d93b141180..abf685f8883971 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -782,6 +782,9 @@ ArrayRef PPCTargetInfo::getGCCRegNames() 
const {
 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
 // While some of these aliases do map to different registers
 // they still share the same register name.
+// Strictly speaking, "ca" is a subregister of "xer". However
+// currently we don't model other bit fields of "xer", so treat
+// "ca" aliasing to "xer".
 {{"0"}, "r0"}, {{"1", "sp"}, "r1"}, {{"2"}, "r2"},
 {{"3"}, "r3"}, {{"4"}, "r4"},   {{"5"}, "r5"},
 {{"6"}, "r6"}, {{"7"}, "r7"},   {{"8"}, "r8"},
diff --git a/clang/test/CodeGen/ppc-register-names.c 
b/clang/test/CodeGen/ppc-register-names.c
new file mode 100644
index 00..209488c2e5f1ae
--- /dev/null
+++ b/clang/test/CodeGen/ppc-register-names.c
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -target powerpc64le -c %s -mllvm -stop-after=finalize-isel -o - 
| \
+// RUN:   FileCheck %s
+// RUN: %clang -target powerpc64 -c %s -mllvm -stop-after=finalize-isel -o - | 
\
+// RUN:   FileCheck %s
+
+void test_function(void) {
+  asm volatile("":::"ca");
+  asm volatile("":::"xer");
+  // CHECK: call void asm sideeffect "", "~{xer}"()
+  // CHECK: call void asm sideeffect "", "~{xer}"()
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $xer
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $xer
+}

>From f871c97964ca600ad62f04993b93912203a8cd02 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Wed, 10 Jan 2024 06:08:04 +
Subject: [PATCH 3/4] Adjust comment

---
 clang/lib/Basic/Targets/PPC.cpp | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index abf685f8883971..01f58b57f6096f 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -782,9 +782,8 @@ ArrayRef PPCTargetInfo::getGCCRegNames() 
const {
 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
 // While some of these aliases do map to different registers
 // they still share the same register name.
-// Strictly speaking, "ca" is a subregister of "xer". However
-// currently we don't model other bit fields of "xer", so treat
-// "ca" aliasing to "xer".
+// Strictly speaking, "ca" is a subregister of "xer". However currently we
+// don't model other bit fields of "xer", so treat "ca" aliased to "xer".
 {{"0"}, "r0"}, {{"1", "sp"}, "r1"}, {{"2"}, "r2"},
 {{"3"}, "r3"}, {{"4"}, "r4"},   {{"5"}, "r5"},
 {{"6"}, "r6"}, {{"7"}, "r7"},   {{"8"}, "r8"},
@@ -806,7 +805,7 @@ const TargetInfo::GCCRegAlias 
PPCTargetInfo::GCCRegAliases[] = {
 {{"fr22"}, "f22"}, {{"fr23"}, "f23"},   {{"fr24"}, "f24"},
 {{"fr25"}, "f25"}, {{"fr26"}, "f26"},   {{"fr27"}, "f27"},
 {{"fr28"}, "f28"}, {{"fr29"}, "f29"},   {{"fr30"}, "f30"},
-{{"fr31"}, "f31"}, {{"cc"}, "cr0"}, {{"ca"},   "xer"},
+{{"fr31"}, "f31"}, {{"cc"}, "cr0"}, {{"ca"}, "xer"},
 };
 
 ArrayRef PPCTargetInfo::getGCCRegAliases() const {

>From 9057159a874ce4693aeee12d36c86ed0ee409c2e Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Thu, 11 Jan 2024 03:20:24 +
Subject: [PATCH 4/4] Backend stuff

---
 llvm/lib/Target/PowerPC/PPCRegisterInfo.td|  8 ---
 .../PowerPC/inline-asm-clobber-xer-ca.ll  | 21 +++
 2 files changed, 26 insertions(+), 3 deletions(-)
 create m

[llvm] [clang] [PowerPC] Make "ca" aliased to "xer" (PR #77557)

[Kai Luo via cfe-commits]

bzEq wrote:

Add test for backend and adjust comment of `CARRY`.

https://github.com/llvm/llvm-project/pull/77557
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[llvm] [clang] [PowerPC] Make "ca" aliased to "xer" (PR #77557)

[Kai Luo via cfe-commits]

@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -target powerpc64le -c %s -mllvm -stop-after=finalize-isel -o - 
| \
+// RUN:   FileCheck %s
+// RUN: %clang -target powerpc64 -c %s -mllvm -stop-after=finalize-isel -o - | 
\
+// RUN:   FileCheck %s

bzEq wrote:

`-mllvm -stop-after=finalize-isel` should make `-c` and `-S` no difference, I 
think.

https://github.com/llvm/llvm-project/pull/77557
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[llvm] [clang] [PowerPC] Make "ca" aliased to "xer" (PR #77557)

[Kai Luo via cfe-commits]

https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/77557

>From e1caee46dc81e59b8eab0379e200ca2a709801c3 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Wed, 10 Jan 2024 05:29:22 +
Subject: [PATCH 1/5] Alias

---
 clang/lib/Basic/Targets/PPC.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 045c273f03c7a0..fa86d93b141180 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -803,7 +803,7 @@ const TargetInfo::GCCRegAlias 
PPCTargetInfo::GCCRegAliases[] = {
 {{"fr22"}, "f22"}, {{"fr23"}, "f23"},   {{"fr24"}, "f24"},
 {{"fr25"}, "f25"}, {{"fr26"}, "f26"},   {{"fr27"}, "f27"},
 {{"fr28"}, "f28"}, {{"fr29"}, "f29"},   {{"fr30"}, "f30"},
-{{"fr31"}, "f31"}, {{"cc"}, "cr0"},
+{{"fr31"}, "f31"}, {{"cc"}, "cr0"}, {{"ca"},   "xer"},
 };
 
 ArrayRef PPCTargetInfo::getGCCRegAliases() const {

>From aaee97fb9f7bef5ff4e3f845fa29d45e9c7a83b0 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Wed, 10 Jan 2024 05:56:27 +
Subject: [PATCH 2/5] CA aliasing to XER

---
 clang/lib/Basic/Targets/PPC.cpp |  3 +++
 clang/test/CodeGen/ppc-register-names.c | 14 ++
 2 files changed, 17 insertions(+)
 create mode 100644 clang/test/CodeGen/ppc-register-names.c

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index fa86d93b141180..abf685f8883971 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -782,6 +782,9 @@ ArrayRef PPCTargetInfo::getGCCRegNames() 
const {
 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
 // While some of these aliases do map to different registers
 // they still share the same register name.
+// Strictly speaking, "ca" is a subregister of "xer". However
+// currently we don't model other bit fields of "xer", so treat
+// "ca" aliasing to "xer".
 {{"0"}, "r0"}, {{"1", "sp"}, "r1"}, {{"2"}, "r2"},
 {{"3"}, "r3"}, {{"4"}, "r4"},   {{"5"}, "r5"},
 {{"6"}, "r6"}, {{"7"}, "r7"},   {{"8"}, "r8"},
diff --git a/clang/test/CodeGen/ppc-register-names.c 
b/clang/test/CodeGen/ppc-register-names.c
new file mode 100644
index 00..209488c2e5f1ae
--- /dev/null
+++ b/clang/test/CodeGen/ppc-register-names.c
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -target powerpc64le -c %s -mllvm -stop-after=finalize-isel -o - 
| \
+// RUN:   FileCheck %s
+// RUN: %clang -target powerpc64 -c %s -mllvm -stop-after=finalize-isel -o - | 
\
+// RUN:   FileCheck %s
+
+void test_function(void) {
+  asm volatile("":::"ca");
+  asm volatile("":::"xer");
+  // CHECK: call void asm sideeffect "", "~{xer}"()
+  // CHECK: call void asm sideeffect "", "~{xer}"()
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $xer
+  // CHECK: INLINEASM &"", {{.*}} implicit-def early-clobber $xer
+}

>From f871c97964ca600ad62f04993b93912203a8cd02 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Wed, 10 Jan 2024 06:08:04 +
Subject: [PATCH 3/5] Adjust comment

---
 clang/lib/Basic/Targets/PPC.cpp | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index abf685f8883971..01f58b57f6096f 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -782,9 +782,8 @@ ArrayRef PPCTargetInfo::getGCCRegNames() 
const {
 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
 // While some of these aliases do map to different registers
 // they still share the same register name.
-// Strictly speaking, "ca" is a subregister of "xer". However
-// currently we don't model other bit fields of "xer", so treat
-// "ca" aliasing to "xer".
+// Strictly speaking, "ca" is a subregister of "xer". However currently we
+// don't model other bit fields of "xer", so treat "ca" aliased to "xer".
 {{"0"}, "r0"}, {{"1", "sp"}, "r1"}, {{"2"}, "r2"},
 {{"3"}, "r3"}, {{"4"}, "r4"},   {{"5"}, "r5"},
 {{"6"}, "r6"}, {{"7"}, "r7"},   {{"8"}, "r8"},
@@ -806,7 +805,7 @@ const TargetInfo::GCCRegAlias 
PPCTargetInfo::GCCRegAliases[] = {
 {{"fr22"}, "f22"}, {{"fr23"}, "f23"},   {{"fr24"}, "f24"},
 {{"fr25"}, "f25"}, {{"fr26"}, "f26"},   {{"fr27"}, "f27"},
 {{"fr28"}, "f28"}, {{"fr29"}, "f29"},   {{"fr30"}, "f30"},
-{{"fr31"}, "f31"}, {{"cc"}, "cr0"}, {{"ca"},   "xer"},
+{{"fr31"}, "f31"}, {{"cc"}, "cr0"}, {{"ca"}, "xer"},
 };
 
 ArrayRef PPCTargetInfo::getGCCRegAliases() const {

>From 9057159a874ce4693aeee12d36c86ed0ee409c2e Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Thu, 11 Jan 2024 03:20:24 +
Subject: [PATCH 4/5] Backend stuff

---
 llvm/lib/Target/PowerPC/PPCRegisterInfo.td|  8 ---
 .../PowerPC/inline-asm-clobber-xer-ca.ll  | 21 +++
 2 files changed, 26 insertions(+), 3 deletions(-)
 create m

[clang] b8388fa - [clang][NFC] Fix warning of integer comparison

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2022-03-24T14:06:45+08:00
New Revision: b8388fa319bc68bee396a14857331fb2e7b815bd

URL: 
https://github.com/llvm/llvm-project/commit/b8388fa319bc68bee396a14857331fb2e7b815bd
DIFF: 
https://github.com/llvm/llvm-project/commit/b8388fa319bc68bee396a14857331fb2e7b815bd.diff

LOG: [clang][NFC] Fix warning of integer comparison

```
warning: comparison of integers of different signs: 'const unsigned long' and 
'const int' [-Wsign-compare]
```

Fix https://lab.llvm.org/buildbot/#/builders/57/builds/16220.

Added: 


Modified: 
clang/unittests/AST/DeclTest.cpp

Removed: 




diff  --git a/clang/unittests/AST/DeclTest.cpp 
b/clang/unittests/AST/DeclTest.cpp
index bf2826c7b329f..7c227d40af86b 100644
--- a/clang/unittests/AST/DeclTest.cpp
+++ b/clang/unittests/AST/DeclTest.cpp
@@ -188,7 +188,7 @@ TEST(Decl, InConsistLinkageForTemplates) {
   llvm::SmallVector Funcs =
   match(functionDecl().bind("f"), Ctx);
 
-  EXPECT_EQ(Funcs.size(), 2);
+  EXPECT_EQ(Funcs.size(), 2U);
   const FunctionDecl *TemplateF = Funcs[0].getNodeAs("f");
   const FunctionDecl *SpecializedF = Funcs[1].getNodeAs("f");
   EXPECT_EQ(TemplateF->getLinkageInternal(),



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[clang] 1cbaf68 - [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2022-07-27T01:56:25Z
New Revision: 1cbaf681b0f1e7257e7e2a63d290a20216668f17

URL: 
https://github.com/llvm/llvm-project/commit/1cbaf681b0f1e7257e7e2a63d290a20216668f17
DIFF: 
https://github.com/llvm/llvm-project/commit/1cbaf681b0f1e7257e7e2a63d290a20216668f17.diff

LOG: [clang][AIX] Add option to control quadword lock free atomics ABI on AIX

We are supporting quadword lock free atomics on AIX. For the situation that 
users on AIX are using a libatomic that is lock-based for quadword types, we 
can't enable quadword lock free atomics by default on AIX in case user's new 
code and existing code accessing the same shared atomic quadword variable, we 
can't guarentee atomicity. So we need an option to enable quadword lock free 
atomics on AIX, thus we can build a quadword lock-free libatomic(also for 
advanced users considering atomic performance critical) for users to make the 
transition smooth.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D127189

Added: 
clang/test/Driver/aix-quadword-atomics-abi.c

Modified: 
clang/include/clang/Basic/LangOptions.def
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/CodeGen/PowerPC/quadword-atomics.c
clang/test/Driver/ppc-unsupported.c
clang/test/Sema/atomic-ops.c

Removed: 




diff  --git a/clang/include/clang/Basic/LangOptions.def 
b/clang/include/clang/Basic/LangOptions.def
index 6fb31c5655ab..ad366821f3cb 100644
--- a/clang/include/clang/Basic/LangOptions.def
+++ b/clang/include/clang/Basic/LangOptions.def
@@ -195,6 +195,7 @@ VALUE_LANGOPT(DoubleSize, 32, 0, "width of 
double")
 VALUE_LANGOPT(LongDoubleSize, 32, 0, "width of long double")
 LANGOPT(PPCIEEELongDouble, 1, 0, "use IEEE 754 quadruple-precision 
for long double")
 LANGOPT(EnableAIXExtendedAltivecABI  , 1, 0, "__EXTABI__  predefined macro")
+LANGOPT(EnableAIXQuadwordAtomicsABI  , 1, 0, "Use 16-byte atomic lock free 
semantics")
 COMPATIBLE_VALUE_LANGOPT(PICLevel, 2, 0, "__PIC__ level")
 COMPATIBLE_VALUE_LANGOPT(PIE , 1, 0, "is pie")
 LANGOPT(ROPI , 1, 0, "Read-only position independence")

diff  --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index b9c2e4d528e4..3cab37b21aaf 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -3679,6 +3679,10 @@ def mabi_EQ_vec_extabi : Flag<["-"], "mabi=vec-extabi">, 
Group, Flags<[
   MarshallingInfoFlag>;
 def mabi_EQ_vec_default : Flag<["-"], "mabi=vec-default">, Group, 
Flags<[CC1Option]>,
   HelpText<"Enable the default Altivec ABI on AIX (AIX only). Uses only 
volatile vector registers.">;
+def mabi_EQ_quadword_atomics : Flag<["-"], "mabi=quadword-atomics">,
+  Group, Flags<[CC1Option]>,
+  HelpText<"Enable quadword atomics ABI on AIX (AIX PPC64 only). Uses 
lqarx/stqcx. instructions.">,
+  MarshallingInfoFlag>;
 def mvsx : Flag<["-"], "mvsx">, Group;
 def mno_vsx : Flag<["-"], "mno-vsx">, Group;
 def msecure_plt : Flag<["-"], "msecure-plt">, Group;

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 9120808e298d..ca01b44ae3a5 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -849,6 +849,9 @@ void PPCTargetInfo::adjust(DiagnosticsEngine &Diags, 
LangOptions &Opts) {
? &llvm::APFloat::IEEEquad()
: &llvm::APFloat::PPCDoubleDouble();
   Opts.IEEE128 = 1;
+  if (getTriple().isOSAIX() && Opts.EnableAIXQuadwordAtomicsABI &&
+  HasQuadwordAtomics)
+MaxAtomicInlineWidth = 128;
 }
 
 ArrayRef PPCTargetInfo::getTargetBuiltins() const {

diff  --git a/clang/lib/Driver/ToolChains/Clang.cpp 
b/clang/lib/Driver/ToolChains/Clang.cpp
index 3044c2d92d21..b62a025c5072 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -5112,6 +5112,13 @@ void Clang::ConstructJob(Compilation &C, const JobAction 
&JA,
   CmdArgs.push_back("-mabi=vec-default");
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ_quadword_atomics)) {
+if (!Triple.isOSAIX() || Triple.isPPC32())
+  D.Diag(diag::err_drv_unsupported_opt_for_target)
+<< A->getSpelling() << RawTriple.str();
+CmdArgs.push_back("-mabi=quadword-atomics");
+  }
+
   if (Arg *A = Args.getLastArg(options::OPT_mlong_double_128)) {
 // Emit the unsupported option error until the Clang's library integration
 // support for 128-bit long double is available for AIX.

diff  --git a/clang/lib/Frontend/CompilerInvocation.cpp 
b/clang/lib/Frontend/CompilerInvocation.cpp
index 48cd6a394107..2dd96e68bb92 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -1926,6 +

[clang] e4ed93c - [PowerPC] Implement XL compatible behavior of __compare_and_swap

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2021-07-23T01:16:02Z
New Revision: e4ed93cb25acc624a1d32e77d2c63c8c25fddbae

URL: 
https://github.com/llvm/llvm-project/commit/e4ed93cb25acc624a1d32e77d2c63c8c25fddbae
DIFF: 
https://github.com/llvm/llvm-project/commit/e4ed93cb25acc624a1d32e77d2c63c8c25fddbae.diff

LOG: [PowerPC] Implement XL compatible behavior of __compare_and_swap

According to 
https://www.ibm.com/docs/en/xl-c-and-cpp-aix/16.1?topic=functions-compare-swap-compare-swaplp
XL's `__compare_and_swap` has a weird behavior that

> In either case, the contents of the memory location specified by addr are 
> copied into the memory location specified by old_val_addr.

(unlike c11 `atomic_compare_exchange` specified in 
http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1548.pdf)

This patch let clang's implementation follow this behavior.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D106344

Added: 
llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll

Modified: 
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-cas.c

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index a4d0d87f2cbc..a3a0c3e88359 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15662,6 +15662,15 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 auto Pair = EmitAtomicCompareExchange(
 LV, RValue::get(OldVal), RValue::get(Ops[2]), E->getExprLoc(),
 llvm::AtomicOrdering::Monotonic, llvm::AtomicOrdering::Monotonic, 
true);
+// Unlike c11's atomic_compare_exchange, accroding to
+// 
https://www.ibm.com/docs/en/xl-c-and-cpp-aix/16.1?topic=functions-compare-swap-compare-swaplp
+// > In either case, the contents of the memory location specified by addr
+// > are copied into the memory location specified by old_val_addr.
+// But it hasn't specified storing to OldValAddr is atomic or not and
+// which order to use. Now following XL's codegen, treat it as a normal
+// store.
+Value *LoadedVal = Pair.first.getScalarVal();
+Builder.CreateStore(LoadedVal, OldValAddr);
 return Pair.second;
   }
   case PPC::BI__builtin_ppc_fetch_and_add:

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-cas.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
index ea4b349d9a52..cd66eb09d36f 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
@@ -19,6 +19,7 @@
 // CHECK-NEXT:[[TMP2:%.*]] = cmpxchg weak volatile i32* [[A_ADDR]], i32 
[[TMP1]], i32 [[TMP0]] monotonic monotonic, align 4
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
+// CHECK-NEXT:store i32 [[TMP3]], i32* [[B_ADDR]], align 4
 // CHECK-NEXT:ret void
 //
 void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
@@ -39,6 +40,7 @@ void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
 // CHECK-NEXT:[[TMP2:%.*]] = cmpxchg weak volatile i64* [[A_ADDR]], i64 
[[TMP1]], i64 [[TMP0]] monotonic monotonic, align 8
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
+// CHECK-NEXT:store i64 [[TMP3]], i64* [[B_ADDR]], align 8
 // CHECK-NEXT:ret void
 //
 void test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {

diff  --git a/llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll 
b/llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll
new file mode 100644
index ..a3279c8a2c2c
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/opt-builtins-ppc-xlcompat-cas.ll
@@ -0,0 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -enable-new-pm=1 -S -passes='default' %s -o - | FileCheck %s
+define void @test_builtin_ppc_compare_and_swaplp(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: @test_builtin_ppc_compare_and_swaplp(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+; CHECK-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+; CHECK-NEXT:[[TMP0:%.*]] = cmpxchg weak volatile i64* [[A_ADDR]], i64 
[[B:%.*]], i64 [[C:%.*]] monotonic monotonic, align 8
+; CHECK-NEXT:ret void
+;
+entry:
+  %a.addr = alloca i64, align 8
+  %b.addr = alloca i64, align 8
+  %c.addr = alloca i64, align 8
+  store i64 %a, i64* %a.addr, align 8
+  store i64 %b, i64* %b.addr, align 8
+  store i64 %c, i64* %c.addr, align 8
+  %0 = load i64, i64* %c.addr, align 8
+  %1 = load i64, i64* %b.addr, align 8
+  %2 = cmpxchg weak volatile i64* %a.addr, i64 %1, i64 %0 monotonic monotonic, 
align 8
+  %3 = extractvalue { i64, i1 } %2, 0
+  %4 = extractvalue { i64, i1 } %2, 1
+  store i64 %3, i64* %b.addr, align 8
+  ret void
+}
+
+define dso_local void @test_builtin_ppc_compare_and_swaplp_loop

[clang] e4902e6 - [PowerPC] Fix return type of XL compat CAS

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2021-07-29T14:49:26Z
New Revision: e4902e69e99d07d6d311425d87d4c1d075b72bf8

URL: 
https://github.com/llvm/llvm-project/commit/e4902e69e99d07d6d311425d87d4c1d075b72bf8
DIFF: 
https://github.com/llvm/llvm-project/commit/e4902e69e99d07d6d311425d87d4c1d075b72bf8.diff

LOG: [PowerPC] Fix return type of XL compat CAS

`__compare_and_swap*` should return `i32` rather than `i1`.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D107077

Added: 


Modified: 
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-cas.c

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index d9b2a5fe16bec..b316a865f2fc7 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15808,7 +15808,7 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 // store.
 Value *LoadedVal = Pair.first.getScalarVal();
 Builder.CreateStore(LoadedVal, OldValAddr);
-return Pair.second;
+return Builder.CreateZExt(Pair.second, Builder.getInt32Ty());
   }
   case PPC::BI__builtin_ppc_fetch_and_add:
   case PPC::BI__builtin_ppc_fetch_and_addlp: {

diff  --git a/clang/test/CodeGen/builtins-ppc-xlcompat-cas.c 
b/clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
index cd66eb09d36f3..9407f696d6ff9 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-cas.c
@@ -20,10 +20,11 @@
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
 // CHECK-NEXT:store i32 [[TMP3]], i32* [[B_ADDR]], align 4
-// CHECK-NEXT:ret void
+// CHECK-NEXT:[[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+// CHECK-NEXT:ret i32 [[TMP5]]
 //
-void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
-  __compare_and_swap(&a, &b, c);
+int test_builtin_ppc_compare_and_swap(int a, int b, int c) {
+  return __compare_and_swap(&a, &b, c);
 }
 
 
@@ -41,9 +42,10 @@ void test_builtin_ppc_compare_and_swap(int a, int b, int c) {
 // CHECK-NEXT:[[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
 // CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
 // CHECK-NEXT:store i64 [[TMP3]], i64* [[B_ADDR]], align 8
-// CHECK-NEXT:ret void
+// CHECK-NEXT:[[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+// CHECK-NEXT:ret i32 [[TMP5]]
 //
-void test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
-  __compare_and_swaplp(&a, &b, c);
+int test_builtin_ppc_compare_and_swaplp(long a, long b, long c) {
+  return __compare_and_swaplp(&a, &b, c);
 }
 



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[clang] 9247145 - [PowerPC][NFC] Add atomic alignments and ops tests for powerpc

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2022-03-18T13:22:28+08:00
New Revision: 9247145fbae7c4273acd6b8f3b331716ca80bf18

URL: 
https://github.com/llvm/llvm-project/commit/9247145fbae7c4273acd6b8f3b331716ca80bf18
DIFF: 
https://github.com/llvm/llvm-project/commit/9247145fbae7c4273acd6b8f3b331716ca80bf18.diff

LOG: [PowerPC][NFC] Add atomic alignments and ops tests for powerpc

PowerPC is lacking tests checking `_Atomic` alignment in cfe. Adding these 
tests since we're going to make change to align with gcc on Linux.

Reviewed By: hubert.reinterpretcast, jsji

Differential Revision: https://reviews.llvm.org/D121441

Added: 
clang/test/CodeGen/PowerPC/atomic-alignment.c

Modified: 
clang/test/Sema/atomic-ops.c

Removed: 




diff  --git a/clang/test/CodeGen/PowerPC/atomic-alignment.c 
b/clang/test/CodeGen/PowerPC/atomic-alignment.c
new file mode 100644
index 0..cd6985962c39e
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -0,0 +1,37 @@
+// RUN: %clang_cc1 -verify -triple powerpc-unknown-unknown -emit-llvm -o - %s 
| \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC32
+// RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux -emit-llvm -o - 
%s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -verify -triple powerpc64-unknown-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+
+// PPC: @c = global i8 0, align 1{{$}}
+_Atomic(char) c; // expected-no-diagnostics
+
+// PPC: @s = global i16 0, align 2{{$}}
+_Atomic(short) s; // expected-no-diagnostics
+
+// PPC: @i = global i32 0, align 4{{$}}
+_Atomic(int) i; // expected-no-diagnostics
+
+// PPC32: @l = global i32 0, align 4{{$}}
+// PPC64: @l = global i64 0, align 8{{$}}
+_Atomic(long) l; // expected-no-diagnostics
+
+// PPC: @ll = global i64 0, align 8{{$}}
+_Atomic(long long) ll; // expected-no-diagnostics
+
+typedef struct {
+  char x[8];
+} O;
+
+// PPC32: @o = global %struct.O zeroinitializer, align 1{{$}}
+// PPC64: @o = global %struct.O zeroinitializer, align 8{{$}}
+_Atomic(O) o; // expected-no-diagnostics
+
+typedef struct {
+  char x[16];
+} Q;
+
+// PPC: @q = global %struct.Q zeroinitializer, align 1{{$}}
+_Atomic(Q) q; // expected-no-diagnostics

diff  --git a/clang/test/Sema/atomic-ops.c b/clang/test/Sema/atomic-ops.c
index 160a0c09903d9..a3c156d6663b9 100644
--- a/clang/test/Sema/atomic-ops.c
+++ b/clang/test/Sema/atomic-ops.c
@@ -4,6 +4,12 @@
 // RUN:   -fsyntax-only -triple=i686-linux-android -std=c11
 // RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
 // RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64-linux-gnu -std=c11 \
+// RUN:   -target-cpu pwr7
+// RUN: %clang_cc1 %s -verify -fgnuc-version=4.2.1 -ffreestanding \
+// RUN:   -fsyntax-only -triple=powerpc64le-linux-gnu -std=c11 \
+// RUN:   -target-cpu pwr8
 
 // Basic parsing/Sema tests for __c11_atomic_*
 



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[clang] 549e118 - [PowerPC] Support 16-byte lock free atomics on pwr8 and up

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2022-04-08T23:25:56Z
New Revision: 549e118e93c666914a1045fde38a2cac33e1e445

URL: 
https://github.com/llvm/llvm-project/commit/549e118e93c666914a1045fde38a2cac33e1e445
DIFF: 
https://github.com/llvm/llvm-project/commit/549e118e93c666914a1045fde38a2cac33e1e445.diff

LOG: [PowerPC] Support 16-byte lock free atomics on pwr8 and up

Make 16-byte atomic type aligned to 16-byte on PPC64, thus consistent with GCC. 
Also enable inlining 16-byte atomics on non-AIX targets on PPC64.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D122377

Added: 
clang/test/CodeGen/PowerPC/quadword-atomics.c

Modified: 
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/CodeGen/PowerPC/atomic-alignment.c
clang/test/Sema/atomic-ops.c
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/test/CodeGen/PowerPC/atomics-i128.ll

Removed: 




diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index bafcc23b38334..1f2f583b9462d 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -81,6 +81,8 @@ bool 
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
   IsISA3_0 = true;
 } else if (Feature == "+isa-v31-instructions") {
   IsISA3_1 = true;
+} else if (Feature == "+quadword-atomics") {
+  HasQuadwordAtomics = true;
 }
 // TODO: Finish this list and add an assert that we've handled them
 // all.
@@ -550,6 +552,12 @@ bool PPCTargetInfo::initFeatureMap(
   Features["isa-v30-instructions"] =
   llvm::StringSwitch(CPU).Case("pwr9", true).Default(false);
 
+  Features["quadword-atomics"] =
+  getTriple().isArch64Bit() && llvm::StringSwitch(CPU)
+   .Case("pwr9", true)
+   .Case("pwr8", true)
+   .Default(false);
+
   // Power10 includes all the same features as Power9 plus any features 
specific
   // to the Power10 core.
   if (CPU == "pwr10" || CPU == "power10") {
@@ -660,6 +668,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
   .Case("isa-v207-instructions", IsISA2_07)
   .Case("isa-v30-instructions", IsISA3_0)
   .Case("isa-v31-instructions", IsISA3_1)
+  .Case("quadword-atomics", HasQuadwordAtomics)
   .Default(false);
 }
 

diff  --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index ac52eb219f54d..44489d06307f2 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -78,6 +78,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   bool IsISA2_07 = false;
   bool IsISA3_0 = false;
   bool IsISA3_1 = false;
+  bool HasQuadwordAtomics = false;
 
 protected:
   std::string ABI;
@@ -439,8 +440,18 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public 
PPCTargetInfo {
   DataLayout += "-S128-v256:256:256-v512:512:512";
 resetDataLayout(DataLayout);
 
-// PPC64 supports atomics up to 8 bytes.
-MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+// Newer PPC64 instruction sets support atomics up to 16 bytes.
+MaxAtomicPromoteWidth = 128;
+// Baseline PPC64 supports inlining atomics up to 8 bytes.
+MaxAtomicInlineWidth = 64;
+  }
+
+  void setMaxAtomicWidth() override {
+// For power8 and up, backend is able to inline 16-byte atomic lock free
+// code.
+// TODO: We should allow AIX to inline quadword atomics in the future.
+if (!getTriple().isOSAIX() && hasFeature("quadword-atomics"))
+  MaxAtomicInlineWidth = 128;
   }
 
   BuiltinVaListKind getBuiltinVaListKind() const override {

diff  --git a/clang/test/CodeGen/PowerPC/atomic-alignment.c 
b/clang/test/CodeGen/PowerPC/atomic-alignment.c
index cd6985962c39e..537ba1a95c048 100644
--- a/clang/test/CodeGen/PowerPC/atomic-alignment.c
+++ b/clang/test/CodeGen/PowerPC/atomic-alignment.c
@@ -1,25 +1,30 @@
-// RUN: %clang_cc1 -verify -triple powerpc-unknown-unknown -emit-llvm -o - %s 
| \
+// RUN: %clang_cc1 -Werror -triple powerpc-unknown-unknown -emit-llvm -o - %s 
| \
 // RUN:   FileCheck %s --check-prefixes=PPC,PPC32
-// RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux -emit-llvm -o - 
%s | \
-// RUN:   FileCheck %s --check-prefixes=PPC,PPC64
-// RUN: %clang_cc1 -verify -triple powerpc64-unknown-aix -emit-llvm -o - %s | \
+// RUN: %clang_cc1 -Werror -triple powerpc64le-unknown-linux -emit-llvm -o - 
%s | \
 // RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -Werror -triple powerpc64le-unknown-linux -emit-llvm -o - 
%s \
+// RUN:   -target-cpu pwr8 | FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -Werror -triple powerpc64-unknown-aix -emit-llvm -o - %s | \
+// RUN:   FileCheck %s --check-prefixes=PPC,AIX64
+// RUN: %clang_cc1 -Werror -triple powerpc64-unknown-aix 

[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level by heuristic (PR #84132)

[Kai Luo via cfe-commits]

@@ -80,6 +80,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   bool IsISA3_0 = false;
   bool IsISA3_1 = false;
   bool HasQuadwordAtomics = false;
+  bool HasAIXShLibTLSModelHeuristic = false;

bzEq wrote:

This looks redundant. Frontend doesn't read this flag to change behavior.

https://github.com/llvm/llvm-project/pull/84132
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[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level by heuristic (PR #84132)

[Kai Luo via cfe-commits]

@@ -3369,6 +3369,48 @@ SDValue 
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
   bool Is64Bit = Subtarget.isPPC64();
   bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
   TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+  // Initialize heuristic setting lazily:
+  // (1) Use initial-exec for single TLS var reference within current function.
+  // (2) Use local-dynamic for multiple TLS var references within current func.
+  PPCFunctionInfo *FuncInfo =
+  DAG.getMachineFunction().getInfo();
+  if (Subtarget.hasAIXShLibTLSModelHeuristic() &&
+  !FuncInfo->isAIXFuncUseInitDone()) {
+std::set TLSGV;
+for (SDNode &Node : DAG.allnodes()) {

bzEq wrote:

One DAG is mapped to a single basic block, I notice your description is about 
whole function. So the size of `TLSGV` is smaller than what you really want to 
count.

https://github.com/llvm/llvm-project/pull/84132
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[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level by heuristic (PR #84132)

[Kai Luo via cfe-commits]

@@ -3369,6 +3369,48 @@ SDValue 
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
   bool Is64Bit = Subtarget.isPPC64();
   bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
   TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+  // Initialize heuristic setting lazily:
+  // (1) Use initial-exec for single TLS var reference within current function.
+  // (2) Use local-dynamic for multiple TLS var references within current func.
+  PPCFunctionInfo *FuncInfo =
+  DAG.getMachineFunction().getInfo();
+  if (Subtarget.hasAIXShLibTLSModelHeuristic() &&
+  !FuncInfo->isAIXFuncUseInitDone()) {
+std::set TLSGV;

bzEq wrote:

```suggestion
SmallPtrSet TLSGV;
```

https://github.com/llvm/llvm-project/pull/84132
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[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level by heuristic (PR #84132)

[Kai Luo via cfe-commits]

@@ -329,6 +329,12 @@ def FeatureAIXLocalExecTLS :
"Produce a TOC-free local-exec TLS sequence for this 
function "
"for 64-bit AIX">;
 
+def FeatureAIXSharedLibraryTLSModelHeuristic :
+  SubtargetFeature<"aix-shared-library-tls-model-heuristic",

bzEq wrote:

This should be an optimization, maybe rename to 
`aix-shared-library-tls-model-opt`, we perform optimization based on some 
heuristics.

https://github.com/llvm/llvm-project/pull/84132
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[clang] [PowerPC][RFC] Make power9-vector indicate isa-3.0 and power9-altivec (PR #86905)

[Kai Luo via cfe-commits]

https://github.com/bzEq created https://github.com/llvm/llvm-project/pull/86905

This is to address https://github.com/llvm/llvm-project/issues/84703. However 
this might not be a long-term solution in my view.

>From 99e76dbe0016332ed1d21edbf5297cd5189afe3d Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Thu, 28 Mar 2024 03:31:30 +
Subject: [PATCH] Indicate pwr9 and p9 altivec

---
 clang/lib/Basic/Targets/PPC.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index aebe51bfa4daad..14caa1898a9eb8 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -597,6 +597,7 @@ bool PPCTargetInfo::initFeatureMap(
   .Default(false);
 
   Features["isa-v30-instructions"] =
+  llvm::is_contained(FeaturesVec, "+power9-vector") or
   llvm::StringSwitch(CPU).Case("pwr9", true).Default(false);
 
   Features["quadword-atomics"] =
@@ -605,6 +606,8 @@ bool PPCTargetInfo::initFeatureMap(
.Case("pwr8", true)
.Default(false);
 
+  Features["power9-altivec"] = llvm::is_contained(FeaturesVec, 
"+power9-vector");
+
   // Power10 includes all the same features as Power9 plus any features 
specific
   // to the Power10 core.
   if (CPU == "pwr10" || CPU == "power10") {

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[clang] [llvm] [PowerPC] Implement 32-bit expansion for rldimi (PR #86783)

[Kai Luo via cfe-commits]

bzEq wrote:

> due to backward compatibility, it needs to be expanded into series of rlwimi 
> in 32-bit environment

Why must be 'series of rlwimi'?

Why don't we just expand it following what ISA describes and let legalizer 
generates code sequence under 32-bit mode?
```
n ← sh5 || sh0:4
r ← ROTL64((RS), n)
b ← mb5 || mb0:4
m ← MASK(b, ¬n) RA ← r&m | (RA) & ¬m
```

https://github.com/llvm/llvm-project/pull/86783
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[clang] [llvm] [clang-tools-extra] [PowerPC] Check value uses in ValueBit tracking (PR #66040)

[Kai Luo via cfe-commits]

bzEq wrote:

Though I do see some codegen improvement, I don't think we should check uses 
inside `getValueBits`, since `getValueBits` is for analysis and is gathering as 
much information as it can. Can you post your motivation code?

https://github.com/llvm/llvm-project/pull/66040
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[llvm] [libcxxabi] [libcxx] [clang-tools-extra] [libunwind] [compiler-rt] [lld] [libc] [clang] [flang] [lldb] [PowerPC] Combine sub within setcc back to sext (PR #66978)

[Kai Luo via cfe-commits]

bzEq wrote:

Please provide more description in PR summary.

https://github.com/llvm/llvm-project/pull/66978
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[clang-tools-extra] [libunwind] [libcxx] [compiler-rt] [clang] [llvm] [lld] [libcxxabi] [lldb] [libc] [flang] [PowerPC] Combine sub within setcc back to sext (PR #66978)

[Kai Luo via cfe-commits]

@@ -14428,15 +14431,52 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
 // x != 0-y --> x+y != 0
 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
 RHS.hasOneUse()) {
-  SDLoc DL(N);
-  SelectionDAG &DAG = DCI.DAG;
-  EVT VT = N->getValueType(0);
-  EVT OpVT = LHS.getValueType();
   SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
   return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
 }
   }
 
+  if (CC == ISD::SETULT && isa(RHS)) {
+uint64_t RHSVal = cast(RHS)->getZExtValue();
+if (LHS.getOpcode() == ISD::ADD && isa(LHS.getOperand(1))) 
{
+  uint64_t Addend = 
cast(LHS.getOperand(1))->getZExtValue();
+  if (OpVT == MVT::i64) {
+uint64_t ShiftVal = ~Addend + 1;

bzEq wrote:

```suggestion
uint64_t ShiftVal = -Addend;
```

https://github.com/llvm/llvm-project/pull/66978
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[libcxx] [lldb] [compiler-rt] [clang-tools-extra] [flang] [clang] [libcxxabi] [libc] [libunwind] [lld] [llvm] [PowerPC] Combine sub within setcc back to sext (PR #66978)

[Kai Luo via cfe-commits]

@@ -14428,15 +14431,52 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
 // x != 0-y --> x+y != 0
 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
 RHS.hasOneUse()) {
-  SDLoc DL(N);
-  SelectionDAG &DAG = DCI.DAG;
-  EVT VT = N->getValueType(0);
-  EVT OpVT = LHS.getValueType();
   SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
   return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
 }
   }
 
+  if (CC == ISD::SETULT && isa(RHS)) {
+uint64_t RHSVal = cast(RHS)->getZExtValue();
+if (LHS.getOpcode() == ISD::ADD && isa(LHS.getOperand(1))) 
{
+  uint64_t Addend = 
cast(LHS.getOperand(1))->getZExtValue();
+  if (OpVT == MVT::i64) {
+uint64_t ShiftVal = ~Addend + 1;
+uint64_t CmpVal = ~RHSVal + 1;

bzEq wrote:

```suggestion
uint64_t CmpVal = -RHSVal;
```

https://github.com/llvm/llvm-project/pull/66978
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[libunwind] [clang-tools-extra] [lld] [flang] [libc] [compiler-rt] [libcxx] [clang] [libcxxabi] [lldb] [llvm] [PowerPC] Combine sub within setcc back to sext (PR #66978)

[Kai Luo via cfe-commits]

@@ -14428,15 +14431,52 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
 // x != 0-y --> x+y != 0
 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
 RHS.hasOneUse()) {
-  SDLoc DL(N);
-  SelectionDAG &DAG = DCI.DAG;
-  EVT VT = N->getValueType(0);
-  EVT OpVT = LHS.getValueType();
   SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
   return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
 }
   }
 
+  if (CC == ISD::SETULT && isa(RHS)) {
+uint64_t RHSVal = cast(RHS)->getZExtValue();
+if (LHS.getOpcode() == ISD::ADD && isa(LHS.getOperand(1))) 
{
+  uint64_t Addend = 
cast(LHS.getOperand(1))->getZExtValue();
+  if (OpVT == MVT::i64) {
+uint64_t ShiftVal = ~Addend + 1;
+uint64_t CmpVal = ~RHSVal + 1;
+if (isPowerOf2_64(ShiftVal) && ShiftVal << 1 == CmpVal) {

bzEq wrote:

Add comment for the DAG pattern found. Better provide alive2 prove in the PR 
summary.

https://github.com/llvm/llvm-project/pull/66978
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[clang] [llvm] [PowerPC] Make "ca" aliased to "xer" (PR #77557)

[Kai Luo via cfe-commits]

@@ -288,9 +288,9 @@ def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
 
 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
 
-// Carry bit.  In the architecture this is really bit 0 of the XER register
-// (which really is SPR register 1);  this is the only bit interesting to a
-// compiler.
+// Carry bit. In the architecture this is really bit 2 of the 32-bit XER

bzEq wrote:

> Is there a history of the compiler assuming that all SPR are 32 bits?

The code was written more than a decade ago. I guess authors referenced *The 
PowerPC Compiler Writer’s Guide*. Figure 2-1 of the book shows XER, FPER, FPSCR 
are 32-bit width even under 64-bit environment.

In appendix, there is

> Carry bit Bit 2 in the Fixed-Point Exception Register (XER).

https://github.com/llvm/llvm-project/pull/77557
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[llvm] [clang] [PowerPC] Make "ca" aliased to "xer" (PR #77557)

[Kai Luo via cfe-commits]

@@ -782,6 +782,8 @@ ArrayRef PPCTargetInfo::getGCCRegNames() 
const {
 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
 // While some of these aliases do map to different registers
 // they still share the same register name.
+// Strictly speaking, "ca" is a subregister of "xer". However currently we

bzEq wrote:

> If that happens, would we have to add those other fields and then specify 
> them as proper subregs of XER?

I think so. However, existing instructions look not using other fields like OV 
and OV32.

> does GCC support on PowerPC?

Currently, GCC looks only support `xer` and `ca`. See 
https://godbolt.org/z/6qWqc3Pdd. I have tried using `ov`, hit CE.

https://github.com/llvm/llvm-project/pull/77557
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[llvm] [clang] [PowerPC] Make "ca" aliased to "xer" (PR #77557)

[Kai Luo via cfe-commits]

@@ -288,9 +288,9 @@ def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
 
 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
 
-// Carry bit.  In the architecture this is really bit 0 of the XER register
-// (which really is SPR register 1);  this is the only bit interesting to a
-// compiler.
+// Carry bit. In the architecture this is really bit 2 of the 32-bit XER

bzEq wrote:

I'll update it according to OpenPower's ISA, since it's more generally 
available.

https://github.com/llvm/llvm-project/pull/77557
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[clang] 6ea2431 - [clang][compiler-rt][atomics] Add `__c11_atomic_fetch_nand` builtin and support `__atomic_fetch_nand` libcall

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2021-10-28T02:18:43Z
New Revision: 6ea2431d3f109aefa31cd4d520cc234a5aa5484a

URL: 
https://github.com/llvm/llvm-project/commit/6ea2431d3f109aefa31cd4d520cc234a5aa5484a
DIFF: 
https://github.com/llvm/llvm-project/commit/6ea2431d3f109aefa31cd4d520cc234a5aa5484a.diff

LOG: [clang][compiler-rt][atomics] Add `__c11_atomic_fetch_nand` builtin and 
support `__atomic_fetch_nand` libcall

Add `__c11_atomic_fetch_nand` builtin to language extensions and support 
`__atomic_fetch_nand` libcall in compiler-rt.

Reviewed By: theraven

Differential Revision: https://reviews.llvm.org/D112400

Added: 


Modified: 
clang/docs/LanguageExtensions.rst
clang/include/clang/Basic/Builtins.def
clang/lib/AST/Expr.cpp
clang/lib/CodeGen/CGAtomic.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/Sema/atomic-implicit-seq_cst.c
clang/test/Sema/atomic-ops.c
compiler-rt/lib/builtins/atomic.c
compiler-rt/test/builtins/Unit/atomic_test.c

Removed: 




diff  --git a/clang/docs/LanguageExtensions.rst 
b/clang/docs/LanguageExtensions.rst
index 143b2359b58d7..da2c90778ef46 100644
--- a/clang/docs/LanguageExtensions.rst
+++ b/clang/docs/LanguageExtensions.rst
@@ -2866,6 +2866,7 @@ the corresponding C11 operations, are:
 * ``__c11_atomic_fetch_and``
 * ``__c11_atomic_fetch_or``
 * ``__c11_atomic_fetch_xor``
+* ``__c11_atomic_fetch_nand`` (Nand is not presented in )
 * ``__c11_atomic_fetch_max``
 * ``__c11_atomic_fetch_min``
 

diff  --git a/clang/include/clang/Basic/Builtins.def 
b/clang/include/clang/Basic/Builtins.def
index 874bc655a00b7..7d331a86126f1 100644
--- a/clang/include/clang/Basic/Builtins.def
+++ b/clang/include/clang/Basic/Builtins.def
@@ -796,6 +796,7 @@ ATOMIC_BUILTIN(__c11_atomic_fetch_sub, "v.", "t")
 ATOMIC_BUILTIN(__c11_atomic_fetch_and, "v.", "t")
 ATOMIC_BUILTIN(__c11_atomic_fetch_or, "v.", "t")
 ATOMIC_BUILTIN(__c11_atomic_fetch_xor, "v.", "t")
+ATOMIC_BUILTIN(__c11_atomic_fetch_nand, "v.", "t")
 ATOMIC_BUILTIN(__c11_atomic_fetch_max, "v.", "t")
 ATOMIC_BUILTIN(__c11_atomic_fetch_min, "v.", "t")
 BUILTIN(__c11_atomic_thread_fence, "vi", "n")

diff  --git a/clang/lib/AST/Expr.cpp b/clang/lib/AST/Expr.cpp
index e9ee624e499da..415b6e52b564b 100644
--- a/clang/lib/AST/Expr.cpp
+++ b/clang/lib/AST/Expr.cpp
@@ -4695,6 +4695,7 @@ unsigned AtomicExpr::getNumSubExprs(AtomicOp Op) {
   case AO__c11_atomic_fetch_and:
   case AO__c11_atomic_fetch_or:
   case AO__c11_atomic_fetch_xor:
+  case AO__c11_atomic_fetch_nand:
   case AO__c11_atomic_fetch_max:
   case AO__c11_atomic_fetch_min:
   case AO__atomic_fetch_add:

diff  --git a/clang/lib/CodeGen/CGAtomic.cpp b/clang/lib/CodeGen/CGAtomic.cpp
index b6722ad4e4f18..326ca8d50533e 100644
--- a/clang/lib/CodeGen/CGAtomic.cpp
+++ b/clang/lib/CodeGen/CGAtomic.cpp
@@ -664,6 +664,7 @@ static void EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr 
*E, Address Dest,
   case AtomicExpr::AO__atomic_nand_fetch:
 PostOp = llvm::Instruction::And; // the NOT is special cased below
 LLVM_FALLTHROUGH;
+  case AtomicExpr::AO__c11_atomic_fetch_nand:
   case AtomicExpr::AO__atomic_fetch_nand:
 Op = llvm::AtomicRMWInst::Nand;
 break;
@@ -906,6 +907,7 @@ RValue CodeGenFunction::EmitAtomicExpr(AtomicExpr *E) {
   case AtomicExpr::AO__c11_atomic_fetch_and:
   case AtomicExpr::AO__c11_atomic_fetch_or:
   case AtomicExpr::AO__c11_atomic_fetch_xor:
+  case AtomicExpr::AO__c11_atomic_fetch_nand:
   case AtomicExpr::AO__c11_atomic_fetch_max:
   case AtomicExpr::AO__c11_atomic_fetch_min:
   case AtomicExpr::AO__opencl_atomic_fetch_and:
@@ -972,6 +974,7 @@ RValue CodeGenFunction::EmitAtomicExpr(AtomicExpr *E) {
 case AtomicExpr::AO__c11_atomic_fetch_or:
 case AtomicExpr::AO__opencl_atomic_fetch_or:
 case AtomicExpr::AO__atomic_fetch_or:
+case AtomicExpr::AO__c11_atomic_fetch_nand:
 case AtomicExpr::AO__atomic_fetch_nand:
 case AtomicExpr::AO__c11_atomic_fetch_sub:
 case AtomicExpr::AO__opencl_atomic_fetch_sub:
@@ -1211,6 +1214,7 @@ RValue CodeGenFunction::EmitAtomicExpr(AtomicExpr *E) {
 case AtomicExpr::AO__atomic_nand_fetch:
   PostOp = llvm::Instruction::And; // the NOT is special cased below
   LLVM_FALLTHROUGH;
+case AtomicExpr::AO__c11_atomic_fetch_nand:
 case AtomicExpr::AO__atomic_fetch_nand:
   LibCallName = "__atomic_fetch_nand";
   AddDirectArgument(*this, Args, UseOptimizedLibcall, Val1.getPointer(),

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 3eaeae197648a..147f50aeed97f 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5287,6 +5287,7 @@ ExprResult Sema::BuildAtomicExpr(SourceRange CallRange, 
SourceRange ExprRange,
   case AtomicExpr::AO__c11_atomic_fetch_and:
   case AtomicExpr::AO__c11_atomic_fetch_or:
   case AtomicExpr::AO__c11_atomic_fetch_xor:
+  case AtomicExpr::AO__c11_atomic_fetch_nand:
   case AtomicExpr

[clang] 7236273 - [AIX] Set D111860's test unsupported on AIX

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2021-11-11T15:51:19Z
New Revision: 72362736c380699a79ba43a1411baeab76205c39

URL: 
https://github.com/llvm/llvm-project/commit/72362736c380699a79ba43a1411baeab76205c39
DIFF: 
https://github.com/llvm/llvm-project/commit/72362736c380699a79ba43a1411baeab76205c39.diff

LOG: [AIX] Set D111860's test unsupported on AIX

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D113654

Added: 


Modified: 
clang/test/Modules/merge-objc-protocol-visibility.m

Removed: 




diff  --git a/clang/test/Modules/merge-objc-protocol-visibility.m 
b/clang/test/Modules/merge-objc-protocol-visibility.m
index 04cf60b7e997..8521a60e7adc 100644
--- a/clang/test/Modules/merge-objc-protocol-visibility.m
+++ b/clang/test/Modules/merge-objc-protocol-visibility.m
@@ -1,3 +1,4 @@
+// UNSUPPORTED: -aix
 // RUN: rm -rf %t
 // RUN: split-file %s %t
 // RUN: %clang_cc1 -emit-llvm -o %t/test.bc -F%t/Frameworks %t/test.m 
-Werror=objc-method-access -DHIDDEN_FIRST=1 \



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[clang-tools-extra] 2e73129 - [include-cleaner] Fix link errors when -DBUILD_SHARED_LIBS=ON

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2022-10-19T07:26:08Z
New Revision: 2e73129483c4be78d32f4bbe3f9a3130d9fc83b7

URL: 
https://github.com/llvm/llvm-project/commit/2e73129483c4be78d32f4bbe3f9a3130d9fc83b7
DIFF: 
https://github.com/llvm/llvm-project/commit/2e73129483c4be78d32f4bbe3f9a3130d9fc83b7.diff

LOG: [include-cleaner] Fix link errors when -DBUILD_SHARED_LIBS=ON

Fixed ppc buildbot https://lab.llvm.org/buildbot/#/builders/121/builds/24273 
which is using `-DBUILD_SHARED_LIBS=ON`.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D136229

Added: 


Modified: 
clang-tools-extra/include-cleaner/lib/CMakeLists.txt
clang-tools-extra/include-cleaner/tool/CMakeLists.txt

Removed: 




diff  --git a/clang-tools-extra/include-cleaner/lib/CMakeLists.txt 
b/clang-tools-extra/include-cleaner/lib/CMakeLists.txt
index f65f50c243b86..b255abca7499d 100644
--- a/clang-tools-extra/include-cleaner/lib/CMakeLists.txt
+++ b/clang-tools-extra/include-cleaner/lib/CMakeLists.txt
@@ -6,7 +6,8 @@ add_clang_library(clangIncludeCleaner
   WalkAST.cpp
 
   LINK_LIBS
-  clangBasic
   clangAST
+  clangBasic
+  clangLex
   )
 

diff  --git a/clang-tools-extra/include-cleaner/tool/CMakeLists.txt 
b/clang-tools-extra/include-cleaner/tool/CMakeLists.txt
index bd407aec847d9..3fc8c44081cd2 100644
--- a/clang-tools-extra/include-cleaner/tool/CMakeLists.txt
+++ b/clang-tools-extra/include-cleaner/tool/CMakeLists.txt
@@ -4,6 +4,8 @@ include_directories("../lib") # FIXME: use public APIs instead.
 add_clang_tool(clang-include-cleaner IncludeCleaner.cpp)
 clang_target_link_libraries(clang-include-cleaner PRIVATE
   clangBasic
+  clangFrontend
+  clangSerialization
   clangTooling
   )
 target_link_libraries(clang-include-cleaner PRIVATE



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[clang] e231a58 - [clang][Module][AIX] Mark test unsupported since objc doesn't have xcoff support

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2022-10-13T12:03:55+08:00
New Revision: e231a580139a50aff639296c4b95a65e7d89cf1e

URL: 
https://github.com/llvm/llvm-project/commit/e231a580139a50aff639296c4b95a65e7d89cf1e
DIFF: 
https://github.com/llvm/llvm-project/commit/e231a580139a50aff639296c4b95a65e7d89cf1e.diff

LOG: [clang][Module][AIX] Mark test unsupported since objc doesn't have xcoff 
support

Fixed error
```
Command Output (stderr):
--
fatal error: error in backend: Objective-C support is unimplemented for object 
file format
```
Source code in `clang/lib/CodeGen/CGObjCMac.cpp:5080`

```
  case llvm::Triple::Wasm:
  case llvm::Triple::GOFF:
  case llvm::Triple::SPIRV:
  case llvm::Triple::XCOFF:
  case llvm::Triple::DXContainer:
llvm::report_fatal_error(
"Objective-C support is unimplemented for object file format");
  }

```

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D135848

Added: 


Modified: 
clang/test/Modules/module-file-home-is-cwd.m

Removed: 




diff  --git a/clang/test/Modules/module-file-home-is-cwd.m 
b/clang/test/Modules/module-file-home-is-cwd.m
index 57f8856406484..41f1988864610 100644
--- a/clang/test/Modules/module-file-home-is-cwd.m
+++ b/clang/test/Modules/module-file-home-is-cwd.m
@@ -1,3 +1,4 @@
+// UNSUPPORTED: -zos, -aix
 // RUN: cd %S
 // RUN: %clang_cc1 -x objective-c -fmodules -fno-implicit-modules \
 // RUN: -fmodule-file-home-is-cwd -fmodule-name=libA -emit-module \



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[clang] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

[Kai Luo via cfe-commits]

@@ -3412,13 +3416,23 @@ SDValue 
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset);
   }
 
-  // Only Local-Exec, Initial-Exec and General-Dynamic TLS models are currently
-  // supported models. If Local- or Initial-exec are not possible or specified,
-  // all GlobalTLSAddress nodes are lowered using the general-dynamic model.
-  // We need to generate two TOC entries, one for the variable offset, one for
-  // the region handle. The global address for the TOC entry of the region
-  // handle is created with the MO_TLSGDM_FLAG flag and the global address
-  // for the TOC entry of the variable offset is created with MO_TLSGD_FLAG.
+  if (Model == TLSModel::LocalDynamic) {
+// For local-dynamic on AIX, we need to generate two TOC entries, one for
+// the variable offset, the other for the module handle. The module handle
+// is encapsulated inside the TLSLD_AIX pseudo node, and will be expanded 
by
+// PPCTLSDynamicCall.
+SDValue VariableOffsetTGA =
+DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSLD_FLAG);
+SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);

bzEq wrote:

I don't think the module handle has external linkage, `_$TLSML` is renamed from 
the module handle defined in the module. If we need a `GlobalValue` to create a 
TOC entry for the module handle, `PreISelIntrinsicLowering` would be a 
candidate pass to realize it.

https://github.com/llvm/llvm-project/pull/66316
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[clang] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

[Kai Luo via cfe-commits]

https://github.com/bzEq deleted https://github.com/llvm/llvm-project/pull/66316
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[clang] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

[Kai Luo via cfe-commits]

bzEq wrote:

> Also, is it intentional that we combined the patch to enable local-dynamic in 
> clang within this patch?

Yes. For github's nature, we are unable to set parent PR in llvm-project repo, 
so clang part is included in this PR.

https://github.com/llvm/llvm-project/pull/66316
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[clang] be1516d - [PowerPC] Precommit test of `vec_promote` on `vector char`. NFC.

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2023-08-22T04:14:34Z
New Revision: be1516d46b1c9ad873d1b30b3494c3a3d0d8e02b

URL: 
https://github.com/llvm/llvm-project/commit/be1516d46b1c9ad873d1b30b3494c3a3d0d8e02b
DIFF: 
https://github.com/llvm/llvm-project/commit/be1516d46b1c9ad873d1b30b3494c3a3d0d8e02b.diff

LOG: [PowerPC] Precommit test of `vec_promote` on `vector char`. NFC.

Added: 


Modified: 
clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c

Removed: 




diff  --git a/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c 
b/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
index 790f886985a9f5..89c361454a421b 100644
--- a/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
@@ -2247,6 +2247,22 @@ res_vull = vec_promote(ull, 0);
 // CHECK: insertelement <2 x i64>
 // CHECK-LE: store <2 x i64> zeroinitializer
 // CHECK-LE: insertelement <2 x i64>
+
+res_vsc = vec_promote(asc[0], 8);
+// CHECK: store <16 x i8> zeroinitializer
+// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
+// CHECK-LE: store <16 x i8> zeroinitializer
+// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
+
+res_vuc = vec_promote(auc[0], 8);
+// CHECK: store <16 x i8> zeroinitializer
+// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
+// CHECK-LE: store <16 x i8> zeroinitializer
+// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 }
 
 // The return type of the call expression may be 
diff erent from the return type of the shufflevector.



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[clang] 6b6ea93 - [PowerPC][altivec] Correct modulo number of vec_promote on vector char

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2023-08-23T01:58:36Z
New Revision: 6b6ea93125bd834cae22149e18b742d498dc79a3

URL: 
https://github.com/llvm/llvm-project/commit/6b6ea93125bd834cae22149e18b742d498dc79a3
DIFF: 
https://github.com/llvm/llvm-project/commit/6b6ea93125bd834cae22149e18b742d498dc79a3.diff

LOG: [PowerPC][altivec] Correct modulo number of vec_promote on vector char

According to 
https://www.ibm.com/docs/en/xl-c-and-cpp-linux/16.1.1?topic=functions-vec-promote,
 the index should be input modulo the number of elements in the vector. When 
the type is `vector char`, the number of elements should be 16.

Reviewed By: qiucf

Differential Revision: https://reviews.llvm.org/D158484

Added: 


Modified: 
clang/lib/Headers/altivec.h
clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c

Removed: 




diff  --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index c036f5ebba580e..44b5a24de89f1a 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -14648,14 +14648,14 @@ static __inline__ void __ATTRS_o_ai vec_stvrxl(vector 
float __a, int __b,
 static __inline__ vector signed char __ATTRS_o_ai vec_promote(signed char __a,
   int __b) {
   vector signed char __res = (vector signed char)(0);
-  __res[__b & 0x7] = __a;
+  __res[__b & 0xf] = __a;
   return __res;
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_promote(unsigned char __a, int __b) {
   vector unsigned char __res = (vector unsigned char)(0);
-  __res[__b & 0x7] = __a;
+  __res[__b & 0xf] = __a;
   return __res;
 }
 

diff  --git a/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c 
b/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
index 89c361454a421b..cca2a8b2f55bd4 100644
--- a/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
@@ -2250,18 +2250,18 @@ res_vull = vec_promote(ull, 0);
 
 res_vsc = vec_promote(asc[0], 8);
 // CHECK: store <16 x i8> zeroinitializer
-// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 // CHECK-LE: store <16 x i8> zeroinitializer
-// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 
 res_vuc = vec_promote(auc[0], 8);
 // CHECK: store <16 x i8> zeroinitializer
-// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 // CHECK-LE: store <16 x i8> zeroinitializer
-// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 7
+// CHECK-LE: [[IDX:%.*]] = and i32 {{.*}}, 15
 // CHECK-LE: insertelement <16 x i8> {{.*}}, i8 {{.*}}, i32 [[IDX]]
 }
 



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[clang] ca8d253 - [clang-repl][Orc] Export executable symbols in ClangReplInterpreterExceptionTests

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2023-09-13T05:24:20Z
New Revision: ca8d2533c79ccfbcb2de4090f0d48914a60b0a3d

URL: 
https://github.com/llvm/llvm-project/commit/ca8d2533c79ccfbcb2de4090f0d48914a60b0a3d
DIFF: 
https://github.com/llvm/llvm-project/commit/ca8d2533c79ccfbcb2de4090f0d48914a60b0a3d.diff

LOG: [clang-repl][Orc] Export executable symbols in 
ClangReplInterpreterExceptionTests

In Orc runtime, we use `dlopen(nullptr, ...)` to open current executable and 
use `dlsym` to find addresses of symbols, this requires `-rdynamic` flag.

As `llvm/CMakeLists.txt` suggests

```
# Make sure we don't get -rdynamic in every binary. For those that need it,
# use export_executable_symbols(target).
```
This patch exports symbols in `ClangReplInterpreterExceptionTests`. This also 
fixes `ClangReplInterpreterExceptionTests` is skipped on ppc64 when jitlink is 
used.

Reviewed By: v.g.vassilev

Differential Revision: https://reviews.llvm.org/D159167

Added: 


Modified: 
clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt

Removed: 




diff  --git a/clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt 
b/clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
index 9f6ed2eb4fe7da0..5a6597d1b6728f9 100644
--- a/clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
+++ b/clang/unittests/Interpreter/ExceptionTests/CMakeLists.txt
@@ -22,3 +22,5 @@ target_link_libraries(ClangReplInterpreterExceptionTests 
PUBLIC
   clangFrontend
   )
 add_dependencies(ClangReplInterpreterExceptionTests clang-resource-headers)
+
+export_executable_symbols(ClangReplInterpreterExceptionTests)



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[clang] 1ceaec3 - [PowerPC][altivec] Optimize codegen of vec_promote

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2023-08-24T02:10:13Z
New Revision: 1ceaec3e81044d8a671b28d1f556045cf7fe6ef0

URL: 
https://github.com/llvm/llvm-project/commit/1ceaec3e81044d8a671b28d1f556045cf7fe6ef0
DIFF: 
https://github.com/llvm/llvm-project/commit/1ceaec3e81044d8a671b28d1f556045cf7fe6ef0.diff

LOG: [PowerPC][altivec] Optimize codegen of vec_promote

According to 
https://www.ibm.com/docs/en/xl-c-and-cpp-linux/16.1.1?topic=functions-vec-promote,
 elements not specified by the input index argument are undefined. So that we 
don't need to set these elements to be zeros.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D158487

Added: 
llvm/test/CodeGen/PowerPC/vec-promote.ll

Modified: 
clang/lib/Headers/altivec.h
clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c

Removed: 




diff  --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 44b5a24de89f1a..4971631c50f412 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -14647,67 +14647,86 @@ static __inline__ void __ATTRS_o_ai vec_stvrxl(vector 
float __a, int __b,
 
 static __inline__ vector signed char __ATTRS_o_ai vec_promote(signed char __a,
   int __b) {
-  vector signed char __res = (vector signed char)(0);
+  const vector signed char __zero = (vector signed char)0;
+  vector signed char __res =
+  __builtin_shufflevector(__zero, __zero, -1, -1, -1, -1, -1, -1, -1, -1,
+  -1, -1, -1, -1, -1, -1, -1, -1);
   __res[__b & 0xf] = __a;
   return __res;
 }
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_promote(unsigned char __a, int __b) {
-  vector unsigned char __res = (vector unsigned char)(0);
+  const vector unsigned char __zero = (vector unsigned char)(0);
+  vector unsigned char __res =
+  __builtin_shufflevector(__zero, __zero, -1, -1, -1, -1, -1, -1, -1, -1,
+  -1, -1, -1, -1, -1, -1, -1, -1);
   __res[__b & 0xf] = __a;
   return __res;
 }
 
 static __inline__ vector short __ATTRS_o_ai vec_promote(short __a, int __b) {
-  vector short __res = (vector short)(0);
+  const vector short __zero = (vector short)(0);
+  vector short __res =
+  __builtin_shufflevector(__zero, __zero, -1, -1, -1, -1, -1, -1, -1, -1);
   __res[__b & 0x7] = __a;
   return __res;
 }
 
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_promote(unsigned short __a, int __b) {
-  vector unsigned short __res = (vector unsigned short)(0);
+  const vector unsigned short __zero = (vector unsigned short)(0);
+  vector unsigned short __res =
+  __builtin_shufflevector(__zero, __zero, -1, -1, -1, -1, -1, -1, -1, -1);
   __res[__b & 0x7] = __a;
   return __res;
 }
 
 static __inline__ vector int __ATTRS_o_ai vec_promote(int __a, int __b) {
-  vector int __res = (vector int)(0);
+  const vector int __zero = (vector int)(0);
+  vector int __res = __builtin_shufflevector(__zero, __zero, -1, -1, -1, -1);
   __res[__b & 0x3] = __a;
   return __res;
 }
 
 static __inline__ vector unsigned int __ATTRS_o_ai vec_promote(unsigned int 
__a,
int __b) {
-  vector unsigned int __res = (vector unsigned int)(0);
+  const vector unsigned int __zero = (vector unsigned int)(0);
+  vector unsigned int __res =
+  __builtin_shufflevector(__zero, __zero, -1, -1, -1, -1);
   __res[__b & 0x3] = __a;
   return __res;
 }
 
 static __inline__ vector float __ATTRS_o_ai vec_promote(float __a, int __b) {
-  vector float __res = (vector float)(0);
+  const vector float __zero = (vector float)(0);
+  vector float __res = __builtin_shufflevector(__zero, __zero, -1, -1, -1, -1);
   __res[__b & 0x3] = __a;
   return __res;
 }
 
 #ifdef __VSX__
 static __inline__ vector double __ATTRS_o_ai vec_promote(double __a, int __b) {
-  vector double __res = (vector double)(0);
+  const vector double __zero = (vector double)(0);
+  vector double __res = __builtin_shufflevector(__zero, __zero, -1, -1);
   __res[__b & 0x1] = __a;
   return __res;
 }
 
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_promote(signed long long __a, int __b) {
-  vector signed long long __res = (vector signed long long)(0);
+  const vector signed long long __zero = (vector signed long long)(0);
+  vector signed long long __res =
+  __builtin_shufflevector(__zero, __zero, -1, -1);
   __res[__b & 0x1] = __a;
   return __res;
 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_promote(unsigned long long __a, int __b) {
-  vector unsigned long long __res = (vector unsigned long long)(0);
+  const vector unsigned long long __zero = (vector unsigned long long)(0);
+  vector unsigned long long __res =
+  __builtin_shufflevector(__zero, __zero, -1, -1);
   __res[__b & 0x1] = __a;
   return __res;
 }

diff  --git a/clang/test/CodeGen/PowerPC/builtins-ppc-vs

[clang] 09ccc55 - Fix [-Werror,-Wsign-compare] error. NFC.

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2023-08-24T07:56:43Z
New Revision: 09ccc5563ebe70be2b5a5421df43cd5720ba1f5b

URL: 
https://github.com/llvm/llvm-project/commit/09ccc5563ebe70be2b5a5421df43cd5720ba1f5b
DIFF: 
https://github.com/llvm/llvm-project/commit/09ccc5563ebe70be2b5a5421df43cd5720ba1f5b.diff

LOG: Fix [-Werror,-Wsign-compare] error. NFC.

Added: 


Modified: 
clang/unittests/Analysis/FlowSensitive/TransferTest.cpp

Removed: 




diff  --git a/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp 
b/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
index ef28f2f233b844..8100db2aec4090 100644
--- a/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
+++ b/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
@@ -5621,7 +5621,7 @@ TEST(TransferTest, 
MemberOperatorCallModelsPointerForCallee) {
 auto Matches = match(
 traverse(TK_AsIs, cxxOperatorCallExpr().bind("call")), ASTCtx);
 
-ASSERT_EQ(Matches.size(), 2);
+ASSERT_EQ(Matches.size(), 2UL);
 
 auto *Call1 = Matches[0].getNodeAs("call");
 auto *Call2 = Matches[1].getNodeAs("call");



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[clang] 2db83b1 - [CMake] Fix -DBUILD_SHARED_LIBS=on builds after D137534

[Kai Luo via cfe-commits]

Author: Kai Luo
Date: 2023-02-10T04:58:20Z
New Revision: 2db83b1b311bae3d14067970edf15c6a1d37

URL: 
https://github.com/llvm/llvm-project/commit/2db83b1b311bae3d14067970edf15c6a1d37
DIFF: 
https://github.com/llvm/llvm-project/commit/2db83b1b311bae3d14067970edf15c6a1d37.diff

LOG: [CMake] Fix -DBUILD_SHARED_LIBS=on builds after D137534

Added: 


Modified: 
clang/tools/clang-scan-deps/CMakeLists.txt

Removed: 




diff  --git a/clang/tools/clang-scan-deps/CMakeLists.txt 
b/clang/tools/clang-scan-deps/CMakeLists.txt
index 6aa914f3b256..4db565314c06 100644
--- a/clang/tools/clang-scan-deps/CMakeLists.txt
+++ b/clang/tools/clang-scan-deps/CMakeLists.txt
@@ -1,6 +1,8 @@
 set(LLVM_LINK_COMPONENTS
   Core
+  Option
   Support
+  TargetParser
   )
 
 add_clang_tool(clang-scan-deps



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[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level (PR #84132)

[Kai Luo via cfe-commits]

@@ -80,6 +80,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   bool IsISA3_0 = false;
   bool IsISA3_1 = false;
   bool HasQuadwordAtomics = false;
+  bool HasAIXShLibTLSModelHeuristic = false;

bzEq wrote:

The variable defined here is only visible to clang and clang doesn't use this 
flag further. What backend sees is the feature string and set corresponding 
variables in backend accordingly.

https://github.com/llvm/llvm-project/pull/84132
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[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level (PR #84132)

[Kai Luo via cfe-commits]

@@ -80,6 +80,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   bool IsISA3_0 = false;
   bool IsISA3_1 = false;
   bool HasQuadwordAtomics = false;
+  bool HasAIXShLibTLSModelHeuristic = false;

bzEq wrote:

Code in `PPCTargetLowering::LowerGlobalTLSAddressAIX` like
```
Subtarget.hasAIXSmallLocalExecTLS()
```
which is generated in `PPCGenSubtargetInfo.inc`, whose value is initialized by 
feature string `aix-small-local-exec-tls` in LLVM IR rather than the variable 
defined in clang.

https://github.com/llvm/llvm-project/pull/84132
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[clang] [Driver] Pass `--no-cuda-version-check` to test (PR #117415)

[Kai Luo via cfe-commits]

https://github.com/bzEq edited https://github.com/llvm/llvm-project/pull/117415
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[clang] [Driver] Pass `--no-cuda-version-check` to test (PR #117415)

[Kai Luo via cfe-commits]

https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/117415

>From f4e8c55a4dbe9092bcf5f61cca67359a779861bc Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Sat, 23 Nov 2024 13:14:27 +0800
Subject: [PATCH 1/2] [Driver] Pass `--no-cuda-version-check` to test

My local build, on Debian GNU/Linux 12 (bookworm), complains
```
clang: error: GPU arch sm_20 is supported by CUDA versions between 7.0 and 8.0 
(inclusive), but installation at /usr/lib/cuda is 11.8; use '--cuda-path' to 
specify a different CUDA install, pass a different GPU arch with 
'--cuda-gpu-arch', or pass '--no-cuda-version-check'
```

Fix it by passing `--no-cuda-version-check`.
---
 clang/test/Driver/cuda-no-threadsafe-statics.cu | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/test/Driver/cuda-no-threadsafe-statics.cu 
b/clang/test/Driver/cuda-no-threadsafe-statics.cu
index eb15312f8f7d14..494f0e7a89ff32 100644
--- a/clang/test/Driver/cuda-no-threadsafe-statics.cu
+++ b/clang/test/Driver/cuda-no-threadsafe-statics.cu
@@ -2,7 +2,7 @@
 // compilation only.
 //
 // RUN: %clang -### -x cuda --target=x86_64-linux-gnu -c --cuda-gpu-arch=sm_20 
%s \
-// RUN:-nocudainc -nocudalib 2>&1 | FileCheck %s
+// RUN:-nocudainc -nocudalib --no-cuda-version-check 2>&1 | 
FileCheck %s
 
 // RUN: %clang -### -x hip --target=x86_64-linux-gnu -c 
--cuda-gpu-arch=gfx1010 %s \
 // RUN:-nocudainc -nocudalib 2>&1 | FileCheck %s

>From 253a66970087da8d6c66cad3a64959273039aad2 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Tue, 26 Nov 2024 07:46:42 +0800
Subject: [PATCH 2/2] Address comment

---
 clang/test/Driver/cuda-no-threadsafe-statics.cu | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/clang/test/Driver/cuda-no-threadsafe-statics.cu 
b/clang/test/Driver/cuda-no-threadsafe-statics.cu
index 494f0e7a89ff32..8730605f18828e 100644
--- a/clang/test/Driver/cuda-no-threadsafe-statics.cu
+++ b/clang/test/Driver/cuda-no-threadsafe-statics.cu
@@ -2,7 +2,8 @@
 // compilation only.
 //
 // RUN: %clang -### -x cuda --target=x86_64-linux-gnu -c --cuda-gpu-arch=sm_20 
%s \
-// RUN:-nocudainc -nocudalib --no-cuda-version-check 2>&1 | 
FileCheck %s
+// RUN:-nocudainc -nocudalib 
--cuda-path=%S/Inputs/CUDA_80/usr/local/cuda \
+// RUN:2>&1 | FileCheck %s
 
 // RUN: %clang -### -x hip --target=x86_64-linux-gnu -c 
--cuda-gpu-arch=gfx1010 %s \
 // RUN:-nocudainc -nocudalib 2>&1 | FileCheck %s

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[clang] [Driver] Pass `--no-cuda-version-check` to test (PR #117415)

[Kai Luo via cfe-commits]

bzEq wrote:

Address comment.

https://github.com/llvm/llvm-project/pull/117415
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[clang] [Driver] Pass `--cuda-path` to test (PR #117415)

[Kai Luo via cfe-commits]

https://github.com/bzEq edited https://github.com/llvm/llvm-project/pull/117415
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[clang] [Driver] Pass `--no-cuda-version-check` to test (PR #117415)

[Kai Luo via cfe-commits]

https://github.com/bzEq edited https://github.com/llvm/llvm-project/pull/117415
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[clang] [Driver] Pass `--cuda-path` to test (PR #117415)

[Kai Luo via cfe-commits]

https://github.com/bzEq closed https://github.com/llvm/llvm-project/pull/117415
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[clang] [Driver] Pass `--no-cuda-version-check` to test (PR #117415)

[Kai Luo via cfe-commits]

https://github.com/bzEq created https://github.com/llvm/llvm-project/pull/117415

My local build, on Debian GNU/Linux 12 (bookworm), complains
```
clang: error: GPU arch sm_20 is supported by CUDA versions between 7.0 and 8.0 
(inclusive), but installation at /usr/lib/cuda is 11.8; use '--cuda-path' to 
specify a different CUDA install, pass a different GPU arch with 
'--cuda-gpu-arch', or pass '--no-cuda-version-check'
```

Fix it by passing `--no-cuda-version-check`.

>From eb0bc0ba240f03c84e8bd6e829badd3df4ca2d20 Mon Sep 17 00:00:00 2001
From: Kai Luo 
Date: Sat, 23 Nov 2024 13:14:27 +0800
Subject: [PATCH] [Driver] Pass `--no-cuda-version-check` to test

My local build, on Debian GNU/Linux 12 (bookworm), complains
```
clang: error: GPU arch sm_20 is supported by CUDA versions between 7.0 and 8.0 
(inclusive), but installation at /usr/lib/cuda is 11.8; use '--cuda-path' to 
specify a different CUDA install, pass a different GPU arch with 
'--cuda-gpu-arch', or pass '--no-cuda-version-check'
```

Fix it by passing `--no-cuda-version-check`.
---
 clang/test/Driver/cuda-no-threadsafe-statics.cu | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/test/Driver/cuda-no-threadsafe-statics.cu 
b/clang/test/Driver/cuda-no-threadsafe-statics.cu
index eb15312f8f7d14..494f0e7a89ff32 100644
--- a/clang/test/Driver/cuda-no-threadsafe-statics.cu
+++ b/clang/test/Driver/cuda-no-threadsafe-statics.cu
@@ -2,7 +2,7 @@
 // compilation only.
 //
 // RUN: %clang -### -x cuda --target=x86_64-linux-gnu -c --cuda-gpu-arch=sm_20 
%s \
-// RUN:-nocudainc -nocudalib 2>&1 | FileCheck %s
+// RUN:-nocudainc -nocudalib --no-cuda-version-check 2>&1 | 
FileCheck %s
 
 // RUN: %clang -### -x hip --target=x86_64-linux-gnu -c 
--cuda-gpu-arch=gfx1010 %s \
 // RUN:-nocudainc -nocudalib 2>&1 | FileCheck %s

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[clang] [PowerPC][RFC] Make power9-vector indicate isa-3.0 and power9-altivec (PR #86905)

[Kai Luo via cfe-commits]

https://github.com/bzEq closed https://github.com/llvm/llvm-project/pull/86905
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[clang] [PowerPC][RFC] Make power9-vector indicate isa-3.0 and power9-altivec (PR #86905)

[Kai Luo via cfe-commits]

bzEq wrote:

I am not going to pursue this PR, close it.

https://github.com/llvm/llvm-project/pull/86905
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