[clang] [Clang][SYCL] Add AOT compilation support for Intel GPUs in clang-sycl-linker (PR #133194)

2025-04-05 Thread Justin Cai via cfe-commits 

https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/133194

>From 8f22fbe1f6272beec61e62bfae72832d75b4f25b Mon Sep 17 00:00:00 2001
From: "Cai, Justin" 
Date: Fri, 14 Feb 2025 21:16:27 +
Subject: [PATCH 1/3] [SYCL] Add support AOT compilation support for Intel GPUs
 in clang-sycl-linker

---
 clang/include/clang/Basic/SYCL.h  | 131 ++
 clang/lib/Basic/CMakeLists.txt|   1 +
 clang/lib/Basic/SYCL.cpp  | 226 ++
 clang/test/Driver/clang-sycl-linker-test.cpp  |  36 +++
 .../clang-sycl-linker/ClangSYCLLinker.cpp | 112 -
 clang/tools/clang-sycl-linker/SYCLLinkOpts.td |   8 +
 6 files changed, 506 insertions(+), 8 deletions(-)
 create mode 100644 clang/include/clang/Basic/SYCL.h
 create mode 100644 clang/lib/Basic/SYCL.cpp

diff --git a/clang/include/clang/Basic/SYCL.h b/clang/include/clang/Basic/SYCL.h
new file mode 100644
index 0..c7cad37639b91
--- /dev/null
+++ b/clang/include/clang/Basic/SYCL.h
@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CLANG_BASIC_SYCL_H
+#define LLVM_CLANG_BASIC_SYCL_H
+
+#include "clang/Basic/Cuda.h"
+
+namespace llvm {
+class StringRef;
+template  class SmallString;
+} // namespace llvm
+
+namespace clang {
+// List of architectures (Intel CPUs and Intel GPUs)
+// that support SYCL offloading.
+enum class SYCLSupportedIntelArchs {
+  // Intel CPUs
+  UNKNOWN,
+  SKYLAKEAVX512,
+  COREAVX2,
+  COREI7AVX,
+  COREI7,
+  WESTMERE,
+  SANDYBRIDGE,
+  IVYBRIDGE,
+  BROADWELL,
+  COFFEELAKE,
+  ALDERLAKE,
+  SKYLAKE,
+  SKX,
+  CASCADELAKE,
+  ICELAKECLIENT,
+  ICELAKESERVER,
+  SAPPHIRERAPIDS,
+  GRANITERAPIDS,
+  // Intel GPUs
+  BDW,
+  SKL,
+  KBL,
+  CFL,
+  APL,
+  BXT,
+  GLK,
+  WHL,
+  AML,
+  CML,
+  ICLLP,
+  ICL,
+  EHL,
+  JSL,
+  TGLLP,
+  TGL,
+  RKL,
+  ADL_S,
+  RPL_S,
+  ADL_P,
+  ADL_N,
+  DG1,
+  ACM_G10,
+  DG2_G10,
+  ACM_G11,
+  DG2_G11,
+  ACM_G12,
+  DG2_G12,
+  PVC,
+  PVC_VG,
+  MTL_U,
+  MTL_S,
+  ARL_U,
+  ARL_S,
+  MTL_H,
+  ARL_H,
+  BMG_G21,
+  LNL_M,
+};
+
+// Check if the given Arch value is a Generic AMD GPU.
+// Currently GFX*_GENERIC AMD GPUs do not support SYCL offloading.
+// This list is used to filter out GFX*_GENERIC AMD GPUs in
+// `IsSYCLSupportedAMDGPUArch`.
+static inline bool IsAMDGenericGPUArch(OffloadArch Arch) {
+  return Arch == OffloadArch::GFX9_GENERIC ||
+ Arch == OffloadArch::GFX10_1_GENERIC ||
+ Arch == OffloadArch::GFX10_3_GENERIC ||
+ Arch == OffloadArch::GFX11_GENERIC ||
+ Arch == OffloadArch::GFX12_GENERIC;
+}
+
+// Check if the given Arch value is a valid SYCL supported AMD GPU.
+static inline bool IsSYCLSupportedAMDGPUArch(OffloadArch Arch) {
+  return Arch >= OffloadArch::GFX700 && Arch < OffloadArch::AMDGCNSPIRV &&
+ !IsAMDGenericGPUArch(Arch);
+}
+
+// Check if the given Arch value is a valid SYCL supported NVidia GPU.
+static inline bool IsSYCLSupportedNVidiaGPUArch(OffloadArch Arch) {
+  return Arch >= OffloadArch::SM_50 && Arch <= OffloadArch::SM_90a;
+}
+
+// Check if the given Arch value is a valid SYCL supported Intel CPU.
+static inline bool IsSYCLSupportedIntelCPUArch(SYCLSupportedIntelArchs Arch) {
+  return Arch >= SYCLSupportedIntelArchs::SKYLAKEAVX512 &&
+ Arch <= SYCLSupportedIntelArchs::GRANITERAPIDS;
+}
+
+// Check if the given Arch value is a valid SYCL supported Intel GPU.
+static inline bool IsSYCLSupportedIntelGPUArch(SYCLSupportedIntelArchs Arch) {
+  return Arch >= SYCLSupportedIntelArchs::BDW &&
+ Arch <= SYCLSupportedIntelArchs::LNL_M;
+}
+
+// Check if the user provided value for --offload-arch is a valid
+// SYCL supported Intel AOT target.
+SYCLSupportedIntelArchs
+StringToOffloadArchSYCL(llvm::StringRef ArchNameAsString);
+
+// This is a mapping between the user provided --offload-arch value for Intel
+// GPU targets and the spir64_gen device name accepted by OCLOC (the Intel GPU
+// AOT compiler).
+llvm::StringRef mapIntelGPUArchName(llvm::StringRef ArchName);
+llvm::SmallString<64> getGenDeviceMacro(llvm::StringRef DeviceName);
+
+} // namespace clang
+
+#endif // LLVM_CLANG_BASIC_SYCL_H
diff --git a/clang/lib/Basic/CMakeLists.txt b/clang/lib/Basic/CMakeLists.txt
index 331dfbb3f4b67..be6d915e01b0a 100644
--- a/clang/lib/Basic/CMakeLists.txt
+++ b/clang/lib/Basic/CMakeLists.txt
@@ -90,6 +90,7 @@ add_clang_library(clangBasic
   SourceMgrAdapter.cpp
   Stack.cpp
   StackExhaustionHandler.cpp
+  SYCL.cpp
   TargetID.cpp
   TargetInfo.cpp
   Targets.cpp
diff --git a/clang/lib/Basic/SYCL.cpp b/clang/lib/Basic/SYCL.cpp
new file mode 100644
index 0..9ac5470cdbe5a

[clang] [Clang][SYCL] Add support AOT compilation support for Intel GPUs in clang-sycl-linker (PR #133194)

2025-03-26 Thread Justin Cai via cfe-commits 

https://github.com/jzc created https://github.com/llvm/llvm-project/pull/133194

This PR adds support for AOT compilation for Intel CPUs and GPUs in 
clang-sycl-linker. When no `-arch` is passed to `clang-sycl-linker`, the output 
of the tool will be the resulting linked SPIR-V bytecode. If the `-arch` is 
passed to `clang-sycl-linker` and the value is a supported Intel CPU or GPU, 
then SPIR-V bytecode is then further passed to the respective tool 
(`opencl-aot` or `ocloc`) for AOT compilation.

>From 8f22fbe1f6272beec61e62bfae72832d75b4f25b Mon Sep 17 00:00:00 2001
From: "Cai, Justin" 
Date: Fri, 14 Feb 2025 21:16:27 +
Subject: [PATCH] [SYCL] Add support AOT compilation support for Intel GPUs in
 clang-sycl-linker

---
 clang/include/clang/Basic/SYCL.h  | 131 ++
 clang/lib/Basic/CMakeLists.txt|   1 +
 clang/lib/Basic/SYCL.cpp  | 226 ++
 clang/test/Driver/clang-sycl-linker-test.cpp  |  36 +++
 .../clang-sycl-linker/ClangSYCLLinker.cpp | 112 -
 clang/tools/clang-sycl-linker/SYCLLinkOpts.td |   8 +
 6 files changed, 506 insertions(+), 8 deletions(-)
 create mode 100644 clang/include/clang/Basic/SYCL.h
 create mode 100644 clang/lib/Basic/SYCL.cpp

diff --git a/clang/include/clang/Basic/SYCL.h b/clang/include/clang/Basic/SYCL.h
new file mode 100644
index 0..c7cad37639b91
--- /dev/null
+++ b/clang/include/clang/Basic/SYCL.h
@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CLANG_BASIC_SYCL_H
+#define LLVM_CLANG_BASIC_SYCL_H
+
+#include "clang/Basic/Cuda.h"
+
+namespace llvm {
+class StringRef;
+template  class SmallString;
+} // namespace llvm
+
+namespace clang {
+// List of architectures (Intel CPUs and Intel GPUs)
+// that support SYCL offloading.
+enum class SYCLSupportedIntelArchs {
+  // Intel CPUs
+  UNKNOWN,
+  SKYLAKEAVX512,
+  COREAVX2,
+  COREI7AVX,
+  COREI7,
+  WESTMERE,
+  SANDYBRIDGE,
+  IVYBRIDGE,
+  BROADWELL,
+  COFFEELAKE,
+  ALDERLAKE,
+  SKYLAKE,
+  SKX,
+  CASCADELAKE,
+  ICELAKECLIENT,
+  ICELAKESERVER,
+  SAPPHIRERAPIDS,
+  GRANITERAPIDS,
+  // Intel GPUs
+  BDW,
+  SKL,
+  KBL,
+  CFL,
+  APL,
+  BXT,
+  GLK,
+  WHL,
+  AML,
+  CML,
+  ICLLP,
+  ICL,
+  EHL,
+  JSL,
+  TGLLP,
+  TGL,
+  RKL,
+  ADL_S,
+  RPL_S,
+  ADL_P,
+  ADL_N,
+  DG1,
+  ACM_G10,
+  DG2_G10,
+  ACM_G11,
+  DG2_G11,
+  ACM_G12,
+  DG2_G12,
+  PVC,
+  PVC_VG,
+  MTL_U,
+  MTL_S,
+  ARL_U,
+  ARL_S,
+  MTL_H,
+  ARL_H,
+  BMG_G21,
+  LNL_M,
+};
+
+// Check if the given Arch value is a Generic AMD GPU.
+// Currently GFX*_GENERIC AMD GPUs do not support SYCL offloading.
+// This list is used to filter out GFX*_GENERIC AMD GPUs in
+// `IsSYCLSupportedAMDGPUArch`.
+static inline bool IsAMDGenericGPUArch(OffloadArch Arch) {
+  return Arch == OffloadArch::GFX9_GENERIC ||
+ Arch == OffloadArch::GFX10_1_GENERIC ||
+ Arch == OffloadArch::GFX10_3_GENERIC ||
+ Arch == OffloadArch::GFX11_GENERIC ||
+ Arch == OffloadArch::GFX12_GENERIC;
+}
+
+// Check if the given Arch value is a valid SYCL supported AMD GPU.
+static inline bool IsSYCLSupportedAMDGPUArch(OffloadArch Arch) {
+  return Arch >= OffloadArch::GFX700 && Arch < OffloadArch::AMDGCNSPIRV &&
+ !IsAMDGenericGPUArch(Arch);
+}
+
+// Check if the given Arch value is a valid SYCL supported NVidia GPU.
+static inline bool IsSYCLSupportedNVidiaGPUArch(OffloadArch Arch) {
+  return Arch >= OffloadArch::SM_50 && Arch <= OffloadArch::SM_90a;
+}
+
+// Check if the given Arch value is a valid SYCL supported Intel CPU.
+static inline bool IsSYCLSupportedIntelCPUArch(SYCLSupportedIntelArchs Arch) {
+  return Arch >= SYCLSupportedIntelArchs::SKYLAKEAVX512 &&
+ Arch <= SYCLSupportedIntelArchs::GRANITERAPIDS;
+}
+
+// Check if the given Arch value is a valid SYCL supported Intel GPU.
+static inline bool IsSYCLSupportedIntelGPUArch(SYCLSupportedIntelArchs Arch) {
+  return Arch >= SYCLSupportedIntelArchs::BDW &&
+ Arch <= SYCLSupportedIntelArchs::LNL_M;
+}
+
+// Check if the user provided value for --offload-arch is a valid
+// SYCL supported Intel AOT target.
+SYCLSupportedIntelArchs
+StringToOffloadArchSYCL(llvm::StringRef ArchNameAsString);
+
+// This is a mapping between the user provided --offload-arch value for Intel
+// GPU targets and the spir64_gen device name accepted by OCLOC (the Intel GPU
+// AOT compiler).
+llvm::StringRef mapIntelGPUArchName(llvm::StringRef ArchName);
+llvm::SmallString<64> getGenDeviceMacro(llvm::StringRef DeviceName);
+
+} // namespace clang
+
+#endif // LLVM_CLANG_BASIC_SYCL_H
diff --git a/clang/lib/Basic/CMakeLists.txt b/clang/lib/Basic/CMakeLists

[clang] [Clang][SYCL] Add AOT compilation support for Intel GPUs in clang-sycl-linker (PR #133194)

2025-03-31 Thread Justin Cai via cfe-commits 

https://github.com/jzc edited https://github.com/llvm/llvm-project/pull/133194
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[clang] [llvm] [SYCL] Add SYCL property set registry class (PR #136697)

2025-04-22 Thread Justin Cai via cfe-commits 

https://github.com/jzc created https://github.com/llvm/llvm-project/pull/136697

None

>From f5388e43a3ace6429ad911aebe2a3599858abf8f Mon Sep 17 00:00:00 2001
From: "Cai, Justin" 
Date: Tue, 22 Apr 2025 06:34:45 -0700
Subject: [PATCH] [SYCL] Add SYCL property set registry class

---
 .../clang-sycl-linker/ClangSYCLLinker.cpp |  14 ++-
 .../llvm/Frontend/Offloading/Utility.h| 102 ++
 llvm/lib/Frontend/Offloading/Utility.cpp  | 102 ++
 llvm/unittests/Frontend/CMakeLists.txt|   1 +
 .../Frontend/PropertySetRegistryTest.cpp  |  39 +++
 5 files changed, 253 insertions(+), 5 deletions(-)
 create mode 100644 llvm/unittests/Frontend/PropertySetRegistryTest.cpp

diff --git a/clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp 
b/clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
index 61ec4dbc1489d..e7f7654d377a1 100644
--- a/clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
+++ b/clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
@@ -20,6 +20,7 @@
 #include "llvm/BinaryFormat/Magic.h"
 #include "llvm/Bitcode/BitcodeWriter.h"
 #include "llvm/CodeGen/CommandFlags.h"
+#include "llvm/Frontend/Offloading/Utility.h"
 #include "llvm/IR/DiagnosticPrinter.h"
 #include "llvm/IR/LLVMContext.h"
 #include "llvm/IRReader/IRReader.h"
@@ -54,6 +55,7 @@
 using namespace llvm;
 using namespace llvm::opt;
 using namespace llvm::object;
+using namespace llvm::offloading::sycl;
 
 /// Save intermediary results.
 static bool SaveTemps = false;
@@ -355,18 +357,18 @@ Error runSYCLLink(ArrayRef Files, const 
ArgList &Args) {
   // result in multiple bitcode codes.
   // The following lines are placeholders to represent multiple files and will
   // be refactored once SYCL post link support is available.
-  SmallVector SplitModules;
-  SplitModules.emplace_back(*LinkedFile);
+  SmallVector> SplitModules;
+  SplitModules.emplace_back(*LinkedFile, PropertySetRegistry{});
 
   // SPIR-V code generation step.
   for (size_t I = 0, E = SplitModules.size(); I != E; ++I) {
 auto Stem = OutputFile.rsplit('.').first;
 std::string SPVFile(Stem);
 SPVFile.append("_" + utostr(I) + ".spv");
-auto Err = runSPIRVCodeGen(SplitModules[I], Args, SPVFile, C);
+auto Err = runSPIRVCodeGen(SplitModules[I].first, Args, SPVFile, C);
 if (Err)
   return Err;
-SplitModules[I] = SPVFile;
+SplitModules[I].first = SPVFile;
   }
 
   // Write the final output into file.
@@ -376,7 +378,7 @@ Error runSYCLLink(ArrayRef Files, const 
ArgList &Args) {
   llvm::raw_fd_ostream FS(FD, /*shouldClose=*/true);
 
   for (size_t I = 0, E = SplitModules.size(); I != E; ++I) {
-auto File = SplitModules[I];
+const auto &[File, Properties] = SplitModules[I];
 llvm::ErrorOr> FileOrErr =
 llvm::MemoryBuffer::getFileOrSTDIN(File);
 if (std::error_code EC = FileOrErr.getError()) {
@@ -385,6 +387,7 @@ Error runSYCLLink(ArrayRef Files, const 
ArgList &Args) {
   else
 return createFileError(File, EC);
 }
+
 OffloadingImage TheImage{};
 TheImage.TheImageKind = IMG_Object;
 TheImage.TheOffloadKind = OFK_SYCL;
@@ -392,6 +395,7 @@ Error runSYCLLink(ArrayRef Files, const 
ArgList &Args) {
 Args.MakeArgString(Args.getLastArgValue(OPT_triple_EQ));
 TheImage.StringData["arch"] =
 Args.MakeArgString(Args.getLastArgValue(OPT_arch_EQ));
+TheImage.StringData["sycl_properties"] = Properties.writeJSON();
 TheImage.Image = std::move(*FileOrErr);
 
 llvm::SmallString<0> Buffer = OffloadBinary::write(TheImage);
diff --git a/llvm/include/llvm/Frontend/Offloading/Utility.h 
b/llvm/include/llvm/Frontend/Offloading/Utility.h
index 7b717a4733b79..c33a94a6cdf29 100644
--- a/llvm/include/llvm/Frontend/Offloading/Utility.h
+++ b/llvm/include/llvm/Frontend/Offloading/Utility.h
@@ -11,6 +11,7 @@
 
 #include 
 #include 
+#include 
 
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringRef.h"
@@ -159,6 +160,107 @@ namespace intel {
 /// the Intel runtime offload plugin.
 Error containerizeOpenMPSPIRVImage(std::unique_ptr &Binary);
 } // namespace intel
+
+namespace sycl {
+class PropertySetRegistry;
+
+// A property value. It can be either a 32-bit unsigned integer or a byte 
array.
+class PropertyValue {
+public:
+  using ByteArrayTy = SmallVector;
+
+  PropertyValue() = default;
+  PropertyValue(uint32_t Val) : Value(Val) {}
+  PropertyValue(StringRef Data)
+  : Value(ByteArrayTy(Data.begin(), Data.end())) {}
+
+  template 
+  PropertyValue(const C &Data)
+  : PropertyValue({reinterpret_cast(Data.data()),
+   Data.size() * sizeof(T)}) {}
+
+  uint32_t asUint32() const {
+assert(getType() == PV_UInt32 && "must be UINT32 value");
+return std::get(Value);
+  }
+
+  StringRef asByteArray() const {
+assert(getType() == PV_ByteArray && "must be BYTE_ARRAY value");
+const auto &ByteArrayRef = std::get(Value);
+return {ByteArrayRef.data(), ByteArrayRef.size()};
+  }
+
+  // Note: each enumeratio

[clang] [llvm] [SYCL] Add SYCL property set registry class (PR #136697)

2025-04-22 Thread Justin Cai via cfe-commits 




jzc wrote:

For now, I've placed the class in `Frontend/Offloading/Utility.h`. If we get 
`Frontend/Offloading/SYCL` later on then I then that would be the most 
appropriate place to put it. 

https://github.com/llvm/llvm-project/pull/136697
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[clang] [llvm] [SYCL] Add SYCL property set registry class (PR #136697)

2025-04-22 Thread Justin Cai via cfe-commits 


@@ -159,6 +160,107 @@ namespace intel {
 /// the Intel runtime offload plugin.
 Error containerizeOpenMPSPIRVImage(std::unique_ptr &Binary);
 } // namespace intel
+
+namespace sycl {
+class PropertySetRegistry;
+
+// A property value. It can be either a 32-bit unsigned integer or a byte 
array.
+class PropertyValue {
+public:
+  using ByteArrayTy = SmallVector;
+
+  PropertyValue() = default;
+  PropertyValue(uint32_t Val) : Value(Val) {}
+  PropertyValue(StringRef Data)
+  : Value(ByteArrayTy(Data.begin(), Data.end())) {}
+
+  template 
+  PropertyValue(const C &Data)
+  : PropertyValue({reinterpret_cast(Data.data()),
+   Data.size() * sizeof(T)}) {}

jzc wrote:

I've simplified the byte array code compared to the downstream code, but they 
won't compatible downstream and would cause ABI-break and runtime changes. The 
downstream implementation always wrote the number of bits the data uses in the 
first 8 bytes of a byte-array property value, but after some tests, I found 
this values way never used, except for one place that could be worked around.

https://github.com/intel/llvm/blob/a9db58476ab1e1ff87f128088ac203539d87d22b/llvm/lib/Support/PropertySetIO.cpp#L153-L169

https://github.com/llvm/llvm-project/pull/136697
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[clang] [llvm] [SYCL] Add SYCL property set registry class (PR #136697)

2025-04-22 Thread Justin Cai via cfe-commits 

https://github.com/jzc closed https://github.com/llvm/llvm-project/pull/136697
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[clang] [llvm] [SYCL] Add SYCL property set registry class (PR #136697)

2025-04-22 Thread Justin Cai via cfe-commits 

https://github.com/jzc deleted https://github.com/llvm/llvm-project/pull/136697
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[clang] [llvm] [SYCL] Add SYCL property set registry class (PR #136697)

2025-04-22 Thread Justin Cai via cfe-commits 

https://github.com/jzc deleted https://github.com/llvm/llvm-project/pull/136697
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[clang] [Clang][SYCL] Add AOT compilation support for Intel GPUs in clang-sycl-linker (PR #133194)

2025-05-05 Thread Justin Cai via cfe-commits 

https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/133194



  



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[clang] [Clang][SYCL] Add initial set of Intel OffloadArch values (PR #138158)

2025-05-01 Thread Justin Cai via cfe-commits 

https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/138158

>From f1b0e2cbe8229ba00956e0eac58f97d71995b0dd Mon Sep 17 00:00:00 2001
From: "Cai, Justin" 
Date: Mon, 14 Apr 2025 21:30:39 +
Subject: [PATCH 1/2] [Clang][SYCL] Add initial set of Intel OffloadArch values

---
 clang/include/clang/Basic/OffloadArch.h   | 19 
 clang/lib/Basic/OffloadArch.cpp   |  4 +++
 clang/lib/Basic/Targets/NVPTX.cpp |  2 ++
 clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp  |  2 ++
 clang/unittests/Basic/CMakeLists.txt  |  1 +
 clang/unittests/Basic/OffloadArchTest.cpp | 36 +++
 6 files changed, 64 insertions(+)
 create mode 100644 clang/unittests/Basic/OffloadArchTest.cpp

diff --git a/clang/include/clang/Basic/OffloadArch.h 
b/clang/include/clang/Basic/OffloadArch.h
index c5ccd17e7a8be..c681f99f2e146 100644
--- a/clang/include/clang/Basic/OffloadArch.h
+++ b/clang/include/clang/Basic/OffloadArch.h
@@ -101,6 +101,13 @@ enum class OffloadArch {
   AMDGCNSPIRV,
   Generic, // A processor model named 'generic' if the target backend defines a
// public one.
+  // Note: this is an initial list of Intel GPU and GPU offloading
+  // architectures. The list will be expanded later as support for more
+  // architectures is added.
+  // Intel CPUs
+  GRANITERAPIDS,
+  // Intel GPUs
+  BMG_G21,
   LAST,
 
   CudaDefault = OffloadArch::SM_52,
@@ -116,6 +123,18 @@ static inline bool IsAMDOffloadArch(OffloadArch A) {
   return A >= OffloadArch::GFX600 && A < OffloadArch::Generic;
 }
 
+static inline bool IsIntelCPUOffloadArch(OffloadArch Arch) {
+  return Arch >= OffloadArch::GRANITERAPIDS && Arch < OffloadArch::BMG_G21;
+}
+
+static inline bool IsIntelGPUOffloadArch(OffloadArch Arch) {
+  return Arch >= OffloadArch::BMG_G21 && Arch < OffloadArch::LAST;
+}
+
+static inline bool IsIntelOffloadArch(OffloadArch Arch) {
+  return IsIntelCPUOffloadArch(Arch) || IsIntelGPUOffloadArch(Arch);
+}
+
 const char *OffloadArchToString(OffloadArch A);
 const char *OffloadArchToVirtualArchString(OffloadArch A);
 
diff --git a/clang/lib/Basic/OffloadArch.cpp b/clang/lib/Basic/OffloadArch.cpp
index 5e29742478b99..a019f0ac18c84 100644
--- a/clang/lib/Basic/OffloadArch.cpp
+++ b/clang/lib/Basic/OffloadArch.cpp
@@ -87,6 +87,10 @@ static const OffloadArchToStringMap ArchNames[] = {
 GFX(1200), // gfx1200
 GFX(1201), // gfx1201
 {OffloadArch::AMDGCNSPIRV, "amdgcnspirv", "compute_amdgcn"},
+// Intel CPUs
+{OffloadArch::GRANITERAPIDS, "graniterapids", ""},
+// Intel GPUS
+{OffloadArch::BMG_G21, "bmg_g21", ""},
 {OffloadArch::Generic, "generic", ""},
 // clang-format on
 };
diff --git a/clang/lib/Basic/Targets/NVPTX.cpp 
b/clang/lib/Basic/Targets/NVPTX.cpp
index 08c8460045c6a..42b66d3559f6a 100644
--- a/clang/lib/Basic/Targets/NVPTX.cpp
+++ b/clang/lib/Basic/Targets/NVPTX.cpp
@@ -241,6 +241,8 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions 
&Opts,
   case OffloadArch::GFX1201:
   case OffloadArch::AMDGCNSPIRV:
   case OffloadArch::Generic:
+  case OffloadArch::GRANITERAPIDS:
+  case OffloadArch::BMG_G21:
   case OffloadArch::LAST:
 break;
   case OffloadArch::UNKNOWN:
diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp 
b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
index 59a5f7b914ce5..aa97422d54ede 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
+++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
@@ -2334,6 +2334,8 @@ void CGOpenMPRuntimeGPU::processRequiresDirective(const 
OMPRequiresDecl *D) {
   case OffloadArch::GFX1201:
   case OffloadArch::AMDGCNSPIRV:
   case OffloadArch::Generic:
+  case OffloadArch::GRANITERAPIDS:
+  case OffloadArch::BMG_G21:
   case OffloadArch::UNUSED:
   case OffloadArch::UNKNOWN:
 break;
diff --git a/clang/unittests/Basic/CMakeLists.txt 
b/clang/unittests/Basic/CMakeLists.txt
index b0e0a97168757..8c8baa57b64e7 100644
--- a/clang/unittests/Basic/CMakeLists.txt
+++ b/clang/unittests/Basic/CMakeLists.txt
@@ -7,6 +7,7 @@ add_distinct_clang_unittest(BasicTests
   FileEntryTest.cpp
   FileManagerTest.cpp
   LineOffsetMappingTest.cpp
+  OffloadArchTest.cpp
   SanitizersTest.cpp
   SarifTest.cpp
   SourceManagerTest.cpp
diff --git a/clang/unittests/Basic/OffloadArchTest.cpp 
b/clang/unittests/Basic/OffloadArchTest.cpp
new file mode 100644
index 0..c19ad0043d774
--- /dev/null
+++ b/clang/unittests/Basic/OffloadArchTest.cpp
@@ -0,0 +1,36 @@
+//===- unittests/Basic/OffloadArchTest.cpp - Test OffloadArch ---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "clang/Basic/OffloadArch.h"
+#include "gtest/gtest.h"
+
+using namespace clang;
+
+TEST(OffloadArchTest, basic) {
+  E

[clang] [Clang][SYCL] Add initial set of Intel OffloadArch values (PR #138158)

2025-05-01 Thread Justin Cai via cfe-commits 

https://github.com/jzc created https://github.com/llvm/llvm-project/pull/138158

Following #137070, this PR adds an initial set of Intel `OffloadArch` values 
with corresponding predicates that will be used in SYCL offloading. More Intel 
architectures will be added in a future PR.

>From f1b0e2cbe8229ba00956e0eac58f97d71995b0dd Mon Sep 17 00:00:00 2001
From: "Cai, Justin" 
Date: Mon, 14 Apr 2025 21:30:39 +
Subject: [PATCH] [Clang][SYCL] Add initial set of Intel OffloadArch values

---
 clang/include/clang/Basic/OffloadArch.h   | 19 
 clang/lib/Basic/OffloadArch.cpp   |  4 +++
 clang/lib/Basic/Targets/NVPTX.cpp |  2 ++
 clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp  |  2 ++
 clang/unittests/Basic/CMakeLists.txt  |  1 +
 clang/unittests/Basic/OffloadArchTest.cpp | 36 +++
 6 files changed, 64 insertions(+)
 create mode 100644 clang/unittests/Basic/OffloadArchTest.cpp

diff --git a/clang/include/clang/Basic/OffloadArch.h 
b/clang/include/clang/Basic/OffloadArch.h
index c5ccd17e7a8be..c681f99f2e146 100644
--- a/clang/include/clang/Basic/OffloadArch.h
+++ b/clang/include/clang/Basic/OffloadArch.h
@@ -101,6 +101,13 @@ enum class OffloadArch {
   AMDGCNSPIRV,
   Generic, // A processor model named 'generic' if the target backend defines a
// public one.
+  // Note: this is an initial list of Intel GPU and GPU offloading
+  // architectures. The list will be expanded later as support for more
+  // architectures is added.
+  // Intel CPUs
+  GRANITERAPIDS,
+  // Intel GPUs
+  BMG_G21,
   LAST,
 
   CudaDefault = OffloadArch::SM_52,
@@ -116,6 +123,18 @@ static inline bool IsAMDOffloadArch(OffloadArch A) {
   return A >= OffloadArch::GFX600 && A < OffloadArch::Generic;
 }
 
+static inline bool IsIntelCPUOffloadArch(OffloadArch Arch) {
+  return Arch >= OffloadArch::GRANITERAPIDS && Arch < OffloadArch::BMG_G21;
+}
+
+static inline bool IsIntelGPUOffloadArch(OffloadArch Arch) {
+  return Arch >= OffloadArch::BMG_G21 && Arch < OffloadArch::LAST;
+}
+
+static inline bool IsIntelOffloadArch(OffloadArch Arch) {
+  return IsIntelCPUOffloadArch(Arch) || IsIntelGPUOffloadArch(Arch);
+}
+
 const char *OffloadArchToString(OffloadArch A);
 const char *OffloadArchToVirtualArchString(OffloadArch A);
 
diff --git a/clang/lib/Basic/OffloadArch.cpp b/clang/lib/Basic/OffloadArch.cpp
index 5e29742478b99..a019f0ac18c84 100644
--- a/clang/lib/Basic/OffloadArch.cpp
+++ b/clang/lib/Basic/OffloadArch.cpp
@@ -87,6 +87,10 @@ static const OffloadArchToStringMap ArchNames[] = {
 GFX(1200), // gfx1200
 GFX(1201), // gfx1201
 {OffloadArch::AMDGCNSPIRV, "amdgcnspirv", "compute_amdgcn"},
+// Intel CPUs
+{OffloadArch::GRANITERAPIDS, "graniterapids", ""},
+// Intel GPUS
+{OffloadArch::BMG_G21, "bmg_g21", ""},
 {OffloadArch::Generic, "generic", ""},
 // clang-format on
 };
diff --git a/clang/lib/Basic/Targets/NVPTX.cpp 
b/clang/lib/Basic/Targets/NVPTX.cpp
index 08c8460045c6a..42b66d3559f6a 100644
--- a/clang/lib/Basic/Targets/NVPTX.cpp
+++ b/clang/lib/Basic/Targets/NVPTX.cpp
@@ -241,6 +241,8 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions 
&Opts,
   case OffloadArch::GFX1201:
   case OffloadArch::AMDGCNSPIRV:
   case OffloadArch::Generic:
+  case OffloadArch::GRANITERAPIDS:
+  case OffloadArch::BMG_G21:
   case OffloadArch::LAST:
 break;
   case OffloadArch::UNKNOWN:
diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp 
b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
index 59a5f7b914ce5..aa97422d54ede 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
+++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
@@ -2334,6 +2334,8 @@ void CGOpenMPRuntimeGPU::processRequiresDirective(const 
OMPRequiresDecl *D) {
   case OffloadArch::GFX1201:
   case OffloadArch::AMDGCNSPIRV:
   case OffloadArch::Generic:
+  case OffloadArch::GRANITERAPIDS:
+  case OffloadArch::BMG_G21:
   case OffloadArch::UNUSED:
   case OffloadArch::UNKNOWN:
 break;
diff --git a/clang/unittests/Basic/CMakeLists.txt 
b/clang/unittests/Basic/CMakeLists.txt
index b0e0a97168757..8c8baa57b64e7 100644
--- a/clang/unittests/Basic/CMakeLists.txt
+++ b/clang/unittests/Basic/CMakeLists.txt
@@ -7,6 +7,7 @@ add_distinct_clang_unittest(BasicTests
   FileEntryTest.cpp
   FileManagerTest.cpp
   LineOffsetMappingTest.cpp
+  OffloadArchTest.cpp
   SanitizersTest.cpp
   SarifTest.cpp
   SourceManagerTest.cpp
diff --git a/clang/unittests/Basic/OffloadArchTest.cpp 
b/clang/unittests/Basic/OffloadArchTest.cpp
new file mode 100644
index 0..c19ad0043d774
--- /dev/null
+++ b/clang/unittests/Basic/OffloadArchTest.cpp
@@ -0,0 +1,36 @@
+//===- unittests/Basic/OffloadArchTest.cpp - Test OffloadArch ---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---

[clang] [Clang] Move OffloadArch enum to a generic location and add initial set of Intel OffloadArch values (PR #137070)

2025-04-23 Thread Justin Cai via cfe-commits 

https://github.com/jzc created https://github.com/llvm/llvm-project/pull/137070

None

>From 924f54246910cad42f97efe1bc3d3bdfec039ecb Mon Sep 17 00:00:00 2001
From: "Cai, Justin" 
Date: Mon, 14 Apr 2025 21:30:39 +
Subject: [PATCH] [Clang] Move OffloadArch enum to a generic location and add
 initial set of Intel OffloadArch values

---
 clang/include/clang/Basic/Cuda.h  | 109 +
 clang/include/clang/Basic/OffloadArch.h   | 143 ++
 clang/lib/Basic/CMakeLists.txt|   1 +
 clang/lib/Basic/Cuda.cpp  | 117 --
 clang/lib/Basic/OffloadArch.cpp   | 133 
 clang/lib/Basic/Targets/NVPTX.cpp |   2 +
 clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp  |   2 +
 clang/unittests/Basic/CMakeLists.txt  |   1 +
 clang/unittests/Basic/OffloadArchTest.cpp |  36 ++
 9 files changed, 320 insertions(+), 224 deletions(-)
 create mode 100644 clang/include/clang/Basic/OffloadArch.h
 create mode 100644 clang/lib/Basic/OffloadArch.cpp
 create mode 100644 clang/unittests/Basic/OffloadArchTest.cpp

diff --git a/clang/include/clang/Basic/Cuda.h b/clang/include/clang/Basic/Cuda.h
index c4eb7b7cac1d6..d6a22a7af559b 100644
--- a/clang/include/clang/Basic/Cuda.h
+++ b/clang/include/clang/Basic/Cuda.h
@@ -9,6 +9,8 @@
 #ifndef LLVM_CLANG_BASIC_CUDA_H
 #define LLVM_CLANG_BASIC_CUDA_H
 
+#include "clang/Basic/OffloadArch.h"
+
 namespace llvm {
 class StringRef;
 class Twine;
@@ -54,98 +56,6 @@ const char *CudaVersionToString(CudaVersion V);
 // Input is "Major.Minor"
 CudaVersion CudaStringToVersion(const llvm::Twine &S);
 
-enum class OffloadArch {
-  UNUSED,
-  UNKNOWN,
-  // TODO: Deprecate and remove GPU architectures older than sm_52.
-  SM_20,
-  SM_21,
-  SM_30,
-  // This has a name conflict with sys/mac.h on AIX, rename it as a workaround.
-  SM_32_,
-  SM_35,
-  SM_37,
-  SM_50,
-  SM_52,
-  SM_53,
-  SM_60,
-  SM_61,
-  SM_62,
-  SM_70,
-  SM_72,
-  SM_75,
-  SM_80,
-  SM_86,
-  SM_87,
-  SM_89,
-  SM_90,
-  SM_90a,
-  SM_100,
-  SM_100a,
-  SM_101,
-  SM_101a,
-  SM_120,
-  SM_120a,
-  GFX600,
-  GFX601,
-  GFX602,
-  GFX700,
-  GFX701,
-  GFX702,
-  GFX703,
-  GFX704,
-  GFX705,
-  GFX801,
-  GFX802,
-  GFX803,
-  GFX805,
-  GFX810,
-  GFX9_GENERIC,
-  GFX900,
-  GFX902,
-  GFX904,
-  GFX906,
-  GFX908,
-  GFX909,
-  GFX90a,
-  GFX90c,
-  GFX9_4_GENERIC,
-  GFX942,
-  GFX950,
-  GFX10_1_GENERIC,
-  GFX1010,
-  GFX1011,
-  GFX1012,
-  GFX1013,
-  GFX10_3_GENERIC,
-  GFX1030,
-  GFX1031,
-  GFX1032,
-  GFX1033,
-  GFX1034,
-  GFX1035,
-  GFX1036,
-  GFX11_GENERIC,
-  GFX1100,
-  GFX1101,
-  GFX1102,
-  GFX1103,
-  GFX1150,
-  GFX1151,
-  GFX1152,
-  GFX1153,
-  GFX12_GENERIC,
-  GFX1200,
-  GFX1201,
-  AMDGCNSPIRV,
-  Generic, // A processor model named 'generic' if the target backend defines a
-   // public one.
-  LAST,
-
-  CudaDefault = OffloadArch::SM_52,
-  HIPDefault = OffloadArch::GFX906,
-};
-
 enum class CUDAFunctionTarget {
   Device,
   Global,
@@ -154,21 +64,6 @@ enum class CUDAFunctionTarget {
   InvalidTarget
 };
 
-static inline bool IsNVIDIAOffloadArch(OffloadArch A) {
-  return A >= OffloadArch::SM_20 && A < OffloadArch::GFX600;
-}
-
-static inline bool IsAMDOffloadArch(OffloadArch A) {
-  // Generic processor model is for testing only.
-  return A >= OffloadArch::GFX600 && A < OffloadArch::Generic;
-}
-
-const char *OffloadArchToString(OffloadArch A);
-const char *OffloadArchToVirtualArchString(OffloadArch A);
-
-// The input should have the form "sm_20".
-OffloadArch StringToOffloadArch(llvm::StringRef S);
-
 /// Get the earliest CudaVersion that supports the given OffloadArch.
 CudaVersion MinVersionForOffloadArch(OffloadArch A);
 
diff --git a/clang/include/clang/Basic/OffloadArch.h 
b/clang/include/clang/Basic/OffloadArch.h
new file mode 100644
index 0..6fee1e2bc8c06
--- /dev/null
+++ b/clang/include/clang/Basic/OffloadArch.h
@@ -0,0 +1,143 @@
+//===--- OffloadArch.h - Definition of offloading architectures --- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CLANG_BASIC_OFFLOADARCH_H
+#define LLVM_CLANG_BASIC_OFFLOADARCH_H
+
+namespace llvm {
+class StringRef;
+} // namespace llvm
+
+namespace clang {
+
+enum class OffloadArch {
+  UNUSED,
+  UNKNOWN,
+  // TODO: Deprecate and remove GPU architectures older than sm_52.
+  SM_20,
+  SM_21,
+  SM_30,
+  // This has a name conflict with sys/mac.h on AIX, rename it as a workaround.
+  SM_32_,
+  SM_35,
+  SM_37,
+  SM_50,
+  SM_52,
+  SM_53,
+  SM_60,
+  SM_61,
+  SM_62,
+  SM_70,
+  SM_72,
+  SM_75,
+  SM_80,
+  SM_86,
+  SM_87,
+  SM_89,
+  SM_90,
+  SM_90a,
+  SM_100,
+  SM_100a,
+  SM_101,
+  SM_101a,
+  SM_120,
+  SM_120a,
+  GFX600,
+  GFX601,
+

[clang] [Clang] Move OffloadArch enum to a generic location and add initial set of Intel OffloadArch values (PR #137070)

2025-04-23 Thread Justin Cai via cfe-commits 

https://github.com/jzc edited https://github.com/llvm/llvm-project/pull/137070
___
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[clang] [Clang] Move OffloadArch enum to a generic location and add initial set of Intel OffloadArch values (PR #137070)

2025-04-24 Thread Justin Cai via cfe-commits 

https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/137070

>From 924f54246910cad42f97efe1bc3d3bdfec039ecb Mon Sep 17 00:00:00 2001
From: "Cai, Justin" 
Date: Mon, 14 Apr 2025 21:30:39 +
Subject: [PATCH 1/2] [Clang] Move OffloadArch enum to a generic location and
 add initial set of Intel OffloadArch values

---
 clang/include/clang/Basic/Cuda.h  | 109 +
 clang/include/clang/Basic/OffloadArch.h   | 143 ++
 clang/lib/Basic/CMakeLists.txt|   1 +
 clang/lib/Basic/Cuda.cpp  | 117 --
 clang/lib/Basic/OffloadArch.cpp   | 133 
 clang/lib/Basic/Targets/NVPTX.cpp |   2 +
 clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp  |   2 +
 clang/unittests/Basic/CMakeLists.txt  |   1 +
 clang/unittests/Basic/OffloadArchTest.cpp |  36 ++
 9 files changed, 320 insertions(+), 224 deletions(-)
 create mode 100644 clang/include/clang/Basic/OffloadArch.h
 create mode 100644 clang/lib/Basic/OffloadArch.cpp
 create mode 100644 clang/unittests/Basic/OffloadArchTest.cpp

diff --git a/clang/include/clang/Basic/Cuda.h b/clang/include/clang/Basic/Cuda.h
index c4eb7b7cac1d6..d6a22a7af559b 100644
--- a/clang/include/clang/Basic/Cuda.h
+++ b/clang/include/clang/Basic/Cuda.h
@@ -9,6 +9,8 @@
 #ifndef LLVM_CLANG_BASIC_CUDA_H
 #define LLVM_CLANG_BASIC_CUDA_H
 
+#include "clang/Basic/OffloadArch.h"
+
 namespace llvm {
 class StringRef;
 class Twine;
@@ -54,98 +56,6 @@ const char *CudaVersionToString(CudaVersion V);
 // Input is "Major.Minor"
 CudaVersion CudaStringToVersion(const llvm::Twine &S);
 
-enum class OffloadArch {
-  UNUSED,
-  UNKNOWN,
-  // TODO: Deprecate and remove GPU architectures older than sm_52.
-  SM_20,
-  SM_21,
-  SM_30,
-  // This has a name conflict with sys/mac.h on AIX, rename it as a workaround.
-  SM_32_,
-  SM_35,
-  SM_37,
-  SM_50,
-  SM_52,
-  SM_53,
-  SM_60,
-  SM_61,
-  SM_62,
-  SM_70,
-  SM_72,
-  SM_75,
-  SM_80,
-  SM_86,
-  SM_87,
-  SM_89,
-  SM_90,
-  SM_90a,
-  SM_100,
-  SM_100a,
-  SM_101,
-  SM_101a,
-  SM_120,
-  SM_120a,
-  GFX600,
-  GFX601,
-  GFX602,
-  GFX700,
-  GFX701,
-  GFX702,
-  GFX703,
-  GFX704,
-  GFX705,
-  GFX801,
-  GFX802,
-  GFX803,
-  GFX805,
-  GFX810,
-  GFX9_GENERIC,
-  GFX900,
-  GFX902,
-  GFX904,
-  GFX906,
-  GFX908,
-  GFX909,
-  GFX90a,
-  GFX90c,
-  GFX9_4_GENERIC,
-  GFX942,
-  GFX950,
-  GFX10_1_GENERIC,
-  GFX1010,
-  GFX1011,
-  GFX1012,
-  GFX1013,
-  GFX10_3_GENERIC,
-  GFX1030,
-  GFX1031,
-  GFX1032,
-  GFX1033,
-  GFX1034,
-  GFX1035,
-  GFX1036,
-  GFX11_GENERIC,
-  GFX1100,
-  GFX1101,
-  GFX1102,
-  GFX1103,
-  GFX1150,
-  GFX1151,
-  GFX1152,
-  GFX1153,
-  GFX12_GENERIC,
-  GFX1200,
-  GFX1201,
-  AMDGCNSPIRV,
-  Generic, // A processor model named 'generic' if the target backend defines a
-   // public one.
-  LAST,
-
-  CudaDefault = OffloadArch::SM_52,
-  HIPDefault = OffloadArch::GFX906,
-};
-
 enum class CUDAFunctionTarget {
   Device,
   Global,
@@ -154,21 +64,6 @@ enum class CUDAFunctionTarget {
   InvalidTarget
 };
 
-static inline bool IsNVIDIAOffloadArch(OffloadArch A) {
-  return A >= OffloadArch::SM_20 && A < OffloadArch::GFX600;
-}
-
-static inline bool IsAMDOffloadArch(OffloadArch A) {
-  // Generic processor model is for testing only.
-  return A >= OffloadArch::GFX600 && A < OffloadArch::Generic;
-}
-
-const char *OffloadArchToString(OffloadArch A);
-const char *OffloadArchToVirtualArchString(OffloadArch A);
-
-// The input should have the form "sm_20".
-OffloadArch StringToOffloadArch(llvm::StringRef S);
-
 /// Get the earliest CudaVersion that supports the given OffloadArch.
 CudaVersion MinVersionForOffloadArch(OffloadArch A);
 
diff --git a/clang/include/clang/Basic/OffloadArch.h 
b/clang/include/clang/Basic/OffloadArch.h
new file mode 100644
index 0..6fee1e2bc8c06
--- /dev/null
+++ b/clang/include/clang/Basic/OffloadArch.h
@@ -0,0 +1,143 @@
+//===--- OffloadArch.h - Definition of offloading architectures --- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CLANG_BASIC_OFFLOADARCH_H
+#define LLVM_CLANG_BASIC_OFFLOADARCH_H
+
+namespace llvm {
+class StringRef;
+} // namespace llvm
+
+namespace clang {
+
+enum class OffloadArch {
+  UNUSED,
+  UNKNOWN,
+  // TODO: Deprecate and remove GPU architectures older than sm_52.
+  SM_20,
+  SM_21,
+  SM_30,
+  // This has a name conflict with sys/mac.h on AIX, rename it as a workaround.
+  SM_32_,
+  SM_35,
+  SM_37,
+  SM_50,
+  SM_52,
+  SM_53,
+  SM_60,
+  SM_61,
+  SM_62,
+  SM_70,
+  SM_72,
+  SM_75,
+  SM_80,
+  SM_86,
+  SM_87,
+  SM_89,
+  SM_90,
+  SM_90a,
+  SM_100,
+  SM_100a,
+  SM_101,
+  SM_101a,
+  SM_120,
+  SM_120a,
+  GFX600,
+  GFX601,
+  G

[clang] [Clang][NFC[ Move OffloadArch enum to a generic location (PR #137070)

2025-04-24 Thread Justin Cai via cfe-commits 

https://github.com/jzc edited https://github.com/llvm/llvm-project/pull/137070
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[clang] [Clang][NFC] Move OffloadArch enum to a generic location (PR #137070)

2025-04-24 Thread Justin Cai via cfe-commits 

https://github.com/jzc edited https://github.com/llvm/llvm-project/pull/137070
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[clang] [Clang][NFC] Move OffloadArch enum to a generic location (PR #137070)

2025-04-24 Thread Justin Cai via cfe-commits 

https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/137070

>From 924f54246910cad42f97efe1bc3d3bdfec039ecb Mon Sep 17 00:00:00 2001
From: "Cai, Justin" 
Date: Mon, 14 Apr 2025 21:30:39 +
Subject: [PATCH 1/3] [Clang] Move OffloadArch enum to a generic location and
 add initial set of Intel OffloadArch values

---
 clang/include/clang/Basic/Cuda.h  | 109 +
 clang/include/clang/Basic/OffloadArch.h   | 143 ++
 clang/lib/Basic/CMakeLists.txt|   1 +
 clang/lib/Basic/Cuda.cpp  | 117 --
 clang/lib/Basic/OffloadArch.cpp   | 133 
 clang/lib/Basic/Targets/NVPTX.cpp |   2 +
 clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp  |   2 +
 clang/unittests/Basic/CMakeLists.txt  |   1 +
 clang/unittests/Basic/OffloadArchTest.cpp |  36 ++
 9 files changed, 320 insertions(+), 224 deletions(-)
 create mode 100644 clang/include/clang/Basic/OffloadArch.h
 create mode 100644 clang/lib/Basic/OffloadArch.cpp
 create mode 100644 clang/unittests/Basic/OffloadArchTest.cpp

diff --git a/clang/include/clang/Basic/Cuda.h b/clang/include/clang/Basic/Cuda.h
index c4eb7b7cac1d6..d6a22a7af559b 100644
--- a/clang/include/clang/Basic/Cuda.h
+++ b/clang/include/clang/Basic/Cuda.h
@@ -9,6 +9,8 @@
 #ifndef LLVM_CLANG_BASIC_CUDA_H
 #define LLVM_CLANG_BASIC_CUDA_H
 
+#include "clang/Basic/OffloadArch.h"
+
 namespace llvm {
 class StringRef;
 class Twine;
@@ -54,98 +56,6 @@ const char *CudaVersionToString(CudaVersion V);
 // Input is "Major.Minor"
 CudaVersion CudaStringToVersion(const llvm::Twine &S);
 
-enum class OffloadArch {
-  UNUSED,
-  UNKNOWN,
-  // TODO: Deprecate and remove GPU architectures older than sm_52.
-  SM_20,
-  SM_21,
-  SM_30,
-  // This has a name conflict with sys/mac.h on AIX, rename it as a workaround.
-  SM_32_,
-  SM_35,
-  SM_37,
-  SM_50,
-  SM_52,
-  SM_53,
-  SM_60,
-  SM_61,
-  SM_62,
-  SM_70,
-  SM_72,
-  SM_75,
-  SM_80,
-  SM_86,
-  SM_87,
-  SM_89,
-  SM_90,
-  SM_90a,
-  SM_100,
-  SM_100a,
-  SM_101,
-  SM_101a,
-  SM_120,
-  SM_120a,
-  GFX600,
-  GFX601,
-  GFX602,
-  GFX700,
-  GFX701,
-  GFX702,
-  GFX703,
-  GFX704,
-  GFX705,
-  GFX801,
-  GFX802,
-  GFX803,
-  GFX805,
-  GFX810,
-  GFX9_GENERIC,
-  GFX900,
-  GFX902,
-  GFX904,
-  GFX906,
-  GFX908,
-  GFX909,
-  GFX90a,
-  GFX90c,
-  GFX9_4_GENERIC,
-  GFX942,
-  GFX950,
-  GFX10_1_GENERIC,
-  GFX1010,
-  GFX1011,
-  GFX1012,
-  GFX1013,
-  GFX10_3_GENERIC,
-  GFX1030,
-  GFX1031,
-  GFX1032,
-  GFX1033,
-  GFX1034,
-  GFX1035,
-  GFX1036,
-  GFX11_GENERIC,
-  GFX1100,
-  GFX1101,
-  GFX1102,
-  GFX1103,
-  GFX1150,
-  GFX1151,
-  GFX1152,
-  GFX1153,
-  GFX12_GENERIC,
-  GFX1200,
-  GFX1201,
-  AMDGCNSPIRV,
-  Generic, // A processor model named 'generic' if the target backend defines a
-   // public one.
-  LAST,
-
-  CudaDefault = OffloadArch::SM_52,
-  HIPDefault = OffloadArch::GFX906,
-};
-
 enum class CUDAFunctionTarget {
   Device,
   Global,
@@ -154,21 +64,6 @@ enum class CUDAFunctionTarget {
   InvalidTarget
 };
 
-static inline bool IsNVIDIAOffloadArch(OffloadArch A) {
-  return A >= OffloadArch::SM_20 && A < OffloadArch::GFX600;
-}
-
-static inline bool IsAMDOffloadArch(OffloadArch A) {
-  // Generic processor model is for testing only.
-  return A >= OffloadArch::GFX600 && A < OffloadArch::Generic;
-}
-
-const char *OffloadArchToString(OffloadArch A);
-const char *OffloadArchToVirtualArchString(OffloadArch A);
-
-// The input should have the form "sm_20".
-OffloadArch StringToOffloadArch(llvm::StringRef S);
-
 /// Get the earliest CudaVersion that supports the given OffloadArch.
 CudaVersion MinVersionForOffloadArch(OffloadArch A);
 
diff --git a/clang/include/clang/Basic/OffloadArch.h 
b/clang/include/clang/Basic/OffloadArch.h
new file mode 100644
index 0..6fee1e2bc8c06
--- /dev/null
+++ b/clang/include/clang/Basic/OffloadArch.h
@@ -0,0 +1,143 @@
+//===--- OffloadArch.h - Definition of offloading architectures --- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CLANG_BASIC_OFFLOADARCH_H
+#define LLVM_CLANG_BASIC_OFFLOADARCH_H
+
+namespace llvm {
+class StringRef;
+} // namespace llvm
+
+namespace clang {
+
+enum class OffloadArch {
+  UNUSED,
+  UNKNOWN,
+  // TODO: Deprecate and remove GPU architectures older than sm_52.
+  SM_20,
+  SM_21,
+  SM_30,
+  // This has a name conflict with sys/mac.h on AIX, rename it as a workaround.
+  SM_32_,
+  SM_35,
+  SM_37,
+  SM_50,
+  SM_52,
+  SM_53,
+  SM_60,
+  SM_61,
+  SM_62,
+  SM_70,
+  SM_72,
+  SM_75,
+  SM_80,
+  SM_86,
+  SM_87,
+  SM_89,
+  SM_90,
+  SM_90a,
+  SM_100,
+  SM_100a,
+  SM_101,
+  SM_101a,
+  SM_120,
+  SM_120a,
+  GFX600,
+  GFX601,
+  G

[clang] [Clang][NFC] Move OffloadArch enum to a generic location (PR #137070)

2025-04-24 Thread Justin Cai via cfe-commits 

https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/137070

>From 924f54246910cad42f97efe1bc3d3bdfec039ecb Mon Sep 17 00:00:00 2001
From: "Cai, Justin" 
Date: Mon, 14 Apr 2025 21:30:39 +
Subject: [PATCH 1/4] [Clang] Move OffloadArch enum to a generic location and
 add initial set of Intel OffloadArch values

---
 clang/include/clang/Basic/Cuda.h  | 109 +
 clang/include/clang/Basic/OffloadArch.h   | 143 ++
 clang/lib/Basic/CMakeLists.txt|   1 +
 clang/lib/Basic/Cuda.cpp  | 117 --
 clang/lib/Basic/OffloadArch.cpp   | 133 
 clang/lib/Basic/Targets/NVPTX.cpp |   2 +
 clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp  |   2 +
 clang/unittests/Basic/CMakeLists.txt  |   1 +
 clang/unittests/Basic/OffloadArchTest.cpp |  36 ++
 9 files changed, 320 insertions(+), 224 deletions(-)
 create mode 100644 clang/include/clang/Basic/OffloadArch.h
 create mode 100644 clang/lib/Basic/OffloadArch.cpp
 create mode 100644 clang/unittests/Basic/OffloadArchTest.cpp

diff --git a/clang/include/clang/Basic/Cuda.h b/clang/include/clang/Basic/Cuda.h
index c4eb7b7cac1d6..d6a22a7af559b 100644
--- a/clang/include/clang/Basic/Cuda.h
+++ b/clang/include/clang/Basic/Cuda.h
@@ -9,6 +9,8 @@
 #ifndef LLVM_CLANG_BASIC_CUDA_H
 #define LLVM_CLANG_BASIC_CUDA_H
 
+#include "clang/Basic/OffloadArch.h"
+
 namespace llvm {
 class StringRef;
 class Twine;
@@ -54,98 +56,6 @@ const char *CudaVersionToString(CudaVersion V);
 // Input is "Major.Minor"
 CudaVersion CudaStringToVersion(const llvm::Twine &S);
 
-enum class OffloadArch {
-  UNUSED,
-  UNKNOWN,
-  // TODO: Deprecate and remove GPU architectures older than sm_52.
-  SM_20,
-  SM_21,
-  SM_30,
-  // This has a name conflict with sys/mac.h on AIX, rename it as a workaround.
-  SM_32_,
-  SM_35,
-  SM_37,
-  SM_50,
-  SM_52,
-  SM_53,
-  SM_60,
-  SM_61,
-  SM_62,
-  SM_70,
-  SM_72,
-  SM_75,
-  SM_80,
-  SM_86,
-  SM_87,
-  SM_89,
-  SM_90,
-  SM_90a,
-  SM_100,
-  SM_100a,
-  SM_101,
-  SM_101a,
-  SM_120,
-  SM_120a,
-  GFX600,
-  GFX601,
-  GFX602,
-  GFX700,
-  GFX701,
-  GFX702,
-  GFX703,
-  GFX704,
-  GFX705,
-  GFX801,
-  GFX802,
-  GFX803,
-  GFX805,
-  GFX810,
-  GFX9_GENERIC,
-  GFX900,
-  GFX902,
-  GFX904,
-  GFX906,
-  GFX908,
-  GFX909,
-  GFX90a,
-  GFX90c,
-  GFX9_4_GENERIC,
-  GFX942,
-  GFX950,
-  GFX10_1_GENERIC,
-  GFX1010,
-  GFX1011,
-  GFX1012,
-  GFX1013,
-  GFX10_3_GENERIC,
-  GFX1030,
-  GFX1031,
-  GFX1032,
-  GFX1033,
-  GFX1034,
-  GFX1035,
-  GFX1036,
-  GFX11_GENERIC,
-  GFX1100,
-  GFX1101,
-  GFX1102,
-  GFX1103,
-  GFX1150,
-  GFX1151,
-  GFX1152,
-  GFX1153,
-  GFX12_GENERIC,
-  GFX1200,
-  GFX1201,
-  AMDGCNSPIRV,
-  Generic, // A processor model named 'generic' if the target backend defines a
-   // public one.
-  LAST,
-
-  CudaDefault = OffloadArch::SM_52,
-  HIPDefault = OffloadArch::GFX906,
-};
-
 enum class CUDAFunctionTarget {
   Device,
   Global,
@@ -154,21 +64,6 @@ enum class CUDAFunctionTarget {
   InvalidTarget
 };
 
-static inline bool IsNVIDIAOffloadArch(OffloadArch A) {
-  return A >= OffloadArch::SM_20 && A < OffloadArch::GFX600;
-}
-
-static inline bool IsAMDOffloadArch(OffloadArch A) {
-  // Generic processor model is for testing only.
-  return A >= OffloadArch::GFX600 && A < OffloadArch::Generic;
-}
-
-const char *OffloadArchToString(OffloadArch A);
-const char *OffloadArchToVirtualArchString(OffloadArch A);
-
-// The input should have the form "sm_20".
-OffloadArch StringToOffloadArch(llvm::StringRef S);
-
 /// Get the earliest CudaVersion that supports the given OffloadArch.
 CudaVersion MinVersionForOffloadArch(OffloadArch A);
 
diff --git a/clang/include/clang/Basic/OffloadArch.h 
b/clang/include/clang/Basic/OffloadArch.h
new file mode 100644
index 0..6fee1e2bc8c06
--- /dev/null
+++ b/clang/include/clang/Basic/OffloadArch.h
@@ -0,0 +1,143 @@
+//===--- OffloadArch.h - Definition of offloading architectures --- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CLANG_BASIC_OFFLOADARCH_H
+#define LLVM_CLANG_BASIC_OFFLOADARCH_H
+
+namespace llvm {
+class StringRef;
+} // namespace llvm
+
+namespace clang {
+
+enum class OffloadArch {
+  UNUSED,
+  UNKNOWN,
+  // TODO: Deprecate and remove GPU architectures older than sm_52.
+  SM_20,
+  SM_21,
+  SM_30,
+  // This has a name conflict with sys/mac.h on AIX, rename it as a workaround.
+  SM_32_,
+  SM_35,
+  SM_37,
+  SM_50,
+  SM_52,
+  SM_53,
+  SM_60,
+  SM_61,
+  SM_62,
+  SM_70,
+  SM_72,
+  SM_75,
+  SM_80,
+  SM_86,
+  SM_87,
+  SM_89,
+  SM_90,
+  SM_90a,
+  SM_100,
+  SM_100a,
+  SM_101,
+  SM_101a,
+  SM_120,
+  SM_120a,
+  GFX600,
+  GFX601,
+  G

[clang] [Clang][SYCL] Add AOT compilation support for Intel GPUs in clang-sycl-linker (PR #133194)

2025-04-03 Thread Justin Cai via cfe-commits 


@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CLANG_BASIC_SYCL_H
+#define LLVM_CLANG_BASIC_SYCL_H
+
+#include "clang/Basic/Cuda.h"
+
+namespace llvm {
+class StringRef;
+template  class SmallString;
+} // namespace llvm
+
+namespace clang {
+// List of architectures (Intel CPUs and Intel GPUs)
+// that support SYCL offloading.
+enum class SYCLSupportedIntelArchs {

jzc wrote:

I added the Intel arches to the OffloadArch enum. Although, perhaps the file it 
is defined in (Cuda.h) should be named to something more appropriate? If so, I 
can change that in a follow up PR to avoid unrelated changes.

https://github.com/llvm/llvm-project/pull/133194
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[clang] [Clang][SYCL] Add AOT compilation support for Intel GPUs in clang-sycl-linker (PR #133194)

2025-04-03 Thread Justin Cai via cfe-commits 


@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CLANG_BASIC_SYCL_H
+#define LLVM_CLANG_BASIC_SYCL_H
+
+#include "clang/Basic/Cuda.h"
+
+namespace llvm {
+class StringRef;
+template  class SmallString;
+} // namespace llvm
+
+namespace clang {
+// List of architectures (Intel CPUs and Intel GPUs)
+// that support SYCL offloading.
+enum class SYCLSupportedIntelArchs {
+  // Intel CPUs
+  UNKNOWN,
+  SKYLAKEAVX512,
+  COREAVX2,
+  COREI7AVX,
+  COREI7,
+  WESTMERE,
+  SANDYBRIDGE,
+  IVYBRIDGE,
+  BROADWELL,
+  COFFEELAKE,
+  ALDERLAKE,
+  SKYLAKE,
+  SKX,
+  CASCADELAKE,
+  ICELAKECLIENT,
+  ICELAKESERVER,
+  SAPPHIRERAPIDS,
+  GRANITERAPIDS,
+  // Intel GPUs
+  BDW,
+  SKL,
+  KBL,
+  CFL,
+  APL,
+  BXT,
+  GLK,
+  WHL,
+  AML,
+  CML,
+  ICLLP,
+  ICL,
+  EHL,
+  JSL,
+  TGLLP,
+  TGL,
+  RKL,
+  ADL_S,
+  RPL_S,
+  ADL_P,
+  ADL_N,
+  DG1,
+  ACM_G10,
+  DG2_G10,
+  ACM_G11,
+  DG2_G11,
+  ACM_G12,
+  DG2_G12,
+  PVC,
+  PVC_VG,
+  MTL_U,
+  MTL_S,
+  ARL_U,
+  ARL_S,
+  MTL_H,
+  ARL_H,
+  BMG_G21,
+  LNL_M,
+};
+
+// Check if the given Arch value is a Generic AMD GPU.
+// Currently GFX*_GENERIC AMD GPUs do not support SYCL offloading.
+// This list is used to filter out GFX*_GENERIC AMD GPUs in
+// `IsSYCLSupportedAMDGPUArch`.
+static inline bool IsAMDGenericGPUArch(OffloadArch Arch) {

jzc wrote:

I am unsure myself. However, I actually included this code in this PR by 
accident, so I am removing this function for the time being.

https://github.com/llvm/llvm-project/pull/133194
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[clang] [Clang][SYCL] Add AOT compilation support for Intel GPUs in clang-sycl-linker (PR #133194)

2025-04-03 Thread Justin Cai via cfe-commits 


@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CLANG_BASIC_SYCL_H
+#define LLVM_CLANG_BASIC_SYCL_H
+
+#include "clang/Basic/Cuda.h"
+
+namespace llvm {
+class StringRef;
+template  class SmallString;
+} // namespace llvm
+
+namespace clang {
+// List of architectures (Intel CPUs and Intel GPUs)
+// that support SYCL offloading.
+enum class SYCLSupportedIntelArchs {

jzc wrote:

Good idea, I moved the `OffloadArch` enum into Offloading.cpp/h, and kept the 
CUDA specific stuff in Cuda.h, and included that in Cuda.h, so it looks like no 
follow up PR of renaming of Cuda.h will be necessary.

[Add 
Offloading.cpp/h](https://github.com/llvm/llvm-project/pull/133194/commits/9002f9a743b83077eeeb0fe316eadd33f4880e96)

https://github.com/llvm/llvm-project/pull/133194
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[clang] [Clang][SYCL] Add AOT compilation support for Intel GPUs in clang-sycl-linker (PR #133194)

2025-04-03 Thread Justin Cai via cfe-commits 

https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/133194

>From 8f22fbe1f6272beec61e62bfae72832d75b4f25b Mon Sep 17 00:00:00 2001
From: "Cai, Justin" 
Date: Fri, 14 Feb 2025 21:16:27 +
Subject: [PATCH 1/6] [SYCL] Add support AOT compilation support for Intel GPUs
 in clang-sycl-linker

---
 clang/include/clang/Basic/SYCL.h  | 131 ++
 clang/lib/Basic/CMakeLists.txt|   1 +
 clang/lib/Basic/SYCL.cpp  | 226 ++
 clang/test/Driver/clang-sycl-linker-test.cpp  |  36 +++
 .../clang-sycl-linker/ClangSYCLLinker.cpp | 112 -
 clang/tools/clang-sycl-linker/SYCLLinkOpts.td |   8 +
 6 files changed, 506 insertions(+), 8 deletions(-)
 create mode 100644 clang/include/clang/Basic/SYCL.h
 create mode 100644 clang/lib/Basic/SYCL.cpp

diff --git a/clang/include/clang/Basic/SYCL.h b/clang/include/clang/Basic/SYCL.h
new file mode 100644
index 0..c7cad37639b91
--- /dev/null
+++ b/clang/include/clang/Basic/SYCL.h
@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CLANG_BASIC_SYCL_H
+#define LLVM_CLANG_BASIC_SYCL_H
+
+#include "clang/Basic/Cuda.h"
+
+namespace llvm {
+class StringRef;
+template  class SmallString;
+} // namespace llvm
+
+namespace clang {
+// List of architectures (Intel CPUs and Intel GPUs)
+// that support SYCL offloading.
+enum class SYCLSupportedIntelArchs {
+  // Intel CPUs
+  UNKNOWN,
+  SKYLAKEAVX512,
+  COREAVX2,
+  COREI7AVX,
+  COREI7,
+  WESTMERE,
+  SANDYBRIDGE,
+  IVYBRIDGE,
+  BROADWELL,
+  COFFEELAKE,
+  ALDERLAKE,
+  SKYLAKE,
+  SKX,
+  CASCADELAKE,
+  ICELAKECLIENT,
+  ICELAKESERVER,
+  SAPPHIRERAPIDS,
+  GRANITERAPIDS,
+  // Intel GPUs
+  BDW,
+  SKL,
+  KBL,
+  CFL,
+  APL,
+  BXT,
+  GLK,
+  WHL,
+  AML,
+  CML,
+  ICLLP,
+  ICL,
+  EHL,
+  JSL,
+  TGLLP,
+  TGL,
+  RKL,
+  ADL_S,
+  RPL_S,
+  ADL_P,
+  ADL_N,
+  DG1,
+  ACM_G10,
+  DG2_G10,
+  ACM_G11,
+  DG2_G11,
+  ACM_G12,
+  DG2_G12,
+  PVC,
+  PVC_VG,
+  MTL_U,
+  MTL_S,
+  ARL_U,
+  ARL_S,
+  MTL_H,
+  ARL_H,
+  BMG_G21,
+  LNL_M,
+};
+
+// Check if the given Arch value is a Generic AMD GPU.
+// Currently GFX*_GENERIC AMD GPUs do not support SYCL offloading.
+// This list is used to filter out GFX*_GENERIC AMD GPUs in
+// `IsSYCLSupportedAMDGPUArch`.
+static inline bool IsAMDGenericGPUArch(OffloadArch Arch) {
+  return Arch == OffloadArch::GFX9_GENERIC ||
+ Arch == OffloadArch::GFX10_1_GENERIC ||
+ Arch == OffloadArch::GFX10_3_GENERIC ||
+ Arch == OffloadArch::GFX11_GENERIC ||
+ Arch == OffloadArch::GFX12_GENERIC;
+}
+
+// Check if the given Arch value is a valid SYCL supported AMD GPU.
+static inline bool IsSYCLSupportedAMDGPUArch(OffloadArch Arch) {
+  return Arch >= OffloadArch::GFX700 && Arch < OffloadArch::AMDGCNSPIRV &&
+ !IsAMDGenericGPUArch(Arch);
+}
+
+// Check if the given Arch value is a valid SYCL supported NVidia GPU.
+static inline bool IsSYCLSupportedNVidiaGPUArch(OffloadArch Arch) {
+  return Arch >= OffloadArch::SM_50 && Arch <= OffloadArch::SM_90a;
+}
+
+// Check if the given Arch value is a valid SYCL supported Intel CPU.
+static inline bool IsSYCLSupportedIntelCPUArch(SYCLSupportedIntelArchs Arch) {
+  return Arch >= SYCLSupportedIntelArchs::SKYLAKEAVX512 &&
+ Arch <= SYCLSupportedIntelArchs::GRANITERAPIDS;
+}
+
+// Check if the given Arch value is a valid SYCL supported Intel GPU.
+static inline bool IsSYCLSupportedIntelGPUArch(SYCLSupportedIntelArchs Arch) {
+  return Arch >= SYCLSupportedIntelArchs::BDW &&
+ Arch <= SYCLSupportedIntelArchs::LNL_M;
+}
+
+// Check if the user provided value for --offload-arch is a valid
+// SYCL supported Intel AOT target.
+SYCLSupportedIntelArchs
+StringToOffloadArchSYCL(llvm::StringRef ArchNameAsString);
+
+// This is a mapping between the user provided --offload-arch value for Intel
+// GPU targets and the spir64_gen device name accepted by OCLOC (the Intel GPU
+// AOT compiler).
+llvm::StringRef mapIntelGPUArchName(llvm::StringRef ArchName);
+llvm::SmallString<64> getGenDeviceMacro(llvm::StringRef DeviceName);
+
+} // namespace clang
+
+#endif // LLVM_CLANG_BASIC_SYCL_H
diff --git a/clang/lib/Basic/CMakeLists.txt b/clang/lib/Basic/CMakeLists.txt
index 331dfbb3f4b67..be6d915e01b0a 100644
--- a/clang/lib/Basic/CMakeLists.txt
+++ b/clang/lib/Basic/CMakeLists.txt
@@ -90,6 +90,7 @@ add_clang_library(clangBasic
   SourceMgrAdapter.cpp
   Stack.cpp
   StackExhaustionHandler.cpp
+  SYCL.cpp
   TargetID.cpp
   TargetInfo.cpp
   Targets.cpp
diff --git a/clang/lib/Basic/SYCL.cpp b/clang/lib/Basic/SYCL.cpp
new file mode 100644
index 0..9ac5470cdbe5a

[clang] [Clang][SYCL] Add AOT compilation support for Intel GPUs in clang-sycl-linker (PR #133194)

2025-04-04 Thread Justin Cai via cfe-commits 

https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/133194

>From 8f22fbe1f6272beec61e62bfae72832d75b4f25b Mon Sep 17 00:00:00 2001
From: "Cai, Justin" 
Date: Fri, 14 Feb 2025 21:16:27 +
Subject: [PATCH 1/5] [SYCL] Add support AOT compilation support for Intel GPUs
 in clang-sycl-linker

---
 clang/include/clang/Basic/SYCL.h  | 131 ++
 clang/lib/Basic/CMakeLists.txt|   1 +
 clang/lib/Basic/SYCL.cpp  | 226 ++
 clang/test/Driver/clang-sycl-linker-test.cpp  |  36 +++
 .../clang-sycl-linker/ClangSYCLLinker.cpp | 112 -
 clang/tools/clang-sycl-linker/SYCLLinkOpts.td |   8 +
 6 files changed, 506 insertions(+), 8 deletions(-)
 create mode 100644 clang/include/clang/Basic/SYCL.h
 create mode 100644 clang/lib/Basic/SYCL.cpp

diff --git a/clang/include/clang/Basic/SYCL.h b/clang/include/clang/Basic/SYCL.h
new file mode 100644
index 0..c7cad37639b91
--- /dev/null
+++ b/clang/include/clang/Basic/SYCL.h
@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CLANG_BASIC_SYCL_H
+#define LLVM_CLANG_BASIC_SYCL_H
+
+#include "clang/Basic/Cuda.h"
+
+namespace llvm {
+class StringRef;
+template  class SmallString;
+} // namespace llvm
+
+namespace clang {
+// List of architectures (Intel CPUs and Intel GPUs)
+// that support SYCL offloading.
+enum class SYCLSupportedIntelArchs {
+  // Intel CPUs
+  UNKNOWN,
+  SKYLAKEAVX512,
+  COREAVX2,
+  COREI7AVX,
+  COREI7,
+  WESTMERE,
+  SANDYBRIDGE,
+  IVYBRIDGE,
+  BROADWELL,
+  COFFEELAKE,
+  ALDERLAKE,
+  SKYLAKE,
+  SKX,
+  CASCADELAKE,
+  ICELAKECLIENT,
+  ICELAKESERVER,
+  SAPPHIRERAPIDS,
+  GRANITERAPIDS,
+  // Intel GPUs
+  BDW,
+  SKL,
+  KBL,
+  CFL,
+  APL,
+  BXT,
+  GLK,
+  WHL,
+  AML,
+  CML,
+  ICLLP,
+  ICL,
+  EHL,
+  JSL,
+  TGLLP,
+  TGL,
+  RKL,
+  ADL_S,
+  RPL_S,
+  ADL_P,
+  ADL_N,
+  DG1,
+  ACM_G10,
+  DG2_G10,
+  ACM_G11,
+  DG2_G11,
+  ACM_G12,
+  DG2_G12,
+  PVC,
+  PVC_VG,
+  MTL_U,
+  MTL_S,
+  ARL_U,
+  ARL_S,
+  MTL_H,
+  ARL_H,
+  BMG_G21,
+  LNL_M,
+};
+
+// Check if the given Arch value is a Generic AMD GPU.
+// Currently GFX*_GENERIC AMD GPUs do not support SYCL offloading.
+// This list is used to filter out GFX*_GENERIC AMD GPUs in
+// `IsSYCLSupportedAMDGPUArch`.
+static inline bool IsAMDGenericGPUArch(OffloadArch Arch) {
+  return Arch == OffloadArch::GFX9_GENERIC ||
+ Arch == OffloadArch::GFX10_1_GENERIC ||
+ Arch == OffloadArch::GFX10_3_GENERIC ||
+ Arch == OffloadArch::GFX11_GENERIC ||
+ Arch == OffloadArch::GFX12_GENERIC;
+}
+
+// Check if the given Arch value is a valid SYCL supported AMD GPU.
+static inline bool IsSYCLSupportedAMDGPUArch(OffloadArch Arch) {
+  return Arch >= OffloadArch::GFX700 && Arch < OffloadArch::AMDGCNSPIRV &&
+ !IsAMDGenericGPUArch(Arch);
+}
+
+// Check if the given Arch value is a valid SYCL supported NVidia GPU.
+static inline bool IsSYCLSupportedNVidiaGPUArch(OffloadArch Arch) {
+  return Arch >= OffloadArch::SM_50 && Arch <= OffloadArch::SM_90a;
+}
+
+// Check if the given Arch value is a valid SYCL supported Intel CPU.
+static inline bool IsSYCLSupportedIntelCPUArch(SYCLSupportedIntelArchs Arch) {
+  return Arch >= SYCLSupportedIntelArchs::SKYLAKEAVX512 &&
+ Arch <= SYCLSupportedIntelArchs::GRANITERAPIDS;
+}
+
+// Check if the given Arch value is a valid SYCL supported Intel GPU.
+static inline bool IsSYCLSupportedIntelGPUArch(SYCLSupportedIntelArchs Arch) {
+  return Arch >= SYCLSupportedIntelArchs::BDW &&
+ Arch <= SYCLSupportedIntelArchs::LNL_M;
+}
+
+// Check if the user provided value for --offload-arch is a valid
+// SYCL supported Intel AOT target.
+SYCLSupportedIntelArchs
+StringToOffloadArchSYCL(llvm::StringRef ArchNameAsString);
+
+// This is a mapping between the user provided --offload-arch value for Intel
+// GPU targets and the spir64_gen device name accepted by OCLOC (the Intel GPU
+// AOT compiler).
+llvm::StringRef mapIntelGPUArchName(llvm::StringRef ArchName);
+llvm::SmallString<64> getGenDeviceMacro(llvm::StringRef DeviceName);
+
+} // namespace clang
+
+#endif // LLVM_CLANG_BASIC_SYCL_H
diff --git a/clang/lib/Basic/CMakeLists.txt b/clang/lib/Basic/CMakeLists.txt
index 331dfbb3f4b67..be6d915e01b0a 100644
--- a/clang/lib/Basic/CMakeLists.txt
+++ b/clang/lib/Basic/CMakeLists.txt
@@ -90,6 +90,7 @@ add_clang_library(clangBasic
   SourceMgrAdapter.cpp
   Stack.cpp
   StackExhaustionHandler.cpp
+  SYCL.cpp
   TargetID.cpp
   TargetInfo.cpp
   Targets.cpp
diff --git a/clang/lib/Basic/SYCL.cpp b/clang/lib/Basic/SYCL.cpp
new file mode 100644
index 0..9ac5470cdbe5a

[clang] [Clang][SYCL] Add AOT compilation support for Intel GPUs in clang-sycl-linker (PR #133194)

2025-05-06 Thread Justin Cai via cfe-commits 


@@ -338,6 +382,87 @@ static Error runSPIRVCodeGen(StringRef File, const ArgList 
&Args,
   return Error::success();
 }
 
+/// Run AOT compilation for Intel CPU.
+/// Calls opencl-aot tool to generate device code for Intel CPU backend.

jzc wrote:

Changed to `Calls opencl-aot tool to generate device code for the Intel OpenCL 
CPU Runtime` / `Calls ocloc tool to generate device code for the Intel Graphics 
Compute Runtime`.

https://github.com/llvm/llvm-project/pull/133194
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[clang] [Clang][SYCL] Add AOT compilation support for Intel GPUs in clang-sycl-linker (PR #133194)

2025-05-06 Thread Justin Cai via cfe-commits 


@@ -440,9 +570,15 @@ int main(int argc, char **argv) {
   DryRun = Args.hasArg(OPT_dry_run);
   SaveTemps = Args.hasArg(OPT_save_temps);
 
-  OutputFile = "a.out";
-  if (Args.hasArg(OPT_o))
-OutputFile = Args.getLastArgValue(OPT_o);
+  IsAOTCompileNeeded = IsIntelOffloadArch(
+  StringToOffloadArch(Args.getLastArgValue(OPT_arch_EQ)));
+
+  if (!Args.hasArg(OPT_o))

jzc wrote:

I think for the AOT compilation functionality these changes are not strictly 
required, so I could remove them if we want to. For the `OPT_o` check, I 
believe there was an earlier review comment noting that the default `a.out` 
name conflicts with clang's default `a.out` name, so I made `OPT_o` mandatory. 
For `OPT_triple_eq`, we use it throughout `clang-sycl-linker` assuming it is 
nonempty.

https://github.com/llvm/llvm-project/pull/133194
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[clang] [clang-sycl-linker] Add AOT compilation support for Intel GPUs/CPUs (PR #133194)

2025-05-06 Thread Justin Cai via cfe-commits 

https://github.com/jzc edited https://github.com/llvm/llvm-project/pull/133194
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