from:"Jonathan Thackray via cfe\-commits"

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray created 
https://github.com/llvm/llvm-project/pull/74822

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52


>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52
---
 clang/docs/ReleaseNotes.rst|  1 +
 clang/test/CodeGen/arm-target-features.c   |  3 +++
 clang/test/Driver/arm-cortex-cpus-2.c  |  3 +++
 clang/test/Misc/target-invalid-cpu-note.c  |  2 +-
 llvm/docs/ReleaseNotes.rst |  2 +-
 llvm/include/llvm/TargetParser/ARMTargetParser.def |  3 +++
 llvm/lib/Target/ARM/ARM.td | 11 +++
 llvm/lib/Target/ARM/ARMSubtarget.cpp   |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h |  1 +
 llvm/lib/TargetParser/Host.cpp |  1 +
 llvm/unittests/TargetParser/TargetParserTest.cpp   |  8 +++-
 11 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c044658197139..6f3b6efbfe08c0 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc1..ad4bfd45c408b5 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f3..4bf2b3a50412d0 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f2..f921c4605bb976 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
corte

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/74822

>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/2] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52
---
 clang/docs/ReleaseNotes.rst|  1 +
 clang/test/CodeGen/arm-target-features.c   |  3 +++
 clang/test/Driver/arm-cortex-cpus-2.c  |  3 +++
 clang/test/Misc/target-invalid-cpu-note.c  |  2 +-
 llvm/docs/ReleaseNotes.rst |  2 +-
 llvm/include/llvm/TargetParser/ARMTargetParser.def |  3 +++
 llvm/lib/Target/ARM/ARM.td | 11 +++
 llvm/lib/Target/ARM/ARMSubtarget.cpp   |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h |  1 +
 llvm/lib/TargetParser/Host.cpp |  1 +
 llvm/unittests/TargetParser/TargetParserTest.cpp   |  8 +++-
 11 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c04465819713..6f3b6efbfe08c 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc..ad4bfd45c408b 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f..4bf2b3a50412d 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f..f921c4605bb97 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-a32, cortex-a35, c

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/74822

>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/3] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52
---
 clang/docs/ReleaseNotes.rst|  1 +
 clang/test/CodeGen/arm-target-features.c   |  3 +++
 clang/test/Driver/arm-cortex-cpus-2.c  |  3 +++
 clang/test/Misc/target-invalid-cpu-note.c  |  2 +-
 llvm/docs/ReleaseNotes.rst |  2 +-
 llvm/include/llvm/TargetParser/ARMTargetParser.def |  3 +++
 llvm/lib/Target/ARM/ARM.td | 11 +++
 llvm/lib/Target/ARM/ARMSubtarget.cpp   |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h |  1 +
 llvm/lib/TargetParser/Host.cpp |  1 +
 llvm/unittests/TargetParser/TargetParserTest.cpp   |  8 +++-
 11 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c04465819713..6f3b6efbfe08c 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc..ad4bfd45c408b 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f..4bf2b3a50412d 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f..f921c4605bb97 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-a32, cortex-a35, c

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits



@@ -102,7 +102,7 @@ Changes to the AMDGPU Backend
 
 * Implemented :ref:`llvm.get.rounding `
 
-* Added support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs.
+* Added support for Cortex-A520, Cortex-A720, Cortex-X4 and Cortex-M52 CPUs.

jthackray wrote:

Thanks, David. Good spot. I added those new CPUs a month ago, and somehow 
missed they were in the wrong section. Now fixed.

https://github.com/llvm/llvm-project/pull/74822
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[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits


jthackray wrote:

> Going by the page (didn't see a link to a manual, maybe I missed it), MVE and 
> FPU are optional.
> 
> "Optional Helium technology (M-profile Vector Extension) supporting up to:" 
> "Optional FPU with support for half precision (fp16), single precision (fp32) 
> and double precision (fp64) floating-point operations."
> 
> Is this following a pattern from previous CPUs where these things are 
> optional, but users are expected to pass `+nomve` etc. to disable them? (I 
> don't disagree with that, just want to keep it consistent)

Yes, that's correct. We enable all mandatory and optional architecture 
extensions, with the exception of crypto.

https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits



@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).

jthackray wrote:

Sure. Something like this?

```
+  --target=arm
+ * Arm Cortex-M52 (cortex-m52).
+
+  --target=aarch64
+ * Arm Cortex-A520 (cortex-a520).
+ * Arm Cortex-A720 (cortex-a720).
+ * Arm Cortex-X4 (cortex-x4).
```

https://github.com/llvm/llvm-project/pull/74822
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[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/74822

>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/4] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52
---
 clang/docs/ReleaseNotes.rst|  1 +
 clang/test/CodeGen/arm-target-features.c   |  3 +++
 clang/test/Driver/arm-cortex-cpus-2.c  |  3 +++
 clang/test/Misc/target-invalid-cpu-note.c  |  2 +-
 llvm/docs/ReleaseNotes.rst |  2 +-
 llvm/include/llvm/TargetParser/ARMTargetParser.def |  3 +++
 llvm/lib/Target/ARM/ARM.td | 11 +++
 llvm/lib/Target/ARM/ARMSubtarget.cpp   |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h |  1 +
 llvm/lib/TargetParser/Host.cpp |  1 +
 llvm/unittests/TargetParser/TargetParserTest.cpp   |  8 +++-
 11 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c044658197139..6f3b6efbfe08c0 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc1..ad4bfd45c408b5 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f3..4bf2b3a50412d0 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f2..f921c4605bb976 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-a32, corte

[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/74822

>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/5] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52
---
 clang/docs/ReleaseNotes.rst|  1 +
 clang/test/CodeGen/arm-target-features.c   |  3 +++
 clang/test/Driver/arm-cortex-cpus-2.c  |  3 +++
 clang/test/Misc/target-invalid-cpu-note.c  |  2 +-
 llvm/docs/ReleaseNotes.rst |  2 +-
 llvm/include/llvm/TargetParser/ARMTargetParser.def |  3 +++
 llvm/lib/Target/ARM/ARM.td | 11 +++
 llvm/lib/Target/ARM/ARMSubtarget.cpp   |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h |  1 +
 llvm/lib/TargetParser/Host.cpp |  1 +
 llvm/unittests/TargetParser/TargetParserTest.cpp   |  8 +++-
 11 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c044658197139..6f3b6efbfe08c0 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc1..ad4bfd45c408b5 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f3..4bf2b3a50412d0 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f2..f921c4605bb976 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-a32, corte

[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits



@@ -896,9 +896,13 @@ Arm and AArch64 Support
 
   Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
 
-  * Arm Cortex-A520 (cortex-a520).
-  * Arm Cortex-A720 (cortex-a720).
-  * Arm Cortex-X4 (cortex-x4).
+  --target=arm
+ * Arm Cortex-M52 (cortex-m52).
+
+  --target=aarch64
+ * Arm Cortex-A520 (cortex-a520).
+ * Arm Cortex-A720 (cortex-a720).
+ * Arm Cortex-X4 (cortex-x4).

jthackray wrote:

Thanks. I've adjusted the formatting so they render correctly as two lists.

https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray closed 
https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [AArch64] Correctly mark Neoverse-N2 as an Armv9.0a core (PR #75055)

2023-12-11 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray created 
https://github.com/llvm/llvm-project/pull/75055

Neoverse-N2 was incorrectly marked as an Armv8.5a core. This has been
changed to an Armv9.0a core. However, crypto options are not enabled
by default for Armv9 cores, so `-mcpu=neoverse-n2+crypto` is required
to enable crypto for this core.


>From f04fea5a67c37a7ae33b611adb04733893563342 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Mon, 11 Dec 2023 14:30:46 +
Subject: [PATCH] [AArch64] Correctly mark Neoverse-N2 as an Armv9.0a core

Neoverse-N2 was incorrectly marked as an Armv8.5a core. This has been
changed to an Armv9.0a core. However, crypto options are not enabled
by default for Armv9 cores, so `-mcpu=neoverse-n2+crypto` is required
to enable crypto for this core.
---
 clang/test/Driver/arm-cortex-cpus-2.c|  2 +-
 llvm/docs/ReleaseNotes.rst   |  5 +
 llvm/include/llvm/TargetParser/AArch64TargetParser.h |  5 ++---
 llvm/include/llvm/TargetParser/ARMTargetParser.def   |  2 +-
 llvm/lib/Target/AArch64/AArch64.td   |  4 ++--
 llvm/lib/Target/ARM/ARM.td   |  2 +-
 llvm/test/CodeGen/AArch64/misched-fusion-aes.ll  |  1 -
 llvm/unittests/TargetParser/TargetParserTest.cpp | 10 --
 8 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 4bf2b3a50412d..c322303d22786 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -566,7 +566,7 @@
 // CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
 
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
-// CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
+// CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv9a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
 // == Check whether -mcpu accepts mixed-case values.
 // RUN: %clang -target arm-linux-gnueabi -mcpu=Cortex-a5 -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 6b70146efe824..707d422342b2b 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -94,6 +94,11 @@ Changes to the AArch64 Backend
 
 * Added support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs.
 
+* Neoverse-N2 was incorrectly marked as an Armv8.5a core. This has been
+  changed to an Armv9.0a core. However, crypto options are not enabled
+  by default for Armv9 cores, so `-mcpu=neoverse-n2+crypto` is required
+  to enable crypto for this core.
+
 Changes to the AMDGPU Backend
 -
 
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h 
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 17cafd146b0e7..56c32fae712ce 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -536,10 +536,9 @@ inline constexpr CpuInfo CpuInfos[] = {
  {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
   AArch64::AEK_FP16, AArch64::AEK_PROFILE, AArch64::AEK_RCPC,
   AArch64::AEK_SSBS}))},
-{"neoverse-n2", ARMV8_5A,
+{"neoverse-n2", ARMV9A,
  (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
-  AArch64::AEK_SM4, AArch64::AEK_BF16, AArch64::AEK_DOTPROD,
+ {AArch64::AEK_BF16, AArch64::AEK_DOTPROD,
   AArch64::AEK_FP16, AArch64::AEK_I8MM, AArch64::AEK_MTE,
   AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_SVE,
   AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM}))},
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def 
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 558b6f127de3f..c520ab898cb90 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -340,7 +340,7 @@ ARM_CPU_NAME("cortex-x1c", ARMV8_2A, 
FK_CRYPTO_NEON_FP_ARMV8, false,
  (ARM::AEK_FP16 | ARM::AEK_DOTPROD))
 ARM_CPU_NAME("neoverse-n1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
  (ARM::AEK_FP16 | ARM::AEK_DOTPROD))
-ARM_CPU_NAME("neoverse-n2", ARMV8_5A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ARM_CPU_NAME("neoverse-n2", ARMV9A, FK_NEON_FP_ARMV8, false,
  (ARM::AEK_BF16 | ARM::AEK_DOTPROD | ARM::AEK_I8MM | ARM::AEK_RAS |
   ARM::AEK_SB))
 ARM_CPU_NAME("neoverse-v1", ARMV8_4A, FK_CRYPTO_NEON_FP_ARMV8, false,
diff --git a/llvm/lib/Target/AArch64/AArch64.td 
b/llvm/lib/Target/AArch64/AArch64.td
index ff256c9a8ccdf..c600bcaab2b3e 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -1480,9 +1480,9 @@ def ProcessorFeatures {
FeatureFPARMv8, FeatureFullFP16, 
FeatureNEON,

[llvm] [clang] [AArch64] Correctly mark Neoverse N2 as an Armv9.0a core (PR #75055)

2023-12-11 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray edited 
https://github.com/llvm/llvm-project/pull/75055
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[llvm] [clang] [AArch64] Correctly mark Neoverse N2 as an Armv9.0a core (PR #75055)

2023-12-11 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray edited 
https://github.com/llvm/llvm-project/pull/75055
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[llvm] [clang] [AArch64] Correctly mark Neoverse N2 as an Armv9.0a core (PR #75055)

2023-12-11 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/75055

>From f04fea5a67c37a7ae33b611adb04733893563342 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Mon, 11 Dec 2023 14:30:46 +
Subject: [PATCH 1/2] [AArch64] Correctly mark Neoverse-N2 as an Armv9.0a core

Neoverse-N2 was incorrectly marked as an Armv8.5a core. This has been
changed to an Armv9.0a core. However, crypto options are not enabled
by default for Armv9 cores, so `-mcpu=neoverse-n2+crypto` is required
to enable crypto for this core.
---
 clang/test/Driver/arm-cortex-cpus-2.c|  2 +-
 llvm/docs/ReleaseNotes.rst   |  5 +
 llvm/include/llvm/TargetParser/AArch64TargetParser.h |  5 ++---
 llvm/include/llvm/TargetParser/ARMTargetParser.def   |  2 +-
 llvm/lib/Target/AArch64/AArch64.td   |  4 ++--
 llvm/lib/Target/ARM/ARM.td   |  2 +-
 llvm/test/CodeGen/AArch64/misched-fusion-aes.ll  |  1 -
 llvm/unittests/TargetParser/TargetParserTest.cpp | 10 --
 8 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 4bf2b3a50412d..c322303d22786 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -566,7 +566,7 @@
 // CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
 
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
-// CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
+// CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv9a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
 // == Check whether -mcpu accepts mixed-case values.
 // RUN: %clang -target arm-linux-gnueabi -mcpu=Cortex-a5 -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 6b70146efe824..707d422342b2b 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -94,6 +94,11 @@ Changes to the AArch64 Backend
 
 * Added support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs.
 
+* Neoverse-N2 was incorrectly marked as an Armv8.5a core. This has been
+  changed to an Armv9.0a core. However, crypto options are not enabled
+  by default for Armv9 cores, so `-mcpu=neoverse-n2+crypto` is required
+  to enable crypto for this core.
+
 Changes to the AMDGPU Backend
 -
 
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h 
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 17cafd146b0e7..56c32fae712ce 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -536,10 +536,9 @@ inline constexpr CpuInfo CpuInfos[] = {
  {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
   AArch64::AEK_FP16, AArch64::AEK_PROFILE, AArch64::AEK_RCPC,
   AArch64::AEK_SSBS}))},
-{"neoverse-n2", ARMV8_5A,
+{"neoverse-n2", ARMV9A,
  (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
-  AArch64::AEK_SM4, AArch64::AEK_BF16, AArch64::AEK_DOTPROD,
+ {AArch64::AEK_BF16, AArch64::AEK_DOTPROD,
   AArch64::AEK_FP16, AArch64::AEK_I8MM, AArch64::AEK_MTE,
   AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_SVE,
   AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM}))},
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def 
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 558b6f127de3f..c520ab898cb90 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -340,7 +340,7 @@ ARM_CPU_NAME("cortex-x1c", ARMV8_2A, 
FK_CRYPTO_NEON_FP_ARMV8, false,
  (ARM::AEK_FP16 | ARM::AEK_DOTPROD))
 ARM_CPU_NAME("neoverse-n1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
  (ARM::AEK_FP16 | ARM::AEK_DOTPROD))
-ARM_CPU_NAME("neoverse-n2", ARMV8_5A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ARM_CPU_NAME("neoverse-n2", ARMV9A, FK_NEON_FP_ARMV8, false,
  (ARM::AEK_BF16 | ARM::AEK_DOTPROD | ARM::AEK_I8MM | ARM::AEK_RAS |
   ARM::AEK_SB))
 ARM_CPU_NAME("neoverse-v1", ARMV8_4A, FK_CRYPTO_NEON_FP_ARMV8, false,
diff --git a/llvm/lib/Target/AArch64/AArch64.td 
b/llvm/lib/Target/AArch64/AArch64.td
index ff256c9a8ccdf..c600bcaab2b3e 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -1480,9 +1480,9 @@ def ProcessorFeatures {
FeatureFPARMv8, FeatureFullFP16, 
FeatureNEON,
FeatureRCPC, FeatureSPE, FeatureSSBS,
FeaturePerfMon];
-  list NeoverseN2 = [HasV8_5aOps, FeatureBF16, FeatureETE,
+  list NeoverseN2 = [HasV9_0aOps, FeatureBF16, Fea

[llvm] [clang] [AArch64] Correctly mark Neoverse N2 as an Armv9.0a core (PR #75055)

2023-12-11 Thread Jonathan Thackray via cfe-commits



@@ -94,6 +94,11 @@ Changes to the AArch64 Backend
 
 * Added support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs.
 
+* Neoverse-N2 was incorrectly marked as an Armv8.5a core. This has been
+  changed to an Armv9.0a core. However, crypto options are not enabled
+  by default for Armv9 cores, so `-mcpu=neoverse-n2+crypto` is required

jthackray wrote:

Thanks for your comments. I've adjusted the wording in another commit to:

```
 * Neoverse-N2 was incorrectly marked as an Armv8.5a core. This has been
   changed to an Armv9.0a core. However, crypto options are not enabled
   by default for Armv9 cores, so `-mcpu=neoverse-n2+crypto` is now required
   to enable crypto for this core. As far as the compiler is concerned,
   Armv9.0a has the same features enabled as Armv8.5a, with the exception
   of crypto.
```

https://github.com/llvm/llvm-project/pull/75055
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[llvm] [clang] [AArch64] Correctly mark Neoverse N2 as an Armv9.0a core (PR #75055)

2023-12-11 Thread Jonathan Thackray via cfe-commits


jthackray wrote:

> Looking good. Is there a document to reference in the commit message?

Sure, I can put a link to the Technical Reference Manual

https://github.com/llvm/llvm-project/pull/75055
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[llvm] [clang] [AArch64] Correctly mark Neoverse N2 as an Armv9.0a core (PR #75055)

2023-12-11 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray edited 
https://github.com/llvm/llvm-project/pull/75055
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[llvm] [clang] [AArch64] Correctly mark Neoverse N2 as an Armv9.0a core (PR #75055)

2023-12-11 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray closed 
https://github.com/llvm/llvm-project/pull/75055
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[clang] [llvm] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)

2023-11-15 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray created 
https://github.com/llvm/llvm-project/pull/72395

Cortex-A520, Cortex-A720 and Cortex-X4 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520:
   https://developer.arm.com/documentation/102517/latest/

Technical Reference Manual for Cortex-A720:
   https://developer.arm.com/documentation/102530/latest/

Technical Reference Manual for Cortex-X4:
   https://developer.arm.com/documentation/102484/latest/

Patch co-authored by: Sivan Shani 


>From 2656af94138e61452f34b1a599fe1d54eee2aee9 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Fri, 10 Nov 2023 15:37:08 +
Subject: [PATCH] [AArch64] Add support for Cortex-A520, Cortex-A720 and
 Cortex-X4 CPUs

Cortex-A520, Cortex-A720 and Cortex-X4 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520:
   https://developer.arm.com/documentation/102517/latest/

Technical Reference Manual for Cortex-A720:
   https://developer.arm.com/documentation/102530/latest/

Technical Reference Manual for Cortex-X4:
   https://developer.arm.com/documentation/102484/latest/

Patch co-authored by: Sivan Shani 
---
 clang/docs/ReleaseNotes.rst   |  6 +++
 clang/test/Driver/aarch64-mcpu.c  |  6 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +-
 llvm/docs/ReleaseNotes.rst|  2 +
 .../llvm/TargetParser/AArch64TargetParser.h   | 17 +++
 llvm/lib/Target/AArch64/AArch64.td| 47 +++
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  3 ++
 llvm/lib/Target/AArch64/AArch64Subtarget.h|  3 ++
 llvm/lib/TargetParser/Host.cpp|  3 ++
 .../TargetParser/TargetParserTest.cpp | 40 +++-
 10 files changed, 128 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index ed1a978b5382d71..31ebe89fb0cafd6 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -760,6 +760,12 @@ Arm and AArch64 Support
 
 - New AArch64 asm constraints have been added for r8-r11(Uci) and r12-r15(Ucj).
 
+  Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
+
+  * Arm Cortex-A520 (cortex-a520).
+  * Arm Cortex-A720 (cortex-a720).
+  * Arm Cortex-X4 (cortex-x4).
+
 Android Support
 ^^^
 
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 321d3a739b35350..0006dcda4e3b219 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -44,12 +44,16 @@
 // CORTEXX1C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x1c"
 // RUN: %clang --target=aarch64 -mcpu=cortex-x3 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXX3 %s
 // CORTEXX3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x3"
+// RUN: %clang --target aarch64 -mcpu=cortex-x4 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X4 %s
+// CORTEX-X4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x4"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXA78 %s
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
 // CORTEX-A78C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a78c"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a715  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A715 %s
 // CORTEX-A715: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a715"
+// RUN: %clang --target aarch64 -mcpu=cortex-a720  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A720 %s
+// CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
@@ -62,6 +66,8 @@
 // NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n2"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-512tvb -### -c %s 2>&1 | 
FileCheck -check-prefix=NEOVERSE-512TVB %s
 // NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-512tvb"
+// RUN: %clang --target aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A520 %s
+// CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a520"
 
 // RUN: %clang --target=aarch64 -mcpu=cortex-r82  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXR82 %s
 // CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 8e91eb4c62dd259..25ff51e071b69b3 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-i

[clang] [llvm] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)

2023-11-15 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/72395

>From 07b24207d100ac7d5deac76543c01710b8cab79e Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Fri, 10 Nov 2023 15:37:08 +
Subject: [PATCH] [AArch64] Add support for Cortex-A520, Cortex-A720 and
 Cortex-X4 CPUs

Cortex-A520, Cortex-A720 and Cortex-X4 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520:
   https://developer.arm.com/documentation/102517/latest/

Technical Reference Manual for Cortex-A720:
   https://developer.arm.com/documentation/102530/latest/

Technical Reference Manual for Cortex-X4:
   https://developer.arm.com/documentation/102484/latest/

Patch co-authored by: Sivan Shani 
---
 clang/docs/ReleaseNotes.rst   |  6 +++
 clang/test/Driver/aarch64-mcpu.c  |  6 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +-
 llvm/docs/ReleaseNotes.rst|  2 +
 .../llvm/TargetParser/AArch64TargetParser.h   | 17 +++
 llvm/lib/Target/AArch64/AArch64.td| 47 +++
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  3 ++
 llvm/lib/Target/AArch64/AArch64Subtarget.h|  3 ++
 llvm/lib/TargetParser/Host.cpp|  3 ++
 .../TargetParser/TargetParserTest.cpp | 40 +++-
 10 files changed, 128 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index ed1a978b5382d71..31ebe89fb0cafd6 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -760,6 +760,12 @@ Arm and AArch64 Support
 
 - New AArch64 asm constraints have been added for r8-r11(Uci) and r12-r15(Ucj).
 
+  Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
+
+  * Arm Cortex-A520 (cortex-a520).
+  * Arm Cortex-A720 (cortex-a720).
+  * Arm Cortex-X4 (cortex-x4).
+
 Android Support
 ^^^
 
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 321d3a739b35350..511482a420da268 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -44,12 +44,16 @@
 // CORTEXX1C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x1c"
 // RUN: %clang --target=aarch64 -mcpu=cortex-x3 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXX3 %s
 // CORTEXX3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x3"
+// RUN: %clang --target=aarch64 -mcpu=cortex-x4 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X4 %s
+// CORTEX-X4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x4"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXA78 %s
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
 // CORTEX-A78C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a78c"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a715  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A715 %s
 // CORTEX-A715: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a715"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a720  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A720 %s
+// CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
@@ -62,6 +66,8 @@
 // NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n2"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-512tvb -### -c %s 2>&1 | 
FileCheck -check-prefix=NEOVERSE-512TVB %s
 // NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-512tvb"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A520 %s
+// CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a520"
 
 // RUN: %clang --target=aarch64 -mcpu=cortex-r82  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXR82 %s
 // CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 8e91eb4c62dd259..25ff51e071b69b3 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, 
cortex-a72, cortex-a73, cortex-a75, cortex-

[llvm] [clang] [AArch64] Introduce the Armv9.5-A architecture version (PR #72392)

2023-11-16 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/72392
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[clang] [llvm] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)

2023-11-16 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/72395

>From 07b24207d100ac7d5deac76543c01710b8cab79e Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Fri, 10 Nov 2023 15:37:08 +
Subject: [PATCH 1/2] [AArch64] Add support for Cortex-A520, Cortex-A720 and
 Cortex-X4 CPUs

Cortex-A520, Cortex-A720 and Cortex-X4 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520:
   https://developer.arm.com/documentation/102517/latest/

Technical Reference Manual for Cortex-A720:
   https://developer.arm.com/documentation/102530/latest/

Technical Reference Manual for Cortex-X4:
   https://developer.arm.com/documentation/102484/latest/

Patch co-authored by: Sivan Shani 
---
 clang/docs/ReleaseNotes.rst   |  6 +++
 clang/test/Driver/aarch64-mcpu.c  |  6 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +-
 llvm/docs/ReleaseNotes.rst|  2 +
 .../llvm/TargetParser/AArch64TargetParser.h   | 17 +++
 llvm/lib/Target/AArch64/AArch64.td| 47 +++
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  3 ++
 llvm/lib/Target/AArch64/AArch64Subtarget.h|  3 ++
 llvm/lib/TargetParser/Host.cpp|  3 ++
 .../TargetParser/TargetParserTest.cpp | 40 +++-
 10 files changed, 128 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index ed1a978b5382d71..31ebe89fb0cafd6 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -760,6 +760,12 @@ Arm and AArch64 Support
 
 - New AArch64 asm constraints have been added for r8-r11(Uci) and r12-r15(Ucj).
 
+  Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
+
+  * Arm Cortex-A520 (cortex-a520).
+  * Arm Cortex-A720 (cortex-a720).
+  * Arm Cortex-X4 (cortex-x4).
+
 Android Support
 ^^^
 
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 321d3a739b35350..511482a420da268 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -44,12 +44,16 @@
 // CORTEXX1C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x1c"
 // RUN: %clang --target=aarch64 -mcpu=cortex-x3 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXX3 %s
 // CORTEXX3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x3"
+// RUN: %clang --target=aarch64 -mcpu=cortex-x4 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X4 %s
+// CORTEX-X4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x4"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXA78 %s
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
 // CORTEX-A78C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a78c"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a715  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A715 %s
 // CORTEX-A715: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a715"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a720  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A720 %s
+// CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
@@ -62,6 +66,8 @@
 // NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n2"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-512tvb -### -c %s 2>&1 | 
FileCheck -check-prefix=NEOVERSE-512TVB %s
 // NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-512tvb"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A520 %s
+// CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a520"
 
 // RUN: %clang --target=aarch64 -mcpu=cortex-r82  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXR82 %s
 // CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 8e91eb4c62dd259..25ff51e071b69b3 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, 
cortex-a72, cortex-a73, cortex-a75, cor

[clang] [llvm] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)

2023-11-16 Thread Jonathan Thackray via cfe-commits



@@ -1372,6 +1408,11 @@ def ProcessorFeatures {
  FeatureSPE, FeatureBF16, FeatureMatMulInt8,
  FeatureMTE, FeatureSVE2BitPerm, 
FeatureFullFP16,
  FeatureFP16FML];
+  list X4 =   [HasV9_2aOps, FeatureSVE, FeatureNEON,

jthackray wrote:

Thanks, good spot. Superfluous defines removed, and FEAT_SPEv1p2 added to 
Cortex-A720 and Cortex-X4.

https://github.com/llvm/llvm-project/pull/72395
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[clang] [llvm] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)

2023-11-16 Thread Jonathan Thackray via cfe-commits



@@ -1325,6 +1352,10 @@ def ProcessorFeatures {
  FeatureMatMulInt8, FeatureBF16, FeatureAM,
  FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
  FeatureFP16FML];
+  list A520 = [HasV9_2aOps, FeatureNEON, FeaturePerfMon,

jthackray wrote:

Thanks. Superfluous defines removed.

https://github.com/llvm/llvm-project/pull/72395
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[clang] [llvm] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)

2023-11-16 Thread Jonathan Thackray via cfe-commits



@@ -1351,6 +1382,11 @@ def ProcessorFeatures {
  FeatureFP16FML, FeatureSVE, FeatureTRBE,
  FeatureSVE2BitPerm, FeatureBF16, FeatureETE,
  FeaturePerfMon, FeatureMatMulInt8, 
FeatureSPE];
+  list A720 = [HasV9_2aOps, FeatureNEON, FeatureMTE,

jthackray wrote:

Thanks. Superfluous defines removed, and erroneous FEAT_TME excised.

https://github.com/llvm/llvm-project/pull/72395
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[clang] [llvm] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)

2023-11-16 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/72395

>From 07b24207d100ac7d5deac76543c01710b8cab79e Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Fri, 10 Nov 2023 15:37:08 +
Subject: [PATCH 1/2] [AArch64] Add support for Cortex-A520, Cortex-A720 and
 Cortex-X4 CPUs

Cortex-A520, Cortex-A720 and Cortex-X4 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520:
   https://developer.arm.com/documentation/102517/latest/

Technical Reference Manual for Cortex-A720:
   https://developer.arm.com/documentation/102530/latest/

Technical Reference Manual for Cortex-X4:
   https://developer.arm.com/documentation/102484/latest/

Patch co-authored by: Sivan Shani 
---
 clang/docs/ReleaseNotes.rst   |  6 +++
 clang/test/Driver/aarch64-mcpu.c  |  6 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +-
 llvm/docs/ReleaseNotes.rst|  2 +
 .../llvm/TargetParser/AArch64TargetParser.h   | 17 +++
 llvm/lib/Target/AArch64/AArch64.td| 47 +++
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  3 ++
 llvm/lib/Target/AArch64/AArch64Subtarget.h|  3 ++
 llvm/lib/TargetParser/Host.cpp|  3 ++
 .../TargetParser/TargetParserTest.cpp | 40 +++-
 10 files changed, 128 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index ed1a978b5382d71..31ebe89fb0cafd6 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -760,6 +760,12 @@ Arm and AArch64 Support
 
 - New AArch64 asm constraints have been added for r8-r11(Uci) and r12-r15(Ucj).
 
+  Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
+
+  * Arm Cortex-A520 (cortex-a520).
+  * Arm Cortex-A720 (cortex-a720).
+  * Arm Cortex-X4 (cortex-x4).
+
 Android Support
 ^^^
 
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 321d3a739b35350..511482a420da268 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -44,12 +44,16 @@
 // CORTEXX1C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x1c"
 // RUN: %clang --target=aarch64 -mcpu=cortex-x3 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXX3 %s
 // CORTEXX3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x3"
+// RUN: %clang --target=aarch64 -mcpu=cortex-x4 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X4 %s
+// CORTEX-X4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x4"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXA78 %s
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
 // CORTEX-A78C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a78c"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a715  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A715 %s
 // CORTEX-A715: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a715"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a720  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A720 %s
+// CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
@@ -62,6 +66,8 @@
 // NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n2"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-512tvb -### -c %s 2>&1 | 
FileCheck -check-prefix=NEOVERSE-512TVB %s
 // NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-512tvb"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A520 %s
+// CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a520"
 
 // RUN: %clang --target=aarch64 -mcpu=cortex-r82  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXR82 %s
 // CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 8e91eb4c62dd259..25ff51e071b69b3 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, 
cortex-a72, cortex-a73, cortex-a75, cor

[llvm] [clang] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)

2023-11-16 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/72395

>From 07b24207d100ac7d5deac76543c01710b8cab79e Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Fri, 10 Nov 2023 15:37:08 +
Subject: [PATCH 1/3] [AArch64] Add support for Cortex-A520, Cortex-A720 and
 Cortex-X4 CPUs

Cortex-A520, Cortex-A720 and Cortex-X4 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520:
   https://developer.arm.com/documentation/102517/latest/

Technical Reference Manual for Cortex-A720:
   https://developer.arm.com/documentation/102530/latest/

Technical Reference Manual for Cortex-X4:
   https://developer.arm.com/documentation/102484/latest/

Patch co-authored by: Sivan Shani 
---
 clang/docs/ReleaseNotes.rst   |  6 +++
 clang/test/Driver/aarch64-mcpu.c  |  6 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +-
 llvm/docs/ReleaseNotes.rst|  2 +
 .../llvm/TargetParser/AArch64TargetParser.h   | 17 +++
 llvm/lib/Target/AArch64/AArch64.td| 47 +++
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  3 ++
 llvm/lib/Target/AArch64/AArch64Subtarget.h|  3 ++
 llvm/lib/TargetParser/Host.cpp|  3 ++
 .../TargetParser/TargetParserTest.cpp | 40 +++-
 10 files changed, 128 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index ed1a978b5382d71..31ebe89fb0cafd6 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -760,6 +760,12 @@ Arm and AArch64 Support
 
 - New AArch64 asm constraints have been added for r8-r11(Uci) and r12-r15(Ucj).
 
+  Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
+
+  * Arm Cortex-A520 (cortex-a520).
+  * Arm Cortex-A720 (cortex-a720).
+  * Arm Cortex-X4 (cortex-x4).
+
 Android Support
 ^^^
 
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 321d3a739b35350..511482a420da268 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -44,12 +44,16 @@
 // CORTEXX1C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x1c"
 // RUN: %clang --target=aarch64 -mcpu=cortex-x3 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXX3 %s
 // CORTEXX3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x3"
+// RUN: %clang --target=aarch64 -mcpu=cortex-x4 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X4 %s
+// CORTEX-X4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x4"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXA78 %s
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
 // CORTEX-A78C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a78c"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a715  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A715 %s
 // CORTEX-A715: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a715"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a720  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A720 %s
+// CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
@@ -62,6 +66,8 @@
 // NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n2"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-512tvb -### -c %s 2>&1 | 
FileCheck -check-prefix=NEOVERSE-512TVB %s
 // NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-512tvb"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A520 %s
+// CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a520"
 
 // RUN: %clang --target=aarch64 -mcpu=cortex-r82  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXR82 %s
 // CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 8e91eb4c62dd259..25ff51e071b69b3 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, 
cortex-a72, cortex-a73, cortex-a75, cor

[clang] [llvm] [AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (PR #72395)

2023-11-16 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray closed 
https://github.com/llvm/llvm-project/pull/72395
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[llvm] [clang] [AArch64] Support for 9.5-A PAuthLR (PR #75947)

2023-12-20 Thread Jonathan Thackray via cfe-commits


jthackray wrote:

Long diff! Looks good to me, great work.

https://github.com/llvm/llvm-project/pull/75947
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[llvm] [clang] [AArch64] Support for 9.5-A PAuthLR (PR #75947)

2023-12-20 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

+2

https://github.com/llvm/llvm-project/pull/75947
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[clang] [llvm] [AArch64] Assembly support for the Checked Pointer Arithmetic Extension (PR #73777)

2023-11-29 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

Great stuff. Looks good to me.

https://github.com/llvm/llvm-project/pull/73777
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[llvm] [clang] [AArch64] Assembly support for the Armv9.5-A Memory System Extensions (PR #76237)

2023-12-22 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

Looks great! :)

https://github.com/llvm/llvm-project/pull/76237
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[llvm] [clang] [clang][AArch64] Add a -mbranch-protection option to enable GCS (PR #75486)

2024-01-10 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

I'm not an expert in this area, but this code LGTM.

https://github.com/llvm/llvm-project/pull/75486
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[clang] [llvm] [AArch64] Remove Automatic Enablement of FEAT_F32MM (PR #85203)

2024-03-14 Thread Jonathan Thackray via cfe-commits



@@ -74,6 +74,7 @@ Changes to the AMDGPU Backend
 
 Changes to the ARM Backend
 --
+* FEAT_F32MM is no longer activated by default when using `+sve` on v8.6-A or 
greater. The feature is still availble and can be using by adding `+f32mm` to 
the command line options.

jthackray wrote:

Nit: typo, s/availble/available/

https://github.com/llvm/llvm-project/pull/85203
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[clang] [llvm] [AArch64] Remove Automatic Enablement of FEAT_F32MM (PR #85203)

2024-03-14 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray edited 
https://github.com/llvm/llvm-project/pull/85203
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[clang] [llvm] [AArch64] Remove Automatic Enablement of FEAT_F32MM (PR #85203)

2024-03-14 Thread Jonathan Thackray via cfe-commits


jthackray wrote:

> When `+sve` is passed in the command line, if the Architecture being targeted 
> is V8.6A/V9.1A or later, `+f32mm` is also added. This enables FEAT_32MM, 
> however at the time of writing no CPU's support this. This leads to the 
> FEAT_32MM instructions being compiled for CPU's that do not support them.
> 
> This commit removes the automatic enablement, however the option is still 
> able to be used by passing `+f32mm`.

Tiny minuscule nit: should be "CPUs" not "CPU's".

https://github.com/llvm/llvm-project/pull/85203
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[clang] [llvm] [AArch64] Remove Automatic Enablement of FEAT_F32MM (PR #85203)

2024-03-14 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

Approved, but please find additional reviewer.

https://github.com/llvm/llvm-project/pull/85203
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[clang] [llvm] [AArch64] Remove Automatic Enablement of FEAT_F32MM (PR #85203)

2024-03-14 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray edited 
https://github.com/llvm/llvm-project/pull/85203
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[clang] [llvm] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (PR #85401)

2024-03-15 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray created 
https://github.com/llvm/llvm-project/pull/85401

None

>From 5124e8c25660c27561586356b28ebd9252a567ed Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 14 Mar 2024 09:26:34 +
Subject: [PATCH] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE
 CPUs

Cortex-A520AE and Cortex-A720AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520AE:
   https://developer.arm.com/documentation/107726/latest/

Technical Reference Manual for Cortex-A720AE:
   https://developer.arm.com/documentation/102828/latest/
---
 clang/docs/ReleaseNotes.rst   |  2 ++
 clang/test/Driver/aarch64-mcpu.c  |  4 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +--
 llvm/docs/ReleaseNotes.rst|  2 ++
 .../llvm/TargetParser/AArch64TargetParser.h   | 11 ++
 llvm/lib/Target/AArch64/AArch64.td| 27 ++
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  2 ++
 llvm/lib/Target/AArch64/AArch64Subtarget.h|  2 ++
 llvm/lib/TargetParser/Host.cpp|  2 ++
 .../TargetParser/TargetParserTest.cpp | 35 ++-
 10 files changed, 88 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index e018d38355945f..0f837ea6181a40 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -420,6 +420,8 @@ Arm and AArch64 Support
   like ``target_version`` or ``target_clones``.
 - Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
 * Arm Cortex-A78AE (cortex-a78ae).
+* Arm Cortex-A520AE (cortex-a520ae).
+* Arm Cortex-A720AE (cortex-a720ae).
 
 Android Support
 ^^^
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index cacfc691058d13..77ba43122b2453 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -56,6 +56,8 @@
 // CORTEX-A715: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a715"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a720  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A720 %s
 // CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a720ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A720AE %s
+// CORTEX-A720AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720ae"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
@@ -70,6 +72,8 @@
 // NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-512tvb"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A520 %s
 // CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a520"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a520ae -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A520AE %s
+// CORTEX-A520AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a520ae"
 
 // RUN: %clang --target=aarch64 -mcpu=cortex-r82  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXR82 %s
 // CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index b65a8fb057ee53..9c91c4157cd6a0 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, 
cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, 
cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, 
cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, 
cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, 
neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, 
apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, 
apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, 
falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, 
thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, 
cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae,

[clang] [llvm] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (PR #85401)

2024-03-15 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray edited 
https://github.com/llvm/llvm-project/pull/85401
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[clang] [llvm] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (PR #85401)

2024-03-15 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/85401

>From 4faf1f908c0c7ddef2833be3dd1b87b3abf302d8 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 14 Mar 2024 09:26:34 +
Subject: [PATCH] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE
 CPUs

Cortex-A520AE and Cortex-A720AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520AE:
   https://developer.arm.com/documentation/107726/latest/

Technical Reference Manual for Cortex-A720AE:
   https://developer.arm.com/documentation/102828/latest/
---
 clang/docs/ReleaseNotes.rst   |  2 ++
 clang/test/Driver/aarch64-mcpu.c  |  4 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +--
 llvm/docs/ReleaseNotes.rst|  2 ++
 .../llvm/TargetParser/AArch64TargetParser.h   | 11 ++
 llvm/lib/Target/AArch64/AArch64.td| 27 ++
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  2 ++
 llvm/lib/Target/AArch64/AArch64Subtarget.h|  2 ++
 llvm/lib/TargetParser/Host.cpp|  2 ++
 .../TargetParser/TargetParserTest.cpp | 35 ++-
 10 files changed, 88 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index e1743368b157e0..a808911d7fab50 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -443,6 +443,8 @@ Arm and AArch64 Support
   like ``target_version`` or ``target_clones``.
 - Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
 * Arm Cortex-A78AE (cortex-a78ae).
+* Arm Cortex-A520AE (cortex-a520ae).
+* Arm Cortex-A720AE (cortex-a720ae).
 
 Android Support
 ^^^
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index cacfc691058d13..77ba43122b2453 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -56,6 +56,8 @@
 // CORTEX-A715: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a715"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a720  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A720 %s
 // CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a720ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A720AE %s
+// CORTEX-A720AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720ae"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
@@ -70,6 +72,8 @@
 // NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-512tvb"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A520 %s
 // CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a520"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a520ae -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A520AE %s
+// CORTEX-A520AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a520ae"
 
 // RUN: %clang --target=aarch64 -mcpu=cortex-r82  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXR82 %s
 // CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index b65a8fb057ee53..9c91c4157cd6a0 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, 
cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, 
cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, 
cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, 
cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, 
neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, 
apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, 
apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, 
falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, 
thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, 
cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex

[clang] [llvm] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (PR #85401)

2024-03-17 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/85401

>From 4faf1f908c0c7ddef2833be3dd1b87b3abf302d8 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 14 Mar 2024 09:26:34 +
Subject: [PATCH 1/2] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE
 CPUs

Cortex-A520AE and Cortex-A720AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520AE:
   https://developer.arm.com/documentation/107726/latest/

Technical Reference Manual for Cortex-A720AE:
   https://developer.arm.com/documentation/102828/latest/
---
 clang/docs/ReleaseNotes.rst   |  2 ++
 clang/test/Driver/aarch64-mcpu.c  |  4 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +--
 llvm/docs/ReleaseNotes.rst|  2 ++
 .../llvm/TargetParser/AArch64TargetParser.h   | 11 ++
 llvm/lib/Target/AArch64/AArch64.td| 27 ++
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  2 ++
 llvm/lib/Target/AArch64/AArch64Subtarget.h|  2 ++
 llvm/lib/TargetParser/Host.cpp|  2 ++
 .../TargetParser/TargetParserTest.cpp | 35 ++-
 10 files changed, 88 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index e1743368b157e0..a808911d7fab50 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -443,6 +443,8 @@ Arm and AArch64 Support
   like ``target_version`` or ``target_clones``.
 - Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
 * Arm Cortex-A78AE (cortex-a78ae).
+* Arm Cortex-A520AE (cortex-a520ae).
+* Arm Cortex-A720AE (cortex-a720ae).
 
 Android Support
 ^^^
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index cacfc691058d13..77ba43122b2453 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -56,6 +56,8 @@
 // CORTEX-A715: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a715"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a720  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A720 %s
 // CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a720ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A720AE %s
+// CORTEX-A720AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720ae"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
@@ -70,6 +72,8 @@
 // NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-512tvb"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A520 %s
 // CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a520"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a520ae -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A520AE %s
+// CORTEX-A520AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a520ae"
 
 // RUN: %clang --target=aarch64 -mcpu=cortex-r82  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXR82 %s
 // CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index b65a8fb057ee53..9c91c4157cd6a0 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, 
cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, 
cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, 
cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, 
cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, 
neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, 
apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, 
apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, 
falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, 
thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, 
cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, co

[clang] [llvm] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (PR #85401)

2024-03-17 Thread Jonathan Thackray via cfe-commits



@@ -67,6 +67,8 @@ Changes to Interprocedural Optimizations
 Changes to the AArch64 Backend
 --
 
+* Added support for Cortex-A520AE and Cortex-A720AE CPUs.

jthackray wrote:

Sure, now fixed.

https://github.com/llvm/llvm-project/pull/85401
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[clang] [llvm] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (PR #85401)

2024-03-17 Thread Jonathan Thackray via cfe-commits



@@ -58,6 +58,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo 
{
 CortexA55,
 CortexA510,
 CortexA520,
+CortexA520AE,

jthackray wrote:

Yes, good idea. Amended.

https://github.com/llvm/llvm-project/pull/85401
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[clang] [llvm] [AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (PR #85401)

2024-03-19 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray closed 
https://github.com/llvm/llvm-project/pull/85401
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[clang] [ARM][AARCH64][NEON]: Wrong return type of NEON intrinsic vqrshrunh_n_s16, vqrshruns_n_s32, and vqrshrund_n_s64 in arm_neon.h (PR #80819)

2024-02-06 Thread Jonathan Thackray via cfe-commits


jthackray wrote:

The author (Gleb) doesn't yet have llvm commit access, so has asked me to merge 
it for him.

https://github.com/llvm/llvm-project/pull/80819
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[clang] [ARM][AARCH64][NEON]: Wrong return type of NEON intrinsic vqrshrunh_n_s16, vqrshruns_n_s32, and vqrshrund_n_s64 in arm_neon.h (PR #80819)

2024-02-06 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray closed 
https://github.com/llvm/llvm-project/pull/80819
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[clang] [llvm] [AArch64] Add the Ampere1B core (PR #81297)

2024-02-09 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray requested changes to this pull request.


https://github.com/llvm/llvm-project/pull/81297
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[clang] [llvm] [AArch64] Add the Ampere1B core (PR #81297)

2024-02-09 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray edited 
https://github.com/llvm/llvm-project/pull/81297
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[clang] [llvm] [AArch64] Add the Ampere1B core (PR #81297)

2024-02-09 Thread Jonathan Thackray via cfe-commits



@@ -784,27 +784,32 @@ inline constexpr CpuInfo CpuInfos[] = {
  (AArch64::ExtensionBitset(
  {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC}))},
 {"tsv110", ARMV8_2A,
- (AArch64::ExtensionBitset(
- {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_DOTPROD,
-  AArch64::AEK_FP16, AArch64::AEK_FP16FML, AArch64::AEK_PROFILE,
-  AArch64::AEK_JSCVT, AArch64::AEK_FCMA}))},
+ (AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,

jthackray wrote:

Nit: this appears to be a NFC whitespace cleanup for an unrelated core. Would 
prefer it if your change was just for ampere1b.

(Can we clang-format in a later change, as there are a lot of other places 
indentation needs fixing?)

https://github.com/llvm/llvm-project/pull/81297
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[clang] [llvm] [AArch64] Add the Ampere1B core (PR #81297)

2024-02-09 Thread Jonathan Thackray via cfe-commits


jthackray wrote:

> The clang-format failures are caused by preexisting/unchanged code. All newly 
> added code passes clang-format.

Yes, I had this issue when I landed new cores previously. This whole file needs 
an NFC clang-format cleanup, IMHO.

https://github.com/llvm/llvm-project/pull/81297
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[clang] [llvm] [AArch64] Add the Ampere1B core (PR #81297)

2024-02-09 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/81297
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[clang] [llvm] Add support for Arm Cortex A78AE CPU (PR #84485)

2024-03-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray created 
https://github.com/llvm/llvm-project/pull/84485

None

>From 40c20f5b4413bd8aac0249d4d1fc4fb4ce8c6438 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Fri, 8 Mar 2024 13:39:35 +
Subject: [PATCH] [ARM][AArch64] Add support for Arm Cortex A78AE CPU

Add support for Arm Cortex A78AE CPU

Technical Reference Manual for Arm Cortex A78AE:
   https://developer.arm.com/documentation/101779/0003

Fixes #84450
---
 clang/test/Driver/aarch64-mcpu.c  |  2 ++
 clang/test/Driver/arm-cortex-cpus-2.c |  7 +++
 clang/test/Misc/target-invalid-cpu-note.c |  6 +++---
 .../llvm/TargetParser/AArch64TargetParser.h   |  5 +
 .../llvm/TargetParser/ARMTargetParser.def |  2 ++
 llvm/lib/Target/AArch64/AArch64.td| 18 ++
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  1 +
 llvm/lib/Target/AArch64/AArch64Subtarget.h|  1 +
 llvm/lib/Target/ARM/ARM.td| 10 ++
 llvm/lib/Target/ARM/ARMSubtarget.cpp  |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h|  1 +
 llvm/lib/TargetParser/Host.cpp|  1 +
 .../TargetParser/TargetParserTest.cpp | 19 +--
 13 files changed, 69 insertions(+), 5 deletions(-)

diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 3e07f3597f3408..cacfc691058d13 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -50,6 +50,8 @@
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
 // CORTEX-A78C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a78c"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a78ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A78AE %s
+// CORTEX-A78AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a78ae"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a715  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A715 %s
 // CORTEX-A715: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a715"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a720  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A720 %s
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index c322303d227866..5ce3758655b500 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -537,6 +537,13 @@
 // CHECK-CORTEX-A78C-MFPU: "-target-feature" "+sha2"
 // CHECK-CORTEX-A78C-MFPU: "-target-feature" "+aes"
 
+// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a78ae -### -c %s 2>&1 
| FileCheck -check-prefix=CHECK-CORTEX-A78AE %s
+// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a78ae 
-mfpu=crypto-neon-fp-armv8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-A78AE-MFPU %s
+// CHECK-CORTEX-A78AE: "-cc1"{{.*}} "-triple" "armv8.2a-{{.*}} "-target-cpu" 
"cortex-a78ae"
+// CHECK-CORTEX-A78AE-MFPU: "-cc1"{{.*}} "-target-feature" "+fp-armv8"
+// CHECK-CORTEX-A78AE-MFPU: "-target-feature" "+sha2"
+// CHECK-CORTEX-A78AE-MFPU: "-target-feature" "+aes"
+
 // RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a710 -### -c %s 2>&1 
| FileCheck -check-prefix=CHECK-CORTEX-A710 %s
 // RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a710 
-mfpu=crypto-neon-fp-armv8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-A710-MFPU %s
 // CHECK-CORTEX-A710: "-cc1"{{.*}} "-triple" "armv9a-{{.*}} "-target-cpu" 
"cortex-a710"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index ef2c1c0cfd3d29..b65a8fb057ee53 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,15 +1,15 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-m52, cortex-a32, cortex-a35, 
cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, 
cortex-a76, cortex-a76ae, cortex-a77, cortex-a7

[clang] [llvm] Add support for Arm Cortex A78AE CPU (PR #84485)

2024-03-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray edited 
https://github.com/llvm/llvm-project/pull/84485
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[clang] [llvm] Add support for Arm Cortex A78AE CPU (PR #84485)

2024-03-08 Thread Jonathan Thackray via cfe-commits


jthackray wrote:

> Should this be added to the release notes? (so it doesn't get forgotten in a 
> mad scramble in a few months time)

Sure, happy to do that.

https://github.com/llvm/llvm-project/pull/84485
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[clang] [llvm] Add support for Arm Cortex A78AE CPU (PR #84485)

2024-03-08 Thread Jonathan Thackray via cfe-commits


jthackray wrote:

> Also does this address the -mcpu=native part of #84450 as well?

I've added a host id (0xd42) to llvm/lib/TargetParser/Host.cpp, so I think so 
(unless there's something else required).

https://github.com/llvm/llvm-project/pull/84485
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[clang] [llvm] Add support for Arm Cortex A78AE CPU (PR #84485)

2024-03-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/84485

>From 40c20f5b4413bd8aac0249d4d1fc4fb4ce8c6438 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Fri, 8 Mar 2024 13:39:35 +
Subject: [PATCH 1/2] [ARM][AArch64] Add support for Arm Cortex A78AE CPU

Add support for Arm Cortex A78AE CPU

Technical Reference Manual for Arm Cortex A78AE:
   https://developer.arm.com/documentation/101779/0003

Fixes #84450
---
 clang/test/Driver/aarch64-mcpu.c  |  2 ++
 clang/test/Driver/arm-cortex-cpus-2.c |  7 +++
 clang/test/Misc/target-invalid-cpu-note.c |  6 +++---
 .../llvm/TargetParser/AArch64TargetParser.h   |  5 +
 .../llvm/TargetParser/ARMTargetParser.def |  2 ++
 llvm/lib/Target/AArch64/AArch64.td| 18 ++
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  1 +
 llvm/lib/Target/AArch64/AArch64Subtarget.h|  1 +
 llvm/lib/Target/ARM/ARM.td| 10 ++
 llvm/lib/Target/ARM/ARMSubtarget.cpp  |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h|  1 +
 llvm/lib/TargetParser/Host.cpp|  1 +
 .../TargetParser/TargetParserTest.cpp | 19 +--
 13 files changed, 69 insertions(+), 5 deletions(-)

diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 3e07f3597f3408..cacfc691058d13 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -50,6 +50,8 @@
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
 // CORTEX-A78C: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a78c"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a78ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A78AE %s
+// CORTEX-A78AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a78ae"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a715  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A715 %s
 // CORTEX-A715: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a715"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a720  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A720 %s
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index c322303d227866..5ce3758655b500 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -537,6 +537,13 @@
 // CHECK-CORTEX-A78C-MFPU: "-target-feature" "+sha2"
 // CHECK-CORTEX-A78C-MFPU: "-target-feature" "+aes"
 
+// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a78ae -### -c %s 2>&1 
| FileCheck -check-prefix=CHECK-CORTEX-A78AE %s
+// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a78ae 
-mfpu=crypto-neon-fp-armv8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-A78AE-MFPU %s
+// CHECK-CORTEX-A78AE: "-cc1"{{.*}} "-triple" "armv8.2a-{{.*}} "-target-cpu" 
"cortex-a78ae"
+// CHECK-CORTEX-A78AE-MFPU: "-cc1"{{.*}} "-target-feature" "+fp-armv8"
+// CHECK-CORTEX-A78AE-MFPU: "-target-feature" "+sha2"
+// CHECK-CORTEX-A78AE-MFPU: "-target-feature" "+aes"
+
 // RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a710 -### -c %s 2>&1 
| FileCheck -check-prefix=CHECK-CORTEX-A710 %s
 // RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a710 
-mfpu=crypto-neon-fp-armv8 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-A710-MFPU %s
 // CHECK-CORTEX-A710: "-cc1"{{.*}} "-triple" "armv9a-{{.*}} "-target-cpu" 
"cortex-a710"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index ef2c1c0cfd3d29..b65a8fb057ee53 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,15 +1,15 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-m52, cortex-a32, cortex-a35, 
cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, 
cortex-a76, cortex-a76ae, cortex-a77, cortex-a78,

[clang] [llvm] Add support for Arm Cortex A78AE CPU (PR #84485)

2024-03-08 Thread Jonathan Thackray via cfe-commits


jthackray wrote:

Linux and Windows builds are passing, but someone has left a trailing 
whitespace character at clang/docs/ReleaseNotes.rst:407 (not me), so I'll merge 
anyway.

https://github.com/llvm/llvm-project/pull/84485
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[clang] [llvm] Add support for Arm Cortex A78AE CPU (PR #84485)

2024-03-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray closed 
https://github.com/llvm/llvm-project/pull/84485
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[clang] [llvm] [ARM][AArch64] Add support for Arm Cortex A78AE CPU (PR #84485)

2024-03-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray edited 
https://github.com/llvm/llvm-project/pull/84485
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[clang] [Clang][AArch64] Add ACLE macros for FEAT_PAuth_LR (PR #80163)

2024-02-01 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

Good stuff, approved.

https://github.com/llvm/llvm-project/pull/80163
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[clang] [ARM][AARCH64][NEON]: Wrong return type of NEON intrinsic vqrshrunh_n_s16, vqrshruns_n_s32, and vqrshrund_n_s64 in arm_neon.h (PR #80819)

2024-02-06 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

Looks good to me.

https://github.com/llvm/llvm-project/pull/80819
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[clang] [flang] [llvm] [AArch64][Driver] Better handling of target feature dependencies (PR #78270)

2024-01-17 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

No specific comments, but am in favour of this, as it reduces code complexity 
and should ensure accuracy of features.

https://github.com/llvm/llvm-project/pull/78270
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[clang] [llvm] [ARM] Introduce the v9.5-A architecture version to Arm targets (PR #78994)

2024-01-22 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

Thanks, Lucas. I can't spot anything obviously wrong, so approved.

https://github.com/llvm/llvm-project/pull/78994
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[clang] [llvm] [AArch64][RISCV] Improve the tests for --print-enabled-extensions and --print-supported-extensions (PR #97829)

2024-07-05 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

Large diff! LGTM, although obvs haven't read every line :)

https://github.com/llvm/llvm-project/pull/97829
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[clang] [Arm][AArch64][Clang] Respect function's branch protection attributes. (PR #101978)

2024-08-09 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/101978
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[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)

2024-08-15 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray commented:

It looks like you've still got the text "FIXME what about nofp here?" in the 
commit message.

https://github.com/llvm/llvm-project/pull/104435
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[clang] [llvm] [AArch64] Add a check for invalid default features (PR #104435)

2024-08-15 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

C++ code looks good. Does this also fix the "+nossbs" issue we saw earlier this 
week?

Presumably this should be cherry-picked to the llvm19 branch?

https://github.com/llvm/llvm-project/pull/104435
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[clang] [llvm] [ARM] Add support for Cortex-R52+ (PR #94633)

2024-06-06 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray created 
https://github.com/llvm/llvm-project/pull/94633

Cortex-R52+ is an Armv8-R AArch32 CPU.

Technical Reference Manual for Cortex-R52+:
   https://developer.arm.com/documentation/102199/latest/

>From 46334c67cc0e47926d46dd16c0d58424ea25c661 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 6 Jun 2024 16:24:55 +0100
Subject: [PATCH] [ARM] Add support for Cortex-R52+

Cortex-R52+ is an Armv8-R AArch32 CPU.

Technical Reference Manual for Cortex-R52+:
   https://developer.arm.com/documentation/102199/latest/
---
 clang/docs/ReleaseNotes.rst| 1 +
 clang/test/Misc/target-invalid-cpu-note.c  | 2 +-
 llvm/docs/ReleaseNotes.rst | 1 +
 llvm/include/llvm/TargetParser/ARMTargetParser.def | 1 +
 llvm/lib/Target/ARM/ARMProcessors.td   | 8 
 llvm/lib/Target/ARM/ARMSubtarget.cpp   | 1 +
 llvm/lib/TargetParser/Host.cpp | 1 +
 llvm/test/CodeGen/ARM/build-attributes.ll  | 4 
 llvm/test/CodeGen/ARM/cortexr52-misched-basic.ll   | 1 +
 llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll   | 1 +
 llvm/test/CodeGen/ARM/misched-fp-basic.ll  | 2 ++
 llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir | 2 ++
 llvm/test/CodeGen/ARM/misched-int-basic.mir| 2 ++
 llvm/test/CodeGen/ARM/proc-resource-sched.ll   | 1 +
 llvm/test/CodeGen/ARM/single-issue-r52.mir | 2 ++
 llvm/test/CodeGen/ARM/useaa.ll | 1 +
 llvm/test/MC/ARM/dfb-neg.s | 2 ++
 llvm/test/MC/ARM/dfb.s | 2 ++
 llvm/test/MC/ARM/invalid-armv8r.s  | 6 ++
 llvm/test/MC/ARM/thumb-hints.s | 2 ++
 llvm/test/MC/Disassembler/ARM/dfb-thumb.txt| 2 ++
 llvm/unittests/TargetParser/TargetParserTest.cpp   | 9 -
 22 files changed, 52 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/MC/ARM/invalid-armv8r.s

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index b9c9070fcb22f..cf1ba02cbc4b2 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -907,6 +907,7 @@ Arm and AArch64 Support
 * Arm Cortex-A520AE (cortex-a520ae).
 * Arm Cortex-A720AE (cortex-a720ae).
 * Arm Cortex-R82AE (cortex-r82ae).
+* Arm Cortex-R52+ (cortex-r52plus).
 * Arm Neoverse-N3 (neoverse-n3).
 * Arm Neoverse-V3 (neoverse-v3).
 * Arm Neoverse-V3AE (neoverse-v3ae).
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 5ec2743c8d41f..845e6a09045a8 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-m52, cortex-a32, cortex-a35, 
cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, 
cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, 
cortex-a710, cortex-x1, cortex-x1c, neoverse-n1, neoverse-n2, neoverse-v1, 
cyclone, exynos-m3, exynos-m4, exynos-m5, kryo, iwmmxt, xscale, swift{{$}}
+// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, cortex-r52plus, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, 
cortex-m33, cortex-m35p, cortex-m55, cortex-m85, cortex-m52, cortex-a32, 
cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, 
cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-

[clang] [llvm] [ARM] Add support for Cortex-R52+ (PR #94633)

2024-06-07 Thread Jonathan Thackray via cfe-commits



@@ -90,6 +90,8 @@ def ProcR7  : SubtargetFeature<"r7", "ARMProcFamily", 
"CortexR7",
"Cortex-R7 ARM processors", []>;
 def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
"Cortex-R52 ARM processors", []>;
+def ProcR52plus  : SubtargetFeature<"r52plus", "ARMProcFamily", 
"CortexR52plus",

jthackray wrote:

Thanks. I'll probably just keep it as-is (too many other concurrent tasks); 
upstreaming this now, since it was accidentally left downstream previously.

https://github.com/llvm/llvm-project/pull/94633
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[clang] [llvm] [ARM] Add support for Cortex-R52+ (PR #94633)

2024-06-07 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray closed 
https://github.com/llvm/llvm-project/pull/94633
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[clang] [llvm] Enable LLDB tests in Linux pre-merge CI (PR #94208)

2024-06-07 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/94208

>From 5c757153a3f462d40663add6a9ae7caf42272913 Mon Sep 17 00:00:00 2001
From: Vlad Serebrennikov 
Date: Mon, 3 Jun 2024 13:33:36 +0300
Subject: [PATCH 1/8] Enable LLDB tests in pre-submit CI

---
 .ci/generate-buildkite-pipeline-premerge | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/.ci/generate-buildkite-pipeline-premerge 
b/.ci/generate-buildkite-pipeline-premerge
index 033ab804b165e..a9972f235ff46 100755
--- a/.ci/generate-buildkite-pipeline-premerge
+++ b/.ci/generate-buildkite-pipeline-premerge
@@ -153,7 +153,6 @@ function exclude-linux() {
   for project in ${projects}; do
 case ${project} in
 cross-project-tests) ;; # tests failing
-lldb);; # tests failing
 openmp)  ;; # 
https://github.com/google/llvm-premerge-checks/issues/410
 *)
   echo "${project}"
@@ -170,7 +169,6 @@ function exclude-windows() {
 compiler-rt) ;; # tests taking too long
 openmp)  ;; # TODO: having trouble with the Perl installation
 libc);; # no Windows support
-lldb);; # tests failing
 bolt);; # tests are not supported yet
 *)
   echo "${project}"
@@ -213,7 +211,7 @@ function check-targets() {
   echo "check-unwind"
 ;;
 lldb)
-  echo "check-all" # TODO: check-lldb may not include all the LLDB tests?
+  echo "check-lldb" # TODO: check-lldb may not include all the LLDB tests?
 ;;
 pstl)
   echo "check-all"

>From 49e21f6b92623e280cfc49ac631b7481eb7a1229 Mon Sep 17 00:00:00 2001
From: Vlad Serebrennikov 
Date: Mon, 3 Jun 2024 13:34:18 +0300
Subject: [PATCH 2/8] Trigger Clang CI

---
 clang/examples/PrintFunctionNames/PrintFunctionNames.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/clang/examples/PrintFunctionNames/PrintFunctionNames.cpp 
b/clang/examples/PrintFunctionNames/PrintFunctionNames.cpp
index 6509a6440e12d..b2b785b87c25c 100644
--- a/clang/examples/PrintFunctionNames/PrintFunctionNames.cpp
+++ b/clang/examples/PrintFunctionNames/PrintFunctionNames.cpp
@@ -72,7 +72,7 @@ class PrintFunctionsConsumer : public ASTConsumer {
   *sema.LateParsedTemplateMap.find(FD)->second;
   sema.LateTemplateParser(sema.OpaqueParser, LPT);
   llvm::errs() << "late-parsed-decl: \"" << FD->getNameAsString() << 
"\"\n";
-}   
+}
   }
 };
 

>From c2d7679f76e971e5532c1cd91d99e7866f738960 Mon Sep 17 00:00:00 2001
From: Vlad Serebrennikov 
Date: Mon, 3 Jun 2024 15:48:05 +0300
Subject: [PATCH 3/8] Add `pip install pexpect`

---
 .ci/monolithic-linux.sh   | 2 ++
 .ci/monolithic-windows.sh | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/.ci/monolithic-linux.sh b/.ci/monolithic-linux.sh
index 38d7128f241b6..95ac4218ef8fa 100755
--- a/.ci/monolithic-linux.sh
+++ b/.ci/monolithic-linux.sh
@@ -39,6 +39,8 @@ targets="${2}"
 
 echo "--- cmake"
 pip install -q -r "${MONOREPO_ROOT}"/mlir/python/requirements.txt
+# Needed for several LLDB tests
+pip install pexpect
 cmake -S "${MONOREPO_ROOT}"/llvm -B "${BUILD_DIR}" \
   -D LLVM_ENABLE_PROJECTS="${projects}" \
   -G Ninja \
diff --git a/.ci/monolithic-windows.sh b/.ci/monolithic-windows.sh
index 91e719c52d436..e8807e3ba69bf 100755
--- a/.ci/monolithic-windows.sh
+++ b/.ci/monolithic-windows.sh
@@ -38,6 +38,8 @@ targets="${2}"
 
 echo "--- cmake"
 pip install -q -r "${MONOREPO_ROOT}"/mlir/python/requirements.txt
+# Needed for several LLDB tests
+pip install pexpect
 
 # The CMAKE_*_LINKER_FLAGS to disable the manifest come from research
 # on fixing a build reliability issue on the build server, please

>From 496d2998a722a7bb57fc9a5a38f9ee5e52440c1d Mon Sep 17 00:00:00 2001
From: Vlad Serebrennikov 
Date: Mon, 3 Jun 2024 21:20:01 +0300
Subject: [PATCH 4/8] Switch to `requirements.txt` provided by LLDB now

---
 .ci/monolithic-linux.sh   | 3 +--
 .ci/monolithic-windows.sh | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/.ci/monolithic-linux.sh b/.ci/monolithic-linux.sh
index 95ac4218ef8fa..b78dc59432b65 100755
--- a/.ci/monolithic-linux.sh
+++ b/.ci/monolithic-linux.sh
@@ -39,8 +39,7 @@ targets="${2}"
 
 echo "--- cmake"
 pip install -q -r "${MONOREPO_ROOT}"/mlir/python/requirements.txt
-# Needed for several LLDB tests
-pip install pexpect
+pip install -q -r "${MONOREPO_ROOT}"/lldb/test/requirements.txt
 cmake -S "${MONOREPO_ROOT}"/llvm -B "${BUILD_DIR}" \
   -D LLVM_ENABLE_PROJECTS="${projects}" \
   -G Ninja \
diff --git a/.ci/monolithic-windows.sh b/.ci/monolithic-windows.sh
index e8807e3ba69bf..af78447295012 100755
--- a/.ci/monolithic-windows.sh
+++ b/.ci/monolithic-windows.sh
@@ -38,8 +38,7 @@ targets="${2}"
 
 echo "--- cmake"
 pip install -q -r "${MONOREPO_ROOT}"/mlir/python/requirements.txt
-# Needed for several LLDB tests
-pip install pexpect
+pip install -q -r "${MONOREPO_ROOT}"/lldb/test/requirements.txt
 
 # The CMA

[clang] [llvm] [AArch64] Add support for Cortex-A725 and Cortex-X925 (PR #95214)

2024-06-12 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray created 
https://github.com/llvm/llvm-project/pull/95214

Cortex-A725 and Cortex-X925 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A725:
   https://developer.arm.com/documentation/107652/latest

Technical Reference Manual for Cortex-X925:
   https://developer.arm.com/documentation/102807/latest

>From 1e0bb8109b06d29c177765dd7279c7f8f62d1c1d Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Wed, 29 May 2024 22:14:28 +0100
Subject: [PATCH] [AArch64] Add support for Cortex-A725 and Cortex-X925

Cortex-A725 and Cortex-X925 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A725:
   https://developer.arm.com/documentation/107652/latest

Technical Reference Manual for Cortex-X925:
   https://developer.arm.com/documentation/102807/latest
---
 clang/docs/ReleaseNotes.rst   |  6 ++--
 clang/test/Driver/aarch64-mcpu.c  |  4 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +--
 llvm/docs/ReleaseNotes.rst|  4 +--
 .../llvm/TargetParser/AArch64TargetParser.h   | 12 +++
 llvm/lib/Target/AArch64/AArch64Processors.td  | 30 
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  2 ++
 llvm/lib/TargetParser/Host.cpp|  2 ++
 .../TargetParser/TargetParserTest.cpp | 36 ++-
 9 files changed, 93 insertions(+), 7 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index cf1ba02cbc4b2..148ff05008552 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -903,11 +903,13 @@ Arm and AArch64 Support
   a feature modifier for -march and -mcpu as well as via target attributes
   like ``target_version`` or ``target_clones``.
 - Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
+* Arm Cortex-R52+ (cortex-r52plus).
+* Arm Cortex-R82AE (cortex-r82ae).
 * Arm Cortex-A78AE (cortex-a78ae).
 * Arm Cortex-A520AE (cortex-a520ae).
 * Arm Cortex-A720AE (cortex-a720ae).
-* Arm Cortex-R82AE (cortex-r82ae).
-* Arm Cortex-R52+ (cortex-r52plus).
+* Arm Cortex-A725 (cortex-a725).
+* Arm Cortex-X925 (cortex-x925).
 * Arm Neoverse-N3 (neoverse-n3).
 * Arm Neoverse-V3 (neoverse-v3).
 * Arm Neoverse-V3AE (neoverse-v3ae).
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index ad4a5f9ac6fb8..97303510d6881 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -46,6 +46,8 @@
 // CORTEXX3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x3"
 // RUN: %clang --target=aarch64 -mcpu=cortex-x4 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X4 %s
 // CORTEX-X4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x4"
+// RUN: %clang --target=aarch64 -mcpu=cortex-x925 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X925 %s
+// CORTEX-X925: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-x925"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXA78 %s
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
@@ -58,6 +60,8 @@
 // CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a720ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A720AE %s
 // CORTEX-A720AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720ae"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a725  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A725 %s
+// CORTEX-A725: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a725"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 2439025609b9f..790dbd9e07475 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, 
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n

[clang] [llvm] [AArch64] Add support for Cortex-A725 and Cortex-X925 (PR #95214)

2024-06-12 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/95214

>From 1e0bb8109b06d29c177765dd7279c7f8f62d1c1d Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Wed, 29 May 2024 22:14:28 +0100
Subject: [PATCH] [AArch64] Add support for Cortex-A725 and Cortex-X925

Cortex-A725 and Cortex-X925 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A725:
   https://developer.arm.com/documentation/107652/latest

Technical Reference Manual for Cortex-X925:
   https://developer.arm.com/documentation/102807/latest
---
 clang/docs/ReleaseNotes.rst   |  6 ++--
 clang/test/Driver/aarch64-mcpu.c  |  4 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +--
 llvm/docs/ReleaseNotes.rst|  4 +--
 .../llvm/TargetParser/AArch64TargetParser.h   | 12 +++
 llvm/lib/Target/AArch64/AArch64Processors.td  | 30 
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  2 ++
 llvm/lib/TargetParser/Host.cpp|  2 ++
 .../TargetParser/TargetParserTest.cpp | 36 ++-
 9 files changed, 93 insertions(+), 7 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index cf1ba02cbc4b2..148ff05008552 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -903,11 +903,13 @@ Arm and AArch64 Support
   a feature modifier for -march and -mcpu as well as via target attributes
   like ``target_version`` or ``target_clones``.
 - Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
+* Arm Cortex-R52+ (cortex-r52plus).
+* Arm Cortex-R82AE (cortex-r82ae).
 * Arm Cortex-A78AE (cortex-a78ae).
 * Arm Cortex-A520AE (cortex-a520ae).
 * Arm Cortex-A720AE (cortex-a720ae).
-* Arm Cortex-R82AE (cortex-r82ae).
-* Arm Cortex-R52+ (cortex-r52plus).
+* Arm Cortex-A725 (cortex-a725).
+* Arm Cortex-X925 (cortex-x925).
 * Arm Neoverse-N3 (neoverse-n3).
 * Arm Neoverse-V3 (neoverse-v3).
 * Arm Neoverse-V3AE (neoverse-v3ae).
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index ad4a5f9ac6fb8..97303510d6881 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -46,6 +46,8 @@
 // CORTEXX3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x3"
 // RUN: %clang --target=aarch64 -mcpu=cortex-x4 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X4 %s
 // CORTEX-X4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x4"
+// RUN: %clang --target=aarch64 -mcpu=cortex-x925 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X925 %s
+// CORTEX-X925: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-x925"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXA78 %s
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
@@ -58,6 +60,8 @@
 // CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a720ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A720AE %s
 // CORTEX-A720AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720ae"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a725  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A725 %s
+// CORTEX-A725: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a725"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 2439025609b9f..790dbd9e07475 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, 
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, 
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, 
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, 
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, 
apple-m1, apple-m2, apple-m3

[clang] [llvm] [AArch64] Add support for Cortex-A725 and Cortex-X925 (PR #95214)

2024-06-12 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/95214

>From 2cdb7257614201cc0907d7908a5f7cb3d300fd51 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Wed, 29 May 2024 22:14:28 +0100
Subject: [PATCH] [AArch64] Add support for Cortex-A725 and Cortex-X925

Cortex-A725 and Cortex-X925 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A725:
   https://developer.arm.com/documentation/107652/latest

Technical Reference Manual for Cortex-X925:
   https://developer.arm.com/documentation/102807/latest
---
 clang/docs/ReleaseNotes.rst   |  6 ++--
 clang/test/Driver/aarch64-mcpu.c  |  4 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +--
 llvm/docs/ReleaseNotes.rst|  4 +--
 .../llvm/TargetParser/AArch64TargetParser.h   | 12 +++
 llvm/lib/Target/AArch64/AArch64Processors.td  | 30 
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  2 ++
 llvm/lib/TargetParser/Host.cpp|  2 ++
 .../TargetParser/TargetParserTest.cpp | 36 ++-
 9 files changed, 93 insertions(+), 7 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index cf1ba02cbc4b2..148ff05008552 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -903,11 +903,13 @@ Arm and AArch64 Support
   a feature modifier for -march and -mcpu as well as via target attributes
   like ``target_version`` or ``target_clones``.
 - Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
+* Arm Cortex-R52+ (cortex-r52plus).
+* Arm Cortex-R82AE (cortex-r82ae).
 * Arm Cortex-A78AE (cortex-a78ae).
 * Arm Cortex-A520AE (cortex-a520ae).
 * Arm Cortex-A720AE (cortex-a720ae).
-* Arm Cortex-R82AE (cortex-r82ae).
-* Arm Cortex-R52+ (cortex-r52plus).
+* Arm Cortex-A725 (cortex-a725).
+* Arm Cortex-X925 (cortex-x925).
 * Arm Neoverse-N3 (neoverse-n3).
 * Arm Neoverse-V3 (neoverse-v3).
 * Arm Neoverse-V3AE (neoverse-v3ae).
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index ad4a5f9ac6fb8..97303510d6881 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -46,6 +46,8 @@
 // CORTEXX3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x3"
 // RUN: %clang --target=aarch64 -mcpu=cortex-x4 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X4 %s
 // CORTEX-X4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x4"
+// RUN: %clang --target=aarch64 -mcpu=cortex-x925 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X925 %s
+// CORTEX-X925: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-x925"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXA78 %s
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
@@ -58,6 +60,8 @@
 // CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a720ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A720AE %s
 // CORTEX-A720AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720ae"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a725  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A725 %s
+// CORTEX-A725: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a725"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 2439025609b9f..790dbd9e07475 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, 
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, 
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, 
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, 
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, 
apple-m1, apple-m2, apple-m3

[clang] [llvm] [AArch64] Add support for Cortex-A725 and Cortex-X925 (PR #95214)

2024-06-12 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/95214

>From f48ed213e7c1c9e8ab32f4916622c2089e67a628 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Wed, 29 May 2024 22:14:28 +0100
Subject: [PATCH] [AArch64] Add support for Cortex-A725 and Cortex-X925

Cortex-A725 and Cortex-X925 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A725:
   https://developer.arm.com/documentation/107652/latest

Technical Reference Manual for Cortex-X925:
   https://developer.arm.com/documentation/102807/latest
---
 clang/docs/ReleaseNotes.rst   |  6 ++--
 clang/test/Driver/aarch64-mcpu.c  |  4 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +--
 llvm/docs/ReleaseNotes.rst|  4 +--
 .../llvm/TargetParser/AArch64TargetParser.h   | 12 +++
 llvm/lib/Target/AArch64/AArch64Processors.td  | 30 
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  2 ++
 llvm/lib/TargetParser/Host.cpp|  2 ++
 .../TargetParser/TargetParserTest.cpp | 36 ++-
 9 files changed, 93 insertions(+), 7 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index cf1ba02cbc4b2..148ff05008552 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -903,11 +903,13 @@ Arm and AArch64 Support
   a feature modifier for -march and -mcpu as well as via target attributes
   like ``target_version`` or ``target_clones``.
 - Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
+* Arm Cortex-R52+ (cortex-r52plus).
+* Arm Cortex-R82AE (cortex-r82ae).
 * Arm Cortex-A78AE (cortex-a78ae).
 * Arm Cortex-A520AE (cortex-a520ae).
 * Arm Cortex-A720AE (cortex-a720ae).
-* Arm Cortex-R82AE (cortex-r82ae).
-* Arm Cortex-R52+ (cortex-r52plus).
+* Arm Cortex-A725 (cortex-a725).
+* Arm Cortex-X925 (cortex-x925).
 * Arm Neoverse-N3 (neoverse-n3).
 * Arm Neoverse-V3 (neoverse-v3).
 * Arm Neoverse-V3AE (neoverse-v3ae).
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index ad4a5f9ac6fb8..97303510d6881 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -46,6 +46,8 @@
 // CORTEXX3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x3"
 // RUN: %clang --target=aarch64 -mcpu=cortex-x4 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X4 %s
 // CORTEX-X4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x4"
+// RUN: %clang --target=aarch64 -mcpu=cortex-x925 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X925 %s
+// CORTEX-X925: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-x925"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXA78 %s
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
@@ -58,6 +60,8 @@
 // CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a720ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A720AE %s
 // CORTEX-A720AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720ae"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a725  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A725 %s
+// CORTEX-A725: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a725"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 2439025609b9f..5362c6f882c25 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, 
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, 
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, 
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, 
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, 
apple-m1, apple-m2, apple-m3

[clang] [llvm] [AArch64] Add support for Cortex-A725 and Cortex-X925 (PR #95214)

2024-06-12 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/95214

>From f48ed213e7c1c9e8ab32f4916622c2089e67a628 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Wed, 29 May 2024 22:14:28 +0100
Subject: [PATCH 1/2] [AArch64] Add support for Cortex-A725 and Cortex-X925

Cortex-A725 and Cortex-X925 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A725:
   https://developer.arm.com/documentation/107652/latest

Technical Reference Manual for Cortex-X925:
   https://developer.arm.com/documentation/102807/latest
---
 clang/docs/ReleaseNotes.rst   |  6 ++--
 clang/test/Driver/aarch64-mcpu.c  |  4 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +--
 llvm/docs/ReleaseNotes.rst|  4 +--
 .../llvm/TargetParser/AArch64TargetParser.h   | 12 +++
 llvm/lib/Target/AArch64/AArch64Processors.td  | 30 
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  2 ++
 llvm/lib/TargetParser/Host.cpp|  2 ++
 .../TargetParser/TargetParserTest.cpp | 36 ++-
 9 files changed, 93 insertions(+), 7 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index cf1ba02cbc4b2..148ff05008552 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -903,11 +903,13 @@ Arm and AArch64 Support
   a feature modifier for -march and -mcpu as well as via target attributes
   like ``target_version`` or ``target_clones``.
 - Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
+* Arm Cortex-R52+ (cortex-r52plus).
+* Arm Cortex-R82AE (cortex-r82ae).
 * Arm Cortex-A78AE (cortex-a78ae).
 * Arm Cortex-A520AE (cortex-a520ae).
 * Arm Cortex-A720AE (cortex-a720ae).
-* Arm Cortex-R82AE (cortex-r82ae).
-* Arm Cortex-R52+ (cortex-r52plus).
+* Arm Cortex-A725 (cortex-a725).
+* Arm Cortex-X925 (cortex-x925).
 * Arm Neoverse-N3 (neoverse-n3).
 * Arm Neoverse-V3 (neoverse-v3).
 * Arm Neoverse-V3AE (neoverse-v3ae).
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index ad4a5f9ac6fb8..97303510d6881 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -46,6 +46,8 @@
 // CORTEXX3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x3"
 // RUN: %clang --target=aarch64 -mcpu=cortex-x4 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X4 %s
 // CORTEX-X4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x4"
+// RUN: %clang --target=aarch64 -mcpu=cortex-x925 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X925 %s
+// CORTEX-X925: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-x925"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXA78 %s
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
@@ -58,6 +60,8 @@
 // CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a720ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A720AE %s
 // CORTEX-A720AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720ae"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a725  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A725 %s
+// CORTEX-A725: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a725"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 2439025609b9f..5362c6f882c25 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, 
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, 
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, 
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, 
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, 
apple-m1, apple-m2, appl

[clang] [llvm] [AArch64] Add support for Cortex-A725 and Cortex-X925 (PR #95214)

2024-06-12 Thread Jonathan Thackray via cfe-commits



@@ -723,6 +746,9 @@ def ProcessorFeatures {
  FeaturePerfMon, FeatureETE, FeatureTRBE,
  FeatureSPE, FeatureMTE, FeatureSVE2BitPerm,
  FeatureFP16FML, FeatureSPE_EEF];
+  list X925 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,

jthackray wrote:

Thanks, good spot. Fixed.

https://github.com/llvm/llvm-project/pull/95214
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[clang] [llvm] [AArch64][TargetParser] move CPUInfo into tablegen [NFC] (PR #92145)

2024-06-12 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray approved this pull request.

LGTM, assuming it causes no regressions.

https://github.com/llvm/llvm-project/pull/92145
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[clang] [llvm] [AArch64] Add support for Cortex-A725 and Cortex-X925 (PR #95214)

2024-06-12 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray closed 
https://github.com/llvm/llvm-project/pull/95214
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[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)

2024-06-17 Thread Jonathan Thackray via cfe-commits


jthackray wrote:

This is a good idea. Happy to approve, once all the FIXMEs are removed, since 
others have already made many salient suggestions, which I agree with.

https://github.com/llvm/llvm-project/pull/95805
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[clang] [llvm] [AArch64] Add support for Cortex-A725 and Cortex-X925 (PR #93978)

2024-05-31 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray created 
https://github.com/llvm/llvm-project/pull/93978

Cortex-A725 and Cortex-X925 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A725:
   https://developer.arm.com/documentation/107652/latest

Technical Reference Manual for Cortex-X925:
   https://developer.arm.com/documentation/102807/latest

>From 6a1729a6c7226660207210a304f04e888288b5f9 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Wed, 29 May 2024 22:14:28 +0100
Subject: [PATCH] [AArch64] Add support for Cortex-A725 and Cortex-X925

Cortex-A725 and Cortex-X925 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A725:
   https://developer.arm.com/documentation/107652/latest

Technical Reference Manual for Cortex-X925:
   https://developer.arm.com/documentation/102807/latest
---
 clang/docs/ReleaseNotes.rst   |  4 ++-
 clang/test/Driver/aarch64-mcpu.c  |  4 +++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +--
 llvm/docs/ReleaseNotes.rst|  4 +--
 .../llvm/TargetParser/AArch64TargetParser.h   | 12 +++
 llvm/lib/Target/AArch64/AArch64Processors.td  | 30 
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  2 ++
 llvm/lib/TargetParser/Host.cpp|  2 ++
 .../TargetParser/TargetParserTest.cpp | 36 ++-
 9 files changed, 92 insertions(+), 6 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 44035f48cb3f9..8405cb31b3c76 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -870,10 +870,12 @@ Arm and AArch64 Support
   a feature modifier for -march and -mcpu as well as via target attributes
   like ``target_version`` or ``target_clones``.
 - Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
+* Arm Cortex-R82AE (cortex-r82ae).
 * Arm Cortex-A78AE (cortex-a78ae).
 * Arm Cortex-A520AE (cortex-a520ae).
 * Arm Cortex-A720AE (cortex-a720ae).
-* Arm Cortex-R82AE (cortex-r82ae).
+* Arm Cortex-A725 (cortex-a725).
+* Arm Cortex-X925 (cortex-x925).
 * Arm Neoverse-N3 (neoverse-n3).
 * Arm Neoverse-V3 (neoverse-v3).
 * Arm Neoverse-V3AE (neoverse-v3ae).
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index ad4a5f9ac6fb8..97303510d6881 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -46,6 +46,8 @@
 // CORTEXX3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x3"
 // RUN: %clang --target=aarch64 -mcpu=cortex-x4 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X4 %s
 // CORTEX-X4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x4"
+// RUN: %clang --target=aarch64 -mcpu=cortex-x925 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-X925 %s
+// CORTEX-X925: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-x925"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXA78 %s
 // CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a78c  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A78C %s
@@ -58,6 +60,8 @@
 // CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a720ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=CORTEX-A720AE %s
 // CORTEX-A720AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a720ae"
+// RUN: %clang --target=aarch64 -mcpu=cortex-a725  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A725 %s
+// CORTEX-A725: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"cortex-a725"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-e1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-E1 %s
 // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-e1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v1  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V1 %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 768b243b04e3a..b7f8bef0bcae0 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, 
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, 
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, 
neoverse-

[clang] [llvm] [AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (PR #87414)

2024-04-25 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/87414

>From 5ced9f33871ea66647e04f62c637b92259805c2e Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Tue, 2 Apr 2024 22:08:50 +0100
Subject: [PATCH] [AArch64] Add support for Neoverse-N3, Neoverse-V3 and
 Neoverse-V3AE

Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Neoverse-N3:
   https://developer.arm.com/documentation/107997/latest/

Technical Reference Manual for Neoverse-V3:
   https://developer.arm.com/documentation/107734/latest/

Technical Reference Manual for Neoverse-V3AE:
   https://developer.arm.com/documentation/101595/latest/
---
 clang/docs/ReleaseNotes.rst   |  3 +
 clang/test/Driver/aarch64-mcpu.c  |  6 ++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +-
 llvm/docs/ReleaseNotes.rst|  3 +-
 .../llvm/TargetParser/AArch64TargetParser.h   | 21 +++
 llvm/lib/Target/AArch64/AArch64Processors.td  | 46 +++
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  2 +
 llvm/lib/TargetParser/Host.cpp|  3 +
 .../TargetParser/TargetParserTest.cpp | 58 ++-
 9 files changed, 142 insertions(+), 4 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 00c684e773a2e0..4b768db003b273 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -640,6 +640,9 @@ Arm and AArch64 Support
 * Arm Cortex-A78AE (cortex-a78ae).
 * Arm Cortex-A520AE (cortex-a520ae).
 * Arm Cortex-A720AE (cortex-a720ae).
+* Arm Neoverse-N3 (neoverse-n3).
+* Arm Neoverse-V3 (neoverse-v3).
+* Arm Neoverse-V3AE (neoverse-v3ae).
 
 Android Support
 ^^^
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 77ba43122b2453..ad4a5f9ac6fb80 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -64,10 +64,16 @@
 // NEOVERSE-V1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-v1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v2  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V2 %s
 // NEOVERSE-V2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-v2"
+// RUN: %clang --target=aarch64 -mcpu=neoverse-v3  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V3 %s
+// NEOVERSE-V3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-v3"
+// RUN: %clang --target=aarch64 -mcpu=neoverse-v3ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=NEOVERSE-V3AE %s
+// NEOVERSE-V3AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-v3ae"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-n1 -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-N1 %s
 // NEOVERSE-N1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-N2 %s
 // NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n2"
+// RUN: %clang --target=aarch64 -mcpu=neoverse-n3 -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-N3 %s
+// NEOVERSE-N3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n3"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-512tvb -### -c %s 2>&1 | 
FileCheck -check-prefix=NEOVERSE-512TVB %s
 // NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-512tvb"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A520 %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 9c91c4157cd6a0..21d80b7134508f 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, 
cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, 
neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, 
apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, 
apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, 
exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, 
thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, 
carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53,

[clang] [llvm] [AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (PR #87414)

2024-04-25 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray closed 
https://github.com/llvm/llvm-project/pull/87414
___
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[clang] [llvm] [AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (PR #90143)

2024-04-25 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray created 
https://github.com/llvm/llvm-project/pull/90143

Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Neoverse-N3:
   https://developer.arm.com/documentation/107997/latest/

Technical Reference Manual for Neoverse-V3:
   https://developer.arm.com/documentation/107734/latest/

Technical Reference Manual for Neoverse-V3AE:
   https://developer.arm.com/documentation/101595/latest/


>From 5ced9f33871ea66647e04f62c637b92259805c2e Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Tue, 2 Apr 2024 22:08:50 +0100
Subject: [PATCH] [AArch64] Add support for Neoverse-N3, Neoverse-V3 and
 Neoverse-V3AE

Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Neoverse-N3:
   https://developer.arm.com/documentation/107997/latest/

Technical Reference Manual for Neoverse-V3:
   https://developer.arm.com/documentation/107734/latest/

Technical Reference Manual for Neoverse-V3AE:
   https://developer.arm.com/documentation/101595/latest/
---
 clang/docs/ReleaseNotes.rst   |  3 +
 clang/test/Driver/aarch64-mcpu.c  |  6 ++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +-
 llvm/docs/ReleaseNotes.rst|  3 +-
 .../llvm/TargetParser/AArch64TargetParser.h   | 21 +++
 llvm/lib/Target/AArch64/AArch64Processors.td  | 46 +++
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  2 +
 llvm/lib/TargetParser/Host.cpp|  3 +
 .../TargetParser/TargetParserTest.cpp | 58 ++-
 9 files changed, 142 insertions(+), 4 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 00c684e773a2e0..4b768db003b273 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -640,6 +640,9 @@ Arm and AArch64 Support
 * Arm Cortex-A78AE (cortex-a78ae).
 * Arm Cortex-A520AE (cortex-a520ae).
 * Arm Cortex-A720AE (cortex-a720ae).
+* Arm Neoverse-N3 (neoverse-n3).
+* Arm Neoverse-V3 (neoverse-v3).
+* Arm Neoverse-V3AE (neoverse-v3ae).
 
 Android Support
 ^^^
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 77ba43122b2453..ad4a5f9ac6fb80 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -64,10 +64,16 @@
 // NEOVERSE-V1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-v1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v2  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V2 %s
 // NEOVERSE-V2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-v2"
+// RUN: %clang --target=aarch64 -mcpu=neoverse-v3  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V3 %s
+// NEOVERSE-V3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-v3"
+// RUN: %clang --target=aarch64 -mcpu=neoverse-v3ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=NEOVERSE-V3AE %s
+// NEOVERSE-V3AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-v3ae"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-n1 -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-N1 %s
 // NEOVERSE-N1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-N2 %s
 // NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n2"
+// RUN: %clang --target=aarch64 -mcpu=neoverse-n3 -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-N3 %s
+// NEOVERSE-N3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n3"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-512tvb -### -c %s 2>&1 | 
FileCheck -check-prefix=NEOVERSE-512TVB %s
 // NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-512tvb"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A520 %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 9c91c4157cd6a0..21d80b7134508f 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, 
cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, 
neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, 
apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, app

[clang] [llvm] [AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (PR #90143)

2024-04-26 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/90143

>From 020b30260b501902d728fbc9a92b4bc6fa81af18 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Tue, 2 Apr 2024 22:08:50 +0100
Subject: [PATCH 1/2] [AArch64] Add support for Neoverse-N3, Neoverse-V3 and
 Neoverse-V3AE

Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Neoverse-N3:
   https://developer.arm.com/documentation/107997/latest/

Technical Reference Manual for Neoverse-V3:
   https://developer.arm.com/documentation/107734/latest/

Technical Reference Manual for Neoverse-V3AE:
   https://developer.arm.com/documentation/101595/latest/
---
 clang/docs/ReleaseNotes.rst   |  3 +
 clang/test/Driver/aarch64-mcpu.c  |  6 ++
 clang/test/Misc/target-invalid-cpu-note.c |  4 +-
 llvm/docs/ReleaseNotes.rst|  3 +-
 .../llvm/TargetParser/AArch64TargetParser.h   | 21 +++
 llvm/lib/Target/AArch64/AArch64Processors.td  | 46 +++
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp  |  2 +
 llvm/lib/TargetParser/Host.cpp|  3 +
 .../TargetParser/TargetParserTest.cpp | 58 ++-
 9 files changed, 142 insertions(+), 4 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 1576f681707de0..92563262cc6737 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -633,6 +633,9 @@ Arm and AArch64 Support
 * Arm Cortex-A78AE (cortex-a78ae).
 * Arm Cortex-A520AE (cortex-a520ae).
 * Arm Cortex-A720AE (cortex-a720ae).
+* Arm Neoverse-N3 (neoverse-n3).
+* Arm Neoverse-V3 (neoverse-v3).
+* Arm Neoverse-V3AE (neoverse-v3ae).
 
 Android Support
 ^^^
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 77ba43122b2453..ad4a5f9ac6fb80 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -64,10 +64,16 @@
 // NEOVERSE-V1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-v1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-v2  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V2 %s
 // NEOVERSE-V2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-v2"
+// RUN: %clang --target=aarch64 -mcpu=neoverse-v3  -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-V3 %s
+// NEOVERSE-V3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-v3"
+// RUN: %clang --target=aarch64 -mcpu=neoverse-v3ae  -### -c %s 2>&1 | 
FileCheck -check-prefix=NEOVERSE-V3AE %s
+// NEOVERSE-V3AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-v3ae"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-n1 -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-N1 %s
 // NEOVERSE-N1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n1"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-N2 %s
 // NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n2"
+// RUN: %clang --target=aarch64 -mcpu=neoverse-n3 -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-N3 %s
+// NEOVERSE-N3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n3"
 // RUN: %clang --target=aarch64 -mcpu=neoverse-512tvb -### -c %s 2>&1 | 
FileCheck -check-prefix=NEOVERSE-512TVB %s
 // NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-512tvb"
 // RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A520 %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 9c91c4157cd6a0..21d80b7134508f 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, 
cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, 
neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, 
apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, 
apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, 
exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, 
thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, 
carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-

[clang] [llvm] [AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (PR #90143)

2024-04-26 Thread Jonathan Thackray via cfe-commits



@@ -447,6 +447,16 @@ def TuneNeoverseN2 : SubtargetFeature<"neoversen2", 
"ARMProcFamily", "NeoverseN2
   FeatureEnableSelectOptimize,
   FeaturePredictableSelectIsExpensive]>;
 
+def TuneNeoverseN3 : SubtargetFeature<"neoversen3", "ARMProcFamily", 
"NeoverseN3",
+  "Neoverse N3 ARM processors", [
+  FeatureFuseAES,
+  FeaturePostRAScheduler,
+  FeatureCmpBccFusion,

jthackray wrote:

Thanks for the suggestion, Dave. I've removed the `FeatureCmpBccFusion` feature 
flag in a new commit, as we don't want performance to suffer.

https://github.com/llvm/llvm-project/pull/90143
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[clang] [llvm] [AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (PR #90143)

2024-04-26 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray closed 
https://github.com/llvm/llvm-project/pull/90143
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[clang] [llvm] main (PR #90439)

2024-04-29 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray created 
https://github.com/llvm/llvm-project/pull/90439

- Fix mismatches between function parameter definitions and declarations 
(#89512)
- Revert "[llvm][RISCV] Enable trailing fences for seq-cst stores by default 
(#87376)"
- Revert "[RISCV] Support RISCV Atomics ABI attributes (#84597)"
- [SelectionDAG] Treat CopyFromReg as freezing the value (#85932)
- [DAGCombiner] Do not always fold FREEZE over BUILD_VECTOR (#85932)
- [AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (#90143)
- [clang][X86] Fix -Wundef warning in cpuid.h (#89842)
- Add test cases for SELECT->AND miscompiles in DAGCombiner
- [M68k] Add support for MOVEQ instruction (#88542)
- [Transforms] Debug values are not remapped when cloning. (#87747)
- [RISCV][NFC] Future-proof reference to ISA manual in RISCVInstrInfoC.td
- [DAG] visitORCommutative - fold build_pair(not(x),not(y)) -> 
not(build_pair(x,y)) style patterns (#90050)
- [NFC][OpenACC] Remove stale FIXME comment in a test
- DAG: Simplify demanded bits for truncating atomic_store (#90113)
- [Offload] Remove remaining `__tgt_register_requires` references (#90198)
- Revert "[TableGen] Ignore inaccessible memory when checking pattern flags 
(#90061)"
- [SLP]Attempt to vectorize long stores, if short one failed.
- [mlir][MemRef] Add ExtractStridedMetadataOpCollapseShapeFolder (#89954)
- [mlir] Mark `isa/dyn_cast/cast/...` member functions deprecated. (#89998)
- [clang] Add test for CWG2149 "Brace elision and array length deduction" 
(#90079)
- [libc++][ranges] LWG3984: ranges::to's recursion branch may be ill-formed 
(#87964)
- [clang-tidy][NFC] Fix broken link in documentation of cert-env33-c (#90216)
- [mlir] Fix -Wdeprecated-declarations of cast in VCIXToLLVMIRTranslation.cpp 
(NFC)
- [mlir] Add sub-byte type emulation support for `memref.collapse_shape` 
(#89962)
- [MC] Rename temporary symbols of empty name to ".L0 " (#89693)
- [X86] Regenerate subreg-to-reg tests with update_llc_test_checks.py
- [C++17] Support __GCC_[CON|DE]STRUCTIVE_SIZE (#89446)
- [AArch64][SVE2] SVE2 NBSL instruction lowering. (#89732)
- [libc++][ranges] Exports operator|. (#90071)
- [NFC] update comments from an earlier version of SuffixTree (#89800)
- [scudo] Reflect the allowed values for M_DECAY_TIME on Android (#89114)
- [DXIL] Fix build warning (#90226)
- [OpenMP][AIX] Use syssmt() to get the number of SMTs per physical CPU (#89985)
- [RISCV] Flatten the ImpliedExts table in RISCVISAInfo.cpp (#89975)
- [LV] Add tests showing missed propgation of versiond stride values.
- [mlir][sparse] fold sparse convert into producer linalg op. (#8)
- [Arm64EC] Improve alignment mangling in arm64ec thunks. (#90115)
- [RISCV] Add an instruction PrettyPrinter to llvm-objdump (#90093)
- [APINotes] Allow annotating a C++ type as non-copyable in Swift
- [lldb] Switch to llvm::DWARFUnitHeader (#89808)
- [SLP]Fix PR90224: check that users of gep are all vectorized.
- [lldb] Fix typo in CumulativeSystemTimeIsValid check (#89680)
- [Libomptarget] Rename `libomptarget.rtl.x86_64` to `libomptarget.rtl.host` 
(#86868)
- [RISCV] Consistently use uint32_t in Disassembler decode functions. NFC
- [Driver,test] Replace CHECK-NOT: warning with -### -Werror
- [HLSL][SPIR-V] Target `directx` is required
- Revert "[mlir] Mark `isa/dyn_cast/cast/...` member functions deprecated. 
(#89998)" (#90250)
- [RISCV] Fix off by 1 typo in decodeVMaskReg. NFC
- Implement the DWARF 6 language and version attributes. (#89980)
- [AMDGPU] Support byte_sel modifier on v_cvt_sr_fp8_f32 and v_cvt_sr_bf8_f32 
(#90244)
- [ci] Add clang project dependency for bolt testing (#90262)
- [NFC] [HWASan] factor out debug record annotation (#90252)
- [lldb][sbapi] Fix API break in SBDebugger broadcast bits (#90261)
- [VPlan] Also propagate versioned strides to users via sext/zext.
- [flang][cuda] Avoid to issue data transfer in device context (#90247)
- [WebAssembly] Add half-precision feature (#90248)
- [BOLT][NFC] Use getEHFrameHdrSectionName() (#90257)
- [alpha.webkit.UncountedCallArgsChecker] Avoid emitting warnings for Ref, 
RefPtr, and their variants. (#90153)
- [ASan][Test] Remove hardcoded linker version from test (#90147)
- [AArch64] Add support for Cortex-R82AE and improve Cortex-R82


>From 16f06cb0d4b84a8084e963dc7d2036ead9446a87 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Sat, 27 Apr 2024 22:51:19 +0100
Subject: [PATCH] [AArch64] Add support for Cortex-R82AE and improve Cortex-R82

Cortex-R82AE is an Armv8R AArch64 CPU. Also, update Cortex-R82
feature flags to be more accurate.

Technical Reference Manual for Cortex-R82AE:
   https://developer.arm.com/documentation/101550/latest/
---
 clang/docs/ReleaseNotes.rst |  1 +
 clang/test/Misc/target-invalid-cpu-note.c   |  4 ++--
 llvm/docs/ReleaseNotes.rst  |  2 +-
 .../llvm/TargetParser/AArch64TargetParser.h | 13 -
 llvm/lib/Target/AArch64/AArch64Processors.td| 15 ++-
 ll

[clang] [llvm] main (PR #90439)

2024-04-29 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray closed 
https://github.com/llvm/llvm-project/pull/90439
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[clang] [llvm] [AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (PR #90440)

2024-04-29 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray created 
https://github.com/llvm/llvm-project/pull/90440

- Fix mismatches between function parameter definitions and declarations 
(#89512)
- Revert "[llvm][RISCV] Enable trailing fences for seq-cst stores by default 
(#87376)"
- Revert "[RISCV] Support RISCV Atomics ABI attributes (#84597)"
- [SelectionDAG] Treat CopyFromReg as freezing the value (#85932)
- [DAGCombiner] Do not always fold FREEZE over BUILD_VECTOR (#85932)
- [AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (#90143)
- [clang][X86] Fix -Wundef warning in cpuid.h (#89842)
- Add test cases for SELECT->AND miscompiles in DAGCombiner
- [M68k] Add support for MOVEQ instruction (#88542)
- [Transforms] Debug values are not remapped when cloning. (#87747)
- [RISCV][NFC] Future-proof reference to ISA manual in RISCVInstrInfoC.td
- [DAG] visitORCommutative - fold build_pair(not(x),not(y)) -> 
not(build_pair(x,y)) style patterns (#90050)
- [NFC][OpenACC] Remove stale FIXME comment in a test
- DAG: Simplify demanded bits for truncating atomic_store (#90113)
- [Offload] Remove remaining `__tgt_register_requires` references (#90198)
- Revert "[TableGen] Ignore inaccessible memory when checking pattern flags 
(#90061)"
- [SLP]Attempt to vectorize long stores, if short one failed.
- [mlir][MemRef] Add ExtractStridedMetadataOpCollapseShapeFolder (#89954)
- [mlir] Mark `isa/dyn_cast/cast/...` member functions deprecated. (#89998)
- [clang] Add test for CWG2149 "Brace elision and array length deduction" 
(#90079)
- [libc++][ranges] LWG3984: ranges::to's recursion branch may be ill-formed 
(#87964)
- [clang-tidy][NFC] Fix broken link in documentation of cert-env33-c (#90216)
- [mlir] Fix -Wdeprecated-declarations of cast in VCIXToLLVMIRTranslation.cpp 
(NFC)
- [mlir] Add sub-byte type emulation support for `memref.collapse_shape` 
(#89962)
- [MC] Rename temporary symbols of empty name to ".L0 " (#89693)
- [X86] Regenerate subreg-to-reg tests with update_llc_test_checks.py
- [C++17] Support __GCC_[CON|DE]STRUCTIVE_SIZE (#89446)
- [AArch64][SVE2] SVE2 NBSL instruction lowering. (#89732)
- [libc++][ranges] Exports operator|. (#90071)
- [NFC] update comments from an earlier version of SuffixTree (#89800)
- [scudo] Reflect the allowed values for M_DECAY_TIME on Android (#89114)
- [DXIL] Fix build warning (#90226)
- [OpenMP][AIX] Use syssmt() to get the number of SMTs per physical CPU (#89985)
- [RISCV] Flatten the ImpliedExts table in RISCVISAInfo.cpp (#89975)
- [LV] Add tests showing missed propgation of versiond stride values.
- [mlir][sparse] fold sparse convert into producer linalg op. (#8)
- [Arm64EC] Improve alignment mangling in arm64ec thunks. (#90115)
- [RISCV] Add an instruction PrettyPrinter to llvm-objdump (#90093)
- [APINotes] Allow annotating a C++ type as non-copyable in Swift
- [lldb] Switch to llvm::DWARFUnitHeader (#89808)
- [SLP]Fix PR90224: check that users of gep are all vectorized.
- [lldb] Fix typo in CumulativeSystemTimeIsValid check (#89680)
- [Libomptarget] Rename `libomptarget.rtl.x86_64` to `libomptarget.rtl.host` 
(#86868)
- [RISCV] Consistently use uint32_t in Disassembler decode functions. NFC
- [Driver,test] Replace CHECK-NOT: warning with -### -Werror
- [HLSL][SPIR-V] Target `directx` is required
- Revert "[mlir] Mark `isa/dyn_cast/cast/...` member functions deprecated. 
(#89998)" (#90250)
- [RISCV] Fix off by 1 typo in decodeVMaskReg. NFC
- Implement the DWARF 6 language and version attributes. (#89980)
- [AMDGPU] Support byte_sel modifier on v_cvt_sr_fp8_f32 and v_cvt_sr_bf8_f32 
(#90244)
- [ci] Add clang project dependency for bolt testing (#90262)
- [NFC] [HWASan] factor out debug record annotation (#90252)
- [lldb][sbapi] Fix API break in SBDebugger broadcast bits (#90261)
- [VPlan] Also propagate versioned strides to users via sext/zext.
- [flang][cuda] Avoid to issue data transfer in device context (#90247)
- [WebAssembly] Add half-precision feature (#90248)
- [BOLT][NFC] Use getEHFrameHdrSectionName() (#90257)
- [alpha.webkit.UncountedCallArgsChecker] Avoid emitting warnings for Ref, 
RefPtr, and their variants. (#90153)
- [ASan][Test] Remove hardcoded linker version from test (#90147)
- [AArch64] Add support for Cortex-R82AE and improve Cortex-R82


>From 16f06cb0d4b84a8084e963dc7d2036ead9446a87 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Sat, 27 Apr 2024 22:51:19 +0100
Subject: [PATCH] [AArch64] Add support for Cortex-R82AE and improve Cortex-R82

Cortex-R82AE is an Armv8R AArch64 CPU. Also, update Cortex-R82
feature flags to be more accurate.

Technical Reference Manual for Cortex-R82AE:
   https://developer.arm.com/documentation/101550/latest/
---
 clang/docs/ReleaseNotes.rst |  1 +
 clang/test/Misc/target-invalid-cpu-note.c   |  4 ++--
 llvm/docs/ReleaseNotes.rst  |  2 +-
 .../llvm/TargetParser/AArch64TargetParser.h | 13 -
 llvm/lib/Target/AArch64/AArch64Processors.td| 15 ++-
 ll

[clang] [llvm] [AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (PR #90440)

2024-04-29 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray closed 
https://github.com/llvm/llvm-project/pull/90440
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[clang] [llvm] [AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (PR #90440)

2024-04-29 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray reopened 
https://github.com/llvm/llvm-project/pull/90440
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[clang] [llvm] [AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (PR #90440)

2024-04-29 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray edited 
https://github.com/llvm/llvm-project/pull/90440
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[clang] [llvm] [AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (PR #90440)

2024-04-29 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/90440

>From 16f06cb0d4b84a8084e963dc7d2036ead9446a87 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Sat, 27 Apr 2024 22:51:19 +0100
Subject: [PATCH 1/2] [AArch64] Add support for Cortex-R82AE and improve
 Cortex-R82

Cortex-R82AE is an Armv8R AArch64 CPU. Also, update Cortex-R82
feature flags to be more accurate.

Technical Reference Manual for Cortex-R82AE:
   https://developer.arm.com/documentation/101550/latest/
---
 clang/docs/ReleaseNotes.rst |  1 +
 clang/test/Misc/target-invalid-cpu-note.c   |  4 ++--
 llvm/docs/ReleaseNotes.rst  |  2 +-
 .../llvm/TargetParser/AArch64TargetParser.h | 13 -
 llvm/lib/Target/AArch64/AArch64Processors.td| 15 ++-
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp|  1 +
 llvm/lib/TargetParser/Host.cpp  |  1 +
 .../unittests/TargetParser/TargetParserTest.cpp | 17 +++--
 8 files changed, 47 insertions(+), 7 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5d4d152b2eb540..c92d480023f4d4 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -645,6 +645,7 @@ Arm and AArch64 Support
 * Arm Cortex-A78AE (cortex-a78ae).
 * Arm Cortex-A520AE (cortex-a520ae).
 * Arm Cortex-A720AE (cortex-a720ae).
+* Arm Cortex-R82AE (cortex-r82ae).
 * Arm Neoverse-N3 (neoverse-n3).
 * Arm Neoverse-V3 (neoverse-v3).
 * Arm Neoverse-V3AE (neoverse-v3ae).
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 21d80b7134508f..768b243b04e3a3 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, 
cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, 
neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, 
neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, 
apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, 
apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, 
falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, 
thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, 
cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, 
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, 
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, 
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, 
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, 
apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, 
exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, 
thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, 
ampere1a, ampere1b, cobalt-100, grace{{$}}
 
 // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
-// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, 
cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, 
cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, 
cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, 
cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, 
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, 
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, 
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, 
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, 
apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, 
exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, 
thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, 
ampere1a, ampere1b, cobalt

[clang] [llvm] [AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (PR #90440)

2024-04-29 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/90440

>From 16f06cb0d4b84a8084e963dc7d2036ead9446a87 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Sat, 27 Apr 2024 22:51:19 +0100
Subject: [PATCH 1/3] [AArch64] Add support for Cortex-R82AE and improve
 Cortex-R82

Cortex-R82AE is an Armv8R AArch64 CPU. Also, update Cortex-R82
feature flags to be more accurate.

Technical Reference Manual for Cortex-R82AE:
   https://developer.arm.com/documentation/101550/latest/
---
 clang/docs/ReleaseNotes.rst |  1 +
 clang/test/Misc/target-invalid-cpu-note.c   |  4 ++--
 llvm/docs/ReleaseNotes.rst  |  2 +-
 .../llvm/TargetParser/AArch64TargetParser.h | 13 -
 llvm/lib/Target/AArch64/AArch64Processors.td| 15 ++-
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp|  1 +
 llvm/lib/TargetParser/Host.cpp  |  1 +
 .../unittests/TargetParser/TargetParserTest.cpp | 17 +++--
 8 files changed, 47 insertions(+), 7 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5d4d152b2eb540..c92d480023f4d4 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -645,6 +645,7 @@ Arm and AArch64 Support
 * Arm Cortex-A78AE (cortex-a78ae).
 * Arm Cortex-A520AE (cortex-a520ae).
 * Arm Cortex-A720AE (cortex-a720ae).
+* Arm Cortex-R82AE (cortex-r82ae).
 * Arm Neoverse-N3 (neoverse-n3).
 * Arm Neoverse-V3 (neoverse-v3).
 * Arm Neoverse-V3AE (neoverse-v3ae).
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 21d80b7134508f..768b243b04e3a3 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, 
cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, 
neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, 
neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, 
apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, 
apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, 
falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, 
thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, 
cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, 
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, 
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, 
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, 
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, 
apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, 
exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, 
thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, 
ampere1a, ampere1b, cobalt-100, grace{{$}}
 
 // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
-// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, 
cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, 
cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, 
cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, 
cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, 
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, 
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, 
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, 
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, 
apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, 
exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, 
thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, 
ampere1a, ampere1b, cobalt

[clang] [llvm] [AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (PR #90440)

2024-04-29 Thread Jonathan Thackray via cfe-commits



@@ -143,6 +143,7 @@ void AArch64Subtarget::initializeProperties(bool 
HasMinSize) {
   case CortexA78AE:
   case CortexA78C:
   case CortexR82:
+  case CortexR82AE:

jthackray wrote:

Thanks, done.

https://github.com/llvm/llvm-project/pull/90440
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[clang] [llvm] [AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (PR #90440)

2024-04-29 Thread Jonathan Thackray via cfe-commits



@@ -632,7 +632,18 @@ inline constexpr CpuInfo CpuInfos[] = {
AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
AArch64::AEK_PREDRES, AArch64::AEK_PROFILE})},
-{"cortex-r82", ARMV8R, AArch64::ExtensionBitset({AArch64::AEK_LSE})},
+{"cortex-r82", ARMV8R,
+ AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_DOTPROD,

jthackray wrote:

Thanks, good spot, yes these can be trimmed.

- AEK_FP is enabled for ARMV8A
- AEK_LSE is enabled for ARMV8_1A
- AEK_CRC is enabled for ARMV8_1A
- AEK_RDM is enabled for ARMV8_1A
- AEK_RAS is enabled for ARMV8_2A
- AEK_RCPC is enabled for ARMV8_3A
- AEK_PAUTH is enabled for ARMV8_3A
- AEK_DOTPROD is enabled for ARMV8_4A
- AEK_FLAGM doesn't default
- AEK_PERFMON doesn't default
- AEK_PREDRES doesn't default

ARMV8R inherits from ARMV8_5A.DefaultExts, so we only need the latter 3 flags.

Code now updated.



https://github.com/llvm/llvm-project/pull/90440
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[clang] [llvm] [AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (PR #90440)

2024-04-30 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/90440

>From 16f06cb0d4b84a8084e963dc7d2036ead9446a87 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Sat, 27 Apr 2024 22:51:19 +0100
Subject: [PATCH 1/4] [AArch64] Add support for Cortex-R82AE and improve
 Cortex-R82

Cortex-R82AE is an Armv8R AArch64 CPU. Also, update Cortex-R82
feature flags to be more accurate.

Technical Reference Manual for Cortex-R82AE:
   https://developer.arm.com/documentation/101550/latest/
---
 clang/docs/ReleaseNotes.rst |  1 +
 clang/test/Misc/target-invalid-cpu-note.c   |  4 ++--
 llvm/docs/ReleaseNotes.rst  |  2 +-
 .../llvm/TargetParser/AArch64TargetParser.h | 13 -
 llvm/lib/Target/AArch64/AArch64Processors.td| 15 ++-
 llvm/lib/Target/AArch64/AArch64Subtarget.cpp|  1 +
 llvm/lib/TargetParser/Host.cpp  |  1 +
 .../unittests/TargetParser/TargetParserTest.cpp | 17 +++--
 8 files changed, 47 insertions(+), 7 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5d4d152b2eb540..c92d480023f4d4 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -645,6 +645,7 @@ Arm and AArch64 Support
 * Arm Cortex-A78AE (cortex-a78ae).
 * Arm Cortex-A520AE (cortex-a520ae).
 * Arm Cortex-A720AE (cortex-a720ae).
+* Arm Cortex-R82AE (cortex-r82ae).
 * Arm Neoverse-N3 (neoverse-n3).
 * Arm Neoverse-V3 (neoverse-v3).
 * Arm Neoverse-V3AE (neoverse-v3ae).
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 21d80b7134508f..768b243b04e3a3 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, 
cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, 
neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, 
neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, 
apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, 
apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, 
falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, 
thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, 
cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, 
cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, 
cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-r82ae, cortex-x1, 
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, 
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, 
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, 
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, 
apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, 
exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, 
thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, 
ampere1a, ampere1b, cobalt-100, grace{{$}}
 
 // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
-// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, 
cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, 
cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, 
cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, 
cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, 
cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, 
neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, 
neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, 
apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, 
apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, 
exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, 
thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, 
ampere1a, ampere1b, cobalt

[clang] [llvm] [AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (PR #90440)

2024-04-30 Thread Jonathan Thackray via cfe-commits



@@ -632,7 +632,18 @@ inline constexpr CpuInfo CpuInfos[] = {
AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
AArch64::AEK_PREDRES, AArch64::AEK_PROFILE})},
-{"cortex-r82", ARMV8R, AArch64::ExtensionBitset({AArch64::AEK_LSE})},
+{"cortex-r82", ARMV8R,
+ AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_DOTPROD,

jthackray wrote:

Ah yes. Now definitely enabled in the latest commit.

https://github.com/llvm/llvm-project/pull/90440
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