[clang] 1179ef4 - [RISCV] Implement assembler support for XTHeadVdot

[Jojo R via cfe-commits]

Author: Jojo R
Date: 2022-12-26T18:32:42+08:00
New Revision: 1179ef46a34292179d3e7e8570d7342edd2dc27d

URL: 
https://github.com/llvm/llvm-project/commit/1179ef46a34292179d3e7e8570d7342edd2dc27d
DIFF: 
https://github.com/llvm/llvm-project/commit/1179ef46a34292179d3e7e8570d7342edd2dc27d.diff

LOG: [RISCV] Implement assembler support for XTHeadVdot

This patch implements the T-Head vendor extensions (XTHeadVdot),
which is documented here, it's based on standard vector extension v1.0:
  https://github.com/T-head-Semi/thead-extension-spec

Added: 
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
llvm/test/MC/RISCV/XTHeadVdot-valid.s

Modified: 
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/TargetParser/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/attributes.ll

Removed: 




diff  --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 8884b0989086d..7791703cbbe46 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -446,6 +446,10 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
 // CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 100{{$}}
 
+// RUN: %clang -target riscv64 -march=rv64ixtheadvdot -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADVDOT-EXT %s
+// CHECK-XTHEADVDOT-EXT: __riscv_xtheadvdot 100{{$}}
+
 // RUN: %clang -target riscv32 -march=rv32izcd0p70 
-menable-experimental-extensions \
 // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s
 // RUN: %clang -target riscv64 -march=rv64izcd0p70 
-menable-experimental-extensions \

diff  --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index aa39935153973..c5f947a76eb28 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -160,6 +160,9 @@ The current vendor extensions supported are:
 ``XVentanaCondOps``
   LLVM implements `version 1.0.0 of the VTx-family custom instructions 
specification 
`_
 by Ventana Micro Systems.  All instructions are prefixed with `vt.` as 
described in the specification, and the riscv-toolchai-convention document 
linked above.  These instructions are only available for riscv64 at this time.
 
+``XTHeadVdot``
+  LLVM implements `version 1.0.0 of the THeadV-family custom instructions 
specification 
`_
 by T-HEAD of Alibaba.  All instructions are prefixed with `th.` as described 
in the specification, and the riscv-toolchai-convention document linked above.
+
 
 Specification Documents
 ===

diff  --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 4a00e5045462b..42cdd755b5b42 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -474,6 +474,15 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, 
uint64_t &Size,
 return Result;
   }
 }
+if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadVdot]) {
+  LLVM_DEBUG(dbgs() << "Trying T-Head custom opcode table:\n");
+  Result =
+  decodeInstruction(DecoderTableTHeadV32, MI, Insn, Address, this, 
STI);
+  if (Result != MCDisassembler::Fail) {
+Size = 4;
+return Result;
+  }
+}
 
 LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
 Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);

diff  --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 2ba00bd7b7b72..c94d426fb72e3 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -445,6 +445,14 @@ def HasVendorXVentanaCondOps : 
Predicate<"Subtarget->hasVendorXVentanaCondOps()"
 AssemblerPredicate<(all_of 
FeatureVendorXVentanaCondOps),
 "'XVentanaCondOps' (Ventana Conditional Ops)">;
 
+def FeatureVendorXTHeadVdot
+: SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true",
+   "'xtheadvdot' (T-Head Vector Extensions for Dot)",
+   [FeatureStdExtV]>;
+def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
+AssemblerPredicate<(all_of 
FeatureVendorXTHeadVdot),
+"'xtheadvdot' (T-Head Vector Extensions 
for Dot)">;
+
 
//===--===//
 // L

[clang] 54752f3 - [RISCV] Implement assembler support for XTHeadVdot

[Jojo R via cfe-commits]

Author: Jojo R
Date: 2022-12-26T19:05:22+08:00
New Revision: 54752f3ff6d50944f17c260a6dc47a4758a026fc

URL: 
https://github.com/llvm/llvm-project/commit/54752f3ff6d50944f17c260a6dc47a4758a026fc
DIFF: 
https://github.com/llvm/llvm-project/commit/54752f3ff6d50944f17c260a6dc47a4758a026fc.diff

LOG: [RISCV] Implement assembler support for XTHeadVdot

This patch implements the T-Head vendor extensions (XTHeadVdot),
which is documented here, it's based on standard vector extension v1.0:
  https://github.com/T-head-Semi/thead-extension-spec

Added: 
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
llvm/test/MC/RISCV/XTHeadVdot-valid.s

Modified: 
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/TargetParser/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/attributes.ll

Removed: 




diff  --git a/clang/test/Preprocessor/riscv-target-features.c 
b/clang/test/Preprocessor/riscv-target-features.c
index 8884b0989086d..7791703cbbe46 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -446,6 +446,10 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
 // CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 100{{$}}
 
+// RUN: %clang -target riscv64 -march=rv64ixtheadvdot -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADVDOT-EXT %s
+// CHECK-XTHEADVDOT-EXT: __riscv_xtheadvdot 100{{$}}
+
 // RUN: %clang -target riscv32 -march=rv32izcd0p70 
-menable-experimental-extensions \
 // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s
 // RUN: %clang -target riscv64 -march=rv64izcd0p70 
-menable-experimental-extensions \

diff  --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index aa39935153973..c5f947a76eb28 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -160,6 +160,9 @@ The current vendor extensions supported are:
 ``XVentanaCondOps``
   LLVM implements `version 1.0.0 of the VTx-family custom instructions 
specification 
`_
 by Ventana Micro Systems.  All instructions are prefixed with `vt.` as 
described in the specification, and the riscv-toolchai-convention document 
linked above.  These instructions are only available for riscv64 at this time.
 
+``XTHeadVdot``
+  LLVM implements `version 1.0.0 of the THeadV-family custom instructions 
specification 
`_
 by T-HEAD of Alibaba.  All instructions are prefixed with `th.` as described 
in the specification, and the riscv-toolchai-convention document linked above.
+
 
 Specification Documents
 ===

diff  --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 4a00e5045462b..42cdd755b5b42 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -474,6 +474,15 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, 
uint64_t &Size,
 return Result;
   }
 }
+if (STI.getFeatureBits()[RISCV::FeatureVendorXTHeadVdot]) {
+  LLVM_DEBUG(dbgs() << "Trying T-Head custom opcode table:\n");
+  Result =
+  decodeInstruction(DecoderTableTHeadV32, MI, Insn, Address, this, 
STI);
+  if (Result != MCDisassembler::Fail) {
+Size = 4;
+return Result;
+  }
+}
 
 LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
 Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);

diff  --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 2ba00bd7b7b72..c94d426fb72e3 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -445,6 +445,14 @@ def HasVendorXVentanaCondOps : 
Predicate<"Subtarget->hasVendorXVentanaCondOps()"
 AssemblerPredicate<(all_of 
FeatureVendorXVentanaCondOps),
 "'XVentanaCondOps' (Ventana Conditional Ops)">;
 
+def FeatureVendorXTHeadVdot
+: SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true",
+   "'xtheadvdot' (T-Head Vector Extensions for Dot)",
+   [FeatureStdExtV]>;
+def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
+AssemblerPredicate<(all_of 
FeatureVendorXTHeadVdot),
+"'xtheadvdot' (T-Head Vector Extensions 
for Dot)">;
+
 
//===--===//
 // L