[PATCH] D129542: [CodeGen] Add codegen of IR function attribute fine_grained_bitfields

[John McIver via Phabricator via cfe-commits]

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This change helps to prevents mixing fine grained and non fine grained bit-field
addressing schemes, which can result in incorrect poison state at
initialization. The IR function attribute fine_grained_bitfields is only added
when fine grained bitfield accesses are enable. The attribute is used by opt to
prevent inlining.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129542

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CodeGenFunction.cpp
  clang/test/CodeGen/fine-grained-bitfield-accesses.c


Index: clang/test/CodeGen/fine-grained-bitfield-accesses.c
===
--- /dev/null
+++ clang/test/CodeGen/fine-grained-bitfield-accesses.c
@@ -0,0 +1,21 @@
+// RUN: %clang -ffine-grained-bitfield-accesses -S -emit-llvm -o - %s | 
FileCheck %s
+// CHECK: define{{.*}} @g(){{.*}} #[[GATTR:[0-9]+]] {
+// CHECK: declare{{.*}} void @f(ptr noundef){{.*}} #[[FATTR:[0-9]+]]
+// CHECK: attributes #[[GATTR]] = {{.*}} fine_grained_bitfields {{.*}}
+// CHECK: attributes #[[FATTR]] = {{.*}} fine_grained_bitfields {{.*}}
+//
+// Verify that the clang fine-grained-bitfield-accesses option adds the IR
+// function attribute fine_grained_bitfields.
+struct X {
+  int a : 8;
+  int b : 24;
+};
+
+void f(struct X*);
+
+int g() {
+  struct X x;
+  x.a = 10;
+  f(&x);
+  return x.a;
+}
Index: clang/lib/CodeGen/CodeGenFunction.cpp
===
--- clang/lib/CodeGen/CodeGenFunction.cpp
+++ clang/lib/CodeGen/CodeGenFunction.cpp
@@ -984,6 +984,11 @@
 Fn->addFnAttr(llvm::Attribute::StrictFP);
   }
 
+  // The fine grained bit-fields attribute is used to determine IPO inlining
+  // compatibility.
+  if (getTypes().getCodeGenOpts().FineGrainedBitfieldAccesses)
+Fn->addFnAttr(llvm::Attribute::FineGrainedBitfields);
+
   // If a custom alignment is used, force realigning to this alignment on
   // any main function which certainly will need it.
   if (FD && ((FD->isMain() || FD->isMSVCRTEntryPoint()) &&
Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -1890,6 +1890,9 @@
 if (CodeGenOpts.SpeculativeLoadHardening)
   FuncAttrs.addAttribute(llvm::Attribute::SpeculativeLoadHardening);
 
+if (getTypes().getCodeGenOpts().FineGrainedBitfieldAccesses)
+  FuncAttrs.addAttribute(llvm::Attribute::FineGrainedBitfields);
+
 // Add zero-call-used-regs attribute.
 switch (CodeGenOpts.getZeroCallUsedRegs()) {
 case llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind::Skip:


Index: clang/test/CodeGen/fine-grained-bitfield-accesses.c
===
--- /dev/null
+++ clang/test/CodeGen/fine-grained-bitfield-accesses.c
@@ -0,0 +1,21 @@
+// RUN: %clang -ffine-grained-bitfield-accesses -S -emit-llvm -o - %s | FileCheck %s
+// CHECK: define{{.*}} @g(){{.*}} #[[GATTR:[0-9]+]] {
+// CHECK: declare{{.*}} void @f(ptr noundef){{.*}} #[[FATTR:[0-9]+]]
+// CHECK: attributes #[[GATTR]] = {{.*}} fine_grained_bitfields {{.*}}
+// CHECK: attributes #[[FATTR]] = {{.*}} fine_grained_bitfields {{.*}}
+//
+// Verify that the clang fine-grained-bitfield-accesses option adds the IR
+// function attribute fine_grained_bitfields.
+struct X {
+  int a : 8;
+  int b : 24;
+};
+
+void f(struct X*);
+
+int g() {
+  struct X x;
+  x.a = 10;
+  f(&x);
+  return x.a;
+}
Index: clang/lib/CodeGen/CodeGenFunction.cpp
===
--- clang/lib/CodeGen/CodeGenFunction.cpp
+++ clang/lib/CodeGen/CodeGenFunction.cpp
@@ -984,6 +984,11 @@
 Fn->addFnAttr(llvm::Attribute::StrictFP);
   }
 
+  // The fine grained bit-fields attribute is used to determine IPO inlining
+  // compatibility.
+  if (getTypes().getCodeGenOpts().FineGrainedBitfieldAccesses)
+Fn->addFnAttr(llvm::Attribute::FineGrainedBitfields);
+
   // If a custom alignment is used, force realigning to this alignment on
   // any main function which certainly will need it.
   if (FD && ((FD->isMain() || FD->isMSVCRTEntryPoint()) &&
Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -1890,6 +1890,9 @@
 if (CodeGenOpts.SpeculativeLoadHardening)
   FuncAttrs.addAttribute(llvm::Attribute::SpeculativeLoadHardening);
 
+if (getTypes().getCodeGenOpts().FineGrainedBitfieldAccesses)
+  FuncAttrs.addAttribute(llvm::Attribute::FineGrainedBitfields);
+
 // Add zero-call-used-regs attribute.
 switch (CodeGenOpts.getZeroCallUsedRegs()) {
 case llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind::Skip:
_

[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary)

[John McIver via Phabricator via cfe-commits]

jmciver added inline comments.



Comment at: clang/lib/CodeGen/CGExpr.cpp:1746
 
+  if (auto TyPtr = Ty.getTypePtrOrNull()) {
+if (!(TyPtr->isSpecificBuiltinType(BuiltinType::UChar) ||

vitalybuka wrote:
> Taking into account potantial risks from pre-existing UB, I believe we need 
> clang switch to be able to shutdown this branch, similar to 
> enable_noundef_analysis.
> User with large code bases maybe need some time for transition.
> 
> I have no opinion if this should be ON or OFF by default
A flag is a good idea; I'll go ahead and add that. We can determine the default 
later, for now I would like to default to `on` to see/show the effects. Anyone 
feel free to let me know if you have reasoning otherwise.

For the flag name: `enable_noundef_loads`?


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[PATCH] D136546: [clang][unittest] Resolve ClangSupportTest link time errors

[John McIver via Phabricator via cfe-commits]

jmciver created this revision.
Herald added a project: All.
jmciver added reviewers: Izaron, Ericson2314, thieta, tstellar.
jmciver published this revision for review.
Herald added a project: clang.
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Resolves undefined references to vtable for clang::ASTConsumer,
PCHContainerOperations::PCHContainerOperations(), and
CodeGenOptions::CodeGenOptions().


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136546

Files:
  clang/unittests/Support/CMakeLists.txt


Index: clang/unittests/Support/CMakeLists.txt
===
--- clang/unittests/Support/CMakeLists.txt
+++ clang/unittests/Support/CMakeLists.txt
@@ -8,5 +8,8 @@
 
 clang_target_link_libraries(ClangSupportTests
   PRIVATE
+  clangAST
+  clangBasic
   clangFrontend
+  clangSerialization
   )


Index: clang/unittests/Support/CMakeLists.txt
===
--- clang/unittests/Support/CMakeLists.txt
+++ clang/unittests/Support/CMakeLists.txt
@@ -8,5 +8,8 @@
 
 clang_target_link_libraries(ClangSupportTests
   PRIVATE
+  clangAST
+  clangBasic
   clangFrontend
+  clangSerialization
   )
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[PATCH] D136546: [clang][unittest] Resolve ClangSupportTest link time errors

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

Added GitHub issue 58553 , 
which provides the full error message and repeatability information.

If this patch is accepted can someone please commit on my behalf?

- User name: `John McIver`
- User email: `john.mciver@gmail.com`


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[PATCH] D136546: [clang][unittest] Resolve ClangSupportTest link time errors

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

Thanks @Izaron for taking the time to review and commit on my behalf!


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[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary)

[John McIver via Phabricator via cfe-commits]

jmciver updated this revision to Diff 471708.
jmciver added a comment.

Updating D134410 : [clang][CodeGen] Add 
noundef metadata to load instructions (preliminary)

Add flag -enable-noundef-load-analysis and rebase with main. Refactored noundef
metadata functionality into anonymous function to be used by additional patches.


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Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/CGExpr.cpp
  clang/test/CodeGen/X86/avx-builtins.c
  clang/test/CodeGen/X86/avx512bw-builtins.c
  clang/test/CodeGen/X86/avx512f-builtins.c
  clang/test/CodeGen/X86/avx512fp16-builtins.c
  clang/test/CodeGen/X86/avx512vl-builtins.c
  clang/test/CodeGen/X86/avx512vlbw-builtins.c
  clang/test/CodeGen/X86/sse-builtins.c
  clang/test/CodeGen/X86/sse2-builtins.c
  clang/test/CodeGen/aarch64-ls64-inline-asm.c
  clang/test/CodeGen/aarch64-ls64.c
  clang/test/CodeGen/memcpy-inline-builtin.c
  clang/test/CodeGen/tbaa-array.cpp
  clang/test/CodeGen/tbaa-base.cpp
  clang/test/CodeGen/tbaa.cpp
  clang/test/CodeGen/ubsan-pass-object-size.c
  clang/test/CodeGenCXX/attr-likelihood-if-branch-weights.cpp
  clang/test/CodeGenCXX/attr-likelihood-switch-branch-weights.cpp
  clang/test/CodeGenCXX/builtin-bit-cast-no-tbaa.cpp
  clang/test/CodeGenCXX/debug-info-line.cpp
  clang/test/CodeGenCXX/pr12251.cpp
  clang/test/CodeGenCXX/pragma-followup_inner.cpp
  clang/test/OpenMP/cancel_codegen.cpp
  clang/test/OpenMP/cancellation_point_codegen.cpp
  clang/test/OpenMP/distribute_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp
  clang/test/OpenMP/distribute_simd_codegen.cpp
  clang/test/OpenMP/distribute_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_simd_reduction_codegen.cpp
  clang/test/OpenMP/for_reduction_task_codegen.cpp
  clang/test/OpenMP/irbuilder_safelen.cpp
  clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
  clang/test/OpenMP/irbuilder_simdlen.cpp
  clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
  clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp
  clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
  clang/test/OpenMP/ordered_codegen.cpp
  clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_aligned_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp
  clang/test/OpenMP/sections_reduction_task_codegen.cpp
  clang/test/OpenMP/target_defaultmap_codegen_01.cpp
  clang/test/OpenMP/target_in_reduction_codegen.cpp
  clang/test/OpenMP/target_is_device_ptr_codegen.cpp
  clang/test/OpenMP/target_map_codegen_00.cpp
  clang/test/OpenMP/target_map_codegen_01.cpp
  clang/test/OpenMP/target_map_codegen_02.cpp
  clang/test/OpenMP/target_map_codegen_04.cpp
  clang/test/OpenMP/target_map_codegen_05.cpp
  clang/test/OpenMP/target_map_codegen_07.cpp
  clang/test/OpenMP/target_map_codegen_11.cpp
  clang/test/OpenMP/target_map_codegen_13.cpp
  clang/test/OpenMP/target_map_codegen_14.cpp
  clang/test/OpenMP/target_map_codegen_15.cpp
  clang/test/OpenMP/target_map_codegen_17.cpp
  clang/test/OpenMP/target_map_codegen_26.cpp
  clang/test/OpenMP/target_map_codegen_27.cpp
  clang/test/OpenMP/target_map_codegen_29.cpp
  clang/test/OpenMP/target_parallel_codegen.cpp
  clang/test/OpenMP/target_parallel_for_codegen.cpp
  clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
  clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/target_teams_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp
  clang/test/OpenMP/target_teams_di

[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary)

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

I'll start fixing reported test failures tomorrow.


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[PATCH] D137005: [clang][CodeGen] Add noundef metadata to load insturctions (preliminary 2 of 2)

[John McIver via Phabricator via cfe-commits]

jmciver created this revision.
jmciver added reviewers: nikic, efriedma, aqjune, rjmccall, jdoerfert, 
vitalybuka.
Herald added a project: All.
jmciver retitled this revision from "[clang][CodeGen] Add noundef metadata to 
scalar load insturctions (preliminary 2 of 2)" to "[clang][CodeGen] Add noundef 
metadata to load insturctions (preliminary 2 of 2)".
jmciver published this revision for review.
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Add support for scalar elements of ext_vector_type


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137005

Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/test/CodeGenCXX/vector-noundef.cpp

Index: clang/test/CodeGenCXX/vector-noundef.cpp
===
--- /dev/null
+++ clang/test/CodeGenCXX/vector-noundef.cpp
@@ -0,0 +1,84 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -std=c++17 -triple x86_64-gnu-linux -O0 -enable-noundef-load-analysis -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -std=c++17 -triple x86_64-gnu-linux -O0 -no-enable-noundef-load-analysis -emit-llvm -o - %s | FileCheck %s --check-prefix=DISABLE
+
+using VecOfFourBools __attribute__((ext_vector_type(4))) = bool;
+using VecOfThreeChars __attribute__((ext_vector_type(3))) = char;
+using VecOfThreeUChars __attribute__((ext_vector_type(3))) = unsigned char;
+
+// CHECK-LABEL: @_Z15getElement4BoolRDv4_b(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT:store ptr [[A:%.*]], ptr [[A_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// CHECK-NEXT:[[LOAD_BITS:%.*]] = load i8, ptr [[TMP0]], align 1, !noundef [[NOUNDEF2:![0-9]+]]
+// CHECK-NEXT:[[TMP1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>
+// CHECK-NEXT:[[EXTRACTVEC:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> poison, <4 x i32> 
+// CHECK-NEXT:[[VECEXT:%.*]] = extractelement <4 x i1> [[EXTRACTVEC]], i32 0
+// CHECK-NEXT:ret i1 [[VECEXT]]
+//
+// DISABLE-LABEL: @_Z15getElement4BoolRDv4_b(
+// DISABLE-NEXT:  entry:
+// DISABLE-NEXT:[[A_ADDR:%.*]] = alloca ptr, align 8
+// DISABLE-NEXT:store ptr [[A:%.*]], ptr [[A_ADDR]], align 8
+// DISABLE-NEXT:[[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// DISABLE-NEXT:[[LOAD_BITS:%.*]] = load i8, ptr [[TMP0]], align 1
+// DISABLE-NEXT:[[TMP1:%.*]] = bitcast i8 [[LOAD_BITS]] to <8 x i1>
+// DISABLE-NEXT:[[EXTRACTVEC:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> poison, <4 x i32> 
+// DISABLE-NEXT:[[VECEXT:%.*]] = extractelement <4 x i1> [[EXTRACTVEC]], i32 0
+// DISABLE-NEXT:ret i1 [[VECEXT]]
+//
+bool getElement4Bool(VecOfFourBools& a)
+{
+  return a[0];
+}
+
+// CHECK-LABEL: @_Z15getElement3CharRDv3_c(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT:store ptr [[A:%.*]], ptr [[A_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// CHECK-NEXT:[[LOADVEC4:%.*]] = load <4 x i8>, ptr [[TMP0]], align 4, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:[[EXTRACTVEC:%.*]] = shufflevector <4 x i8> [[LOADVEC4]], <4 x i8> poison, <3 x i32> 
+// CHECK-NEXT:[[VECEXT:%.*]] = extractelement <3 x i8> [[EXTRACTVEC]], i32 0
+// CHECK-NEXT:ret i8 [[VECEXT]]
+//
+// DISABLE-LABEL: @_Z15getElement3CharRDv3_c(
+// DISABLE-NEXT:  entry:
+// DISABLE-NEXT:[[A_ADDR:%.*]] = alloca ptr, align 8
+// DISABLE-NEXT:store ptr [[A:%.*]], ptr [[A_ADDR]], align 8
+// DISABLE-NEXT:[[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// DISABLE-NEXT:[[LOADVEC4:%.*]] = load <4 x i8>, ptr [[TMP0]], align 4
+// DISABLE-NEXT:[[EXTRACTVEC:%.*]] = shufflevector <4 x i8> [[LOADVEC4]], <4 x i8> poison, <3 x i32> 
+// DISABLE-NEXT:[[VECEXT:%.*]] = extractelement <3 x i8> [[EXTRACTVEC]], i32 0
+// DISABLE-NEXT:ret i8 [[VECEXT]]
+//
+char getElement3Char(VecOfThreeChars& a)
+{
+  return a[0];
+}
+
+// CHECK-LABEL: @_Z16getElement3UCharRDv3_h(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT:store ptr [[A:%.*]], ptr [[A_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// CHECK-NEXT:[[LOADVEC4:%.*]] = load <4 x i8>, ptr [[TMP0]], align 4
+// CHECK-NEXT:[[EXTRACTVEC:%.*]] = shufflevector <4 x i8> [[LOADVEC4]], <4 x i8> poison, <3 x i32> 
+// CHECK-NEXT:[[VECEXT:%.*]] = extractelement <3 x i8> [[EXTRACTVEC]], i32 0
+// CHECK-NEXT:ret i8 [[VECEXT]]
+//
+// DISABLE-LABEL: @_Z16getElement3UCharRDv3_h(
+// DISABLE-NEXT:  entry:
+// DISABLE-NEXT:[[A_ADDR:%.*]] = alloca ptr, align 8
+// DISABLE-NEXT:store ptr [[A:%.*]], ptr [[A_ADDR]], align 8
+// DISABLE-NEXT:[[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
+// DISABLE-NEXT:[[LOADVEC4:%.*]] = load <4 x i8>, ptr [[TMP0]], align 4
+// DISABLE-NEXT:[[EXTRACTVEC:%.*]] = shufflevector <4 x i8> [

[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary 1 or 2)

[John McIver via Phabricator via cfe-commits]

jmciver updated this revision to Diff 471878.
jmciver added a comment.
Herald added subscribers: kosarev, kerbowa, jvesely.

Updating D134410 : [clang][CodeGen] Add 
noundef metadata to load instructions (preliminary 1 or 2)

Fix AMD-GPU, ARM, PowerPC, and new OpenMP tests.


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Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/CGExpr.cpp
  clang/test/CodeGen/X86/avx-builtins.c
  clang/test/CodeGen/X86/avx512bw-builtins.c
  clang/test/CodeGen/X86/avx512f-builtins.c
  clang/test/CodeGen/X86/avx512fp16-builtins.c
  clang/test/CodeGen/X86/avx512vl-builtins.c
  clang/test/CodeGen/X86/avx512vlbw-builtins.c
  clang/test/CodeGen/X86/sse-builtins.c
  clang/test/CodeGen/X86/sse2-builtins.c
  clang/test/CodeGen/aarch64-ls64-inline-asm.c
  clang/test/CodeGen/aarch64-ls64.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/memcpy-inline-builtin.c
  clang/test/CodeGen/tbaa-array.cpp
  clang/test/CodeGen/tbaa-base.cpp
  clang/test/CodeGen/tbaa.cpp
  clang/test/CodeGen/ubsan-pass-object-size.c
  clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
  clang/test/CodeGenCXX/attr-likelihood-if-branch-weights.cpp
  clang/test/CodeGenCXX/attr-likelihood-switch-branch-weights.cpp
  clang/test/CodeGenCXX/builtin-bit-cast-no-tbaa.cpp
  clang/test/CodeGenCXX/debug-info-line.cpp
  clang/test/CodeGenCXX/pr12251.cpp
  clang/test/CodeGenCXX/pragma-followup_inner.cpp
  clang/test/OpenMP/cancel_codegen.cpp
  clang/test/OpenMP/cancellation_point_codegen.cpp
  clang/test/OpenMP/distribute_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp
  clang/test/OpenMP/distribute_simd_codegen.cpp
  clang/test/OpenMP/distribute_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_simd_reduction_codegen.cpp
  clang/test/OpenMP/for_reduction_task_codegen.cpp
  clang/test/OpenMP/irbuilder_safelen.cpp
  clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
  clang/test/OpenMP/irbuilder_simd_aligned.cpp
  clang/test/OpenMP/irbuilder_simdlen.cpp
  clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
  clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp
  clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
  clang/test/OpenMP/ordered_codegen.cpp
  clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_aligned_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp
  clang/test/OpenMP/sections_reduction_task_codegen.cpp
  clang/test/OpenMP/target_defaultmap_codegen_01.cpp
  clang/test/OpenMP/target_in_reduction_codegen.cpp
  clang/test/OpenMP/target_is_device_ptr_codegen.cpp
  clang/test/OpenMP/target_map_codegen_00.cpp
  clang/test/OpenMP/target_map_codegen_01.cpp
  clang/test/OpenMP/target_map_codegen_02.cpp
  clang/test/OpenMP/target_map_codegen_04.cpp
  clang/test/OpenMP/target_map_codegen_05.cpp
  clang/test/OpenMP/target_map_codegen_07.cpp
  clang/test/OpenMP/target_map_codegen_11.cpp
  clang/test/OpenMP/target_map_codegen_13.cpp
  clang/test/OpenMP/target_map_codegen_14.cpp
  clang/test/OpenMP/target_map_codegen_15.cpp
  clang/test/OpenMP/target_map_codegen_17.cpp
  clang/test/OpenMP/target_map_codegen_26.cpp
  clang/test/OpenMP/target_map_codegen_27.cpp
  clang/test/OpenMP/target_map_codegen_29.cpp
  clang/test/OpenMP/target_parallel_codegen.cpp
  clang/test/OpenMP/target_parallel_for_codegen.cpp
  clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
  clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/target_teams_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_pa

[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary 1 or 2)

[John McIver via Phabricator via cfe-commits]

jmciver updated this revision to Diff 472051.
jmciver added a comment.

Updating D134410 : [clang][CodeGen] Add 
noundef metadata to load instructions (preliminary 1 or 2)

Refactor local linkage function, applyNoundefToLoadInst, to use static rather
than an anonymous namespace as per LLVM coding standards.


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Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/CGExpr.cpp
  clang/test/CodeGen/X86/avx-builtins.c
  clang/test/CodeGen/X86/avx512bw-builtins.c
  clang/test/CodeGen/X86/avx512f-builtins.c
  clang/test/CodeGen/X86/avx512fp16-builtins.c
  clang/test/CodeGen/X86/avx512vl-builtins.c
  clang/test/CodeGen/X86/avx512vlbw-builtins.c
  clang/test/CodeGen/X86/sse-builtins.c
  clang/test/CodeGen/X86/sse2-builtins.c
  clang/test/CodeGen/aarch64-ls64-inline-asm.c
  clang/test/CodeGen/aarch64-ls64.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/memcpy-inline-builtin.c
  clang/test/CodeGen/tbaa-array.cpp
  clang/test/CodeGen/tbaa-base.cpp
  clang/test/CodeGen/tbaa.cpp
  clang/test/CodeGen/ubsan-pass-object-size.c
  clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
  clang/test/CodeGenCXX/attr-likelihood-if-branch-weights.cpp
  clang/test/CodeGenCXX/attr-likelihood-switch-branch-weights.cpp
  clang/test/CodeGenCXX/builtin-bit-cast-no-tbaa.cpp
  clang/test/CodeGenCXX/debug-info-line.cpp
  clang/test/CodeGenCXX/pr12251.cpp
  clang/test/CodeGenCXX/pragma-followup_inner.cpp
  clang/test/OpenMP/cancel_codegen.cpp
  clang/test/OpenMP/cancellation_point_codegen.cpp
  clang/test/OpenMP/distribute_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp
  clang/test/OpenMP/distribute_simd_codegen.cpp
  clang/test/OpenMP/distribute_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_simd_reduction_codegen.cpp
  clang/test/OpenMP/for_reduction_task_codegen.cpp
  clang/test/OpenMP/irbuilder_safelen.cpp
  clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
  clang/test/OpenMP/irbuilder_simd_aligned.cpp
  clang/test/OpenMP/irbuilder_simdlen.cpp
  clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
  clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp
  clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
  clang/test/OpenMP/ordered_codegen.cpp
  clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_aligned_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp
  clang/test/OpenMP/sections_reduction_task_codegen.cpp
  clang/test/OpenMP/target_defaultmap_codegen_01.cpp
  clang/test/OpenMP/target_in_reduction_codegen.cpp
  clang/test/OpenMP/target_is_device_ptr_codegen.cpp
  clang/test/OpenMP/target_map_codegen_00.cpp
  clang/test/OpenMP/target_map_codegen_01.cpp
  clang/test/OpenMP/target_map_codegen_02.cpp
  clang/test/OpenMP/target_map_codegen_04.cpp
  clang/test/OpenMP/target_map_codegen_05.cpp
  clang/test/OpenMP/target_map_codegen_07.cpp
  clang/test/OpenMP/target_map_codegen_11.cpp
  clang/test/OpenMP/target_map_codegen_13.cpp
  clang/test/OpenMP/target_map_codegen_14.cpp
  clang/test/OpenMP/target_map_codegen_15.cpp
  clang/test/OpenMP/target_map_codegen_17.cpp
  clang/test/OpenMP/target_map_codegen_26.cpp
  clang/test/OpenMP/target_map_codegen_27.cpp
  clang/test/OpenMP/target_map_codegen_29.cpp
  clang/test/OpenMP/target_parallel_codegen.cpp
  clang/test/OpenMP/target_parallel_for_codegen.cpp
  clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
  clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/target_teams_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
  
clang/test

[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary 1 or 2)

[John McIver via Phabricator via cfe-commits]

jmciver added inline comments.



Comment at: clang/lib/CodeGen/CGExpr.cpp:676
+namespace {
+void applyNoundefToLoadInst(bool enable, const clang::QualType &Ty,
+llvm::LoadInst *Load) {

tschuett wrote:
> Nit: You meant static.
Thank you for bringing that to my attention. I reviewed the [[ 
https://llvm.org/docs/CodingStandards.html#anonymous-namespaces | LLVM Coding 
Standards ]] guidance on the topic.


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[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary)

[John McIver via Phabricator via cfe-commits]

jmciver created this revision.
Herald added subscribers: mattd, asavonic, jdoerfert, pengfei.
Herald added a project: All.
jmciver retitled this revision from "[clang][CodeGen] Add noundef metadata to 
scalar load instructions" to "[clang][CodeGen] Add noundef metadata to scalar 
load instructions (preliminary)".
jmciver edited the summary of this revision.
jmciver retitled this revision from "[clang][CodeGen] Add noundef metadata to 
scalar load instructions (preliminary)" to "[clang][CodeGen] Add noundef 
metadata to load instructions (preliminary)".
jmciver edited the summary of this revision.
jmciver added reviewers: nikic, efriedma, aqjune, rjmccall.
jmciver published this revision for review.
Herald added a reviewer: jdoerfert.
Herald added subscribers: cfe-commits, pcwang-thead, sstefan1.
Herald added a project: clang.

This patch adds noundef metadata to scalar load instructions and is intended to 
gain implementation feedback before proceeding to adding noundef to other load 
types.

The intent is to apply noundef to scalar load instructions that are not of type:

- char (if the target system maps to unsigned char)
- unsigned char
- std::byte

These types are excluded because of their different indeterminate value 
semantics (I think this is correct, but need to ask someone).

Feedback is greatly appreciated.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134410

Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/test/CodeGen/X86/avx-builtins.c
  clang/test/CodeGen/X86/avx512bw-builtins.c
  clang/test/CodeGen/X86/avx512f-builtins.c
  clang/test/CodeGen/X86/avx512fp16-builtins.c
  clang/test/CodeGen/X86/avx512vl-builtins.c
  clang/test/CodeGen/X86/avx512vlbw-builtins.c
  clang/test/CodeGen/X86/sse-builtins.c
  clang/test/CodeGen/X86/sse2-builtins.c
  clang/test/CodeGen/aarch64-ls64-inline-asm.c
  clang/test/CodeGen/aarch64-ls64.c
  clang/test/CodeGen/memcpy-inline-builtin.c
  clang/test/CodeGen/tbaa-array.cpp
  clang/test/CodeGen/tbaa-base.cpp
  clang/test/CodeGen/tbaa.cpp
  clang/test/CodeGen/ubsan-pass-object-size.c
  clang/test/CodeGenCXX/attr-likelihood-if-branch-weights.cpp
  clang/test/CodeGenCXX/attr-likelihood-switch-branch-weights.cpp
  clang/test/CodeGenCXX/builtin-bit-cast-no-tbaa.cpp
  clang/test/CodeGenCXX/debug-info-line.cpp
  clang/test/CodeGenCXX/pr12251.cpp
  clang/test/CodeGenCXX/pragma-followup_inner.cpp
  clang/test/OpenMP/cancel_codegen.cpp
  clang/test/OpenMP/cancellation_point_codegen.cpp
  clang/test/OpenMP/distribute_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp
  clang/test/OpenMP/distribute_simd_codegen.cpp
  clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp
  clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp
  clang/test/OpenMP/distribute_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_simd_reduction_codegen.cpp
  clang/test/OpenMP/for_reduction_task_codegen.cpp
  clang/test/OpenMP/irbuilder_safelen.cpp
  clang/test/OpenMP/irbuilder_simdlen.cpp
  clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
  clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp
  clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
  clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp
  clang/test/OpenMP/ordered_codegen.cpp
  clang/test/OpenMP/parallel_for_codegen.cpp
  clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_aligned_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp
  clang/test/OpenMP/sections_reduction_task_codegen.cpp
  clang/test/OpenMP/target_defaultmap_codegen_01.cpp
  clang/test/OpenMP/target_in_reduction_codegen.cpp
  clang/test/OpenMP/target_is_device_ptr_codegen.cpp
  clang/test/OpenMP/target_map_codegen_00.cpp
  clang/test/OpenMP/target_map_codegen_01.cpp
  clang/test/OpenMP/target_map_codegen_02.cpp
  clang/test/OpenMP/target_map_codegen_04.cpp
  clang/test/OpenMP/target_map_codegen_05.cpp
  clang/test/OpenMP/target_map_codegen_07.cpp
  clang/test/OpenMP/target_map_codegen_11.cpp
  clang/test/Ope

[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary)

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

The regression and test-suite pass using a bootstrap build. I'll provide 
performance data tomorrow.


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[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary)

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

The following are results from test-suite execution. LHS is a main build 
(17dde371e773 
) and the 
RHS is main with patch applied. The `results-subset.txt` is absent of unit, 
micro, and torture tests. Execution runtime is comprised from three runs of the 
main and patched version combined using the `compare.py` `vs` argument (compare 
the minimums of the two sets). Compilation times are acquired from a single 
invocation of each type of build. I will gather more compile time runs this 
weekend.
F24671737: results-subset.txt 

F24671745: results-full.txt 


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[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary)

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

In D134410#3816881 , @vitalybuka 
wrote:

> Are these patches uploaded with arc tool?

Yes, the patches were uploaded with `arc`. The size of the patch was too large 
to use the web interface.


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[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary)

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

Decreased CPU loading during test-suite build did lower times in some 
instances, but not a lot.

F24724990: results-subset.txt 

F24725002: results-full.txt 


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[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary)

[John McIver via Phabricator via cfe-commits]

jmciver updated this revision to Diff 467690.
jmciver edited the summary of this revision.
jmciver added a comment.

Updating D134410 : [clang][CodeGen] Add 
noundef metadata to load instructions (preliminary)

Resolve merge conflicts due to the adoption of the ptr type in openmp tests.


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Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/test/CodeGen/X86/avx-builtins.c
  clang/test/CodeGen/X86/avx512bw-builtins.c
  clang/test/CodeGen/X86/avx512f-builtins.c
  clang/test/CodeGen/X86/avx512fp16-builtins.c
  clang/test/CodeGen/X86/avx512vl-builtins.c
  clang/test/CodeGen/X86/avx512vlbw-builtins.c
  clang/test/CodeGen/X86/sse-builtins.c
  clang/test/CodeGen/X86/sse2-builtins.c
  clang/test/CodeGen/aarch64-ls64-inline-asm.c
  clang/test/CodeGen/aarch64-ls64.c
  clang/test/CodeGen/memcpy-inline-builtin.c
  clang/test/CodeGen/tbaa-array.cpp
  clang/test/CodeGen/tbaa-base.cpp
  clang/test/CodeGen/tbaa.cpp
  clang/test/CodeGen/ubsan-pass-object-size.c
  clang/test/CodeGenCXX/attr-likelihood-if-branch-weights.cpp
  clang/test/CodeGenCXX/attr-likelihood-switch-branch-weights.cpp
  clang/test/CodeGenCXX/builtin-bit-cast-no-tbaa.cpp
  clang/test/CodeGenCXX/debug-info-line.cpp
  clang/test/CodeGenCXX/pr12251.cpp
  clang/test/CodeGenCXX/pragma-followup_inner.cpp
  clang/test/OpenMP/cancel_codegen.cpp
  clang/test/OpenMP/cancellation_point_codegen.cpp
  clang/test/OpenMP/distribute_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp
  clang/test/OpenMP/distribute_simd_codegen.cpp
  clang/test/OpenMP/distribute_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_simd_reduction_codegen.cpp
  clang/test/OpenMP/for_reduction_task_codegen.cpp
  clang/test/OpenMP/irbuilder_safelen.cpp
  clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
  clang/test/OpenMP/irbuilder_simdlen.cpp
  clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
  clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp
  clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
  clang/test/OpenMP/ordered_codegen.cpp
  clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_aligned_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp
  clang/test/OpenMP/sections_reduction_task_codegen.cpp
  clang/test/OpenMP/target_defaultmap_codegen_01.cpp
  clang/test/OpenMP/target_in_reduction_codegen.cpp
  clang/test/OpenMP/target_is_device_ptr_codegen.cpp
  clang/test/OpenMP/target_map_codegen_00.cpp
  clang/test/OpenMP/target_map_codegen_01.cpp
  clang/test/OpenMP/target_map_codegen_02.cpp
  clang/test/OpenMP/target_map_codegen_04.cpp
  clang/test/OpenMP/target_map_codegen_05.cpp
  clang/test/OpenMP/target_map_codegen_07.cpp
  clang/test/OpenMP/target_map_codegen_11.cpp
  clang/test/OpenMP/target_map_codegen_13.cpp
  clang/test/OpenMP/target_map_codegen_14.cpp
  clang/test/OpenMP/target_map_codegen_15.cpp
  clang/test/OpenMP/target_map_codegen_17.cpp
  clang/test/OpenMP/target_map_codegen_26.cpp
  clang/test/OpenMP/target_map_codegen_27.cpp
  clang/test/OpenMP/target_map_codegen_29.cpp
  clang/test/OpenMP/target_parallel_codegen.cpp
  clang/test/OpenMP/target_parallel_for_codegen.cpp
  clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
  clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/target_teams_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_proc_bind_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_simd_reduction_codegen.cpp
  clang/test/OpenMP/target_update_codegen.cpp
  clang/test/OpenMP/task_affinity_codegen.cp

[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary 1 or 5)

[John McIver via Phabricator via cfe-commits]

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As Nuno mentioned we are targeting the proposal for next week. I will update 
the ticket with the Discourse link once it becomes available.


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[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary 1 or 5)

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

The Discourse proposal is available: RFC Load Instruction: Uninitialized Memory 
Semantics 



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[PATCH] D127271: [pseudo] Fix link time undefined reference to llvm::EnableABIBreakingChecks

[John McIver via Phabricator via cfe-commits]

jmciver created this revision.
Herald added a subscriber: mgorny.
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When building in debug mode, ABI breaking assertion checks are enabled and
require linking against LLVMSupport.


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Files:
  clang-tools-extra/pseudo/lib/cxx/CMakeLists.txt


Index: clang-tools-extra/pseudo/lib/cxx/CMakeLists.txt
===
--- clang-tools-extra/pseudo/lib/cxx/CMakeLists.txt
+++ clang-tools-extra/pseudo/lib/cxx/CMakeLists.txt
@@ -6,4 +6,5 @@
 
   LINK_LIBS
   clangPseudoGrammar
+  LLVMSupport
   )


Index: clang-tools-extra/pseudo/lib/cxx/CMakeLists.txt
===
--- clang-tools-extra/pseudo/lib/cxx/CMakeLists.txt
+++ clang-tools-extra/pseudo/lib/cxx/CMakeLists.txt
@@ -6,4 +6,5 @@
 
   LINK_LIBS
   clangPseudoGrammar
+  LLVMSupport
   )
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[PATCH] D127271: [pseudo] Fix link time undefined reference to llvm::EnableABIBreakingChecks

[John McIver via Phabricator via cfe-commits]

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This patch is associated to: https://github.com/llvm/llvm-project/issues/55935


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[PATCH] D127271: [pseudo] Fix link time undefined reference to llvm::EnableABIBreakingChecks

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

Thanks @sammccall  for taking the time to review!

Can you please commit on my behalf?

Name: `John McIver`
Email: `john.mciver@gmail.com`


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[PATCH] D127271: [pseudo] Fix link time undefined reference to llvm::EnableABIBreakingChecks

[John McIver via Phabricator via cfe-commits]

jmciver closed this revision.
jmciver added a comment.

Obsoleted by D127269 .


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[PATCH] D155773: [llvm][MemoryBuiltins] Add alloca support to getInitialValueOfAllocation

[John McIver via Phabricator via cfe-commits]

jmciver created this revision.
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This commit is in support of future uninitialized memory handling and adds
alloca instruction support to getInitialValueOfAllocation. This unifies initial
memory state querying (both stack and heap) to a single utility function.

Several optimizations are refactored to take advantage of alloca support in
getInitialValueOfAllocation, see below list. A majority of the optimizations are
effected by the migration of PromoteMemToReg to use getInitialValueOfAllocation,
which requires TLI for allocation function data, but is not used in support of
alloca instructions.

- PromoteMemToReg
- Mem2Reg
- IPO
- CoroSplit
- Coroutines (clang)
- GVN
- NewGVN
- Statepoint

Coroutines have a clang based optimization call to PromoteMemToReg from
FinishFunction, which requires a TLI object outside of the optimization pass
framework. Generation of the TLI is added at the module level to prevent
generation of multiple TLI objects for each coroutine function contained
within. Furthermore generation of the TLI object is lazy.


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Files:
  clang/lib/CodeGen/CodeGenFunction.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenModule.h
  llvm/include/llvm/Analysis/MemoryBuiltins.h
  llvm/include/llvm/Transforms/Scalar/SROA.h
  llvm/include/llvm/Transforms/Utils/PromoteMemToReg.h
  llvm/lib/Analysis/MemoryBuiltins.cpp
  llvm/lib/Transforms/Coroutines/CoroFrame.cpp
  llvm/lib/Transforms/Coroutines/CoroInternal.h
  llvm/lib/Transforms/Coroutines/CoroSplit.cpp
  llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
  llvm/lib/Transforms/Scalar/GVN.cpp
  llvm/lib/Transforms/Scalar/NewGVN.cpp
  llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
  llvm/lib/Transforms/Scalar/SROA.cpp
  llvm/lib/Transforms/Utils/Mem2Reg.cpp
  llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
  llvm/test/Other/new-pm-defaults.ll
  llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
  llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
  llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
  llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
  llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll

Index: llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
===
--- llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
+++ llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
@@ -39,8 +39,8 @@
 ; CHECK-O-NEXT: Running analysis: AssumptionAnalysis
 ; CHECK-O-NEXT: Running pass: SROAPass
 ; CHECK-O-NEXT: Running analysis: DominatorTreeAnalysis
-; CHECK-O-NEXT: Running pass: EarlyCSEPass
 ; CHECK-O-NEXT: Running analysis: TargetLibraryAnalysis
+; CHECK-O-NEXT: Running pass: EarlyCSEPass
 ; CHECK-O3-NEXT: Running pass: CallSiteSplittingPass
 ; CHECK-O-NEXT: Running pass: SampleProfileLoaderPass
 ; CHECK-O-NEXT: Running analysis: ProfileSummaryAnalysis
Index: llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
===
--- llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
+++ llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
@@ -40,8 +40,8 @@
 ; CHECK-O-NEXT: Running analysis: AssumptionAnalysis
 ; CHECK-O-NEXT: Running pass: SROAPass
 ; CHECK-O-NEXT: Running analysis: DominatorTreeAnalysis
-; CHECK-O-NEXT: Running pass: EarlyCSEPass
 ; CHECK-O-NEXT: Running analysis: TargetLibraryAnalysis
+; CHECK-O-NEXT: Running pass: EarlyCSEPass
 ; CHECK-O3-NEXT: Running pass: CallSiteSplittingPass
 ; CHECK-O-NEXT: Running pass: OpenMPOptPass
 ; CHECK-O-NEXT: Running pass: IPSCCPPass
Index: llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
===
--- llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
+++ llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
@@ -52,8 +52,8 @@
 ; CHECK-O-NEXT: Running analysis: AssumptionAnalysis
 ; CHECK-O-NEXT: Running pass: SROAPass
 ; CHECK-O-NEXT: Running analysis: DominatorTreeAnalysis
-; CHECK-O-NEXT: Running pass: EarlyCSEPass
 ; CHECK-O-NEXT: Running analysis: TargetLibraryAnalysis
+; CHECK-O-NEXT: Running pass: EarlyCSEPass
 ; CHECK-O3-NEXT: Running pass: CallSiteSplittingPass
 ; CHECK-O-NEXT: Running pass: OpenMPOptPass
 ; CHECK-O-NEXT: Running pass: IPSCCPPass
Index: llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
===
--- llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
+++ llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
@@ -38,8 +38,8 @@
 ; CHECK-O-NEXT: Running pass: GlobalOptPass
 ; CHECK-O-NEXT: Ru

[PATCH] D155773: [llvm][MemoryBuiltins] Add alloca support to getInitialValueOfAllocation

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

@nikic as per my GSoC project I am trying, under the guidance of @nlopes, a 
load attribute based approach to migrating uninitialized load to poison. The 
first attribute that I am working on is !freeze which effectively inserts a 
freeze poison if the load is uninitialized. Obviously this can only be done in
optimizations that allow instruction creation. In the future I am looking to 
add a load instruction parameter to getInitialValueOfAllocation to allow 
modification of the returned constant based on the allocation 
function/instruction and the presence of a load attribute.

So why pack the alloca test into getInitialValueOfAllocation? The reasoning is 
that attribute is on a per-load instruction, but allocation could be alloca or 
function. I agree if the application of the load attribute were universal 
passing in the default value to mem2reg would work, but as we are modulating 
the returned constant based on individual load instruction attributes this 
would not work. Hence the query based approach.

As for the TLI I agree that making it required is probably not ideal. @nlopes 
can vouch that I thought about this :-). Two options off the top of my head are:

1. Make the TLI parameter of getInitialValueOfAllocation a pointer with 
defaults to nullptr.

2. Add a separated query function for alloca instructions.

The advantage to option 1 is all allocation initial state queries are handled 
in one place. The detractor is we have a parameter that has a default nullptr.

The advantage to option 2 is allocation functions vs alloca instruction are 
handled by functions that have only the required parameterizations exposed. The 
detractor is there will be some combinatorial overlap between the two functions.

Thoughts?


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[PATCH] D155773: [llvm][MemoryBuiltins] Add alloca support to getInitialValueOfAllocation

[John McIver via Phabricator via cfe-commits]

jmciver updated this revision to Diff 542618.
jmciver added a comment.

Remove reliance on TLI objects where only alloca instructions are processes


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Files:
  llvm/include/llvm/Analysis/MemoryBuiltins.h
  llvm/lib/Analysis/MemoryBuiltins.cpp
  llvm/lib/Transforms/Scalar/GVN.cpp
  llvm/lib/Transforms/Scalar/NewGVN.cpp
  llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp

Index: llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
===
--- llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
+++ llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
@@ -24,6 +24,7 @@
 #include "llvm/Analysis/AssumptionCache.h"
 #include "llvm/Analysis/InstructionSimplify.h"
 #include "llvm/Analysis/IteratedDominanceFrontier.h"
+#include "llvm/Analysis/MemoryBuiltins.h"
 #include "llvm/Analysis/ValueTracking.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/CFG.h"
@@ -600,7 +601,7 @@
 if (I == StoresByIndex.begin()) {
   if (StoresByIndex.empty())
 // If there are no stores, the load takes the undef value.
-ReplVal = UndefValue::get(LI->getType());
+ReplVal = getInitialValueOfAllocation(AI, nullptr, LI->getType());
   else
 // There is no store before this load, bail out (load may be affected
 // by the following stores - see main comment).
Index: llvm/lib/Transforms/Scalar/NewGVN.cpp
===
--- llvm/lib/Transforms/Scalar/NewGVN.cpp
+++ llvm/lib/Transforms/Scalar/NewGVN.cpp
@@ -1489,21 +1489,18 @@
   if (LoadPtr != lookupOperandLeader(DepInst) &&
   !AA->isMustAlias(LoadPtr, DepInst))
 return nullptr;
-  // If this load really doesn't depend on anything, then we must be loading an
-  // undef value.  This can happen when loading for a fresh allocation with no
-  // intervening stores, for example.  Note that this is only true in the case
-  // that the result of the allocation is pointer equal to the load ptr.
-  if (isa(DepInst)) {
-return createConstantExpression(UndefValue::get(LoadType));
-  }
   // If this load occurs either right after a lifetime begin,
   // then the loaded value is undefined.
-  else if (auto *II = dyn_cast(DepInst)) {
+  if (auto *II = dyn_cast(DepInst)) {
 if (II->getIntrinsicID() == Intrinsic::lifetime_start)
   return createConstantExpression(UndefValue::get(LoadType));
-  } else if (auto *InitVal =
- getInitialValueOfAllocation(DepInst, TLI, LoadType))
-  return createConstantExpression(InitVal);
+  }
+  // If this load really doesn't depend on anything, then we must be loading an
+  // undef value.  This can happen when loading for a fresh allocation with no
+  // intervening stores, for example.  Note that this is only true in the case
+  // that the result of the allocation is pointer equal to the load ptr.
+  else if (auto *InitVal = getInitialValueOfAllocation(DepInst, TLI, LoadType))
+return createConstantExpression(InitVal);
 
   return nullptr;
 }
Index: llvm/lib/Transforms/Scalar/GVN.cpp
===
--- llvm/lib/Transforms/Scalar/GVN.cpp
+++ llvm/lib/Transforms/Scalar/GVN.cpp
@@ -1240,11 +1240,12 @@
   }
   assert(DepInfo.isDef() && "follows from above");
 
-  // Loading the alloca -> undef.
   // Loading immediately after lifetime begin -> undef.
-  if (isa(DepInst) || isLifetimeStart(DepInst))
+  if (isLifetimeStart(DepInst))
 return AvailableValue::get(UndefValue::get(Load->getType()));
 
+  // In addition to allocator function calls this includes loading the alloca ->
+  // undef.
   if (Constant *InitVal =
   getInitialValueOfAllocation(DepInst, TLI, Load->getType()))
 return AvailableValue::get(InitVal);
Index: llvm/lib/Analysis/MemoryBuiltins.cpp
===
--- llvm/lib/Analysis/MemoryBuiltins.cpp
+++ llvm/lib/Analysis/MemoryBuiltins.cpp
@@ -436,6 +436,9 @@
 Constant *llvm::getInitialValueOfAllocation(const Value *V,
 const TargetLibraryInfo *TLI,
 Type *Ty) {
+  if (isa(V))
+return UndefValue::get(Ty);
+
   auto *Alloc = dyn_cast(V);
   if (!Alloc)
 return nullptr;
Index: llvm/include/llvm/Analysis/MemoryBuiltins.h
===
--- llvm/include/llvm/Analysis/MemoryBuiltins.h
+++ llvm/include/llvm/Analysis/MemoryBuiltins.h
@@ -119,8 +119,8 @@
 });
 
 /// If this is a call to an allocation function that initializes memory to a
-/// fixed value, return said value in the requested type.  Otherwise, return
-/// nullptr.
+/// fixed value, return said value in the requested type. If this is a call to
+/// alloca instruction the returned value is 

[PATCH] D155773: [llvm][MemoryBuiltins] Add alloca support to getInitialValueOfAllocation

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

Ping


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[PATCH] D155773: [llvm][MemoryBuiltins] Add alloca support to getInitialValueOfAllocation

[John McIver via Phabricator via cfe-commits]

jmciver added inline comments.



Comment at: llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp:809-811
+  Updater.AddAvailableValue(
+  Alloca.getParent(),
+  getInitialValueOfAllocation(&Alloca, nullptr, VectorTy));

arsenm wrote:
> This is very specifically handling alloca, not any random allocation like 
> function
@arsenm thanks for the feedback. I added functionality to 
`getInitalValueOfAllocation` to handle `alloca` instructions specifically. This 
is being done as preliminary to some possible refactorizations allowing 
uninitialized memory to move to poison semantics. The behavior for these 
changes would be the same for `alloca` and allocation like functions.


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[PATCH] D155773: [llvm][MemoryBuiltins] Add alloca support to getInitialValueOfAllocation

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

@nikic Thanks for responding. I will get a "work in progress" patch up in the 
next three days.

In the API adaptation, instruction insertion is still being handled in the 
caller as some passes are only allowed removal and not insertion.


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[PATCH] D158343: WIP: [UpdateTestChecks] Add update test check support for freeze_bits metadata

[John McIver via Phabricator via cfe-commits]

jmciver created this revision.
Herald added subscribers: luismarques, jdoerfert, arichardson.
Herald added a project: All.
jmciver retitled this revision from "WIP: [UpdateTestChecks] Add update test 
check support for freeze_bits metadata

Part of a sequence of exploratory patches using poison semantics for
uninitialized memory." to "WIP: [UpdateTestChecks] Add update test check 
support for freeze_bits metadata".
jmciver edited the summary of this revision.
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Part of a sequence of exploratory patches using poison semantics for
uninitialized memory.

Add freeze_bits metadata support to update test check utilities.


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Files:
  clang/test/utils/update_cc_test_checks/Inputs/basic-cplusplus.cpp.expected
  
clang/test/utils/update_cc_test_checks/Inputs/check-attributes.cpp.funcattrs.expected
  
clang/test/utils/update_cc_test_checks/Inputs/check-attributes.cpp.plain.expected
  clang/test/utils/update_cc_test_checks/Inputs/def-and-decl.c.expected
  
clang/test/utils/update_cc_test_checks/Inputs/explicit-template-instantiation.cpp.expected
  clang/test/utils/update_cc_test_checks/Inputs/generated-funcs-regex.c.expected
  
clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.generated.expected
  
clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.no-generated.expected
  clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.expected
  clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.funcsig.expected
  
clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.funcsig.v2.expected
  clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.v2.expected
  
clang/test/utils/update_cc_test_checks/Inputs/resolve-tmp-conflict.cpp.expected
  llvm/utils/UpdateTestChecks/common.py

Index: llvm/utils/UpdateTestChecks/common.py
===
--- llvm/utils/UpdateTestChecks/common.py
+++ llvm/utils/UpdateTestChecks/common.py
@@ -980,6 +980,7 @@
 ),
 NamelessValue(r"DBG", "!", r"!dbg ", r"![0-9]+", None),
 NamelessValue(r"DIASSIGNID", "!", r"!DIAssignID ", r"![0-9]+", None),
+NamelessValue(r'FREEZE_BITS', '!', r'!freeze_bits ', r'![0-9]+', None),
 NamelessValue(r"PROF", "!", r"!prof ", r"![0-9]+", None),
 NamelessValue(r"TBAA", "!", r"!tbaa ", r"![0-9]+", None),
 NamelessValue(r"TBAA_STRUCT", "!", r"!tbaa.struct ", r"![0-9]+", None),
Index: clang/test/utils/update_cc_test_checks/Inputs/resolve-tmp-conflict.cpp.expected
===
--- clang/test/utils/update_cc_test_checks/Inputs/resolve-tmp-conflict.cpp.expected
+++ clang/test/utils/update_cc_test_checks/Inputs/resolve-tmp-conflict.cpp.expected
@@ -12,8 +12,8 @@
 // CHECK-NEXT:store ptr [[A_ADDR]], ptr [[_TMP0]], align 8
 // CHECK-NEXT:store i32 1, ptr [[REF_TMP]], align 4
 // CHECK-NEXT:store ptr [[REF_TMP]], ptr [[_TMP1]], align 8
-// CHECK-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// CHECK-NEXT:[[TMP1:%.*]] = load ptr, ptr [[_TMP1]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr, ptr [[_TMP1]], align 8, !freeze_bits [[FREEZE_BITS2]]
 // CHECK-NEXT:store i32 [[TMP0]], ptr [[TMP1]], align 4
 // CHECK-NEXT:ret void
 //
Index: clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.v2.expected
===
--- clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.v2.expected
+++ clang/test/utils/update_cc_test_checks/Inputs/mangled_names.c.v2.expected
@@ -9,8 +9,8 @@
 // CHECK-NEXT:[[B_ADDR:%.*]] = alloca i32, align 4
 // CHECK-NEXT:store i64 [[A]], ptr [[A_ADDR]], align 8
 // CHECK-NEXT:store i32 [[B]], ptr [[B_ADDR]], align 4
-// CHECK-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8, !freeze_bits [[FREEZE_BITS2:![0-9]+]]
+// CHECK-NEXT:[[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4, !freeze_bits [[FREEZE_BITS2]]
 // CHECK-NEXT:[[CONV:%.*]] = sext i32 [[TMP1]] to i64
 // CHECK-NEXT:[[ADD:%.*]] = add nsw i64 [[TMP0]], [[CONV]]
 // CHECK-NEXT:ret i64 [[ADD]]
@@ -29,11 +29,11 @@
 // CHECK-NEXT:store i64 [[A]], ptr [[A_ADDR]], align 8
 // CHECK-NEXT:store i32 [[B]], ptr [[B_ADDR]], align 4
 // CHECK-NEXT:store i32 [[C]], ptr [[C_ADDR]], align 4
-// CHECK-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
-// CHECK-NEXT:[[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = l

[PATCH] D158345: WIP: [clang][llvm][test] Update tests to support freeze_bits metadata

[John McIver via Phabricator via cfe-commits]

jmciver created this revision.
Herald added subscribers: kerbowa, pengfei, jvesely.
Herald added a project: All.
jmciver retitled this revision from "[clang][llvm][test] Update tests to 
support freeze_bits metadata" to "WIP: [clang][llvm][test] Update tests to 
support freeze_bits metadata".
jmciver added a subscriber: nlopes.
jmciver edited the summary of this revision.
jmciver published this revision for review.
Herald added a reviewer: jdoerfert.
Herald added subscribers: llvm-commits, cfe-commits, wangpc, jplehr, sstefan1.
Herald added projects: clang, LLVM.

Part of a sequence of exploratory patches using poison semantics for
uninitialized memory.

Add freeze_bits metadata to regression tests. At this time freeze_bits
support has not been added to optimizations.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158345

Files:
  clang/test/CodeGen/X86/avx-builtins.c
  clang/test/CodeGen/X86/avx512bw-builtins.c
  clang/test/CodeGen/X86/avx512f-builtins.c
  clang/test/CodeGen/X86/avx512fp16-builtins.c
  clang/test/CodeGen/X86/avx512vl-builtins.c
  clang/test/CodeGen/X86/avx512vlbw-builtins.c
  clang/test/CodeGen/X86/sse-builtins.c
  clang/test/CodeGen/X86/sse2-builtins.c
  clang/test/CodeGen/aarch64-ls64-inline-asm.c
  clang/test/CodeGen/aarch64-ls64.c
  clang/test/CodeGen/asm-goto2.c
  clang/test/CodeGen/matrix-type-operators.c
  clang/test/CodeGen/memcpy-inline-builtin.c
  clang/test/CodeGen/sanitize-metadata-nosanitize.c
  clang/test/CodeGen/tbaa-array.cpp
  clang/test/CodeGen/tbaa-base.cpp
  clang/test/CodeGen/tbaa-reference.cpp
  clang/test/CodeGen/tbaa.cpp
  clang/test/CodeGenCXX/attr-likelihood-switch-branch-weights.cpp
  clang/test/CodeGenCXX/builtin-bit-cast-no-tbaa.cpp
  clang/test/CodeGenCXX/cxx1z-decomposition.cpp
  clang/test/CodeGenCXX/debug-info-line.cpp
  clang/test/CodeGenCXX/matrix-type-operators.cpp
  clang/test/CodeGenObjC/ivar-invariant.m
  clang/test/CodeGenObjC/nontrivial-c-struct-exception.m
  clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl
  clang/test/OpenMP/atomic_capture_codegen.cpp
  clang/test/OpenMP/atomic_update_codegen.cpp
  clang/test/OpenMP/bug57757.cpp
  clang/test/OpenMP/cancel_codegen.cpp
  clang/test/OpenMP/cancellation_point_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/distribute_simd_codegen.cpp
  clang/test/OpenMP/for_reduction_task_codegen.cpp
  clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp
  clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp
  clang/test/OpenMP/sections_reduction_task_codegen.cpp
  clang/test/OpenMP/target_defaultmap_codegen_01.cpp
  clang/test/OpenMP/target_in_reduction_codegen.cpp
  clang/test/OpenMP/target_map_codegen_00.cpp
  clang/test/OpenMP/target_map_codegen_01.cpp
  clang/test/OpenMP/target_map_codegen_02.cpp
  clang/test/OpenMP/target_map_codegen_04.cpp
  clang/test/OpenMP/target_map_codegen_05.cpp
  clang/test/OpenMP/target_map_codegen_07.cpp
  clang/test/OpenMP/target_map_codegen_11.cpp
  clang/test/OpenMP/target_map_codegen_13.cpp
  clang/test/OpenMP/target_map_codegen_14.cpp
  clang/test/OpenMP/target_map_codegen_15.cpp
  clang/test/OpenMP/target_map_codegen_17.cpp
  clang/test/OpenMP/target_map_codegen_26.cpp
  clang/test/OpenMP/target_map_codegen_27.cpp
  clang/test/OpenMP/target_map_codegen_29.cpp
  clang/test/OpenMP/target_map_codegen_35.cpp
  clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp
  clang/test/OpenMP/target_parallel_codegen.cpp
  clang/test/OpenMP/target_parallel_for_codegen.cpp
  clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
  clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/target_task_affinity_codegen.cpp
  clang/test/OpenMP/target_teams_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
  clang/test/OpenMP/target_update_codegen.cpp
  clang/test/OpenMP/task_affinity_codegen.cpp
  clang/test/OpenMP/task_codegen.cpp
  clang/test/OpenMP/task_if_codegen.cpp
  clang/test/OpenMP/t

[PATCH] D155773: [llvm][MemoryBuiltins] Add alloca support to getInitialValueOfAllocation

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

@nikic I added this patch to a work in progress (WIP) "stack" of patches. 
D158352  and D158353 
 show what the intended progression looks 
like for mem2reg. I will add WIP SROA changes in the next few days.


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[PATCH] D155773: [llvm][MemoryBuiltins] Add alloca support to getInitialValueOfAllocation

[John McIver via Phabricator via cfe-commits]

jmciver updated this revision to Diff 545294.
jmciver edited the summary of this revision.
jmciver added a comment.
Herald added subscribers: foad, kerbowa, jvesely, arsenm.

Refactor AMDGPUPromoteAlloca to use getInitialValueOfAllocation.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155773/new/

https://reviews.llvm.org/D155773

Files:
  llvm/include/llvm/Analysis/MemoryBuiltins.h
  llvm/lib/Analysis/MemoryBuiltins.cpp
  llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
  llvm/lib/Transforms/Scalar/GVN.cpp
  llvm/lib/Transforms/Scalar/NewGVN.cpp
  llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp

Index: llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
===
--- llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
+++ llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp
@@ -24,6 +24,7 @@
 #include "llvm/Analysis/AssumptionCache.h"
 #include "llvm/Analysis/InstructionSimplify.h"
 #include "llvm/Analysis/IteratedDominanceFrontier.h"
+#include "llvm/Analysis/MemoryBuiltins.h"
 #include "llvm/Analysis/ValueTracking.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/CFG.h"
@@ -600,7 +601,7 @@
 if (I == StoresByIndex.begin()) {
   if (StoresByIndex.empty())
 // If there are no stores, the load takes the undef value.
-ReplVal = UndefValue::get(LI->getType());
+ReplVal = getInitialValueOfAllocation(AI, nullptr, LI->getType());
   else
 // There is no store before this load, bail out (load may be affected
 // by the following stores - see main comment).
Index: llvm/lib/Transforms/Scalar/NewGVN.cpp
===
--- llvm/lib/Transforms/Scalar/NewGVN.cpp
+++ llvm/lib/Transforms/Scalar/NewGVN.cpp
@@ -1496,21 +1496,18 @@
   if (LoadPtr != lookupOperandLeader(DepInst) &&
   !AA->isMustAlias(LoadPtr, DepInst))
 return nullptr;
-  // If this load really doesn't depend on anything, then we must be loading an
-  // undef value.  This can happen when loading for a fresh allocation with no
-  // intervening stores, for example.  Note that this is only true in the case
-  // that the result of the allocation is pointer equal to the load ptr.
-  if (isa(DepInst)) {
-return createConstantExpression(UndefValue::get(LoadType));
-  }
   // If this load occurs either right after a lifetime begin,
   // then the loaded value is undefined.
-  else if (auto *II = dyn_cast(DepInst)) {
+  if (auto *II = dyn_cast(DepInst)) {
 if (II->getIntrinsicID() == Intrinsic::lifetime_start)
   return createConstantExpression(UndefValue::get(LoadType));
-  } else if (auto *InitVal =
- getInitialValueOfAllocation(DepInst, TLI, LoadType))
-  return createConstantExpression(InitVal);
+  }
+  // If this load really doesn't depend on anything, then we must be loading an
+  // undef value.  This can happen when loading for a fresh allocation with no
+  // intervening stores, for example.  Note that this is only true in the case
+  // that the result of the allocation is pointer equal to the load ptr.
+  else if (auto *InitVal = getInitialValueOfAllocation(DepInst, TLI, LoadType))
+return createConstantExpression(InitVal);
 
   return nullptr;
 }
Index: llvm/lib/Transforms/Scalar/GVN.cpp
===
--- llvm/lib/Transforms/Scalar/GVN.cpp
+++ llvm/lib/Transforms/Scalar/GVN.cpp
@@ -1239,11 +1239,12 @@
   }
   assert(DepInfo.isDef() && "follows from above");
 
-  // Loading the alloca -> undef.
   // Loading immediately after lifetime begin -> undef.
-  if (isa(DepInst) || isLifetimeStart(DepInst))
+  if (isLifetimeStart(DepInst))
 return AvailableValue::get(UndefValue::get(Load->getType()));
 
+  // In addition to allocator function calls this includes loading the alloca ->
+  // undef.
   if (Constant *InitVal =
   getInitialValueOfAllocation(DepInst, TLI, Load->getType()))
 return AvailableValue::get(InitVal);
Index: llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
===
--- llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
@@ -32,6 +32,7 @@
 #include "llvm/Analysis/CaptureTracking.h"
 #include "llvm/Analysis/InstSimplifyFolder.h"
 #include "llvm/Analysis/InstructionSimplify.h"
+#include "llvm/Analysis/MemoryBuiltins.h"
 #include "llvm/Analysis/ValueTracking.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/IRBuilder.h"
@@ -805,7 +806,9 @@
   // undef.
   SSAUpdater Updater;
   Updater.Initialize(VectorTy, "promotealloca");
-  Updater.AddAvailableValue(Alloca.getParent(), UndefValue::get(VectorTy));
+  Updater.AddAvailableValue(
+  Alloca.getParent(),
+  getInitialValueOfAllocation(&Alloca, nullptr, VectorTy));
 
   // First handle the initial worklist.
   SmallVector DeferredLoads;
Inde

[PATCH] D155773: [llvm][MemoryBuiltins] Add alloca support to getInitialValueOfAllocation

[John McIver via Phabricator via cfe-commits]

jmciver added a comment.

Ping


Repository:
  rG LLVM Github Monorepo

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[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary 1 or 2)

[John McIver via Phabricator via cfe-commits]

jmciver updated this revision to Diff 478821.
jmciver added a comment.

Updating D134410 : [clang][CodeGen] Add 
noundef metadata to load instructions (preliminary 1 or 2)

Refactor test matrix-type-operators.c to contain the noundef attribute. This
test will be further modified in future patches.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D134410

Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/CGExpr.cpp
  clang/test/CodeGen/X86/avx-builtins.c
  clang/test/CodeGen/X86/avx512bw-builtins.c
  clang/test/CodeGen/X86/avx512f-builtins.c
  clang/test/CodeGen/X86/avx512fp16-builtins.c
  clang/test/CodeGen/X86/avx512vl-builtins.c
  clang/test/CodeGen/X86/avx512vlbw-builtins.c
  clang/test/CodeGen/X86/sse-builtins.c
  clang/test/CodeGen/X86/sse2-builtins.c
  clang/test/CodeGen/aarch64-ls64-inline-asm.c
  clang/test/CodeGen/aarch64-ls64.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/matrix-type-operators.c
  clang/test/CodeGen/memcpy-inline-builtin.c
  clang/test/CodeGen/tbaa-array.cpp
  clang/test/CodeGen/tbaa-base.cpp
  clang/test/CodeGen/tbaa.cpp
  clang/test/CodeGen/ubsan-pass-object-size.c
  clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
  clang/test/CodeGenCXX/attr-likelihood-if-branch-weights.cpp
  clang/test/CodeGenCXX/attr-likelihood-switch-branch-weights.cpp
  clang/test/CodeGenCXX/builtin-bit-cast-no-tbaa.cpp
  clang/test/CodeGenCXX/debug-info-line.cpp
  clang/test/CodeGenCXX/pr12251.cpp
  clang/test/CodeGenCXX/pragma-followup_inner.cpp
  clang/test/OpenMP/cancel_codegen.cpp
  clang/test/OpenMP/cancellation_point_codegen.cpp
  clang/test/OpenMP/distribute_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp
  clang/test/OpenMP/distribute_simd_codegen.cpp
  clang/test/OpenMP/distribute_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_simd_reduction_codegen.cpp
  clang/test/OpenMP/for_reduction_task_codegen.cpp
  clang/test/OpenMP/irbuilder_safelen.cpp
  clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
  clang/test/OpenMP/irbuilder_simd_aligned.cpp
  clang/test/OpenMP/irbuilder_simdlen.cpp
  clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
  clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp
  clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
  clang/test/OpenMP/ordered_codegen.cpp
  clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_aligned_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp
  clang/test/OpenMP/sections_reduction_task_codegen.cpp
  clang/test/OpenMP/target_defaultmap_codegen_01.cpp
  clang/test/OpenMP/target_in_reduction_codegen.cpp
  clang/test/OpenMP/target_is_device_ptr_codegen.cpp
  clang/test/OpenMP/target_map_codegen_00.cpp
  clang/test/OpenMP/target_map_codegen_01.cpp
  clang/test/OpenMP/target_map_codegen_02.cpp
  clang/test/OpenMP/target_map_codegen_04.cpp
  clang/test/OpenMP/target_map_codegen_05.cpp
  clang/test/OpenMP/target_map_codegen_07.cpp
  clang/test/OpenMP/target_map_codegen_11.cpp
  clang/test/OpenMP/target_map_codegen_13.cpp
  clang/test/OpenMP/target_map_codegen_14.cpp
  clang/test/OpenMP/target_map_codegen_15.cpp
  clang/test/OpenMP/target_map_codegen_17.cpp
  clang/test/OpenMP/target_map_codegen_26.cpp
  clang/test/OpenMP/target_map_codegen_27.cpp
  clang/test/OpenMP/target_map_codegen_29.cpp
  clang/test/OpenMP/target_parallel_codegen.cpp
  clang/test/OpenMP/target_parallel_for_codegen.cpp
  clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
  clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/target_teams_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_

[PATCH] D138983: [clang][CodeGen] Add noundef metadata to load instructions (preliminary 3 or 3)

[John McIver via Phabricator via cfe-commits]

jmciver created this revision.
Herald added a project: All.
jmciver added reviewers: vitalybuka, jdoerfert, rjmccall, aqjune, efriedma, 
nikic.
jmciver added subscribers: mattd, asavonic, pengfei, pcwang-thead, sstefan1, 
xbolva00, nlopes.
jmciver edited the summary of this revision.
jmciver published this revision for review.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Add noundef attribute support for matrix and vector type loads in support of 
elemental or sufflevector operations.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138983

Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/test/CodeGen/matrix-type-operators.c
  clang/test/CodeGen/vector-noundef.c
  clang/test/CodeGenCXX/vector-noundef.cpp

Index: clang/test/CodeGenCXX/vector-noundef.cpp
===
--- clang/test/CodeGenCXX/vector-noundef.cpp
+++ clang/test/CodeGenCXX/vector-noundef.cpp
@@ -6,6 +6,9 @@
 using VecOfThreeChars __attribute__((ext_vector_type(3))) = char;
 using VecOfThreeUChars __attribute__((ext_vector_type(3))) = unsigned char;
 
+using VecOfFourFloats __attribute__((ext_vector_type(4))) = float;
+using VecOfTwoFloats __attribute__((ext_vector_type(2))) = float;
+
 // CHECK-LABEL: @_Z15getElement4BoolRDv4_b(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[A_ADDR:%.*]] = alloca ptr, align 8
@@ -82,3 +85,33 @@
 {
   return a[0];
 }
+
+// CHECK-LABEL: @_Z16vectorSubsectionRDv2_fRDv4_f(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VEC2_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT:[[VEC4_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT:store ptr [[VEC2:%.*]], ptr [[VEC2_ADDR]], align 8
+// CHECK-NEXT:store ptr [[VEC4:%.*]], ptr [[VEC4_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, ptr [[TMP0]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:[[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <2 x i32> 
+// CHECK-NEXT:[[TMP3:%.*]] = load ptr, ptr [[VEC2_ADDR]], align 8
+// CHECK-NEXT:store <2 x float> [[TMP2]], ptr [[TMP3]], align 8
+// CHECK-NEXT:ret void
+//
+// DISABLE-LABEL: @_Z16vectorSubsectionRDv2_fRDv4_f(
+// DISABLE-NEXT:  entry:
+// DISABLE-NEXT:[[VEC2_ADDR:%.*]] = alloca ptr, align 8
+// DISABLE-NEXT:[[VEC4_ADDR:%.*]] = alloca ptr, align 8
+// DISABLE-NEXT:store ptr [[VEC2:%.*]], ptr [[VEC2_ADDR]], align 8
+// DISABLE-NEXT:store ptr [[VEC4:%.*]], ptr [[VEC4_ADDR]], align 8
+// DISABLE-NEXT:[[TMP0:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// DISABLE-NEXT:[[TMP1:%.*]] = load <4 x float>, ptr [[TMP0]], align 16
+// DISABLE-NEXT:[[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <2 x i32> 
+// DISABLE-NEXT:[[TMP3:%.*]] = load ptr, ptr [[VEC2_ADDR]], align 8
+// DISABLE-NEXT:store <2 x float> [[TMP2]], ptr [[TMP3]], align 8
+// DISABLE-NEXT:ret void
+//
+void vectorSubsection(VecOfTwoFloats& vec2, VecOfFourFloats& vec4) {
+vec2 = vec4.xy;
+}
Index: clang/test/CodeGen/vector-noundef.c
===
--- /dev/null
+++ clang/test/CodeGen/vector-noundef.c
@@ -0,0 +1,107 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -no-opaque-pointers -flax-vector-conversions=none -ffreestanding -triple x86_64-gnu-linux -target-feature +avx512f -O0 -enable-noundef-load-analysis -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -no-opaque-pointers -flax-vector-conversions=none -ffreestanding -triple x86_64-gnu-linux -target-feature +avx512f -O0 -no-enable-noundef-load-analysis -emit-llvm -o - %s | FileCheck %s --check-prefix=DISABLE
+
+#include 
+
+// CHECK-LABEL: @test_mm_mask_div_ss(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[__A_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__B_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__W_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__U_ADDR_I:%.*]] = alloca i8, align 1
+// CHECK-NEXT:[[__A_ADDR_I2:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__B_ADDR_I2:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__W_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__U_ADDR:%.*]] = alloca i8, align 1
+// CHECK-NEXT:[[__A_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__B_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:store <4 x float> [[__W:%.*]], <4 x float>* [[__W_ADDR]], align 16
+// CHECK-NEXT:store i8 [[__U:%.*]], i8* [[__U_ADDR]], align 1
+// CHECK-NEXT:store <4 x float> [[__A:%.*]], <4 x float>* [[__A_ADDR]], align 16
+// CHECK-NEXT:store <4 x float> [[__B:%.*]], <4 x float>* [[__B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <4 x float>, <4 x float>* [[__W_ADDR]], align 16, !noundef [[NOUNDEF2:![0-9]+]]
+// CHECK-NEXT:[[TMP1:%.*]] = load i8,

[PATCH] D128501: [CodeGen] Make uninitialized Lvalue bit-field stores poison compatible

[John McIver via Phabricator via cfe-commits]

jmciver closed this revision.
jmciver added a comment.

I am closing this ticket as we are working on alternative solutions to poison 
based load semantics 
.

Thanks to everyone for taking the time to discuss this patch and its 
limitations!


Repository:
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[PATCH] D129542: [CodeGen] Add codegen of IR function attribute fine_grained_bitfields

[John McIver via Phabricator via cfe-commits]

jmciver abandoned this revision.
jmciver added a comment.

I am closing this ticket as we are working on alternative solutions to poison 
based load semantics 
.

Thanks to everyone for taking the time to discuss this patch and its 
limitations!


Repository:
  rG LLVM Github Monorepo

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[PATCH] D153184: [NFC][clang] Refactor FileCheck metadata references in pragma-followup_inner.cpp

[John McIver via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG148075cf87c7: [clang][test] Refactor FileCheck metadata in 
pragma-followup_inner.cpp (authored by jmciver).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/test/CodeGenCXX/pragma-followup_inner.cpp


Index: clang/test/CodeGenCXX/pragma-followup_inner.cpp
===
--- clang/test/CodeGenCXX/pragma-followup_inner.cpp
+++ clang/test/CodeGenCXX/pragma-followup_inner.cpp
@@ -20,23 +20,23 @@
 
 // CHECK-DAG: ![[ACCESSGROUP_2:[0-9]+]] = distinct !{}
 
-// CHECK-DAG: ![[INNERLOOP_3:[0-9]+]] = distinct !{![[INNERLOOP_3:[0-9]+]], 
![[PARALLEL_ACCESSES_4:[0-9]+]], ![[DISTRIBUTE_5:[0-9]+]], 
![[DISTRIBUTE_FOLLOWUP_6:[0-9]+]]}
-// CHECK-DAG: ![[PARALLEL_ACCESSES_4:[0-9]+]] = 
!{!"llvm.loop.parallel_accesses", !2}
-// CHECK-DAG: ![[DISTRIBUTE_5:[0-9]+]] = !{!"llvm.loop.distribute.enable", i1 
true}
-// CHECK-DAG: ![[DISTRIBUTE_FOLLOWUP_6:[0-9]+]] = 
!{!"llvm.loop.distribute.followup_all", ![[LOOP_7:[0-9]+]]}
-
-// CHECK-DAG: ![[LOOP_7:[0-9]+]] = distinct !{![[LOOP_7:[0-9]+]], 
![[PARALLEL_ACCESSES_4:[0-9]+]], ![[VECTORIZE_8:[0-9]+]]}
-// CHECK-DAG: ![[VECTORIZE_8:[0-9]+]] = !{!"llvm.loop.vectorize.enable", i1 
true}
-
-// CHECK-DAG: ![[OUTERLOOP_9:[0-9]+]] = distinct !{![[OUTERLOOP_9:[0-9]+]], 
[[MP:![0-9]+]], ![[UNROLLANDJAM_COUNT_10:[0-9]+]], 
![[UNROLLANDJAM_FOLLOWUPINNER_11:[0-9]+]]}
-// CHECK-DAG: ![[UNROLLANDJAM_COUNT_10:[0-9]+]] = 
!{!"llvm.loop.unroll_and_jam.count", i32 4}
-// CHECK-DAG: ![[UNROLLANDJAM_FOLLOWUPINNER_11:[0-9]+]] = 
!{!"llvm.loop.unroll_and_jam.followup_inner", !13}
-
-// CHECK-DAG: ![[LOOP_12:[0-9]+]] = distinct !{![[LOOP_12:[0-9]+]], 
![[PARALLEL_ACCESSES_4:[0-9]+]], ![[ISVECTORIZED_13:[0-9]+]], 
![[UNROLL_COUNT_13:[0-9]+]], ![[UNROLL_FOLLOWUP_14:[0-9]+]]}
-// CHECK-DAG: ![[ISVECTORIZED_13:[0-9]+]] = !{!"llvm.loop.isvectorized"}
-// CHECK-DAG: ![[UNROLL_COUNT_13:[0-9]+]] = !{!"llvm.loop.unroll.count", i32 4}
-// CHECK-DAG: ![[UNROLL_FOLLOWUP_14:[0-9]+]] = 
!{!"llvm.loop.unroll.followup_all", ![[LOOP_15:[0-9]+]]}
-
-// CHECK-DAG: ![[LOOP_15:[0-9]+]] = distinct !{![[LOOP_15:[0-9]+]], 
![[PARALLEL_ACCESSES_4:[0-9]+]], ![[ISVECTORIZED_13:[0-9]+]], 
![[UNROLL_DISABLE_16:[0-9]+]], ![[PIPELINE_17:[0-9]+]]}
-// CHECK-DAG: ![[UNROLL_DISABLE_16:[0-9]+]] = !{!"llvm.loop.unroll.disable"}
-// CHECK-DAG: ![[PIPELINE_17:[0-9]+]] = 
!{!"llvm.loop.pipeline.initiationinterval", i32 10}
+// CHECK-DAG: ![[INNERLOOP_3]] = distinct !{![[INNERLOOP_3]], 
![[PARALLEL_ACCESSES_4:[0-9]+]], ![[DISTRIBUTE_5:[0-9]+]], 
![[DISTRIBUTE_FOLLOWUP_6:[0-9]+]]}
+// CHECK-DAG: ![[PARALLEL_ACCESSES_4]] = !{!"llvm.loop.parallel_accesses", 
![[ACCESSGROUP_2]]}
+// CHECK-DAG: ![[DISTRIBUTE_5]] = !{!"llvm.loop.distribute.enable", i1 true}
+// CHECK-DAG: ![[DISTRIBUTE_FOLLOWUP_6]] = 
!{!"llvm.loop.distribute.followup_all", ![[LOOP_7:[0-9]+]]}
+
+// CHECK-DAG: ![[LOOP_7]] = distinct !{![[LOOP_7]], ![[PARALLEL_ACCESSES_4]], 
![[VECTORIZE_8:[0-9]+]]}
+// CHECK-DAG: ![[VECTORIZE_8]] = !{!"llvm.loop.vectorize.enable", i1 true}
+
+// CHECK-DAG: ![[OUTERLOOP_9]] = distinct !{![[OUTERLOOP_9]], [[MP:![0-9]+]], 
![[UNROLLANDJAM_COUNT_10:[0-9]+]], ![[UNROLLANDJAM_FOLLOWUPINNER_11:[0-9]+]]}
+// CHECK-DAG: ![[UNROLLANDJAM_COUNT_10]] = 
!{!"llvm.loop.unroll_and_jam.count", i32 4}
+// CHECK-DAG: ![[UNROLLANDJAM_FOLLOWUPINNER_11]] = 
!{!"llvm.loop.unroll_and_jam.followup_inner", ![[LOOP_12:[0-9]+]]}
+
+// CHECK-DAG: ![[LOOP_12]] = distinct !{![[LOOP_12:[0-9]+]], 
![[PARALLEL_ACCESSES_4]], ![[ISVECTORIZED_13:[0-9]+]], 
![[UNROLL_COUNT_13:[0-9]+]], ![[UNROLL_FOLLOWUP_14:[0-9]+]]}
+// CHECK-DAG: ![[ISVECTORIZED_13]] = !{!"llvm.loop.isvectorized"}
+// CHECK-DAG: ![[UNROLL_COUNT_13]] = !{!"llvm.loop.unroll.count", i32 4}
+// CHECK-DAG: ![[UNROLL_FOLLOWUP_14]] = !{!"llvm.loop.unroll.followup_all", 
![[LOOP_15:[0-9]+]]}
+
+// CHECK-DAG: ![[LOOP_15]] = distinct !{![[LOOP_15]], 
![[PARALLEL_ACCESSES_4]], ![[ISVECTORIZED_13]], ![[UNROLL_DISABLE_16:[0-9]+]], 
![[PIPELINE_17:[0-9]+]]}
+// CHECK-DAG: ![[UNROLL_DISABLE_16]] = !{!"llvm.loop.unroll.disable"}
+// CHECK-DAG: ![[PIPELINE_17]] = !{!"llvm.loop.pipeline.initiationinterval", 
i32 10}


Index: clang/test/CodeGenCXX/pragma-followup_inner.cpp
===
--- clang/test/CodeGenCXX/pragma-followup_inner.cpp
+++ clang/test/CodeGenCXX/pragma-followup_inner.cpp
@@ -20,23 +20,23 @@
 
 // CHECK-DAG: ![[ACCESSGROUP_2:[0-9]+]] = distinct !{}
 
-// CHECK-DAG: ![[INNERLOOP_3:[0-9]+]] = distinct !{![[INNERLOOP_3:[0-9]+]], ![[PARALLEL_ACCESSES_4:[0-9]+]], ![[DISTRIBUTE_5:[0-9]+]], ![[DISTRIBUTE_FOLLOWUP_6:[0-9]+]]}
-// CHECK-DAG: ![[PARALLEL_ACCESSES_4:[0-9]+]] = !{!"llvm.loop.parallel_accesses", !2}
-// CHECK-DAG: ![[DISTRIBUTE_5:[0-9]+]] = !{!"llvm.loop.dist

[PATCH] D153184: [NFC][clang] Refactor FileCheck metadata references in pragma-followup_inner.cpp

[John McIver via Phabricator via cfe-commits]

jmciver created this revision.
Herald added a project: All.
jmciver added reviewers: MaskRay, Meinersbur.
jmciver added a subscriber: nlopes.
jmciver published this revision for review.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

- FileCheck variables for metadata are defined and referenced rather than 
repeatedly redefined.
- All numeric metadata identifiers are refactored to a FileCheck variable.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153184

Files:
  clang/test/CodeGenCXX/pragma-followup_inner.cpp


Index: clang/test/CodeGenCXX/pragma-followup_inner.cpp
===
--- clang/test/CodeGenCXX/pragma-followup_inner.cpp
+++ clang/test/CodeGenCXX/pragma-followup_inner.cpp
@@ -20,23 +20,23 @@
 
 // CHECK-DAG: ![[ACCESSGROUP_2:[0-9]+]] = distinct !{}
 
-// CHECK-DAG: ![[INNERLOOP_3:[0-9]+]] = distinct !{![[INNERLOOP_3:[0-9]+]], 
![[PARALLEL_ACCESSES_4:[0-9]+]], ![[DISTRIBUTE_5:[0-9]+]], 
![[DISTRIBUTE_FOLLOWUP_6:[0-9]+]]}
-// CHECK-DAG: ![[PARALLEL_ACCESSES_4:[0-9]+]] = 
!{!"llvm.loop.parallel_accesses", !2}
-// CHECK-DAG: ![[DISTRIBUTE_5:[0-9]+]] = !{!"llvm.loop.distribute.enable", i1 
true}
-// CHECK-DAG: ![[DISTRIBUTE_FOLLOWUP_6:[0-9]+]] = 
!{!"llvm.loop.distribute.followup_all", ![[LOOP_7:[0-9]+]]}
-
-// CHECK-DAG: ![[LOOP_7:[0-9]+]] = distinct !{![[LOOP_7:[0-9]+]], 
![[PARALLEL_ACCESSES_4:[0-9]+]], ![[VECTORIZE_8:[0-9]+]]}
-// CHECK-DAG: ![[VECTORIZE_8:[0-9]+]] = !{!"llvm.loop.vectorize.enable", i1 
true}
-
-// CHECK-DAG: ![[OUTERLOOP_9:[0-9]+]] = distinct !{![[OUTERLOOP_9:[0-9]+]], 
[[MP:![0-9]+]], ![[UNROLLANDJAM_COUNT_10:[0-9]+]], 
![[UNROLLANDJAM_FOLLOWUPINNER_11:[0-9]+]]}
-// CHECK-DAG: ![[UNROLLANDJAM_COUNT_10:[0-9]+]] = 
!{!"llvm.loop.unroll_and_jam.count", i32 4}
-// CHECK-DAG: ![[UNROLLANDJAM_FOLLOWUPINNER_11:[0-9]+]] = 
!{!"llvm.loop.unroll_and_jam.followup_inner", !13}
-
-// CHECK-DAG: ![[LOOP_12:[0-9]+]] = distinct !{![[LOOP_12:[0-9]+]], 
![[PARALLEL_ACCESSES_4:[0-9]+]], ![[ISVECTORIZED_13:[0-9]+]], 
![[UNROLL_COUNT_13:[0-9]+]], ![[UNROLL_FOLLOWUP_14:[0-9]+]]}
-// CHECK-DAG: ![[ISVECTORIZED_13:[0-9]+]] = !{!"llvm.loop.isvectorized"}
-// CHECK-DAG: ![[UNROLL_COUNT_13:[0-9]+]] = !{!"llvm.loop.unroll.count", i32 4}
-// CHECK-DAG: ![[UNROLL_FOLLOWUP_14:[0-9]+]] = 
!{!"llvm.loop.unroll.followup_all", ![[LOOP_15:[0-9]+]]}
-
-// CHECK-DAG: ![[LOOP_15:[0-9]+]] = distinct !{![[LOOP_15:[0-9]+]], 
![[PARALLEL_ACCESSES_4:[0-9]+]], ![[ISVECTORIZED_13:[0-9]+]], 
![[UNROLL_DISABLE_16:[0-9]+]], ![[PIPELINE_17:[0-9]+]]}
-// CHECK-DAG: ![[UNROLL_DISABLE_16:[0-9]+]] = !{!"llvm.loop.unroll.disable"}
-// CHECK-DAG: ![[PIPELINE_17:[0-9]+]] = 
!{!"llvm.loop.pipeline.initiationinterval", i32 10}
+// CHECK-DAG: ![[INNERLOOP_3]] = distinct !{![[INNERLOOP_3]], 
![[PARALLEL_ACCESSES_4:[0-9]+]], ![[DISTRIBUTE_5:[0-9]+]], 
![[DISTRIBUTE_FOLLOWUP_6:[0-9]+]]}
+// CHECK-DAG: ![[PARALLEL_ACCESSES_4]] = !{!"llvm.loop.parallel_accesses", 
![[ACCESSGROUP_2]]}
+// CHECK-DAG: ![[DISTRIBUTE_5]] = !{!"llvm.loop.distribute.enable", i1 true}
+// CHECK-DAG: ![[DISTRIBUTE_FOLLOWUP_6]] = 
!{!"llvm.loop.distribute.followup_all", ![[LOOP_7:[0-9]+]]}
+
+// CHECK-DAG: ![[LOOP_7]] = distinct !{![[LOOP_7]], ![[PARALLEL_ACCESSES_4]], 
![[VECTORIZE_8:[0-9]+]]}
+// CHECK-DAG: ![[VECTORIZE_8]] = !{!"llvm.loop.vectorize.enable", i1 true}
+
+// CHECK-DAG: ![[OUTERLOOP_9]] = distinct !{![[OUTERLOOP_9]], [[MP:![0-9]+]], 
![[UNROLLANDJAM_COUNT_10:[0-9]+]], ![[UNROLLANDJAM_FOLLOWUPINNER_11:[0-9]+]]}
+// CHECK-DAG: ![[UNROLLANDJAM_COUNT_10]] = 
!{!"llvm.loop.unroll_and_jam.count", i32 4}
+// CHECK-DAG: ![[UNROLLANDJAM_FOLLOWUPINNER_11]] = 
!{!"llvm.loop.unroll_and_jam.followup_inner", ![[LOOP_12:[0-9]+]]}
+
+// CHECK-DAG: ![[LOOP_12]] = distinct !{![[LOOP_12:[0-9]+]], 
![[PARALLEL_ACCESSES_4]], ![[ISVECTORIZED_13:[0-9]+]], 
![[UNROLL_COUNT_13:[0-9]+]], ![[UNROLL_FOLLOWUP_14:[0-9]+]]}
+// CHECK-DAG: ![[ISVECTORIZED_13]] = !{!"llvm.loop.isvectorized"}
+// CHECK-DAG: ![[UNROLL_COUNT_13]] = !{!"llvm.loop.unroll.count", i32 4}
+// CHECK-DAG: ![[UNROLL_FOLLOWUP_14]] = !{!"llvm.loop.unroll.followup_all", 
![[LOOP_15:[0-9]+]]}
+
+// CHECK-DAG: ![[LOOP_15]] = distinct !{![[LOOP_15]], 
![[PARALLEL_ACCESSES_4]], ![[ISVECTORIZED_13]], ![[UNROLL_DISABLE_16:[0-9]+]], 
![[PIPELINE_17:[0-9]+]]}
+// CHECK-DAG: ![[UNROLL_DISABLE_16]] = !{!"llvm.loop.unroll.disable"}
+// CHECK-DAG: ![[PIPELINE_17]] = !{!"llvm.loop.pipeline.initiationinterval", 
i32 10}


Index: clang/test/CodeGenCXX/pragma-followup_inner.cpp
===
--- clang/test/CodeGenCXX/pragma-followup_inner.cpp
+++ clang/test/CodeGenCXX/pragma-followup_inner.cpp
@@ -20,23 +20,23 @@
 
 // CHECK-DAG: ![[ACCESSGROUP_2:[0-9]+]] = distinct !{}
 
-// CHECK-DAG: ![[INNERLOOP_3:[0-9]+]] = distinct !{![[INNERLOOP_3:[0-9]+]], ![[PARALLEL_ACCESSES_4:[0-9]+]], ![[DISTRIBUTE_5:[0-9]+]], ![[DISTRIBUTE_FOLLOWUP_6:[0-9]+]]}
-// CHECK-DAG: ![[PARALLEL_ACCESSES_4:[0-

[PATCH] D134410: [clang][CodeGen] Add noundef metadata to load instructions (preliminary 1 or 3)

[John McIver via Phabricator via cfe-commits]

jmciver updated this revision to Diff 480265.
jmciver added a comment.

Updating D134410 : [clang][CodeGen] Add 
noundef metadata to load instructions (preliminary 1 or 3)

The following tests have been updated:

- avx512f-builtins.c
- avx512fp16-builtins.c
- matrix-type-operators.c
- matrix-type-operators.cpp


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134410/new/

https://reviews.llvm.org/D134410

Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/CGExpr.cpp
  clang/test/CodeGen/X86/avx-builtins.c
  clang/test/CodeGen/X86/avx512bw-builtins.c
  clang/test/CodeGen/X86/avx512f-builtins.c
  clang/test/CodeGen/X86/avx512fp16-builtins.c
  clang/test/CodeGen/X86/avx512vl-builtins.c
  clang/test/CodeGen/X86/avx512vlbw-builtins.c
  clang/test/CodeGen/X86/sse-builtins.c
  clang/test/CodeGen/X86/sse2-builtins.c
  clang/test/CodeGen/aarch64-ls64-inline-asm.c
  clang/test/CodeGen/aarch64-ls64.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/matrix-type-operators.c
  clang/test/CodeGen/memcpy-inline-builtin.c
  clang/test/CodeGen/tbaa-array.cpp
  clang/test/CodeGen/tbaa-base.cpp
  clang/test/CodeGen/tbaa.cpp
  clang/test/CodeGen/ubsan-pass-object-size.c
  clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu
  clang/test/CodeGenCXX/attr-likelihood-if-branch-weights.cpp
  clang/test/CodeGenCXX/attr-likelihood-switch-branch-weights.cpp
  clang/test/CodeGenCXX/builtin-bit-cast-no-tbaa.cpp
  clang/test/CodeGenCXX/debug-info-line.cpp
  clang/test/CodeGenCXX/matrix-type-operators.cpp
  clang/test/CodeGenCXX/pr12251.cpp
  clang/test/CodeGenCXX/pragma-followup_inner.cpp
  clang/test/OpenMP/cancel_codegen.cpp
  clang/test/OpenMP/cancellation_point_codegen.cpp
  clang/test/OpenMP/distribute_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_parallel_for_simd_proc_bind_codegen.cpp
  clang/test/OpenMP/distribute_simd_codegen.cpp
  clang/test/OpenMP/distribute_simd_private_codegen.cpp
  clang/test/OpenMP/distribute_simd_reduction_codegen.cpp
  clang/test/OpenMP/for_reduction_task_codegen.cpp
  clang/test/OpenMP/irbuilder_safelen.cpp
  clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
  clang/test/OpenMP/irbuilder_simd_aligned.cpp
  clang/test/OpenMP/irbuilder_simdlen.cpp
  clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
  clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp
  clang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
  clang/test/OpenMP/ordered_codegen.cpp
  clang/test/OpenMP/parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_aligned_codegen.cpp
  clang/test/OpenMP/parallel_for_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp
  clang/test/OpenMP/parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/parallel_sections_reduction_task_codegen.cpp
  clang/test/OpenMP/sections_reduction_task_codegen.cpp
  clang/test/OpenMP/target_defaultmap_codegen_01.cpp
  clang/test/OpenMP/target_in_reduction_codegen.cpp
  clang/test/OpenMP/target_is_device_ptr_codegen.cpp
  clang/test/OpenMP/target_map_codegen_00.cpp
  clang/test/OpenMP/target_map_codegen_01.cpp
  clang/test/OpenMP/target_map_codegen_02.cpp
  clang/test/OpenMP/target_map_codegen_04.cpp
  clang/test/OpenMP/target_map_codegen_05.cpp
  clang/test/OpenMP/target_map_codegen_07.cpp
  clang/test/OpenMP/target_map_codegen_11.cpp
  clang/test/OpenMP/target_map_codegen_13.cpp
  clang/test/OpenMP/target_map_codegen_14.cpp
  clang/test/OpenMP/target_map_codegen_15.cpp
  clang/test/OpenMP/target_map_codegen_17.cpp
  clang/test/OpenMP/target_map_codegen_26.cpp
  clang/test/OpenMP/target_map_codegen_27.cpp
  clang/test/OpenMP/target_map_codegen_29.cpp
  clang/test/OpenMP/target_parallel_codegen.cpp
  clang/test/OpenMP/target_parallel_for_codegen.cpp
  clang/test/OpenMP/target_parallel_for_reduction_task_codegen.cpp
  clang/test/OpenMP/target_parallel_for_simd_codegen.cpp
  clang/test/OpenMP/target_parallel_reduction_task_codegen.cpp
  clang/test/OpenMP/target_teams_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_order_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_reduction_task_codegen.cpp
  
clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
  clang/test/OpenMP/target_teams_distribute_parallel_for_simd_if_codegen.cpp

[PATCH] D138983: [clang][CodeGen] Add noundef metadata to load instructions (preliminary 3 or 3)

[John McIver via Phabricator via cfe-commits]

jmciver updated this revision to Diff 480267.
jmciver added a comment.

Updating D138983 : [clang][CodeGen] Add 
noundef metadata to load instructions (preliminary 3 or 3)

The following tests have been updated:

- matrix-type-operators.c


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138983/new/

https://reviews.llvm.org/D138983

Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/test/CodeGen/matrix-type-operators.c
  clang/test/CodeGen/vector-noundef.c
  clang/test/CodeGenCXX/vector-noundef.cpp

Index: clang/test/CodeGenCXX/vector-noundef.cpp
===
--- clang/test/CodeGenCXX/vector-noundef.cpp
+++ clang/test/CodeGenCXX/vector-noundef.cpp
@@ -6,6 +6,9 @@
 using VecOfThreeChars __attribute__((ext_vector_type(3))) = char;
 using VecOfThreeUChars __attribute__((ext_vector_type(3))) = unsigned char;
 
+using VecOfFourFloats __attribute__((ext_vector_type(4))) = float;
+using VecOfTwoFloats __attribute__((ext_vector_type(2))) = float;
+
 // CHECK-LABEL: @_Z15getElement4BoolRDv4_b(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[A_ADDR:%.*]] = alloca ptr, align 8
@@ -82,3 +85,33 @@
 {
   return a[0];
 }
+
+// CHECK-LABEL: @_Z16vectorSubsectionRDv2_fRDv4_f(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VEC2_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT:[[VEC4_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT:store ptr [[VEC2:%.*]], ptr [[VEC2_ADDR]], align 8
+// CHECK-NEXT:store ptr [[VEC4:%.*]], ptr [[VEC4_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, ptr [[TMP0]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:[[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <2 x i32> 
+// CHECK-NEXT:[[TMP3:%.*]] = load ptr, ptr [[VEC2_ADDR]], align 8
+// CHECK-NEXT:store <2 x float> [[TMP2]], ptr [[TMP3]], align 8
+// CHECK-NEXT:ret void
+//
+// DISABLE-LABEL: @_Z16vectorSubsectionRDv2_fRDv4_f(
+// DISABLE-NEXT:  entry:
+// DISABLE-NEXT:[[VEC2_ADDR:%.*]] = alloca ptr, align 8
+// DISABLE-NEXT:[[VEC4_ADDR:%.*]] = alloca ptr, align 8
+// DISABLE-NEXT:store ptr [[VEC2:%.*]], ptr [[VEC2_ADDR]], align 8
+// DISABLE-NEXT:store ptr [[VEC4:%.*]], ptr [[VEC4_ADDR]], align 8
+// DISABLE-NEXT:[[TMP0:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// DISABLE-NEXT:[[TMP1:%.*]] = load <4 x float>, ptr [[TMP0]], align 16
+// DISABLE-NEXT:[[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <2 x i32> 
+// DISABLE-NEXT:[[TMP3:%.*]] = load ptr, ptr [[VEC2_ADDR]], align 8
+// DISABLE-NEXT:store <2 x float> [[TMP2]], ptr [[TMP3]], align 8
+// DISABLE-NEXT:ret void
+//
+void vectorSubsection(VecOfTwoFloats& vec2, VecOfFourFloats& vec4) {
+vec2 = vec4.xy;
+}
Index: clang/test/CodeGen/vector-noundef.c
===
--- /dev/null
+++ clang/test/CodeGen/vector-noundef.c
@@ -0,0 +1,107 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -no-opaque-pointers -flax-vector-conversions=none -ffreestanding -triple x86_64-gnu-linux -target-feature +avx512f -O0 -enable-noundef-load-analysis -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -no-opaque-pointers -flax-vector-conversions=none -ffreestanding -triple x86_64-gnu-linux -target-feature +avx512f -O0 -no-enable-noundef-load-analysis -emit-llvm -o - %s | FileCheck %s --check-prefix=DISABLE
+
+#include 
+
+// CHECK-LABEL: @test_mm_mask_div_ss(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[__A_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__B_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__W_ADDR_I:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__U_ADDR_I:%.*]] = alloca i8, align 1
+// CHECK-NEXT:[[__A_ADDR_I2:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__B_ADDR_I2:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__W_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__U_ADDR:%.*]] = alloca i8, align 1
+// CHECK-NEXT:[[__A_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:[[__B_ADDR:%.*]] = alloca <4 x float>, align 16
+// CHECK-NEXT:store <4 x float> [[__W:%.*]], <4 x float>* [[__W_ADDR]], align 16
+// CHECK-NEXT:store i8 [[__U:%.*]], i8* [[__U_ADDR]], align 1
+// CHECK-NEXT:store <4 x float> [[__A:%.*]], <4 x float>* [[__A_ADDR]], align 16
+// CHECK-NEXT:store <4 x float> [[__B:%.*]], <4 x float>* [[__B_ADDR]], align 16
+// CHECK-NEXT:[[TMP0:%.*]] = load <4 x float>, <4 x float>* [[__W_ADDR]], align 16, !noundef [[NOUNDEF2:![0-9]+]]
+// CHECK-NEXT:[[TMP1:%.*]] = load i8, i8* [[__U_ADDR]], align 1
+// CHECK-NEXT:[[TMP2:%.*]] = load <4 x float>, <4 x float>* [[__A_ADDR]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:[[TMP3:%.*]] = load 

[PATCH] D139378: Add noundef metadata to load instructions (preliminary 4 or 4)

[John McIver via Phabricator via cfe-commits]

jmciver created this revision.
jmciver added reviewers: vitalybuka, jdoerfert, rjmccall, aqjune, efriedma, 
nikic.
Herald added a project: All.
jmciver retitled this revision from "[clang][CodeGen] Add noundef metadata to 
load instructions (item 4)" to "Add noundef metadata to load instructions 
(preliminary 4 or 4)".
jmciver edited the summary of this revision.
jmciver published this revision for review.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Add noundef attribute support when an rvalue is being stored into a 
vector/matrix lvalue.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139378

Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/test/CodeGen/matrix-type-operators.c
  clang/test/CodeGenCXX/matrix-type-operators.cpp
  clang/test/CodeGenCXX/vector-noundef.cpp

Index: clang/test/CodeGenCXX/vector-noundef.cpp
===
--- clang/test/CodeGenCXX/vector-noundef.cpp
+++ clang/test/CodeGenCXX/vector-noundef.cpp
@@ -115,3 +115,65 @@
 void vectorSubsection(VecOfTwoFloats& vec2, VecOfFourFloats& vec4) {
 vec2 = vec4.xy;
 }
+
+// CHECK-LABEL: @_Z18vectorStoreElementRDv2_ff(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VEC2_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT:[[F_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:store ptr [[VEC2:%.*]], ptr [[VEC2_ADDR]], align 8
+// CHECK-NEXT:store float [[F:%.*]], ptr [[F_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr, ptr [[VEC2_ADDR]], align 8
+// CHECK-NEXT:[[TMP2:%.*]] = load <2 x float>, ptr [[TMP1]], align 8, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:[[TMP3:%.*]] = insertelement <2 x float> [[TMP2]], float [[TMP0]], i64 0
+// CHECK-NEXT:store <2 x float> [[TMP3]], ptr [[TMP1]], align 8
+// CHECK-NEXT:ret void
+//
+// DISABLE-LABEL: @_Z18vectorStoreElementRDv2_ff(
+// DISABLE-NEXT:  entry:
+// DISABLE-NEXT:[[VEC2_ADDR:%.*]] = alloca ptr, align 8
+// DISABLE-NEXT:[[F_ADDR:%.*]] = alloca float, align 4
+// DISABLE-NEXT:store ptr [[VEC2:%.*]], ptr [[VEC2_ADDR]], align 8
+// DISABLE-NEXT:store float [[F:%.*]], ptr [[F_ADDR]], align 4
+// DISABLE-NEXT:[[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4
+// DISABLE-NEXT:[[TMP1:%.*]] = load ptr, ptr [[VEC2_ADDR]], align 8
+// DISABLE-NEXT:[[TMP2:%.*]] = load <2 x float>, ptr [[TMP1]], align 8
+// DISABLE-NEXT:[[TMP3:%.*]] = insertelement <2 x float> [[TMP2]], float [[TMP0]], i64 0
+// DISABLE-NEXT:store <2 x float> [[TMP3]], ptr [[TMP1]], align 8
+// DISABLE-NEXT:ret void
+//
+void vectorStoreElement(VecOfTwoFloats& vec2, float f) {
+vec2.x = f;
+}
+
+// CHECK-LABEL: @_Z12vectorRotateRDv4_f(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VEC4_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT:store ptr [[VEC4:%.*]], ptr [[VEC4_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, ptr [[TMP0]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:[[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <3 x i32> 
+// CHECK-NEXT:[[TMP3:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// CHECK-NEXT:[[TMP4:%.*]] = load <4 x float>, ptr [[TMP3]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:[[TMP5:%.*]] = shufflevector <3 x float> [[TMP2]], <3 x float> poison, <4 x i32> 
+// CHECK-NEXT:[[TMP6:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[TMP5]], <4 x i32> 
+// CHECK-NEXT:store <4 x float> [[TMP6]], ptr [[TMP3]], align 16
+// CHECK-NEXT:ret void
+//
+// DISABLE-LABEL: @_Z12vectorRotateRDv4_f(
+// DISABLE-NEXT:  entry:
+// DISABLE-NEXT:[[VEC4_ADDR:%.*]] = alloca ptr, align 8
+// DISABLE-NEXT:store ptr [[VEC4:%.*]], ptr [[VEC4_ADDR]], align 8
+// DISABLE-NEXT:[[TMP0:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// DISABLE-NEXT:[[TMP1:%.*]] = load <4 x float>, ptr [[TMP0]], align 16
+// DISABLE-NEXT:[[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <3 x i32> 
+// DISABLE-NEXT:[[TMP3:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// DISABLE-NEXT:[[TMP4:%.*]] = load <4 x float>, ptr [[TMP3]], align 16
+// DISABLE-NEXT:[[TMP5:%.*]] = shufflevector <3 x float> [[TMP2]], <3 x float> poison, <4 x i32> 
+// DISABLE-NEXT:[[TMP6:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[TMP5]], <4 x i32> 
+// DISABLE-NEXT:store <4 x float> [[TMP6]], ptr [[TMP3]], align 16
+// DISABLE-NEXT:ret void
+//
+void vectorRotate(VecOfFourFloats& vec4) {
+vec4.xyz = vec4.zyx;
+}
Index: clang/test/CodeGenCXX/matrix-type-operators.cpp
===
--- clang/test/CodeGenCXX/matrix-type-operators.cpp
+++ clang/test/CodeGenCXX/matrix-type-operators.cpp
@@ -239,7 +239,7 @@
   // CHECK-NEXT:[[IDX2:%.*]] = add i64 [[IDX1]],

[PATCH] D139378: [clang][CodeGen] Add noundef metadata to load instructions (preliminary 4 or 4)

[John McIver via Phabricator via cfe-commits]

jmciver updated this revision to Diff 480767.
jmciver added a comment.

Updating D139378 : [clang][CodeGen] Add 
noundef metadata to load instructions (preliminary 4 or 4)

Update vector-noundef.cpp with rvalue element being stored in lvalue vector.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139378/new/

https://reviews.llvm.org/D139378

Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/test/CodeGen/matrix-type-operators.c
  clang/test/CodeGen/vector-noundef.c
  clang/test/CodeGenCXX/matrix-type-operators.cpp
  clang/test/CodeGenCXX/vector-noundef.cpp

Index: clang/test/CodeGenCXX/vector-noundef.cpp
===
--- clang/test/CodeGenCXX/vector-noundef.cpp
+++ clang/test/CodeGenCXX/vector-noundef.cpp
@@ -115,3 +115,65 @@
 void vectorSubsection(VecOfTwoFloats& vec2, VecOfFourFloats& vec4) {
 vec2 = vec4.xy;
 }
+
+// CHECK-LABEL: @_Z18vectorStoreElementRDv2_ff(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VEC2_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT:[[F_ADDR:%.*]] = alloca float, align 4
+// CHECK-NEXT:store ptr [[VEC2:%.*]], ptr [[VEC2_ADDR]], align 8
+// CHECK-NEXT:store float [[F:%.*]], ptr [[F_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr, ptr [[VEC2_ADDR]], align 8
+// CHECK-NEXT:[[TMP2:%.*]] = load <2 x float>, ptr [[TMP1]], align 8, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:[[TMP3:%.*]] = insertelement <2 x float> [[TMP2]], float [[TMP0]], i64 0
+// CHECK-NEXT:store <2 x float> [[TMP3]], ptr [[TMP1]], align 8
+// CHECK-NEXT:ret void
+//
+// DISABLE-LABEL: @_Z18vectorStoreElementRDv2_ff(
+// DISABLE-NEXT:  entry:
+// DISABLE-NEXT:[[VEC2_ADDR:%.*]] = alloca ptr, align 8
+// DISABLE-NEXT:[[F_ADDR:%.*]] = alloca float, align 4
+// DISABLE-NEXT:store ptr [[VEC2:%.*]], ptr [[VEC2_ADDR]], align 8
+// DISABLE-NEXT:store float [[F:%.*]], ptr [[F_ADDR]], align 4
+// DISABLE-NEXT:[[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4
+// DISABLE-NEXT:[[TMP1:%.*]] = load ptr, ptr [[VEC2_ADDR]], align 8
+// DISABLE-NEXT:[[TMP2:%.*]] = load <2 x float>, ptr [[TMP1]], align 8
+// DISABLE-NEXT:[[TMP3:%.*]] = insertelement <2 x float> [[TMP2]], float [[TMP0]], i64 0
+// DISABLE-NEXT:store <2 x float> [[TMP3]], ptr [[TMP1]], align 8
+// DISABLE-NEXT:ret void
+//
+void vectorStoreElement(VecOfTwoFloats& vec2, float f) {
+vec2.x = f;
+}
+
+// CHECK-LABEL: @_Z12vectorRotateRDv4_f(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VEC4_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-NEXT:store ptr [[VEC4:%.*]], ptr [[VEC4_ADDR]], align 8
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load <4 x float>, ptr [[TMP0]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:[[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <3 x i32> 
+// CHECK-NEXT:[[TMP3:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// CHECK-NEXT:[[TMP4:%.*]] = load <4 x float>, ptr [[TMP3]], align 16, !noundef [[NOUNDEF2]]
+// CHECK-NEXT:[[TMP5:%.*]] = shufflevector <3 x float> [[TMP2]], <3 x float> poison, <4 x i32> 
+// CHECK-NEXT:[[TMP6:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[TMP5]], <4 x i32> 
+// CHECK-NEXT:store <4 x float> [[TMP6]], ptr [[TMP3]], align 16
+// CHECK-NEXT:ret void
+//
+// DISABLE-LABEL: @_Z12vectorRotateRDv4_f(
+// DISABLE-NEXT:  entry:
+// DISABLE-NEXT:[[VEC4_ADDR:%.*]] = alloca ptr, align 8
+// DISABLE-NEXT:store ptr [[VEC4:%.*]], ptr [[VEC4_ADDR]], align 8
+// DISABLE-NEXT:[[TMP0:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// DISABLE-NEXT:[[TMP1:%.*]] = load <4 x float>, ptr [[TMP0]], align 16
+// DISABLE-NEXT:[[TMP2:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <3 x i32> 
+// DISABLE-NEXT:[[TMP3:%.*]] = load ptr, ptr [[VEC4_ADDR]], align 8
+// DISABLE-NEXT:[[TMP4:%.*]] = load <4 x float>, ptr [[TMP3]], align 16
+// DISABLE-NEXT:[[TMP5:%.*]] = shufflevector <3 x float> [[TMP2]], <3 x float> poison, <4 x i32> 
+// DISABLE-NEXT:[[TMP6:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[TMP5]], <4 x i32> 
+// DISABLE-NEXT:store <4 x float> [[TMP6]], ptr [[TMP3]], align 16
+// DISABLE-NEXT:ret void
+//
+void vectorRotate(VecOfFourFloats& vec4) {
+vec4.xyz = vec4.zyx;
+}
Index: clang/test/CodeGenCXX/matrix-type-operators.cpp
===
--- clang/test/CodeGenCXX/matrix-type-operators.cpp
+++ clang/test/CodeGenCXX/matrix-type-operators.cpp
@@ -239,7 +239,7 @@
   // CHECK-NEXT:[[IDX2:%.*]] = add i64 [[IDX1]], [[I_EXT]]
   // OPT-NEXT:  [[CMP:%.*]] = icmp ult i64 [[IDX2]], 4
   // OPT-NEXT:  call void @llvm.assume(i1 [[CMP]])
-  // CHECK-NEXT:[[MAT:%.*]] = load <4 x i32>, ptr {{

[PATCH] D139505: [clang][CodeGen] Add noundef metadata to loading of references (preliminary 5 of 5)

[John McIver via Phabricator via cfe-commits]

jmciver created this revision.
jmciver added reviewers: vitalybuka, jdoerfert, rjmccall, aqjune, efriedma, 
nikic.
Herald added a project: All.
jmciver retitled this revision from "[clang][CodeGen] Add noundef metadata to 
loading of references (item 5)" to "[clang][CodeGen] Add noundef metadata to 
loading of references (preliminary 5 of 5)".
jmciver published this revision for review.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Update CodGenFunction::EmitLoadOfReference to apply the noundef attribute to
load instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139505

Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/test/CodeGen/tbaa-reference.cpp
  clang/test/CodeGenCXX/matrix-type-operators.cpp
  clang/test/CodeGenCXX/vector-noundef.cpp
  clang/test/OpenMP/for_reduction_codegen.cpp
  clang/test/OpenMP/for_reduction_codegen_UDR.cpp
  clang/test/OpenMP/target_map_codegen_35.cpp
  
clang/test/utils/update_cc_test_checks/Inputs/resolve-tmp-conflict.cpp.expected

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