[PATCH] D92762: [clang][AArch64][SVE] Avoid going through memory for coerced VLST arguments

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 310185.
joechrisellis added a comment.

Do not try to generate `llvm.experimental.vector.extract` instructions if the 
vector element types differ.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92762/new/

https://reviews.llvm.org/D92762

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c

Index: clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
@@ -13,11 +13,8 @@
 
 // CHECK-LABEL: @to_svint32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <16 x i32>, <16 x i32>* [[TYPE]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TYPE1]], i64 0)
+// CHECK-NEXT:[[TYPE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TYPE]], i64 0)
 // CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 svint32_t to_svint32_t(fixed_int32_t type) {
@@ -39,11 +36,8 @@
 
 // CHECK-LABEL: @to_svfloat64_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <8 x double>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x double>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x double>, <8 x double>* [[TYPE]], align 16, [[TBAA6]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 x double> [[TYPE1]], i64 0)
+// CHECK-NEXT:[[TYPE:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 x double> [[TYPE]], i64 0)
 // CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 svfloat64_t to_svfloat64_t(fixed_float64_t type) {
@@ -69,7 +63,7 @@
 // CHECK-NEXT:[[TYPE_ADDR:%.*]] = alloca <8 x i8>, align 16
 // CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x i8>* [[TYPE]] to *
 // CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x i8>, <8 x i8>* [[TYPE]], align 16, [[TBAA6]]
+// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x i8>, <8 x i8>* [[TYPE]], align 16, [[TBAA6:!tbaa !.*]]
 // CHECK-NEXT:store <8 x i8> [[TYPE1]], <8 x i8>* [[TYPE_ADDR]], align 16, [[TBAA6]]
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast <8 x i8>* [[TYPE_ADDR]] to *
 // CHECK-NEXT:[[TMP2:%.*]] = load , * [[TMP1]], align 16, [[TBAA6]]
@@ -130,11 +124,8 @@
 
 // CHECK-LABEL: @from_fixed_int32_t__to_gnu_int32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <16 x i32>, <16 x i32>* [[TYPE]], align 16, [[TBAA6]]
-// CHECK-NEXT:store <16 x i32> [[TYPE1]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
+// CHECK-NEXT:[[TYPE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:store <16 x i32> [[TYPE]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
 // CHECK-NEXT:ret void
 //
 gnu_int32_t from_fixed_int32_t__to_gnu_int32_t(fixed_int32_t type) {
Index: clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
@@ -24,17 +24,14 @@
 
 // CHECK-LABEL: @fixed_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[X:%.*]] = alloca <16 x i32>, align 16
 // CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[X]] to *
-// CHECK-NEXT:store  [[X_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[X1:%.*]] = load <16 x i32>, <16 x i32>* [[X]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[X1]], i64 0)
+// CHECK-NEXT:[[X:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
+// CHECK-NE

[PATCH] D92761: [clang][AArch64][SVE] Avoid going through memory for VLAT <-> VLST casts

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 310529.
joechrisellis added a comment.
Herald added a subscriber: NickHung.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92761/new/

https://reviews.llvm.org/D92761

Files:
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
  llvm/include/llvm/IR/IRBuilder.h

Index: llvm/include/llvm/IR/IRBuilder.h
===
--- llvm/include/llvm/IR/IRBuilder.h
+++ llvm/include/llvm/IR/IRBuilder.h
@@ -923,6 +923,20 @@
 return CreateBinaryIntrinsic(Intrinsic::maximum, LHS, RHS, nullptr, Name);
   }
 
+  CallInst *CreateExtractVector(Type *DstType, Value *SrcVec, Value *Idx,
+const Twine &Name = "") {
+return CreateIntrinsic(Intrinsic::experimental_vector_extract,
+   {DstType, SrcVec->getType()}, {SrcVec, Idx}, nullptr,
+   Name);
+  }
+
+  CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec,
+   Value *Idx, const Twine &Name = "") {
+return CreateIntrinsic(Intrinsic::experimental_vector_insert,
+   {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
+   nullptr, Name);
+  }
+
 private:
   /// Create a call to a masked intrinsic with given Id.
   CallInst *CreateMaskedIntrinsic(Intrinsic::ID Id, ArrayRef Ops,
Index: clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
@@ -21,40 +21,28 @@
 
 // CHECK-128-LABEL: @write_global_i64(
 // CHECK-128-NEXT:  entry:
-// CHECK-128-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-128-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-128-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <2 x i64>*
-// CHECK-128-NEXT:[[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[TMP0]], align 16, [[TBAA10:!tbaa !.*]]
-// CHECK-128-NEXT:store <2 x i64> [[TMP1]], <2 x i64>* @global_i64, align 16, [[TBAA10]]
+// CHECK-128-NEXT:[[CASTFIXEDSVE:%.*]] = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64( [[V:%.*]], i64 0)
+// CHECK-128-NEXT:store <2 x i64> [[CASTFIXEDSVE]], <2 x i64>* @global_i64, align 16, [[TBAA6:!tbaa !.*]]
 // CHECK-128-NEXT:ret void
 //
 // CHECK-512-LABEL: @write_global_i64(
 // CHECK-512-NEXT:  entry:
-// CHECK-512-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-512-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-512-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <8 x i64>*
-// CHECK-512-NEXT:[[TMP1:%.*]] = load <8 x i64>, <8 x i64>* [[TMP0]], align 16, [[TBAA10:!tbaa !.*]]
-// CHECK-512-NEXT:store <8 x i64> [[TMP1]], <8 x i64>* @global_i64, align 16, [[TBAA10]]
+// CHECK-512-NEXT:[[CASTFIXEDSVE:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64( [[V:%.*]], i64 0)
+// CHECK-512-NEXT:store <8 x i64> [[CASTFIXEDSVE]], <8 x i64>* @global_i64, align 16, [[TBAA6:!tbaa !.*]]
 // CHECK-512-NEXT:ret void
 //
 void write_global_i64(svint64_t v) { global_i64 = v; }
 
 // CHECK-128-LABEL: @write_global_bf16(
 // CHECK-128-NEXT:  entry:
-// CHECK-128-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-128-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA11:!tbaa !.*]]
-// CHECK-128-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <8 x bfloat>*
-// CHECK-128-NEXT:[[TMP1:%.*]] = load <8 x bfloat>, <8 x bfloat>* [[TMP0]], align 16, [[TBAA10]]
-// CHECK-128-NEXT:store <8 x bfloat> [[TMP1]], <8 x bfloat>* @global_bf16, align 16, [[TBAA10]]
+// CHECK-128-NEXT:[[CASTFIXEDSVE:%.*]] = call <8 x bfloat> @llvm.experimental.vector.extract.v8bf16.nxv8bf16( [[V:%.*]], i64 0)
+// CHECK-128-NEXT:store <8 x bfloat> [[CASTFIXEDSVE]], <8 x bfloat>* @global_bf16, align 16, [[TBAA6]]
 // CHECK-128-NEXT:ret void
 //
 // CHECK-512-LABEL: @write_global_bf16(
 // CHECK-512-NEXT:  entry:
-// CHECK-512-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-512-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA11:!tbaa !.*]]
-// CHECK-512-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <32 x bfloat>*
-// CHECK-512-NEXT:[[TMP1:%.*]] = load <32 x bfloat>, <32 x bfloat>* [[TMP0]], align 16, [[TBAA10]]
-// CHECK-512-NEXT:store <32 x bfloat> [[TMP1]], <32 x bfloat>* @global_bf16, align 16, [[TBAA10]]
+// CHECK-512-NEXT:[[CASTFIXEDSVE:%.*]] = call <32 x bfloat> @llvm.experimental.vector.extr

[PATCH] D92762: [clang][AArch64][SVE] Avoid going through memory for coerced VLST arguments

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 310532.
joechrisellis added a comment.
Herald added a subscriber: NickHung.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92762/new/

https://reviews.llvm.org/D92762

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c

Index: clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
@@ -13,11 +13,8 @@
 
 // CHECK-LABEL: @to_svint32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <16 x i32>, <16 x i32>* [[TYPE]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TYPE1]], i64 0)
+// CHECK-NEXT:[[TYPE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TYPE]], i64 0)
 // CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 svint32_t to_svint32_t(fixed_int32_t type) {
@@ -39,11 +36,8 @@
 
 // CHECK-LABEL: @to_svfloat64_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <8 x double>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x double>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x double>, <8 x double>* [[TYPE]], align 16, [[TBAA6]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 x double> [[TYPE1]], i64 0)
+// CHECK-NEXT:[[TYPE:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 x double> [[TYPE]], i64 0)
 // CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 svfloat64_t to_svfloat64_t(fixed_float64_t type) {
@@ -69,7 +63,7 @@
 // CHECK-NEXT:[[TYPE_ADDR:%.*]] = alloca <8 x i8>, align 16
 // CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x i8>* [[TYPE]] to *
 // CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x i8>, <8 x i8>* [[TYPE]], align 16, [[TBAA6]]
+// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x i8>, <8 x i8>* [[TYPE]], align 16, [[TBAA6:!tbaa !.*]]
 // CHECK-NEXT:store <8 x i8> [[TYPE1]], <8 x i8>* [[TYPE_ADDR]], align 16, [[TBAA6]]
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast <8 x i8>* [[TYPE_ADDR]] to *
 // CHECK-NEXT:[[TMP2:%.*]] = load , * [[TMP1]], align 16, [[TBAA6]]
@@ -130,11 +124,8 @@
 
 // CHECK-LABEL: @from_fixed_int32_t__to_gnu_int32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <16 x i32>, <16 x i32>* [[TYPE]], align 16, [[TBAA6]]
-// CHECK-NEXT:store <16 x i32> [[TYPE1]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
+// CHECK-NEXT:[[TYPE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:store <16 x i32> [[TYPE]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
 // CHECK-NEXT:ret void
 //
 gnu_int32_t from_fixed_int32_t__to_gnu_int32_t(fixed_int32_t type) {
Index: clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
@@ -24,17 +24,14 @@
 
 // CHECK-LABEL: @fixed_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[X:%.*]] = alloca <16 x i32>, align 16
 // CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[X]] to *
-// CHECK-NEXT:store  [[X_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[X1:%.*]] = load <16 x i32>, <16 x i32>* [[X]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[X1]], i64 0)
+// CHECK-NEXT:[[X:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vecto

[PATCH] D92761: [clang][AArch64][SVE] Avoid going through memory for VLAT <-> VLST casts

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis added reviewers: c-rhodes, aeubanks.
joechrisellis added subscribers: aeubanks, c-rhodes.
joechrisellis added a comment.

Adding reviewers @c-rhodes and @aeubanks because `git blame` tells me they've 
touched the surrounding code. 🙂


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92761/new/

https://reviews.llvm.org/D92761

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D93206: [AArch64][NEON] Remove undocumented vceqz{,q}_p16, vml{a,s}q_n_f64 intrinsics

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis created this revision.
joechrisellis added reviewers: bsmith, pbarrio, AshokBhat.
Herald added subscribers: danielkiss, kristof.beyls.
joechrisellis requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Prior to this patch, Clang supported the following C/C++ intrinsics:

  vceqz_p16
  vceqzq_p16
  vmlaq_n_f64
  vmlsq_n_f64

... exposed through arm_neon.h. However, these intrinsics are not part
of the ACLE, allowing developers to write code that is not compatible
with other toolchains.

This patch removes these intrinsics.

There is a bug report capturing this issue here:

  https://bugs.llvm.org/show_bug.cgi?id=47471


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93206

Files:
  clang/include/clang/Basic/arm_neon.td
  clang/test/CodeGen/aarch64-neon-fma.c
  clang/test/CodeGen/aarch64-neon-misc.c


Index: clang/test/CodeGen/aarch64-neon-misc.c
===
--- clang/test/CodeGen/aarch64-neon-misc.c
+++ clang/test/CodeGen/aarch64-neon-misc.c
@@ -198,24 +198,6 @@
   return vceqzq_p8(a);
 }
 
-// CHECK-LABEL: @test_vceqz_p16(
-// CHECK:   [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
-// CHECK:   [[TMP1:%.*]] = icmp eq <4 x i16> %a, zeroinitializer
-// CHECK:   [[VCEQZ_I:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
-// CHECK:   ret <4 x i16> [[VCEQZ_I]]
-uint16x4_t test_vceqz_p16(poly16x4_t a) {
-  return vceqz_p16(a);
-}
-
-// CHECK-LABEL: @test_vceqzq_p16(
-// CHECK:   [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
-// CHECK:   [[TMP1:%.*]] = icmp eq <8 x i16> %a, zeroinitializer
-// CHECK:   [[VCEQZ_I:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
-// CHECK:   ret <8 x i16> [[VCEQZ_I]]
-uint16x8_t test_vceqzq_p16(poly16x8_t a) {
-  return vceqzq_p16(a);
-}
-
 // CHECK-LABEL: @test_vceqzq_f64(
 // CHECK:   [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
 // CHECK:   [[TMP1:%.*]] = fcmp oeq <2 x double> %a, zeroinitializer
Index: clang/test/CodeGen/aarch64-neon-fma.c
===
--- clang/test/CodeGen/aarch64-neon-fma.c
+++ clang/test/CodeGen/aarch64-neon-fma.c
@@ -26,16 +26,6 @@
   return vmlaq_n_f32(a, b, c);
 }
 
-// CHECK-LABEL: define <2 x double> @test_vmlaq_n_f64(<2 x double> %a, <2 x 
double> %b, double %c) #1 {
-// CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, 
i32 0
-// CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], 
double %c, i32 1
-// CHECK:   [[MUL_I:%.*]] = fmul <2 x double> %b, [[VECINIT1_I]]
-// CHECK:   [[ADD_I:%.*]] = fadd <2 x double> %a, [[MUL_I]]
-// CHECK:   ret <2 x double> [[ADD_I]]
-float64x2_t test_vmlaq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {
-  return vmlaq_n_f64(a, b, c);
-}
-
 // CHECK-LABEL: define <4 x float> @test_vmlsq_n_f32(<4 x float> %a, <4 x 
float> %b, float %c) #1 {
 // CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %c, i32 0
 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], 
float %c, i32 1
@@ -58,16 +48,6 @@
   return vmls_n_f32(a, b, c);
 }
 
-// CHECK-LABEL: define <2 x double> @test_vmlsq_n_f64(<2 x double> %a, <2 x 
double> %b, double %c) #1 {
-// CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, 
i32 0
-// CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], 
double %c, i32 1
-// CHECK:   [[MUL_I:%.*]] = fmul <2 x double> %b, [[VECINIT1_I]]
-// CHECK:   [[SUB_I:%.*]] = fsub <2 x double> %a, [[MUL_I]]
-// CHECK:   ret <2 x double> [[SUB_I]]
-float64x2_t test_vmlsq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {
-  return vmlsq_n_f64(a, b, c);
-}
-
 // CHECK-LABEL: define <2 x float> @test_vmla_lane_f32_0(<2 x float> %a, <2 x 
float> %b, <2 x float> %v) #0 {
 // CHECK:[[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
 // CHECK:[[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
Index: clang/include/clang/Basic/arm_neon.td
===
--- clang/include/clang/Basic/arm_neon.td
+++ clang/include/clang/Basic/arm_neon.td
@@ -786,9 +786,6 @@
 def FMLA_N : SOpInst<"vfma_n", "...1", "dQd", OP_FMLA_N>;
 def FMLS_N : SOpInst<"vfms_n", "...1", "fdQfQd", OP_FMLS_N>;
 
-def MLA_N : SOpInst<"vmla_n", "...1", "Qd", OP_MLA_N>;
-def MLS_N : SOpInst<"vmls_n", "...1", "Qd", OP_MLS_N>;
-
 

 // Logical operations
 def BSL : SInst<"vbsl", ".U..", "dPlQdQPl">;
@@ -868,7 +865,7 @@
 def CFMLT  : SOpInst<"vclt", "U..", "lUldQdQlQUl", OP_LT>;
 
 def CMEQ  : SInst<"vceqz", "U.",
-  "csilfUcUsUiUlPcPsPlQcQsQiQlQfQUcQUsQUiQUlQPcQPsdQdQPl">;
+  "csilfUcUsUiUlPcPlQcQsQiQlQfQUcQUsQUiQUlQPcdQdQPl">;
 def CMGE  : SInst<"vcgez", "U.", "csilfdQcQsQiQlQfQd">;
 def CMLE  : SInst<"vclez", "U.", "csilfdQcQsQiQlQfQd">;
 def CMGT  : SInst<"vcgtz", "U.", "csilfdQcQsQiQlQ

[PATCH] D93206: [AArch64][NEON] Remove undocumented vceqz{,q}_p16, vml{a,s}q_n_f64 intrinsics

[Joe Ellis via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5a2a8369e82c: [AArch64][NEON] Remove undocumented 
vceqz{,q}_p16, vml{a,s}q_n_f64 intrinsics (authored by joechrisellis).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93206/new/

https://reviews.llvm.org/D93206

Files:
  clang/include/clang/Basic/arm_neon.td
  clang/test/CodeGen/aarch64-neon-fma.c
  clang/test/CodeGen/aarch64-neon-misc.c


Index: clang/test/CodeGen/aarch64-neon-misc.c
===
--- clang/test/CodeGen/aarch64-neon-misc.c
+++ clang/test/CodeGen/aarch64-neon-misc.c
@@ -198,24 +198,6 @@
   return vceqzq_p8(a);
 }
 
-// CHECK-LABEL: @test_vceqz_p16(
-// CHECK:   [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
-// CHECK:   [[TMP1:%.*]] = icmp eq <4 x i16> %a, zeroinitializer
-// CHECK:   [[VCEQZ_I:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i16>
-// CHECK:   ret <4 x i16> [[VCEQZ_I]]
-uint16x4_t test_vceqz_p16(poly16x4_t a) {
-  return vceqz_p16(a);
-}
-
-// CHECK-LABEL: @test_vceqzq_p16(
-// CHECK:   [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
-// CHECK:   [[TMP1:%.*]] = icmp eq <8 x i16> %a, zeroinitializer
-// CHECK:   [[VCEQZ_I:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
-// CHECK:   ret <8 x i16> [[VCEQZ_I]]
-uint16x8_t test_vceqzq_p16(poly16x8_t a) {
-  return vceqzq_p16(a);
-}
-
 // CHECK-LABEL: @test_vceqzq_f64(
 // CHECK:   [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
 // CHECK:   [[TMP1:%.*]] = fcmp oeq <2 x double> %a, zeroinitializer
Index: clang/test/CodeGen/aarch64-neon-fma.c
===
--- clang/test/CodeGen/aarch64-neon-fma.c
+++ clang/test/CodeGen/aarch64-neon-fma.c
@@ -26,16 +26,6 @@
   return vmlaq_n_f32(a, b, c);
 }
 
-// CHECK-LABEL: define <2 x double> @test_vmlaq_n_f64(<2 x double> %a, <2 x 
double> %b, double %c) #1 {
-// CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, 
i32 0
-// CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], 
double %c, i32 1
-// CHECK:   [[MUL_I:%.*]] = fmul <2 x double> %b, [[VECINIT1_I]]
-// CHECK:   [[ADD_I:%.*]] = fadd <2 x double> %a, [[MUL_I]]
-// CHECK:   ret <2 x double> [[ADD_I]]
-float64x2_t test_vmlaq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {
-  return vmlaq_n_f64(a, b, c);
-}
-
 // CHECK-LABEL: define <4 x float> @test_vmlsq_n_f32(<4 x float> %a, <4 x 
float> %b, float %c) #1 {
 // CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %c, i32 0
 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], 
float %c, i32 1
@@ -58,16 +48,6 @@
   return vmls_n_f32(a, b, c);
 }
 
-// CHECK-LABEL: define <2 x double> @test_vmlsq_n_f64(<2 x double> %a, <2 x 
double> %b, double %c) #1 {
-// CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, 
i32 0
-// CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], 
double %c, i32 1
-// CHECK:   [[MUL_I:%.*]] = fmul <2 x double> %b, [[VECINIT1_I]]
-// CHECK:   [[SUB_I:%.*]] = fsub <2 x double> %a, [[MUL_I]]
-// CHECK:   ret <2 x double> [[SUB_I]]
-float64x2_t test_vmlsq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {
-  return vmlsq_n_f64(a, b, c);
-}
-
 // CHECK-LABEL: define <2 x float> @test_vmla_lane_f32_0(<2 x float> %a, <2 x 
float> %b, <2 x float> %v) #0 {
 // CHECK:[[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
 // CHECK:[[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
Index: clang/include/clang/Basic/arm_neon.td
===
--- clang/include/clang/Basic/arm_neon.td
+++ clang/include/clang/Basic/arm_neon.td
@@ -786,9 +786,6 @@
 def FMLA_N : SOpInst<"vfma_n", "...1", "dQd", OP_FMLA_N>;
 def FMLS_N : SOpInst<"vfms_n", "...1", "fdQfQd", OP_FMLS_N>;
 
-def MLA_N : SOpInst<"vmla_n", "...1", "Qd", OP_MLA_N>;
-def MLS_N : SOpInst<"vmls_n", "...1", "Qd", OP_MLS_N>;
-
 

 // Logical operations
 def BSL : SInst<"vbsl", ".U..", "dPlQdQPl">;
@@ -868,7 +865,7 @@
 def CFMLT  : SOpInst<"vclt", "U..", "lUldQdQlQUl", OP_LT>;
 
 def CMEQ  : SInst<"vceqz", "U.",
-  "csilfUcUsUiUlPcPsPlQcQsQiQlQfQUcQUsQUiQUlQPcQPsdQdQPl">;
+  "csilfUcUsUiUlPcPlQcQsQiQlQfQUcQUsQUiQUlQPcdQdQPl">;
 def CMGE  : SInst<"vcgez", "U.", "csilfdQcQsQiQlQfQd">;
 def CMLE  : SInst<"vclez", "U.", "csilfdQcQsQiQlQfQd">;
 def CMGT  : SInst<"vcgtz", "U.", "csilfdQcQsQiQlQfQd">;


Index: clang/test/CodeGen/aarch64-neon-misc.c
===
--- clang/test/CodeGen/aarch64-neon-misc.c
+++ clang/test/CodeGen/aarch64-neon-misc.c
@@ -198,24 +198,6 @@
   return vceqzq_p8(a);
 }
 
-// CHECK-LABEL: @test_vceqz_p16(
-// CHECK:   [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
-//

[PATCH] D92761: [clang][AArch64][SVE] Avoid going through memory for VLAT <-> VLST casts

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 312150.
joechrisellis added a comment.

Address @c-rhodes's comments.

- Add a comment stating that we intend to eliminate going through memory when 
the element types of the vectors are not the same (for example, with 
predicates).
- Doc comments for the new methods in `IRBuilder.h`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92761/new/

https://reviews.llvm.org/D92761

Files:
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
  llvm/include/llvm/IR/IRBuilder.h

Index: llvm/include/llvm/IR/IRBuilder.h
===
--- llvm/include/llvm/IR/IRBuilder.h
+++ llvm/include/llvm/IR/IRBuilder.h
@@ -923,6 +923,22 @@
 return CreateBinaryIntrinsic(Intrinsic::maximum, LHS, RHS, nullptr, Name);
   }
 
+  /// Create a call to the experimental.vector.extract intrinsic.
+  CallInst *CreateExtractVector(Type *DstType, Value *SrcVec, Value *Idx,
+const Twine &Name = "") {
+return CreateIntrinsic(Intrinsic::experimental_vector_extract,
+   {DstType, SrcVec->getType()}, {SrcVec, Idx}, nullptr,
+   Name);
+  }
+
+  /// Create a call to the experimental.vector.insert intrinsic.
+  CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec,
+   Value *Idx, const Twine &Name = "") {
+return CreateIntrinsic(Intrinsic::experimental_vector_insert,
+   {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
+   nullptr, Name);
+  }
+
 private:
   /// Create a call to a masked intrinsic with given Id.
   CallInst *CreateMaskedIntrinsic(Intrinsic::ID Id, ArrayRef Ops,
Index: clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
@@ -21,40 +21,28 @@
 
 // CHECK-128-LABEL: @write_global_i64(
 // CHECK-128-NEXT:  entry:
-// CHECK-128-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-128-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-128-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <2 x i64>*
-// CHECK-128-NEXT:[[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[TMP0]], align 16, [[TBAA10:!tbaa !.*]]
-// CHECK-128-NEXT:store <2 x i64> [[TMP1]], <2 x i64>* @global_i64, align 16, [[TBAA10]]
+// CHECK-128-NEXT:[[CASTFIXEDSVE:%.*]] = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64( [[V:%.*]], i64 0)
+// CHECK-128-NEXT:store <2 x i64> [[CASTFIXEDSVE]], <2 x i64>* @global_i64, align 16, [[TBAA6:!tbaa !.*]]
 // CHECK-128-NEXT:ret void
 //
 // CHECK-512-LABEL: @write_global_i64(
 // CHECK-512-NEXT:  entry:
-// CHECK-512-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-512-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-512-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <8 x i64>*
-// CHECK-512-NEXT:[[TMP1:%.*]] = load <8 x i64>, <8 x i64>* [[TMP0]], align 16, [[TBAA10:!tbaa !.*]]
-// CHECK-512-NEXT:store <8 x i64> [[TMP1]], <8 x i64>* @global_i64, align 16, [[TBAA10]]
+// CHECK-512-NEXT:[[CASTFIXEDSVE:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64( [[V:%.*]], i64 0)
+// CHECK-512-NEXT:store <8 x i64> [[CASTFIXEDSVE]], <8 x i64>* @global_i64, align 16, [[TBAA6:!tbaa !.*]]
 // CHECK-512-NEXT:ret void
 //
 void write_global_i64(svint64_t v) { global_i64 = v; }
 
 // CHECK-128-LABEL: @write_global_bf16(
 // CHECK-128-NEXT:  entry:
-// CHECK-128-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-128-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA11:!tbaa !.*]]
-// CHECK-128-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <8 x bfloat>*
-// CHECK-128-NEXT:[[TMP1:%.*]] = load <8 x bfloat>, <8 x bfloat>* [[TMP0]], align 16, [[TBAA10]]
-// CHECK-128-NEXT:store <8 x bfloat> [[TMP1]], <8 x bfloat>* @global_bf16, align 16, [[TBAA10]]
+// CHECK-128-NEXT:[[CASTFIXEDSVE:%.*]] = call <8 x bfloat> @llvm.experimental.vector.extract.v8bf16.nxv8bf16( [[V:%.*]], i64 0)
+// CHECK-128-NEXT:store <8 x bfloat> [[CASTFIXEDSVE]], <8 x bfloat>* @global_bf16, align 16, [[TBAA6]]
 // CHECK-128-NEXT:ret void
 //
 // CHECK-512-LABEL: @write_global_bf16(
 // CHECK-512-NEXT:  entry:
-// CHECK-512-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-512-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA11:!tbaa !.*]]
-// CHECK-512-NEXT:[[TMP0:%.*]] = bitcast

[PATCH] D92761: [clang][AArch64][SVE] Avoid going through memory for VLAT <-> VLST casts

[Joe Ellis via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdad07baf123e: [clang][AArch64][SVE] Avoid going through 
memory for VLAT <-> VLST casts (authored by joechrisellis).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92761/new/

https://reviews.llvm.org/D92761

Files:
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
  llvm/include/llvm/IR/IRBuilder.h

Index: llvm/include/llvm/IR/IRBuilder.h
===
--- llvm/include/llvm/IR/IRBuilder.h
+++ llvm/include/llvm/IR/IRBuilder.h
@@ -923,6 +923,22 @@
 return CreateBinaryIntrinsic(Intrinsic::maximum, LHS, RHS, nullptr, Name);
   }
 
+  /// Create a call to the experimental.vector.extract intrinsic.
+  CallInst *CreateExtractVector(Type *DstType, Value *SrcVec, Value *Idx,
+const Twine &Name = "") {
+return CreateIntrinsic(Intrinsic::experimental_vector_extract,
+   {DstType, SrcVec->getType()}, {SrcVec, Idx}, nullptr,
+   Name);
+  }
+
+  /// Create a call to the experimental.vector.insert intrinsic.
+  CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec,
+   Value *Idx, const Twine &Name = "") {
+return CreateIntrinsic(Intrinsic::experimental_vector_insert,
+   {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
+   nullptr, Name);
+  }
+
 private:
   /// Create a call to a masked intrinsic with given Id.
   CallInst *CreateMaskedIntrinsic(Intrinsic::ID Id, ArrayRef Ops,
Index: clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
@@ -21,40 +21,28 @@
 
 // CHECK-128-LABEL: @write_global_i64(
 // CHECK-128-NEXT:  entry:
-// CHECK-128-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-128-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-128-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <2 x i64>*
-// CHECK-128-NEXT:[[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[TMP0]], align 16, [[TBAA10:!tbaa !.*]]
-// CHECK-128-NEXT:store <2 x i64> [[TMP1]], <2 x i64>* @global_i64, align 16, [[TBAA10]]
+// CHECK-128-NEXT:[[CASTFIXEDSVE:%.*]] = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64( [[V:%.*]], i64 0)
+// CHECK-128-NEXT:store <2 x i64> [[CASTFIXEDSVE]], <2 x i64>* @global_i64, align 16, [[TBAA6:!tbaa !.*]]
 // CHECK-128-NEXT:ret void
 //
 // CHECK-512-LABEL: @write_global_i64(
 // CHECK-512-NEXT:  entry:
-// CHECK-512-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-512-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-512-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <8 x i64>*
-// CHECK-512-NEXT:[[TMP1:%.*]] = load <8 x i64>, <8 x i64>* [[TMP0]], align 16, [[TBAA10:!tbaa !.*]]
-// CHECK-512-NEXT:store <8 x i64> [[TMP1]], <8 x i64>* @global_i64, align 16, [[TBAA10]]
+// CHECK-512-NEXT:[[CASTFIXEDSVE:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64( [[V:%.*]], i64 0)
+// CHECK-512-NEXT:store <8 x i64> [[CASTFIXEDSVE]], <8 x i64>* @global_i64, align 16, [[TBAA6:!tbaa !.*]]
 // CHECK-512-NEXT:ret void
 //
 void write_global_i64(svint64_t v) { global_i64 = v; }
 
 // CHECK-128-LABEL: @write_global_bf16(
 // CHECK-128-NEXT:  entry:
-// CHECK-128-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-128-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA11:!tbaa !.*]]
-// CHECK-128-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <8 x bfloat>*
-// CHECK-128-NEXT:[[TMP1:%.*]] = load <8 x bfloat>, <8 x bfloat>* [[TMP0]], align 16, [[TBAA10]]
-// CHECK-128-NEXT:store <8 x bfloat> [[TMP1]], <8 x bfloat>* @global_bf16, align 16, [[TBAA10]]
+// CHECK-128-NEXT:[[CASTFIXEDSVE:%.*]] = call <8 x bfloat> @llvm.experimental.vector.extract.v8bf16.nxv8bf16( [[V:%.*]], i64 0)
+// CHECK-128-NEXT:store <8 x bfloat> [[CASTFIXEDSVE]], <8 x bfloat>* @global_bf16, align 16, [[TBAA6]]
 // CHECK-128-NEXT:ret void
 //
 // CHECK-512-LABEL: @write_global_bf16(
 // CHECK-512-NEXT:  entry:
-// CHECK-512-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-512-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA11:!tbaa !.*]]
-// CHECK-512-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <32 x bfloat>*
-// CHECK-512-NEXT:[[TMP1:%.*

[PATCH] D91067: [AArch64][SVE] Support implicit lax vector conversions for SVE types

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis created this revision.
joechrisellis added reviewers: peterwaller-arm, fpetrogalli, DavidTruby.
Herald added subscribers: cfe-commits, psnobl, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: efriedma.
Herald added a project: clang.
joechrisellis requested review of this revision.

Lax vector conversions was behaving incorrectly for implicit casts
between scalable and fixed-length vector types. For example, this:

  #include 
  
  #define N __ARM_FEATURE_SVE_BITS
  #define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
  
  typedef svfloat32_t fixed_float32_t FIXED_ATTR;
  typedef svfloat64_t fixed_float64_t FIXED_ATTR;
  
  void allowed_depending() {
fixed_float32_t fs32;
svfloat64_t s64;
  
fs32 = s64;
  }

... would fail because the vectors have differing lane sizes. This patch
implements the correct behaviour for
-flax-vector-conversions={none,all,integer}. Specifically:

- -flax-vector-conversions=none prevents all lax vector conversions between 
scalable and fixed-sized vectors.
- -flax-vector-conversions=integer allows lax vector conversions between 
scalable and fixed-size vectors whose element types are integers.
- -flax-vector-conversions=all allows all lax vector conversions between 
scalable and fixed-size vectors (including those with floating point element 
types).

The implicit conversions are implemented as bitcasts.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91067

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/test/Sema/aarch64-sve-lax-vector-conversions.cpp

Index: clang/test/Sema/aarch64-sve-lax-vector-conversions.cpp
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-lax-vector-conversions.cpp
@@ -0,0 +1,44 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-none %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=integer -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-integer %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=all -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-all %s
+
+// lax-vector-all-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svfloat64_t fixed_float64_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+
+void allowed_always() {
+  fixed_float32_t ff32;
+  svfloat64_t sf64;
+
+  // This explicit cast is always allowed, irrespective of the value of -flax-vector-conversions.
+  ff32 = (fixed_float32_t)sf64;
+}
+
+void allowed_with_integer_lax_conversions() {
+  fixed_int32_t fi32;
+  svint64_t si64;
+
+  // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
+  // -flax-vector-conversions={integer,all}.
+  fi32 = si64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+}
+
+void allowed_with_all_lax_conversions() {
+  fixed_float32_t ff32;
+  svfloat64_t sf64;
+
+  // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
+  // -flax-vector-conversions=all.
+  ff32 = sf64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+}
Index: clang/lib/Sema/SemaOverload.cpp
===
--- clang/lib/Sema/SemaOverload.cpp
+++ clang/lib/Sema/SemaOverload.cpp
@@ -1644,11 +1644,12 @@
 }
   }
 
-  if ((ToType->isSizelessBuiltinType() || FromType->isSizelessBuiltinType()) &&
-  S.Context.areCompatibleSveTypes(FromType, ToType)) {
-ICK = ICK_SVE_Vector_Conversion;
-return true;
-  }
+  if (ToType->isSizelessBuiltinType() || FromType->isSizelessBuiltinType())
+if (S.Context.areCompatibleSveTypes(FromType, ToType) ||
+S.Context.areLaxCompatibleSveTypes(FromType, ToType)) {
+  ICK = ICK_SVE_Vector_Conversion;
+  return true;
+}
 
   // We can perform the conversion between vector types in the following cases:
   // 1)vector types are equivalent AltiVec and GCC vector types
Index: clang/lib/Sema/SemaCast.cpp
===
--- clang/lib/Sema/SemaCast.cpp
+++ clang/lib/Sema/SemaCast.cpp
@@ -2219,6 +2219,12 @@
   bool destIsVec

[PATCH] D91067: [AArch64][SVE] Support implicit lax vector conversions for SVE types

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 303838.
joechrisellis marked an inline comment as done.
joechrisellis added a comment.

Address @peterwaller-arm's comment regarding unused types.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91067/new/

https://reviews.llvm.org/D91067

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/test/Sema/aarch64-sve-lax-vector-conversions.cpp

Index: clang/test/Sema/aarch64-sve-lax-vector-conversions.cpp
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-lax-vector-conversions.cpp
@@ -0,0 +1,42 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-none %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=integer -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-integer %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=all -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-all %s
+
+// lax-vector-all-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+
+void allowed_always() {
+  fixed_float32_t ff32;
+  svfloat64_t sf64;
+
+  // This explicit cast is always allowed, irrespective of the value of -flax-vector-conversions.
+  ff32 = (fixed_float32_t)sf64;
+}
+
+void allowed_with_integer_lax_conversions() {
+  fixed_int32_t fi32;
+  svint64_t si64;
+
+  // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
+  // -flax-vector-conversions={integer,all}.
+  fi32 = si64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+}
+
+void allowed_with_all_lax_conversions() {
+  fixed_float32_t ff32;
+  svfloat64_t sf64;
+
+  // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
+  // -flax-vector-conversions=all.
+  ff32 = sf64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+}
Index: clang/lib/Sema/SemaOverload.cpp
===
--- clang/lib/Sema/SemaOverload.cpp
+++ clang/lib/Sema/SemaOverload.cpp
@@ -1644,11 +1644,12 @@
 }
   }
 
-  if ((ToType->isSizelessBuiltinType() || FromType->isSizelessBuiltinType()) &&
-  S.Context.areCompatibleSveTypes(FromType, ToType)) {
-ICK = ICK_SVE_Vector_Conversion;
-return true;
-  }
+  if (ToType->isSizelessBuiltinType() || FromType->isSizelessBuiltinType())
+if (S.Context.areCompatibleSveTypes(FromType, ToType) ||
+S.Context.areLaxCompatibleSveTypes(FromType, ToType)) {
+  ICK = ICK_SVE_Vector_Conversion;
+  return true;
+}
 
   // We can perform the conversion between vector types in the following cases:
   // 1)vector types are equivalent AltiVec and GCC vector types
Index: clang/lib/Sema/SemaCast.cpp
===
--- clang/lib/Sema/SemaCast.cpp
+++ clang/lib/Sema/SemaCast.cpp
@@ -2219,6 +2219,12 @@
   bool destIsVector = DestType->isVectorType();
   bool srcIsVector = SrcType->isVectorType();
   if (srcIsVector || destIsVector) {
+// Scalable vectors can be cast to and from liberally.
+if (SrcType->isSizelessBuiltinType() || DestType->isSizelessBuiltinType()) {
+  Kind = CK_BitCast;
+  return TC_Success;
+}
+
 // The non-vector type, if any, must have integral type.  This is
 // the same rule that C vector casts use; note, however, that enum
 // types are not integral in C++.
Index: clang/lib/AST/ASTContext.cpp
===
--- clang/lib/AST/ASTContext.cpp
+++ clang/lib/AST/ASTContext.cpp
@@ -8553,6 +8553,39 @@
  IsValidCast(SecondType, FirstType);
 }
 
+bool ASTContext::areLaxCompatibleSveTypes(QualType FirstType,
+  QualType SecondType) {
+  assert(((FirstType->isSizelessBuiltinType() && SecondType->isVectorType()) ||
+  (FirstType->isVectorType() && SecondType->isSizelessBuiltinType())) &&
+ "Expected SVE builtin type and vector type!");
+
+  auto IsLaxCompatible = [this](QualType FirstType, QualType SecondType) {
+if (const auto *BT = FirstType->getAs()) {
+  if (const auto *VT = SecondTyp

[PATCH] D91067: [AArch64][SVE] Support implicit lax vector conversions for SVE types

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis added inline comments.



Comment at: clang/test/Sema/aarch64-sve-lax-vector-conversions.cpp:15
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+

peterwaller-arm wrote:
> I can't see any uses of fixed_float64_t and fixed_int64_t?
Good spot! Removed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91067/new/

https://reviews.llvm.org/D91067

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D91067: [AArch64][SVE] Support implicit lax vector conversions for SVE types

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis marked an inline comment as done.
joechrisellis added inline comments.



Comment at: clang/lib/AST/ASTContext.cpp:8563-8566
+if (const auto *BT = FirstType->getAs()) {
+  if (const auto *VT = SecondType->getAs()) {
+if (VT->getVectorKind() == VectorType::SveFixedLengthDataVector) {
+  const LangOptions::LaxVectorConversionKind LVCKind =

fpetrogalli wrote:
> May I ask to avoid this triple if statement? Given that `BT` is not used 
> after being defined, I think the following form would be easier to understand:
> 
> ```
> if (!FirstType->getAs())
>   return false;
> 
> const auto *VT = SecondType->getAs();
> 
> if (VT && VT->getVectorKind() == VectorType::SveFixedLengthDataVector) {
>/// ...
> return ...
> }
> 
> return false;
> ```
> 
> May I ask you to give meaningful names to the variables? BT and VT are quite 
> cryptic to me.
> 
> Moreover.. are BT and VT really needed? You are asserting 
> `FirstType->isSizelessBuiltinType() && SecondType->isVectorType()` ... the 
> `getAs` calls should not fail, no? given that the lambda is local to this 
> method, I wouldn't bother making it work for the generic case.
Simplified the code as per your suggestion, but the lambda here here serves a 
purpose: it makes sure that `areLaxCompatibleSveTypes` has the same behaviour 
irrespective of the ordering of the parameters. So we do actually need the if 
statements inside the lambda.



Comment at: clang/lib/Sema/SemaCast.cpp:
   if (srcIsVector || destIsVector) {
+// Scalable vectors can be cast to and from liberally.
+if (SrcType->isSizelessBuiltinType() || DestType->isSizelessBuiltinType()) 
{

fpetrogalli wrote:
> This code path seems untested.
Thinking about it, this could do with being broken out into its own patch. Will 
do this.



Comment at: clang/lib/Sema/SemaOverload.cpp:1650-1652
+  ICK = ICK_SVE_Vector_Conversion;
+  return true;
+}

fpetrogalli wrote:
> tabs!
Not sure where these came from, since I ran `clang-format` over the patch. 
Think they should be gone now...



Comment at: clang/test/Sema/aarch64-sve-lax-vector-conversions.cpp:19
+
+  // This explicit cast is always allowed, irrespective of the value of 
-flax-vector-conversions.
+  ff32 = (fixed_float32_t)sf64;

fpetrogalli wrote:
> Why this one in particular? To me the comment would make more sense if saying 
> 
> ```
> // An explicit cast is always allowed, irrespective of the value of 
> -flax-vector-conversions.
> ```
Will break this out into another patch as mentioned above.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91067/new/

https://reviews.llvm.org/D91067

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D91067: [AArch64][SVE] Support implicit lax vector conversions for SVE types

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 304469.
joechrisellis marked 3 inline comments as done.
joechrisellis added a comment.

Address @fpetrogalli's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91067/new/

https://reviews.llvm.org/D91067

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/test/Sema/aarch64-sve-lax-vector-conversions.cpp

Index: clang/test/Sema/aarch64-sve-lax-vector-conversions.cpp
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-lax-vector-conversions.cpp
@@ -0,0 +1,34 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-none %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=integer -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-integer %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=all -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-all %s
+
+// lax-vector-all-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+
+void allowed_with_integer_lax_conversions() {
+  fixed_int32_t fi32;
+  svint64_t si64;
+
+  // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
+  // -flax-vector-conversions={integer,all}.
+  fi32 = si64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+}
+
+void allowed_with_all_lax_conversions() {
+  fixed_float32_t ff32;
+  svfloat64_t sf64;
+
+  // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
+  // -flax-vector-conversions=all.
+  ff32 = sf64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+}
Index: clang/lib/Sema/SemaOverload.cpp
===
--- clang/lib/Sema/SemaOverload.cpp
+++ clang/lib/Sema/SemaOverload.cpp
@@ -1644,11 +1644,12 @@
 }
   }
 
-  if ((ToType->isSizelessBuiltinType() || FromType->isSizelessBuiltinType()) &&
-  S.Context.areCompatibleSveTypes(FromType, ToType)) {
-ICK = ICK_SVE_Vector_Conversion;
-return true;
-  }
+  if (ToType->isSizelessBuiltinType() || FromType->isSizelessBuiltinType())
+if (S.Context.areCompatibleSveTypes(FromType, ToType) ||
+S.Context.areLaxCompatibleSveTypes(FromType, ToType)) {
+  ICK = ICK_SVE_Vector_Conversion;
+  return true;
+}
 
   // We can perform the conversion between vector types in the following cases:
   // 1)vector types are equivalent AltiVec and GCC vector types
Index: clang/lib/AST/ASTContext.cpp
===
--- clang/lib/AST/ASTContext.cpp
+++ clang/lib/AST/ASTContext.cpp
@@ -8553,6 +8553,41 @@
  IsValidCast(SecondType, FirstType);
 }
 
+bool ASTContext::areLaxCompatibleSveTypes(QualType FirstType,
+  QualType SecondType) {
+  assert(((FirstType->isSizelessBuiltinType() && SecondType->isVectorType()) ||
+  (FirstType->isVectorType() && SecondType->isSizelessBuiltinType())) &&
+ "Expected SVE builtin type and vector type!");
+
+  auto IsLaxCompatible = [this](QualType FirstType, QualType SecondType) {
+if (!FirstType->getAs())
+  return false;
+
+const auto *VecTy = SecondType->getAs();
+if (VecTy &&
+VecTy->getVectorKind() == VectorType::SveFixedLengthDataVector) {
+  const LangOptions::LaxVectorConversionKind LVCKind =
+  getLangOpts().getLaxVectorConversions();
+
+  // If -flax-vector-conversions=all is specified, the types are
+  // certainly compatible.
+  if (LVCKind == LangOptions::LaxVectorConversionKind::All)
+return true;
+
+  // If -flax-vector-conversions=integer is specified, the types are
+  // compatible if the elements are integer types.
+  if (LVCKind == LangOptions::LaxVectorConversionKind::Integer)
+return VecTy->getElementType().getCanonicalType()->isIntegerType() &&
+   FirstType->getSveEltType(*this)->isIntegerType();
+}
+
+return false;
+  };
+
+  return IsLaxCompatible(FirstType, SecondType) ||
+ IsLaxCompatible(SecondType, FirstType);
+}
+
 bool ASTContext::hasDirectOwnershipQualifier(QualType Ty) const {
   while 

[PATCH] D91262: [AArch64][SVE] Allow C-style casts between fixed-size and scalable vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis created this revision.
joechrisellis added reviewers: fpetrogalli, peterwaller-arm, DavidTruby.
Herald added subscribers: cfe-commits, psnobl, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: clang.
joechrisellis requested review of this revision.

This patch allows C-style casting between fixed-size and scalable
vectors. This kind of cast was previously blocked by the compiler, but
it should be allowed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91262

Files:
  clang/lib/Sema/SemaCast.cpp
  clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.cpp
  clang/test/Sema/aarch64-sve-explicit-casts.cpp

Index: clang/test/Sema/aarch64-sve-explicit-casts.cpp
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-explicit-casts.cpp
@@ -0,0 +1,36 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+#include 
+
+// SVE types cannot be C-style casted to one another.
+// "To avoid any ambiguity [between the two operations], the ACLE does not allow C-style casting from one
+// vector type to another." ~ACLE Section 3.4 (Vector Types)
+// The functions below check that C-style casting between scalable types correctly raises an error.
+
+void svint32_to_svint64() {
+  svint32_t si32;
+  svint64_t si64;
+
+  si64 = (svint64_t) si32; // expected-error-re {{C-style cast from 'svint32_t' {{.*}} is not allowed}}
+}
+
+void svint64_to_svint32() {
+  svint32_t si32;
+  svint64_t si64;
+
+  si32 = (svint32_t) si64; // expected-error-re {{C-style cast from 'svint64_t' {{.*}} is not allowed}}
+}
+
+void svfloat32_to_svfloat64() {
+  svfloat32_t sf32;
+  svfloat64_t sf64;
+
+  sf64 = (svfloat64_t) sf32; // expected-error-re {{C-style cast from 'svfloat32_t' {{.*}} is not allowed}}
+}
+
+void svfloat64_to_svfloat32() {
+  svfloat32_t sf32;
+  svfloat64_t sf64;
+
+  sf32 = (svfloat32_t) sf64; // expected-error-re {{C-style cast from 'svfloat64_t' {{.*}} is not allowed}}
+}
Index: clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.cpp
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.cpp
@@ -0,0 +1,72 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svfloat64_t fixed_float64_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+
+// Fixed-size SVE types can be cast to scalable SVE types (regardless of lane size).
+// NOTE: the list below is not exhaustive for all SVE types.
+
+void svint32_to_fixed_int32_t() {
+  svint32_t si32;
+  fixed_int32_t fi32;
+
+  fi32 = (fixed_int32_t)si32;
+}
+
+void fixed_int32_t_to_svint32() {
+  svint32_t si32;
+  fixed_int32_t fi32;
+
+  si32 = (svint32_t)fi32;
+}
+
+void svint64_to_fixed_int32_t() {
+  svint64_t si64;
+  fixed_int32_t fi32;
+
+  fi32 = (fixed_int32_t)si64;
+}
+
+void fixed_int32_t_to_svint64() {
+  svint64_t si64;
+  fixed_int32_t fi32;
+
+  si64 = (svint64_t)fi32;
+}
+
+void svint32_to_fixed_int64_t() {
+  svint32_t si32;
+  fixed_int64_t fi32;
+
+  fi32 = (fixed_int64_t)si32;
+}
+
+void fixed_int64_t_to_svint32() {
+  svint32_t si32;
+  fixed_int64_t fi32;
+
+  si32 = (svint32_t)fi32;
+}
+
+void svint64_to_fixed_int64_t() {
+  svint64_t si64;
+  fixed_int64_t fi32;
+
+  fi32 = (fixed_int64_t)si64;
+}
+
+void fixed_int64_t_to_svint64() {
+  svint64_t si64;
+  fixed_int64_t fi32;
+
+  si64 = (svint64_t)fi32;
+}
Index: clang/lib/Sema/SemaCast.cpp
===
--- clang/lib/Sema/SemaCast.cpp
+++ clang/lib/Sema/SemaCast.cpp
@@ -2219,6 +2219,13 @@
   bool destIsVector = DestType->isVectorType();
   bool srcIsVector = SrcType->isVectorType();
   if (srcIsVector || destIsVector) {
+// Allow bitcasting if either the source or destination is a scalable
+// vector.
+if (SrcType->isSizelessBuiltinType() || DestType->isSizelessBuiltinType()) {
+  Kind = CK_BitCast;
+  return TC_Success;
+}
+
 // The non-vector type, if any, must have integral type.  This is
 // the same rule that C vector casts use; note, however, that enum
 // types are not integral in C++.
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D91262: [AArch64][SVE] Allow C-style casts between fixed-size and scalable vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 304513.
joechrisellis added a comment.

Add tests for C-style casts to/from scalable/fixed float vector types.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91262/new/

https://reviews.llvm.org/D91262

Files:
  clang/lib/Sema/SemaCast.cpp
  clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.cpp
  clang/test/Sema/aarch64-sve-explicit-casts.cpp

Index: clang/test/Sema/aarch64-sve-explicit-casts.cpp
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-explicit-casts.cpp
@@ -0,0 +1,36 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+#include 
+
+// SVE types cannot be C-style casted to one another.
+// "To avoid any ambiguity [between the two operations], the ACLE does not allow C-style casting from one
+// vector type to another." ~ACLE Section 3.4 (Vector Types)
+// The functions below check that C-style casting between scalable types correctly raises an error.
+
+void svint32_to_svint64() {
+  svint32_t si32;
+  svint64_t si64;
+
+  si64 = (svint64_t) si32; // expected-error-re {{C-style cast from 'svint32_t' {{.*}} is not allowed}}
+}
+
+void svint64_to_svint32() {
+  svint32_t si32;
+  svint64_t si64;
+
+  si32 = (svint32_t) si64; // expected-error-re {{C-style cast from 'svint64_t' {{.*}} is not allowed}}
+}
+
+void svfloat32_to_svfloat64() {
+  svfloat32_t sf32;
+  svfloat64_t sf64;
+
+  sf64 = (svfloat64_t) sf32; // expected-error-re {{C-style cast from 'svfloat32_t' {{.*}} is not allowed}}
+}
+
+void svfloat64_to_svfloat32() {
+  svfloat32_t sf32;
+  svfloat64_t sf64;
+
+  sf32 = (svfloat32_t) sf64; // expected-error-re {{C-style cast from 'svfloat64_t' {{.*}} is not allowed}}
+}
Index: clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.cpp
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.cpp
@@ -0,0 +1,128 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svfloat64_t fixed_float64_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+
+// Fixed-size SVE types can be cast to scalable SVE types (regardless of lane size).
+// NOTE: the list below is not exhaustive for all SVE types.
+
+void svint32_to_fixed_int32_t() {
+  svint32_t si32;
+  fixed_int32_t fi32;
+
+  fi32 = (fixed_int32_t)si32;
+}
+
+void fixed_int32_t_to_svint32() {
+  svint32_t si32;
+  fixed_int32_t fi32;
+
+  si32 = (svint32_t)fi32;
+}
+
+void svint64_to_fixed_int32_t() {
+  svint64_t si64;
+  fixed_int32_t fi32;
+
+  fi32 = (fixed_int32_t)si64;
+}
+
+void fixed_int32_t_to_svint64() {
+  svint64_t si64;
+  fixed_int32_t fi32;
+
+  si64 = (svint64_t)fi32;
+}
+
+void svint32_to_fixed_int64_t() {
+  svint32_t si32;
+  fixed_int64_t fi32;
+
+  fi32 = (fixed_int64_t)si32;
+}
+
+void fixed_int64_t_to_svint32() {
+  svint32_t si32;
+  fixed_int64_t fi32;
+
+  si32 = (svint32_t)fi32;
+}
+
+void svint64_to_fixed_int64_t() {
+  svint64_t si64;
+  fixed_int64_t fi32;
+
+  fi32 = (fixed_int64_t)si64;
+}
+
+void fixed_int64_t_to_svint64() {
+  svint64_t si64;
+  fixed_int64_t fi32;
+
+  si64 = (svint64_t)fi32;
+}
+
+void svfloat32_to_fixed_float32_t() {
+  svfloat32_t sf32;
+  fixed_float32_t ff32;
+
+  ff32 = (fixed_float32_t)sf32;
+}
+
+void fixed_float32_t_to_svfloat32() {
+  svfloat32_t sf32;
+  fixed_float32_t ff32;
+
+  sf32 = (svfloat32_t)ff32;
+}
+
+void svfloat64_to_fixed_float32_t() {
+  svfloat64_t sf64;
+  fixed_float32_t ff32;
+
+  ff32 = (fixed_float32_t)sf64;
+}
+
+void fixed_float32_t_to_svfloat64() {
+  svfloat64_t sf64;
+  fixed_float32_t ff32;
+
+  sf64 = (svfloat64_t)ff32;
+}
+
+void svfloat32_to_fixed_float64_t() {
+  svfloat32_t sf32;
+  fixed_float64_t ff32;
+
+  ff32 = (fixed_float64_t)sf32;
+}
+
+void fixed_float64_t_to_svfloat32() {
+  svfloat32_t sf32;
+  fixed_float64_t ff32;
+
+  sf32 = (svfloat32_t)ff32;
+}
+
+void svfloat64_to_fixed_float64_t() {
+  svfloat64_t sf64;
+  fixed_float64_t ff32;
+
+  ff32 = (fixed_float64_t)sf64;
+}
+
+void fixed_float64_t_to_svfloat64() {
+  svfloat64_t sf64;
+  fixed_float64_t ff32;
+
+  sf64 = (svfloat64_t)ff32;
+}
Index: clang/lib/Sema/SemaCast.cpp
===
--- clang/lib/Sema/SemaCast.cpp
+++ clang/lib/Sema/SemaCast.cpp
@@ -2219,6 +2219,13 @@
   bool destIsVector = DestType->isVectorType();
   bool srcIsVector = SrcType->isVectorTyp

[PATCH] D91262: [AArch64][SVE] Allow C-style casts between fixed-size and scalable vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 304553.
joechrisellis marked 4 inline comments as done.
joechrisellis added a comment.

Address @fpetrogalli's comments.

- Add version of ACLE spec.
- Use ACLE nomenclature.
- Introduce preprocessor macro to reduce code size of 
aarch64-sve-explicit-casts.cpp.
- Test more values for `-msve-vector-bits` in aarch64-sve-explicit-casts.cpp.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91262/new/

https://reviews.llvm.org/D91262

Files:
  clang/lib/Sema/SemaCast.cpp
  clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.cpp
  clang/test/Sema/aarch64-sve-explicit-casts.cpp

Index: clang/test/Sema/aarch64-sve-explicit-casts.cpp
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-explicit-casts.cpp
@@ -0,0 +1,39 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+#include 
+
+// SVE VLAT types cannot be C-style casted to one another.
+//
+//   "To avoid any ambiguity [between the two operations], the ACLE does not allow C-style casting from one
+//   vector type to another."
+//   Section 3.4 (Vector Types), ACLE 0.0bet6
+
+// The functions below check that C-style casting between scalable types correctly raises an error.
+
+void svint32_to_svint64() {
+  svint32_t si32;
+  svint64_t si64;
+
+  si64 = (svint64_t) si32; // expected-error-re {{C-style cast from 'svint32_t' {{.*}} is not allowed}}
+}
+
+void svint64_to_svint32() {
+  svint32_t si32;
+  svint64_t si64;
+
+  si32 = (svint32_t) si64; // expected-error-re {{C-style cast from 'svint64_t' {{.*}} is not allowed}}
+}
+
+void svfloat32_to_svfloat64() {
+  svfloat32_t sf32;
+  svfloat64_t sf64;
+
+  sf64 = (svfloat64_t) sf32; // expected-error-re {{C-style cast from 'svfloat32_t' {{.*}} is not allowed}}
+}
+
+void svfloat64_to_svfloat32() {
+  svfloat32_t sf32;
+  svfloat64_t sf64;
+
+  sf32 = (svfloat32_t) sf64; // expected-error-re {{C-style cast from 'svfloat64_t' {{.*}} is not allowed}}
+}
Index: clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.cpp
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.cpp
@@ -0,0 +1,68 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=128 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=256 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=1024 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=2048 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svfloat64_t fixed_float64_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+
+// SVE VLSTs can be cast to SVE VLATs, regardless of lane size.
+// NOTE: the list below is NOT exhaustive for all SVE types.
+
+#define TESTCASE(from, to) \
+void from##_to_##to() {\
+from a;\
+to b;  \
+   \
+b = (to) a;\
+}
+
+TESTCASE(fixed_float32_t, svfloat32_t)
+TESTCASE(fixed_float32_t, svfloat64_t)
+TESTCASE(fixed_float32_t, svint32_t)
+TESTCASE(fixed_float32_t, svint64_t)
+
+TESTCASE(fixed_float64_t, svfloat32_t)
+TESTCASE(fixed_float64_t, svfloat64_t)
+TESTCASE(fixed_float64_t, svint32_t)
+TESTCASE(fixed_float64_t, svint64_t)
+
+TESTCASE(fixed_int32_t, svfloat32_t)
+TESTCASE(fixed_int32_t, svfloat64_t)
+TESTCASE(fixed_int32_t, svint32_t)
+TESTCASE(fixed_int32_t, svint64_t)
+
+TESTCASE(fixed_int64_t, svfloat32_t)
+TESTCASE(fixed_int64_t, svfloat64_t)
+TESTCASE(fixed_int64_t, svint32_t)
+TESTCASE(fixed_int64_t, svint64_t)
+
+TESTCASE(svfloat32_t, fixed_float32_t)
+TESTCASE(svfloat32_t, fixed_float64_t)
+TESTCASE(svfloat32_t, fixed_int32_t)
+TESTCASE(svfloat32_t, fixed_int64_t)
+
+TESTCASE(svfloat64_t, fixed_float32_t)
+TESTCASE(svfloat64_t, fixed_float64_t)
+TESTCASE(svfloat64_t, fixed_int32_t)
+TESTCASE(svfloat64_t, fixed_int64_t)
+
+TESTCASE(sv

[PATCH] D91262: [AArch64][SVE] Allow C-style casts between fixed-size and scalable vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis added inline comments.



Comment at: clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.cpp:16
+// Fixed-size SVE types can be cast to scalable SVE types (regardless of lane 
size).
+// NOTE: the list below is not exhaustive for all SVE types.
+

fpetrogalli wrote:
> Maybe write a CPP macro to reduce the amount of typing in this test? The 
> functions below they all look the same... 
Excellent idea, done!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91262/new/

https://reviews.llvm.org/D91262

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D91262: [AArch64][SVE] Allow C-style casts between fixed-size and scalable vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 304796.
joechrisellis marked 2 inline comments as done.
joechrisellis added a comment.

Address @c-rhodes's comments.

- Only allow casting between VLATs and VLSTs.
- Add C test.
- Move C++ test to the correct directory.
- Remove superfluous test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91262/new/

https://reviews.llvm.org/D91262

Files:
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
  clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp

Index: clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp
===
--- /dev/null
+++ clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp
@@ -0,0 +1,68 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=128 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=256 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=1024 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=2048 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svfloat64_t fixed_float64_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+
+// SVE VLSTs can be cast to SVE VLATs, regardless of lane size.
+// NOTE: the list below is NOT exhaustive for all SVE types.
+
+#define TESTCASE(from, to) \
+void from##_to_##to() {\
+from a;\
+to b;  \
+   \
+b = (to) a;\
+}
+
+TESTCASE(fixed_float32_t, svfloat32_t)
+TESTCASE(fixed_float32_t, svfloat64_t)
+TESTCASE(fixed_float32_t, svint32_t)
+TESTCASE(fixed_float32_t, svint64_t)
+
+TESTCASE(fixed_float64_t, svfloat32_t)
+TESTCASE(fixed_float64_t, svfloat64_t)
+TESTCASE(fixed_float64_t, svint32_t)
+TESTCASE(fixed_float64_t, svint64_t)
+
+TESTCASE(fixed_int32_t, svfloat32_t)
+TESTCASE(fixed_int32_t, svfloat64_t)
+TESTCASE(fixed_int32_t, svint32_t)
+TESTCASE(fixed_int32_t, svint64_t)
+
+TESTCASE(fixed_int64_t, svfloat32_t)
+TESTCASE(fixed_int64_t, svfloat64_t)
+TESTCASE(fixed_int64_t, svint32_t)
+TESTCASE(fixed_int64_t, svint64_t)
+
+TESTCASE(svfloat32_t, fixed_float32_t)
+TESTCASE(svfloat32_t, fixed_float64_t)
+TESTCASE(svfloat32_t, fixed_int32_t)
+TESTCASE(svfloat32_t, fixed_int64_t)
+
+TESTCASE(svfloat64_t, fixed_float32_t)
+TESTCASE(svfloat64_t, fixed_float64_t)
+TESTCASE(svfloat64_t, fixed_int32_t)
+TESTCASE(svfloat64_t, fixed_int64_t)
+
+TESTCASE(svint32_t, fixed_float32_t)
+TESTCASE(svint32_t, fixed_float64_t)
+TESTCASE(svint32_t, fixed_int32_t)
+TESTCASE(svint32_t, fixed_int64_t)
+
+TESTCASE(svint64_t, fixed_float32_t)
+TESTCASE(svint64_t, fixed_float64_t)
+TESTCASE(svint64_t, fixed_int32_t)
+TESTCASE(svint64_t, fixed_int64_t)
Index: clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
@@ -0,0 +1,68 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=128 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=256 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=1024 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=2048 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+// expected-no

[PATCH] D91262: [AArch64][SVE] Allow C-style casts between fixed-size and scalable vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis added inline comments.



Comment at: clang/lib/Sema/SemaCast.cpp:-2227
+// Allow bitcasting if either the source or destination is a scalable
+// vector.
+if (SrcType->isSizelessBuiltinType() || DestType->isSizelessBuiltinType()) 
{
+  Kind = CK_BitCast;
+  return TC_Success;
+}

c-rhodes wrote:
> This is a bit ambiguous, it'll allow bitcasting between things like a fixed 
> predicate and any sizeless type which I don't think makes sense. I think 
> it'll also allow bitcasting between any scalable and GNU vectors regardless 
> of vector length, e.g.:
> 
> ```
> typedef int32_t int32x4_t __attribute__((vector_size(16)));
> 
> void foo() {
> svint32_t s32;
> int32x4_t g32;
> g32 = (int32x4_t)s32;
> s32 = (svint32_t)g32;
> }
> ```
> 
> the above should only work when `-msve-vector-bits=128` but will currently be 
> allowed for any N.
Ah, you're dead right. I think the next diff should fix this, but if there are 
any more inconsistencies/ambiguities I'll fix them too. :) 



Comment at: clang/test/Sema/aarch64-sve-explicit-casts.cpp:1-36
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-msve-vector-bits=512 -flax-vector-conversions=none 
-fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+#include 
+
+// SVE types cannot be C-style casted to one another.
+// "To avoid any ambiguity [between the two operations], the ACLE does not 
allow C-style casting from one
+// vector type to another." ~ACLE Section 3.4 (Vector Types)

c-rhodes wrote:
> `clang/test/SemaCXX/sizeless-1.cpp` already contains a test checking C-style 
> casts between distinct sizeless types aren't supported, I'm not sure if 
> adding this is necessary.
ACK -- removed. :)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91262/new/

https://reviews.llvm.org/D91262

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D91067: [AArch64][SVE] Support implicit lax vector conversions for SVE types

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 304811.
joechrisellis marked an inline comment as done.
joechrisellis added a comment.

- Support C lax vector conversions.
- Test C lax vector conversions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91067/new/

https://reviews.llvm.org/D91067

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/test/Sema/aarch64-sve-lax-vector-conversions.c
  clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp

Index: clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
===
--- /dev/null
+++ clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
@@ -0,0 +1,34 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-none %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=integer -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-integer %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=all -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-all %s
+
+// lax-vector-all-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+
+void allowed_with_integer_lax_conversions() {
+  fixed_int32_t fi32;
+  svint64_t si64;
+
+  // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
+  // -flax-vector-conversions={integer,all}.
+  fi32 = si64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+}
+
+void allowed_with_all_lax_conversions() {
+  fixed_float32_t ff32;
+  svfloat64_t sf64;
+
+  // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
+  // -flax-vector-conversions=all.
+  ff32 = sf64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+}
Index: clang/test/Sema/aarch64-sve-lax-vector-conversions.c
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-lax-vector-conversions.c
@@ -0,0 +1,34 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-none %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=integer -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-integer %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=all -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-all %s
+
+// lax-vector-all-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+
+void allowed_with_integer_lax_conversions() {
+  fixed_int32_t fi32;
+  svint64_t si64;
+
+  // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
+  // -flax-vector-conversions={integer,all}.
+  fi32 = si64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+}
+
+void allowed_with_all_lax_conversions() {
+  fixed_float32_t ff32;
+  svfloat64_t sf64;
+
+  // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
+  // -flax-vector-conversions=all.
+  ff32 = sf64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+}
Index: clang/lib/Sema/SemaOverload.cpp
===
--- clang/lib/Sema/SemaOverload.cpp
+++ clang/lib/Sema/SemaOverload.cpp
@@ -1644,11 +1644,12 @@
 }
   }
 
-  if ((ToType->isSizelessBuiltinType() || FromType->isSizelessBuiltinType()) &&
-  S.Context.areCompatibleSveTypes(FromType, ToType)) {
-ICK = ICK_SVE_Vector_Conversion;
-return true;
-  }
+  if (ToType->isSizelessBuiltinType() || FromType->isSizelessBuilti

[PATCH] D91333: [clang][SveEmitter] Fix enum declarations. [NFCI]

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis added a comment.

Thanks for the patch @fpetrogalli! One small comment from me, but not a blocker 
for me, so approved.




Comment at: clang/test/Sema/aarch64-sve-enums.c:14-15
+#include 
+enum svpattern a1 = SV_ALL;
+svpattern b1 = {1.0f};
+enum svprfop a2 = SV_PLDL1KEEP;

[nit] It would be good if you could add a small comment here explaining what 
this is doing. As far as I can tell, you're creating a typedef'd struct with 
the same identifier as the one defined in `arm_sve.h`, then checking that it 
does not overload `enum svpattern` defined in `arm_sve.h`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91333/new/

https://reviews.llvm.org/D91333

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D91067: [AArch64][SVE] Support implicit lax vector conversions for SVE types

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 305494.
joechrisellis added a comment.

Remove failing test; it was checking that a conversion _failed_, although the 
conversion should now _pass_ given the changes in this patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91067/new/

https://reviews.llvm.org/D91067

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/test/Sema/aarch64-sve-lax-vector-conversions.c
  clang/test/Sema/attr-arm-sve-vector-bits.c
  clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp

Index: clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
===
--- /dev/null
+++ clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
@@ -0,0 +1,34 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-none %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=integer -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-integer %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=all -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-all %s
+
+// lax-vector-all-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+
+void allowed_with_integer_lax_conversions() {
+  fixed_int32_t fi32;
+  svint64_t si64;
+
+  // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
+  // -flax-vector-conversions={integer,all}.
+  fi32 = si64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+}
+
+void allowed_with_all_lax_conversions() {
+  fixed_float32_t ff32;
+  svfloat64_t sf64;
+
+  // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
+  // -flax-vector-conversions=all.
+  ff32 = sf64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+}
Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -270,7 +270,6 @@
 TEST_CAST_COMMON(bool)
 
 // Test the implicit conversion only applies to valid types
-fixed_int8_t to_fixed_int8_t__from_svuint8_t(svuint8_t x) { return x; } // expected-error-re {{returning 'svuint8_t' (aka '__SVUint8_t') from a function with incompatible result type 'fixed_int8_t' (vector of {{[0-9]+}} 'signed char' values)}}
 fixed_bool_t to_fixed_bool_t__from_svint32_t(svint32_t x) { return x; } // expected-error-re {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible result type 'fixed_bool_t' (vector of {{[0-9]+}} 'unsigned char' values)}}
 
 svint64_t to_svint64_t__from_gnu_int32_t(gnu_int32_t x) { return x; } // expected-error-re {{returning 'gnu_int32_t' (vector of {{[0-9]+}} 'int32_t' values) from a function with incompatible result type 'svint64_t' (aka '__SVInt64_t')}}
Index: clang/test/Sema/aarch64-sve-lax-vector-conversions.c
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-lax-vector-conversions.c
@@ -0,0 +1,34 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-none %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=integer -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-integer %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=all -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-all %s
+
+// lax-vector-all-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+
+void allowed_with_integer_lax_conversions() {
+  fixed_int32_t fi32;
+  svint64_t si64;
+
+  // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
+  // -flax-vector-conversions={i

[PATCH] D91262: [AArch64][SVE] Allow C-style casts between fixed-size and scalable vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 305763.
joechrisellis marked 7 inline comments as done.
joechrisellis added a comment.

Address @c-rhodes's and @peterwaller-arm's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91262/new/

https://reviews.llvm.org/D91262

Files:
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
  clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp

Index: clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp
===
--- /dev/null
+++ clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp
@@ -0,0 +1,49 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=128 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=256 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=1024 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=2048 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svfloat64_t fixed_float64_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+
+// SVE VLSTs can be cast to SVE VLATs, regardless of lane size.
+// NOTE: the list below is NOT exhaustive for all SVE types.
+
+#define CAST(from, to) \
+void from##_to_##to(from a, to b) { \
+b = (to) a; \
+}
+
+#define TESTCASE(ty1, ty2) \
+CAST(ty1, ty2) \
+CAST(ty2, ty1)
+
+TESTCASE(fixed_float32_t, svfloat32_t)
+TESTCASE(fixed_float32_t, svfloat64_t)
+TESTCASE(fixed_float32_t, svint32_t)
+TESTCASE(fixed_float32_t, svint64_t)
+
+TESTCASE(fixed_float64_t, svfloat32_t)
+TESTCASE(fixed_float64_t, svfloat64_t)
+TESTCASE(fixed_float64_t, svint32_t)
+TESTCASE(fixed_float64_t, svint64_t)
+
+TESTCASE(fixed_int32_t, svfloat32_t)
+TESTCASE(fixed_int32_t, svfloat64_t)
+TESTCASE(fixed_int32_t, svint32_t)
+TESTCASE(fixed_int32_t, svint64_t)
+
+TESTCASE(fixed_int64_t, svfloat32_t)
+TESTCASE(fixed_int64_t, svfloat64_t)
+TESTCASE(fixed_int64_t, svint32_t)
+TESTCASE(fixed_int64_t, svint64_t)
Index: clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
@@ -0,0 +1,49 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=128 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=256 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=1024 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=2048 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svfloat64_t fixed_float64_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+
+// SVE VLSTs can be cast to SVE VLATs, regardless of lane size.
+// NOTE: the list below is NOT exhaustive for all SVE types.
+
+#define CAST(from, to) \
+void from##_to_##to(from a, to b) { \
+b = (to) a; \
+}
+
+#define TESTCASE(ty1, ty2) \
+CAST(ty1, ty2) \
+CAST(ty2, ty1)
+
+TESTCASE(fixed_float32_t, svfloat32_t)
+TESTCASE(fixed_float32_t, svfloat64_t)
+TESTCASE(fixed_float32_t, svint32_t)
+

[PATCH] D91262: [AArch64][SVE] Allow C-style casts between fixed-size and scalable vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis added inline comments.



Comment at: clang/lib/Sema/SemaCast.cpp:2217-2218
 
-  // Allow reinterpret_casts between vectors of the same size and
-  // between vectors and integers of the same size.
   bool destIsVector = DestType->isVectorType();

c-rhodes wrote:
> nit: not sure we need to change this
I changed this because the code changes mean that the original comment is 
incomplete. I.e., we now allow for reinterpret casts VLAT <-> VLST, which is 
not captured by the comment above.



Comment at: clang/lib/Sema/SemaCast.cpp:2763
+  // SVE bitcast. We can bitcast between SVE VLATs and VLSTs, and vice-versa.
+  if (SrcType->isVectorType() || DestType->isVectorType())
+if (Self.isValidSveBitcast(SrcType, DestType)) {

peterwaller-arm wrote:
> c-rhodes wrote:
> > I think braces are recommended on the outer if as well, see: 
> > https://llvm.org/docs/CodingStandards.html#don-t-use-braces-on-simple-single-statement-bodies-of-if-else-loop-statements
> > 
> > Although I suppose it could also be written as:
> > 
> > ```
> > if ((SrcType->isVectorType() || DestType->isVectorType()) &&
> > Self.isValidSveBitcast(SrcType, DestType)) {
> >   Kind = CK_BitCast;
> >   return;
> > }```
> I don't understand why this is an || rather than an &&, please can you 
> clarify? I would have expected they must both be vectors.
The sizeless types defined by the ACLE are represented in Clang as 
`BuiltinType`s rather than `VectorType`s. The sized types are represented as 
`VectorTypes`. The only possibility for a valid C-style cast is when we're 
casting VLAT <-> VLST, which is if one of the two is a `VectorType`. :) 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91262/new/

https://reviews.llvm.org/D91262

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D91262: [AArch64][SVE] Allow C-style casts between fixed-size and scalable vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis added inline comments.



Comment at: clang/lib/Sema/SemaCast.cpp:2217-2218
 
-  // Allow reinterpret_casts between vectors of the same size and
-  // between vectors and integers of the same size.
   bool destIsVector = DestType->isVectorType();

c-rhodes wrote:
> joechrisellis wrote:
> > c-rhodes wrote:
> > > nit: not sure we need to change this
> > I changed this because the code changes mean that the original comment is 
> > incomplete. I.e., we now allow for reinterpret casts VLAT <-> VLST, which 
> > is not captured by the comment above.
> > I changed this because the code changes mean that the original comment is 
> > incomplete. I.e., we now allow for reinterpret casts VLAT <-> VLST, which 
> > is not captured by the comment above.
> 
> It's a minor point but the reason I raised it is we have to be conscious of 
> the fact most people probably don't care about SVE and this is changing an 
> existing comment to put it first and foremost.
Ok, I see what you mean. Will revert this part.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91262/new/

https://reviews.llvm.org/D91262

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D91262: [AArch64][SVE] Allow C-style casts between fixed-size and scalable vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 305769.
joechrisellis added a comment.

Address @c-rhodes's comment regarding comment change.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91262/new/

https://reviews.llvm.org/D91262

Files:
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
  clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp

Index: clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp
===
--- /dev/null
+++ clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp
@@ -0,0 +1,49 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=128 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=256 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=1024 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=2048 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svfloat64_t fixed_float64_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+
+// SVE VLSTs can be cast to SVE VLATs, regardless of lane size.
+// NOTE: the list below is NOT exhaustive for all SVE types.
+
+#define CAST(from, to) \
+void from##_to_##to(from a, to b) { \
+b = (to) a; \
+}
+
+#define TESTCASE(ty1, ty2) \
+CAST(ty1, ty2) \
+CAST(ty2, ty1)
+
+TESTCASE(fixed_float32_t, svfloat32_t)
+TESTCASE(fixed_float32_t, svfloat64_t)
+TESTCASE(fixed_float32_t, svint32_t)
+TESTCASE(fixed_float32_t, svint64_t)
+
+TESTCASE(fixed_float64_t, svfloat32_t)
+TESTCASE(fixed_float64_t, svfloat64_t)
+TESTCASE(fixed_float64_t, svint32_t)
+TESTCASE(fixed_float64_t, svint64_t)
+
+TESTCASE(fixed_int32_t, svfloat32_t)
+TESTCASE(fixed_int32_t, svfloat64_t)
+TESTCASE(fixed_int32_t, svint32_t)
+TESTCASE(fixed_int32_t, svint64_t)
+
+TESTCASE(fixed_int64_t, svfloat32_t)
+TESTCASE(fixed_int64_t, svfloat64_t)
+TESTCASE(fixed_int64_t, svint32_t)
+TESTCASE(fixed_int64_t, svint64_t)
Index: clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
@@ -0,0 +1,49 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=128 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=256 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=1024 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=2048 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svfloat64_t fixed_float64_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+
+// SVE VLSTs can be cast to SVE VLATs, regardless of lane size.
+// NOTE: the list below is NOT exhaustive for all SVE types.
+
+#define CAST(from, to) \
+void from##_to_##to(from a, to b) { \
+b = (to) a; \
+}
+
+#define TESTCASE(ty1, ty2) \
+CAST(ty1, ty2) \
+CAST(ty2, ty1)
+
+TESTCASE(fixed_float32_t, svfloat32_t)
+TESTCASE(fixed_float32_t, svfloat64_t)
+TESTCASE(fixed_float32_t, svint32_t)
+TESTCASE(fixed_float32_t, svint64_t)
+
+TESTCAS

[PATCH] D91067: [AArch64][SVE] Support implicit lax vector conversions for SVE types

[Joe Ellis via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG23a96b84a8d9: [AArch64][SVE] Support implicit lax vector 
conversions for SVE types (authored by joechrisellis).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91067/new/

https://reviews.llvm.org/D91067

Files:
  clang/include/clang/AST/ASTContext.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/test/Sema/aarch64-sve-lax-vector-conversions.c
  clang/test/Sema/attr-arm-sve-vector-bits.c
  clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp

Index: clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
===
--- /dev/null
+++ clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
@@ -0,0 +1,34 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-none %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=integer -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-integer %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=all -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-all %s
+
+// lax-vector-all-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+
+void allowed_with_integer_lax_conversions() {
+  fixed_int32_t fi32;
+  svint64_t si64;
+
+  // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
+  // -flax-vector-conversions={integer,all}.
+  fi32 = si64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+}
+
+void allowed_with_all_lax_conversions() {
+  fixed_float32_t ff32;
+  svfloat64_t sf64;
+
+  // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
+  // -flax-vector-conversions=all.
+  ff32 = sf64;
+  // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+}
Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -270,7 +270,6 @@
 TEST_CAST_COMMON(bool)
 
 // Test the implicit conversion only applies to valid types
-fixed_int8_t to_fixed_int8_t__from_svuint8_t(svuint8_t x) { return x; } // expected-error-re {{returning 'svuint8_t' (aka '__SVUint8_t') from a function with incompatible result type 'fixed_int8_t' (vector of {{[0-9]+}} 'signed char' values)}}
 fixed_bool_t to_fixed_bool_t__from_svint32_t(svint32_t x) { return x; } // expected-error-re {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible result type 'fixed_bool_t' (vector of {{[0-9]+}} 'unsigned char' values)}}
 
 svint64_t to_svint64_t__from_gnu_int32_t(gnu_int32_t x) { return x; } // expected-error-re {{returning 'gnu_int32_t' (vector of {{[0-9]+}} 'int32_t' values) from a function with incompatible result type 'svint64_t' (aka '__SVInt64_t')}}
Index: clang/test/Sema/aarch64-sve-lax-vector-conversions.c
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-lax-vector-conversions.c
@@ -0,0 +1,34 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-none %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=integer -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-integer %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=all -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify=lax-vector-all %s
+
+// lax-vector-all-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+
+void allowed_with_integer_lax_conversions() {
+  fixed_int32_t fi32;
+  svint64_t si64;
+
+  // The implicit cast here should fail if -flax-vector-conversions=none, but pass 

[PATCH] D91642: [AArch64][SVE] Add tests for VLST -> VLAT lax conversions

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis created this revision.
joechrisellis added a reviewer: fpetrogalli.
Herald added subscribers: cfe-commits, psnobl, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: clang.
joechrisellis requested review of this revision.

These were previously missing from the SVE lax conversions tests.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91642

Files:
  clang/test/Sema/aarch64-sve-lax-vector-conversions.c
  clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp


Index: clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
===
--- clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
+++ clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
@@ -20,6 +20,8 @@
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 
'int' values) from incompatible type}}
+  si64 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') 
from incompatible type}}
 }
 
 void allowed_with_all_lax_conversions() {
@@ -31,4 +33,7 @@
   ff32 = sf64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 
'float' values) from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 
16 'float' values) from incompatible type}}
+  sf64 = ff32;
+  // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka 
'__SVFloat64_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka 
'__SVFloat64_t') from incompatible type}}
 }
Index: clang/test/Sema/aarch64-sve-lax-vector-conversions.c
===
--- clang/test/Sema/aarch64-sve-lax-vector-conversions.c
+++ clang/test/Sema/aarch64-sve-lax-vector-conversions.c
@@ -20,6 +20,8 @@
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 
'int' values) from incompatible type}}
+  si64 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') 
from incompatible type}}
 }
 
 void allowed_with_all_lax_conversions() {
@@ -31,4 +33,7 @@
   ff32 = sf64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 
'float' values) from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 
16 'float' values) from incompatible type}}
+  sf64 = ff32;
+  // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka 
'__SVFloat64_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka 
'__SVFloat64_t') from incompatible type}}
 }


Index: clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
===
--- clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
+++ clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
@@ -20,6 +20,8 @@
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  si64 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
 }
 
 void allowed_with_all_lax_conversions() {
@@ -31,4 +33,7 @@
   ff32 = sf64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  sf64 = ff32;
+  // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
 }
Index: clang/test/Sema/aarch64-sve-lax-vector-conversions.c
===
--- clang/test/Sema/aarch64-sve-lax-vector-conversions.c
+++ clang/test/Sema/aarch64-sve-lax-vector-conversions.c
@@ -20,6 +20,8 @@
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  si64 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
 }
 
 void allowed_with_all_lax_conversions() {
@@ -31,4 +33,7 @@
   ff32 = sf64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  sf64 = ff32;
+  // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVF

[PATCH] D91642: [AArch64][SVE] Add tests for VLST -> VLAT lax conversions

[Joe Ellis via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1d7abcf99e3d: [AArch64][SVE] Add tests for VLST -> VLAT 
lax conversions (authored by joechrisellis).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91642/new/

https://reviews.llvm.org/D91642

Files:
  clang/test/Sema/aarch64-sve-lax-vector-conversions.c
  clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp


Index: clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
===
--- clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
+++ clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
@@ -20,6 +20,8 @@
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 
'int' values) from incompatible type}}
+  si64 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') 
from incompatible type}}
 }
 
 void allowed_with_all_lax_conversions() {
@@ -31,4 +33,7 @@
   ff32 = sf64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 
'float' values) from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 
16 'float' values) from incompatible type}}
+  sf64 = ff32;
+  // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka 
'__SVFloat64_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka 
'__SVFloat64_t') from incompatible type}}
 }
Index: clang/test/Sema/aarch64-sve-lax-vector-conversions.c
===
--- clang/test/Sema/aarch64-sve-lax-vector-conversions.c
+++ clang/test/Sema/aarch64-sve-lax-vector-conversions.c
@@ -20,6 +20,8 @@
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 
'int' values) from incompatible type}}
+  si64 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') 
from incompatible type}}
 }
 
 void allowed_with_all_lax_conversions() {
@@ -31,4 +33,7 @@
   ff32 = sf64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 
'float' values) from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 
16 'float' values) from incompatible type}}
+  sf64 = ff32;
+  // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka 
'__SVFloat64_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka 
'__SVFloat64_t') from incompatible type}}
 }


Index: clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
===
--- clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
+++ clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
@@ -20,6 +20,8 @@
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  si64 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
 }
 
 void allowed_with_all_lax_conversions() {
@@ -31,4 +33,7 @@
   ff32 = sf64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  sf64 = ff32;
+  // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
 }
Index: clang/test/Sema/aarch64-sve-lax-vector-conversions.c
===
--- clang/test/Sema/aarch64-sve-lax-vector-conversions.c
+++ clang/test/Sema/aarch64-sve-lax-vector-conversions.c
@@ -20,6 +20,8 @@
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  si64 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
 }
 
 void allowed_with_all_lax_conversions() {
@@ -31,4 +33,7 @@
   ff32 = sf64;
   // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  sf64 = ff32;
+  // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from inco

[PATCH] D91696: [AArch64][SVE] Allow lax conversion between VLATs and GNU vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis created this revision.
joechrisellis added reviewers: fpetrogalli, peterwaller-arm.
Herald added subscribers: cfe-commits, psnobl, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: clang.
joechrisellis requested review of this revision.

Previously, lax conversions were only allowed between SVE vector-length
agnostic types and vector-length specific types. This meant that code
such as the following:

  #include 
  #define N __ARM_FEATURE_SVE_BITS
  #define FIXED_ATTR __attribute__ ((vector_size (N/8)))
  typedef float fixed_float32_t FIXED_ATTR;
  
  void foo() {
  fixed_float32_t fs32;
  svfloat64_t s64;
  fs32 = s64;
  }

was not allowed.

This patch makes a minor change to areLaxCompatibleSveTypes to allow for
lax conversions to be performed between SVE vector-length agnostic types
and GNU vectors.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91696

Files:
  clang/lib/AST/ASTContext.cpp
  clang/test/Sema/aarch64-sve-lax-vector-conversions.c
  clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp

Index: clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
===
--- clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
+++ clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
@@ -7,32 +7,61 @@
 #include 
 
 #define N __ARM_FEATURE_SVE_BITS
-#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+#define SVE_FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+#define GNU_FIXED_ATTR __attribute__((vector_size(N / 8)))
 
-typedef svfloat32_t fixed_float32_t FIXED_ATTR;
-typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svfloat32_t sve_fixed_float32_t SVE_FIXED_ATTR;
+typedef svint32_t sve_fixed_int32_t SVE_FIXED_ATTR;
+typedef float gnu_fixed_float32_t GNU_FIXED_ATTR;
+typedef int gnu_fixed_int32_t GNU_FIXED_ATTR;
 
-void allowed_with_integer_lax_conversions() {
-  fixed_int32_t fi32;
+void sve_allowed_with_integer_lax_conversions() {
+  sve_fixed_int32_t fi32;
   svint64_t si64;
 
   // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
-  // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  // lax-vector-none-error@-1 {{assigning to 'sve_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
   si64 = fi32;
   // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
 }
 
-void allowed_with_all_lax_conversions() {
-  fixed_float32_t ff32;
+void sve_allowed_with_all_lax_conversions() {
+  sve_fixed_float32_t ff32;
   svfloat64_t sf64;
 
   // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
   // -flax-vector-conversions=all.
   ff32 = sf64;
-  // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
-  // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-none-error@-1 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  sf64 = ff32;
+  // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
+}
+
+void gnu_allowed_with_integer_lax_conversions() {
+  gnu_fixed_int32_t fi32;
+  svint64_t si64;
+
+  // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
+  // -flax-vector-conversions={integer,all}.
+  fi32 = si64;
+  // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  si64 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
+}
+
+void gnu_allowed_with_all_lax_conversions() {
+  gnu_fixed_float32_t ff32;
+  svfloat64_t sf64;
+
+  // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
+  // -flax-vector-conversions=all.
+  ff32 = sf64;
+  // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
   sf64 = ff32;
   // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
Index: clang/test/Sema/aarch64-sve-lax-vector-conversions.c
===
--- clang/test/Se

[PATCH] D91696: [AArch64][SVE] Allow lax conversion between VLATs and GNU vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 306043.
joechrisellis added a comment.

Remove redundant tests from clang/test/Sema/attr-arm-sve-vector-bits.c.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91696/new/

https://reviews.llvm.org/D91696

Files:
  clang/lib/AST/ASTContext.cpp
  clang/test/Sema/aarch64-sve-lax-vector-conversions.c
  clang/test/Sema/attr-arm-sve-vector-bits.c
  clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp

Index: clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
===
--- clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
+++ clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
@@ -7,32 +7,61 @@
 #include 
 
 #define N __ARM_FEATURE_SVE_BITS
-#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+#define SVE_FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+#define GNU_FIXED_ATTR __attribute__((vector_size(N / 8)))
 
-typedef svfloat32_t fixed_float32_t FIXED_ATTR;
-typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svfloat32_t sve_fixed_float32_t SVE_FIXED_ATTR;
+typedef svint32_t sve_fixed_int32_t SVE_FIXED_ATTR;
+typedef float gnu_fixed_float32_t GNU_FIXED_ATTR;
+typedef int gnu_fixed_int32_t GNU_FIXED_ATTR;
 
-void allowed_with_integer_lax_conversions() {
-  fixed_int32_t fi32;
+void sve_allowed_with_integer_lax_conversions() {
+  sve_fixed_int32_t fi32;
   svint64_t si64;
 
   // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
-  // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  // lax-vector-none-error@-1 {{assigning to 'sve_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
   si64 = fi32;
   // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
 }
 
-void allowed_with_all_lax_conversions() {
-  fixed_float32_t ff32;
+void sve_allowed_with_all_lax_conversions() {
+  sve_fixed_float32_t ff32;
   svfloat64_t sf64;
 
   // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
   // -flax-vector-conversions=all.
   ff32 = sf64;
-  // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
-  // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-none-error@-1 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  sf64 = ff32;
+  // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
+}
+
+void gnu_allowed_with_integer_lax_conversions() {
+  gnu_fixed_int32_t fi32;
+  svint64_t si64;
+
+  // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
+  // -flax-vector-conversions={integer,all}.
+  fi32 = si64;
+  // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  si64 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
+}
+
+void gnu_allowed_with_all_lax_conversions() {
+  gnu_fixed_float32_t ff32;
+  svfloat64_t sf64;
+
+  // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
+  // -flax-vector-conversions=all.
+  ff32 = sf64;
+  // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
   sf64 = ff32;
   // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -272,16 +272,6 @@
 // Test the implicit conversion only applies to valid types
 fixed_bool_t to_fixed_bool_t__from_svint32_t(svint32_t x) { return x; } // expected-error-re {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible result type 'fixed_bool_t' (vector of {{[0-9]+}} 'unsigned char' values)}}
 
-svint64_t to_svint64_t__from_gnu_int32_t(gnu_int32_t x) { return x; } // expected-error-re {{returning 'gnu_int32_t' (vector of {{[0-9]+}} 'int32_t' values) from a function with incompatible result type 'svi

[PATCH] D91696: [AArch64][SVE] Allow lax conversion between VLATs and GNU vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 306351.
joechrisellis marked an inline comment as done.
joechrisellis added a comment.

Address @c-rhodes's comments regarding lax conversion when 
__ARM_FEATURE_SVE_BITS != N for GNU vectors.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91696/new/

https://reviews.llvm.org/D91696

Files:
  clang/lib/AST/ASTContext.cpp
  clang/test/Sema/aarch64-sve-lax-vector-conversions.c
  clang/test/Sema/attr-arm-sve-vector-bits.c
  clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp

Index: clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
===
--- clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
+++ clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
@@ -7,32 +7,61 @@
 #include 
 
 #define N __ARM_FEATURE_SVE_BITS
-#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+#define SVE_FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+#define GNU_FIXED_ATTR __attribute__((vector_size(N / 8)))
 
-typedef svfloat32_t fixed_float32_t FIXED_ATTR;
-typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svfloat32_t sve_fixed_float32_t SVE_FIXED_ATTR;
+typedef svint32_t sve_fixed_int32_t SVE_FIXED_ATTR;
+typedef float gnu_fixed_float32_t GNU_FIXED_ATTR;
+typedef int gnu_fixed_int32_t GNU_FIXED_ATTR;
 
-void allowed_with_integer_lax_conversions() {
-  fixed_int32_t fi32;
+void sve_allowed_with_integer_lax_conversions() {
+  sve_fixed_int32_t fi32;
   svint64_t si64;
 
   // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
-  // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  // lax-vector-none-error@-1 {{assigning to 'sve_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
   si64 = fi32;
   // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
 }
 
-void allowed_with_all_lax_conversions() {
-  fixed_float32_t ff32;
+void sve_allowed_with_all_lax_conversions() {
+  sve_fixed_float32_t ff32;
   svfloat64_t sf64;
 
   // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
   // -flax-vector-conversions=all.
   ff32 = sf64;
-  // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
-  // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-none-error@-1 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  sf64 = ff32;
+  // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
+}
+
+void gnu_allowed_with_integer_lax_conversions() {
+  gnu_fixed_int32_t fi32;
+  svint64_t si64;
+
+  // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
+  // -flax-vector-conversions={integer,all}.
+  fi32 = si64;
+  // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  si64 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
+}
+
+void gnu_allowed_with_all_lax_conversions() {
+  gnu_fixed_float32_t ff32;
+  svfloat64_t sf64;
+
+  // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
+  // -flax-vector-conversions=all.
+  ff32 = sf64;
+  // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
   sf64 = ff32;
   // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -272,9 +272,6 @@
 // Test the implicit conversion only applies to valid types
 fixed_bool_t to_fixed_bool_t__from_svint32_t(svint32_t x) { return x; } // expected-error-re {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible result type 'fixed_bool_t' (vector of {{[0-9]+}} 'unsigned char' values)}}
 
-svint64_t to_svint64_t__from_gnu_int32_t(gnu_int32_t x) { return x; } // expected-error-re {{returning 'gnu_int32_t' (vector of

[PATCH] D91696: [AArch64][SVE] Allow lax conversion between VLATs and GNU vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis added inline comments.



Comment at: clang/test/Sema/attr-arm-sve-vector-bits.c:278-283
-// Test implicit conversion between SVE and GNU vector is invalid when
-// __ARM_FEATURE_SVE_BITS != N
-#if defined(__ARM_FEATURE_SVE_BITS) && __ARM_FEATURE_SVE_BITS == 512
-typedef int32_t int4 __attribute__((vector_size(16)));
-svint32_t badcast(int4 x) { return x; } // expected-error {{returning 'int4' 
(vector of 4 'int32_t' values) from a function with incompatible result type 
'svint32_t' (aka '__SVInt32_t')}}
-#endif

c-rhodes wrote:
> I don't think this can be removed. The ACLE states "Whenever 
> __ARM_FEATURE_SVE_BITS==N, GNUT implicitly converts to VLAT and VLAT 
> implicitly converts to GNUT.".
> 
> AFAIK lax vector conversions only apply to vectors of the same width, with 
> GNU vectors for example the following is invalid regardless of lax vector 
> conversions:
> 
> ```typedef int8_t int8x16_t __attribute__((vector_size(16)));
> typedef int8_t int8x64_t __attribute__((vector_size(64)));
> 
> int8x16_t foo(int8x64_t x) { return x; }```
Great spot, didn't see that in the spec. I've re-added the test and added an 
extra condition to check if `__ARM_FEATURE_SVE_BITS == N` before allowing the 
lax conversion for GNU vectors. Not sure if this is the best way to do it, 
though. :) 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91696/new/

https://reviews.llvm.org/D91696

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D91262: [AArch64][SVE] Allow C-style casts between fixed-size and scalable vectors

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 306358.
joechrisellis added a comment.

Avoid doing `FirstType->getAs()`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91262/new/

https://reviews.llvm.org/D91262

Files:
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
  clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp

Index: clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp
===
--- /dev/null
+++ clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp
@@ -0,0 +1,49 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=128 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=256 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=1024 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=2048 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svfloat64_t fixed_float64_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+
+// SVE VLSTs can be cast to SVE VLATs, regardless of lane size.
+// NOTE: the list below is NOT exhaustive for all SVE types.
+
+#define CAST(from, to) \
+void from##_to_##to(from a, to b) { \
+b = (to) a; \
+}
+
+#define TESTCASE(ty1, ty2) \
+CAST(ty1, ty2) \
+CAST(ty2, ty1)
+
+TESTCASE(fixed_float32_t, svfloat32_t)
+TESTCASE(fixed_float32_t, svfloat64_t)
+TESTCASE(fixed_float32_t, svint32_t)
+TESTCASE(fixed_float32_t, svint64_t)
+
+TESTCASE(fixed_float64_t, svfloat32_t)
+TESTCASE(fixed_float64_t, svfloat64_t)
+TESTCASE(fixed_float64_t, svint32_t)
+TESTCASE(fixed_float64_t, svint64_t)
+
+TESTCASE(fixed_int32_t, svfloat32_t)
+TESTCASE(fixed_int32_t, svfloat64_t)
+TESTCASE(fixed_int32_t, svint32_t)
+TESTCASE(fixed_int32_t, svint64_t)
+
+TESTCASE(fixed_int64_t, svfloat32_t)
+TESTCASE(fixed_int64_t, svfloat64_t)
+TESTCASE(fixed_int64_t, svint32_t)
+TESTCASE(fixed_int64_t, svint64_t)
Index: clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
@@ -0,0 +1,49 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=128 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=256 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=1024 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=2048 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svfloat64_t fixed_float64_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+
+// SVE VLSTs can be cast to SVE VLATs, regardless of lane size.
+// NOTE: the list below is NOT exhaustive for all SVE types.
+
+#define CAST(from, to) \
+void from##_to_##to(from a, to b) { \
+b = (to) a; \
+}
+
+#define TESTCASE(ty1, ty2) \
+CAST(ty1, ty2) \
+CAST(ty2, ty1)
+
+TESTCASE(fixed_float32_t, svfloat32_t)
+TESTCASE(fixed_float32_t, svfloat64_t)
+TESTCASE(fixed_float32_t, svint32_t)
+TESTCASE(fixed_float32_t, svint64_t)
+
+TESTCASE(fixed_float64_t, s

[PATCH] D91262: [AArch64][SVE] Allow C-style casts between fixed-size and scalable vectors

[Joe Ellis via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1e2da3839cc3: [AArch64][SVE] Allow C-style casts between 
fixed-size and scalable vectors (authored by joechrisellis).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91262/new/

https://reviews.llvm.org/D91262

Files:
  clang/include/clang/Sema/Sema.h
  clang/lib/Sema/SemaCast.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
  clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp

Index: clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp
===
--- /dev/null
+++ clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp
@@ -0,0 +1,49 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=128 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=256 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=1024 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=2048 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svfloat64_t fixed_float64_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+
+// SVE VLSTs can be cast to SVE VLATs, regardless of lane size.
+// NOTE: the list below is NOT exhaustive for all SVE types.
+
+#define CAST(from, to) \
+void from##_to_##to(from a, to b) { \
+b = (to) a; \
+}
+
+#define TESTCASE(ty1, ty2) \
+CAST(ty1, ty2) \
+CAST(ty2, ty1)
+
+TESTCASE(fixed_float32_t, svfloat32_t)
+TESTCASE(fixed_float32_t, svfloat64_t)
+TESTCASE(fixed_float32_t, svint32_t)
+TESTCASE(fixed_float32_t, svint64_t)
+
+TESTCASE(fixed_float64_t, svfloat32_t)
+TESTCASE(fixed_float64_t, svfloat64_t)
+TESTCASE(fixed_float64_t, svint32_t)
+TESTCASE(fixed_float64_t, svint64_t)
+
+TESTCASE(fixed_int32_t, svfloat32_t)
+TESTCASE(fixed_int32_t, svfloat64_t)
+TESTCASE(fixed_int32_t, svint32_t)
+TESTCASE(fixed_int32_t, svint64_t)
+
+TESTCASE(fixed_int64_t, svfloat32_t)
+TESTCASE(fixed_int64_t, svfloat64_t)
+TESTCASE(fixed_int64_t, svint32_t)
+TESTCASE(fixed_int64_t, svint64_t)
Index: clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
===
--- /dev/null
+++ clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
@@ -0,0 +1,49 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=128 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=256 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=512 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=1024 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -msve-vector-bits=2048 -flax-vector-conversions=none -fallow-half-arguments-and-returns -ffreestanding -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svfloat32_t fixed_float32_t FIXED_ATTR;
+typedef svfloat64_t fixed_float64_t FIXED_ATTR;
+typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svint64_t fixed_int64_t FIXED_ATTR;
+
+// SVE VLSTs can be cast to SVE VLATs, regardless of lane size.
+// NOTE: the list below is NOT exhaustive for all SVE types.
+
+#define CAST(from, to) \
+void from##_to_##to(from a, to b) { \
+b = (to) a; \
+}
+
+#define TESTCASE(ty1, ty2) \
+CAST(ty1, ty2) \
+CAST(ty2, ty1)
+
+TESTCASE(fixed_float32_t, svfloat32_

[PATCH] D91696: [AArch64][SVE] Allow lax conversion between VLATs and GNU vectors

[Joe Ellis via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3c696a212ba4: [AArch64][SVE] Allow lax conversion between 
VLATs and GNU vectors (authored by joechrisellis).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91696/new/

https://reviews.llvm.org/D91696

Files:
  clang/lib/AST/ASTContext.cpp
  clang/test/Sema/aarch64-sve-lax-vector-conversions.c
  clang/test/Sema/attr-arm-sve-vector-bits.c
  clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp

Index: clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
===
--- clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
+++ clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
@@ -7,32 +7,61 @@
 #include 
 
 #define N __ARM_FEATURE_SVE_BITS
-#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+#define SVE_FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+#define GNU_FIXED_ATTR __attribute__((vector_size(N / 8)))
 
-typedef svfloat32_t fixed_float32_t FIXED_ATTR;
-typedef svint32_t fixed_int32_t FIXED_ATTR;
+typedef svfloat32_t sve_fixed_float32_t SVE_FIXED_ATTR;
+typedef svint32_t sve_fixed_int32_t SVE_FIXED_ATTR;
+typedef float gnu_fixed_float32_t GNU_FIXED_ATTR;
+typedef int gnu_fixed_int32_t GNU_FIXED_ATTR;
 
-void allowed_with_integer_lax_conversions() {
-  fixed_int32_t fi32;
+void sve_allowed_with_integer_lax_conversions() {
+  sve_fixed_int32_t fi32;
   svint64_t si64;
 
   // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
   // -flax-vector-conversions={integer,all}.
   fi32 = si64;
-  // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  // lax-vector-none-error@-1 {{assigning to 'sve_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
   si64 = fi32;
   // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
 }
 
-void allowed_with_all_lax_conversions() {
-  fixed_float32_t ff32;
+void sve_allowed_with_all_lax_conversions() {
+  sve_fixed_float32_t ff32;
   svfloat64_t sf64;
 
   // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
   // -flax-vector-conversions=all.
   ff32 = sf64;
-  // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
-  // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-none-error@-1 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  sf64 = ff32;
+  // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
+}
+
+void gnu_allowed_with_integer_lax_conversions() {
+  gnu_fixed_int32_t fi32;
+  svint64_t si64;
+
+  // The implicit cast here should fail if -flax-vector-conversions=none, but pass if
+  // -flax-vector-conversions={integer,all}.
+  fi32 = si64;
+  // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_int32_t' (vector of 16 'int' values) from incompatible type}}
+  si64 = fi32;
+  // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}}
+}
+
+void gnu_allowed_with_all_lax_conversions() {
+  gnu_fixed_float32_t ff32;
+  svfloat64_t sf64;
+
+  // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if
+  // -flax-vector-conversions=all.
+  ff32 = sf64;
+  // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
+  // lax-vector-integer-error@-2 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}}
   sf64 = ff32;
   // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
   // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}}
Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -272,9 +272,6 @@
 // Test the implicit conversion only applies to valid types
 fixed_bool_t to_fixed_bool_t__from_svint32_t(svint32_t x) { return x; } // expected-error-re {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible result type 'fixed_bool_t' (vector of {{[0-9]+}} 'unsigned char' values)}}
 
-svint64_t to_svint64_t__from_gnu_int32_t(gnu_int32_t x) { return x; } // expected-error-re {{returning 'gn

[PATCH] D91806: [SVE] Remove warning from debug info on scalable vector.

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis commandeered this revision.
joechrisellis edited reviewers, added: fpetrogalli; removed: joechrisellis.
joechrisellis added a comment.

I am finishing up this patch. 😄


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91806/new/

https://reviews.llvm.org/D91806

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D91806: [SVE] Remove warning from debug info on scalable vector.

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 308910.
joechrisellis added a comment.

Reduce debug info in `debug-declare-no-warnings-on-scalable-vectors.ll`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91806/new/

https://reviews.llvm.org/D91806

Files:
  llvm/lib/Transforms/Utils/Debugify.cpp
  llvm/lib/Transforms/Utils/Local.cpp
  
llvm/test/Transforms/InstCombine/debug-declare-no-warnings-on-scalable-vectors.ll

Index: llvm/test/Transforms/InstCombine/debug-declare-no-warnings-on-scalable-vectors.ll
===
--- /dev/null
+++ llvm/test/Transforms/InstCombine/debug-declare-no-warnings-on-scalable-vectors.ll
@@ -0,0 +1,31 @@
+; RUN: opt -mtriple aarch64-gnu-linux -mattr=+sve -instcombine -S < %s 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; If this check fails please read
+; clang/test/CodeGen/aarch64-sve-intrinsics/README for instructions on
+; how to resolve it.
+
+; WARN-NOT: warning
+
+; CHECK-LABEL: @debug_local_scalable(
+define  @debug_local_scalable( %tostore) {
+  %vx = alloca , align 16
+  call void @llvm.dbg.declare(metadata * %vx, metadata !3, metadata !DIExpression()), !dbg !5
+  store  %tostore, * %vx, align 16
+  %ret = call  @f(* %vx)
+  ret  %ret
+}
+
+declare  @f(*)
+
+; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
+declare void @llvm.dbg.declare(metadata, metadata, metadata)
+
+!llvm.module.flags = !{!2}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1)
+!1 = !DIFile(filename: "/tmp/test.c", directory: "/tmp/")
+!2 = !{i32 2, !"Debug Info Version", i32 3}
+!3 = !DILocalVariable(scope: !4)
+!4 = distinct !DISubprogram(unit: !0)
+!5 = !DILocation(scope: !4)
Index: llvm/lib/Transforms/Utils/Local.cpp
===
--- llvm/lib/Transforms/Utils/Local.cpp
+++ llvm/lib/Transforms/Utils/Local.cpp
@@ -1368,16 +1368,22 @@
 /// least n bits.
 static bool valueCoversEntireFragment(Type *ValTy, DbgVariableIntrinsic *DII) {
   const DataLayout &DL = DII->getModule()->getDataLayout();
-  uint64_t ValueSize = DL.getTypeAllocSizeInBits(ValTy);
-  if (auto FragmentSize = DII->getFragmentSizeInBits())
-return ValueSize >= *FragmentSize;
+  TypeSize ValueSize = DL.getTypeAllocSizeInBits(ValTy);
+  if (Optional FragmentSize = DII->getFragmentSizeInBits()) {
+assert(!ValueSize.isScalable() &&
+   "Fragments don't work on scalable types.");
+return ValueSize.getFixedSize() >= *FragmentSize;
+  }
   // We can't always calculate the size of the DI variable (e.g. if it is a
   // VLA). Try to use the size of the alloca that the dbg intrinsic describes
   // intead.
   if (DII->isAddressOfVariable())
 if (auto *AI = dyn_cast_or_null(DII->getVariableLocation()))
-  if (auto FragmentSize = AI->getAllocationSizeInBits(DL))
-return ValueSize >= *FragmentSize;
+  if (Optional FragmentSize = AI->getAllocationSizeInBits(DL)) {
+assert(ValueSize.isScalable() == FragmentSize->isScalable() &&
+   "Both sizes should agree on the scalable flag.");
+return TypeSize::isKnownGE(ValueSize, *FragmentSize);
+  }
   // Could not determine size of variable. Conservatively return false.
   return false;
 }
Index: llvm/lib/Transforms/Utils/Debugify.cpp
===
--- llvm/lib/Transforms/Utils/Debugify.cpp
+++ llvm/lib/Transforms/Utils/Debugify.cpp
@@ -44,8 +44,9 @@
 
 raw_ostream &dbg() { return Quiet ? nulls() : errs(); }
 
-uint64_t getAllocSizeInBits(Module &M, Type *Ty) {
-  return Ty->isSized() ? M.getDataLayout().getTypeAllocSizeInBits(Ty) : 0;
+TypeSize getAllocSizeInBits(Module &M, Type *Ty) {
+  return Ty->isSized() ? M.getDataLayout().getTypeAllocSizeInBits(Ty)
+   : TypeSize::getFixed(0);
 }
 
 bool isFunctionSkipped(Function &F) {
@@ -276,7 +277,7 @@
 return false;
 
   Type *Ty = V->getType();
-  uint64_t ValueOperandSize = getAllocSizeInBits(M, Ty);
+  TypeSize ValueOperandSize = getAllocSizeInBits(M, Ty);
   Optional DbgVarSize = DVI->getFragmentSizeInBits();
   if (!ValueOperandSize || !DbgVarSize)
 return false;
@@ -285,7 +286,7 @@
   if (Ty->isIntegerTy()) {
 auto Signedness = DVI->getVariable()->getSignedness();
 if (Signedness && *Signedness == DIBasicType::Signedness::Signed)
-  HasBadSize = ValueOperandSize < *DbgVarSize;
+  HasBadSize = ValueOperandSize.getFixedSize() < *DbgVarSize;
   } else {
 HasBadSize = ValueOperandSize != *DbgVarSize;
   }
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D91806: [SVE] Remove warning from debug info on scalable vector.

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 308964.
joechrisellis added a comment.

Address @sdesmalen's comments.

- Update commit message to better reflect the changes in this patch.
- Rename `debug-declare-no-warnings-on-scalable-vectors.ll` to 
`dbg-info-scalable-typesize-warning.ll`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91806/new/

https://reviews.llvm.org/D91806

Files:
  llvm/lib/Transforms/Utils/Debugify.cpp
  llvm/lib/Transforms/Utils/Local.cpp
  llvm/test/Transforms/InstCombine/dbg-info-scalable-typesize-warning.ll

Index: llvm/test/Transforms/InstCombine/dbg-info-scalable-typesize-warning.ll
===
--- /dev/null
+++ llvm/test/Transforms/InstCombine/dbg-info-scalable-typesize-warning.ll
@@ -0,0 +1,36 @@
+; RUN: opt -mtriple aarch64-gnu-linux -mattr=+sve -instcombine -S < %s 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; This test is defending against a TypeSize warning raised in the method
+; `valueCoversEntireFragment` in Local.cpp because of an implicit cast from
+; `TypeSize` to `uint64_t`. This particular TypeSize warning only occurred when
+; debug info was available.
+
+; If this check fails please read
+; clang/test/CodeGen/aarch64-sve-intrinsics/README for instructions on
+; how to resolve it.
+
+; WARN-NOT: warning: {{.*}}TypeSize is not scalable
+
+; CHECK-LABEL: @debug_local_scalable(
+define  @debug_local_scalable( %tostore) {
+  %vx = alloca , align 16
+  call void @llvm.dbg.declare(metadata * %vx, metadata !3, metadata !DIExpression()), !dbg !5
+  store  %tostore, * %vx, align 16
+  %ret = call  @f(* %vx)
+  ret  %ret
+}
+
+declare  @f(*)
+
+; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
+declare void @llvm.dbg.declare(metadata, metadata, metadata)
+
+!llvm.module.flags = !{!2}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1)
+!1 = !DIFile(filename: "/tmp/test.c", directory: "/tmp/")
+!2 = !{i32 2, !"Debug Info Version", i32 3}
+!3 = !DILocalVariable(scope: !4)
+!4 = distinct !DISubprogram(unit: !0)
+!5 = !DILocation(scope: !4)
Index: llvm/lib/Transforms/Utils/Local.cpp
===
--- llvm/lib/Transforms/Utils/Local.cpp
+++ llvm/lib/Transforms/Utils/Local.cpp
@@ -1368,16 +1368,22 @@
 /// least n bits.
 static bool valueCoversEntireFragment(Type *ValTy, DbgVariableIntrinsic *DII) {
   const DataLayout &DL = DII->getModule()->getDataLayout();
-  uint64_t ValueSize = DL.getTypeAllocSizeInBits(ValTy);
-  if (auto FragmentSize = DII->getFragmentSizeInBits())
-return ValueSize >= *FragmentSize;
+  TypeSize ValueSize = DL.getTypeAllocSizeInBits(ValTy);
+  if (Optional FragmentSize = DII->getFragmentSizeInBits()) {
+assert(!ValueSize.isScalable() &&
+   "Fragments don't work on scalable types.");
+return ValueSize.getFixedSize() >= *FragmentSize;
+  }
   // We can't always calculate the size of the DI variable (e.g. if it is a
   // VLA). Try to use the size of the alloca that the dbg intrinsic describes
   // intead.
   if (DII->isAddressOfVariable())
 if (auto *AI = dyn_cast_or_null(DII->getVariableLocation()))
-  if (auto FragmentSize = AI->getAllocationSizeInBits(DL))
-return ValueSize >= *FragmentSize;
+  if (Optional FragmentSize = AI->getAllocationSizeInBits(DL)) {
+assert(ValueSize.isScalable() == FragmentSize->isScalable() &&
+   "Both sizes should agree on the scalable flag.");
+return TypeSize::isKnownGE(ValueSize, *FragmentSize);
+  }
   // Could not determine size of variable. Conservatively return false.
   return false;
 }
Index: llvm/lib/Transforms/Utils/Debugify.cpp
===
--- llvm/lib/Transforms/Utils/Debugify.cpp
+++ llvm/lib/Transforms/Utils/Debugify.cpp
@@ -44,8 +44,9 @@
 
 raw_ostream &dbg() { return Quiet ? nulls() : errs(); }
 
-uint64_t getAllocSizeInBits(Module &M, Type *Ty) {
-  return Ty->isSized() ? M.getDataLayout().getTypeAllocSizeInBits(Ty) : 0;
+TypeSize getAllocSizeInBits(Module &M, Type *Ty) {
+  return Ty->isSized() ? M.getDataLayout().getTypeAllocSizeInBits(Ty)
+   : TypeSize::getFixed(0);
 }
 
 bool isFunctionSkipped(Function &F) {
@@ -276,7 +277,7 @@
 return false;
 
   Type *Ty = V->getType();
-  uint64_t ValueOperandSize = getAllocSizeInBits(M, Ty);
+  TypeSize ValueOperandSize = getAllocSizeInBits(M, Ty);
   Optional DbgVarSize = DVI->getFragmentSizeInBits();
   if (!ValueOperandSize || !DbgVarSize)
 return false;
@@ -285,7 +286,7 @@
   if (Ty->isIntegerTy()) {
 auto Signedness = DVI->getVariable()->getSignedness();
 if (Signedness && *Signedness == DIBasicType::Signedness::Signed)
-  HasBadSize = ValueOperandSize < *DbgVarSize;
+  HasBadSize = ValueOperandSize.getFixedSize() < *DbgVarSize;
   } else {
 HasBadSize = Valu

[PATCH] D92761: [clang][AArch64][SVE] Avoid going through memory for VLAT <-> VLST casts

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis created this revision.
joechrisellis added reviewers: peterwaller-arm, DavidTruby.
Herald added subscribers: psnobl, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
joechrisellis requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This change makes use of the llvm.vector.extract intrinsic to avoid
going through memory when performing bitcasts between vector-length
agnostic types and vector-length specific types.

Depends on D91362 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92761

Files:
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
  llvm/include/llvm/IR/IRBuilder.h

Index: llvm/include/llvm/IR/IRBuilder.h
===
--- llvm/include/llvm/IR/IRBuilder.h
+++ llvm/include/llvm/IR/IRBuilder.h
@@ -919,6 +919,20 @@
 return CreateBinaryIntrinsic(Intrinsic::maximum, LHS, RHS, nullptr, Name);
   }
 
+  CallInst *CreateExtractVector(Type *DstType, Value *SrcVec, Value *Idx,
+const Twine &Name = "") {
+return CreateIntrinsic(Intrinsic::experimental_vector_extract,
+   {DstType, SrcVec->getType()}, {SrcVec, Idx}, nullptr,
+   Name);
+  }
+
+  CallInst *CreateInsertVector(Type *DstType, Value *SrcVec, Value *SubVec,
+   Value *Idx, const Twine &Name = "") {
+return CreateIntrinsic(Intrinsic::experimental_vector_insert,
+   {DstType, SubVec->getType()}, {SrcVec, SubVec, Idx},
+   nullptr, Name);
+  }
+
 private:
   /// Create a call to a masked intrinsic with given Id.
   CallInst *CreateMaskedIntrinsic(Intrinsic::ID Id, ArrayRef Ops,
Index: clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
@@ -21,40 +21,28 @@
 
 // CHECK-128-LABEL: @write_global_i64(
 // CHECK-128-NEXT:  entry:
-// CHECK-128-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-128-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-128-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <2 x i64>*
-// CHECK-128-NEXT:[[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[TMP0]], align 16, [[TBAA10:!tbaa !.*]]
-// CHECK-128-NEXT:store <2 x i64> [[TMP1]], <2 x i64>* @global_i64, align 16, [[TBAA10]]
+// CHECK-128-NEXT:[[CASTFIXEDSVE:%.*]] = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64( [[V:%.*]], i64 0)
+// CHECK-128-NEXT:store <2 x i64> [[CASTFIXEDSVE]], <2 x i64>* @global_i64, align 16, [[TBAA6:!tbaa !.*]]
 // CHECK-128-NEXT:ret void
 //
 // CHECK-512-LABEL: @write_global_i64(
 // CHECK-512-NEXT:  entry:
-// CHECK-512-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-512-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-512-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <8 x i64>*
-// CHECK-512-NEXT:[[TMP1:%.*]] = load <8 x i64>, <8 x i64>* [[TMP0]], align 16, [[TBAA10:!tbaa !.*]]
-// CHECK-512-NEXT:store <8 x i64> [[TMP1]], <8 x i64>* @global_i64, align 16, [[TBAA10]]
+// CHECK-512-NEXT:[[CASTFIXEDSVE:%.*]] = call <8 x i64> @llvm.experimental.vector.extract.v8i64.nxv2i64( [[V:%.*]], i64 0)
+// CHECK-512-NEXT:store <8 x i64> [[CASTFIXEDSVE]], <8 x i64>* @global_i64, align 16, [[TBAA6:!tbaa !.*]]
 // CHECK-512-NEXT:ret void
 //
 void write_global_i64(svint64_t v) { global_i64 = v; }
 
 // CHECK-128-LABEL: @write_global_bf16(
 // CHECK-128-NEXT:  entry:
-// CHECK-128-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-128-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA11:!tbaa !.*]]
-// CHECK-128-NEXT:[[TMP0:%.*]] = bitcast * [[V_ADDR]] to <8 x bfloat>*
-// CHECK-128-NEXT:[[TMP1:%.*]] = load <8 x bfloat>, <8 x bfloat>* [[TMP0]], align 16, [[TBAA10]]
-// CHECK-128-NEXT:store <8 x bfloat> [[TMP1]], <8 x bfloat>* @global_bf16, align 16, [[TBAA10]]
+// CHECK-128-NEXT:[[CASTFIXEDSVE:%.*]] = call <8 x bfloat> @llvm.experimental.vector.extract.v8bf16.nxv8bf16( [[V:%.*]], i64 0)
+// CHECK-128-NEXT:store <8 x bfloat> [[CASTFIXEDSVE]], <8 x bfloat>* @global_bf16, align 16, [[TBAA6]]
 // CHECK-128-NEXT:ret void
 //
 // CHECK-512-LABEL: @write_global_bf16(
 // CHECK-512-NEXT:  entry:
-// CHECK-512-NEXT:[[V_ADDR:%.*]] = alloca , align 16
-// CHECK-512-NEXT:store  [[V:%.*]], * [[V_ADDR]], align 16, [[TBAA11:!tbaa !.*]]
-// CH

[PATCH] D92762: [clang][AArch64][SVE] Avoid going through memory for coerced VLST arguments

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis created this revision.
joechrisellis added reviewers: peterwaller-arm, DavidTruby.
Herald added subscribers: psnobl, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
joechrisellis requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

VLST arguments are coerced to VLATs at the function boundary for
consistency with the VLAT ABI. They are then bitcast back to VLSTs in
the function prolog. Previously, this conversion is done through memory.
With the introduction of the llvm.vector.{insert,extract} intrinsic, we
can avoid going through memory here.

Depends on D92761 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92762

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c

Index: clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
@@ -13,11 +13,8 @@
 
 // CHECK-LABEL: @to_svint32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <16 x i32>, <16 x i32>* [[TYPE]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TYPE1]], i64 0)
+// CHECK-NEXT:[[TYPE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[TYPE_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TYPE]], i64 0)
 // CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 svint32_t to_svint32_t(fixed_int32_t type) {
@@ -39,11 +36,8 @@
 
 // CHECK-LABEL: @to_svfloat64_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <8 x double>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x double>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x double>, <8 x double>* [[TYPE]], align 16, [[TBAA6]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 x double> [[TYPE1]], i64 0)
+// CHECK-NEXT:[[TYPE:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64( [[TYPE_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 x double> [[TYPE]], i64 0)
 // CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 svfloat64_t to_svfloat64_t(fixed_float64_t type) {
@@ -65,15 +59,12 @@
 
 // CHECK-LABEL: @to_svbool_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <8 x i8>, align 16
 // CHECK-NEXT:[[TYPE_ADDR:%.*]] = alloca <8 x i8>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x i8>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x i8>, <8 x i8>* [[TYPE]], align 16, [[TBAA6]]
-// CHECK-NEXT:store <8 x i8> [[TYPE1]], <8 x i8>* [[TYPE_ADDR]], align 16, [[TBAA6]]
-// CHECK-NEXT:[[TMP1:%.*]] = bitcast <8 x i8>* [[TYPE_ADDR]] to *
-// CHECK-NEXT:[[TMP2:%.*]] = load , * [[TMP1]], align 16, [[TBAA6]]
-// CHECK-NEXT:ret  [[TMP2]]
+// CHECK-NEXT:[[TYPE:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv16i1( [[TYPE_COERCE:%.*]], i64 0)
+// CHECK-NEXT:store <8 x i8> [[TYPE]], <8 x i8>* [[TYPE_ADDR]], align 16, [[TBAA6:!tbaa !.*]]
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x i8>* [[TYPE_ADDR]] to *
+// CHECK-NEXT:[[TMP1:%.*]] = load , * [[TMP0]], align 16, [[TBAA6]]
+// CHECK-NEXT:ret  [[TMP1]]
 //
 svbool_t to_svbool_t(fixed_bool_t type) {
   return type;
@@ -130,11 +121,8 @@
 
 // CHECK-LABEL: @from_fixed_int32_t__to_gnu_int32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <16 x i32>, <16 x i32>* [[TYPE]], align 16, [[TBAA6]]
-// CHECK-NEXT:store <16 x i32> [[TYPE1]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
+// CHECK-NEXT:[[TYPE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[TYPE_COERCE:%.*]], i64 0)
+// CHECK-NEXT:store <16 x i32> [[TYPE]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
 // CHECK-NEXT:ret void
 //
 gnu_int32_t from_fixed_int32_t__to_gnu_int32_t(fix

[PATCH] D101986: [InstSimplify] Remove redundant {insert,extract}_vector intrinsic chains

[Joe Ellis via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2ed7db0d206b: [InstSimplify] Remove redundant 
{insert,extract}_vector intrinsic chains (authored by joechrisellis).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101986/new/

https://reviews.llvm.org/D101986

Files:
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
  llvm/lib/Analysis/InstructionSimplify.cpp
  llvm/test/Transforms/InstSimplify/extract-vector.ll
  llvm/test/Transforms/InstSimplify/insert-vector.ll

Index: llvm/test/Transforms/InstSimplify/insert-vector.ll
===
--- /dev/null
+++ llvm/test/Transforms/InstSimplify/insert-vector.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instsimplify -S | FileCheck %s
+
+define  @redundant_extract_insert_chain( %pg,  %x) {
+; CHECK-LABEL: @redundant_extract_insert_chain(
+; CHECK-NEXT:ret  [[X:%.*]]
+;
+  %extracted = call <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv16i8( %x, i64 0)
+  %inserted = call  @llvm.experimental.vector.insert.nxv16i8.v32i8( undef, <32 x i8> %extracted, i64 0)
+  ret  %inserted
+}
+
+define  @non_redundant_extract_insert_chain( %pg,  %x) {
+; CHECK-LABEL: @non_redundant_extract_insert_chain(
+; CHECK-NEXT:[[EXTRACTED:%.*]] = call <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv32i8( [[X:%.*]], i64 0)
+; CHECK-NEXT:[[INSERTED:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v32i8( undef, <32 x i8> [[EXTRACTED]], i64 0)
+; CHECK-NEXT:ret  [[INSERTED]]
+;
+  %extracted = call <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv32i8( %x, i64 0)
+  %inserted = call  @llvm.experimental.vector.insert.nxv16i8.v32i8( undef, <32 x i8> %extracted, i64 0)
+  ret  %inserted
+}
+
+declare <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv16i8(, i64)
+declare <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv32i8(, i64)
+declare  @llvm.experimental.vector.insert.nxv16i8.v32i8(, <32 x i8>, i64)
Index: llvm/test/Transforms/InstSimplify/extract-vector.ll
===
--- /dev/null
+++ llvm/test/Transforms/InstSimplify/extract-vector.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instsimplify -S | FileCheck %s
+
+define <16 x i8> @redundant_insert_extract_chain(<16 x i8> %x) {
+; CHECK-LABEL: @redundant_insert_extract_chain(
+; CHECK-NEXT:ret <16 x i8> [[X:%.*]]
+;
+  %inserted = call  @llvm.experimental.vector.insert.nxv32i8.v16i8( undef, <16 x i8> %x, i64 0)
+  %extracted = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv32i8( %inserted, i64 0)
+  ret <16 x i8> %extracted
+}
+
+define <8 x i8> @non_redundant_insert_extract_chain(<16 x i8> %x) {
+; CHECK-LABEL: @non_redundant_insert_extract_chain(
+; CHECK-NEXT:[[INSERTED:%.*]] = call  @llvm.experimental.vector.insert.nxv32i8.v16i8( undef, <16 x i8> [[X:%.*]], i64 0)
+; CHECK-NEXT:[[EXTRACTED:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv32i8( [[INSERTED]], i64 0)
+; CHECK-NEXT:ret <8 x i8> [[EXTRACTED]]
+;
+  %inserted = call  @llvm.experimental.vector.insert.nxv32i8.v16i8( undef, <16 x i8> %x, i64 0)
+  %extracted = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv32i8( %inserted, i64 0)
+  ret <8 x i8> %extracted
+}
+
+declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv32i8(, i64)
+declare <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv32i8(, i64)
+declare  @llvm.experimental.vector.insert.nxv32i8.v16i8(, <16 x i8>, i64)
Index: llvm/lib/Analysis/InstructionSimplify.cpp
===
--- llvm/lib/Analysis/InstructionSimplify.cpp
+++ llvm/lib/Analysis/InstructionSimplify.cpp
@@ -5625,6 +5625,19 @@
 
 break;
   }
+  case Intrinsic::experimental_vector_extract: {
+Type *ReturnType = F->getReturnType();
+
+// (extract_vector (insert_vector _, X, 0), 0) -> X
+unsigned IdxN = cast(Op1)->getZExtValue();
+Value *X = nullptr;
+if (match(Op0, m_Intrinsic(
+   m_Value(), m_Value(X), m_Zero())) &&
+IdxN == 0 && X->getType() == ReturnType)
+  return X;
+
+break;
+  }
   default:
 break;
   }
@@ -5720,6 +5733,21 @@
 
 return nullptr;
   }
+  case Intrinsic::experimental_vector_insert: {
+Value *SubVec = Call->getArgOperand(1);
+Value *Idx = Call->getArgOperand(2);
+Type *ReturnType = F->getReturnType();
+
+// (insert_vector _, (extract_vector X, 0), 0) -> X
+unsigned IdxN = cast(Idx)->getZExtValue();
+Value *X = nullptr;
+if (match(SubVec, m_Intrinsic(
+  m_Value(X), m_Zero())) &&
+IdxN == 0 && X->getType() == ReturnType)
+  ret

[PATCH] D96852: [clang][SVE] Remove inline keyword from arm_sve.h

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis created this revision.
joechrisellis added reviewers: DavidTruby, peterwaller-arm, paulwalker-arm, 
bsmith.
Herald added subscribers: psnobl, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
joechrisellis requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

The inline keyword is not defined in the C89 standard, so source files
that include arm_sve.h will fail compilation if -std=c89 is specified.
We already use the __always_inline__ function attribute so the inline
keyword here is redundant anyway.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D96852

Files:
  clang/utils/TableGen/SveEmitter.cpp


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1201,7 +1201,7 @@
   OS << "};\n\n";
 
   OS << "/* Function attributes */\n";
-  OS << "#define __aio static inline __attribute__((__always_inline__, "
+  OS << "#define __aio static __attribute__((__always_inline__, "
 "__nodebug__, __overloadable__))\n\n";
 
   // Add reinterpret functions.


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1201,7 +1201,7 @@
   OS << "};\n\n";
 
   OS << "/* Function attributes */\n";
-  OS << "#define __aio static inline __attribute__((__always_inline__, "
+  OS << "#define __aio static __attribute__((__always_inline__, "
 "__nodebug__, __overloadable__))\n\n";
 
   // Add reinterpret functions.
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D96852: [clang][SVE] Remove inline keyword from arm_sve.h

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis planned changes to this revision.
joechrisellis added a comment.

Speaking to @DavidTruby about this, it appears that this fix is insufficient -- 
`inline` has important semantic meaning in C++ that means that we can't simply 
omit the keyword here.

The `inline` keyword bypasses the one-definition rule. If we have a function 
defined in a header that isn't marked `inline`, and you include that header in 
two different source files, then your program is ill formed because it contains 
2 definitions of that function. So we have to keep it for C++.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96852/new/

https://reviews.llvm.org/D96852

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D96852: [clang][SVE] Remove inline keyword from arm_sve.h

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis added a comment.

> That makes sense and suggests we're missing some additional C++ testing?

Agreed -- this passes all tests at the moment, so we can do better test-wise. 
The error to do with the one definition rule would crop up at link time, 
though, so we'd need at least two compilation units to validate this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96852/new/

https://reviews.llvm.org/D96852

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D96852: [clang][SVE] Remove inline keyword from arm_sve.h

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 324311.
joechrisellis added a comment.
This revision is now accepted and ready to land.

Use __inline__ instead of inline.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96852/new/

https://reviews.llvm.org/D96852

Files:
  clang/utils/TableGen/SveEmitter.cpp


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1201,7 +1201,7 @@
   OS << "};\n\n";
 
   OS << "/* Function attributes */\n";
-  OS << "#define __aio static inline __attribute__((__always_inline__, "
+  OS << "#define __aio static __inline__ __attribute__((__always_inline__, "
 "__nodebug__, __overloadable__))\n\n";
 
   // Add reinterpret functions.


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1201,7 +1201,7 @@
   OS << "};\n\n";
 
   OS << "/* Function attributes */\n";
-  OS << "#define __aio static inline __attribute__((__always_inline__, "
+  OS << "#define __aio static __inline__ __attribute__((__always_inline__, "
 "__nodebug__, __overloadable__))\n\n";
 
   // Add reinterpret functions.
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D96852: [clang][SVE] Use __inline__ instead of inline in arm_sve.h

[Joe Ellis via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1f2122c9b046: [clang][SVE] Use __inline__ instead of inline 
in arm_sve.h (authored by joechrisellis).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96852/new/

https://reviews.llvm.org/D96852

Files:
  clang/utils/TableGen/SveEmitter.cpp


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1201,7 +1201,7 @@
   OS << "};\n\n";
 
   OS << "/* Function attributes */\n";
-  OS << "#define __aio static inline __attribute__((__always_inline__, "
+  OS << "#define __aio static __inline__ __attribute__((__always_inline__, "
 "__nodebug__, __overloadable__))\n\n";
 
   // Add reinterpret functions.


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1201,7 +1201,7 @@
   OS << "};\n\n";
 
   OS << "/* Function attributes */\n";
-  OS << "#define __aio static inline __attribute__((__always_inline__, "
+  OS << "#define __aio static __inline__ __attribute__((__always_inline__, "
 "__nodebug__, __overloadable__))\n\n";
 
   // Add reinterpret functions.
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D97053: [clang][SVE] Don't warn on vector to sizeless builtin implicit conversion

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis created this revision.
joechrisellis added reviewers: c-rhodes, bsmith.
Herald added subscribers: psnobl, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
joechrisellis requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

This commit prevents warnings from -Wconversion when a clang vector type
is implicitly converted to a sizeless builtin type -- for example, when
implicitly converting a fixed-predicate to a scalable predicate.

The code below:

  1#include 
  2
  3#define N __ARM_FEATURE_SVE_BITS
  4#define FIXED_ATTR __attribute__((arm_sve_vector_bits (N)))
  5typedef svbool_t fixed_svbool_t FIXED_ATTR;
  6
  7inline fixed_svbool_t foo(fixed_svbool_t p) {
  8  return svnot_z(svptrue_b64(), p);
  9}

would previously raise this warning:

  warning: implicit conversion turns vector to scalar: \
  'fixed_svbool_t' (vector of 8 'unsigned char' values) to 'svbool_t' \
  (aka '__SVBool_t') [-Wconversion]

Note that many cases of these implicit conversions were already
permitted because many functions inside arm_sve.h are spawned via
preprocessor macros, and the call to isInSystemMacro would cover us in
this case. This commit fixes the remaining cases.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97053

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/Sema/aarch64-fixed-vector-to-scalable-implicit-conversion.c


Index: clang/test/Sema/aarch64-fixed-vector-to-scalable-implicit-conversion.c
===
--- /dev/null
+++ clang/test/Sema/aarch64-fixed-vector-to-scalable-implicit-conversion.c
@@ -0,0 +1,32 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \
+// RUN: -msve-vector-bits=512 -Wconversion -fallow-half-arguments-and-returns \
+// RUN: -o /dev/null %s 2>&1 | FileCheck %s -allow-empty
+
+// CHECK-NOT: warning
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svbool_t fixed_svbool_t FIXED_ATTR;
+
+fixed_svbool_t check_svnot(fixed_svbool_t p) {
+  return svnot_z(svptrue_b64(), p);
+}
+
+fixed_svbool_t check_svorr(fixed_svbool_t p1, fixed_svbool_t p2) {
+  return svorr_z(svptrue_b64(), p1, p2);
+}
+
+fixed_svbool_t check_svorn(fixed_svbool_t p1, fixed_svbool_t p2) {
+  return svorn_z(svptrue_b64(), p1, p2);
+}
+
+fixed_svbool_t check_svand(fixed_svbool_t p1, fixed_svbool_t p2) {
+  return svand_z(svptrue_b64(), p1, p2);
+}
+
+fixed_svbool_t check_svnand(fixed_svbool_t p1, fixed_svbool_t p2) {
+  return svnand_z(svptrue_b64(), p1, p2);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -12052,6 +12052,9 @@
 
   // Strip vector types.
   if (isa(Source)) {
+// Converting from a vector to a sizeless builtin type is fine.
+if (Target->isSizelessBuiltinType())
+  return;
 if (!isa(Target)) {
   if (S.SourceMgr.isInSystemMacro(CC))
 return;


Index: clang/test/Sema/aarch64-fixed-vector-to-scalable-implicit-conversion.c
===
--- /dev/null
+++ clang/test/Sema/aarch64-fixed-vector-to-scalable-implicit-conversion.c
@@ -0,0 +1,32 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \
+// RUN: -msve-vector-bits=512 -Wconversion -fallow-half-arguments-and-returns \
+// RUN: -o /dev/null %s 2>&1 | FileCheck %s -allow-empty
+
+// CHECK-NOT: warning
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N)))
+
+typedef svbool_t fixed_svbool_t FIXED_ATTR;
+
+fixed_svbool_t check_svnot(fixed_svbool_t p) {
+  return svnot_z(svptrue_b64(), p);
+}
+
+fixed_svbool_t check_svorr(fixed_svbool_t p1, fixed_svbool_t p2) {
+  return svorr_z(svptrue_b64(), p1, p2);
+}
+
+fixed_svbool_t check_svorn(fixed_svbool_t p1, fixed_svbool_t p2) {
+  return svorn_z(svptrue_b64(), p1, p2);
+}
+
+fixed_svbool_t check_svand(fixed_svbool_t p1, fixed_svbool_t p2) {
+  return svand_z(svptrue_b64(), p1, p2);
+}
+
+fixed_svbool_t check_svnand(fixed_svbool_t p1, fixed_svbool_t p2) {
+  return svnand_z(svptrue_b64(), p1, p2);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -12052,6 +12052,9 @@
 
   // Strip vector types.
   if (isa(Source)) {
+// Converting from a vector to a sizeless builtin type is fine.
+if (Target->isSizelessBuiltinType())
+  return;
 if (!isa(Target)) {
   if (S.SourceMgr.isInSystemMacro(CC))
 return;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D97053: [clang][SVE] Don't warn on vector to sizeless builtin implicit conversion

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis added inline comments.



Comment at: 
clang/test/Sema/aarch64-fixed-vector-to-scalable-implicit-conversion.c:1-32
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \
+// RUN: -msve-vector-bits=512 -Wconversion -fallow-half-arguments-and-returns \
+// RUN: -o /dev/null %s 2>&1 | FileCheck %s -allow-empty
+
+// CHECK-NOT: warning
+
+#include 

c-rhodes wrote:
> I wonder if we can just add `-Wconversion` to the existing Sema tests?
> * clang/test/Sema/attr-arm-sve-vector-bits.c
> * clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
> 
`clang/test/Sema/attr-arm-sve-vector-bits.c` contains a lot of `// 
expected-error ...` and such, so I'm reluctant to make changes to that because 
it seems a little weird to mix up expected errors and non-expected warnings.

I suppose we could cat this test into `attr-arm-sve-vector-bits.cpp`, though, 
if you would prefer? 🙂 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97053/new/

https://reviews.llvm.org/D97053

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D97053: [clang][SVE] Don't warn on vector to sizeless builtin implicit conversion

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 325410.
joechrisellis added a comment.

Address comments.

- @c-rhodes: remove test; it is probably not necessary.
- @craig.topper: add better constraints for when we do/don't bail out.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97053/new/

https://reviews.llvm.org/D97053

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp


Index: clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
===
--- clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
+++ clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 
-msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 
-msve-vector-bits=512 -fallow-half-arguments-and-returns -Wconversion %s
 // expected-no-diagnostics
 
 #include 
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -12051,7 +12051,16 @@
 checkObjCDictionaryLiteral(S, QualType(Target, 0), DictionaryLiteral);
 
   // Strip vector types.
-  if (isa(Source)) {
+  if (auto *SourceVT = dyn_cast(Source)) {
+if (Target->isSizelessBuiltinType()) {
+  auto SourceVectorKind = SourceVT->getVectorKind();
+  if (SourceVectorKind == VectorType::SveFixedLengthDataVector ||
+  SourceVectorKind == VectorType::SveFixedLengthPredicateVector ||
+  (SourceVectorKind == VectorType::GenericVector &&
+   S.Context.getTypeSize(Source) == S.getLangOpts().ArmSveVectorBits))
+return;
+}
+
 if (!isa(Target)) {
   if (S.SourceMgr.isInSystemMacro(CC))
 return;


Index: clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
===
--- clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
+++ clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 -msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 -msve-vector-bits=512 -fallow-half-arguments-and-returns -Wconversion %s
 // expected-no-diagnostics
 
 #include 
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -12051,7 +12051,16 @@
 checkObjCDictionaryLiteral(S, QualType(Target, 0), DictionaryLiteral);
 
   // Strip vector types.
-  if (isa(Source)) {
+  if (auto *SourceVT = dyn_cast(Source)) {
+if (Target->isSizelessBuiltinType()) {
+  auto SourceVectorKind = SourceVT->getVectorKind();
+  if (SourceVectorKind == VectorType::SveFixedLengthDataVector ||
+  SourceVectorKind == VectorType::SveFixedLengthPredicateVector ||
+  (SourceVectorKind == VectorType::GenericVector &&
+   S.Context.getTypeSize(Source) == S.getLangOpts().ArmSveVectorBits))
+return;
+}
+
 if (!isa(Target)) {
   if (S.SourceMgr.isInSystemMacro(CC))
 return;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D97053: [clang][SVE] Don't warn on vector to sizeless builtin implicit conversion

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 325461.
joechrisellis marked an inline comment as done.
joechrisellis added a comment.

Address @c-rhodes's comment.

- use `isVLSTBuiltinType` instead of `isSizelessBuiltinType`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97053/new/

https://reviews.llvm.org/D97053

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp


Index: clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
===
--- clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
+++ clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 
-msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 
-msve-vector-bits=512 -fallow-half-arguments-and-returns -Wconversion %s
 // expected-no-diagnostics
 
 #include 
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -12051,7 +12051,16 @@
 checkObjCDictionaryLiteral(S, QualType(Target, 0), DictionaryLiteral);
 
   // Strip vector types.
-  if (isa(Source)) {
+  if (auto *SourceVT = dyn_cast(Source)) {
+if (Target->isVLSTBuiltinType()) {
+  auto SourceVectorKind = SourceVT->getVectorKind();
+  if (SourceVectorKind == VectorType::SveFixedLengthDataVector ||
+  SourceVectorKind == VectorType::SveFixedLengthPredicateVector ||
+  (SourceVectorKind == VectorType::GenericVector &&
+   S.Context.getTypeSize(Source) == S.getLangOpts().ArmSveVectorBits))
+return;
+}
+
 if (!isa(Target)) {
   if (S.SourceMgr.isInSystemMacro(CC))
 return;


Index: clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
===
--- clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
+++ clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 -msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 -msve-vector-bits=512 -fallow-half-arguments-and-returns -Wconversion %s
 // expected-no-diagnostics
 
 #include 
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -12051,7 +12051,16 @@
 checkObjCDictionaryLiteral(S, QualType(Target, 0), DictionaryLiteral);
 
   // Strip vector types.
-  if (isa(Source)) {
+  if (auto *SourceVT = dyn_cast(Source)) {
+if (Target->isVLSTBuiltinType()) {
+  auto SourceVectorKind = SourceVT->getVectorKind();
+  if (SourceVectorKind == VectorType::SveFixedLengthDataVector ||
+  SourceVectorKind == VectorType::SveFixedLengthPredicateVector ||
+  (SourceVectorKind == VectorType::GenericVector &&
+   S.Context.getTypeSize(Source) == S.getLangOpts().ArmSveVectorBits))
+return;
+}
+
 if (!isa(Target)) {
   if (S.SourceMgr.isInSystemMacro(CC))
 return;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D97053: [clang][SVE] Don't warn on vector to sizeless builtin implicit conversion

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:12055
+  if (auto *SourceVT = dyn_cast(Source)) {
+if (Target->isSizelessBuiltinType()) {
+  auto SourceVectorKind = SourceVT->getVectorKind();

c-rhodes wrote:
> I suppose we could tighten this further by replacing `isSizelessBuiltinType` 
> with `isVLSTBuiltinType`
Good shout -- thanks. :smile:


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97053/new/

https://reviews.llvm.org/D97053

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D97053: [clang][SVE] Don't warn on vector to sizeless builtin implicit conversion

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 325749.
joechrisellis marked an inline comment as done.
joechrisellis added a comment.

Address linter comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97053/new/

https://reviews.llvm.org/D97053

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp


Index: clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
===
--- clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
+++ clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 
-msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 
-msve-vector-bits=512 -fallow-half-arguments-and-returns -Wconversion %s
 // expected-no-diagnostics
 
 #include 
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -12051,7 +12051,16 @@
 checkObjCDictionaryLiteral(S, QualType(Target, 0), DictionaryLiteral);
 
   // Strip vector types.
-  if (isa(Source)) {
+  if (const auto *SourceVT = dyn_cast(Source)) {
+if (Target->isVLSTBuiltinType()) {
+  auto SourceVectorKind = SourceVT->getVectorKind();
+  if (SourceVectorKind == VectorType::SveFixedLengthDataVector ||
+  SourceVectorKind == VectorType::SveFixedLengthPredicateVector ||
+  (SourceVectorKind == VectorType::GenericVector &&
+   S.Context.getTypeSize(Source) == S.getLangOpts().ArmSveVectorBits))
+return;
+}
+
 if (!isa(Target)) {
   if (S.SourceMgr.isInSystemMacro(CC))
 return;


Index: clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
===
--- clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
+++ clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 -msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 -msve-vector-bits=512 -fallow-half-arguments-and-returns -Wconversion %s
 // expected-no-diagnostics
 
 #include 
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -12051,7 +12051,16 @@
 checkObjCDictionaryLiteral(S, QualType(Target, 0), DictionaryLiteral);
 
   // Strip vector types.
-  if (isa(Source)) {
+  if (const auto *SourceVT = dyn_cast(Source)) {
+if (Target->isVLSTBuiltinType()) {
+  auto SourceVectorKind = SourceVT->getVectorKind();
+  if (SourceVectorKind == VectorType::SveFixedLengthDataVector ||
+  SourceVectorKind == VectorType::SveFixedLengthPredicateVector ||
+  (SourceVectorKind == VectorType::GenericVector &&
+   S.Context.getTypeSize(Source) == S.getLangOpts().ArmSveVectorBits))
+return;
+}
+
 if (!isa(Target)) {
   if (S.SourceMgr.isInSystemMacro(CC))
 return;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D97053: [clang][SVE] Don't warn on vector to sizeless builtin implicit conversion

[Joe Ellis via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1b1b30cf0f7d: [clang][SVE] Don't warn on vector to 
sizeless builtin implicit conversion (authored by joechrisellis).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97053/new/

https://reviews.llvm.org/D97053

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp


Index: clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
===
--- clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
+++ clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 
-msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 
-msve-vector-bits=512 -fallow-half-arguments-and-returns -Wconversion %s
 // expected-no-diagnostics
 
 #include 
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -12051,7 +12051,16 @@
 checkObjCDictionaryLiteral(S, QualType(Target, 0), DictionaryLiteral);
 
   // Strip vector types.
-  if (isa(Source)) {
+  if (const auto *SourceVT = dyn_cast(Source)) {
+if (Target->isVLSTBuiltinType()) {
+  auto SourceVectorKind = SourceVT->getVectorKind();
+  if (SourceVectorKind == VectorType::SveFixedLengthDataVector ||
+  SourceVectorKind == VectorType::SveFixedLengthPredicateVector ||
+  (SourceVectorKind == VectorType::GenericVector &&
+   S.Context.getTypeSize(Source) == S.getLangOpts().ArmSveVectorBits))
+return;
+}
+
 if (!isa(Target)) {
   if (S.SourceMgr.isInSystemMacro(CC))
 return;


Index: clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
===
--- clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
+++ clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 -msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -ffreestanding -fsyntax-only -verify -std=c++11 -msve-vector-bits=512 -fallow-half-arguments-and-returns -Wconversion %s
 // expected-no-diagnostics
 
 #include 
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -12051,7 +12051,16 @@
 checkObjCDictionaryLiteral(S, QualType(Target, 0), DictionaryLiteral);
 
   // Strip vector types.
-  if (isa(Source)) {
+  if (const auto *SourceVT = dyn_cast(Source)) {
+if (Target->isVLSTBuiltinType()) {
+  auto SourceVectorKind = SourceVT->getVectorKind();
+  if (SourceVectorKind == VectorType::SveFixedLengthDataVector ||
+  SourceVectorKind == VectorType::SveFixedLengthPredicateVector ||
+  (SourceVectorKind == VectorType::GenericVector &&
+   S.Context.getTypeSize(Source) == S.getLangOpts().ArmSveVectorBits))
+return;
+}
+
 if (!isa(Target)) {
   if (S.SourceMgr.isInSystemMacro(CC))
 return;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D101986: [InstSimplify] Remove redundant {insert,extract}_vector intrinsic chains

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis created this revision.
joechrisellis added reviewers: bsmith, DavidTruby, peterwaller-arm.
Herald added a subscriber: hiraditya.
joechrisellis requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This commit removes some redundant {insert,extract}_vector intrinsic
chains by implementing the following patterns as instsimplifies:

  (insert_vector _, (extract_vector X, 0), 0) -> X
  (extract_vector (insert_vector _, X, 0), 0) -> X


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101986

Files:
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
  llvm/lib/Analysis/InstructionSimplify.cpp
  llvm/test/Transforms/InstSimplify/extract-vector.ll
  llvm/test/Transforms/InstSimplify/insert-vector.ll

Index: llvm/test/Transforms/InstSimplify/insert-vector.ll
===
--- /dev/null
+++ llvm/test/Transforms/InstSimplify/insert-vector.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instsimplify -S | FileCheck %s
+
+define  @redundant_extract_insert_chain( %pg,  %x) {
+; CHECK-LABEL: @redundant_extract_insert_chain(
+; CHECK-NEXT:ret  [[X:%.*]]
+;
+  %extracted = call <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv16i8( %x, i64 0)
+  %inserted = call  @llvm.experimental.vector.insert.nxv16i8.v32i8( undef, <32 x i8> %extracted, i64 0)
+  ret  %inserted
+}
+
+define  @non_redundant_extract_insert_chain( %pg,  %x) {
+; CHECK-LABEL: @non_redundant_extract_insert_chain(
+; CHECK-NEXT:[[EXTRACTED:%.*]] = call <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv32i8( [[X:%.*]], i64 0)
+; CHECK-NEXT:[[INSERTED:%.*]] = call  @llvm.experimental.vector.insert.nxv16i8.v32i8( undef, <32 x i8> [[EXTRACTED]], i64 0)
+; CHECK-NEXT:ret  [[INSERTED]]
+;
+  %extracted = call <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv32i8( %x, i64 0)
+  %inserted = call  @llvm.experimental.vector.insert.nxv16i8.v32i8( undef, <32 x i8> %extracted, i64 0)
+  ret  %inserted
+}
+
+declare <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv16i8(, i64)
+declare <32 x i8> @llvm.experimental.vector.extract.v32i8.nxv32i8(, i64)
+declare  @llvm.experimental.vector.insert.nxv16i8.v32i8(, <32 x i8>, i64)
Index: llvm/test/Transforms/InstSimplify/extract-vector.ll
===
--- /dev/null
+++ llvm/test/Transforms/InstSimplify/extract-vector.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instsimplify -S | FileCheck %s
+
+define <16 x i8> @redundant_insert_extract_chain(<16 x i8> %x) {
+; CHECK-LABEL: @redundant_insert_extract_chain(
+; CHECK-NEXT:ret <16 x i8> [[X:%.*]]
+;
+  %inserted = call  @llvm.experimental.vector.insert.nxv32i8.v16i8( undef, <16 x i8> %x, i64 0)
+  %extracted = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv32i8( %inserted, i64 0)
+  ret <16 x i8> %extracted
+}
+
+define <8 x i8> @non_redundant_insert_extract_chain(<16 x i8> %x) {
+; CHECK-LABEL: @non_redundant_insert_extract_chain(
+; CHECK-NEXT:[[INSERTED:%.*]] = call  @llvm.experimental.vector.insert.nxv32i8.v16i8( undef, <16 x i8> [[X:%.*]], i64 0)
+; CHECK-NEXT:[[EXTRACTED:%.*]] = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv32i8( [[INSERTED]], i64 0)
+; CHECK-NEXT:ret <8 x i8> [[EXTRACTED]]
+;
+  %inserted = call  @llvm.experimental.vector.insert.nxv32i8.v16i8( undef, <16 x i8> %x, i64 0)
+  %extracted = call <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv32i8( %inserted, i64 0)
+  ret <8 x i8> %extracted
+}
+
+declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv32i8(, i64)
+declare <8 x i8> @llvm.experimental.vector.extract.v8i8.nxv32i8(, i64)
+declare  @llvm.experimental.vector.insert.nxv32i8.v16i8(, <16 x i8>, i64)
Index: llvm/lib/Analysis/InstructionSimplify.cpp
===
--- llvm/lib/Analysis/InstructionSimplify.cpp
+++ llvm/lib/Analysis/InstructionSimplify.cpp
@@ -5625,6 +5625,19 @@
 
 break;
   }
+  case Intrinsic::experimental_vector_extract: {
+Type *ReturnType = F->getReturnType();
+
+// (extract_vector (insert_vector _, X, 0), 0) -> X
+unsigned IdxN = cast(Op1)->getZExtValue();
+Value *X = nullptr;
+if (match(Op0, m_Intrinsic(
+   m_Value(), m_Value(X), m_Zero())) &&
+IdxN == 0 && X->getType() == ReturnType)
+  return X;
+
+break;
+  }
   default:
 break;
   }
@@ -5720,6 +5733,21 @@
 
 return nullptr;
   }
+  case Intrinsic::experimental_vector_insert: {
+Value *SubVec = Call->getArgOperand(1);
+Value *Idx = Call->getArgOperand(2);
+Type *ReturnType = F->getReturnType();
+
+// (insert_vector _, (extract_vector X, 0), 0) -> X
+unsigned IdxN = cast(Idx)->get

[PATCH] D92762: [clang][AArch64][SVE] Avoid going through memory for coerced VLST arguments

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 314354.
joechrisellis marked 2 inline comments as done.
joechrisellis added a comment.

Address @c-rhodes's comments.

- Make comment clearer.
- Change structure of the if statements for better readability.
- Drop superfluous `this->`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92762/new/

https://reviews.llvm.org/D92762

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c

Index: clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
@@ -13,11 +13,8 @@
 
 // CHECK-LABEL: @to_svint32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <16 x i32>, <16 x i32>* [[TYPE]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TYPE1]], i64 0)
+// CHECK-NEXT:[[TYPE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TYPE]], i64 0)
 // CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 svint32_t to_svint32_t(fixed_int32_t type) {
@@ -39,11 +36,8 @@
 
 // CHECK-LABEL: @to_svfloat64_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <8 x double>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x double>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x double>, <8 x double>* [[TYPE]], align 16, [[TBAA6]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 x double> [[TYPE1]], i64 0)
+// CHECK-NEXT:[[TYPE:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 x double> [[TYPE]], i64 0)
 // CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 svfloat64_t to_svfloat64_t(fixed_float64_t type) {
@@ -69,7 +63,7 @@
 // CHECK-NEXT:[[TYPE_ADDR:%.*]] = alloca <8 x i8>, align 16
 // CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x i8>* [[TYPE]] to *
 // CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x i8>, <8 x i8>* [[TYPE]], align 16, [[TBAA6]]
+// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x i8>, <8 x i8>* [[TYPE]], align 16, [[TBAA6:!tbaa !.*]]
 // CHECK-NEXT:store <8 x i8> [[TYPE1]], <8 x i8>* [[TYPE_ADDR]], align 16, [[TBAA6]]
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast <8 x i8>* [[TYPE_ADDR]] to *
 // CHECK-NEXT:[[TMP2:%.*]] = load , * [[TMP1]], align 16, [[TBAA6]]
@@ -130,11 +124,8 @@
 
 // CHECK-LABEL: @from_fixed_int32_t__to_gnu_int32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <16 x i32>, <16 x i32>* [[TYPE]], align 16, [[TBAA6]]
-// CHECK-NEXT:store <16 x i32> [[TYPE1]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
+// CHECK-NEXT:[[TYPE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:store <16 x i32> [[TYPE]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
 // CHECK-NEXT:ret void
 //
 gnu_int32_t from_fixed_int32_t__to_gnu_int32_t(fixed_int32_t type) {
Index: clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
@@ -24,17 +24,14 @@
 
 // CHECK-LABEL: @fixed_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[X:%.*]] = alloca <16 x i32>, align 16
 // CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[X]] to *
-// CHECK-NEXT:store  [[X_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[X1:%.*]] = load <16 x i32>, <16 x i32>* [[X]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[X1]], i64 0)
+// CHECK-NEXT:[[X:%.*]] = call <16 x i32>

[PATCH] D92762: [clang][AArch64][SVE] Avoid going through memory for coerced VLST arguments

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 314365.
joechrisellis added a comment.

Address @c-rhodes's comment.

- Use name `castFixedSve` instead of `castScalableSve`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92762/new/

https://reviews.llvm.org/D92762

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c

Index: clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
@@ -13,11 +13,8 @@
 
 // CHECK-LABEL: @to_svint32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <16 x i32>, <16 x i32>* [[TYPE]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TYPE1]], i64 0)
+// CHECK-NEXT:[[TYPE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TYPE]], i64 0)
 // CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 svint32_t to_svint32_t(fixed_int32_t type) {
@@ -39,11 +36,8 @@
 
 // CHECK-LABEL: @to_svfloat64_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <8 x double>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x double>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x double>, <8 x double>* [[TYPE]], align 16, [[TBAA6]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 x double> [[TYPE1]], i64 0)
+// CHECK-NEXT:[[TYPE:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 x double> [[TYPE]], i64 0)
 // CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 svfloat64_t to_svfloat64_t(fixed_float64_t type) {
@@ -69,7 +63,7 @@
 // CHECK-NEXT:[[TYPE_ADDR:%.*]] = alloca <8 x i8>, align 16
 // CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x i8>* [[TYPE]] to *
 // CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x i8>, <8 x i8>* [[TYPE]], align 16, [[TBAA6]]
+// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x i8>, <8 x i8>* [[TYPE]], align 16, [[TBAA6:!tbaa !.*]]
 // CHECK-NEXT:store <8 x i8> [[TYPE1]], <8 x i8>* [[TYPE_ADDR]], align 16, [[TBAA6]]
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast <8 x i8>* [[TYPE_ADDR]] to *
 // CHECK-NEXT:[[TMP2:%.*]] = load , * [[TMP1]], align 16, [[TBAA6]]
@@ -130,11 +124,8 @@
 
 // CHECK-LABEL: @from_fixed_int32_t__to_gnu_int32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <16 x i32>, <16 x i32>* [[TYPE]], align 16, [[TBAA6]]
-// CHECK-NEXT:store <16 x i32> [[TYPE1]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
+// CHECK-NEXT:[[TYPE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:store <16 x i32> [[TYPE]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
 // CHECK-NEXT:ret void
 //
 gnu_int32_t from_fixed_int32_t__to_gnu_int32_t(fixed_int32_t type) {
Index: clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
@@ -24,17 +24,14 @@
 
 // CHECK-LABEL: @fixed_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[X:%.*]] = alloca <16 x i32>, align 16
 // CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[X]] to *
-// CHECK-NEXT:store  [[X_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[X1:%.*]] = load <16 x i32>, <16 x i32>* [[X]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[X1]], i64 0)
+// CHECK-NEXT:[[X:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLES

[PATCH] D92762: [clang][AArch64][SVE] Avoid going through memory for coerced VLST arguments

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis marked an inline comment as done.
joechrisellis added inline comments.



Comment at: clang/lib/CodeGen/CGCall.cpp:2671-2673
+  // See if this is a VLST coerced to a VLAT at the function boundary and
+  // the types match up. If so, use llvm.experimental.vector.extract to
+  // perform the conversion.

c-rhodes wrote:
> this is slightly confusing since the coercion done in TargetInfo is from 
> fixed -> scalable so VLSTs are represented as scalable vectors in functions 
> args/return, yet this is casting back to fixed in the function prolog using 
> `llvm.experimental.vector.extract` like you mention in the commit message, 
> could this comment clarify that?
I am a bit unsure what you mean in this comment, but I have tried to reword the 
comment to be a bit clearer about what's happening. Let me know if you still 
think it needs clarifying. 😄 



Comment at: clang/lib/CodeGen/CGCall.cpp:2674
+  // perform the conversion.
+  if (Ty->getAs()) {
+auto *Coerced = Fn->getArg(FirstIRArg);

c-rhodes wrote:
> Do we want to check `VT->getVectorKind() == 
> VectorType::SveFixedLengthDataVector` and 
> `isa(Coerced->getType());`?
Do we not also want to account for predicate vectors here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92762/new/

https://reviews.llvm.org/D92762

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D92762: [clang][AArch64][SVE] Avoid going through memory for coerced VLST arguments

[Joe Ellis via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG3d5b18a3fdf4: [clang][AArch64][SVE] Avoid going through 
memory for coerced VLST arguments (authored by joechrisellis).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92762/new/

https://reviews.llvm.org/D92762

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c

Index: clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
@@ -13,11 +13,8 @@
 
 // CHECK-LABEL: @to_svint32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <16 x i32>, <16 x i32>* [[TYPE]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TYPE1]], i64 0)
+// CHECK-NEXT:[[TYPE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TYPE]], i64 0)
 // CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 svint32_t to_svint32_t(fixed_int32_t type) {
@@ -39,11 +36,8 @@
 
 // CHECK-LABEL: @to_svfloat64_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <8 x double>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x double>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x double>, <8 x double>* [[TYPE]], align 16, [[TBAA6]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 x double> [[TYPE1]], i64 0)
+// CHECK-NEXT:[[TYPE:%.*]] = call <8 x double> @llvm.experimental.vector.extract.v8f64.nxv2f64( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv2f64.v8f64( undef, <8 x double> [[TYPE]], i64 0)
 // CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 svfloat64_t to_svfloat64_t(fixed_float64_t type) {
@@ -69,7 +63,7 @@
 // CHECK-NEXT:[[TYPE_ADDR:%.*]] = alloca <8 x i8>, align 16
 // CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x i8>* [[TYPE]] to *
 // CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x i8>, <8 x i8>* [[TYPE]], align 16, [[TBAA6]]
+// CHECK-NEXT:[[TYPE1:%.*]] = load <8 x i8>, <8 x i8>* [[TYPE]], align 16, [[TBAA6:!tbaa !.*]]
 // CHECK-NEXT:store <8 x i8> [[TYPE1]], <8 x i8>* [[TYPE_ADDR]], align 16, [[TBAA6]]
 // CHECK-NEXT:[[TMP1:%.*]] = bitcast <8 x i8>* [[TYPE_ADDR]] to *
 // CHECK-NEXT:[[TMP2:%.*]] = load , * [[TMP1]], align 16, [[TBAA6]]
@@ -130,11 +124,8 @@
 
 // CHECK-LABEL: @from_fixed_int32_t__to_gnu_int32_t(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TYPE:%.*]] = alloca <16 x i32>, align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[TYPE]] to *
-// CHECK-NEXT:store  [[TYPE_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[TYPE1:%.*]] = load <16 x i32>, <16 x i32>* [[TYPE]], align 16, [[TBAA6]]
-// CHECK-NEXT:store <16 x i32> [[TYPE1]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
+// CHECK-NEXT:[[TYPE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]], i64 0)
+// CHECK-NEXT:store <16 x i32> [[TYPE]], <16 x i32>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
 // CHECK-NEXT:ret void
 //
 gnu_int32_t from_fixed_int32_t__to_gnu_int32_t(fixed_int32_t type) {
Index: clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
@@ -24,17 +24,14 @@
 
 // CHECK-LABEL: @fixed_caller(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[X:%.*]] = alloca <16 x i32>, align 16
 // CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i32>* [[X]] to *
-// CHECK-NEXT:store  [[X_COERCE:%.*]], * [[TMP0]], align 16
-// CHECK-NEXT:[[X1:%.*]] = load <16 x i32>, <16 x i32>* [[X]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[X1]], i64 0)
+// CHECK-NEXT:[[X:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[X_COERCE:%.*]],

[PATCH] D94290: [clang][AArch64][SVE] Avoid going through memory for coerced VLST return values

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis created this revision.
joechrisellis added reviewers: c-rhodes, bsmith, peterwaller-arm.
Herald added subscribers: NickHung, psnobl, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
joechrisellis requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

VLST return values are coerced to VLATs in the function epilog for
consistency with the VLAT ABI. Previously, this coercion was done
through memory. It is preferable to use the
llvm.experimental.vector.insert intrinsic to avoid going through memory
here.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94290

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c

Index: clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
@@ -17,7 +17,6 @@
 // CHECK-NEXT:[[PRED_ADDR:%.*]] = alloca , align 2
 // CHECK-NEXT:[[VEC_ADDR:%.*]] = alloca , align 16
 // CHECK-NEXT:[[PG:%.*]] = alloca , align 2
-// CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
 // CHECK-NEXT:store  [[PRED:%.*]], * [[PRED_ADDR]], align 2
 // CHECK-NEXT:store  [[VEC:%.*]], * [[VEC_ADDR]], align 16
 // CHECK-NEXT:[[TMP0:%.*]] = load , * [[PRED_ADDR]], align 2
@@ -35,11 +34,9 @@
 // CHECK-NEXT:[[TMP10:%.*]] = call  @llvm.aarch64.sve.add.nxv4i32( [[TMP9]],  [[CASTSCALABLESVE]],  [[TMP8]])
 // CHECK-NEXT:[[CASTFIXEDSVE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[TMP10]], i64 0)
 // CHECK-NEXT:store <16 x i32> [[CASTFIXEDSVE]], <16 x i32>* [[RETVAL]], align 16
-// CHECK-NEXT:[[TMP11:%.*]] = bitcast * [[RETVAL_COERCE]] to i8*
-// CHECK-NEXT:[[TMP12:%.*]] = bitcast <16 x i32>* [[RETVAL]] to i8*
-// CHECK-NEXT:call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP11]], i8* align 16 [[TMP12]], i64 64, i1 false)
-// CHECK-NEXT:[[TMP13:%.*]] = load , * [[RETVAL_COERCE]], align 16
-// CHECK-NEXT:ret  [[TMP13]]
+// CHECK-NEXT:[[TMP11:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16
+// CHECK-NEXT:[[CASTSCALABLESVE1:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TMP11]], i64 0)
+// CHECK-NEXT:ret  [[CASTSCALABLESVE1]]
 //
 fixed_int32_t foo(svbool_t pred, svint32_t vec) {
   svbool_t pg = svand_z(pred, global_pred, global_pred);
@@ -50,16 +47,13 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[RETVAL:%.*]] = alloca <16 x i32>, align 16
 // CHECK-NEXT:[[GLOBAL_VEC_PTR:%.*]] = alloca <16 x i32>*, align 8
-// CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
 // CHECK-NEXT:store <16 x i32>* @global_vec, <16 x i32>** [[GLOBAL_VEC_PTR]], align 8
 // CHECK-NEXT:[[TMP0:%.*]] = load <16 x i32>*, <16 x i32>** [[GLOBAL_VEC_PTR]], align 8
 // CHECK-NEXT:[[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[TMP0]], align 16
 // CHECK-NEXT:store <16 x i32> [[TMP1]], <16 x i32>* [[RETVAL]], align 16
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast * [[RETVAL_COERCE]] to i8*
-// CHECK-NEXT:[[TMP3:%.*]] = bitcast <16 x i32>* [[RETVAL]] to i8*
-// CHECK-NEXT:call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP2]], i8* align 16 [[TMP3]], i64 64, i1 false)
-// CHECK-NEXT:[[TMP4:%.*]] = load , * [[RETVAL_COERCE]], align 16
-// CHECK-NEXT:ret  [[TMP4]]
+// CHECK-NEXT:[[TMP2:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TMP2]], i64 0)
+// CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 fixed_int32_t test_ptr_to_global() {
   fixed_int32_t *global_vec_ptr;
@@ -73,17 +67,14 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[RETVAL:%.*]] = alloca <16 x i32>, align 16
 // CHECK-NEXT:[[ARR_ADDR:%.*]] = alloca <16 x i32>*, align 8
-// CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
 // CHECK-NEXT:store <16 x i32>* [[ARR:%.*]], <16 x i32>** [[ARR_ADDR]], align 8
 // CHECK-NEXT:[[TMP0:%.*]] = load <16 x i32>*, <16 x i32>** [[ARR_ADDR]], align 8
 // CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds <16 x i32>, <16 x i32>* [[TMP0]], i64 0
 // CHECK-NEXT:[[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[ARRAYIDX]], align 16
 // CHECK-NEXT:store <16 x i32> [[TMP1]], <16 x i32>* [[RETVAL]], align 16
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast * [[RETVAL_COERCE]] to i8*
-// CHECK-NEXT:[[TMP3:%.*]] = bitcast <16 x i32>* [[RETVAL]] to i8*
-// CHECK-NEXT:call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP2]], i8* align 16 [[TMP3]], i64 64, i1 false)
-// CHECK-NEXT:[[TMP4:%.*]] = load , * [[RETVAL_COERCE]], 

[PATCH] D94290: [clang][AArch64][SVE] Avoid going through memory for coerced VLST return values

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis updated this revision to Diff 315339.
joechrisellis added a comment.

Address @c-rhodes's comment.

- Use `SrcTy` instead of `Src.getElementType()`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94290/new/

https://reviews.llvm.org/D94290

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c

Index: clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
@@ -17,7 +17,6 @@
 // CHECK-NEXT:[[PRED_ADDR:%.*]] = alloca , align 2
 // CHECK-NEXT:[[VEC_ADDR:%.*]] = alloca , align 16
 // CHECK-NEXT:[[PG:%.*]] = alloca , align 2
-// CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
 // CHECK-NEXT:store  [[PRED:%.*]], * [[PRED_ADDR]], align 2
 // CHECK-NEXT:store  [[VEC:%.*]], * [[VEC_ADDR]], align 16
 // CHECK-NEXT:[[TMP0:%.*]] = load , * [[PRED_ADDR]], align 2
@@ -35,11 +34,9 @@
 // CHECK-NEXT:[[TMP10:%.*]] = call  @llvm.aarch64.sve.add.nxv4i32( [[TMP9]],  [[CASTSCALABLESVE]],  [[TMP8]])
 // CHECK-NEXT:[[CASTFIXEDSVE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[TMP10]], i64 0)
 // CHECK-NEXT:store <16 x i32> [[CASTFIXEDSVE]], <16 x i32>* [[RETVAL]], align 16
-// CHECK-NEXT:[[TMP11:%.*]] = bitcast * [[RETVAL_COERCE]] to i8*
-// CHECK-NEXT:[[TMP12:%.*]] = bitcast <16 x i32>* [[RETVAL]] to i8*
-// CHECK-NEXT:call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP11]], i8* align 16 [[TMP12]], i64 64, i1 false)
-// CHECK-NEXT:[[TMP13:%.*]] = load , * [[RETVAL_COERCE]], align 16
-// CHECK-NEXT:ret  [[TMP13]]
+// CHECK-NEXT:[[TMP11:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16
+// CHECK-NEXT:[[CASTSCALABLESVE1:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TMP11]], i64 0)
+// CHECK-NEXT:ret  [[CASTSCALABLESVE1]]
 //
 fixed_int32_t foo(svbool_t pred, svint32_t vec) {
   svbool_t pg = svand_z(pred, global_pred, global_pred);
@@ -50,16 +47,13 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[RETVAL:%.*]] = alloca <16 x i32>, align 16
 // CHECK-NEXT:[[GLOBAL_VEC_PTR:%.*]] = alloca <16 x i32>*, align 8
-// CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
 // CHECK-NEXT:store <16 x i32>* @global_vec, <16 x i32>** [[GLOBAL_VEC_PTR]], align 8
 // CHECK-NEXT:[[TMP0:%.*]] = load <16 x i32>*, <16 x i32>** [[GLOBAL_VEC_PTR]], align 8
 // CHECK-NEXT:[[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[TMP0]], align 16
 // CHECK-NEXT:store <16 x i32> [[TMP1]], <16 x i32>* [[RETVAL]], align 16
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast * [[RETVAL_COERCE]] to i8*
-// CHECK-NEXT:[[TMP3:%.*]] = bitcast <16 x i32>* [[RETVAL]] to i8*
-// CHECK-NEXT:call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP2]], i8* align 16 [[TMP3]], i64 64, i1 false)
-// CHECK-NEXT:[[TMP4:%.*]] = load , * [[RETVAL_COERCE]], align 16
-// CHECK-NEXT:ret  [[TMP4]]
+// CHECK-NEXT:[[TMP2:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TMP2]], i64 0)
+// CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 fixed_int32_t test_ptr_to_global() {
   fixed_int32_t *global_vec_ptr;
@@ -73,17 +67,14 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[RETVAL:%.*]] = alloca <16 x i32>, align 16
 // CHECK-NEXT:[[ARR_ADDR:%.*]] = alloca <16 x i32>*, align 8
-// CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
 // CHECK-NEXT:store <16 x i32>* [[ARR:%.*]], <16 x i32>** [[ARR_ADDR]], align 8
 // CHECK-NEXT:[[TMP0:%.*]] = load <16 x i32>*, <16 x i32>** [[ARR_ADDR]], align 8
 // CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds <16 x i32>, <16 x i32>* [[TMP0]], i64 0
 // CHECK-NEXT:[[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[ARRAYIDX]], align 16
 // CHECK-NEXT:store <16 x i32> [[TMP1]], <16 x i32>* [[RETVAL]], align 16
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast * [[RETVAL_COERCE]] to i8*
-// CHECK-NEXT:[[TMP3:%.*]] = bitcast <16 x i32>* [[RETVAL]] to i8*
-// CHECK-NEXT:call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP2]], i8* align 16 [[TMP3]], i64 64, i1 false)
-// CHECK-NEXT:[[TMP4:%.*]] = load , * [[RETVAL_COERCE]], align 16
-// CHECK-NEXT:ret  [[TMP4]]
+// CHECK-NEXT:[[TMP2:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TMP2]], i64 0)
+// CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 fixed_int32_t array_arg(fixed_int32_t arr[])

[PATCH] D94290: [clang][AArch64][SVE] Avoid going through memory for coerced VLST return values

[Joe Ellis via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG8ea72b388734: [clang][AArch64][SVE] Avoid going through 
memory for coerced VLST return values (authored by joechrisellis).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94290/new/

https://reviews.llvm.org/D94290

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
  clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
  clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c

Index: clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
===
--- clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
+++ clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
@@ -17,7 +17,6 @@
 // CHECK-NEXT:[[PRED_ADDR:%.*]] = alloca , align 2
 // CHECK-NEXT:[[VEC_ADDR:%.*]] = alloca , align 16
 // CHECK-NEXT:[[PG:%.*]] = alloca , align 2
-// CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
 // CHECK-NEXT:store  [[PRED:%.*]], * [[PRED_ADDR]], align 2
 // CHECK-NEXT:store  [[VEC:%.*]], * [[VEC_ADDR]], align 16
 // CHECK-NEXT:[[TMP0:%.*]] = load , * [[PRED_ADDR]], align 2
@@ -35,11 +34,9 @@
 // CHECK-NEXT:[[TMP10:%.*]] = call  @llvm.aarch64.sve.add.nxv4i32( [[TMP9]],  [[CASTSCALABLESVE]],  [[TMP8]])
 // CHECK-NEXT:[[CASTFIXEDSVE:%.*]] = call <16 x i32> @llvm.experimental.vector.extract.v16i32.nxv4i32( [[TMP10]], i64 0)
 // CHECK-NEXT:store <16 x i32> [[CASTFIXEDSVE]], <16 x i32>* [[RETVAL]], align 16
-// CHECK-NEXT:[[TMP11:%.*]] = bitcast * [[RETVAL_COERCE]] to i8*
-// CHECK-NEXT:[[TMP12:%.*]] = bitcast <16 x i32>* [[RETVAL]] to i8*
-// CHECK-NEXT:call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP11]], i8* align 16 [[TMP12]], i64 64, i1 false)
-// CHECK-NEXT:[[TMP13:%.*]] = load , * [[RETVAL_COERCE]], align 16
-// CHECK-NEXT:ret  [[TMP13]]
+// CHECK-NEXT:[[TMP11:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16
+// CHECK-NEXT:[[CASTSCALABLESVE1:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TMP11]], i64 0)
+// CHECK-NEXT:ret  [[CASTSCALABLESVE1]]
 //
 fixed_int32_t foo(svbool_t pred, svint32_t vec) {
   svbool_t pg = svand_z(pred, global_pred, global_pred);
@@ -50,16 +47,13 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[RETVAL:%.*]] = alloca <16 x i32>, align 16
 // CHECK-NEXT:[[GLOBAL_VEC_PTR:%.*]] = alloca <16 x i32>*, align 8
-// CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
 // CHECK-NEXT:store <16 x i32>* @global_vec, <16 x i32>** [[GLOBAL_VEC_PTR]], align 8
 // CHECK-NEXT:[[TMP0:%.*]] = load <16 x i32>*, <16 x i32>** [[GLOBAL_VEC_PTR]], align 8
 // CHECK-NEXT:[[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[TMP0]], align 16
 // CHECK-NEXT:store <16 x i32> [[TMP1]], <16 x i32>* [[RETVAL]], align 16
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast * [[RETVAL_COERCE]] to i8*
-// CHECK-NEXT:[[TMP3:%.*]] = bitcast <16 x i32>* [[RETVAL]] to i8*
-// CHECK-NEXT:call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP2]], i8* align 16 [[TMP3]], i64 64, i1 false)
-// CHECK-NEXT:[[TMP4:%.*]] = load , * [[RETVAL_COERCE]], align 16
-// CHECK-NEXT:ret  [[TMP4]]
+// CHECK-NEXT:[[TMP2:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TMP2]], i64 0)
+// CHECK-NEXT:ret  [[CASTSCALABLESVE]]
 //
 fixed_int32_t test_ptr_to_global() {
   fixed_int32_t *global_vec_ptr;
@@ -73,17 +67,14 @@
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[RETVAL:%.*]] = alloca <16 x i32>, align 16
 // CHECK-NEXT:[[ARR_ADDR:%.*]] = alloca <16 x i32>*, align 8
-// CHECK-NEXT:[[RETVAL_COERCE:%.*]] = alloca , align 16
 // CHECK-NEXT:store <16 x i32>* [[ARR:%.*]], <16 x i32>** [[ARR_ADDR]], align 8
 // CHECK-NEXT:[[TMP0:%.*]] = load <16 x i32>*, <16 x i32>** [[ARR_ADDR]], align 8
 // CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds <16 x i32>, <16 x i32>* [[TMP0]], i64 0
 // CHECK-NEXT:[[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[ARRAYIDX]], align 16
 // CHECK-NEXT:store <16 x i32> [[TMP1]], <16 x i32>* [[RETVAL]], align 16
-// CHECK-NEXT:[[TMP2:%.*]] = bitcast * [[RETVAL_COERCE]] to i8*
-// CHECK-NEXT:[[TMP3:%.*]] = bitcast <16 x i32>* [[RETVAL]] to i8*
-// CHECK-NEXT:call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP2]], i8* align 16 [[TMP3]], i64 64, i1 false)
-// CHECK-NEXT:[[TMP4:%.*]] = load , * [[RETVAL_COERCE]], align 16
-// CHECK-NEXT:ret  [[TMP4]]
+// CHECK-NEXT:[[TMP2:%.*]] = load <16 x i32>, <16 x i32>* [[RETVAL]], align 16
+// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.experimental.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TMP2]], i64 0)
+// CHECK-NEXT:ret  [[CASTSCALABLESV

[PATCH] D93101: [Clang][Codegen] Truncate initializers of union bitfield members

[Joe Ellis via Phabricator via cfe-commits]

joechrisellis added inline comments.



Comment at: clang/lib/AST/ExprConstant.cpp:9803-9804
+   (Field->isBitField() &&
+truncateBitfieldValue(Info, InitExpr, Result.getUnionValue(),
+  Field));
   }

nit: I would prefer this:

```
if (Field->isBitField() && truncateBitfieldValue(Info, InitExpr, 
Result.getUnionValue(), Field))
return true;

return EvaluateInPlace(Result.getUnionValue(), Info, Subobject, InitExpr);
```

It feels more in-line with the rest of the function. But it is okay if you want 
to ignore this too. 😄 



Comment at: clang/test/CodeGenCXX/bitfield-layout.cpp:88-95
+// CHECK: define i32 @_Z10test_truncv()
+int test_trunc() {
+  union {
+int i : 4;
+  } U = {15};
+  return U.i;
+  // CHECK: ret i32 -1

I'd like to see some more tests that check the truncation behaviour. My 
understanding is that this is trucating to -1 because of two's complement? How 
about something like:

```
int test_trunc() {
union {
int i : 4;
} U = {80};
return U.i;
// CHECK: ret i32 0
}
```

Am I understanding the behaviour correctly?

Some comments about what is actually happening on the bit-level to get this 
result would also be nice.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93101/new/

https://reviews.llvm.org/D93101

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits