[llvm] [clang] [RISCV] Add support for experimental Zimop extension (PR #74824)

2023-12-08 Thread Jivan Hakobyan via cfe-commits 

https://github.com/JivanH created 
https://github.com/llvm/llvm-project/pull/74824

This implements experimental support for the Zimop extension as specified here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.

This change adds intrinsics of mop.r.[n] and mop.rr.[n] instructions for Zimop 
extension based on 
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md. 


>From 2940a49eed5214668d4235ddaf3c82d076202b94 Mon Sep 17 00:00:00 2001
From: ln8-8 
Date: Fri, 8 Dec 2023 12:25:49 +0400
Subject: [PATCH] [RISCV] Add support for experimental Zimop extension

 This implements experimental support for the Zimop extension as specified 
here: https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.

This change adds IR intrinsics of mop.r.[n] and mop.rr.[n] instructions for 
Zimop extension based on 
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md. 
Also added assembly support.
---
 clang/include/clang/Basic/BuiltinsRISCV.def   |   5 +
 clang/lib/CodeGen/CGBuiltin.cpp   |  34 
 clang/lib/Sema/SemaChecking.cpp   |   8 +
 .../test/CodeGen/RISCV/rvb-intrinsics/zimop.c | 104 +++
 llvm/docs/RISCVUsage.rst  |   3 +
 llvm/include/llvm/IR/IntrinsicsRISCV.td   |  23 +++
 llvm/lib/Support/RISCVISAInfo.cpp |   2 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|   5 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   | 171 ++
 llvm/lib/Target/RISCV/RISCVISelLowering.h |   6 +
 llvm/lib/Target/RISCV/RISCVInstrFormats.td|  21 +++
 llvm/lib/Target/RISCV/RISCVInstrInfo.td   |  53 ++
 llvm/lib/Target/RISCV/RISCVSchedRocket.td |   1 +
 llvm/lib/Target/RISCV/RISCVSchedSiFive7.td|   1 +
 .../Target/RISCV/RISCVSchedSyntacoreSCR1.td   |   1 +
 llvm/lib/Target/RISCV/RISCVSchedule.td|  14 ++
 llvm/test/CodeGen/RISCV/attributes.ll |   4 +
 .../test/CodeGen/RISCV/rv32zimop-intrinsic.ll |  47 +
 .../test/CodeGen/RISCV/rv64zimop-intrinsic.ll |  96 ++
 llvm/test/MC/RISCV/rv32zimop-invalid.s|   6 +
 llvm/test/MC/RISCV/rvzimop-valid.s|  26 +++
 llvm/unittests/Support/RISCVISAInfoTest.cpp   |   1 +
 22 files changed, 632 insertions(+)
 create mode 100644 clang/test/CodeGen/RISCV/rvb-intrinsics/zimop.c
 create mode 100644 llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll
 create mode 100644 llvm/test/MC/RISCV/rv32zimop-invalid.s
 create mode 100644 llvm/test/MC/RISCV/rvzimop-valid.s

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def 
b/clang/include/clang/Basic/BuiltinsRISCV.def
index 1528b18c82ead..6ba5288f9cbd1 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -89,5 +89,10 @@ TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh")
 TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl")
 TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl")
 
+TARGET_BUILTIN(__builtin_riscv_mopr_32, "UiUiUi", "nc", "experimental-zimop")
+TARGET_BUILTIN(__builtin_riscv_mopr_64, "UWiUWiUWi", "nc", 
"experimental-zimop,64bit")
+TARGET_BUILTIN(__builtin_riscv_moprr_32, "UiUiUiUi", "nc", 
"experimental-zimop")
+TARGET_BUILTIN(__builtin_riscv_moprr_64, "UWiUWiUWiUWi", "nc", 
"experimental-zimop,64bit")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 0d8b3e4aaad47..11ba665dda938 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -20808,6 +20808,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
   case RISCV::BI__builtin_riscv_clz_64:
   case RISCV::BI__builtin_riscv_ctz_32:
   case RISCV::BI__builtin_riscv_ctz_64:
+  case RISCV::BI__builtin_riscv_mopr_32:
+  case RISCV::BI__builtin_riscv_mopr_64:
+  case RISCV::BI__builtin_riscv_moprr_32:
+  case RISCV::BI__builtin_riscv_moprr_64:
   case RISCV::BI__builtin_riscv_clmul_32:
   case RISCV::BI__builtin_riscv_clmul_64:
   case RISCV::BI__builtin_riscv_clmulh_32:
@@ -20848,6 +20852,36 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
   return Result;
 }
 
+// Zimop
+case RISCV::BI__builtin_riscv_mopr_32:
+case RISCV::BI__builtin_riscv_mopr_64: {
+  unsigned N = cast(Ops[1])->getZExtValue();
+  Function *F = nullptr;
+  if (N <= 1) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr0 + N, {ResultType});
+  } else if (N >= 10 && N <= 19) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr10 + N - 10, {ResultType});
+  } else if (N == 2) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr2, {ResultType});
+  } else if (N >= 20 && N <= 29) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr20 + N - 20, {ResultType});
+  } else if (N == 3) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr3, {ResultType});
+  } else if (N

[llvm] [clang] [RISCV] Add support for experimental Zimop extension (PR #74824)

2023-12-08 Thread Jivan Hakobyan via cfe-commits 

JivanH wrote:

@topperc 
@asb 
@michaelmaitland 
@wangpc-pp 

https://github.com/llvm/llvm-project/pull/74824
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[llvm] [clang] [RISCV] Add support for experimental Zimop extension (PR #74824)

2023-12-11 Thread Jivan Hakobyan via cfe-commits 

JivanH wrote:

@dtcxzyw @wangpc-pp 

Thank you for your review and suggestions. Will do as you suggested and will 
send the patch series.

https://github.com/llvm/llvm-project/pull/74824
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[clang-tools-extra] [flang] [libc] [llvm] [compiler-rt] [libcxx] [clang] [RISCV][MC] Add support for experimental Zimop extension (PR #75182)

2023-12-13 Thread Jivan Hakobyan via cfe-commits 

https://github.com/JivanH updated 
https://github.com/llvm/llvm-project/pull/75182

>From e6bf0819c96fcfbd73d711acc951065e2ed22d8c Mon Sep 17 00:00:00 2001
From: ln8-8 
Date: Tue, 12 Dec 2023 12:47:32 +0400
Subject: [PATCH] [RISCV][MC] Add support for experimental Zimop extension

This implements experimental support for the Zimop extension as specified here: 
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.

This change adds only assembly support.
---
 llvm/docs/RISCVUsage.rst|  3 ++
 llvm/include/llvm/IR/IntrinsicsRISCV.td | 23 +++
 llvm/lib/Support/RISCVISAInfo.cpp   |  2 +
 llvm/lib/Target/RISCV/RISCVFeatures.td  |  5 +++
 llvm/lib/Target/RISCV/RISCVInstrFormats.td  | 21 ++
 llvm/lib/Target/RISCV/RISCVInstrInfo.td | 45 +
 llvm/test/CodeGen/RISCV/attributes.ll   |  4 ++
 llvm/test/MC/RISCV/rv32zimop-invalid.s  |  6 +++
 llvm/test/MC/RISCV/rvzimop-valid.s  | 26 
 llvm/unittests/Support/RISCVISAInfoTest.cpp |  1 +
 10 files changed, 136 insertions(+)
 create mode 100644 llvm/test/MC/RISCV/rv32zimop-invalid.s
 create mode 100644 llvm/test/MC/RISCV/rvzimop-valid.s

diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 65dd0d83448ed1..bd2f81fba186df 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -208,6 +208,9 @@ The primary goal of experimental support is to assist in 
the process of ratifica
 ``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkb``, 
``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknc``, 
``experimental-zvkned``, ``experimental-zvkng``, ``experimental-zvknha``, 
``experimental-zvknhb``, ``experimental-zvks``, ``experimental-zvksc``, 
``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, 
``experimental-zvkt``
   LLVM implements the `1.0.0-rc2 specification 
`__.
 Note that current vector crypto extension version can be found in: 
.
 
+``experimental-zimop``
+  LLVM implements the `v0.1 proposed specification 
`__.
+
 To use an experimental extension from `clang`, you must add 
`-menable-experimental-extensions` to the command line, and specify the exact 
version of the experimental extension you are using.  To use an experimental 
extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, 
`llvm-mc`), you must prefix the extension name with `experimental-`.  Note that 
you don't need to specify the version with internal tools, and shouldn't 
include the `experimental-` prefix with `clang`.
 
 Vendor Extensions
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td 
b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 20c6a525a86ba7..fcb11c8c51398d 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -108,6 +108,29 @@ let TargetPrefix = "riscv" in {
   def int_riscv_xperm8  : BitManipGPRGPRIntrinsics;
 } // TargetPrefix = "riscv"
 
+//===--===//
+// May-Be-Operations
+
+let TargetPrefix = "riscv" in {
+
+  class MOPGPRIntrinsics
+  : DefaultAttrsIntrinsic<[llvm_any_ty],
+  [LLVMMatchType<0>],
+  [IntrNoMem, IntrSpeculatable]>;
+  class MOPGPRGPRIntrinsics
+  : DefaultAttrsIntrinsic<[llvm_any_ty],
+  [LLVMMatchType<0>, LLVMMatchType<0>],
+  [IntrNoMem, IntrSpeculatable]>;
+
+  // Zimop
+   foreach i = 0...31 in {
+def int_riscv_mopr#i : MOPGPRIntrinsics;
+   }
+  foreach i = 0...7 in {
+def int_riscv_moprr#i : MOPGPRGPRIntrinsics;
+  }
+} // TargetPrefix = "riscv"
+
 
//===--===//
 // Vectors
 
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp 
b/llvm/lib/Support/RISCVISAInfo.cpp
index 6322748430063c..1b303ba1e9431d 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -177,6 +177,8 @@ static const RISCVSupportedExtension 
SupportedExperimentalExtensions[] = {
 {"zicfilp", RISCVExtensionVersion{0, 2}},
 {"zicond", RISCVExtensionVersion{1, 0}},
 
+{"zimop", RISCVExtensionVersion{0, 1}},
+
 {"ztso", RISCVExtensionVersion{0, 1}},
 
 {"zvbb", RISCVExtensionVersion{1, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td 
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 294927aecb94b8..5b642090b7b9eb 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -687,6 +687,11 @@ def HasStdExtZicond : 
Predicate<"Subtarget->hasStdExtZicond()">,
 AssemblerPredicate<(all_of 
FeatureStdExtZicond),
 "'Zicond' (Integer Conditional Oper

[llvm] [clang] [RISCV] Add support for experimental Zimop extension (PR #74824)

2023-12-13 Thread Jivan Hakobyan via cfe-commits 

https://github.com/JivanH closed https://github.com/llvm/llvm-project/pull/74824
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[clang] [libcxx] [clang-tools-extra] [compiler-rt] [libc] [llvm] [flang] [RISCV][MC] Add support for experimental Zimop extension (PR #75182)

2023-12-13 Thread Jivan Hakobyan via cfe-commits 

JivanH wrote:

> > @topperc If I am not mistaken Zicfiss extension uses moprr instructions to 
> > get ROP functionality. But Zimop does not limit only the use of Zicfiss 
> > extension. They can be redefined and assigned other operations.
> 
> Right, but won't users be programming to each of the extensions that redefine 
> them rather than some generic interface? We don't have builtins/intrinsics 
> for all of the HINT encodings that can redefined.

Yeah, I agree with you. 
But can be cases when someone in some narrow case needs to program logic by 
hand. Why restrict it? 
I also think that a generic interface is much better than achieving the same 
logic through builtins/intrinsics.

https://github.com/llvm/llvm-project/pull/75182
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[clang] [RISCV][Clang] Added builtin support for experimental Zimop extension (PR #79971)

2024-03-05 Thread Jivan Hakobyan via cfe-commits 

JivanH wrote:

@topperc 
@wangpc-pp 
@dtcxzyw 

REMIND:

Hi. Could you please review my patch?

https://github.com/llvm/llvm-project/pull/79971
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[clang-tools-extra] [clang] [llvm] [RISCV][ISel] Add ISel support for experimental Zimop extension (PR #77089)

2024-01-28 Thread Jivan Hakobyan via cfe-commits 

https://github.com/JivanH updated 
https://github.com/llvm/llvm-project/pull/77089

>From caab6046a26517946bdce7659e4236ae9d5154fe Mon Sep 17 00:00:00 2001
From: ln8-8 
Date: Fri, 5 Jan 2024 16:08:53 +0400
Subject: [PATCH 1/5] [RISCV][ISel] Add ISel support for experimental Zimop
 extension

This implements ISel support for mopr[0-31] and moprr[0-8] instructions for 32 
and 64 bits
---
 llvm/include/llvm/IR/IntrinsicsRISCV.td   |  23 +++
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   | 171 ++
 llvm/lib/Target/RISCV/RISCVISelLowering.h |   7 +
 llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td  |  28 +++
 .../test/CodeGen/RISCV/rv32zimop-intrinsic.ll |  48 +
 .../test/CodeGen/RISCV/rv64zimop-intrinsic.ll |  97 ++
 6 files changed, 374 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll

diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td 
b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index a391bc53cdb0e99..8ddda2a13e5c3b4 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -108,6 +108,29 @@ let TargetPrefix = "riscv" in {
   def int_riscv_xperm8  : BitManipGPRGPRIntrinsics;
 } // TargetPrefix = "riscv"
 
+//===--===//
+// May-Be-Operations
+
+let TargetPrefix = "riscv" in {
+
+  class MOPGPRIntrinsics
+  : DefaultAttrsIntrinsic<[llvm_any_ty],
+  [LLVMMatchType<0>],
+  [IntrNoMem, IntrSpeculatable]>;
+  class MOPGPRGPRIntrinsics
+  : DefaultAttrsIntrinsic<[llvm_any_ty],
+  [LLVMMatchType<0>, LLVMMatchType<0>],
+  [IntrNoMem, IntrSpeculatable]>;
+
+  // Zimop
+   foreach i = 0...31 in {
+def int_riscv_mopr#i : MOPGPRIntrinsics;
+   }
+  foreach i = 0...7 in {
+def int_riscv_moprr#i : MOPGPRGPRIntrinsics;
+  }
+} // TargetPrefix = "riscv"
+
 
//===--===//
 // Vectors
 
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index bc4b2b022c0ae98..f8c10fcd139f82d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8404,6 +8404,73 @@ SDValue 
RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
 IntNo == Intrinsic::riscv_zip ? RISCVISD::ZIP : RISCVISD::UNZIP;
 return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1));
   }
+#define RISCV_MOPR_64_CASE(NAME, OPCODE)   
\
+  case Intrinsic::riscv_##NAME: {  
\
+if (RV64LegalI32 && Subtarget.is64Bit() && 
\
+Op.getValueType() == MVT::i32) {   
\
+  SDValue NewOp =  
\
+  DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(1));
\
+  SDValue Res = DAG.getNode(OPCODE, DL, MVT::i64, NewOp);  
\
+  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res);
\
+}  
\
+return DAG.getNode(OPCODE, DL, XLenVT, Op.getOperand(1));  
\
+  }
+RISCV_MOPR_64_CASE(mopr0, RISCVISD::MOPR0)
+RISCV_MOPR_64_CASE(mopr1, RISCVISD::MOPR1)
+RISCV_MOPR_64_CASE(mopr2, RISCVISD::MOPR2)
+RISCV_MOPR_64_CASE(mopr3, RISCVISD::MOPR3)
+RISCV_MOPR_64_CASE(mopr4, RISCVISD::MOPR4)
+RISCV_MOPR_64_CASE(mopr5, RISCVISD::MOPR5)
+RISCV_MOPR_64_CASE(mopr6, RISCVISD::MOPR6)
+RISCV_MOPR_64_CASE(mopr7, RISCVISD::MOPR7)
+RISCV_MOPR_64_CASE(mopr8, RISCVISD::MOPR8)
+RISCV_MOPR_64_CASE(mopr9, RISCVISD::MOPR9)
+RISCV_MOPR_64_CASE(mopr10, RISCVISD::MOPR10)
+RISCV_MOPR_64_CASE(mopr11, RISCVISD::MOPR11)
+RISCV_MOPR_64_CASE(mopr12, RISCVISD::MOPR12)
+RISCV_MOPR_64_CASE(mopr13, RISCVISD::MOPR13)
+RISCV_MOPR_64_CASE(mopr14, RISCVISD::MOPR14)
+RISCV_MOPR_64_CASE(mopr15, RISCVISD::MOPR15)
+RISCV_MOPR_64_CASE(mopr16, RISCVISD::MOPR16)
+RISCV_MOPR_64_CASE(mopr17, RISCVISD::MOPR17)
+RISCV_MOPR_64_CASE(mopr18, RISCVISD::MOPR18)
+RISCV_MOPR_64_CASE(mopr19, RISCVISD::MOPR19)
+RISCV_MOPR_64_CASE(mopr20, RISCVISD::MOPR20)
+RISCV_MOPR_64_CASE(mopr21, RISCVISD::MOPR21)
+RISCV_MOPR_64_CASE(mopr22, RISCVISD::MOPR22)
+RISCV_MOPR_64_CASE(mopr23, RISCVISD::MOPR23)
+RISCV_MOPR_64_CASE(mopr24, RISCVISD::MOPR24)
+RISCV_MOPR_64_CASE(mopr25, RISCVISD::MOPR25)
+RISCV_MOPR_64_CASE(mopr26, RISCVISD::MOPR26)
+RISCV_MOPR_64_CASE(mopr27, RISCVISD::MOPR27)
+RISCV_MOPR_64_CASE(mopr28, RISCVISD::MOPR28)
+RISCV_MOPR_64_CASE(mopr29, RISCVISD::MOPR29)
+RISCV_MOPR_64_CASE(mopr30, RISCVISD::MOPR30)
+RISCV_MOPR_64_CASE

[clang] [RISCV][Clang] Added builtin support for experimental Zimop extension (PR #79971)

2024-01-30 Thread Jivan Hakobyan via cfe-commits 

https://github.com/JivanH created 
https://github.com/llvm/llvm-project/pull/79971

This change adds builtin of mop.r.[n] and mop.rr.[n] instructions for Zimop 
extension based on 
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md.

>From a2a37921c83511796e051520c887092a3f58a3ba Mon Sep 17 00:00:00 2001
From: ln8-8 
Date: Tue, 30 Jan 2024 13:02:22 +0400
Subject: [PATCH] [RISCV][Clang] Added builtin support for experimental Zimop
 extension

This change adds builtin of mop.r.[n] and mop.rr.[n] instructions for Zimop 
extension based on 
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md.
---
 clang/include/clang/Basic/BuiltinsRISCV.def   |   7 ++
 clang/lib/CodeGen/CGBuiltin.cpp   |  14 +++
 clang/lib/Sema/SemaChecking.cpp   |   8 ++
 .../test/CodeGen/RISCV/rvb-intrinsics/zimop.c | 105 ++
 4 files changed, 134 insertions(+)
 create mode 100644 clang/test/CodeGen/RISCV/rvb-intrinsics/zimop.c

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def 
b/clang/include/clang/Basic/BuiltinsRISCV.def
index 1528b18c82ead..7e2dda21830c5 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -89,5 +89,12 @@ TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh")
 TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl")
 TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl")
 
+// Zimop extension
+TARGET_BUILTIN(__builtin_riscv_mopr_32, "UiUiUi", "nc", "experimental-zimop")
+TARGET_BUILTIN(__builtin_riscv_mopr_64, "UWiUWiUWi", "nc",
+"experimental-zimop,64bit")
+TARGET_BUILTIN(__builtin_riscv_moprr_32, "UiUiUiUi", "nc", 
"experimental-zimop")
+TARGET_BUILTIN(__builtin_riscv_moprr_64, "UWiUWiUWiUWi", "nc",
+ "experimental-zimop,64bit")
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index f3ab5ad7b08ec..28511f9e0beac 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -21189,6 +21189,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
   case RISCV::BI__builtin_riscv_clmulh_64:
   case RISCV::BI__builtin_riscv_clmulr_32:
   case RISCV::BI__builtin_riscv_clmulr_64:
+  case RISCV::BI__builtin_riscv_mopr_32:
+  case RISCV::BI__builtin_riscv_mopr_64:
+  case RISCV::BI__builtin_riscv_moprr_32:
+  case RISCV::BI__builtin_riscv_moprr_64:
   case RISCV::BI__builtin_riscv_xperm4_32:
   case RISCV::BI__builtin_riscv_xperm4_64:
   case RISCV::BI__builtin_riscv_xperm8_32:
@@ -21237,6 +21241,16 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
   ID = Intrinsic::riscv_clmulr;
   break;
 
+// Zimop
+case RISCV::BI__builtin_riscv_mopr_32:
+case RISCV::BI__builtin_riscv_mopr_64:
+  ID = Intrinsic::riscv_mopr;
+  break;
+case RISCV::BI__builtin_riscv_moprr_32:
+case RISCV::BI__builtin_riscv_moprr_64:
+  ID = Intrinsic::riscv_moprr;
+  break;
+
 // Zbkx
 case RISCV::BI__builtin_riscv_xperm8_32:
 case RISCV::BI__builtin_riscv_xperm8_64:
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 502b24bcdf8b4..c2702bec29dd7 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5588,6 +5588,14 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const 
TargetInfo &TI,
   // Check if rnum is in [0, 10]
   case RISCV::BI__builtin_riscv_aes64ks1i:
 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 10);
+  // Check if n of mop.r.[n] is in [0, 31]
+  case RISCV::BI__builtin_riscv_mopr_32:
+  case RISCV::BI__builtin_riscv_mopr_64:
+return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);
+  // Check if n of mop.rr.[n] is in [0, 7]
+  case RISCV::BI__builtin_riscv_moprr_32:
+  case RISCV::BI__builtin_riscv_moprr_64:
+return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
   // Check if value range for vxrm is in [0, 3]
   case RISCVVector::BI__builtin_rvv_vaaddu_vv:
   case RISCVVector::BI__builtin_rvv_vaaddu_vx:
diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/zimop.c 
b/clang/test/CodeGen/RISCV/rvb-intrinsics/zimop.c
new file mode 100644
index 0..b4367e33bdc19
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/zimop.c
@@ -0,0 +1,105 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zimop 
-emit-llvm %s -o - \
+// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN: | FileCheck %s  -check-prefix=RV32ZIMOP
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zimop 
-emit-llvm %s -o - \
+// RUN: -disable-O0-optnone | opt -S -passes=mem2reg \
+// RUN: | FileCheck %s  -check-prefix=RV64ZIMOP
+
+#include 
+
+#if __riscv_xlen == 64
+// RV64ZIMOP-LABEL: @mopr_0_64(
+// RV64ZIMOP-NEXT:  entry:
+//

[clang] [RISCV][Clang] Added builtin support for experimental Zimop extension (PR #79971)

2024-01-30 Thread Jivan Hakobyan via cfe-commits 

JivanH wrote:

Please review
@topperc 
@wangpc-pp 
@dtcxzyw 

https://github.com/llvm/llvm-project/pull/79971
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