[PATCH] D79770: [RISCV] Fix passing two floating-point values in complex separately by two GPRs on RV64

2020-05-12 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Jim added reviewers: asb, luismarques, lenary.
Herald added subscribers: cfe-commits, evandro, apazos, sameer.abuasal, pzheng, 
s.egerton, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar.
Herald added a project: clang.

This patch fixed the error of counting the remaining FPRs. Complex 
floating-point values should be passed by two FPRs for the hard-float ABI. If 
no two FPRs are available, it should be passed via a 64-bit GPR (fp+fp).  
`ArgFPRsLeft` is only decreased one while the type is complex floating-point. 
It causes two floating-point values in the complex are passed separately by two 
GPRs.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79770

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/riscv64-lp64-abi.c
  clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c


Index: clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c
===
--- clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c
+++ clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c
@@ -165,6 +165,35 @@
   return (struct floatcomplex_s){1.0};
 }
 
+// Complex floating-point values or structs containing a single complex
+// floating-point value should be passed in GPRs if no two FPRs is available.
+
+// CHECK: define void @f_floatcomplex_insufficient_fprs1(float %a.coerce0, 
float %a.coerce1, float %b.coerce0, float %b.coerce1, float %c.coerce0, float 
%c.coerce1, float %d.coerce0, float %d.coerce1, i64 %e.coerce)
+void f_floatcomplex_insufficient_fprs1(float __complex__ a, float __complex__ 
b,
+   float __complex__ c, float __complex__ 
d,
+   float __complex__ e) {}
+
+
+// CHECK: define void @f_floatcomplex_s_arg_insufficient_fprs1(float %0, float 
%1, float %2, float %3, float %4, float %5, float %6, float %7, i64 %e.coerce)
+void f_floatcomplex_s_arg_insufficient_fprs1(struct floatcomplex_s a,
+ struct floatcomplex_s b,
+ struct floatcomplex_s c,
+ struct floatcomplex_s d,
+ struct floatcomplex_s e) {}
+
+// CHECK: define void @f_floatcomplex_insufficient_fprs2(float %a, float 
%b.coerce0, float %b.coerce1, float %c.coerce0, float %c.coerce1, float 
%d.coerce0, float %d.coerce1, i64 %e.coerce)
+void f_floatcomplex_insufficient_fprs2(float a,
+   float __complex__ b, float __complex__ 
c,
+   float __complex__ d, float __complex__ 
e) {}
+
+
+// CHECK: define void @f_floatcomplex_s_arg_insufficient_fprs2(float %a, float 
%0, float %1, float %2, float %3, float %4, float %5, i64 %e.coerce)
+void f_floatcomplex_s_arg_insufficient_fprs2(float a,
+ struct floatcomplex_s b,
+ struct floatcomplex_s c,
+ struct floatcomplex_s d,
+ struct floatcomplex_s e) {}
+
 // Test single or two-element structs that need flattening. e.g. those
 // containing nested structs, floats in small arrays, zero-length structs etc.
 
Index: clang/test/CodeGen/riscv64-lp64-abi.c
===
--- clang/test/CodeGen/riscv64-lp64-abi.c
+++ clang/test/CodeGen/riscv64-lp64-abi.c
@@ -30,3 +30,24 @@
   uint8_t e, int8_t f, uint8_t g) {
   return (struct large){a, e, f, g};
 }
+
+// Complex floating-point values or structs containing a single complex
+// floating-point value should be passed in a GPR.
+
+// CHECK: define void @f_floatcomplex(i64 %a.coerce)
+void f_floatcomplex(float __complex__ a) {}
+
+// CHECK: define i64 @f_ret_floatcomplex()
+float __complex__ f_ret_floatcomplex() {
+  return 1.0;
+}
+
+struct floatcomplex_s { float __complex__ c; };
+
+// CHECK: define void @f_floatcomplex_s_arg(i64 %a.coerce)
+void f_floatcomplex_s_arg(struct floatcomplex_s a) {}
+
+// CHECK: define i64 @f_ret_floatcomplex_s()
+struct floatcomplex_s f_ret_floatcomplex_s() {
+  return (struct floatcomplex_s){1.0};
+}
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10238,7 +10238,8 @@
   uint64_t Size = getContext().getTypeSize(Ty);
 
   // Pass floating point values via FPRs if possible.
-  if (IsFixed && Ty->isFloatingType() && FLen >= Size && ArgFPRsLeft) {
+  if (IsFixed && Ty->isFloatingType() && !Ty->isComplexType() &&
+  FLen >= Size && ArgFPRsLeft) {
 ArgFPRsLeft--;
 return ABIArgInfo::getDirect();
   }


Index: clang/test/CodeGen/riscv64-

[PATCH] D79770: [RISCV] Fix passing two floating-point values in complex separately by two GPRs on RV64

2020-05-17 Thread Jim Lin via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7ee479a760e0: [RISCV] Fix passing two floating-point values 
in complex separately by two GPRs… (authored by Jim).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79770/new/

https://reviews.llvm.org/D79770

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/riscv64-lp64-abi.c
  clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c


Index: clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c
===
--- clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c
+++ clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c
@@ -165,6 +165,35 @@
   return (struct floatcomplex_s){1.0};
 }
 
+// Complex floating-point values or structs containing a single complex
+// floating-point value should be passed in GPRs if no two FPRs is available.
+
+// CHECK: define void @f_floatcomplex_insufficient_fprs1(float %a.coerce0, 
float %a.coerce1, float %b.coerce0, float %b.coerce1, float %c.coerce0, float 
%c.coerce1, float %d.coerce0, float %d.coerce1, i64 %e.coerce)
+void f_floatcomplex_insufficient_fprs1(float __complex__ a, float __complex__ 
b,
+   float __complex__ c, float __complex__ 
d,
+   float __complex__ e) {}
+
+
+// CHECK: define void @f_floatcomplex_s_arg_insufficient_fprs1(float %0, float 
%1, float %2, float %3, float %4, float %5, float %6, float %7, i64 %e.coerce)
+void f_floatcomplex_s_arg_insufficient_fprs1(struct floatcomplex_s a,
+ struct floatcomplex_s b,
+ struct floatcomplex_s c,
+ struct floatcomplex_s d,
+ struct floatcomplex_s e) {}
+
+// CHECK: define void @f_floatcomplex_insufficient_fprs2(float %a, float 
%b.coerce0, float %b.coerce1, float %c.coerce0, float %c.coerce1, float 
%d.coerce0, float %d.coerce1, i64 %e.coerce)
+void f_floatcomplex_insufficient_fprs2(float a,
+   float __complex__ b, float __complex__ 
c,
+   float __complex__ d, float __complex__ 
e) {}
+
+
+// CHECK: define void @f_floatcomplex_s_arg_insufficient_fprs2(float %a, float 
%0, float %1, float %2, float %3, float %4, float %5, i64 %e.coerce)
+void f_floatcomplex_s_arg_insufficient_fprs2(float a,
+ struct floatcomplex_s b,
+ struct floatcomplex_s c,
+ struct floatcomplex_s d,
+ struct floatcomplex_s e) {}
+
 // Test single or two-element structs that need flattening. e.g. those
 // containing nested structs, floats in small arrays, zero-length structs etc.
 
Index: clang/test/CodeGen/riscv64-lp64-abi.c
===
--- clang/test/CodeGen/riscv64-lp64-abi.c
+++ clang/test/CodeGen/riscv64-lp64-abi.c
@@ -30,3 +30,24 @@
   uint8_t e, int8_t f, uint8_t g) {
   return (struct large){a, e, f, g};
 }
+
+// Complex floating-point values or structs containing a single complex
+// floating-point value should be passed in a GPR.
+
+// CHECK: define void @f_floatcomplex(i64 %a.coerce)
+void f_floatcomplex(float __complex__ a) {}
+
+// CHECK: define i64 @f_ret_floatcomplex()
+float __complex__ f_ret_floatcomplex() {
+  return 1.0;
+}
+
+struct floatcomplex_s { float __complex__ c; };
+
+// CHECK: define void @f_floatcomplex_s_arg(i64 %a.coerce)
+void f_floatcomplex_s_arg(struct floatcomplex_s a) {}
+
+// CHECK: define i64 @f_ret_floatcomplex_s()
+struct floatcomplex_s f_ret_floatcomplex_s() {
+  return (struct floatcomplex_s){1.0};
+}
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10238,7 +10238,8 @@
   uint64_t Size = getContext().getTypeSize(Ty);
 
   // Pass floating point values via FPRs if possible.
-  if (IsFixed && Ty->isFloatingType() && FLen >= Size && ArgFPRsLeft) {
+  if (IsFixed && Ty->isFloatingType() && !Ty->isComplexType() &&
+  FLen >= Size && ArgFPRsLeft) {
 ArgFPRsLeft--;
 return ABIArgInfo::getDirect();
   }


Index: clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c
===
--- clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c
+++ clang/test/CodeGen/riscv64-lp64f-lp64d-abi.c
@@ -165,6 +165,35 @@
   return (struct floatcomplex_s){1.0};
 }
 
+// Complex floating-point values or structs containing a single complex
+// floating-point value should be passed in GPRs if no two FPRs is available.
+
+// CHECK: define void @f_floatcomplex_insufficient_fprs1(float %a.coerce0, float %a.coerce1,

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-07-22 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

ping? Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

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[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

2021-07-22 Thread Jim Lin via Phabricator via cfe-commits
Jim updated this revision to Diff 361087.
Jim added a comment.

Recover it. Split preprocessor definitions part of D95588 
 to this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95590/new/

https://reviews.llvm.org/D95590

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -218,6 +218,46 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-32P-EXT %s
+// CHECK-32P-EXT: __riscv_p 93000
+// CHECK-32P-EXT: __riscv_zpn 93000
+// CHECK-32P-EXT: __riscv_zpsfoperand 93000
+// CHECK-32P-NOT: __riscv_zprvsfextra
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-64P-EXT %s
+// CHECK-64P-EXT: __riscv_p 93000
+// CHECK-64P-EXT: __riscv_zpn 93000
+// CHECK-64P-EXT: __riscv_zprvsfextra 93000
+// CHECK-64P-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// CHECK-ZPSFOPERAND-NOT: __riscv_p
+// CHECK-ZPSFOPERAND-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izprvsfextra0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPRVSFEXTRA-EXT %s
+// CHECK-ZPRVSFEXTRA-NOT: __riscv_p
+// CHECK-ZPRVSFEXTRA-EXT: __riscv_zprvsfextra 93000
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32iv0p10 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,6 +31,7 @@
   bool HasD = false;
   bool HasC = false;
   bool HasB = false;
+  bool HasP = false;
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
@@ -43,6 +44,9 @@
   bool HasZbr = false;
   bool HasZbs = false;
   bool HasZbt = false;
+  bool HasZpn = false;
+  bool HasZpsfoperand = false;
+  bool HasZprvsfextra = false;
   bool HasZfh = false;
   bool HasZvamo = false;
   bool HasZvlsseg = false;
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -181,6 +181,9 @@
 Builder.defineMacro("__riscv_bitmanip");
   }
 
+  if (HasP)
+Builder.defineMacro("__riscv_p", "93000");
+
   if (HasV) {
 Builder.defineMacro("__riscv_v", "1");
 Builder.defineMacro("__riscv_vector");
@@ -219,6 +222,15 @@
   if (HasZbt)
 Builder.defineMacro("__riscv_zbt", "93000");
 
+  if (HasZpn)
+Builder.defineMacro("__riscv_zpn", "93000");
+
+  if (HasZpsfoperand)
+Builder.defineMacro("__riscv_zpsfoperand", "93000");
+
+  if (HasZprvsfextra)
+Builder.defineMacro("__riscv_zprvsfextra", "93000");
+
   if (HasZfh)
 Builder.defineMacro("__riscv_zfh", "1000");
 
@@ -266,6 +278,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-p", HasP)
   .Case("experimental-v", HasV)
   .Case("experimental-zba", HasZba)
   .Case("experimental-zbb", HasZbb)
@@ -278,6 +291,9 @@
   .Case("experimental-zbr", HasZbr)
   .Case("experimental-zbs", HasZbs)
   .Case("experimental-zbt", HasZbt)
+  .Case("experimental-zpn", HasZpn)
+  .Case("experimental-zpsfoperand", HasZpsfoperand)
+  .Case("experimental-zprvsfextra", HasZprvsfextra)
   .Case("experimental-zfh", HasZfh)
   .Case("experimental-zvamo", HasZvamo)
   .Case("experimental-zvlsseg", HasZvlsseg)
@@ 

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

2021-07-22 Thread Jim Lin via Phabricator via cfe-commits
Jim updated this revision to Diff 361088.
Jim added a comment.

Recover it. Split arch version for P extension of D95588 
 to this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95589/new/

https://reviews.llvm.org/D95589

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -423,6 +423,82 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
 // RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOFLAG %s
+// RV32-EXPERIMENTAL-P-NOFLAG: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOVERS %s
+// RV32-EXPERIMENTAL-P-NOVERS: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-BADVERS %s
+// RV32-EXPERIMENTAL-P-BADVERS: error: invalid arch name 'rv32ip0p1'
+// RV32-EXPERIMENTAL-P-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-GOODVERS %s
+// RV32-EXPERIMENTAL-P-GOODVERS: "-target-feature" "+experimental-p"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-NOFLAG %s
+// RV32-EXPERIMENTAL-ZPN-NOFLAG: error: invalid arch name 'rv32izpn'
+// RV32-EXPERIMENTAL-ZPN-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-NOVERS %s
+// RV32-EXPERIMENTAL-ZPN-NOVERS: error: invalid arch name 'rv32izpn'
+// RV32-EXPERIMENTAL-ZPN-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-BADVERS %s
+// RV32-EXPERIMENTAL-ZPN-BADVERS: error: invalid arch name 'rv32izpn0p1'
+// RV32-EXPERIMENTAL-ZPN-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-GOODVERS %s
+// RV32-EXPERIMENTAL-ZPN-GOODVERS: "-target-feature" "+experimental-zpn"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG: error: invalid arch name 'rv32izpsfoperand'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS: error: invalid arch name 'rv32izpsfoperand'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS: error: invalid arch name 'rv32izpsfoperand0p1'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-GOODVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-GOODVERS: "-target-feature" "+experimental-zpsfoperand"
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64izprvsfextra -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG %s
+// RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG: error: invalid arch name 'rv64izprvsfextra'
+// RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv64-unknown-elf -march=r

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-07-22 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

In D95588#2898470 , @jrtc27 wrote:

> Oh, technically none of the clang changes belong in this patch. Those are for 
> the Clang driver and preprocessor, not the MC layer which is purely llvm.

I move the clang changes to D95589  and D95590 
.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-07-23 Thread Jim Lin via Phabricator via cfe-commits
Jim marked 8 inline comments as done.
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:442
+
+if (STI.getFeatureBits()[RISCV::FeatureExtZpsfoperand] &&
+!STI.getFeatureBits()[RISCV::Feature64Bit]) {

jrtc27 wrote:
> The table is called RISCV32POnly but you're checking for Zpsfoperand 
> (whatever that mouthful of an extension is). Which is it?
Rename RISCV32POnly to RISCV32Zpsfoperand. 
This is for the instruction with even/odd paired-register operands on RV32. 

In RISCV32Zpsfoperand, two kinds of instruction defined for the same 
instruction in spec, one for RV32 with even/odd paired-register operands 
defined in RISCV32Zpsfoperand table , the other one for RV64 with normal GPR 
operands.





Comment at: llvm/lib/Target/RISCV/RISCV.td:186-188
+   [FeatureExtZpsfoperand,
+FeatureExtZpn,
+FeatureExtZprvsfextra]>;

jrtc27 wrote:
> These aren't correct? RV64 doesn't have Zpsfoperand and RV32 doesn't have 
> Zprvsfextra.
RV64 has Zpsfoperand extension that just has normal GPRs as operands (RV32 has 
even/odd paired-register operand).

RV32 doesn't have Zprvsfextra. All of instruction in Zprvsfextra are defined in 
Predicates = [HasStdExtZprvsfextra, IsRV64].

If P is enabled, it means Zpn+Zpsfoperand enabled on RV32, and 
Zpn+Zpsfoperand+Zprvsfextra enabled on RV64.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:216
+// Dummy zero register for pairing with X0.
+def ZERO : RISCVReg<0, "0">;
+

jrtc27 wrote:
> Ew, this is a gross quirk of the register pair instructions. ZERO is not a 
> good name for it though, that's the ABI name for x0 so already taken and is 
> pretty confusing. I assume LLVM doesn't like it if you create a register pair 
> that is (X0, X0)?
Rename it to REG_PAIR_WITH_X0.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:226-228
+def GPRPair : RegisterClass<"RISCV", [untyped], 64, (add GPRPairs)> {
+  let Size = 64;
+}

jrtc27 wrote:
> IMO the register class should be GPR32Pair not GPRPair unless you also make 
> it have a sensible interpretation for RV32 (which seems like a waste of time)
Rename it to GPR32Pair.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69
 
+def sub_lo : SubRegIndex<32>;
+def sub_hi : SubRegIndex<32, 32>;

jrtc27 wrote:
> Jim wrote:
> > Jim wrote:
> > > luismarques wrote:
> > > > jrtc27 wrote:
> > > > > This assumes RV32, and is not clear it applies to register pairs
> > > > What's the best way to address this?
> > > sub_lo and sub_hi are only used for GPRPair register class to extract a 
> > > register from pair registers on RV32.
> > Do you mean that sub_lo and sub_hi only used on RV32? Does it need to 
> > rename or ..?
> Yes, these should have names that make it clear they're for each half of a 
> 2*32-bit register pair. Otherwise it sounds like they're the 32-bit hi and lo 
> halves of the 64-bit registers on RV64.
Rename it to gpr_pair_lo and gpr_pair_hi


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-07-25 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

@jrtc27 Any more feedback? Thanks.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

2022-02-08 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555
+def GPRF64  : RegisterClass<"RISCV", [f64], 64, (add GPR)>;
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
+X10_PD, X12_PD, X14_PD, X16_PD,

Is XLenRI correct for GPRPF64? RV32 has size 32.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

2022-02-10 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:557
+
+let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add

Is register pair only on RV32 for used as f64?


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[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.96

2022-02-10 Thread Jim Lin via Phabricator via cfe-commits
Jim updated this revision to Diff 407770.
Jim added a comment.
Herald added a subscriber: pcwang-thead.

Rebase


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Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -163,3 +163,12 @@
 
 .attribute arch, "rv32i_zk1p0"
 # CHECK: attribute  5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+
+.attribute arch, "rv32ip0p96"
+# CHECK: attribute  5, "rv32i2p0_p0p96_zpn0p96_zpsfoperand0p96"
+
+.attribute arch, "rv32izpn0p96"
+# CHECK: attribute  5, "rv32i2p0_zpn0p96"
+
+.attribute arch, "rv32izpsfoperand0p96"
+# CHECK: attribute  5, "rv32i2p0_zpsfoperand0p96"
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -99,6 +99,10 @@
 {"zbp", RISCVExtensionVersion{0, 93}},
 {"zbr", RISCVExtensionVersion{0, 93}},
 {"zbt", RISCVExtensionVersion{0, 93}},
+
+{"p", RISCVExtensionVersion{0, 96}},
+{"zpn", RISCVExtensionVersion{0, 96}},
+{"zpsfoperand", RISCVExtensionVersion{0, 96}},
 };
 
 static bool stripExperimentalPrefix(StringRef &Ext) {
@@ -589,7 +593,7 @@
 // The order is OK, then push it into features.
 // TODO: Use version number when setting target features
 // Currently LLVM supports only "mafdcbv".
-StringRef SupportedStandardExtension = "mafdcbv";
+StringRef SupportedStandardExtension = "mafdcbpv";
 if (!SupportedStandardExtension.contains(C))
   return createStringError(errc::invalid_argument,
"unsupported standard user-level extension '%c'",
@@ -754,6 +758,7 @@
 static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
+static const char *ImpliedExtsP[] = {"zpn", "zpsfoperand"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
@@ -768,6 +773,7 @@
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"p"}, {ImpliedExtsP}},
 {{"v"}, {ImpliedExtsV}},
 {{"zfh"}, {ImpliedExtsZfh}},
 {{"zfhmin"}, {ImpliedExtsZfhmin}},
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -211,6 +211,34 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000{{$}}
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// CHECK-P-EXT: __riscv_p 96000{{$}}
+// CHECK-P-EXT: __riscv_zpn 96000{{$}}
+// CHECK-P-EXT: __riscv_zpsfoperand 96000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 96000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpsfoperand0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpsfoperand0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// CHECK-ZPSFOPERAND-NOT: __riscv_p
+// CHECK-ZPSFOPERAND-EXT: __riscv_zpsfoperand 96000{{$}}
+
 // RUN: %clang -target riscv32-unknown-linux-gnu \
 // RUN: -march=rv32iv1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -397,6 +397,63 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBA %s
 // RV32-ZBA: "-target-feature" "+zba"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -### %s

[PATCH] D128604: [RISCV] Support Zbpbo extension v0.9.11

2022-07-11 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:471
+   Sched<[WriteCMix, ReadCMix, ReadCMix, ReadCMix]>;
 def FSR  : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">,
Sched<[WriteFSReg, ReadFSReg, ReadFSReg, ReadFSReg]>;

FSR and FSRI only exist on RV32 for Zbpbo.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:492
+
+let Predicates = [HasStdExtZbbOrZbpbo] in
 def CLZ  : RVBUnary<0b011, 0b0, 0b001, OPC_OP_IMM, "clz">,

CLZ only exist on RV32 for Zbpbo.



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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2022-07-11 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

In D95588#3622052 , @sunshaoce wrote:

> Hello @Jim! We are developing the P extension, are you still maintaining this 
> patch? Or would you mind co-development together?

Yes, I am still on developing the P extension. But it seems spec has the issue 
https://github.com/riscv/riscv-p-spec/issues/137 need to clarify.
And some instruction (CLZ, FSR and FSRI) in Zbpbo only be aliased to B 
extension on RV32. It is complicated if P extension are enabled on RV64.


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[PATCH] D71982: [docs] Update path to clang-tools-extra

2019-12-29 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

There shows "Context not available".
Could you update for this?


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[PATCH] D71982: [docs] Update path to clang-tools-extra

2019-12-30 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang-tools-extra/docs/clang-tidy/Contributing.rst:66
 
-Once you are done, change to the ``llvm/tools/clang/tools/extra`` directory, 
and
+Once you are done, change to the ``llvm/clang-tools-extra`` directory, and
 let's start!

I am no sure that "llvm/clang-tools-extra" should be replaced as 
"llvm-project/clang-tools-extra".
Maybe someone would confuse with "llvm", "llvm-project" and "llvm-project/llvm"



Comment at: clang/www/hacking.html:301
 
-  It is also possible to https://llvm.org/docs/GettingStarted.html#sending-patches-with-git";>use 
git to contribute to Clang.
+  It is also possible to https://llvm.org/docs/GettingStarted.html#checkout-llvm-from-git";>use git 
to contribute to Clang.
 

This change should be in a separate patch.


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[PATCH] D72014: [PowerPC]: Add powerpcspe target triple subarch component

2019-12-30 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

Could you add tests in llvm/unittests/ADT/TripleTest.cpp


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[PATCH] D71982: [docs] Update path to clang-tools-extra

2020-01-01 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

@AlexanderLanin
git commit --amend --author="What-is-your-name " ?


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[PATCH] D71982: [docs] Update path to clang-tools-extra

2020-01-02 Thread Jim Lin via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8188c998ffa4: [docs] Update path to clang-tools-extra 
(authored by AlexanderLanin, committed by Jim).

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  clang-tools-extra/docs/clang-tidy/Contributing.rst
  clang-tools-extra/docs/pp-trace.rst

Index: clang-tools-extra/docs/pp-trace.rst
===
--- clang-tools-extra/docs/pp-trace.rst
+++ clang-tools-extra/docs/pp-trace.rst
@@ -104,16 +104,16 @@
 
   ---
   - Callback: FileChanged
-Loc: "c:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/pp-trace-include.cpp:1:1"
+Loc: "c:/Clang/llvm/clang-tools-extra/test/pp-trace/pp-trace-include.cpp:1:1"
 Reason: EnterFile
 FileType: C_User
 PrevFID: (invalid)
 (etc.)
   - Callback: FileChanged
-Loc: "D:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/pp-trace-include.cpp:5:1"
+Loc: "D:/Clang/llvm/clang-tools-extra/test/pp-trace/pp-trace-include.cpp:5:1"
 Reason: ExitFile
 FileType: C_User
-PrevFID: "D:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/Input/Level1B.h"
+PrevFID: "D:/Clang/llvm/clang-tools-extra/test/pp-trace/Input/Level1B.h"
   - Callback: EndOfMainFile
   ...
 
@@ -172,7 +172,7 @@
 Example:::
 
   - Callback: FileChanged
-Loc: "D:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/pp-trace-include.cpp:1:1"
+Loc: "D:/Clang/llvm/clang-tools-extra/test/pp-trace/pp-trace-include.cpp:1:1"
 Reason: EnterFile
 FileType: C_User
 PrevFID: (invalid)
@@ -248,8 +248,8 @@
 FileName: "Input/Level1B.h"
 IsAngled: false
 FilenameRange: "Input/Level1B.h"
-File: "D:/Clang/llvmnewmod/tools/clang/tools/extra/test/pp-trace/Input/Level1B.h"
-SearchPath: "D:/Clang/llvmnewmod/tools/clang/tools/extra/test/pp-trace"
+File: "D:/Clang/llvmnewmod/clang-tools-extra/test/pp-trace/Input/Level1B.h"
+SearchPath: "D:/Clang/llvmnewmod/clang-tools-extra/test/pp-trace"
 RelativePath: "Input/Level1B.h"
 Imported: (null)
 
@@ -271,8 +271,8 @@
 Example:::
 
   - Callback: moduleImport
-ImportLoc: "d:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/pp-trace-modules.cpp:4:2"
-Path: [{Name: Level1B, Loc: "d:/Clang/llvmnewmod/tools/clang/tools/extra/test/pp-trace/pp-trace-modules.cpp:4:9"}, {Name: Level2B, Loc: "d:/Clang/llvmnewmod/tools/clang/tools/extra/test/pp-trace/pp-trace-modules.cpp:4:17"}]
+ImportLoc: "d:/Clang/llvm/clang-tools-extra/test/pp-trace/pp-trace-modules.cpp:4:2"
+Path: [{Name: Level1B, Loc: "d:/Clang/llvmnewmod/clang-tools-extra/test/pp-trace/pp-trace-modules.cpp:4:9"}, {Name: Level2B, Loc: "d:/Clang/llvmnewmod/clang-tools-extra/test/pp-trace/pp-trace-modules.cpp:4:17"}]
 Imported: Level2B
 
 `EndOfMainFile `_ Callback
@@ -309,7 +309,7 @@
 Example:::
 
   - Callback: Ident
-Loc: "D:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/pp-trace-ident.cpp:3:1"
+Loc: "D:/Clang/llvm/clang-tools-extra/test/pp-trace/pp-trace-ident.cpp:3:1"
 str: "$Id$"
 
 `PragmaDirective `_ Callback
@@ -329,7 +329,7 @@
 Example:::
 
   - Callback: PragmaDirective
-Loc: "D:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/pp-trace-pragma.cpp:3:1"
+Loc: "D:/Clang/llvm/clang-tools-extra/test/pp-trace/pp-trace-pragma.cpp:3:1"
 Introducer: PIK_HashPragma
 
 `PragmaComment `_ Callback
@@ -350,7 +350,7 @@
 Example:::
 
   - Callback: PragmaComment
-Loc: "D:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/pp-trace-pragma.cpp:3:1"
+Loc: "D:/Clang/llvm/clang-tools-extra/test/pp-trace/pp-trace-pragma.cpp:3:1"
 Kind: library
 Str: kernel32.lib
 
@@ -372,7 +372,7 @@
 Example:::
 
   - Callback: PragmaDetectMismatch
-Loc: "D:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/pp-trace-pragma.cpp:3:1"
+Loc: "D:/Clang/llvm/clang-tools-extra/test/pp-trace/pp-trace-pragma.cpp:3:1"
 Name: name
 Value: value
 
@@ -393,7 +393,7 @@
 Example:::
 
   - Callback: PragmaDebug
-Loc: "D:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/pp-trace-pragma.cpp:3:1"
+Loc: "D:/Clang/llvm/clang-tools-extra/test/pp-trace/pp-trace-pragma.cpp:3:1"
 DebugType: warning
 
 `PragmaMessage `_ Callback
@@ -415,7 +415,7 @@
 Example:::
 
   - Callback: PragmaMessage
-Loc: "D:/Clang/llvm/tools/clang/tools/extra/test/pp-trace/pp-trace-pragma.cpp:3:1"
+Loc: "D:/Clang/llvm/clang-tools-extra/test/pp-trace/pp-trace-pragma.cpp:3:1"
 Na

[PATCH] D72320: [NFC] Use isX86() instead of getArch()

2020-01-07 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Jim added reviewers: MaskRay, craig.topper.
Herald added subscribers: llvm-commits, cfe-commits, rupprecht, hiraditya.
Herald added a reviewer: jhenderson.
Herald added projects: clang, LLVM.

This is a clean up for https://reviews.llvm.org/D72247.


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Files:
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/AST/Mangle.cpp
  clang/lib/CodeGen/CGOpenMPRuntime.cpp
  clang/lib/CodeGen/CodeGenFunction.cpp
  clang/lib/Driver/ToolChains/Arch/X86.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Darwin.cpp
  clang/lib/Sema/SemaExpr.cpp
  llvm/lib/Analysis/TargetLibraryInfo.cpp
  llvm/lib/MC/MCObjectFileInfo.cpp
  llvm/tools/llvm-objdump/MachODump.cpp

Index: llvm/tools/llvm-objdump/MachODump.cpp
===
--- llvm/tools/llvm-objdump/MachODump.cpp
+++ llvm/tools/llvm-objdump/MachODump.cpp
@@ -7650,8 +7650,7 @@
   }
   outs() << "\n";
 } else {
-  unsigned int Arch = MachOOF->getArch();
-  if (Arch == Triple::x86_64 || Arch == Triple::x86) {
+  if (MachOOF->getArchTriple().isX86()) {
 outs() << format("\t.byte 0x%02x #bad opcode\n",
  *(Bytes.data() + Index) & 0xff);
 Size = 1; // skip exactly one illegible byte and move on.
@@ -7716,8 +7715,7 @@
   IP->printInst(&Inst, PC, AnnotationsStr, *STI, outs());
   outs() << "\n";
 } else {
-  unsigned int Arch = MachOOF->getArch();
-  if (Arch == Triple::x86_64 || Arch == Triple::x86) {
+  if (MachOOF->getArchTriple().isX86()) {
 outs() << format("\t.byte 0x%02x #bad opcode\n",
  *(Bytes.data() + Index) & 0xff);
 InstSize = 1; // skip exactly one illegible byte and move on.
Index: llvm/lib/MC/MCObjectFileInfo.cpp
===
--- llvm/lib/MC/MCObjectFileInfo.cpp
+++ llvm/lib/MC/MCObjectFileInfo.cpp
@@ -40,8 +40,7 @@
 return true;
 
   // And the iOS simulator.
-  if (T.isiOS() &&
-  (T.getArch() == Triple::x86_64 || T.getArch() == Triple::x86))
+  if (T.isiOS() && T.isX86())
 return true;
 
   return false;
@@ -192,7 +191,7 @@
 Ctx->getMachOSection("__LD", "__compact_unwind", MachO::S_ATTR_DEBUG,
  SectionKind::getReadOnly());
 
-if (T.getArch() == Triple::x86_64 || T.getArch() == Triple::x86)
+if (T.isX86())
   CompactUnwindDwarfEHFrameOnly = 0x0400;  // UNWIND_X86_64_MODE_DWARF
 else if (T.getArch() == Triple::aarch64 || T.getArch() == Triple::aarch64_32)
   CompactUnwindDwarfEHFrameOnly = 0x0300;  // UNWIND_ARM64_MODE_DWARF
Index: llvm/lib/Analysis/TargetLibraryInfo.cpp
===
--- llvm/lib/Analysis/TargetLibraryInfo.cpp
+++ llvm/lib/Analysis/TargetLibraryInfo.cpp
@@ -379,10 +379,8 @@
   case Triple::TvOS:
   case Triple::WatchOS:
 TLI.setUnavailable(LibFunc_exp10l);
-if (!T.isWatchOS() && (T.isOSVersionLT(7, 0) ||
-   (T.isOSVersionLT(9, 0) &&
-(T.getArch() == Triple::x86 ||
- T.getArch() == Triple::x86_64 {
+if (!T.isWatchOS() &&
+(T.isOSVersionLT(7, 0) || (T.isOSVersionLT(9, 0) && T.isX86( {
   TLI.setUnavailable(LibFunc_exp10);
   TLI.setUnavailable(LibFunc_exp10f);
 } else {
Index: clang/lib/Sema/SemaExpr.cpp
===
--- clang/lib/Sema/SemaExpr.cpp
+++ clang/lib/Sema/SemaExpr.cpp
@@ -15359,8 +15359,7 @@
   // These manglings don't do anything on non-Windows or non-x86 platforms, so
   // we don't need parameter type sizes.
   const llvm::Triple &TT = S.Context.getTargetInfo().getTriple();
-  if (!TT.isOSWindows() || (TT.getArch() != llvm::Triple::x86 &&
-TT.getArch() != llvm::Triple::x86_64))
+  if (!TT.isOSWindows() || !TT.isX86())
 return false;
 
   // If this is C++ and this isn't an extern "C" function, parameters do not
Index: clang/lib/Driver/ToolChains/Darwin.cpp
===
--- clang/lib/Driver/ToolChains/Darwin.cpp
+++ clang/lib/Driver/ToolChains/Darwin.cpp
@@ -124,8 +124,7 @@
   AddMachOArch(Args, CmdArgs);
 
   // Use -force_cpusubtype_ALL on x86 by default.
-  if (getToolChain().getArch() == llvm::Triple::x86 ||
-  getToolChain().getArch() == llvm::Triple::x86_64 ||
+  if (getToolChain().getTriple().isX86() ||
   Args.hasArg(options::OPT_force__cpusubtype__ALL))
 CmdArgs.push_back("-force_cpusubtype_ALL");
 
@@ -1836,9 +1835,7 @@
   DarwinEnvironmentKind Environment = OSTarget->getEnvironment();
   // Recognize iOS targets with an x86 architecture as the iOS simulator.
   if (Environment == NativeEnvironment && Pla

[PATCH] D72320: [NFC] Use isX86() instead of getArch()

2020-01-07 Thread Jim Lin via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes.
Closed by commit rGab1bcda851d9: [NFC] Use isX86() instead of getArch() 
(authored by Jim).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72320/new/

https://reviews.llvm.org/D72320

Files:
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/AST/Mangle.cpp
  clang/lib/CodeGen/CGOpenMPRuntime.cpp
  clang/lib/CodeGen/CodeGenFunction.cpp
  clang/lib/Driver/ToolChains/Arch/X86.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Darwin.cpp
  clang/lib/Sema/SemaExpr.cpp
  llvm/lib/Analysis/TargetLibraryInfo.cpp
  llvm/lib/MC/MCObjectFileInfo.cpp
  llvm/tools/llvm-objdump/MachODump.cpp

Index: llvm/tools/llvm-objdump/MachODump.cpp
===
--- llvm/tools/llvm-objdump/MachODump.cpp
+++ llvm/tools/llvm-objdump/MachODump.cpp
@@ -7650,8 +7650,7 @@
   }
   outs() << "\n";
 } else {
-  unsigned int Arch = MachOOF->getArch();
-  if (Arch == Triple::x86_64 || Arch == Triple::x86) {
+  if (MachOOF->getArchTriple().isX86()) {
 outs() << format("\t.byte 0x%02x #bad opcode\n",
  *(Bytes.data() + Index) & 0xff);
 Size = 1; // skip exactly one illegible byte and move on.
@@ -7716,8 +7715,7 @@
   IP->printInst(&Inst, PC, AnnotationsStr, *STI, outs());
   outs() << "\n";
 } else {
-  unsigned int Arch = MachOOF->getArch();
-  if (Arch == Triple::x86_64 || Arch == Triple::x86) {
+  if (MachOOF->getArchTriple().isX86()) {
 outs() << format("\t.byte 0x%02x #bad opcode\n",
  *(Bytes.data() + Index) & 0xff);
 InstSize = 1; // skip exactly one illegible byte and move on.
Index: llvm/lib/MC/MCObjectFileInfo.cpp
===
--- llvm/lib/MC/MCObjectFileInfo.cpp
+++ llvm/lib/MC/MCObjectFileInfo.cpp
@@ -40,8 +40,7 @@
 return true;
 
   // And the iOS simulator.
-  if (T.isiOS() &&
-  (T.getArch() == Triple::x86_64 || T.getArch() == Triple::x86))
+  if (T.isiOS() && T.isX86())
 return true;
 
   return false;
@@ -192,7 +191,7 @@
 Ctx->getMachOSection("__LD", "__compact_unwind", MachO::S_ATTR_DEBUG,
  SectionKind::getReadOnly());
 
-if (T.getArch() == Triple::x86_64 || T.getArch() == Triple::x86)
+if (T.isX86())
   CompactUnwindDwarfEHFrameOnly = 0x0400;  // UNWIND_X86_64_MODE_DWARF
 else if (T.getArch() == Triple::aarch64 || T.getArch() == Triple::aarch64_32)
   CompactUnwindDwarfEHFrameOnly = 0x0300;  // UNWIND_ARM64_MODE_DWARF
Index: llvm/lib/Analysis/TargetLibraryInfo.cpp
===
--- llvm/lib/Analysis/TargetLibraryInfo.cpp
+++ llvm/lib/Analysis/TargetLibraryInfo.cpp
@@ -379,10 +379,8 @@
   case Triple::TvOS:
   case Triple::WatchOS:
 TLI.setUnavailable(LibFunc_exp10l);
-if (!T.isWatchOS() && (T.isOSVersionLT(7, 0) ||
-   (T.isOSVersionLT(9, 0) &&
-(T.getArch() == Triple::x86 ||
- T.getArch() == Triple::x86_64 {
+if (!T.isWatchOS() &&
+(T.isOSVersionLT(7, 0) || (T.isOSVersionLT(9, 0) && T.isX86( {
   TLI.setUnavailable(LibFunc_exp10);
   TLI.setUnavailable(LibFunc_exp10f);
 } else {
Index: clang/lib/Sema/SemaExpr.cpp
===
--- clang/lib/Sema/SemaExpr.cpp
+++ clang/lib/Sema/SemaExpr.cpp
@@ -15359,8 +15359,7 @@
   // These manglings don't do anything on non-Windows or non-x86 platforms, so
   // we don't need parameter type sizes.
   const llvm::Triple &TT = S.Context.getTargetInfo().getTriple();
-  if (!TT.isOSWindows() || (TT.getArch() != llvm::Triple::x86 &&
-TT.getArch() != llvm::Triple::x86_64))
+  if (!TT.isOSWindows() || !TT.isX86())
 return false;
 
   // If this is C++ and this isn't an extern "C" function, parameters do not
Index: clang/lib/Driver/ToolChains/Darwin.cpp
===
--- clang/lib/Driver/ToolChains/Darwin.cpp
+++ clang/lib/Driver/ToolChains/Darwin.cpp
@@ -124,8 +124,7 @@
   AddMachOArch(Args, CmdArgs);
 
   // Use -force_cpusubtype_ALL on x86 by default.
-  if (getToolChain().getArch() == llvm::Triple::x86 ||
-  getToolChain().getArch() == llvm::Triple::x86_64 ||
+  if (getToolChain().getTriple().isX86() ||
   Args.hasArg(options::OPT_force__cpusubtype__ALL))
 CmdArgs.push_back("-force_cpusubtype_ALL");
 
@@ -1836,9 +1835,7 @@
   DarwinEnvironmentKind Environment = OSTarget->getEnvironment();
   // Recognize iOS targets with an x86 architecture as the iOS simulator.
   if (Environment == NativeEnvironment && Platform != MacOS &&
-  OSTarget->canInferSi

[PATCH] D72434: Support offset of member designator with the arrow for __builtin_offsetof

2020-01-08 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Jim added a reviewer: eli.friedman.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Push array index 0 into offsets to support offset of member designator x->b.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D72434

Files:
  clang/lib/Parse/ParseExpr.cpp
  clang/test/Parser/offsetof.c


Index: clang/test/Parser/offsetof.c
===
--- clang/test/Parser/offsetof.c
+++ clang/test/Parser/offsetof.c
@@ -3,5 +3,3 @@
 struct a { struct { int b; } x[2]; };
 
 int a = __builtin_offsetof(struct a, x; // expected-error{{expected ')'}} 
expected-note{{to match this '('}}
-// FIXME: This actually shouldn't give an error
-int b = __builtin_offsetof(struct a, x->b); // expected-error{{expected ')'}} 
expected-note{{to match this '('}}
Index: clang/lib/Parse/ParseExpr.cpp
===
--- clang/lib/Parse/ParseExpr.cpp
+++ clang/lib/Parse/ParseExpr.cpp
@@ -2165,7 +2165,6 @@
 Comps.back().U.IdentInfo = Tok.getIdentifierInfo();
 Comps.back().LocStart = Comps.back().LocEnd = ConsumeToken();
 
-// FIXME: This loop leaks the index expressions on error.
 while (1) {
   if (Tok.is(tok::period)) {
 // offsetof-member-designator: offsetof-member-designator '.' 
identifier
@@ -2200,6 +2199,28 @@
 
 ST.consumeClose();
 Comps.back().LocEnd = ST.getCloseLocation();
+  } else if (Tok.is(tok::arrow)) {
+// offsetof-member-designator: offsetof-member-design '->' identifier
+// Push array index 0 into offsets.
+Comps.push_back(Sema::OffsetOfComponent());
+Comps.back().isBrackets = true;
+SourceLocation SavedLoc = ConsumeToken();
+Comps.back().LocStart = Comps.back().LocEnd = SavedLoc;
+Res = Actions.ActOnIntegerConstant(SourceLocation(), 0);
+Comps.back().U.E = Res.get();
+
+Comps.push_back(Sema::OffsetOfComponent());
+Comps.back().isBrackets = false;
+Comps.back().LocStart = SavedLoc;
+
+if (Tok.isNot(tok::identifier)) {
+  Diag(Tok, diag::err_expected) << tok::identifier;
+  SkipUntil(tok::r_paren, StopAtSemi);
+  return ExprError();
+}
+Comps.back().U.IdentInfo = Tok.getIdentifierInfo();
+Comps.back().LocEnd = ConsumeToken();
+
   } else {
 if (Tok.isNot(tok::r_paren)) {
   PT.consumeClose();


Index: clang/test/Parser/offsetof.c
===
--- clang/test/Parser/offsetof.c
+++ clang/test/Parser/offsetof.c
@@ -3,5 +3,3 @@
 struct a { struct { int b; } x[2]; };
 
 int a = __builtin_offsetof(struct a, x; // expected-error{{expected ')'}} expected-note{{to match this '('}}
-// FIXME: This actually shouldn't give an error
-int b = __builtin_offsetof(struct a, x->b); // expected-error{{expected ')'}} expected-note{{to match this '('}}
Index: clang/lib/Parse/ParseExpr.cpp
===
--- clang/lib/Parse/ParseExpr.cpp
+++ clang/lib/Parse/ParseExpr.cpp
@@ -2165,7 +2165,6 @@
 Comps.back().U.IdentInfo = Tok.getIdentifierInfo();
 Comps.back().LocStart = Comps.back().LocEnd = ConsumeToken();
 
-// FIXME: This loop leaks the index expressions on error.
 while (1) {
   if (Tok.is(tok::period)) {
 // offsetof-member-designator: offsetof-member-designator '.' identifier
@@ -2200,6 +2199,28 @@
 
 ST.consumeClose();
 Comps.back().LocEnd = ST.getCloseLocation();
+  } else if (Tok.is(tok::arrow)) {
+// offsetof-member-designator: offsetof-member-design '->' identifier
+// Push array index 0 into offsets.
+Comps.push_back(Sema::OffsetOfComponent());
+Comps.back().isBrackets = true;
+SourceLocation SavedLoc = ConsumeToken();
+Comps.back().LocStart = Comps.back().LocEnd = SavedLoc;
+Res = Actions.ActOnIntegerConstant(SourceLocation(), 0);
+Comps.back().U.E = Res.get();
+
+Comps.push_back(Sema::OffsetOfComponent());
+Comps.back().isBrackets = false;
+Comps.back().LocStart = SavedLoc;
+
+if (Tok.isNot(tok::identifier)) {
+  Diag(Tok, diag::err_expected) << tok::identifier;
+  SkipUntil(tok::r_paren, StopAtSemi);
+  return ExprError();
+}
+Comps.back().U.IdentInfo = Tok.getIdentifierInfo();
+Comps.back().LocEnd = ConsumeToken();
+
   } else {
 if (Tok.isNot(tok::r_paren)) {
   PT.consumeClose();
___
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[PATCH] D72825: [NFC] Fix options name typo

2020-01-16 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Jim added reviewers: efriedma, MaskRay.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
Jim edited the summary of this revision.

1. -ftree_loop_im -> -ftree-loop-im
2. -ftree_loop_ivcanon -> -ftree-loop-ivcanon
3. -ftree_loop_linear -> -ftree-loop-linear


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D72825

Files:
  clang/include/clang/Driver/Options.td
  clang/test/Driver/clang_f_opts.c


Index: clang/test/Driver/clang_f_opts.c
===
--- clang/test/Driver/clang_f_opts.c
+++ clang/test/Driver/clang_f_opts.c
@@ -292,9 +292,9 @@
 // RUN: -frename-registers\
 // RUN: -fschedule-insns2 \
 // RUN: -fsingle-precision-constant   \
-// RUN: -ftree_loop_im\
-// RUN: -ftree_loop_ivcanon   \
-// RUN: -ftree_loop_linear\
+// RUN: -ftree-loop-im\
+// RUN: -ftree-loop-ivcanon   \
+// RUN: -ftree-loop-linear\
 // RUN: -funsafe-loop-optimizations   \
 // RUN: -fuse-linker-plugin   \
 // RUN: -fvect-cost-model \
@@ -432,9 +432,9 @@
 // CHECK-WARNING-DAG: optimization flag '-frename-registers' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fschedule-insns2' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fsingle-precision-constant' is not 
supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_im' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_ivcanon' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_linear' is not supported
+// CHECK-WARNING-DAG: optimization flag '-ftree-loop-im' is not supported
+// CHECK-WARNING-DAG: optimization flag '-ftree-loop-ivcanon' is not supported
+// CHECK-WARNING-DAG: optimization flag '-ftree-loop-linear' is not supported
 // CHECK-WARNING-DAG: optimization flag '-funsafe-loop-optimizations' is not 
supported
 // CHECK-WARNING-DAG: optimization flag '-fuse-linker-plugin' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fvect-cost-model' is not supported
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3297,9 +3297,9 @@
 defm tls_model : BooleanFFlag<"tls-model">, Group;
 defm tracer : BooleanFFlag<"tracer">, 
Group;
 defm tree_dce : BooleanFFlag<"tree-dce">, 
Group;
-defm tree_loop_im : BooleanFFlag<"tree_loop_im">,  
Group;
-defm tree_loop_ivcanon : BooleanFFlag<"tree_loop_ivcanon">,  
Group;
-defm tree_loop_linear : BooleanFFlag<"tree_loop_linear">,  
Group;
+defm tree_loop_im : BooleanFFlag<"tree-loop-im">,  
Group;
+defm tree_loop_ivcanon : BooleanFFlag<"tree-loop-ivcanon">,  
Group;
+defm tree_loop_linear : BooleanFFlag<"tree-loop-linear">,  
Group;
 defm tree_salias : BooleanFFlag<"tree-salias">, Group;
 defm tree_ter : BooleanFFlag<"tree-ter">, 
Group;
 defm tree_vectorizer_verbose : BooleanFFlag<"tree-vectorizer-verbose">, 
Group;


Index: clang/test/Driver/clang_f_opts.c
===
--- clang/test/Driver/clang_f_opts.c
+++ clang/test/Driver/clang_f_opts.c
@@ -292,9 +292,9 @@
 // RUN: -frename-registers\
 // RUN: -fschedule-insns2 \
 // RUN: -fsingle-precision-constant   \
-// RUN: -ftree_loop_im\
-// RUN: -ftree_loop_ivcanon   \
-// RUN: -ftree_loop_linear\
+// RUN: -ftree-loop-im\
+// RUN: -ftree-loop-ivcanon   \
+// RUN: -ftree-loop-linear\
 // RUN: -funsafe-loop-optimizations   \
 // RUN: -fuse-linker-plugin   \
 // RUN: -fvect-cost-model \
@@ -432,9 +432,9 @@
 // CHECK-WARNING-DAG: optimization flag '-frename-registers' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fschedule-insns2' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fsingle-precision-constant' is 

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

2021-01-27 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Jim added reviewers: craig.topper, HsiangKai, jrtc27, kito-cheng, luismarques.
Herald added subscribers: frasercrmck, NickHung, evandro, apazos, 
sameer.abuasal, pzheng, s.egerton, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Support arch feature for experimental 'P' extension with version 0.9.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95589

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -369,6 +369,25 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
 // RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOFLAG %s
+// RV32-EXPERIMENTAL-P-NOFLAG: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOVERS %s
+// RV32-EXPERIMENTAL-P-NOVERS: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOVERS: experimental extension requires explicit 
version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p1 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-BADVERS %s
+// RV32-EXPERIMENTAL-P-BADVERS: error: invalid arch name 'rv32ip0p1'
+// RV32-EXPERIMENTAL-P-BADVERS: unsupported version number 0.1 for 
experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p9 
-menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-GOODVERS %s
+// RV32-EXPERIMENTAL-P-GOODVERS: "-target-feature" "+experimental-p"
+
 // RUN: %clang -target riscv32-unknown-elf -march=rv32iv -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-V-NOFLAG %s
 // RV32-EXPERIMENTAL-V-NOFLAG: error: invalid arch name 'rv32iv'
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -62,6 +62,8 @@
   Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
   Ext == "zbr" || Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
 return RISCVExtensionVersion{"0", "93"};
+  if (Ext == "p")
+return RISCVExtensionVersion{"0", "9"};
   if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
 return RISCVExtensionVersion{"1", "0"};
   if (Ext == "zfh")
@@ -427,6 +429,9 @@
   Features.push_back("+experimental-zbs");
   Features.push_back("+experimental-zbt");
   break;
+case 'p':
+  Features.push_back("+experimental-p");
+  break;
 case 'v':
   Features.push_back("+experimental-v");
   Features.push_back("+experimental-zvamo");


Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -369,6 +369,25 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
 // RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOFLAG %s
+// RV32-EXPERIMENTAL-P-NOFLAG: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOVERS %s
+// RV32-EXPERIMENTAL-P-NOVERS: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-BADVERS %s
+// RV32-EXPERIMENTAL-P-BADVERS: error: invalid arch name 'rv32ip0p1'
+// RV32-EXPERIMENTAL-P-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p9 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-GOODVERS %s
+// RV32-EXPERIMENTAL-P-GOODVERS: "-target-feature" "+experimental-p"
+
 // RUN: %clang -targe

[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

2021-01-27 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Jim added reviewers: craig.topper, HsiangKai, kito-cheng, jrtc27, luismarques.
Herald added subscribers: frasercrmck, NickHung, evandro, apazos, 
sameer.abuasal, pzheng, s.egerton, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Repository:
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https://reviews.llvm.org/D95590

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -109,6 +109,12 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
+// RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions -march=rv32ip0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions -march=rv64ip0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// CHECK-P-EXT: __riscv_p 9
+
 // RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions \
 // RUN:   -march=rv32iv1p0 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,6 +31,7 @@
   bool HasD = false;
   bool HasC = false;
   bool HasB = false;
+  bool HasP = false;
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -149,6 +149,9 @@
 Builder.defineMacro("__riscv_bitmanip");
   }
 
+  if (HasP)
+Builder.defineMacro("__riscv_p", "9");
+
   if (HasV) {
 Builder.defineMacro("__riscv_v", "100");
 Builder.defineMacro("__riscv_vector");
@@ -210,6 +213,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-p", HasP)
   .Case("experimental-v", HasV)
   .Case("experimental-zba", HasZba)
   .Case("experimental-zbb", HasZbb)
@@ -244,6 +248,8 @@
   HasC = true;
 else if (Feature == "+experimental-b")
   HasB = true;
+else if (Feature == "+experimental-p")
+  HasP = true;
 else if (Feature == "+experimental-v")
   HasV = true;
 else if (Feature == "+experimental-zba")


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -109,6 +109,12 @@
 // CHECK-DOUBLE-NOT: __riscv_float_abi_soft
 // CHECK-DOUBLE-NOT: __riscv_float_abi_single
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions -march=rv32ip0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions -march=rv64ip0p9 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// CHECK-P-EXT: __riscv_p 9
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN:   -march=rv32iv1p0 -x c -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,6 +31,7 @@
   bool HasD = false;
   bool HasC = false;
   bool HasB = false;
+  bool HasP = false;
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -149,6 +149,9 @@
 Builder.defineMacro("__riscv_bitmanip");
   }
 
+  if (HasP)
+Builder.defineMacro("__riscv_p", "9");
+
   if (HasV) {
 Builder.defineMacro("__riscv_v", "100");
 Builder.defineMacro("__riscv_vector");
@@ -210,6 +213,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-p", HasP)
   .Case("experimental-v", HasV)
   .Case("experimental-zba", HasZba)
   .Case("experimental-zbb", HasZbb)
@@ -244,6 +248,8 @@
   HasC = true;
 else if (Feature == "+experimental-b")
   HasB = true;
+else 

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

2021-02-03 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang/test/CodeGen/RISCV/vadd.c:22
+{
+return __builtin_rvv_vadd_vv_i8m1_vl(arg_0, arg_1, arg_2);
+}

Is it necessary with prefix "__builtin_"?
Refer to 
https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv_intrinsic_funcs_vl/06_vector_integer_arithmetic_functions.md.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-09-15 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

Any feedback? I think this patch is good enough to be accepted.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-09-21 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

In D95588#3003090 , @Jim wrote:

> Any feedback? I think this patch is good enough to be accepted.

Ping? Thanks.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-09-24 Thread Jim Lin via Phabricator via cfe-commits
Jim marked 7 inline comments as done.
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:909
+
+// kmar64 has a aliased instruction kmada32 belong to zpn sub-extension on 
RV64.
+let DecoderNamespace = "RISCV32Zpsfoperand_",

jrtc27 wrote:
> Having the same instruction in two different extensions under two different 
> names is insane. Currently this implementation lets you use the "wrong" name 
> for kmar64 with Zpn. But I would prefer the spec weren't crazy.
I am still working on fixing it (from spec or ...) . But it is spec issue.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:228
+
+def GPR32Pair : RegisterClass<"RISCV", [untyped], 64, (add GPR32Pairs)> {
+  let Size = 64;

jrtc27 wrote:
> Why is this untyped?
GPR32Pair has untyped type. 
In code generation, It captures some operation with i64 type supported by 
Zpsoperand to untyped during legalization. 
In my mind, untyped is used to be represented special type don't need any 
legalization.
I refer to ARMRegisterInfo.td that defines GPRPair with untyped.


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[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

2021-02-08 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:11127
+def err_riscvv_builtin_not_useable : Error<
+   "builtin requires 'V' extension support to be enabled">;
 } // end of sema component.

Add blank line.
Is it "err_riscvv_builtin_not_enabled"?



Comment at: clang/lib/Basic/Targets/RISCV.cpp:89
+#define BUILTIN(ID, TYPE, ATTRS)   
\
+  {"__builtin_rvv_" #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
+#include "clang/Basic/BuiltinsRISCV.def"

Builtins for other extension don't have "__builtin_rvv_" prefix.


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-02-09 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:2
 
-RISCVV_BUILTIN(vadd_vv_i8m1_vl, "q8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m1_m_vl, "q8Scq8bq8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_vl, "q4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_m_vl, "q4Ssq4bq4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_vl, "q2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_m_vl, "q2Siq2bq2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_vl, "q1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_vl, "q16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_m_vl, "q16Scq16bq16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_vl, "q8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_m_vl, "q8Ssq8bq8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_vl, "q4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_m_vl, "q4Siq4bq4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_vl, "q2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_vl, "q32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_m_vl, "q32Scq32bq32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_vl, "q16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_m_vl, "q16Ssq16bq16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_vl, "q8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_m_vl, "q8Siq8bq8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_vl, "q4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_vl, "q64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_m_vl, "q64Scq64bq64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_vl, "q32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_m_vl, "q32Ssq32bq32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_vl, "q16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_m_vl, "q16Siq16bq16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_vl, "q8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_vl, "q4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_m_vl, "q4Scq4bq4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_vl, "q2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_m_vl, "q2Ssq2bq2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_vl, "q1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_m_vl, "q1Siq1bq1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_vl, "q2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_m_vl, "q2Scq2bq2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_vl, "q1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_m_vl, "q1Ssq1bq1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_vl, "q1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_m_vl, "q1Scq1bq1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_vl, "q8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_m_vl, "q8Scq8bq8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_vl, "q4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_m_vl, "q4Ssq4bq4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_vl, "q2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_m_vl, "q2Siq2bq2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_vl, "q1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_vl, "q16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_m_vl, "q16Scq16bq16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_vl, "q8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_m_vl, "q8Ssq8bq8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_vl, "q4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_m_vl, "q4Siq4bq4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_vl, "q2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_vl, "q32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_m_vl, "q32Scq32bq32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_vl, "q16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_m_vl, "q16Ssq16bq16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_vl, "q8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_m_vl, "q8Siq8bq8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_vl, "q4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_vl, "q64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_m_vl, "q64Scq64bq64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_vl, "q32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_m_vl, "q32Ssq32bq32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_vl, "q16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_m_vl, "q16Siq16bq16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_vl, "q8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_vl, "q4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_m_vl, "q4Scq4bq4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_vl, "q2Ssq2SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_m_vl, "q2Ssq2bq2Ssq2SsSsz"

[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-02-09 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: llvm/docs/CommandGuide/tblgen.rst:141
 
-  Generate RISCV compressed instructions.
+  Generate RISC-V compressed instructions.
 

It is typo fix. Could you fix it in a separate patch?


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[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

2021-02-09 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:2
 
-RISCVV_BUILTIN(vadd_vv_i8m1_vl, "q8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m1_m_vl, "q8Scq8bq8Scq8Scq8Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_vl, "q4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m1_m_vl, "q4Ssq4bq4Ssq4Ssq4Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_vl, "q2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m1_m_vl, "q2Siq2bq2Siq2Siq2Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_vl, "q1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiq1SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_vl, "q16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m2_m_vl, "q16Scq16bq16Scq16Scq16Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_vl, "q8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m2_m_vl, "q8Ssq8bq8Ssq8Ssq8Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_vl, "q4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m2_m_vl, "q4Siq4bq4Siq4Siq4Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_vl, "q2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiq2SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_vl, "q32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m4_m_vl, "q32Scq32bq32Scq32Scq32Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_vl, "q16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m4_m_vl, "q16Ssq16bq16Ssq16Ssq16Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_vl, "q8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m4_m_vl, "q8Siq8bq8Siq8Siq8Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_vl, "q4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiq4SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_vl, "q64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8m8_m_vl, "q64Scq64bq64Scq64Scq64Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_vl, "q32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16m8_m_vl, "q32Ssq32bq32Ssq32Ssq32Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_vl, "q16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32m8_m_vl, "q16Siq16bq16Siq16Siq16Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_vl, "q8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiq8SWiz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_vl, "q4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf2_m_vl, "q4Scq4bq4Scq4Scq4Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_vl, "q2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf2_m_vl, "q2Ssq2bq2Ssq2Ssq2Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_vl, "q1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i32mf2_m_vl, "q1Siq1bq1Siq1Siq1Siz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_vl, "q2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf4_m_vl, "q2Scq2bq2Scq2Scq2Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_vl, "q1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i16mf4_m_vl, "q1Ssq1bq1Ssq1Ssq1Ssz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_vl, "q1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vv_i8mf8_m_vl, "q1Scq1bq1Scq1Scq1Scz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_vl, "q8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m1_m_vl, "q8Scq8bq8Scq8ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_vl, "q4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m1_m_vl, "q4Ssq4bq4Ssq4SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_vl, "q2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m1_m_vl, "q2Siq2bq2Siq2SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_vl, "q1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_vl, "q16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m2_m_vl, "q16Scq16bq16Scq16ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_vl, "q8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m2_m_vl, "q8Ssq8bq8Ssq8SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_vl, "q4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m2_m_vl, "q4Siq4bq4Siq4SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_vl, "q2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_vl, "q32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m4_m_vl, "q32Scq32bq32Scq32ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_vl, "q16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m4_m_vl, "q16Ssq16bq16Ssq16SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_vl, "q8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m4_m_vl, "q8Siq8bq8Siq8SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_vl, "q4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_vl, "q64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8m8_m_vl, "q64Scq64bq64Scq64ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_vl, "q32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16m8_m_vl, "q32Ssq32bq32Ssq32SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_vl, "q16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i32m8_m_vl, "q16Siq16bq16Siq16SiSiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_vl, "q8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiSWiz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_vl, "q4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i8mf2_m_vl, "q4Scq4bq4Scq4ScScz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_vl, "q2Ssq2SsSsz", "n")
-RISCVV_BUILTIN(vadd_vx_i16mf2_m_vl, "q2Ssq2bq2Ssq2SsSsz"

[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

2021-02-16 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:89
+#define BUILTIN(ID, TYPE, ATTRS)   
\
+  {"__builtin_rvv_" #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
+#include "clang/Basic/BuiltinsRISCV.def"

craig.topper wrote:
> khchen wrote:
> > Jim wrote:
> > > Builtins for other extension don't have "__builtin_rvv_" prefix.
> > maybe we could rename BuiltinsRISCV.def as BuiltinsRVV.def, and other 
> > extension defines their own .def file?
> > 
> > @Jim do you have any suggestion?
> Don't most targets pass the full name with the prefix to the BUILTIN macro?
Most of targets pass the full name with the prefix to the BUILTIN macro.
It can define the full name with the prefix in BuiltinsRISCV.def


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[PATCH] D93446: [RISCV] Add vadd with mask and without mask builtin.

2021-02-17 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:89
+#define BUILTIN(ID, TYPE, ATTRS)   
\
+  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
+#include "clang/Basic/BuiltinsRISCV.def"

Should it put together with `getTargetBuiltins` function?




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[PATCH] D103313: [RISCV][Clang] Implement support for zmmul-experimental

2021-06-09 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

It should add arch string tests such as in clang/test/Driver/riscv-arch.c.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-06-15 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

Any comments? Thanks.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-06-21 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

ping? Thanks.


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[PATCH] D107248: [RISCV] Define preprocessor definitions for 'P' extension

2021-08-01 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107248

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -218,6 +218,46 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-32P-EXT %s
+// CHECK-32P-EXT: __riscv_p 93000
+// CHECK-32P-EXT: __riscv_zpn 93000
+// CHECK-32P-EXT: __riscv_zpsfoperand 93000
+// CHECK-32P-NOT: __riscv_zprvsfextra
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-64P-EXT %s
+// CHECK-64P-EXT: __riscv_p 93000
+// CHECK-64P-EXT: __riscv_zpn 93000
+// CHECK-64P-EXT: __riscv_zprvsfextra 93000
+// CHECK-64P-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// CHECK-ZPSFOPERAND-NOT: __riscv_p
+// CHECK-ZPSFOPERAND-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izprvsfextra0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPRVSFEXTRA-EXT %s
+// CHECK-ZPRVSFEXTRA-NOT: __riscv_p
+// CHECK-ZPRVSFEXTRA-EXT: __riscv_zprvsfextra 93000
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32iv0p10 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,6 +31,7 @@
   bool HasD = false;
   bool HasC = false;
   bool HasB = false;
+  bool HasP = false;
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
@@ -43,6 +44,9 @@
   bool HasZbr = false;
   bool HasZbs = false;
   bool HasZbt = false;
+  bool HasZpn = false;
+  bool HasZpsfoperand = false;
+  bool HasZprvsfextra = false;
   bool HasZfh = false;
   bool HasZvamo = false;
   bool HasZvlsseg = false;
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -181,6 +181,9 @@
 Builder.defineMacro("__riscv_bitmanip");
   }
 
+  if (HasP)
+Builder.defineMacro("__riscv_p", "93000");
+
   if (HasV) {
 Builder.defineMacro("__riscv_v", "1");
 Builder.defineMacro("__riscv_vector");
@@ -219,6 +222,15 @@
   if (HasZbt)
 Builder.defineMacro("__riscv_zbt", "93000");
 
+  if (HasZpn)
+Builder.defineMacro("__riscv_zpn", "93000");
+
+  if (HasZpsfoperand)
+Builder.defineMacro("__riscv_zpsfoperand", "93000");
+
+  if (HasZprvsfextra)
+Builder.defineMacro("__riscv_zprvsfextra", "93000");
+
   if (HasZfh)
 Builder.defineMacro("__riscv_zfh", "1000");
 
@@ -266,6 +278,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-p", HasP)
   .Case("experimental-v", HasV)
   .Case("experimental-zba", HasZba)
   .Case("experimental-zbb", HasZbb)
@@ -278,6 +291,9 @@
   .Case("experimental-zbr", HasZbr)
   .Case("experimental-zbs", HasZbs)
   .Case("experimental-zbt", HasZbt)
+  .Case("experimental-zpn", HasZpn)
+  .Case("experimental-zpsfoperand", HasZpsfoperand)

[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

2021-08-01 Thread Jim Lin via Phabricator via cfe-commits
Jim updated this revision to Diff 363371.
Jim added a comment.

Rebase


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Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -218,6 +218,46 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-32P-EXT %s
+// CHECK-32P-EXT: __riscv_p 93000
+// CHECK-32P-EXT: __riscv_zpn 93000
+// CHECK-32P-EXT: __riscv_zpsfoperand 93000
+// CHECK-32P-NOT: __riscv_zprvsfextra
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-64P-EXT %s
+// CHECK-64P-EXT: __riscv_p 93000
+// CHECK-64P-EXT: __riscv_zpn 93000
+// CHECK-64P-EXT: __riscv_zprvsfextra 93000
+// CHECK-64P-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// CHECK-ZPSFOPERAND-NOT: __riscv_p
+// CHECK-ZPSFOPERAND-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izprvsfextra0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPRVSFEXTRA-EXT %s
+// CHECK-ZPRVSFEXTRA-NOT: __riscv_p
+// CHECK-ZPRVSFEXTRA-EXT: __riscv_zprvsfextra 93000
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32iv0p10 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,6 +31,7 @@
   bool HasD = false;
   bool HasC = false;
   bool HasB = false;
+  bool HasP = false;
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
@@ -43,6 +44,9 @@
   bool HasZbr = false;
   bool HasZbs = false;
   bool HasZbt = false;
+  bool HasZpn = false;
+  bool HasZpsfoperand = false;
+  bool HasZprvsfextra = false;
   bool HasZfh = false;
   bool HasZvamo = false;
   bool HasZvlsseg = false;
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -181,6 +181,9 @@
 Builder.defineMacro("__riscv_bitmanip");
   }
 
+  if (HasP)
+Builder.defineMacro("__riscv_p", "93000");
+
   if (HasV) {
 Builder.defineMacro("__riscv_v", "1");
 Builder.defineMacro("__riscv_vector");
@@ -219,6 +222,15 @@
   if (HasZbt)
 Builder.defineMacro("__riscv_zbt", "93000");
 
+  if (HasZpn)
+Builder.defineMacro("__riscv_zpn", "93000");
+
+  if (HasZpsfoperand)
+Builder.defineMacro("__riscv_zpsfoperand", "93000");
+
+  if (HasZprvsfextra)
+Builder.defineMacro("__riscv_zprvsfextra", "93000");
+
   if (HasZfh)
 Builder.defineMacro("__riscv_zfh", "1000");
 
@@ -266,6 +278,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-p", HasP)
   .Case("experimental-v", HasV)
   .Case("experimental-zba", HasZba)
   .Case("experimental-zbb", HasZbb)
@@ -278,6 +291,9 @@
   .Case("experimental-zbr", HasZbr)
   .Case("experimental-zbs", HasZbs)
   .Case("experimental-zbt", HasZbt)
+  .Case("experimental-zpn", HasZpn)
+  .Case("experimental-zpsfoperand", HasZpsfoperand)
+  .Case("experimental-zprvsfextra", HasZprvsfextra)
   .Case("experimental-zfh", HasZfh)
   .Case("experimental-zvamo", HasZvamo)
   .Case("experimental-zvlsseg", HasZvlsseg)
@@ -300,6 +316,8 @@
   HasC = true;
 else if (Feature == "+experimental-b")
   HasB = 

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

2021-08-01 Thread Jim Lin via Phabricator via cfe-commits
Jim updated this revision to Diff 363372.
Jim added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95589/new/

https://reviews.llvm.org/D95589

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -423,6 +423,82 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
 // RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOFLAG %s
+// RV32-EXPERIMENTAL-P-NOFLAG: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOVERS %s
+// RV32-EXPERIMENTAL-P-NOVERS: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-BADVERS %s
+// RV32-EXPERIMENTAL-P-BADVERS: error: invalid arch name 'rv32ip0p1'
+// RV32-EXPERIMENTAL-P-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-GOODVERS %s
+// RV32-EXPERIMENTAL-P-GOODVERS: "-target-feature" "+experimental-p"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-NOFLAG %s
+// RV32-EXPERIMENTAL-ZPN-NOFLAG: error: invalid arch name 'rv32izpn'
+// RV32-EXPERIMENTAL-ZPN-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-NOVERS %s
+// RV32-EXPERIMENTAL-ZPN-NOVERS: error: invalid arch name 'rv32izpn'
+// RV32-EXPERIMENTAL-ZPN-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-BADVERS %s
+// RV32-EXPERIMENTAL-ZPN-BADVERS: error: invalid arch name 'rv32izpn0p1'
+// RV32-EXPERIMENTAL-ZPN-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-GOODVERS %s
+// RV32-EXPERIMENTAL-ZPN-GOODVERS: "-target-feature" "+experimental-zpn"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG: error: invalid arch name 'rv32izpsfoperand'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS: error: invalid arch name 'rv32izpsfoperand'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS: error: invalid arch name 'rv32izpsfoperand0p1'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-GOODVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-GOODVERS: "-target-feature" "+experimental-zpsfoperand"
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64izprvsfextra -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG %s
+// RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG: error: invalid arch name 'rv64izprvsfextra'
+// RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64izprvsfextra -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -che

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-08-03 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

Kindly ping? Thanks.


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[PATCH] D95590: [RISCV] Define preprocessor definitions for 'P' extension

2021-08-09 Thread Jim Lin via Phabricator via cfe-commits
Jim updated this revision to Diff 365358.
Jim added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95590/new/

https://reviews.llvm.org/D95590

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Preprocessor/riscv-target-features.c

Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -218,6 +218,46 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-32P-EXT %s
+// CHECK-32P-EXT: __riscv_p 93000
+// CHECK-32P-EXT: __riscv_zpn 93000
+// CHECK-32P-EXT: __riscv_zpsfoperand 93000
+// CHECK-32P-NOT: __riscv_zprvsfextra
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-64P-EXT %s
+// CHECK-64P-EXT: __riscv_p 93000
+// CHECK-64P-EXT: __riscv_zpn 93000
+// CHECK-64P-EXT: __riscv_zprvsfextra 93000
+// CHECK-64P-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 93000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpsfoperand0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// CHECK-ZPSFOPERAND-NOT: __riscv_p
+// CHECK-ZPSFOPERAND-EXT: __riscv_zpsfoperand 93000
+
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izprvsfextra0p93 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPRVSFEXTRA-EXT %s
+// CHECK-ZPRVSFEXTRA-NOT: __riscv_p
+// CHECK-ZPRVSFEXTRA-EXT: __riscv_zprvsfextra 93000
+
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32iv0p10 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -31,6 +31,7 @@
   bool HasD = false;
   bool HasC = false;
   bool HasB = false;
+  bool HasP = false;
   bool HasV = false;
   bool HasZba = false;
   bool HasZbb = false;
@@ -43,6 +44,9 @@
   bool HasZbr = false;
   bool HasZbs = false;
   bool HasZbt = false;
+  bool HasZpn = false;
+  bool HasZpsfoperand = false;
+  bool HasZprvsfextra = false;
   bool HasZfh = false;
   bool HasZvamo = false;
   bool HasZvlsseg = false;
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -181,6 +181,9 @@
 Builder.defineMacro("__riscv_bitmanip");
   }
 
+  if (HasP)
+Builder.defineMacro("__riscv_p", "93000");
+
   if (HasV) {
 Builder.defineMacro("__riscv_v", "1");
 Builder.defineMacro("__riscv_vector");
@@ -219,6 +222,15 @@
   if (HasZbt)
 Builder.defineMacro("__riscv_zbt", "93000");
 
+  if (HasZpn)
+Builder.defineMacro("__riscv_zpn", "93000");
+
+  if (HasZpsfoperand)
+Builder.defineMacro("__riscv_zpsfoperand", "93000");
+
+  if (HasZprvsfextra)
+Builder.defineMacro("__riscv_zprvsfextra", "93000");
+
   if (HasZfh)
 Builder.defineMacro("__riscv_zfh", "1000");
 
@@ -266,6 +278,7 @@
   .Case("d", HasD)
   .Case("c", HasC)
   .Case("experimental-b", HasB)
+  .Case("experimental-p", HasP)
   .Case("experimental-v", HasV)
   .Case("experimental-zba", HasZba)
   .Case("experimental-zbb", HasZbb)
@@ -278,6 +291,9 @@
   .Case("experimental-zbr", HasZbr)
   .Case("experimental-zbs", HasZbs)
   .Case("experimental-zbt", HasZbt)
+  .Case("experimental-zpn", HasZpn)
+  .Case("experimental-zpsfoperand", HasZpsfoperand)
+  .Case("experimental-zprvsfextra", HasZprvsfextra)
   .Case("experimental-zfh", HasZfh)
   .Case("experimental-zvamo", HasZvamo)
   .Case("experimental-zvlsseg", HasZvlsseg)
@@ -300,6 +316,8 @@
   HasC = true;
 else if (Feature == "+experimental-b")
   HasB = 

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

2021-08-09 Thread Jim Lin via Phabricator via cfe-commits
Jim updated this revision to Diff 365359.
Jim added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95589/new/

https://reviews.llvm.org/D95589

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -423,6 +423,82 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-ZBA %s
 // RV32-EXPERIMENTAL-ZBA: "-target-feature" "+experimental-zba"
 
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOFLAG %s
+// RV32-EXPERIMENTAL-P-NOFLAG: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-NOVERS %s
+// RV32-EXPERIMENTAL-P-NOVERS: error: invalid arch name 'rv32ip'
+// RV32-EXPERIMENTAL-P-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-BADVERS %s
+// RV32-EXPERIMENTAL-P-BADVERS: error: invalid arch name 'rv32ip0p1'
+// RV32-EXPERIMENTAL-P-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ip0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-P-GOODVERS %s
+// RV32-EXPERIMENTAL-P-GOODVERS: "-target-feature" "+experimental-p"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-NOFLAG %s
+// RV32-EXPERIMENTAL-ZPN-NOFLAG: error: invalid arch name 'rv32izpn'
+// RV32-EXPERIMENTAL-ZPN-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-NOVERS %s
+// RV32-EXPERIMENTAL-ZPN-NOVERS: error: invalid arch name 'rv32izpn'
+// RV32-EXPERIMENTAL-ZPN-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-BADVERS %s
+// RV32-EXPERIMENTAL-ZPN-BADVERS: error: invalid arch name 'rv32izpn0p1'
+// RV32-EXPERIMENTAL-ZPN-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpn0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPN-GOODVERS %s
+// RV32-EXPERIMENTAL-ZPN-GOODVERS: "-target-feature" "+experimental-zpn"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG: error: invalid arch name 'rv32izpsfoperand'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS: error: invalid arch name 'rv32izpsfoperand'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-NOVERS: experimental extension requires explicit version number
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS: error: invalid arch name 'rv32izpsfoperand0p1'
+// RV32-EXPERIMENTAL-ZPSFOPERAND-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izpsfoperand0p93 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZPSFOPERAND-GOODVERS %s
+// RV32-EXPERIMENTAL-ZPSFOPERAND-GOODVERS: "-target-feature" "+experimental-zpsfoperand"
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64izprvsfextra -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG %s
+// RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG: error: invalid arch name 'rv64izprvsfextra'
+// RV64-EXPERIMENTAL-ZPRVSFEXTRA-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv64-unknown-elf -march=rv64izprvsfextra -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -che

[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-08-10 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

Hi @jrtc27, any further feedback? Thanks.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-08-16 Thread Jim Lin via Phabricator via cfe-commits
Jim marked an inline comment as done.
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCV.td:186-188
+   [FeatureExtZpsfoperand,
+FeatureExtZpn,
+FeatureExtZprvsfextra]>;

jrtc27 wrote:
> Jim wrote:
> > jrtc27 wrote:
> > > These aren't correct? RV64 doesn't have Zpsfoperand and RV32 doesn't have 
> > > Zprvsfextra.
> > RV64 has Zpsfoperand extension that just has normal GPRs as operands (RV32 
> > has even/odd paired-register operand).
> > 
> > RV32 doesn't have Zprvsfextra. All of instruction in Zprvsfextra are 
> > defined in Predicates = [HasStdExtZprvsfextra, IsRV64].
> > 
> > If P is enabled, it means Zpn+Zpsfoperand enabled on RV32, and 
> > Zpn+Zpsfoperand+Zprvsfextra enabled on RV64.
> My concern is that the internal inflexibility is going to leak out of LLVM, 
> such as into the .riscv.attributes section, and thus produce broken binaries 
> because they claim they need Zprvsfextra on RV32, which is an invalid 
> combination.
> 
> And if Zpsfoperand exists for RV64 then it shouldn't be called 
> `Paired-register operand 'P' Instructions`, because the operands are only 
> paired on RV32.
I upload a new patch https://reviews.llvm.org/D108189 to support P extension 's 
arch string.
If rv32izprvsfextra (Zprvsfextra on RV32) accepted from *.s arch attribute, it 
emits error message to forbid this invalid combination.
Before emitting _zprvsfextra string, it would check RV64 is enabled.

If llc is given -mattr=+experimental-zprvsfextra on RV32, it would be ignored.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-06-26 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

Any comments? Thanks.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-07-04 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

Ping? Thanks.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-07-12 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69
 
+def sub_lo : SubRegIndex<32>;
+def sub_hi : SubRegIndex<32, 32>;

luismarques wrote:
> jrtc27 wrote:
> > This assumes RV32, and is not clear it applies to register pairs
> What's the best way to address this?
sub_lo and sub_hi are only used for GPRPair register class to extract a 
register from pair registers on RV32.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2021-07-12 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69
 
+def sub_lo : SubRegIndex<32>;
+def sub_hi : SubRegIndex<32, 32>;

Jim wrote:
> luismarques wrote:
> > jrtc27 wrote:
> > > This assumes RV32, and is not clear it applies to register pairs
> > What's the best way to address this?
> sub_lo and sub_hi are only used for GPRPair register class to extract a 
> register from pair registers on RV32.
Do you mean that sub_lo and sub_hi only used on RV32? Does it need to rename or 
..?


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[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

2021-03-04 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1703
+}
+  }
+  Ms.emplace_back(Multilib);

Do you have plan to support other kind of options to build multilib?


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[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

2021-03-04 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1744
+  // which multi-lib should be used.
+  return ScanGCCMultilibConfig(D, TargetTriple, Path, Args, MultilibOutput,
+   Result);

scanGCCMultilibConfig ?


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[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.96

2022-06-01 Thread Jim Lin via Phabricator via cfe-commits
Jim updated this revision to Diff 433612.
Jim added a comment.
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Herald added a project: All.

Rebase


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Files:
  clang/test/Driver/riscv-arch.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -178,3 +178,12 @@
 
 .attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+
+.attribute arch, "rv32ip0p96"
+# CHECK: attribute  5, "rv32i2p0_p0p96_zpn0p96_zpsfoperand0p96"
+
+.attribute arch, "rv32izpn0p96"
+# CHECK: attribute  5, "rv32i2p0_zpn0p96"
+
+.attribute arch, "rv32izpsfoperand0p96"
+# CHECK: attribute  5, "rv32i2p0_zpsfoperand0p96"
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -105,6 +105,10 @@
 {"zbr", RISCVExtensionVersion{0, 93}},
 {"zbt", RISCVExtensionVersion{0, 93}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
+
+{"p", RISCVExtensionVersion{0, 96}},
+{"zpn", RISCVExtensionVersion{0, 96}},
+{"zpsfoperand", RISCVExtensionVersion{0, 96}},
 };
 
 static bool stripExperimentalPrefix(StringRef &Ext) {
@@ -595,7 +599,7 @@
 // The order is OK, then push it into features.
 // TODO: Use version number when setting target features
 // Currently LLVM supports only "mafdcbv".
-StringRef SupportedStandardExtension = "mafdcbv";
+StringRef SupportedStandardExtension = "mafdcbpv";
 if (!SupportedStandardExtension.contains(C))
   return createStringError(errc::invalid_argument,
"unsupported standard user-level extension '%c'",
@@ -769,6 +773,7 @@
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
+static const char *ImpliedExtsP[] = {"zpn", "zpsfoperand"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
@@ -783,6 +788,7 @@
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
+{{"p"}, {ImpliedExtsP}},
 {{"v"}, {ImpliedExtsV}},
 {{"zdinx"}, {ImpliedExtsZdinx}},
 {{"zfh"}, {ImpliedExtsZfh}},
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -222,6 +222,34 @@
 // CHECK-ZBT-NOT: __riscv_b
 // CHECK-ZBT-EXT: __riscv_zbt 93000{{$}}
 
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32ip0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64ip0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s
+// CHECK-P-EXT: __riscv_p 96000{{$}}
+// CHECK-P-EXT: __riscv_zpn 96000{{$}}
+// CHECK-P-EXT: __riscv_zpsfoperand 96000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpn0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpn0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPN-EXT %s
+// CHECK-ZPN-NOT: __riscv_p
+// CHECK-ZPN-EXT: __riscv_zpn 96000{{$}}
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv32izpsfoperand0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64izpsfoperand0p96 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZPSFOPERAND-EXT %s
+// CHECK-ZPSFOPERAND-NOT: __riscv_p
+// CHECK-ZPSFOPERAND-EXT: __riscv_zpsfoperand 96000{{$}}
+
 // RUN: %clang -target riscv32-unknown-linux-gnu \
 // RUN: -march=rv32iv1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -452,6 +452,63 @@
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBA %s
 // RV32-ZBA: "-target-feature" "+zba"
 
+// RUN: %clang -target r

[PATCH] D156507: [RISCV] Upgrade Zihintntl extension to version 1.0 and move out of experimental state.

2023-07-27 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
jdoerfert, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, hiraditya, arichardson.
Herald added a project: All.
Jim requested review of this revision.
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Herald added projects: clang, LLVM.

Zihintntl has been ratified from May 2023 according to 
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions.


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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/nontemporal-scalable.ll
  llvm/test/CodeGen/RISCV/nontemporal.ll
  llvm/test/CodeGen/RISCV/prefetch.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zihintntl-invalid.s
  llvm/test/MC/RISCV/rv32zihintntl-valid.s
  llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
  llvm/test/MC/RISCV/rv32zihintntlc-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntlc-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-valid.s
@@ -1,15 +1,15 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
-# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
 
 # CHECK-ASM-AND-OBJ: ntl.p1
 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
Index: llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
 
 c.ntl.p1 1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 c.ntl.pall 2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntl-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: llvm-mc -

[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

2023-08-21 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:3
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d \
+// RUN: -target-feature +f -target-feature +d -disable-O0-optnone \
+// RUN: -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - %s | \

zve64d has implied f and d.



Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:90
+//
+vfloat32m1_t add_f32(vfloat32m1_t a, vfloat32m1_t b) {
+  return a + b;

Do we support operation for vfloat16 here?


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[PATCH] D158402: [Clang][RISCV] Add vcreate intrinsics for RVV tuple types

2023-08-21 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:2833
   }
+  let Name = "vcreate_v",
+  UnMaskedPolicyScheme = NonePolicy,

Can we add a blank line before this.



Comment at: clang/include/clang/Basic/riscv_vector.td:2848
+  }] in {
+// foreach type = TypeList in {
+  foreach nf = NFList in {

Does this forget to be removed?


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[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

2023-08-21 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:3
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d \
+// RUN: -target-feature +f -target-feature +d -disable-O0-optnone \
+// RUN: -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - %s | \

Jim wrote:
> zve64d has implied f and d.
I misunderstand it. Please ignore the comment.


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[PATCH] D156686: [AST] Simplify Type::isSizelessBuiltinType(). NFC.

2023-07-31 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Herald added subscribers: ctetreau, s.egerton, simoncook.
Herald added a project: All.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, wangpc.
Herald added a project: clang.

Reuse isSVESizelessBuiltinType() and isRVVSizelessBuiltinType().


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Files:
  clang/lib/AST/Type.cpp


Index: clang/lib/AST/Type.cpp
===
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -2353,14 +2353,14 @@
 }
 
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType())
+return true;
+
+  if (isRVVSizelessBuiltinType())
+return true;
+
   if (const BuiltinType *BT = getAs()) {
 switch (BT->getKind()) {
-  // SVE Types
-#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/AArch64SVEACLETypes.def"
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
-  return true;
   // WebAssembly reference types
 #define WASM_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/WebAssemblyReferenceTypes.def"


Index: clang/lib/AST/Type.cpp
===
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -2353,14 +2353,14 @@
 }
 
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType())
+return true;
+
+  if (isRVVSizelessBuiltinType())
+return true;
+
   if (const BuiltinType *BT = getAs()) {
 switch (BT->getKind()) {
-  // SVE Types
-#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/AArch64SVEACLETypes.def"
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
-  return true;
   // WebAssembly reference types
 #define WASM_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/WebAssemblyReferenceTypes.def"
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[PATCH] D156686: [AST] Simplify Type::isSizelessBuiltinType(). NFC.

2023-07-31 Thread Jim Lin via Phabricator via cfe-commits
Jim updated this revision to Diff 545921.
Jim added a comment.

Address comment.


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Files:
  clang/lib/AST/Type.cpp


Index: clang/lib/AST/Type.cpp
===
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -2353,14 +2353,11 @@
 }
 
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType() || isRVVSizelessBuiltinType())
+return true;
+
   if (const BuiltinType *BT = getAs()) {
 switch (BT->getKind()) {
-  // SVE Types
-#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/AArch64SVEACLETypes.def"
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
-  return true;
   // WebAssembly reference types
 #define WASM_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/WebAssemblyReferenceTypes.def"


Index: clang/lib/AST/Type.cpp
===
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -2353,14 +2353,11 @@
 }
 
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType() || isRVVSizelessBuiltinType())
+return true;
+
   if (const BuiltinType *BT = getAs()) {
 switch (BT->getKind()) {
-  // SVE Types
-#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/AArch64SVEACLETypes.def"
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
-  return true;
   // WebAssembly reference types
 #define WASM_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/WebAssemblyReferenceTypes.def"
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[PATCH] D156686: [AST] Simplify Type::isSizelessBuiltinType(). NFC.

2023-08-01 Thread Jim Lin via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1c1066797c5b: [AST] Simplify Type::isSizelessBuiltinType(). 
NFC. (authored by Jim).

Repository:
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Files:
  clang/lib/AST/Type.cpp


Index: clang/lib/AST/Type.cpp
===
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -2353,14 +2353,11 @@
 }
 
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType() || isRVVSizelessBuiltinType())
+return true;
+
   if (const BuiltinType *BT = getAs()) {
 switch (BT->getKind()) {
-  // SVE Types
-#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/AArch64SVEACLETypes.def"
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
-  return true;
   // WebAssembly reference types
 #define WASM_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/WebAssemblyReferenceTypes.def"


Index: clang/lib/AST/Type.cpp
===
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -2353,14 +2353,11 @@
 }
 
 bool Type::isSizelessBuiltinType() const {
+  if (isSVESizelessBuiltinType() || isRVVSizelessBuiltinType())
+return true;
+
   if (const BuiltinType *BT = getAs()) {
 switch (BT->getKind()) {
-  // SVE Types
-#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/AArch64SVEACLETypes.def"
-#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
-#include "clang/Basic/RISCVVTypes.def"
-  return true;
   // WebAssembly reference types
 #define WASM_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
 #include "clang/Basic/WebAssemblyReferenceTypes.def"
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[PATCH] D152793: [RISCV] Add MC layer support for Zicfiss.

2023-08-01 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:33
+let Uses = [SSP] in {
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class RV_SSPop _rd, bits<5> _rs1, string opcodestr, string argstr> :

Two `let` lines can be merged?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:58
+def SSLoadX5: RV_SSPop<0b00101, 0b0, "ssload", "x5">;
+let Defs = [SSP] in {
+def SSPopChkX1: RV_SSPop<0b0, 0b1, "sspopchk", "x1">;

Add a blank line before this line.


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[PATCH] D157353: [RISCV] Remove pre-defined macro test for b extension. NFC.

2023-08-07 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, 
the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, eopXD.
Herald added a project: clang.

B extension has been removed.


Repository:
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Files:
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -16,8 +16,6 @@
 // CHECK-NOT: __riscv_fsqrt {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
-// CHECK-NOT: __riscv_b {{.*$}}
-// CHECK-NOT: __riscv_bitmanip {{.*$}}
 // CHECK-NOT: __riscv_zihintntl {{.*$}}
 // CHECK-NOT: __riscv_zba {{.*$}}
 // CHECK-NOT: __riscv_zbb {{.*$}}
@@ -165,7 +163,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izba -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
-// CHECK-ZBA-NOT: __riscv_b
 // CHECK-ZBA-EXT: __riscv_zba 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -180,7 +177,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbb -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
-// CHECK-ZBB-NOT: __riscv_b
 // CHECK-ZBB-EXT: __riscv_zbb 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -195,7 +191,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbc -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
-// CHECK-ZBC-NOT: __riscv_b
 // CHECK-ZBC-EXT: __riscv_zbc 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -210,7 +205,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbs -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s
-// CHECK-ZBS-NOT: __riscv_b
 // CHECK-ZBS-EXT: __riscv_zbs 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -16,8 +16,6 @@
 // CHECK-NOT: __riscv_fsqrt {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
-// CHECK-NOT: __riscv_b {{.*$}}
-// CHECK-NOT: __riscv_bitmanip {{.*$}}
 // CHECK-NOT: __riscv_zihintntl {{.*$}}
 // CHECK-NOT: __riscv_zba {{.*$}}
 // CHECK-NOT: __riscv_zbb {{.*$}}
@@ -165,7 +163,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izba -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
-// CHECK-ZBA-NOT: __riscv_b
 // CHECK-ZBA-EXT: __riscv_zba 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -180,7 +177,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbb -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
-// CHECK-ZBB-NOT: __riscv_b
 // CHECK-ZBB-EXT: __riscv_zbb 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -195,7 +191,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbc -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
-// CHECK-ZBC-NOT: __riscv_b
 // CHECK-ZBC-EXT: __riscv_zbc 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -210,7 +205,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbs -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s
-// CHECK-ZBS-NOT: __riscv_b
 // CHECK-ZBS-EXT: __riscv_zbs 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
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[PATCH] D157353: [RISCV] Remove pre-defined macro test for b extension. NFC.

2023-08-07 Thread Jim Lin via Phabricator via cfe-commits
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG767ca3a70d6d: [RISCV] Remove pre-defined macro test for b 
extension. NFC. (authored by Jim).

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/test/Preprocessor/riscv-target-features.c


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -16,8 +16,6 @@
 // CHECK-NOT: __riscv_fsqrt {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
-// CHECK-NOT: __riscv_b {{.*$}}
-// CHECK-NOT: __riscv_bitmanip {{.*$}}
 // CHECK-NOT: __riscv_zihintntl {{.*$}}
 // CHECK-NOT: __riscv_zba {{.*$}}
 // CHECK-NOT: __riscv_zbb {{.*$}}
@@ -165,7 +163,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izba -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
-// CHECK-ZBA-NOT: __riscv_b
 // CHECK-ZBA-EXT: __riscv_zba 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -180,7 +177,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbb -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
-// CHECK-ZBB-NOT: __riscv_b
 // CHECK-ZBB-EXT: __riscv_zbb 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -195,7 +191,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbc -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
-// CHECK-ZBC-NOT: __riscv_b
 // CHECK-ZBC-EXT: __riscv_zbc 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -210,7 +205,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbs -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s
-// CHECK-ZBS-NOT: __riscv_b
 // CHECK-ZBS-EXT: __riscv_zbs 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \


Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -16,8 +16,6 @@
 // CHECK-NOT: __riscv_fsqrt {{.*$}}
 // CHECK-NOT: __riscv_c {{.*$}}
 // CHECK-NOT: __riscv_compressed {{.*$}}
-// CHECK-NOT: __riscv_b {{.*$}}
-// CHECK-NOT: __riscv_bitmanip {{.*$}}
 // CHECK-NOT: __riscv_zihintntl {{.*$}}
 // CHECK-NOT: __riscv_zba {{.*$}}
 // CHECK-NOT: __riscv_zbb {{.*$}}
@@ -165,7 +163,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izba -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBA-EXT %s
-// CHECK-ZBA-NOT: __riscv_b
 // CHECK-ZBA-EXT: __riscv_zba 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -180,7 +177,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbb -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBB-EXT %s
-// CHECK-ZBB-NOT: __riscv_b
 // CHECK-ZBB-EXT: __riscv_zbb 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -195,7 +191,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbc -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBC-EXT %s
-// CHECK-ZBC-NOT: __riscv_b
 // CHECK-ZBC-EXT: __riscv_zbc 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
@@ -210,7 +205,6 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izbs -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZBS-EXT %s
-// CHECK-ZBS-NOT: __riscv_b
 // CHECK-ZBS-EXT: __riscv_zbs 100{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
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[PATCH] D154596: [RISCV] Fix required features checking with empty string

2023-07-06 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Herald added subscribers: jobnoorman, VincentWu, vkmr, luismarques, 
sameer.abuasal, s.egerton, benna, psnobl, PkmX, rogfer01, shiva0217, 
kito-cheng, simoncook, arichardson.
Herald added a project: All.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, eopXD.
Herald added a project: clang.

In our downstream, we define some intrinsics that don't require any
extension enabled. Such as

TARGET_BUILTIN(__builtin_riscv_xxx, "LiLi", "nc", "")

But `split` function's `KeepEmpty` argument isn't True. Got the error message

error: builtin requires at least one of the following extensions support to be 
enabled : ''

when we use our customized intrinsic.


Repository:
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Files:
  clang/lib/Sema/SemaChecking.cpp


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4481,7 +4481,7 @@
   bool FeatureMissing = false;
   SmallVector ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  Features.split(ReqFeatures, ',');
+  Features.split(ReqFeatures, ',', -1, false);
 
   // Check if each required feature is included
   for (StringRef F : ReqFeatures) {


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4481,7 +4481,7 @@
   bool FeatureMissing = false;
   SmallVector ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  Features.split(ReqFeatures, ',');
+  Features.split(ReqFeatures, ',', -1, false);
 
   // Check if each required feature is included
   for (StringRef F : ReqFeatures) {
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[PATCH] D154596: [RISCV] Fix required features checking with empty string

2023-07-13 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

Kindly ping.


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[PATCH] D154596: [RISCV] Fix required features checking with empty string

2023-07-13 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

In D154596#4499647 , @wangpc wrote:

> Can you give an example of intrinsic that doesn't require any extra extension 
> enabled?

Like read/write csr intrinsics that we add for convenient usage doesn't need 
any extra extension enabled.


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[PATCH] D154596: [RISCV] Fix required features checking with empty string

2023-07-13 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

In D154596#4499757 , @wangpc wrote:

> In D154596#4499718 , @Jim wrote:
>
>> In D154596#4499647 , @wangpc wrote:
>>
>>> Can you give an example of intrinsic that doesn't require any extra 
>>> extension enabled?
>>
>> Like read/write csr intrinsics that we add for convenient usage doesn't need 
>> any extra extension enabled.
>
> It seems that `zicsr` is related.
> I am not opposed to this change, just out of curiosity. :-)

read/write csr is not a good example for the newest isa spec. In older isa spec 
2.2, it is included in base i extension.
Anyway. just want to add some intrinsics and them generate corresponding 
instruction that is in base i extension.
And it is reasonable if keep required feature string empty should imply no 
features/extensions required.


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[PATCH] D154596: [RISCV] Fix required features checking with empty string

2023-07-14 Thread Jim Lin via Phabricator via cfe-commits
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8fe0449ac990: [RISCV] Fix required features checking with 
empty string (authored by Jim).

Repository:
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Files:
  clang/lib/Sema/SemaChecking.cpp


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4481,7 +4481,7 @@
   bool FeatureMissing = false;
   SmallVector ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  Features.split(ReqFeatures, ',');
+  Features.split(ReqFeatures, ',', -1, false);
 
   // Check if each required feature is included
   for (StringRef F : ReqFeatures) {


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -4481,7 +4481,7 @@
   bool FeatureMissing = false;
   SmallVector ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  Features.split(ReqFeatures, ',');
+  Features.split(ReqFeatures, ',', -1, false);
 
   // Check if each required feature is included
   for (StringRef F : ReqFeatures) {
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[PATCH] D72825: Remove unused option that gcc ignored

2020-02-18 Thread Jim Lin via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes.
Closed by commit rGea789f819f26: Remove unused option that gcc ignored 
(authored by Jim).

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Files:
  clang/include/clang/Driver/Options.td
  clang/test/Driver/clang_f_opts.c


Index: clang/test/Driver/clang_f_opts.c
===
--- clang/test/Driver/clang_f_opts.c
+++ clang/test/Driver/clang_f_opts.c
@@ -291,9 +291,6 @@
 // RUN: -frename-registers\
 // RUN: -fschedule-insns2 \
 // RUN: -fsingle-precision-constant   \
-// RUN: -ftree_loop_im\
-// RUN: -ftree_loop_ivcanon   \
-// RUN: -ftree_loop_linear\
 // RUN: -funsafe-loop-optimizations   \
 // RUN: -fuse-linker-plugin   \
 // RUN: -fvect-cost-model \
@@ -431,9 +428,6 @@
 // CHECK-WARNING-DAG: optimization flag '-frename-registers' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fschedule-insns2' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fsingle-precision-constant' is not 
supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_im' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_ivcanon' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_linear' is not supported
 // CHECK-WARNING-DAG: optimization flag '-funsafe-loop-optimizations' is not 
supported
 // CHECK-WARNING-DAG: optimization flag '-fuse-linker-plugin' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fvect-cost-model' is not supported
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3325,9 +3325,6 @@
 defm tls_model : BooleanFFlag<"tls-model">, Group;
 defm tracer : BooleanFFlag<"tracer">, 
Group;
 defm tree_dce : BooleanFFlag<"tree-dce">, 
Group;
-defm tree_loop_im : BooleanFFlag<"tree_loop_im">,  
Group;
-defm tree_loop_ivcanon : BooleanFFlag<"tree_loop_ivcanon">,  
Group;
-defm tree_loop_linear : BooleanFFlag<"tree_loop_linear">,  
Group;
 defm tree_salias : BooleanFFlag<"tree-salias">, Group;
 defm tree_ter : BooleanFFlag<"tree-ter">, 
Group;
 defm tree_vectorizer_verbose : BooleanFFlag<"tree-vectorizer-verbose">, 
Group;


Index: clang/test/Driver/clang_f_opts.c
===
--- clang/test/Driver/clang_f_opts.c
+++ clang/test/Driver/clang_f_opts.c
@@ -291,9 +291,6 @@
 // RUN: -frename-registers\
 // RUN: -fschedule-insns2 \
 // RUN: -fsingle-precision-constant   \
-// RUN: -ftree_loop_im\
-// RUN: -ftree_loop_ivcanon   \
-// RUN: -ftree_loop_linear\
 // RUN: -funsafe-loop-optimizations   \
 // RUN: -fuse-linker-plugin   \
 // RUN: -fvect-cost-model \
@@ -431,9 +428,6 @@
 // CHECK-WARNING-DAG: optimization flag '-frename-registers' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fschedule-insns2' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fsingle-precision-constant' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_im' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_ivcanon' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_linear' is not supported
 // CHECK-WARNING-DAG: optimization flag '-funsafe-loop-optimizations' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fuse-linker-plugin' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fvect-cost-model' is not supported
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3325,9 +3325,6 @@
 defm tls_model : BooleanFFlag<"tls-model">, Group;
 defm tracer : BooleanFFlag<"tracer">, Group;
 defm tree_dce : BooleanFFlag<"tree-dce">, Group;
-defm tree_loop_im : BooleanFFlag<"tree_loop_im">,  Group;
-defm tree_loop_ivcanon : BooleanFFlag<"tree_loop_ivcanon">,  Group;
-defm

[PATCH] D71049: Remove implicit conversion that promotes half to other larger precision types for fp classification builtins

2019-12-04 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Jim added a reviewer: aaron.ballman.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

It shouldn't promote half to double or any larger precision types for fp 
classification builtins.
Because fp classification builtins would get incorrect result with promoted 
argument.
For example, __builtin_isnormal with a subnormal half value should return 
false, but it is not.
That the subnormal half value is promoted to a normal double value.


Repository:
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Files:
  clang/lib/Sema/SemaChecking.cpp


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -5808,7 +5808,7 @@
<< OrigArg->getType() << OrigArg->getSourceRange();
 
   // If this is an implicit conversion from float -> float, double, or
-  // long double, remove it.
+  // long double, or half -> half, float, double, or long double, remove it.
   if (ImplicitCastExpr *Cast = dyn_cast(OrigArg)) {
 // Only remove standard FloatCasts, leaving other casts inplace
 if (Cast->getCastKind() == CK_FloatingCast) {
@@ -5823,6 +5823,18 @@
 Cast->setSubExpr(nullptr);
 TheCall->setArg(NumArgs-1, CastArg);
   }
+
+  if (CastArg->getType()->isSpecificBuiltinType(BuiltinType::Half)) {
+assert(
+(Cast->getType()->isSpecificBuiltinType(BuiltinType::Double) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::Float) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::Half) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::LongDouble)) 
&&
+"promotion from half to either half, float, double, or long double 
"
+"is the only expected cast here");
+Cast->setSubExpr(nullptr);
+TheCall->setArg(NumArgs-1, CastArg);
+  }
 }
   }
 


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -5808,7 +5808,7 @@
<< OrigArg->getType() << OrigArg->getSourceRange();
 
   // If this is an implicit conversion from float -> float, double, or
-  // long double, remove it.
+  // long double, or half -> half, float, double, or long double, remove it.
   if (ImplicitCastExpr *Cast = dyn_cast(OrigArg)) {
 // Only remove standard FloatCasts, leaving other casts inplace
 if (Cast->getCastKind() == CK_FloatingCast) {
@@ -5823,6 +5823,18 @@
 Cast->setSubExpr(nullptr);
 TheCall->setArg(NumArgs-1, CastArg);
   }
+
+  if (CastArg->getType()->isSpecificBuiltinType(BuiltinType::Half)) {
+assert(
+(Cast->getType()->isSpecificBuiltinType(BuiltinType::Double) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::Float) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::Half) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::LongDouble)) &&
+"promotion from half to either half, float, double, or long double "
+"is the only expected cast here");
+Cast->setSubExpr(nullptr);
+TheCall->setArg(NumArgs-1, CastArg);
+  }
 }
   }
 
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[PATCH] D71049: Remove implicit conversion that promotes half to other larger precision types for fp classification builtins

2019-12-09 Thread Jim Lin via Phabricator via cfe-commits
Jim updated this revision to Diff 232765.
Jim added a comment.

Thank you for review.
Update patch and add tests that test half value will not be promoted to double.


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Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins.c


Index: clang/test/CodeGen/builtins.c
===
--- clang/test/CodeGen/builtins.c
+++ clang/test/CodeGen/builtins.c
@@ -193,8 +193,12 @@
 }
 
 // CHECK-LABEL: define void @test_float_builtins
-void test_float_builtins(float F, double D, long double LD) {
+void test_float_builtins(__fp16 *H, float F, double D, long double LD) {
   volatile int res;
+  res = __builtin_isinf(*H);
+  // CHECK:  call half @llvm.fabs.f16(half
+  // CHECK:  fcmp oeq half {{.*}}, 0xH7C00
+
   res = __builtin_isinf(F);
   // CHECK:  call float @llvm.fabs.f32(float
   // CHECK:  fcmp oeq float {{.*}}, 0x7FF0
@@ -207,6 +211,14 @@
   // CHECK:  call x86_fp80 @llvm.fabs.f80(x86_fp80
   // CHECK:  fcmp oeq x86_fp80 {{.*}}, 0xK7FFF8000
 
+  res = __builtin_isinf_sign(*H);
+  // CHECK:  %[[ABS:.*]] = call half @llvm.fabs.f16(half %[[ARG:.*]])
+  // CHECK:  %[[ISINF:.*]] = fcmp oeq half %[[ABS]], 0xH7C00
+  // CHECK:  %[[BITCAST:.*]] = bitcast half %[[ARG]] to i16
+  // CHECK:  %[[ISNEG:.*]] = icmp slt i16 %[[BITCAST]], 0
+  // CHECK:  %[[SIGN:.*]] = select i1 %[[ISNEG]], i32 -1, i32 1
+  // CHECK:  select i1 %[[ISINF]], i32 %[[SIGN]], i32 0
+
   res = __builtin_isinf_sign(F);
   // CHECK:  %[[ABS:.*]] = call float @llvm.fabs.f32(float %[[ARG:.*]])
   // CHECK:  %[[ISINF:.*]] = fcmp oeq float %[[ABS]], 0x7FF0
@@ -231,6 +243,10 @@
   // CHECK:  %[[SIGN:.*]] = select i1 %[[ISNEG]], i32 -1, i32 1
   // CHECK:  select i1 %[[ISINF]], i32 %[[SIGN]], i32 0
 
+  res = __builtin_isfinite(*H);
+  // CHECK: call half @llvm.fabs.f16(half
+  // CHECK: fcmp one half {{.*}}, 0xH7C00
+
   res = __builtin_isfinite(F);
   // CHECK: call float @llvm.fabs.f32(float
   // CHECK: fcmp one float {{.*}}, 0x7FF0
@@ -239,6 +255,14 @@
   // CHECK: call double @llvm.fabs.f64(double
   // CHECK: fcmp one double {{.*}}, 0x7FF0
 
+  res = __builtin_isnormal(*H);
+  // CHECK: fcmp oeq half
+  // CHECK: call half @llvm.fabs.f16(half
+  // CHECK: fcmp ult half {{.*}}, 0xH7C00
+  // CHECK: fcmp uge half {{.*}}, 0xH0400
+  // CHECK: and i1
+  // CHECK: and i1
+
   res = __builtin_isnormal(F);
   // CHECK: fcmp oeq float
   // CHECK: call float @llvm.fabs.f32(float
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -5808,10 +5808,11 @@
<< OrigArg->getType() << OrigArg->getSourceRange();
 
   // If this is an implicit conversion from float -> float, double, or
-  // long double, remove it.
+  // long double, or half -> half, float, double, or long double, remove it.
   if (ImplicitCastExpr *Cast = dyn_cast(OrigArg)) {
 // Only remove standard FloatCasts, leaving other casts inplace
 if (Cast->getCastKind() == CK_FloatingCast) {
+  bool IgnoreCast = false;
   Expr *CastArg = Cast->getSubExpr();
   if (CastArg->getType()->isSpecificBuiltinType(BuiltinType::Float)) {
 assert(
@@ -5820,6 +5821,19 @@
  Cast->getType()->isSpecificBuiltinType(BuiltinType::LongDouble)) 
&&
 "promotion from float to either float, double, or long double is "
 "the only expected cast here");
+IgnoreCast = true;
+  } else if (CastArg->getType()->isSpecificBuiltinType(BuiltinType::Half)) 
{
+assert(
+(Cast->getType()->isSpecificBuiltinType(BuiltinType::Double) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::Float) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::Half) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::LongDouble)) 
&&
+"promotion from half to either half, float, double, or long double 
"
+"is the only expected cast here");
+IgnoreCast = true;
+  }
+
+  if (IgnoreCast) {
 Cast->setSubExpr(nullptr);
 TheCall->setArg(NumArgs-1, CastArg);
   }


Index: clang/test/CodeGen/builtins.c
===
--- clang/test/CodeGen/builtins.c
+++ clang/test/CodeGen/builtins.c
@@ -193,8 +193,12 @@
 }
 
 // CHECK-LABEL: define void @test_float_builtins
-void test_float_builtins(float F, double D, long double LD) {
+void test_float_builtins(__fp16 *H, float F, double D, long double LD) {
   volatile int res;
+  res = __builtin_isinf(*H);
+  // CHECK:  call half @llvm.fabs.f16(half
+  // CHECK:  fcmp oeq half {{.*}}, 0xH7C00
+
   res = __builtin_isinf(F);
   // CHECK:  call float @llvm.fabs.f32(float
   // CHECK:  fcmp

[PATCH] D71124: [RISCV] support clang driver to select cpu

2019-12-09 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.h:46
 
+  bool setCPU(const std::string &Name) override {
+CPU = Name;

I think this should test cpu name is valid first. And assign Name to CPU, if it 
is valid.


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[PATCH] D71049: Remove implicit conversion that promotes half to other larger precision types for fp classification builtins

2019-12-09 Thread Jim Lin via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes.
Closed by commit rGcefac9dfaac9: Remove implicit conversion that promotes half 
to other larger precision types… (authored by Jim).

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Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins.c


Index: clang/test/CodeGen/builtins.c
===
--- clang/test/CodeGen/builtins.c
+++ clang/test/CodeGen/builtins.c
@@ -193,8 +193,12 @@
 }
 
 // CHECK-LABEL: define void @test_float_builtins
-void test_float_builtins(float F, double D, long double LD) {
+void test_float_builtins(__fp16 *H, float F, double D, long double LD) {
   volatile int res;
+  res = __builtin_isinf(*H);
+  // CHECK:  call half @llvm.fabs.f16(half
+  // CHECK:  fcmp oeq half {{.*}}, 0xH7C00
+
   res = __builtin_isinf(F);
   // CHECK:  call float @llvm.fabs.f32(float
   // CHECK:  fcmp oeq float {{.*}}, 0x7FF0
@@ -207,6 +211,14 @@
   // CHECK:  call x86_fp80 @llvm.fabs.f80(x86_fp80
   // CHECK:  fcmp oeq x86_fp80 {{.*}}, 0xK7FFF8000
 
+  res = __builtin_isinf_sign(*H);
+  // CHECK:  %[[ABS:.*]] = call half @llvm.fabs.f16(half %[[ARG:.*]])
+  // CHECK:  %[[ISINF:.*]] = fcmp oeq half %[[ABS]], 0xH7C00
+  // CHECK:  %[[BITCAST:.*]] = bitcast half %[[ARG]] to i16
+  // CHECK:  %[[ISNEG:.*]] = icmp slt i16 %[[BITCAST]], 0
+  // CHECK:  %[[SIGN:.*]] = select i1 %[[ISNEG]], i32 -1, i32 1
+  // CHECK:  select i1 %[[ISINF]], i32 %[[SIGN]], i32 0
+
   res = __builtin_isinf_sign(F);
   // CHECK:  %[[ABS:.*]] = call float @llvm.fabs.f32(float %[[ARG:.*]])
   // CHECK:  %[[ISINF:.*]] = fcmp oeq float %[[ABS]], 0x7FF0
@@ -231,6 +243,10 @@
   // CHECK:  %[[SIGN:.*]] = select i1 %[[ISNEG]], i32 -1, i32 1
   // CHECK:  select i1 %[[ISINF]], i32 %[[SIGN]], i32 0
 
+  res = __builtin_isfinite(*H);
+  // CHECK: call half @llvm.fabs.f16(half
+  // CHECK: fcmp one half {{.*}}, 0xH7C00
+
   res = __builtin_isfinite(F);
   // CHECK: call float @llvm.fabs.f32(float
   // CHECK: fcmp one float {{.*}}, 0x7FF0
@@ -239,6 +255,14 @@
   // CHECK: call double @llvm.fabs.f64(double
   // CHECK: fcmp one double {{.*}}, 0x7FF0
 
+  res = __builtin_isnormal(*H);
+  // CHECK: fcmp oeq half
+  // CHECK: call half @llvm.fabs.f16(half
+  // CHECK: fcmp ult half {{.*}}, 0xH7C00
+  // CHECK: fcmp uge half {{.*}}, 0xH0400
+  // CHECK: and i1
+  // CHECK: and i1
+
   res = __builtin_isnormal(F);
   // CHECK: fcmp oeq float
   // CHECK: call float @llvm.fabs.f32(float
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -5808,10 +5808,11 @@
<< OrigArg->getType() << OrigArg->getSourceRange();
 
   // If this is an implicit conversion from float -> float, double, or
-  // long double, remove it.
+  // long double, or half -> half, float, double, or long double, remove it.
   if (ImplicitCastExpr *Cast = dyn_cast(OrigArg)) {
 // Only remove standard FloatCasts, leaving other casts inplace
 if (Cast->getCastKind() == CK_FloatingCast) {
+  bool IgnoreCast = false;
   Expr *CastArg = Cast->getSubExpr();
   if (CastArg->getType()->isSpecificBuiltinType(BuiltinType::Float)) {
 assert(
@@ -5820,6 +5821,19 @@
  Cast->getType()->isSpecificBuiltinType(BuiltinType::LongDouble)) 
&&
 "promotion from float to either float, double, or long double is "
 "the only expected cast here");
+IgnoreCast = true;
+  } else if (CastArg->getType()->isSpecificBuiltinType(BuiltinType::Half)) 
{
+assert(
+(Cast->getType()->isSpecificBuiltinType(BuiltinType::Double) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::Float) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::Half) ||
+ Cast->getType()->isSpecificBuiltinType(BuiltinType::LongDouble)) 
&&
+"promotion from half to either half, float, double, or long double 
"
+"is the only expected cast here");
+IgnoreCast = true;
+  }
+
+  if (IgnoreCast) {
 Cast->setSubExpr(nullptr);
 TheCall->setArg(NumArgs-1, CastArg);
   }


Index: clang/test/CodeGen/builtins.c
===
--- clang/test/CodeGen/builtins.c
+++ clang/test/CodeGen/builtins.c
@@ -193,8 +193,12 @@
 }
 
 // CHECK-LABEL: define void @test_float_builtins
-void test_float_builtins(float F, double D, long double LD) {
+void test_float_builtins(__fp16 *H, float F, double D, long double LD) {
   volatile int res;
+  res = __builtin_isinf(*H);
+  // CHECK:  call half @llvm.fabs.f16(half
+  // CHECK:  fcmp oeq half {{.*}}, 0xH7C00
+
   res = __builtin_isinf(F);
   // CHECK:  call float 

[PATCH] D71049: Remove implicit conversion that promotes half to other larger precision types for fp classification builtins

2019-12-10 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

@uweigand
This is fixed by 
https://reviews.llvm.org/rG9c3966379813c198129c57aa3ebecd68d6af1ebd
Thanks.


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[PATCH] D48921: NFC - Typo fix in test/CodeGenCXX/runtime-dllstorage.cpp

2019-12-11 Thread Jim Lin via Phabricator via cfe-commits
Jim accepted this revision.
Jim added a comment.
This revision is now accepted and ready to land.
Herald added a project: clang.

Are you ready to land this patch?


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[PATCH] D71374: Improve support of GNU mempcpy

2019-12-12 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:2524
+else
+  return RValue::get(Builder.CreateGEP(Dest.getPointer(), SizeVal));
   }

Is it an error here?

It should be:

```
if (BuiltinID == Builtin::BImempcpy ||
BuiltinID == Builtin::BI__builtin_mempcpy)
return RValue::get(Builder.CreateGEP(Dest.getPointer(), SizeVal));
else
return RValue::get(Dest.getPointer());
```


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[PATCH] D57732: Correct inf typo

2019-12-12 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

Do you need someone to commit this change for you?


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[PATCH] D57732: Correct inf typo

2019-12-12 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

I can commit it for you.
If you are interested in obtaining the commit right. you can refer 
https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access.


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[PATCH] D57732: Correct inf typo

2019-12-12 Thread Jim Lin via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4daa8d1de6dd: Correct inf typo (authored by gaul, committed 
by Jim).

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Files:
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  clang/include/clang/Format/Format.h


Index: clang/include/clang/Format/Format.h
===
--- clang/include/clang/Format/Format.h
+++ clang/include/clang/Format/Format.h
@@ -981,7 +981,7 @@
 /// set, and the function could/should not be put on a single line (as per
 /// `AllowShortFunctionsOnASingleLine` and constructor formatting options).
 /// \code
-///   int f()   vs.   inf f()
+///   int f()   vs.   int f()
 ///   {}  {
 ///   }
 /// \endcode
Index: clang/docs/ClangFormatStyleOptions.rst
===
--- clang/docs/ClangFormatStyleOptions.rst
+++ clang/docs/ClangFormatStyleOptions.rst
@@ -958,7 +958,7 @@
 
 .. code-block:: c++
 
-  int f()   vs.   inf f()
+  int f()   vs.   int f()
   {}  {
   }
 


Index: clang/include/clang/Format/Format.h
===
--- clang/include/clang/Format/Format.h
+++ clang/include/clang/Format/Format.h
@@ -981,7 +981,7 @@
 /// set, and the function could/should not be put on a single line (as per
 /// `AllowShortFunctionsOnASingleLine` and constructor formatting options).
 /// \code
-///   int f()   vs.   inf f()
+///   int f()   vs.   int f()
 ///   {}  {
 ///   }
 /// \endcode
Index: clang/docs/ClangFormatStyleOptions.rst
===
--- clang/docs/ClangFormatStyleOptions.rst
+++ clang/docs/ClangFormatStyleOptions.rst
@@ -958,7 +958,7 @@
 
 .. code-block:: c++
 
-  int f()   vs.   inf f()
+  int f()   vs.   int f()
   {}  {
   }
 
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[PATCH] D71374: Improve support of GNU mempcpy

2019-12-12 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

I am curious what is difference of code generation after applying your changes?


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[PATCH] D61549: Fix use of 'is' operator for comparison

2019-12-16 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

@j-carl Could you give a Python 3.8 syntax reference for this change.


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[PATCH] D66839: Fix stack address builtin for negative numbers

2019-12-16 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

I think this checking should be implemented in lib/Sema/SemaChecking.cpp.


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[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

2019-12-16 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

This patch is only for RISCV.
The title should have prefix "[RISCV]".




Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:585
+const llvm::opt::ArgList &Args,
+llvm::opt::ArgStringList &CmdArgs) {
+  // -mabi is not encoded in bitcode so we need to pass it to LTO code

Argument list should be aligned.




Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.h:31
+const llvm::opt::ArgList &Args,
+llvm::opt::ArgStringList &CmdArgs);
 } // end namespace riscv

Argument list should be aligned.


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[PATCH] D71541: [Clang]: fix spelling mistake in assert message

2019-12-16 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

Could you add "[NFC]" in the title. 
That means No Function Change.


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[PATCH] D71541: [NFC] [Clang]: fix spelling mistake in assert message

2019-12-18 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

Do you need someone to commit this change for you?


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[PATCH] D45677: [libcxx] [test] Fix typo in filesystem test

2019-12-22 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

This is fixed by 
https://reviews.llvm.org/rG437e0e5191ca255db27e86d232020844c1fd08c8.


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[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

2019-12-24 Thread Jim Lin via Phabricator via cfe-commits
Jim added inline comments.



Comment at: llvm/test/CodeGen/RISCV/calling-conv-ilp32e-double-bug.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -target-abi ilp32e -mattr=+f -verify-machineinstrs 
< %s
+; RUN: llc -mtriple=riscv32 -target-abi ilp32e -mattr=+f,+d 
-verify-machineinstrs < %s

No FileCheck line here.


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[PATCH] D72825: Remove unused option that gcc ignored

2020-02-17 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

ping?


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[PATCH] D72825: [NFC] Fix options name typo

2020-01-16 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

It should be kept for compatibility. These three options may be used in other 
projects compiled by gcc.
Clang should ignore it.
https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html


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[PATCH] D72825: Remove unused option that gcc ignored

2020-01-21 Thread Jim Lin via Phabricator via cfe-commits
Jim updated this revision to Diff 239246.
Jim retitled this revision from "[NFC] Fix options name typo" to "Remove unused 
option that gcc ignored".
Jim edited the summary of this revision.
Jim added a comment.

Address the comment. Delete the options.


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Files:
  clang/include/clang/Driver/Options.td
  clang/test/Driver/clang_f_opts.c


Index: clang/test/Driver/clang_f_opts.c
===
--- clang/test/Driver/clang_f_opts.c
+++ clang/test/Driver/clang_f_opts.c
@@ -292,9 +292,6 @@
 // RUN: -frename-registers\
 // RUN: -fschedule-insns2 \
 // RUN: -fsingle-precision-constant   \
-// RUN: -ftree_loop_im\
-// RUN: -ftree_loop_ivcanon   \
-// RUN: -ftree_loop_linear\
 // RUN: -funsafe-loop-optimizations   \
 // RUN: -fuse-linker-plugin   \
 // RUN: -fvect-cost-model \
@@ -432,9 +429,6 @@
 // CHECK-WARNING-DAG: optimization flag '-frename-registers' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fschedule-insns2' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fsingle-precision-constant' is not 
supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_im' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_ivcanon' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_linear' is not supported
 // CHECK-WARNING-DAG: optimization flag '-funsafe-loop-optimizations' is not 
supported
 // CHECK-WARNING-DAG: optimization flag '-fuse-linker-plugin' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fvect-cost-model' is not supported
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3306,9 +3306,6 @@
 defm tls_model : BooleanFFlag<"tls-model">, Group;
 defm tracer : BooleanFFlag<"tracer">, 
Group;
 defm tree_dce : BooleanFFlag<"tree-dce">, 
Group;
-defm tree_loop_im : BooleanFFlag<"tree_loop_im">,  
Group;
-defm tree_loop_ivcanon : BooleanFFlag<"tree_loop_ivcanon">,  
Group;
-defm tree_loop_linear : BooleanFFlag<"tree_loop_linear">,  
Group;
 defm tree_salias : BooleanFFlag<"tree-salias">, Group;
 defm tree_ter : BooleanFFlag<"tree-ter">, 
Group;
 defm tree_vectorizer_verbose : BooleanFFlag<"tree-vectorizer-verbose">, 
Group;


Index: clang/test/Driver/clang_f_opts.c
===
--- clang/test/Driver/clang_f_opts.c
+++ clang/test/Driver/clang_f_opts.c
@@ -292,9 +292,6 @@
 // RUN: -frename-registers\
 // RUN: -fschedule-insns2 \
 // RUN: -fsingle-precision-constant   \
-// RUN: -ftree_loop_im\
-// RUN: -ftree_loop_ivcanon   \
-// RUN: -ftree_loop_linear\
 // RUN: -funsafe-loop-optimizations   \
 // RUN: -fuse-linker-plugin   \
 // RUN: -fvect-cost-model \
@@ -432,9 +429,6 @@
 // CHECK-WARNING-DAG: optimization flag '-frename-registers' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fschedule-insns2' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fsingle-precision-constant' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_im' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_ivcanon' is not supported
-// CHECK-WARNING-DAG: optimization flag '-ftree_loop_linear' is not supported
 // CHECK-WARNING-DAG: optimization flag '-funsafe-loop-optimizations' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fuse-linker-plugin' is not supported
 // CHECK-WARNING-DAG: optimization flag '-fvect-cost-model' is not supported
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3306,9 +3306,6 @@
 defm tls_model : BooleanFFlag<"tls-model">, Group;
 defm tracer : BooleanFFlag<"tracer">, Group;
 defm tree_dce : BooleanFFlag<"tree-dce">, Group;
-defm tree_loop_im : BooleanFFlag<"tree_loop

[PATCH] D153235: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUi/iULi

2023-06-18 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, 
the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, eopXD, MaskRay.
Herald added a project: clang.

In clang/include/clang/Basic/Builtins.def, the argument type of __builtin_clz 
and __builtin_ctz
are defined `iUi` and __builtin_clzl and __builtin_ctzl are defined `iULi`.

clz/ctz are similar to RISC-V's clz_32 and ctz_32.
clzl/ctzl are similar to RISC-V's clz_64 and ctz_64.


Repository:
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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,7 +34,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -46,7 +46,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long clz_64(long a) {
+long clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
 
@@ -58,7 +58,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
@@ -70,6 +70,6 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long ctz_64(long a) {
+long ctz_64(unsigned long a) {
   return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -22,7 +22,7 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -34,6 +34,6 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
\ No newline at end of file
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -18,10 +18,10 @@
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb|xtheadbb")
-TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb|xtheadbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
-TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_clz_32, "iUi", "nc", "zbb|xtheadbb")
+TARGET_BUILTIN(__builtin_riscv_clz_64, "iULi", "nc", "zbb|xtheadbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctz_32, "iUi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_ctz_64, "iULi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,7 +34,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -46,7 +46,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long clz_64(long a) {
+long clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
 
@@ -58,7 +58,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
@@ -70

[PATCH] D153235: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUi/iULi

2023-06-19 Thread Jim Lin via Phabricator via cfe-commits
Jim updated this revision to Diff 532790.
Jim added a comment.

Address comment.


Repository:
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Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,7 +34,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -46,7 +46,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long clz_64(long a) {
+int clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
 
@@ -58,7 +58,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
@@ -70,6 +70,6 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long ctz_64(long a) {
+int ctz_64(unsigned long a) {
   return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -22,7 +22,7 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -34,6 +34,6 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
\ No newline at end of file
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -18,10 +18,10 @@
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb|xtheadbb")
-TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb|xtheadbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
-TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_clz_32, "iUZi", "nc", "zbb|xtheadbb")
+TARGET_BUILTIN(__builtin_riscv_clz_64, "iUWi", "nc", "zbb|xtheadbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctz_32, "iUZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_ctz_64, "iUWi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,7 +34,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -46,7 +46,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long clz_64(long a) {
+int clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
 
@@ -58,7 +58,7 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
@@ -70,6 +70,6 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i64 [[TMP1]]
 //
-long ctz_64(long a) {
+int ctz_64(unsigned long a) {
   return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -22,7 +22,7 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
 // RV32ZBB-NEXT:ret i32 [[

[PATCH] D153235: [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUZi/iUWi

2023-06-25 Thread Jim Lin via Phabricator via cfe-commits
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG612b7e10a9af: [RISCV] Change the type of argument to clz and 
ctz from ZiZi/WiWi to iUZi/iUWi (authored by Jim).

Changed prior to commit:
  https://reviews.llvm.org/D153235?vs=532790&id=534425#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153235/new/

https://reviews.llvm.org/D153235

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,19 +34,22 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
 // RV64ZBB-LABEL: @clz_64(
 // RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[RETVAL:%.*]] = alloca i32, align 4
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
 // RV64ZBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 
false)
-// RV64ZBB-NEXT:ret i64 [[TMP1]]
+// RV64ZBB-NEXT:store i64 [[TMP1]], ptr [[RETVAL]], align 4
+// RV64ZBB-NEXT:[[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
+// RV64ZBB-NEXT:ret i32 [[TMP2]]
 //
-long clz_64(long a) {
+int clz_64(unsigned long a) {
   return __builtin_riscv_clz_64(a);
 }
 
@@ -58,18 +61,21 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
 
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[RETVAL:%.*]] = alloca i32, align 4
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
 // RV64ZBB-NEXT:store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 
false)
-// RV64ZBB-NEXT:ret i64 [[TMP1]]
+// RV64ZBB-NEXT:store i64 [[TMP1]], ptr [[RETVAL]], align 4
+// RV64ZBB-NEXT:[[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4
+// RV64ZBB-NEXT:ret i32 [[TMP2]]
 //
-long ctz_64(long a) {
+int ctz_64(unsigned long a) {
   return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -22,7 +22,7 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {
+int clz_32(unsigned int a) {
   return __builtin_riscv_clz_32(a);
 }
 
@@ -34,6 +34,6 @@
 // RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
 // RV32ZBB-NEXT:ret i32 [[TMP1]]
 //
-int ctz_32(int a) {
+int ctz_32(unsigned int a) {
   return __builtin_riscv_ctz_32(a);
 }
\ No newline at end of file
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -18,10 +18,10 @@
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb|xtheadbb")
-TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb|xtheadbb,64bit")
-TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
-TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_clz_32, "iUZi", "nc", "zbb|xtheadbb")
+TARGET_BUILTIN(__builtin_riscv_clz_64, "iUWi", "nc", "zbb|xtheadbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctz_32, "iUZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_ctz_64, "iUWi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -34,19 +34,22 @@
 // RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
 // RV64ZBB-NEXT:ret i32 [[TMP1]]
 //
-int clz_32(int a) {

[PATCH] D150945: [RISCV] Add missing test for ctz_32 on RV64

2023-05-21 Thread Jim Lin via Phabricator via cfe-commits
This revision was automatically updated to reflect the committed changes.
Closed by commit rG33d3d51d77a7: [RISCV] Add missing test for ctz_32 on RV64 
(authored by Jim).

Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150945/new/

https://reviews.llvm.org/D150945

Files:
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -50,6 +50,18 @@
   return __builtin_riscv_clz_64(a);
 }
 
+// RV64ZBB-LABEL: @ctz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+  return __builtin_riscv_ctz_32(a);
+}
+
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -50,6 +50,18 @@
   return __builtin_riscv_clz_64(a);
 }
 
+// RV64ZBB-LABEL: @ctz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+  return __builtin_riscv_ctz_32(a);
+}
+
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
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[PATCH] D150945: [RISCV] Add missing test for ctz_32 on RV64

2023-05-19 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, 
the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Apparently, both of clz and ctz should have tests for _32 version on RV64.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150945

Files:
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -50,6 +50,18 @@
   return __builtin_riscv_clz_64(a);
 }
 
+// RV64ZBB-LABEL: @ctz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+  return __builtin_riscv_ctz_32(a);
+}
+
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -50,6 +50,18 @@
   return __builtin_riscv_clz_64(a);
 }
 
+// RV64ZBB-LABEL: @ctz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+  return __builtin_riscv_ctz_32(a);
+}
+
 // RV64ZBB-LABEL: @ctz_64(
 // RV64ZBB-NEXT:  entry:
 // RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
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[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.96

2022-01-20 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.
Herald added a subscriber: eopXD.

In D108189#3188343 , @zixuan-wu wrote:

> Hi, @Jim.
> What time is P extension going to upstream to community since it's been no 
> update for some months?

Hi @zixuan-wu,

From RVP 0.9.7, it has lots of changes (new sub-extension Zbpbo). I am still 
working on it.
Sorry for reply late.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2022-02-21 Thread Jim Lin via Phabricator via cfe-commits
Jim marked 2 inline comments as done.
Jim added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:909
+
+// kmar64 has a aliased instruction kmada32 belong to zpn sub-extension on 
RV64.
+let DecoderNamespace = "RISCV32Zpsfoperand_",

Jim wrote:
> jrtc27 wrote:
> > Having the same instruction in two different extensions under two different 
> > names is insane. Currently this implementation lets you use the "wrong" 
> > name for kmar64 with Zpn. But I would prefer the spec weren't crazy.
> I am still working on fixing it (from spec or ...) . But it is spec issue.
Remove alias inst first. I will discuss with P-extension maintainer on this 
issue.
Could this issue be fixed by a future revision?



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:228
+
+def GPR32Pair : RegisterClass<"RISCV", [untyped], 64, (add GPR32Pairs)> {
+  let Size = 64;

jrtc27 wrote:
> Jim wrote:
> > jrtc27 wrote:
> > > Why is this untyped?
> > GPR32Pair has untyped type. 
> > In code generation, It captures some operation with i64 type supported by 
> > Zpsoperand to untyped during legalization. 
> > In my mind, untyped is used to be represented special type don't need any 
> > legalization.
> > I refer to ARMRegisterInfo.td that defines GPRPair with untyped.
> So, presumably it can't be i64 because that would then make i64 a legal type? 
> Maybe that's fine, maybe it's not, but alternatively it could be typed as 
> v2i32 here (can include v4i16 and v8i8 too) and cast if/when needed. Craig 
> maybe you have thoughts on this? But untyped always feels like laziness to me 
> that results in TableGen being unable to help you when it comes to type 
> checking, with rare exceptions.
All of operation node having untyped operands are customized SDNode lowered in 
RISCVISelLowering.cpp.  And matched to a specific pattern. 
untyped couldn't be as v2i32, v4i16 or v8i8 in the same time. The operand type 
has been checked in custom lowering.

The lowering for operation with specific operand types (v2i32, v4i16, v8i8 or 
i64 in this case) would be set cutsom and lowered to customized SDNode (This 
SDNode has untyped operands). 
Different operand types with the same operation are lowered to different 
customized SDNode.


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

2022-02-21 Thread Jim Lin via Phabricator via cfe-commits
Jim marked an inline comment as done.
Jim added inline comments.



Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll:4360
 ; LMULMAX1-RV64-NEXT:vid.v v10
+; LMULMAX1-RV64-NEXT:vadd.vi v11, v10, 2
+; LMULMAX1-RV64-NEXT:lui a2, %hi(.LCPI132_2)

The change for this testcase is that GPRJALR regclass is subsumed by 
GPR32Pair_with_gpr32_pair_lo_in_GPRNoX0X2 regclass.
And register pressure calculation is different.


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[PATCH] D101426: [RISCV] Update subset naming convertion for the latest spec

2021-04-28 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
Jim requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Update arch string rules for the latest spec 20191213. It introduced
new multi-letter extension prefix with 'h' and 'z', and drop `sx`.
And the canonical order is 's', 'h', 'z' and 'x'.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D101426

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-arch.c

Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -181,31 +181,25 @@
 // RV32-STD: error: invalid arch name 'rv32imqc',
 // RV32-STD: unsupported standard user-level extension 'q'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32xabc -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
-// RV32X: error: invalid arch name 'rv32xabc',
-// RV32X: first letter should be 'e', 'i' or 'g'
-
-// RUN: %clang -target riscv32-unknown-elf -march=rv32sxabc -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32SX %s
-// RV32SX: error: invalid arch name 'rv32sxabc',
-// RV32SX: first letter should be 'e', 'i' or 'g'
-
 // RUN: %clang -target riscv32-unknown-elf -march=rv32sabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32S %s
 // RV32S: error: invalid arch name 'rv32sabc',
 // RV32S: first letter should be 'e', 'i' or 'g'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ix -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X-NAME %s
-// RV32X-NAME: error: invalid arch name 'rv32ix',
-// RV32X-NAME: non-standard user-level extension name missing after 'x'
+// RUN: %clang -target riscv32-unknown-elf -march=rv32habc -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32H %s
+// RV32H: error: invalid arch name 'rv32habc',
+// RV32H: first letter should be 'e', 'i' or 'g'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32isx -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32SX-NAME %s
-// RV32SX-NAME: error: invalid arch name 'rv32isx',
-// RV32SX-NAME: non-standard supervisor-level extension
-// RV32SX-NAME: name missing after 'sx'
+// RUN: %clang -target riscv32-unknown-elf -march=rv32zabc -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32Z %s
+// RV32Z: error: invalid arch name 'rv32zabc',
+// RV32Z: first letter should be 'e', 'i' or 'g'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32xabc -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
+// RV32X: error: invalid arch name 'rv32xabc',
+// RV32X: first letter should be 'e', 'i' or 'g'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32is -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32S-NAME %s
@@ -213,31 +207,53 @@
 // RV32S-NAME: standard supervisor-level extension
 // RV32S-NAME: name missing after 's'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ix_s_sx -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ALL-NAME %s
-// RV32ALL-NAME: error: invalid arch name 'rv32ix_s_sx',
-// RV32ALL-NAME: non-standard user-level extension
-// RV32ALL-NAME: name missing after 'x'
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ih -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32H-NAME %s
+// RV32H-NAME: error: invalid arch name 'rv32ih',
+// RV32H-NAME: standard hypervisor-level extension
+// RV32H-NAME: name missing after 'h'
 
-// RUN: %clang -target riscv32-unknown-elf -march=rv32ixabc -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X-UNS %s
-// RV32X-UNS: error: invalid arch name 'rv32ixabc',
-// RV32X-UNS: unsupported non-standard user-level extension 'xabc'
+// RUN: %clang -target riscv32-unknown-elf -march=rv32iz -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32Z-NAME %s
+// RV32Z-NAME: error: invalid arch name 'rv32iz',
+// RV32Z-NAME: standard machine-level extension
+// RV32Z-NAME: name missing after 'z'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32ix -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X-NAME %s
+// RV32X-NAME: error: invalid arch name 'rv32ix',
+// RV32X-NAME: non-standard extension name missing after 'x'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32is_h_z_x -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32ALL-NAME %s
+// RV32ALL-NAME: error: invalid arch name 'rv32is_h_z_x',
+// RV32ALL-NAME: standard supervisor-level extension
+// RV32ALL-NAME: name missing after 's'
 
 // RUN: %clang -target riscv32-unknown-elf -mar

[PATCH] D101426: [RISCV] Update subset naming convertion for the latest spec

2021-04-28 Thread Jim Lin via Phabricator via cfe-commits
Jim added a comment.

GCC has been updated from 
https://github.com/gcc-mirror/gcc/commit/ca1a9763a1f635d2687ebd5009dd61d4fd0ab5fb#diff-622e89d94803bb804711d5d492a5d4dfa60399bd7a5a7e70a49155534aa6a81f


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101426/new/

https://reviews.llvm.org/D101426

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[PATCH] D116509: [Builtins] Add missing the macro 'y' description in comments

2022-01-02 Thread Jim Lin via Phabricator via cfe-commits
Jim created this revision.
Jim requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116509

Files:
  clang/include/clang/Basic/Builtins.def


Index: clang/include/clang/Basic/Builtins.def
===
--- clang/include/clang/Basic/Builtins.def
+++ clang/include/clang/Basic/Builtins.def
@@ -26,6 +26,7 @@
 //  i -> int
 //  h -> half (__fp16, OpenCL)
 //  x -> half (_Float16)
+//  y -> half (__bf16)
 //  f -> float
 //  d -> double
 //  z -> size_t


Index: clang/include/clang/Basic/Builtins.def
===
--- clang/include/clang/Basic/Builtins.def
+++ clang/include/clang/Basic/Builtins.def
@@ -26,6 +26,7 @@
 //  i -> int
 //  h -> half (__fp16, OpenCL)
 //  x -> half (_Float16)
+//  y -> half (__bf16)
 //  f -> float
 //  d -> double
 //  z -> size_t
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