[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2022-02-14 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

In D105169#3319773 , @dblaikie wrote:

> In D105169#3315009 , @MaskRay wrote:
>
>> It may not be worth changing now, but I want to mention: it's more 
>> conventional to have a `BoolOption` which adds `-[no-]noundef-analysis`. 
>> Since both positive and negative forms exist. When we make the default 
>> switch, existing users don't need to change the option. After the option 
>> becomes quite stable and the workaround is deemed not useful, we can remove 
>> the CC1 option.
>
> +1 to this (changing the name and the default at the same time makes 
> migrations a bit more difficult - if the default is changed without renaming 
> (by having both positive and negative flag names) then users can adopt their 
> current default explicitly with no change ahead of picking up the patch that 
> changes the default) & also this flag seems to have no tests? Could you 
> (@hyeongyukim ) add some frontend test coverage for the flag - and yeah, 
> maybe consider giving it a name that has both explicit on/off names, as 
> @maskray suggested? (I think that's useful even after the default switch - 
> since a user might want to override a previous argument on the command line, 
> etc)

Sure, I'll add some tests.
By the way, is it right to change the flag's name to 
`-[no-]enable-noundef-analysis`? or would it be better to use 
`-[no-]noundef-analysis` as @MaskRay suggested?
I prefer to use `-[no-]enable-noundef-analysis` to maintain backward 
compatibility.


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[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2022-02-14 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

Thank you for your clarification. I'll change it.


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[PATCH] D110226: [InstCombine] Update InstCombine to use poison instead of undef for shufflevector's placeholder (1/3)

2021-09-22 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim updated this revision to Diff 374210.
hyeongyukim added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Fix comment, update test file(wasm.c)


Repository:
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Files:
  clang/test/CodeGen/arm-neon-dot-product.c
  llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
  llvm/test/Transforms/InstCombine/X86/x86-f16c-inseltpoison.ll
  llvm/test/Transforms/InstCombine/X86/x86-f16c.ll
  llvm/test/Transforms/InstCombine/cast.ll
  llvm/test/Transforms/InstCombine/shuffle-cast-dist.ll
  llvm/test/Transforms/InstCombine/shufflevec-bitcast-inseltpoison.ll
  llvm/test/Transforms/InstCombine/shufflevec-bitcast.ll
  llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
  llvm/test/Transforms/InstCombine/trunc.ll
  llvm/test/Transforms/InstCombine/vector-casts.ll

Index: llvm/test/Transforms/InstCombine/vector-casts.ll
===
--- llvm/test/Transforms/InstCombine/vector-casts.ll
+++ llvm/test/Transforms/InstCombine/vector-casts.ll
@@ -414,7 +414,7 @@
 define <4 x float> @sitofp_shuf(<4 x i32> %x) {
 ; CHECK-LABEL: @sitofp_shuf(
 ; CHECK-NEXT:[[TMP1:%.*]] = sitofp <4 x i32> [[X:%.*]] to <4 x float>
-; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> 
+; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> 
 ; CHECK-NEXT:ret <4 x float> [[R]]
 ;
   %s = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> 
@@ -425,7 +425,7 @@
 define <3 x half> @uitofp_shuf(<3 x i16> %x) {
 ; CHECK-LABEL: @uitofp_shuf(
 ; CHECK-NEXT:[[TMP1:%.*]] = uitofp <3 x i16> [[X:%.*]] to <3 x half>
-; CHECK-NEXT:[[R:%.*]] = shufflevector <3 x half> [[TMP1]], <3 x half> undef, <3 x i32> 
+; CHECK-NEXT:[[R:%.*]] = shufflevector <3 x half> [[TMP1]], <3 x half> poison, <3 x i32> 
 ; CHECK-NEXT:ret <3 x half> [[R]]
 ;
   %s = shufflevector <3 x i16> %x, <3 x i16> poison, <3 x i32> 
@@ -436,7 +436,7 @@
 define <4 x i64> @fptosi_shuf(<4 x double> %x) {
 ; CHECK-LABEL: @fptosi_shuf(
 ; CHECK-NEXT:[[TMP1:%.*]] = fptosi <4 x double> [[X:%.*]] to <4 x i64>
-; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> undef, <4 x i32> 
+; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> poison, <4 x i32> 
 ; CHECK-NEXT:ret <4 x i64> [[R]]
 ;
   %s = shufflevector <4 x double> %x, <4 x double> poison, <4 x i32> 
@@ -447,7 +447,7 @@
 define <2 x i32> @fptoui_shuf(<2 x float> %x) {
 ; CHECK-LABEL: @fptoui_shuf(
 ; CHECK-NEXT:[[TMP1:%.*]] = fptoui <2 x float> [[X:%.*]] to <2 x i32>
-; CHECK-NEXT:[[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> 
+; CHECK-NEXT:[[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> 
 ; CHECK-NEXT:ret <2 x i32> [[R]]
 ;
   %s = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> 
Index: llvm/test/Transforms/InstCombine/trunc.ll
===
--- llvm/test/Transforms/InstCombine/trunc.ll
+++ llvm/test/Transforms/InstCombine/trunc.ll
@@ -922,7 +922,7 @@
 define <4 x i8> @wide_splat1(<4 x i32> %x) {
 ; CHECK-LABEL: @wide_splat1(
 ; CHECK-NEXT:[[TMP1:%.*]] = trunc <4 x i32> [[X:%.*]] to <4 x i8>
-; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> undef, <4 x i32> 
+; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> poison, <4 x i32> 
 ; CHECK-NEXT:ret <4 x i8> [[TRUNC]]
 ;
   %shuf = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> 
@@ -936,7 +936,7 @@
 define <3 x i31> @wide_splat2(<3 x i33> %x) {
 ; CHECK-LABEL: @wide_splat2(
 ; CHECK-NEXT:[[TMP1:%.*]] = trunc <3 x i33> [[X:%.*]] to <3 x i31>
-; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <3 x i31> [[TMP1]], <3 x i31> undef, <3 x i32> 
+; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <3 x i31> [[TMP1]], <3 x i31> poison, <3 x i32> 
 ; CHECK-NEXT:ret <3 x i31> [[TRUNC]]
 ;
   %shuf = shufflevector <3 x i33> %x, <3 x i33> undef, <3 x i32> 
Index: llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
===
--- llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
+++ llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
@@ -922,7 +922,7 @@
 define <4 x i8> @wide_splat1(<4 x i32> %x) {
 ; CHECK-LABEL: @wide_splat1(
 ; CHECK-NEXT:[[TMP1:%.*]] = trunc <4 x i32> [[X:%.*]] to <4 x i8>
-; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> undef, <4 x i32> 
+; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> poison, <4 x i32> 
 ; CHECK-NEXT:ret <4 x i8> [[TRUNC]]
 ;
   %shuf = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> 
@@ -936,7 +936,7 @@
 define <3 x i31> @wide_splat2(<3 x i33> %x) {
 ; CHECK-LABEL: @wid

[PATCH] D110226: [InstCombine] Update InstCombine to use poison instead of undef for shufflevector's placeholder (1/3)

2021-09-22 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim updated this revision to Diff 374212.
hyeongyukim added a comment.

Rebase


Repository:
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https://reviews.llvm.org/D110226

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
===
--- llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -368,7 +368,6 @@
   SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N);
   SDValue PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N);
-  SDValue PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N);
   SDValue PromoteIntOp_INSERT_SUBVECTOR(SDNode *N);
   SDValue PromoteIntOp_CONCAT_VECTORS(SDNode *N);
   SDValue PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N);
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===
--- llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1577,7 +1577,6 @@
   case ISD::UINT_TO_FP:   Res = PromoteIntOp_UINT_TO_FP(N); break;
   case ISD::STRICT_UINT_TO_FP:  Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
   case ISD::ZERO_EXTEND:  Res = PromoteIntOp_ZERO_EXTEND(N); break;
-  case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
   case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break;
 
   case ISD::SHL:
@@ -5094,16 +5093,6 @@
   return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
 }
 
-SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
-  SDLoc dl(N);
-  SDValue V0 = GetPromotedInteger(N->getOperand(0));
-  MVT InVT = V0.getValueType().getSimpleVT();
-  MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
-   N->getValueType(0).getVectorNumElements());
-  SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, 
N->getOperand(1));
-  return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
-}
-
 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
   SDLoc dl(N);
 


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
===
--- llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -368,7 +368,6 @@
   SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N);
   SDValue PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N);
-  SDValue PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N);
   SDValue PromoteIntOp_INSERT_SUBVECTOR(SDNode *N);
   SDValue PromoteIntOp_CONCAT_VECTORS(SDNode *N);
   SDValue PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N);
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===
--- llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1577,7 +1577,6 @@
   case ISD::UINT_TO_FP:   Res = PromoteIntOp_UINT_TO_FP(N); break;
   case ISD::STRICT_UINT_TO_FP:  Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
   case ISD::ZERO_EXTEND:  Res = PromoteIntOp_ZERO_EXTEND(N); break;
-  case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
   case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break;
 
   case ISD::SHL:
@@ -5094,16 +5093,6 @@
   return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
 }
 
-SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
-  SDLoc dl(N);
-  SDValue V0 = GetPromotedInteger(N->getOperand(0));
-  MVT InVT = V0.getValueType().getSimpleVT();
-  MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
-   N->getValueType(0).getVectorNumElements());
-  SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
-  return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
-}
-
 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
   SDLoc dl(N);
 
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[PATCH] D110226: [InstCombine] Update InstCombine to use poison instead of undef for shufflevector's placeholder (1/3)

2021-09-22 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim updated this revision to Diff 374213.
hyeongyukim added a comment.
Herald added subscribers: aheejin, sbc100.

Correct the wrong rebase.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110226/new/

https://reviews.llvm.org/D110226

Files:
  clang/test/Headers/wasm.c
  llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
  llvm/test/Transforms/InstCombine/X86/x86-f16c-inseltpoison.ll
  llvm/test/Transforms/InstCombine/X86/x86-f16c.ll
  llvm/test/Transforms/InstCombine/cast.ll
  llvm/test/Transforms/InstCombine/shuffle-cast-dist.ll
  llvm/test/Transforms/InstCombine/shufflevec-bitcast-inseltpoison.ll
  llvm/test/Transforms/InstCombine/shufflevec-bitcast.ll
  llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
  llvm/test/Transforms/InstCombine/trunc.ll
  llvm/test/Transforms/InstCombine/vector-casts.ll

Index: llvm/test/Transforms/InstCombine/vector-casts.ll
===
--- llvm/test/Transforms/InstCombine/vector-casts.ll
+++ llvm/test/Transforms/InstCombine/vector-casts.ll
@@ -414,7 +414,7 @@
 define <4 x float> @sitofp_shuf(<4 x i32> %x) {
 ; CHECK-LABEL: @sitofp_shuf(
 ; CHECK-NEXT:[[TMP1:%.*]] = sitofp <4 x i32> [[X:%.*]] to <4 x float>
-; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> 
+; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> 
 ; CHECK-NEXT:ret <4 x float> [[R]]
 ;
   %s = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> 
@@ -425,7 +425,7 @@
 define <3 x half> @uitofp_shuf(<3 x i16> %x) {
 ; CHECK-LABEL: @uitofp_shuf(
 ; CHECK-NEXT:[[TMP1:%.*]] = uitofp <3 x i16> [[X:%.*]] to <3 x half>
-; CHECK-NEXT:[[R:%.*]] = shufflevector <3 x half> [[TMP1]], <3 x half> undef, <3 x i32> 
+; CHECK-NEXT:[[R:%.*]] = shufflevector <3 x half> [[TMP1]], <3 x half> poison, <3 x i32> 
 ; CHECK-NEXT:ret <3 x half> [[R]]
 ;
   %s = shufflevector <3 x i16> %x, <3 x i16> poison, <3 x i32> 
@@ -436,7 +436,7 @@
 define <4 x i64> @fptosi_shuf(<4 x double> %x) {
 ; CHECK-LABEL: @fptosi_shuf(
 ; CHECK-NEXT:[[TMP1:%.*]] = fptosi <4 x double> [[X:%.*]] to <4 x i64>
-; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> undef, <4 x i32> 
+; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> poison, <4 x i32> 
 ; CHECK-NEXT:ret <4 x i64> [[R]]
 ;
   %s = shufflevector <4 x double> %x, <4 x double> poison, <4 x i32> 
@@ -447,7 +447,7 @@
 define <2 x i32> @fptoui_shuf(<2 x float> %x) {
 ; CHECK-LABEL: @fptoui_shuf(
 ; CHECK-NEXT:[[TMP1:%.*]] = fptoui <2 x float> [[X:%.*]] to <2 x i32>
-; CHECK-NEXT:[[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> 
+; CHECK-NEXT:[[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> 
 ; CHECK-NEXT:ret <2 x i32> [[R]]
 ;
   %s = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> 
Index: llvm/test/Transforms/InstCombine/trunc.ll
===
--- llvm/test/Transforms/InstCombine/trunc.ll
+++ llvm/test/Transforms/InstCombine/trunc.ll
@@ -922,7 +922,7 @@
 define <4 x i8> @wide_splat1(<4 x i32> %x) {
 ; CHECK-LABEL: @wide_splat1(
 ; CHECK-NEXT:[[TMP1:%.*]] = trunc <4 x i32> [[X:%.*]] to <4 x i8>
-; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> undef, <4 x i32> 
+; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> poison, <4 x i32> 
 ; CHECK-NEXT:ret <4 x i8> [[TRUNC]]
 ;
   %shuf = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> 
@@ -936,7 +936,7 @@
 define <3 x i31> @wide_splat2(<3 x i33> %x) {
 ; CHECK-LABEL: @wide_splat2(
 ; CHECK-NEXT:[[TMP1:%.*]] = trunc <3 x i33> [[X:%.*]] to <3 x i31>
-; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <3 x i31> [[TMP1]], <3 x i31> undef, <3 x i32> 
+; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <3 x i31> [[TMP1]], <3 x i31> poison, <3 x i32> 
 ; CHECK-NEXT:ret <3 x i31> [[TRUNC]]
 ;
   %shuf = shufflevector <3 x i33> %x, <3 x i33> undef, <3 x i32> 
Index: llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
===
--- llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
+++ llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
@@ -922,7 +922,7 @@
 define <4 x i8> @wide_splat1(<4 x i32> %x) {
 ; CHECK-LABEL: @wide_splat1(
 ; CHECK-NEXT:[[TMP1:%.*]] = trunc <4 x i32> [[X:%.*]] to <4 x i8>
-; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> undef, <4 x i32> 
+; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> poison, <4 x i32> 
 ; CHECK-NEXT:ret <4 x i8> [[TRUNC]]
 ;
   %shuf = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> 
@@ -936,7 +936,7 @@
 define <3 x i31> @wide_splat2(<3 x i33> %x) {
 ; CHECK-LABEL: @wide_splat2(
 ; CHECK-NEXT:[[TMP1:%.*]] = trunc <3 x i3

[PATCH] D110226: [InstCombine] Update InstCombine to use poison instead of undef for shufflevector's placeholder (1/3)

2021-09-22 Thread Hyeongyu Kim via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe5aaf0332670: [InstCombine] Update InstCombine to use poison 
instead of undef for… (authored by hyeongyukim).

Repository:
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  https://reviews.llvm.org/D110226/new/

https://reviews.llvm.org/D110226

Files:
  clang/test/Headers/wasm.c
  llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
  llvm/test/Transforms/InstCombine/X86/x86-f16c-inseltpoison.ll
  llvm/test/Transforms/InstCombine/X86/x86-f16c.ll
  llvm/test/Transforms/InstCombine/cast.ll
  llvm/test/Transforms/InstCombine/shuffle-cast-dist.ll
  llvm/test/Transforms/InstCombine/shufflevec-bitcast-inseltpoison.ll
  llvm/test/Transforms/InstCombine/shufflevec-bitcast.ll
  llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
  llvm/test/Transforms/InstCombine/trunc.ll
  llvm/test/Transforms/InstCombine/vector-casts.ll

Index: llvm/test/Transforms/InstCombine/vector-casts.ll
===
--- llvm/test/Transforms/InstCombine/vector-casts.ll
+++ llvm/test/Transforms/InstCombine/vector-casts.ll
@@ -414,7 +414,7 @@
 define <4 x float> @sitofp_shuf(<4 x i32> %x) {
 ; CHECK-LABEL: @sitofp_shuf(
 ; CHECK-NEXT:[[TMP1:%.*]] = sitofp <4 x i32> [[X:%.*]] to <4 x float>
-; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> 
+; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> 
 ; CHECK-NEXT:ret <4 x float> [[R]]
 ;
   %s = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> 
@@ -425,7 +425,7 @@
 define <3 x half> @uitofp_shuf(<3 x i16> %x) {
 ; CHECK-LABEL: @uitofp_shuf(
 ; CHECK-NEXT:[[TMP1:%.*]] = uitofp <3 x i16> [[X:%.*]] to <3 x half>
-; CHECK-NEXT:[[R:%.*]] = shufflevector <3 x half> [[TMP1]], <3 x half> undef, <3 x i32> 
+; CHECK-NEXT:[[R:%.*]] = shufflevector <3 x half> [[TMP1]], <3 x half> poison, <3 x i32> 
 ; CHECK-NEXT:ret <3 x half> [[R]]
 ;
   %s = shufflevector <3 x i16> %x, <3 x i16> poison, <3 x i32> 
@@ -436,7 +436,7 @@
 define <4 x i64> @fptosi_shuf(<4 x double> %x) {
 ; CHECK-LABEL: @fptosi_shuf(
 ; CHECK-NEXT:[[TMP1:%.*]] = fptosi <4 x double> [[X:%.*]] to <4 x i64>
-; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> undef, <4 x i32> 
+; CHECK-NEXT:[[R:%.*]] = shufflevector <4 x i64> [[TMP1]], <4 x i64> poison, <4 x i32> 
 ; CHECK-NEXT:ret <4 x i64> [[R]]
 ;
   %s = shufflevector <4 x double> %x, <4 x double> poison, <4 x i32> 
@@ -447,7 +447,7 @@
 define <2 x i32> @fptoui_shuf(<2 x float> %x) {
 ; CHECK-LABEL: @fptoui_shuf(
 ; CHECK-NEXT:[[TMP1:%.*]] = fptoui <2 x float> [[X:%.*]] to <2 x i32>
-; CHECK-NEXT:[[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> 
+; CHECK-NEXT:[[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> 
 ; CHECK-NEXT:ret <2 x i32> [[R]]
 ;
   %s = shufflevector <2 x float> %x, <2 x float> poison, <2 x i32> 
Index: llvm/test/Transforms/InstCombine/trunc.ll
===
--- llvm/test/Transforms/InstCombine/trunc.ll
+++ llvm/test/Transforms/InstCombine/trunc.ll
@@ -922,7 +922,7 @@
 define <4 x i8> @wide_splat1(<4 x i32> %x) {
 ; CHECK-LABEL: @wide_splat1(
 ; CHECK-NEXT:[[TMP1:%.*]] = trunc <4 x i32> [[X:%.*]] to <4 x i8>
-; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> undef, <4 x i32> 
+; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> poison, <4 x i32> 
 ; CHECK-NEXT:ret <4 x i8> [[TRUNC]]
 ;
   %shuf = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> 
@@ -936,7 +936,7 @@
 define <3 x i31> @wide_splat2(<3 x i33> %x) {
 ; CHECK-LABEL: @wide_splat2(
 ; CHECK-NEXT:[[TMP1:%.*]] = trunc <3 x i33> [[X:%.*]] to <3 x i31>
-; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <3 x i31> [[TMP1]], <3 x i31> undef, <3 x i32> 
+; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <3 x i31> [[TMP1]], <3 x i31> poison, <3 x i32> 
 ; CHECK-NEXT:ret <3 x i31> [[TRUNC]]
 ;
   %shuf = shufflevector <3 x i33> %x, <3 x i33> undef, <3 x i32> 
Index: llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
===
--- llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
+++ llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
@@ -922,7 +922,7 @@
 define <4 x i8> @wide_splat1(<4 x i32> %x) {
 ; CHECK-LABEL: @wide_splat1(
 ; CHECK-NEXT:[[TMP1:%.*]] = trunc <4 x i32> [[X:%.*]] to <4 x i8>
-; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> undef, <4 x i32> 
+; CHECK-NEXT:[[TRUNC:%.*]] = shufflevector <4 x i8> [[TMP1]], <4 x i8> poison, <4 x i32> 
 ; CHECK-NEXT:ret <4 x i8> [[TRUNC]]
 ;
   %shuf = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> 
@@ -936,7 +936,7 @@
 define <3 x

[PATCH] D110230: [InstCombine] Update InstCombine to use poison instead of undef for shufflevector's placeholder (3/3)

2021-09-22 Thread Hyeongyu Kim via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG98e96663f6a7: [InstCombine] Update InstCombine to use poison 
instead of undef for… (authored by hyeongyukim).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Changed prior to commit:
  https://reviews.llvm.org/D110230?vs=374192&id=374249#toc

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Files:
  clang/test/CodeGen/aarch64-bf16-ldst-intrinsics.c
  clang/test/CodeGen/aarch64-neon-dot-product.c
  clang/test/CodeGen/arm-neon-dot-product.c
  llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
  llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
  llvm/test/Transforms/InstCombine/X86/x86-avx512.ll
  llvm/test/Transforms/InstCombine/X86/x86-f16c-inseltpoison.ll
  llvm/test/Transforms/InstCombine/X86/x86-f16c.ll
  llvm/test/Transforms/InstCombine/broadcast-inseltpoison.ll
  llvm/test/Transforms/InstCombine/broadcast.ll
  llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll
  llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
  llvm/test/Transforms/InstCombine/obfuscated_splat-inseltpoison.ll
  llvm/test/Transforms/InstCombine/obfuscated_splat.ll
  llvm/test/Transforms/InstCombine/reduction-shufflevector.ll
  llvm/test/Transforms/InstCombine/shuffle-cast-dist.ll
  llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
  llvm/test/Transforms/InstCombine/trunc.ll
  llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
  llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
  llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
  llvm/test/Transforms/InstCombine/vec_shuffle.ll

Index: llvm/test/Transforms/InstCombine/vec_shuffle.ll
===
--- llvm/test/Transforms/InstCombine/vec_shuffle.ll
+++ llvm/test/Transforms/InstCombine/vec_shuffle.ll
@@ -713,8 +713,8 @@
 ; Do not reorder shuffle and binop if LHS of shuffles are of different size
 define <2 x i32> @pr19717(<4 x i32> %in0, <2 x i32> %in1) {
 ; CHECK-LABEL: @pr19717(
-; CHECK-NEXT:[[SHUFFLE:%.*]] = shufflevector <4 x i32> [[IN0:%.*]], <4 x i32> undef, <2 x i32> zeroinitializer
-; CHECK-NEXT:[[SHUFFLE4:%.*]] = shufflevector <2 x i32> [[IN1:%.*]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:[[SHUFFLE:%.*]] = shufflevector <4 x i32> [[IN0:%.*]], <4 x i32> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT:[[SHUFFLE4:%.*]] = shufflevector <2 x i32> [[IN1:%.*]], <2 x i32> poison, <2 x i32> zeroinitializer
 ; CHECK-NEXT:[[MUL:%.*]] = mul <2 x i32> [[SHUFFLE]], [[SHUFFLE4]]
 ; CHECK-NEXT:ret <2 x i32> [[MUL]]
 ;
@@ -1413,7 +1413,7 @@
 
 define <4 x double> @insert_subvector_shuffles_identity(<2 x double> %x) {
 ; CHECK-LABEL: @insert_subvector_shuffles_identity(
-; CHECK-NEXT:[[S3:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> undef, <4 x i32> 
+; CHECK-NEXT:[[S3:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> poison, <4 x i32> 
 ; CHECK-NEXT:ret <4 x double> [[S3]]
 ;
   %s1 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> 
@@ -1458,7 +1458,7 @@
 define <4 x float> @insert_subvector_crash_invalid_mask_elt(<2 x float> %x, <4 x float>* %p) {
 ; CHECK-LABEL: @insert_subvector_crash_invalid_mask_elt(
 ; CHECK-NEXT:[[WIDEN:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> undef, <4 x i32> 
-; CHECK-NEXT:[[I:%.*]] = shufflevector <2 x float> [[X]], <2 x float> undef, <4 x i32> 
+; CHECK-NEXT:[[I:%.*]] = shufflevector <2 x float> [[X]], <2 x float> poison, <4 x i32> 
 ; CHECK-NEXT:store <4 x float> [[I]], <4 x float>* [[P:%.*]], align 16
 ; CHECK-NEXT:ret <4 x float> [[WIDEN]]
 ;
Index: llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
===
--- llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
+++ llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
@@ -713,8 +713,8 @@
 ; Do not reorder shuffle and binop if LHS of shuffles are of different size
 define <2 x i32> @pr19717(<4 x i32> %in0, <2 x i32> %in1) {
 ; CHECK-LABEL: @pr19717(
-; CHECK-NEXT:[[SHUFFLE:%.*]] = shufflevector <4 x i32> [[IN0:%.*]], <4 x i32> undef, <2 x i32> zeroinitializer
-; CHECK-NEXT:[[SHUFFLE4:%.*]] = shufflevector <2 x i32> [[IN1:%.*]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:[[SHUFFLE:%.*]] = shufflevector <4 x i32> [[IN0:%.*]], <4 x i32> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT:[[SHUFFLE4:%.*]] = shufflevector <2 x i32> [[IN1:%.*]], <2 x i32> poison, <2 x i32> zeroinitializer
 ; CHECK-NEXT:[[MUL:%.*]] = mul <2 x i32> [[SHUFFLE]], [[SHUFFLE4]]
 ; CHECK-NEXT:ret <2 x i32> [[MUL]]
 ;
@@ -1413,7 +1413,7 @@
 
 define <4 x double> @insert_subvector_shuffles_identity(<2 x dou

[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2021-11-01 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

I checked the reason for failure in address sanitizer tests on the 2-stage 
aarch64 buildbots.
The buildbot failure was occured because the `internal_clone` function of the 
`compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp` file is being compiled 
incorrectly.
The `internal_clone` function is a simple function that calls the clone system 
call of Linux. Its original return value should be the PID of the newly created 
process, but the actual returned value is 220 (which is the `__NR_clone` value.)

The aarch64 assembly changed by this patch is as follows.

  // before
  84: d2801b88  mov x8, #0xdc                   // #0xdc(220): system call 
number of clone
  88: d401  svc #0x0                        // system call
  ...
  a4: a9434ff4  ldp x20, x19, [sp, #48]
  a8: a94257f6  ldp x22, x21, [sp, #32]
  ac: a9415ff8  ldp x24, x23, [sp, #16]
  b0: a8c467fe  ldp x30, x25, [sp], #64
  b4: d65f03c0  ret
  
  =
  // after
  88: d2801b88  mov x8, #0xdc                   // #0xdc(220): system call 
number of clone
  8c: d401  svc #0x0                        // system call
  ...
  a8: a9434ff4  ldp x20, x19, [sp, #48]
  ac: aa0803e0  mov x0, x8                      // return value(x0) was 
overwritten by 0xdc(220)
  b0: a94257f6  ldp x22, x21, [sp, #32]
  b4: a9415ff8  ldp x24, x23, [sp, #16]
  b8: a8c467fe  ldp x30, x25, [sp], #64
  bc: d65f03c0  ret

Does anyone know why the `internal_clone` function of aarch64 is affected by 
this patch?


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[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2021-11-05 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

  diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp 
b/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
  index ea3e5bdbc754..826c6d36e1b1 100644
  --- a/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
  +++ b/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
  @@ -1360,7 +1360,7 @@ uptr internal_clone(int (*fn)(void *), void 
*child_stack, int flags, void *arg,
   #elif defined(__aarch64__)
   uptr internal_clone(int (*fn)(void *), void *child_stack, int flags, void 
*arg,
   int *parent_tidptr, void *newtls, int *child_tidptr) {
  -  long long res;
  +  register long long res __asm__("x0");
 if (!fn || !child_stack)
   return -EINVAL;
 CHECK_EQ(0, (uptr)child_stack % 16);

After modifying `internal_clone` like this, the problem disappeared.
Is it okay to commit this change by myself?


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[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2021-11-08 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

In D105169#3115814 , @erichkeane 
wrote:

> Either this or D108453  (which were 
> committed together!) caused this assert according to my git-bisect: 
> https://godbolt.org/z/4rqYKfW7K
>
> NOTE that this fails in a lit-test for me, clang CodeGen/ifunc.c (though my 
> downstream seems to run the verifier even with -emit-llvm, so you might need 
> to just swap it to an -emit-obj to get this to repro).
>
> If you cannot fix this quickly, let me know and I can revert it.
>
> IR for this looks like:
>
>   [ekeane1@scsel-clx-24 llvm]$ 
> /localdisk2/ekeane1/workspaces/xmain-web/builds/xmainefi2linux_debug/llvm/bin/clang
>  -cc1 -internal-isystem 
> /localdisk2/ekeane1/workspaces/xmain-web/builds/xmainefi2linux_debug/llvm/lib/clang/14.0.0/include
>  -nostdsysteminc -triple i386-unknown-linux-gnu -emit-llvm -o - 
> /localdisk2/ekeane1/workspaces/xmain-web/llvm/clang/test/CodeGen/ifunc.c 
> -disable-llvm-passes
>   ; ModuleID = 
> '/localdisk2/ekeane1/workspaces/xmain-web/llvm/clang/test/CodeGen/ifunc.c'
>   source_filename = 
> "/localdisk2/ekeane1/workspaces/xmain-web/llvm/clang/test/CodeGen/ifunc.c"
>   target datalayout = 
> "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-f80:32-n8:16:32-S128"
>   target triple = "i386-unknown-linux-gnu"
>   
>   @global = global i32 0, align 4
>   
>   @foo = ifunc i32 (i32), i32 (i32)* ()* @foo_ifunc
>   @goo = ifunc void (), bitcast (i8* ()* @goo_ifunc to void ()* ()*)
>   
>   ; Function Attrs: noinline nounwind optnone
>   define internal i32 (i32)* @foo_ifunc() #0 {
>   entry:
> %0 = load i32, i32* @global, align 4
> %tobool = icmp ne i32 %0, 0
> %1 = zext i1 %tobool to i64
> %cond = select i1 %tobool, i32 (i32)* @f1, i32 (i32)* @f2
> ret i32 (i32)* %cond
>   }
>   
>   ; Function Attrs: noinline nounwind optnone
>   define dso_local i32 @bar() #0 {
>   entry:
> %call = call i32 @foo(i32 noundef 1)
> ret i32 %call
>   }
>   
>   ; Function Attrs: noinline nounwind optnone
>   define dso_local void @bar2() #0 {
>   entry:
> call void @goo()
> ret void
>   }
>   
>   ; Function Attrs: noinline nounwind optnone
>   define dso_local i8* @goo_ifunc() #0 {
>   entry:
> ret i8* null
>   }
>   
>   ; Function Attrs: noinline nounwind optnone
>   define internal i32 @f1(i32 noundef %i) #0 {
>   entry:
> %i.addr = alloca i32, align 4
> store i32 %i, i32* %i.addr, align 4
> %0 = load i32, i32* %i.addr, align 4
> %add = add nsw i32 %0, 1
> ret i32 %add
>   }
>   
>   ; Function Attrs: noinline nounwind optnone
>   define internal i32 @f2(i32 noundef %i) #0 {
>   entry:
> %i.addr = alloca i32, align 4
> store i32 %i, i32* %i.addr, align 4
> %0 = load i32, i32* %i.addr, align 4
> %add = add nsw i32 %0, 2
> ret i32 %add
>   }
>   
>   attributes #0 = { noinline nounwind optnone "frame-pointer"="none" 
> "min-legal-vector-width"="0" "no-trapping-math"="true" 
> "stack-protector-buffer-size"="8" "target-features"="+cx8,+x87" }
>   
>   !llvm.module.flags = !{!0, !1}
>   !llvm.ident = !{!2}
>   
>   !0 = !{i32 1, !"NumRegisterParameters", i32 0}
>   !1 = !{i32 1, !"wchar_size", i32 4}
>   !2 = !{!"Intel(R) oneAPI DPC++/C++ Compiler 2022.1.0 (2022.x.0.MMDD)"}

Hmm.. I'll revert it.


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[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2021-11-14 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

In D105169#3115814 , @erichkeane 
wrote:

> Either this or D108453  (which were 
> committed together!) caused this assert according to my git-bisect: 
> https://godbolt.org/z/4rqYKfW7K
>
> NOTE that this fails in a lit-test for me, clang CodeGen/ifunc.c (though my 
> downstream seems to run the verifier even with -emit-llvm, so you might need 
> to just swap it to an -emit-obj to get this to repro).

The lit-test failure of CodeGen/ifunc.c was not directly related to this patch.
`emitIFuncDefinition` was creating an incorrect function attribute.
It added the noundef attribute to the function even though there are no 
parameters (`foo_ifunc` function of `ifunc.c`), and it was fixed a few days ago.

The patch that solved this problem is D113352 
.

> The `emitIFuncDefinition` fucntion incorrectly passes the GlobalDecl of the 
> IFunc itself to the call to GetOrCreateLLVMFunction for creating the 
> resolver, which causes it to be created with a wrong attribute list, which 
> fails `Verifier::visitFunction` with "Attribute after last parameter!". 
> You'll note that unlike the relationship between aliases and their aliasees, 
> the resolver and the ifunc have different types - the resolver takes no 
> parameters.




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[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2022-01-11 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

@nathanchance

I tried to reproduce the last warning (intelfbhw_validate_mode), but I failed 
to produce it.
I think my reproducer is correct, but it does not make any warning.
Can you tell me which part was wrong?

  clang -O2 -flto=thin -fsanitize=integer-divide-by-zero -c -o intelfb.o 
intelfb.i
  ld.lld -m elf_x86_64 -r -o intelfb.lto.o --whole-archive intelfb.o
  objtool orc generate --module --no-fp --no-unreachable --uaccess --mcount 
intelfb.lto.o

I use these commands, and I attached the `intelfb.i` file.F21595840: intelfb.i 



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[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2022-01-13 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

@nathanchance 
You were right. I succeeded in reproducing the warning with 
`-fsanitize-coverage=trace-pc`
However, this problem seems to be fixed in the latest version. (I used 
`57a551a`)


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[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2022-01-14 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

@nathanchance Hi, I analyzed all four warnings.

Warning #1: can be handled by x86-backend. filled issue #53118 

Warning #2: bug in the kernel, fixed in the next version.
Warning #3: same reason with #2
Warning #4: It was not reproduced in the latest clang.

As you see, one of this patch's advantages is that it exposed some bugs in the 
kernel!
All issues are either identified or will be fixed soon. Is it okay to recommit 
this patch?


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[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2021-12-28 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

In D105169#3116810 , @nathanchance 
wrote:

> Prior to the latest revert (fd9b099906c61e46574d1ea2d99b973321fe1d21 
> ), the 
> Linux kernel's binary verifier (`objtool`) points out an issue when building 
> with ThinLTO and `-fsanitize=integer-divide-by-zero`. I have no idea if this 
> is an issue with the tool or this series. A simplified reproducer:
>
>   $ cat ravb_main.i
>   int ravb_set_gti_ndev_rate;
>   unsigned int ravb_set_gti_ndev_inc;
>   void ravb_set_gti_ndev() {
> ravb_set_gti_ndev_inc = 10;
> ravb_set_gti_ndev_inc = ravb_set_gti_ndev_inc / ravb_set_gti_ndev_rate;
> if (ravb_set_gti_ndev_inc)
>   _dev_err(ravb_set_gti_ndev_inc);
>   }
>   
>   $ clang -std=gnu89 -O2 -flto=thin -fsanitize=integer-divide-by-zero -c -o 
> ravb_main.o ravb_main.i
>   
>   $ llvm-ar cDPrsT ravb.o ravb_main.o
>   
>   $ ld.lld -m elf_x86_64 -r -o ravb.lto.o --whole-archive ravb.o
>   
>   $ ./objtool orc generate --no-fp --no-unreachable --retpoline --uaccess 
> --mcount --module ravb.lto.o
>   ravb.lto.o: warning: objtool: .text.ravb_set_gti_ndev: unexpected end of 
> section
>
> With LLVM 13.0.0, there is no warning with those commands. The original and 
> reduced `.i` file, interestingness test, and static `objtool` binary are 
> available here 
> .

I checked the reason why Objtool makes a warning.

  cont.thread:  ; preds = %entry
tail call void @__ubsan_handle_divrem_overflow(i8* bitcast ({ { [12 x i8]*, 
i32, i32 }, { i16, i16, [15 x i8] }* }* @1 to i8*), i64 10, i64 0) #3, 
!nosanitize !8
br label %if.then
  
  cont: ; preds = %entry
%div = udiv i32 10, %0
store i32 %div, i32* @ravb_set_gti_ndev_inc, align 4, !tbaa !4
%tobool.not = icmp ugt i32 %0, 10
br i1 %tobool.not, label %if.end, label %if.then
  
  if.then:  ; preds = %cont.thread, 
%cont
%div3 = phi i32 [ poison, %cont.thread ], [ %div, %cont ]
%call = tail call i32 (i32, ...) bitcast (i32 (...)* @_dev_err to i32 (i32, 
...)*)(i32 noundef %div3) #3
br label %if.end

This IR code is an IR that has not passed the optimization pass completely.
This code calculates the division only if `ravb_set_gti_ndev_rate` is non-zero 
and it calls `ubsan_handle_divrem_overflow` function to handle UB if 
`ravb_set_gti_ndev_rate` is zero.
So far, there is no warning. But a warning occurs when this code passes the 
SimpleCFG optimization.

  cont.thread:  ; preds = %entry
tail call void @__ubsan_handle_divrem_overflow(i8* bitcast ({ { [12 x i8]*, 
i32, i32 }, { i16, i16, [15 x i8] }* }* @1 to i8*), i64 10, i64 0) #3, 
!nosanitize !8
unreachable
  
  cont: ; preds = %entry
%div = udiv i32 10, %0
store i32 %div, i32* @ravb_set_gti_ndev_inc, align 4, !tbaa !4
%tobool.not = icmp ugt i32 %0, 10
br i1 %tobool.not, label %if.end, label %if.then
  
  if.then:  ; preds = %cont
%call = tail call i32 (i32, ...) bitcast (i32 (...)* @_dev_err to i32 (i32, 
...)*)(i32 noundef %div) #3
br label %if.end
  
  if.end:   ; preds = %if.then, %cont
ret void
  }

After it passes the SimplyCFG, the `br` instruction was changed to the 
`unreachable` instruction in `cont.thread` block.

This patch added noundef to the parameter of the `_dev_err` function, making 
the `%div3` unable to be Poison.
It is impossible to jump from the `cont.thread` block to `if.then` block, so 
`br` instruction was changed to `unreachable` instruction.
It would be nice to remove the unreachable block, but the above IR is not wrong 
because it is UB when `ravb_set_gti_ndev_rate` is zero.

There seems to be no existing problem in clang, and I think we can bypass this 
warning by adding a code that checks whether the `gravb_set_gti_ndev_rate` is 
zero or not as follows.

  int ravb_set_gti_ndev_rate;
  unsigned int ravb_set_gti_ndev_inc;
  void ravb_set_gti_ndev() {
ravb_set_gti_ndev_inc = 10;
ravb_set_gti_ndev_inc = ravb_set_gti_ndev_inc / ravb_set_gti_ndev_rate;
if (ravb_set_gti_ndev_rate != 0)
  if (ravb_set_gti_ndev_inc)
_dev_err(ravb_set_gti_ndev_inc);
  }

@nathanchance How about changing the existing test code as above?


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[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2021-12-28 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

In D105169#3211929 , @nathanchance 
wrote:

> @hyeongyukim I am currently offline for the evening but it seems like my 
> reduction might have been too aggressive. It looks like this code comes from 
> `ravb_set_gti()` 
> (https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/ethernet/renesas/ravb_main.c?h=v5.16-rc7#n2480),
>  which checks that `rate` is not zero before using it as a divisor. I will 
> see if I can get a reproducer without any undefined behavior such as this.

Okay! Thank you for your response.


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[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2021-12-29 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

Great. I'll check it out.

> I have a reproducer for the first two, as that is all I had time for; if you 
> would like them for the other two, I can get those for you tomorrow.

@nathanchance I think the other two can be reproduced without difficulty. If 
the reproduction fails, I will request it :)


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[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2021-10-07 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

Thank you!
In the meantime, I will rebase this patch and resolve conflicts.


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[PATCH] D108453: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default (2)

2021-10-15 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim updated this revision to Diff 380037.
hyeongyukim added a comment.

Rebase


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Files:
  clang/test/CXX/except/except.spec/p14-ir.cpp
  clang/test/CXX/expr/expr.prim/expr.prim.lambda/blocks-irgen.mm
  clang/test/CodeGen/2005-01-02-ConstantInits.c
  clang/test/CodeGen/2006-05-19-SingleEltReturn.c
  clang/test/CodeGen/2007-06-18-SextAttrAggregate.c
  clang/test/CodeGen/2009-02-13-zerosize-union-field.c
  clang/test/CodeGen/2009-05-04-EnumInreg.c
  clang/test/CodeGen/64bit-swiftcall.c
  clang/test/CodeGen/RISCV/riscv-inline-asm.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/SystemZ/systemz-abi-vector.c
  clang/test/CodeGen/SystemZ/systemz-abi.c
  clang/test/CodeGen/SystemZ/systemz-inline-asm.c
  clang/test/CodeGen/WebAssembly/wasm-arguments.c
  clang/test/CodeGen/WebAssembly/wasm-main_argc_argv.c
  clang/test/CodeGen/X86/avx-union.c
  clang/test/CodeGen/X86/avx512fp16-complex-abi.c
  clang/test/CodeGen/X86/ms-x86-intrinsics.c
  clang/test/CodeGen/X86/strictfp_builtins.c
  clang/test/CodeGen/X86/x86-atomic-long_double.c
  clang/test/CodeGen/X86/x86-inline-asm-min-vector-width.c
  clang/test/CodeGen/X86/x86-long-double.cpp
  clang/test/CodeGen/X86/x86-soft-float.c
  clang/test/CodeGen/X86/x86-vec-i128.c
  clang/test/CodeGen/X86/x86_32-arguments-darwin.c
  clang/test/CodeGen/X86/x86_32-arguments-iamcu.c
  clang/test/CodeGen/X86/x86_32-arguments-linux.c
  clang/test/CodeGen/X86/x86_32-arguments-nommx.c
  clang/test/CodeGen/X86/x86_32-arguments-realign.c
  clang/test/CodeGen/X86/x86_32-arguments-win32.c
  clang/test/CodeGen/X86/x86_64-arguments-nacl.c
  clang/test/CodeGen/X86/x86_64-arguments-win32.c
  clang/test/CodeGen/X86/x86_64-arguments.c
  clang/test/CodeGen/X86/x86_64-longdouble.c
  clang/test/CodeGen/aapcs-align.cpp
  clang/test/CodeGen/aapcs64-align.cpp
  clang/test/CodeGen/aarch64-args.cpp
  clang/test/CodeGen/aarch64-byval-temp.c
  clang/test/CodeGen/aarch64-neon-3v.c
  clang/test/CodeGen/aarch64-neon-across.c
  clang/test/CodeGen/aarch64-neon-dot-product.c
  clang/test/CodeGen/aarch64-neon-extract.c
  clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c
  clang/test/CodeGen/aarch64-neon-fma.c
  clang/test/CodeGen/aarch64-neon-ldst-one.c
  clang/test/CodeGen/aarch64-neon-scalar-copy.c
  clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c
  clang/test/CodeGen/aarch64-neon-tbl.c
  clang/test/CodeGen/aarch64-neon-vcombine.c
  clang/test/CodeGen/aarch64-neon-vget-hilo.c
  clang/test/CodeGen/aarch64-neon-vget.c
  clang/test/CodeGen/aarch64-poly128.c
  clang/test/CodeGen/aarch64-poly64.c
  clang/test/CodeGen/aarch64-strictfp-builtins.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
  clang/test/CodeGen/aarch64-varargs.c
  clang/test/CodeGen/address-space-field1.c
  clang/test/CodeGen/address-space.c
  clang/test/CodeGen/aix-alignment.c
  clang/test/CodeGen/aix-altivec.c
  clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
  clang/test/CodeGen/aix-return.c
  clang/test/CodeGen/aix-struct-arg.c
  clang/test/CodeGen/aix-vaargs.c
  clang/test/CodeGen/alias.c
  clang/test/CodeGen/align_value.cpp
  clang/test/CodeGen/alloc-align-attr.c
  clang/test/CodeGen/alloc-fns-alignment.c
  clang/test/CodeGen/alloc-size-fnptr.c
  clang/test/CodeGen/arc/arguments.c
  clang/test/CodeGen/arithmetic-fence-builtin.c
  clang/test/CodeGen/arm-aapcs-vfp.c
  clang/test/CodeGen/arm-abi-vector.c
  clang/test/CodeGen/arm-arguments.c
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-byval-align.c
  clang/test/CodeGen/arm-cmse-attr.c
  clang/test/CodeGen/arm-cmse-call.c
  clang/test/CodeGen/arm-float-helpers.c
  clang/test/CodeGen/arm-fp16-arguments.c
  clang/test/CodeGen/arm-homogenous.c
  clang/test/CodeGen/arm-mangle-bf16.cpp
  clang/test/CodeGen/arm-neon-directed-rounding.c
  clang/test/CodeGen/arm-neon-dot-product.c
  clang/test/CodeGen/arm-neon-fma.c
  clang/test/CodeGen/arm-neon-numeric-maxmin.c
  clang/test/CodeGen/arm-neon-vcvtX.c
  clang/test/CodeGen/arm-swiftcall.c
  clang/test/CodeGen/arm-varargs.c
  clang/test/CodeGen/arm-vector-arguments.c
  clang/test/CodeGen/arm-vfp16-arguments.c
  clang/test/CodeGen/arm64-aapcs-arguments.c
  clang/test/CodeGen/arm64-abi-vector.c
  clang/test/CodeGen/arm64-arguments.c
  clang/test/Cod

[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2021-10-15 Thread Hyeongyu Kim via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG80dba72a669b: [Clang/Test]: Rename enable_noundef_analysis 
to disable-noundef-analysis and… (authored by aqjune, committed by hyeongyukim).

Changed prior to commit:
  https://reviews.llvm.org/D105169?vs=368033&id=380136#toc

Repository:
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Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/CGCall.cpp


Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -2255,7 +2255,7 @@
  getLangOpts().Sanitize.has(SanitizerKind::Return);
 
   // Determine if the return type could be partially undef
-  if (CodeGenOpts.EnableNoundefAttrs && HasStrictReturn) {
+  if (!CodeGenOpts.DisableNoundefAttrs && HasStrictReturn) {
 if (!RetTy->isVoidType() && RetAI.getKind() != ABIArgInfo::Indirect &&
 DetermineNoUndef(RetTy, getTypes(), DL, RetAI))
   RetAttrs.addAttribute(llvm::Attribute::NoUndef);
@@ -2390,7 +2390,7 @@
 
 // Decide whether the argument we're handling could be partially undef
 bool ArgNoUndef = DetermineNoUndef(ParamType, getTypes(), DL, AI);
-if (CodeGenOpts.EnableNoundefAttrs && ArgNoUndef)
+if (!CodeGenOpts.DisableNoundefAttrs && ArgNoUndef)
   Attrs.addAttribute(llvm::Attribute::NoUndef);
 
 // 'restrict' -> 'noalias' is done in EmitFunctionProlog when we
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -5314,9 +5314,9 @@
 def clear_ast_before_backend : Flag<["-"], "clear-ast-before-backend">,
   HelpText<"Clear the Clang AST before running backend code generation">,
   MarshallingInfoFlag>;
-def enable_noundef_analysis : Flag<["-"], "enable-noundef-analysis">, 
Group,
-  HelpText<"Enable analyzing function argument and return types for mandatory 
definedness">,
-  MarshallingInfoFlag>;
+def disable_noundef_analysis : Flag<["-"], "disable-noundef-analysis">, 
Group,
+  HelpText<"Disable analyzing function argument and return types for mandatory 
definedness">,
+  MarshallingInfoFlag>;
 def discard_value_names : Flag<["-"], "discard-value-names">,
   HelpText<"Discard value names in LLVM IR">,
   MarshallingInfoFlag>;
Index: clang/include/clang/Basic/CodeGenOptions.def
===
--- clang/include/clang/Basic/CodeGenOptions.def
+++ clang/include/clang/Basic/CodeGenOptions.def
@@ -64,7 +64,7 @@
 CODEGENOPT(DisableO0ImplyOptNone , 1, 0) ///< Don't annonate function with 
optnone at O0
 CODEGENOPT(ExperimentalStrictFloatingPoint, 1, 0) ///< Enables the new, 
experimental
   ///< strict floating point.
-CODEGENOPT(EnableNoundefAttrs, 1, 0) ///< Enable emitting `noundef` attributes 
on IR call arguments and return values
+CODEGENOPT(DisableNoundefAttrs, 1, 0) ///< Disable emitting `noundef` 
attributes on IR call arguments and return values
 CODEGENOPT(LegacyPassManager, 1, 0) ///< Use the legacy pass manager.
 CODEGENOPT(DebugPassManager, 1, 0) ///< Prints debug information for the new
///< pass manager.


Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -2255,7 +2255,7 @@
  getLangOpts().Sanitize.has(SanitizerKind::Return);
 
   // Determine if the return type could be partially undef
-  if (CodeGenOpts.EnableNoundefAttrs && HasStrictReturn) {
+  if (!CodeGenOpts.DisableNoundefAttrs && HasStrictReturn) {
 if (!RetTy->isVoidType() && RetAI.getKind() != ABIArgInfo::Indirect &&
 DetermineNoUndef(RetTy, getTypes(), DL, RetAI))
   RetAttrs.addAttribute(llvm::Attribute::NoUndef);
@@ -2390,7 +2390,7 @@
 
 // Decide whether the argument we're handling could be partially undef
 bool ArgNoUndef = DetermineNoUndef(ParamType, getTypes(), DL, AI);
-if (CodeGenOpts.EnableNoundefAttrs && ArgNoUndef)
+if (!CodeGenOpts.DisableNoundefAttrs && ArgNoUndef)
   Attrs.addAttribute(llvm::Attribute::NoUndef);
 
 // 'restrict' -> 'noalias' is done in EmitFunctionProlog when we
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -5314,9 +5314,9 @@
 def clear_ast_before_backend : Flag<["-"], "clear-ast-before-backend">,
   HelpText<"Clear the Clang AST before running backend code generation">,
   MarshallingInfoFlag>;
-

[PATCH] D108453: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default (2)

2021-10-17 Thread Hyeongyu Kim via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8ca4b3ef19fe: [Clang/Test]: Rename enable_noundef_analysis 
to disable-noundef-analysis and… (authored by aqjune, committed by hyeongyukim).

Repository:
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Files:
  clang/test/CXX/except/except.spec/p14-ir.cpp
  clang/test/CXX/expr/expr.prim/expr.prim.lambda/blocks-irgen.mm
  clang/test/CodeGen/2005-01-02-ConstantInits.c
  clang/test/CodeGen/2006-05-19-SingleEltReturn.c
  clang/test/CodeGen/2007-06-18-SextAttrAggregate.c
  clang/test/CodeGen/2009-02-13-zerosize-union-field.c
  clang/test/CodeGen/2009-05-04-EnumInreg.c
  clang/test/CodeGen/64bit-swiftcall.c
  clang/test/CodeGen/RISCV/riscv-inline-asm.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/SystemZ/systemz-abi-vector.c
  clang/test/CodeGen/SystemZ/systemz-abi.c
  clang/test/CodeGen/SystemZ/systemz-inline-asm.c
  clang/test/CodeGen/WebAssembly/wasm-arguments.c
  clang/test/CodeGen/WebAssembly/wasm-main_argc_argv.c
  clang/test/CodeGen/X86/avx-union.c
  clang/test/CodeGen/X86/avx512fp16-complex-abi.c
  clang/test/CodeGen/X86/ms-x86-intrinsics.c
  clang/test/CodeGen/X86/strictfp_builtins.c
  clang/test/CodeGen/X86/x86-atomic-long_double.c
  clang/test/CodeGen/X86/x86-inline-asm-min-vector-width.c
  clang/test/CodeGen/X86/x86-long-double.cpp
  clang/test/CodeGen/X86/x86-soft-float.c
  clang/test/CodeGen/X86/x86-vec-i128.c
  clang/test/CodeGen/X86/x86_32-arguments-darwin.c
  clang/test/CodeGen/X86/x86_32-arguments-iamcu.c
  clang/test/CodeGen/X86/x86_32-arguments-linux.c
  clang/test/CodeGen/X86/x86_32-arguments-nommx.c
  clang/test/CodeGen/X86/x86_32-arguments-realign.c
  clang/test/CodeGen/X86/x86_32-arguments-win32.c
  clang/test/CodeGen/X86/x86_64-arguments-nacl.c
  clang/test/CodeGen/X86/x86_64-arguments-win32.c
  clang/test/CodeGen/X86/x86_64-arguments.c
  clang/test/CodeGen/X86/x86_64-longdouble.c
  clang/test/CodeGen/aapcs-align.cpp
  clang/test/CodeGen/aapcs64-align.cpp
  clang/test/CodeGen/aarch64-args.cpp
  clang/test/CodeGen/aarch64-byval-temp.c
  clang/test/CodeGen/aarch64-neon-3v.c
  clang/test/CodeGen/aarch64-neon-across.c
  clang/test/CodeGen/aarch64-neon-dot-product.c
  clang/test/CodeGen/aarch64-neon-extract.c
  clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c
  clang/test/CodeGen/aarch64-neon-fma.c
  clang/test/CodeGen/aarch64-neon-ldst-one.c
  clang/test/CodeGen/aarch64-neon-scalar-copy.c
  clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c
  clang/test/CodeGen/aarch64-neon-tbl.c
  clang/test/CodeGen/aarch64-neon-vcombine.c
  clang/test/CodeGen/aarch64-neon-vget-hilo.c
  clang/test/CodeGen/aarch64-neon-vget.c
  clang/test/CodeGen/aarch64-poly128.c
  clang/test/CodeGen/aarch64-poly64.c
  clang/test/CodeGen/aarch64-strictfp-builtins.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
  clang/test/CodeGen/aarch64-varargs.c
  clang/test/CodeGen/address-space-field1.c
  clang/test/CodeGen/address-space.c
  clang/test/CodeGen/aix-alignment.c
  clang/test/CodeGen/aix-altivec.c
  clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
  clang/test/CodeGen/aix-return.c
  clang/test/CodeGen/aix-struct-arg.c
  clang/test/CodeGen/aix-vaargs.c
  clang/test/CodeGen/alias.c
  clang/test/CodeGen/align_value.cpp
  clang/test/CodeGen/alloc-align-attr.c
  clang/test/CodeGen/alloc-fns-alignment.c
  clang/test/CodeGen/alloc-size-fnptr.c
  clang/test/CodeGen/arc/arguments.c
  clang/test/CodeGen/arithmetic-fence-builtin.c
  clang/test/CodeGen/arm-aapcs-vfp.c
  clang/test/CodeGen/arm-abi-vector.c
  clang/test/CodeGen/arm-arguments.c
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-byval-align.c
  clang/test/CodeGen/arm-cmse-attr.c
  clang/test/CodeGen/arm-cmse-call.c
  clang/test/CodeGen/arm-float-helpers.c
  clang/test/CodeGen/arm-fp16-arguments.c
  clang/test/CodeGen/arm-homogenous.c
  clang/test/CodeGen/arm-mangle-bf16.cpp
  clang/test/CodeGen/arm-neon-directed-rounding.c
  clang/test/CodeGen/arm-neon-dot-product.c
  clang/test/CodeGen/arm-neon-fma.c
  clang/test/CodeGen/arm-neon-numeric-maxmin.c
  clang/test/CodeGen/arm-neon-vcvtX.c
  clang/test/CodeGen/arm-swiftcall.c
  clang/test/CodeGen/arm-varargs.c
  clang/test/CodeGen/arm-

[PATCH] D105169: [Clang/Test]: Enable enable_noundef_analysis as default

2021-08-20 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim updated this revision to Diff 367746.
hyeongyukim added a comment.
Herald added subscribers: cfe-commits, dexonsmith.

Changed `disable_noundef_args` flag to `enable_noundef_args` to enable emitting 
`noundef` attributes on IR call arguments and return values by default.
Changed test codes will be attached at another PR.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105169/new/

https://reviews.llvm.org/D105169

Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/CodeGen/CGCall.cpp


Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -2258,7 +2258,7 @@
  getLangOpts().Sanitize.has(SanitizerKind::Return);
 
   // Determine if the return type could be partially undef
-  if (CodeGenOpts.EnableNoundefAttrs && HasStrictReturn) {
+  if (!CodeGenOpts.DisableNoundefAttrs && HasStrictReturn) {
 if (!RetTy->isVoidType() && RetAI.getKind() != ABIArgInfo::Indirect &&
 DetermineNoUndef(RetTy, getTypes(), DL, RetAI))
   RetAttrs.addAttribute(llvm::Attribute::NoUndef);
@@ -2393,7 +2393,7 @@
 
 // Decide whether the argument we're handling could be partially undef
 bool ArgNoUndef = DetermineNoUndef(ParamType, getTypes(), DL, AI);
-if (CodeGenOpts.EnableNoundefAttrs && ArgNoUndef)
+if (!CodeGenOpts.DisableNoundefAttrs && ArgNoUndef)
   Attrs.addAttribute(llvm::Attribute::NoUndef);
 
 // 'restrict' -> 'noalias' is done in EmitFunctionProlog when we
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -5260,9 +5260,9 @@
 def disable_free : Flag<["-"], "disable-free">,
   HelpText<"Disable freeing of memory on exit">,
   MarshallingInfoFlag>;
-def enable_noundef_analysis : Flag<["-"], "enable-noundef-analysis">, 
Group,
-  HelpText<"Enable analyzing function argument and return types for mandatory 
definedness">,
-  MarshallingInfoFlag>;
+def disable_noundef_analysis : Flag<["-"], "disable-noundef-args">, 
Group,
+  HelpText<"Disable analyzing function argument and return types for mandatory 
definedness">,
+  MarshallingInfoFlag>;
 def discard_value_names : Flag<["-"], "discard-value-names">,
   HelpText<"Discard value names in LLVM IR">,
   MarshallingInfoFlag>;
Index: clang/include/clang/Basic/CodeGenOptions.def
===
--- clang/include/clang/Basic/CodeGenOptions.def
+++ clang/include/clang/Basic/CodeGenOptions.def
@@ -63,7 +63,7 @@
 CODEGENOPT(DisableO0ImplyOptNone , 1, 0) ///< Don't annonate function with 
optnone at O0
 CODEGENOPT(ExperimentalStrictFloatingPoint, 1, 0) ///< Enables the new, 
experimental
   ///< strict floating point.
-CODEGENOPT(EnableNoundefAttrs, 1, 0) ///< Enable emitting `noundef` attributes 
on IR call arguments and return values
+CODEGENOPT(DisableNoundefAttrs, 1, 0) ///< Disable emitting `noundef` 
attributes on IR call arguments and return values
 CODEGENOPT(LegacyPassManager, 1, 0) ///< Use the legacy pass manager.
 CODEGENOPT(DebugPassManager, 1, 0) ///< Prints debug information for the new
///< pass manager.


Index: clang/lib/CodeGen/CGCall.cpp
===
--- clang/lib/CodeGen/CGCall.cpp
+++ clang/lib/CodeGen/CGCall.cpp
@@ -2258,7 +2258,7 @@
  getLangOpts().Sanitize.has(SanitizerKind::Return);
 
   // Determine if the return type could be partially undef
-  if (CodeGenOpts.EnableNoundefAttrs && HasStrictReturn) {
+  if (!CodeGenOpts.DisableNoundefAttrs && HasStrictReturn) {
 if (!RetTy->isVoidType() && RetAI.getKind() != ABIArgInfo::Indirect &&
 DetermineNoUndef(RetTy, getTypes(), DL, RetAI))
   RetAttrs.addAttribute(llvm::Attribute::NoUndef);
@@ -2393,7 +2393,7 @@
 
 // Decide whether the argument we're handling could be partially undef
 bool ArgNoUndef = DetermineNoUndef(ParamType, getTypes(), DL, AI);
-if (CodeGenOpts.EnableNoundefAttrs && ArgNoUndef)
+if (!CodeGenOpts.DisableNoundefAttrs && ArgNoUndef)
   Attrs.addAttribute(llvm::Attribute::NoUndef);
 
 // 'restrict' -> 'noalias' is done in EmitFunctionProlog when we
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -5260,9 +5260,9 @@
 def disable_free : Flag<["-"], "disable-free">,
   HelpText<"Disable freeing of memory on exit">,
   MarshallingInfoFlag>;
-def enable_noundef_analysis : Flag<["-"], "enable-noundef-analysis">, Group,
-  HelpText<"Enable analyzing function argument and return types

[PATCH] D108453: [Clang/Test]: Enable enable_noundef_analysis as default(2)

2021-08-20 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim created this revision.
Herald added subscribers: mstorsjo, frasercrmck, lxfind, jdoerfert, kerbowa, 
luismarques, apazos, sameer.abuasal, pengfei, s.egerton, Jim, jocewei, PkmX, 
jfb, arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, atanasyan, 
edward-jones, zzheng, jrtc27, delcypher, niosHD, sabuasal, simoncook, 
johnrusso, rbar, asb, fedor.sergeev, kbarton, jgravelle-google, sbc100, 
nhaehnle, jvesely, nemanjai, dylanmckay, jyknight, dschuff.
hyeongyukim requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, sstefan1, MaskRay, aheejin.
Herald added a reviewer: jdoerfert.
Herald added projects: clang, LLVM.

This patch contains changed test files made by D105169 
.
Autogenerated test codes are changed by `utils/update_cc_test_checks.py,` and 
non-autogenerated test codes are changed manually.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108453

Files:
  clang/test/CXX/except/except.spec/p14-ir.cpp
  clang/test/CXX/expr/expr.prim/expr.prim.lambda/blocks-irgen.mm
  clang/test/CodeGen/2006-05-19-SingleEltReturn.c
  clang/test/CodeGen/2007-06-18-SextAttrAggregate.c
  clang/test/CodeGen/2009-02-13-zerosize-union-field.c
  clang/test/CodeGen/2009-05-04-EnumInreg.c
  clang/test/CodeGen/64bit-swiftcall.c
  clang/test/CodeGen/RISCV/riscv-inline-asm.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
  clang/test/CodeGen/SystemZ/systemz-abi-vector.c
  clang/test/CodeGen/SystemZ/systemz-abi.c
  clang/test/CodeGen/SystemZ/systemz-inline-asm.c
  clang/test/CodeGen/WebAssembly/wasm-arguments.c
  clang/test/CodeGen/WebAssembly/wasm-main_argc_argv.c
  clang/test/CodeGen/X86/avx-union.c
  clang/test/CodeGen/X86/avx512fp16-complex-abi.c
  clang/test/CodeGen/X86/ms-x86-intrinsics.c
  clang/test/CodeGen/X86/strictfp_builtins.c
  clang/test/CodeGen/X86/x86-atomic-long_double.c
  clang/test/CodeGen/X86/x86-inline-asm-min-vector-width.c
  clang/test/CodeGen/X86/x86-long-double.cpp
  clang/test/CodeGen/X86/x86-soft-float.c
  clang/test/CodeGen/X86/x86-vec-i128.c
  clang/test/CodeGen/X86/x86_32-arguments-darwin.c
  clang/test/CodeGen/X86/x86_32-arguments-iamcu.c
  clang/test/CodeGen/X86/x86_32-arguments-linux.c
  clang/test/CodeGen/X86/x86_32-arguments-nommx.c
  clang/test/CodeGen/X86/x86_32-arguments-realign.c
  clang/test/CodeGen/X86/x86_32-arguments-win32.c
  clang/test/CodeGen/X86/x86_64-arguments-nacl.c
  clang/test/CodeGen/X86/x86_64-arguments-win32.c
  clang/test/CodeGen/X86/x86_64-arguments.c
  clang/test/CodeGen/X86/x86_64-longdouble.c
  clang/test/CodeGen/aapcs-align.cpp
  clang/test/CodeGen/aapcs64-align.cpp
  clang/test/CodeGen/aarch64-args.cpp
  clang/test/CodeGen/aarch64-byval-temp.c
  clang/test/CodeGen/aarch64-neon-3v.c
  clang/test/CodeGen/aarch64-neon-across.c
  clang/test/CodeGen/aarch64-neon-dot-product.c
  clang/test/CodeGen/aarch64-neon-extract.c
  clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c
  clang/test/CodeGen/aarch64-neon-fma.c
  clang/test/CodeGen/aarch64-neon-ldst-one.c
  clang/test/CodeGen/aarch64-neon-scalar-copy.c
  clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c
  clang/test/CodeGen/aarch64-neon-tbl.c
  clang/test/CodeGen/aarch64-neon-vcombine.c
  clang/test/CodeGen/aarch64-neon-vget-hilo.c
  clang/test/CodeGen/aarch64-neon-vget.c
  clang/test/CodeGen/aarch64-poly128.c
  clang/test/CodeGen/aarch64-poly64.c
  clang/test/CodeGen/aarch64-strictfp-builtins.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
  clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
  clang/test/CodeGen/aarch64-varargs.c
  clang/test/CodeGen/address-space-field1.c
  clang/test/CodeGen/address-space.c
  clang/test/CodeGen/aix-alignment.c
  clang/test/CodeGen/aix-altivec.c
  clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
  clang/test/CodeGen/aix-return.c
  clang/test/CodeGen/aix-struct-arg.c
  clang/test/CodeGen/aix-vaargs.c
  clang/test/CodeGen/alias.c
  clang/test/CodeGen/align_value.cpp
  clang/test/CodeGen/alloc-align-attr.c
  clang/test/CodeGen/alloc-size-fnptr.c
  clang/test/CodeGen/arc/arguments.c
  clang/test/CodeGen/arithmetic-fence-builtin.c
  clang/test/CodeGen/arm-aapcs-vfp.c
  clang/test/CodeGen/arm-abi-vector.c
  clang/test/CodeGen/arm-arguments.c
  clang/test/CodeGen/arm-bf16-params-returns.c
  clang/test/CodeGen/arm-byval-align.c
  clang/test/CodeGen/arm-cmse-attr.c
  clang/test/CodeGen/arm-cmse-call.c
  clang/test/CodeGen/arm-float-h

[PATCH] D108453: [Clang/Test]: Enable enable_noundef_analysis as default(2)

2021-08-20 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

This and D105169  are renewed version of the 
old patch (D82317 ).
When pushing to the main branch, I'll commit this and D105169 
 as a single commit to avoid CI failure.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108453/new/

https://reviews.llvm.org/D108453

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[PATCH] D105169: [Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default

2021-09-12 Thread Hyeongyu Kim via Phabricator via cfe-commits 
hyeongyukim added a comment.

I did some experiments to confirm the benefits of adding a noundef attribute to 
the function parameter. (test result link 
)

One of the most significant advantages of this patch is that it can improve 
performance by removing unnecessary Freeze.
To check whether the performance is improved, first, I checked how much 
performance regression occurred on SPECrate2017  
when we fixed the miscompilation problem of LoopUnswitch through the Freeze 
(D106041 .)
Then, I applied this patch to see if the unnecessary Freeze was removed and 
performance was improved.
From the experimental results, the following facts were found.

- Fixing only LoopUnswitch(D106041 ) reduces 
runtime performance and increases object size.
- Freeze added that fixing the LoopUnswitch interferes with other 
optimizations, increasing the number of instructions. (There is still a problem 
with LoopUnswitch due to these performance problems)

- Applying this patch improves runtime and makes the object size almost the 
same as the LLVM trunk.
- Knowing that Function arguments are not noundef/poison, some freezes were 
removed, and performance and binary size have been improved.

The second sheet compares the performance of the LLVM trunk and this patch, but 
there is no noticeable change.
In the last sheet, about 2,000 LLVM test-suites were compiled, and the object 
size was compared. In most cases, the object size was improved.

I think many advantages can be obtained by applying this patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105169/new/

https://reviews.llvm.org/D105169

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