[PATCH] D17378: Add additional Hi/Lo registers to Clang MipsTargetInfoBase
hvarga created this revision. hvarga added reviewers: hfinkel, atrick, chandlerc. hvarga added subscribers: cfe-commits, petarj. This patch fixes bug https://dmz-portal.mips.com/bugz/show_bug.cgi?id=2300 by adding additional (missing) Hi/Lo registers to the Clang `MipsTargetInfoBase` class. http://reviews.llvm.org/D17378 Files: lib/Basic/Targets.cpp test/CodeGen/mips-inline-asm.c Index: test/CodeGen/mips-inline-asm.c === --- test/CodeGen/mips-inline-asm.c +++ test/CodeGen/mips-inline-asm.c @@ -17,3 +17,15 @@ asm("lw $1, %0" :: "R"(data)); // CHECK: call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* @data) } + +int additionalClobberedRegisters () { + int temp0; + asm volatile( +"mfhi %[temp0], $ac1 \n\t" + : [temp0]"=&r"(temp0) + : + : "memory", "t0", "t1", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi", "$ac3lo" + ); + return 0; + // CHECK: call i32 asm sideeffect "mfhi $0, $$ac1 \0A\09", "=&r,~{memory},~{$8},~{$9},~{$ac1hi},~{$ac1lo},~{$ac2hi},~{$ac2lo},~{$ac3hi},~{$ac3lo},~{$1}" +} Index: lib/Basic/Targets.cpp === --- lib/Basic/Targets.cpp +++ lib/Basic/Targets.cpp @@ -6678,7 +6678,8 @@ "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", // Hi/lo and condition register names "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", - "$fcc5","$fcc6","$fcc7", + "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", + "$ac3hi","$ac3lo", // MSA register names "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", Index: test/CodeGen/mips-inline-asm.c === --- test/CodeGen/mips-inline-asm.c +++ test/CodeGen/mips-inline-asm.c @@ -17,3 +17,15 @@ asm("lw $1, %0" :: "R"(data)); // CHECK: call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* @data) } + +int additionalClobberedRegisters () { + int temp0; + asm volatile( +"mfhi %[temp0], $ac1 \n\t" + : [temp0]"=&r"(temp0) + : + : "memory", "t0", "t1", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi", "$ac3lo" + ); + return 0; + // CHECK: call i32 asm sideeffect "mfhi $0, $$ac1 \0A\09", "=&r,~{memory},~{$8},~{$9},~{$ac1hi},~{$ac1lo},~{$ac2hi},~{$ac2lo},~{$ac3hi},~{$ac3lo},~{$1}" +} Index: lib/Basic/Targets.cpp === --- lib/Basic/Targets.cpp +++ lib/Basic/Targets.cpp @@ -6678,7 +6678,8 @@ "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", // Hi/lo and condition register names "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", - "$fcc5","$fcc6","$fcc7", + "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", + "$ac3hi","$ac3lo", // MSA register names "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D17378: Add additional Hi/Lo registers to Clang MipsTargetInfoBase
hvarga added a comment. I'm not sure if I added all of the necessary reviewers or even the correct ones. So please feel free to correct this if it's wrong. http://reviews.llvm.org/D17378 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D17378: Add additional Hi/Lo registers to Clang MipsTargetInfoBase
hvarga added a comment. Are there any thoughts about this patch? http://reviews.llvm.org/D17378 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D17378: Add additional Hi/Lo registers to Clang MipsTargetInfoBase
This revision was automatically updated to reflect the committed changes. Closed by commit rL264727: Add additional Hi/Lo registers to Clang MipsTargetInfoBase (authored by hvarga). Changed prior to commit: http://reviews.llvm.org/D17378?vs=48309&id=51893#toc Repository: rL LLVM http://reviews.llvm.org/D17378 Files: cfe/trunk/lib/Basic/Targets.cpp cfe/trunk/test/CodeGen/mips-inline-asm.c Index: cfe/trunk/test/CodeGen/mips-inline-asm.c === --- cfe/trunk/test/CodeGen/mips-inline-asm.c +++ cfe/trunk/test/CodeGen/mips-inline-asm.c @@ -17,3 +17,15 @@ asm("lw $1, %0" :: "R"(data)); // CHECK: call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* @data) } + +int additionalClobberedRegisters () { + int temp0; + asm volatile( +"mfhi %[temp0], $ac1 \n\t" + : [temp0]"=&r"(temp0) + : + : "memory", "t0", "t1", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi", "$ac3lo" + ); + return 0; + // CHECK: call i32 asm sideeffect "mfhi $0, $$ac1 \0A\09", "=&r,~{memory},~{$8},~{$9},~{$ac1hi},~{$ac1lo},~{$ac2hi},~{$ac2lo},~{$ac3hi},~{$ac3lo},~{$1}" +} Index: cfe/trunk/lib/Basic/Targets.cpp === --- cfe/trunk/lib/Basic/Targets.cpp +++ cfe/trunk/lib/Basic/Targets.cpp @@ -6899,7 +6899,8 @@ "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", // Hi/lo and condition register names "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", - "$fcc5","$fcc6","$fcc7", + "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", + "$ac3hi","$ac3lo", // MSA register names "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", Index: cfe/trunk/test/CodeGen/mips-inline-asm.c === --- cfe/trunk/test/CodeGen/mips-inline-asm.c +++ cfe/trunk/test/CodeGen/mips-inline-asm.c @@ -17,3 +17,15 @@ asm("lw $1, %0" :: "R"(data)); // CHECK: call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* @data) } + +int additionalClobberedRegisters () { + int temp0; + asm volatile( +"mfhi %[temp0], $ac1 \n\t" + : [temp0]"=&r"(temp0) + : + : "memory", "t0", "t1", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi", "$ac3lo" + ); + return 0; + // CHECK: call i32 asm sideeffect "mfhi $0, $$ac1 \0A\09", "=&r,~{memory},~{$8},~{$9},~{$ac1hi},~{$ac1lo},~{$ac2hi},~{$ac2lo},~{$ac3hi},~{$ac3lo},~{$1}" +} Index: cfe/trunk/lib/Basic/Targets.cpp === --- cfe/trunk/lib/Basic/Targets.cpp +++ cfe/trunk/lib/Basic/Targets.cpp @@ -6899,7 +6899,8 @@ "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", // Hi/lo and condition register names "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", - "$fcc5","$fcc6","$fcc7", + "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", + "$ac3hi","$ac3lo", // MSA register names "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r264727 - Add additional Hi/Lo registers to Clang MipsTargetInfoBase
Author: hvarga Date: Tue Mar 29 07:46:16 2016 New Revision: 264727 URL: http://llvm.org/viewvc/llvm-project?rev=264727&view=rev Log: Add additional Hi/Lo registers to Clang MipsTargetInfoBase Differential Revision: http://reviews.llvm.org/D17378 Modified: cfe/trunk/lib/Basic/Targets.cpp cfe/trunk/test/CodeGen/mips-inline-asm.c Modified: cfe/trunk/lib/Basic/Targets.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=264727&r1=264726&r2=264727&view=diff == --- cfe/trunk/lib/Basic/Targets.cpp (original) +++ cfe/trunk/lib/Basic/Targets.cpp Tue Mar 29 07:46:16 2016 @@ -6899,7 +6899,8 @@ public: "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", // Hi/lo and condition register names "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", - "$fcc5","$fcc6","$fcc7", + "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", + "$ac3hi","$ac3lo", // MSA register names "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", Modified: cfe/trunk/test/CodeGen/mips-inline-asm.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-inline-asm.c?rev=264727&r1=264726&r2=264727&view=diff == --- cfe/trunk/test/CodeGen/mips-inline-asm.c (original) +++ cfe/trunk/test/CodeGen/mips-inline-asm.c Tue Mar 29 07:46:16 2016 @@ -17,3 +17,15 @@ void R () { asm("lw $1, %0" :: "R"(data)); // CHECK: call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* @data) } + +int additionalClobberedRegisters () { + int temp0; + asm volatile( +"mfhi %[temp0], $ac1 \n\t" + : [temp0]"=&r"(temp0) + : + : "memory", "t0", "t1", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi", "$ac3lo" + ); + return 0; + // CHECK: call i32 asm sideeffect "mfhi $0, $$ac1 \0A\09", "=&r,~{memory},~{$8},~{$9},~{$ac1hi},~{$ac1lo},~{$ac2hi},~{$ac2lo},~{$ac3hi},~{$ac3lo},~{$1}" +} ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits