Re: [PATCH] D21959: [X86] Add xgetbv xsetbv intrinsics
guyblank added a comment. Sorry about that, forgot that i changed the ms_intrin test. about the failure, I think that xsaveintrin.h is not being included because it requires the xsave feature - which should be on if the target supports it. do you know what in which target the failure occurred? also, can you direct me to the source code for the failure? thanks Repository: rL LLVM https://reviews.llvm.org/D21959 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r279042 - test commit
Author: guyblank
Date: Thu Aug 18 03:44:33 2016
New Revision: 279042
URL: http://llvm.org/viewvc/llvm-project?rev=279042&view=rev
Log:
test commit
Modified:
cfe/trunk/lib/Basic/Targets.cpp
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=279042&r1=279041&r2=279042&view=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Thu Aug 18 03:44:33 2016
@@ -806,7 +806,7 @@ public:
this->SizeType = TargetInfo::UnsignedInt;
this->PtrDiffType = TargetInfo::SignedInt;
this->IntPtrType = TargetInfo::SignedInt;
-// RegParmMax is inherited from the underlying architecture
+// RegParmMax is inherited from the underlying architecture.
this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
if (Triple.getArch() == llvm::Triple::arm) {
// Handled in ARM's setABI().
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Re: [PATCH] D21959: [X86] Add xgetbv xsetbv intrinsics
guyblank added a comment. Still, __XSAVE__ should have been defined when compiling for a target that supports the feature. But anyway, the xsaveintrin.h is quite small so always including it shouldn't be an issue. Are you ok with me removing the #if just for this header file, or would you like to wait for Nico? Repository: rL LLVM https://reviews.llvm.org/D21959 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D21959: [X86] Add xgetbv xsetbv intrinsics
guyblank added a comment. removing the MSC_VER check will not be enough, the feature guards from the intrinsic and the builtin need to be removed to make it work. not sure if this is the right way to go, any thoughts on this? Repository: rL LLVM https://reviews.llvm.org/D21959 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D21959: [X86] Add xgetbv xsetbv intrinsics
guyblank added a comment.
the include is because i added calls to the intrinsics themselves
in the test, no just the builtins.
Comment at: lib/Headers/intrin.h:905
@@ -906,9 +904,3 @@
}
-static __inline__ unsigned __int64 __cdecl __DEFAULT_FN_ATTRS
-_xgetbv(unsigned int __xcr_no) {
- unsigned int __eax, __edx;
- __asm__ ("xgetbv" : "=a" (__eax), "=d" (__edx) : "c" (__xcr_no));
- return ((unsigned __int64)__edx << 32) | __eax;
-}
static __inline__ void __DEFAULT_FN_ATTRS
__halt(void) {
delena wrote:
> I'm not sure that we can move it from one file to another. And what was wrong
> with current implementation.
it can't be left here since it will conflict with non-windows implementation.
my impression was that it is generally better to use "regular" lowering flow,
over using inline asm.
https://reviews.llvm.org/D21959
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Re: [PATCH] D21959: [X86] Add xgetbv xsetbv intrinsics
guyblank updated this revision to Diff 65676.
guyblank marked an inline comment as done.
https://reviews.llvm.org/D21959
Files:
include/clang/Basic/BuiltinsX86.def
lib/CodeGen/CGBuiltin.cpp
lib/Headers/intrin.h
lib/Headers/xsaveintrin.h
test/CodeGen/builtins-x86.c
test/CodeGen/x86_32-xsave.c
test/CodeGen/x86_64-xsave.c
test/Headers/ms-intrin.cpp
Index: test/Headers/ms-intrin.cpp
===
--- test/Headers/ms-intrin.cpp
+++ test/Headers/ms-intrin.cpp
@@ -50,7 +50,6 @@
int info[4];
__cpuid(info, 0);
__cpuidex(info, 0, 0);
- _xgetbv(0);
__halt();
__readmsr(0);
Index: test/CodeGen/x86_64-xsave.c
===
--- test/CodeGen/x86_64-xsave.c
+++ test/CodeGen/x86_64-xsave.c
@@ -1,6 +1,9 @@
// RUN: %clang_cc1 %s -DTEST_XSAVE -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSAVE
// RUN: %clang_cc1 %s -DTEST_XSAVE -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -fno-signed-char -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSAVE
+// RUN: %clang_cc1 %s -DTEST_XGETBV -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XGETBV
+// RUN: %clang_cc1 %s -DTEST_XSETBV -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -fno-signed-char -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSETBV
+
// RUN: %clang_cc1 %s -DTEST_XSAVEOPT -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -target-feature +xsaveopt -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSAVEOPT
// RUN: %clang_cc1 %s -DTEST_XSAVEOPT -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -target-feature +xsaveopt -fno-signed-char -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSAVEOPT
@@ -10,8 +13,14 @@
// RUN: %clang_cc1 %s -DTEST_XSAVES -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -target-feature +xsaves -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSAVES
// RUN: %clang_cc1 %s -DTEST_XSAVES -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -target-feature +xsaves -fno-signed-char -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSAVES
+// Don't include mm_malloc.h, it's system specific.
+#define __MM_MALLOC_H
+#include
+
+
void test() {
unsigned long long tmp_ULLi;
+ unsigned int tmp_Ui;
void* tmp_vp;
#ifdef TEST_XSAVE
@@ -46,6 +55,18 @@
// XSAVE: [[low32_4:%[0-9a-zA-z]+]] = trunc i64 [[tmp_ULLi_4]] to i32
// XSAVE: call void @llvm.x86.xrstor64(i8* [[tmp_vp_4]], i32 [[high32_4]], i32 [[low32_4]])
(void)__builtin_ia32_xrstor64(tmp_vp, tmp_ULLi);
+
+// XSAVE: call void @llvm.x86.xsave
+ (void)_xsave(tmp_vp, tmp_ULLi);
+
+// XSAVE: call void @llvm.x86.xsave64
+ (void)_xsave64(tmp_vp, tmp_ULLi);
+
+// XSAVE: call void @llvm.x86.xrstor
+ (void)_xrstor(tmp_vp, tmp_ULLi);
+
+// XSAVE: call void @llvm.x86.xrstor64
+ (void)_xrstor64(tmp_vp, tmp_ULLi);
#endif
#ifdef TEST_XSAVEOPT
@@ -64,6 +85,12 @@
// XSAVEOPT: [[low32_2:%[0-9a-zA-z]+]] = trunc i64 [[tmp_ULLi_2]] to i32
// XSAVEOPT: call void @llvm.x86.xsaveopt64(i8* [[tmp_vp_2]], i32 [[high32_2]], i32 [[low32_2]])
(void)__builtin_ia32_xsaveopt64(tmp_vp, tmp_ULLi);
+
+// XSAVEOPT: call void @llvm.x86.xsaveopt
+ (void)_xsaveopt(tmp_vp, tmp_ULLi);
+
+// XSAVEOPT: call void @llvm.x86.xsaveopt64
+ (void)_xsaveopt64(tmp_vp, tmp_ULLi);
#endif
#ifdef TEST_XSAVEC
@@ -82,6 +109,12 @@
// XSAVEC: [[low32_2:%[0-9a-zA-z]+]] = trunc i64 [[tmp_ULLi_2]] to i32
// XSAVEC: call void @llvm.x86.xsavec64(i8* [[tmp_vp_2]], i32 [[high32_2]], i32 [[low32_2]])
(void)__builtin_ia32_xsavec64(tmp_vp, tmp_ULLi);
+
+// XSAVEC: call void @llvm.x86.xsavec
+ (void)_xsavec(tmp_vp, tmp_ULLi);
+
+// XSAVEC: call void @llvm.x86.xsavec64
+ (void)_xsavec64(tmp_vp, tmp_ULLi);
#endif
#ifdef TEST_XSAVES
@@ -116,5 +149,39 @@
// XSAVES: [[low32_4:%[0-9a-zA-z]+]] = trunc i64 [[tmp_ULLi_4]] to i32
// XSAVES: call void @llvm.x86.xrstors64(i8* [[tmp_vp_4]], i32 [[high32_4]], i32 [[low32_4]])
(void)__builtin_ia32_xrstors64(tmp_vp, tmp_ULLi);
+
+// XSAVES: call void @llvm.x86.xsaves
+ (void)_xsaves(tmp_vp, tmp_ULLi);
+
+// XSAVES: call void @llvm.x86.xsaves64
+ (void)_xsaves64(tmp_vp, tmp_ULLi);
+
+// XSAVES: call void @llvm.x86.xrstors
+ (void)_xrstors(tmp_vp, tmp_ULLi);
+
+// XSAVES: call void @llvm.x86.xrstors64
+ (void)_xrstors64(tmp_vp, tmp_ULLi);
+#endif
+
+#ifdef TEST_XGETBV
+// XGETBV: [[tmp_Ui:%[0-9a-zA-z]+]] = load i32, i32* %tmp_Ui, align 4
+// XGETBV: call i64 @llvm.x86.xgetbv(i32 [[tmp_Ui]])
+ tmp_ULLi = __builtin_ia32_xgetbv(tmp_Ui);
+
+// XGETBV: call i64 @llvm.x86.xgetbv
+ tmp_ULLi = _xgetbv(tmp_Ui);
+#endif
+
+#ifdef TEST_XSETBV
+// XSETBV: [[tmp_Ui:%[0-9a-zA-z]+]] = load i32, i32* %tmp_Ui, align 4
+// XSETBV: [[tmp_ULLi_3:%[0-9a-zA-z]+]] = load i64, i64* %tmp_ULLi, align 8
+// XSET
Re: [PATCH] D21959: [X86] Add xgetbv xsetbv intrinsics
guyblank added a comment. ping https://reviews.llvm.org/D21959 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D21959: [X86] Add xgetbv xsetbv intrinsics
guyblank added a comment. If there aren't any further objections, I'd like go ahead with the commit. https://reviews.llvm.org/D21959 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D21959: [X86] Add xgetbv xsetbv intrinsics
guyblank created this revision.
guyblank added reviewers: aaboud, delena, craig.topper, AsafBadouh,
m_zuckerman, igorb.
guyblank added a subscriber: cfe-commits.
[X86] Add xgetbv xsetbv intrinsics
http://reviews.llvm.org/D21959
Files:
include/clang/Basic/BuiltinsX86.def
lib/CodeGen/CGBuiltin.cpp
lib/Headers/intrin.h
lib/Headers/xsaveintrin.h
test/CodeGen/builtins-x86.c
test/CodeGen/x86_32-xsave.c
test/CodeGen/x86_64-xsave.c
Index: test/CodeGen/x86_64-xsave.c
===
--- test/CodeGen/x86_64-xsave.c
+++ test/CodeGen/x86_64-xsave.c
@@ -1,6 +1,9 @@
// RUN: %clang_cc1 %s -DTEST_XSAVE -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSAVE
// RUN: %clang_cc1 %s -DTEST_XSAVE -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -fno-signed-char -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSAVE
+// RUN: %clang_cc1 %s -DTEST_XGETBV -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XGETBV
+// RUN: %clang_cc1 %s -DTEST_XSETBV -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -fno-signed-char -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSETBV
+
// RUN: %clang_cc1 %s -DTEST_XSAVEOPT -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -target-feature +xsaveopt -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSAVEOPT
// RUN: %clang_cc1 %s -DTEST_XSAVEOPT -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -target-feature +xsaveopt -fno-signed-char -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSAVEOPT
@@ -10,8 +13,14 @@
// RUN: %clang_cc1 %s -DTEST_XSAVES -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -target-feature +xsaves -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSAVES
// RUN: %clang_cc1 %s -DTEST_XSAVES -O0 -triple=x86_64-unknown-unknown -target-feature +xsave -target-feature +xsaves -fno-signed-char -emit-llvm -o - -Werror | FileCheck %s --check-prefix=XSAVES
+// Don't include mm_malloc.h, it's system specific.
+#define __MM_MALLOC_H
+#include
+
+
void test() {
unsigned long long tmp_ULLi;
+ unsigned int tmp_Ui;
void* tmp_vp;
#ifdef TEST_XSAVE
@@ -46,6 +55,18 @@
// XSAVE: [[low32_4:%[0-9a-zA-z]+]] = trunc i64 [[tmp_ULLi_4]] to i32
// XSAVE: call void @llvm.x86.xrstor64(i8* [[tmp_vp_4]], i32 [[high32_4]], i32 [[low32_4]])
(void)__builtin_ia32_xrstor64(tmp_vp, tmp_ULLi);
+
+// XSAVE: call void @llvm.x86.xsave
+ (void)_xsave(tmp_vp, tmp_ULLi);
+
+// XSAVE: call void @llvm.x86.xsave64
+ (void)_xsave64(tmp_vp, tmp_ULLi);
+
+// XSAVE: call void @llvm.x86.xrstor
+ (void)_xrstor(tmp_vp, tmp_ULLi);
+
+// XSAVE: call void @llvm.x86.xrstor64
+ (void)_xrstor64(tmp_vp, tmp_ULLi);
#endif
#ifdef TEST_XSAVEOPT
@@ -64,6 +85,12 @@
// XSAVEOPT: [[low32_2:%[0-9a-zA-z]+]] = trunc i64 [[tmp_ULLi_2]] to i32
// XSAVEOPT: call void @llvm.x86.xsaveopt64(i8* [[tmp_vp_2]], i32 [[high32_2]], i32 [[low32_2]])
(void)__builtin_ia32_xsaveopt64(tmp_vp, tmp_ULLi);
+
+// XSAVEOPT: call void @llvm.x86.xsaveopt
+ (void)_xsaveopt(tmp_vp, tmp_ULLi);
+
+// XSAVEOPT: call void @llvm.x86.xsaveopt64
+ (void)_xsaveopt64(tmp_vp, tmp_ULLi);
#endif
#ifdef TEST_XSAVEC
@@ -82,6 +109,12 @@
// XSAVEC: [[low32_2:%[0-9a-zA-z]+]] = trunc i64 [[tmp_ULLi_2]] to i32
// XSAVEC: call void @llvm.x86.xsavec64(i8* [[tmp_vp_2]], i32 [[high32_2]], i32 [[low32_2]])
(void)__builtin_ia32_xsavec64(tmp_vp, tmp_ULLi);
+
+// XSAVEC: call void @llvm.x86.xsavec
+ (void)_xsavec(tmp_vp, tmp_ULLi);
+
+// XSAVEC: call void @llvm.x86.xsavec64
+ (void)_xsavec64(tmp_vp, tmp_ULLi);
#endif
#ifdef TEST_XSAVES
@@ -116,5 +149,39 @@
// XSAVES: [[low32_4:%[0-9a-zA-z]+]] = trunc i64 [[tmp_ULLi_4]] to i32
// XSAVES: call void @llvm.x86.xrstors64(i8* [[tmp_vp_4]], i32 [[high32_4]], i32 [[low32_4]])
(void)__builtin_ia32_xrstors64(tmp_vp, tmp_ULLi);
+
+// XSAVES: call void @llvm.x86.xsaves
+ (void)_xsaves(tmp_vp, tmp_ULLi);
+
+// XSAVES: call void @llvm.x86.xsaves64
+ (void)_xsaves64(tmp_vp, tmp_ULLi);
+
+// XSAVES: call void @llvm.x86.xrstors
+ (void)_xrstors(tmp_vp, tmp_ULLi);
+
+// XSAVES: call void @llvm.x86.xrstors64
+ (void)_xrstors64(tmp_vp, tmp_ULLi);
+#endif
+
+#ifdef TEST_XGETBV
+// XGETBV: [[tmp_Ui:%[0-9a-zA-z]+]] = load i32, i32* %tmp_Ui, align 4
+// XGETBV: call i64 @llvm.x86.xgetbv(i32 [[tmp_Ui]])
+ tmp_ULLi = __builtin_ia32_xgetbv(tmp_Ui);
+
+// XGETBV: call i64 @llvm.x86.xgetbv
+ tmp_ULLi = _xgetbv(tmp_Ui);
+#endif
+
+#ifdef TEST_XSETBV
+// XSETBV: [[tmp_Ui:%[0-9a-zA-z]+]] = load i32, i32* %tmp_Ui, align 4
+// XSETBV: [[tmp_ULLi_3:%[0-9a-zA-z]+]] = load i64, i64* %tmp_ULLi, align 8
+// XSETBV: [[high64_3:%[0-9a-zA-z]+]] = lshr i64 [[tmp_ULLi_3]], 32
+// XSETBV: [[high32_3:%[0-9a-zA-z]+]] = trunc i64 [[high64_3]] to i32
+// XSETBV: [[low32_3:%[0-9a-zA-z]+]] = trunc i64 [[tmp_ULLi_3]] to i32
+// XSE
[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// Bundle loads and stores that operate on consecutive memory locations to take
+// the advantage of hardware load/store bonding.
+//
+//===--===//
+
+#include "RISCV.h"
+#include "RISCVTargetMachine.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-load-store-opt"
+#define RISCV_LOAD_STORE_OPT_NAME "RISCV Load / Store Optimizer"
+namespace {
+
+struct RISCVLoadStoreOpt : public MachineFunctionPass {
+ static char ID;
+ bool runOnMachineFunction(MachineFunction &Fn) override;
+
+ RISCVLoadStoreOpt() : MachineFunctionPass(ID) {}
+
+ MachineFunctionProperties getRequiredProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::NoVRegs);
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+AU.addRequired();
+MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
+ StringRef getPassName() const override { return RISCV_LOAD_STORE_OPT_NAME; }
+
+ // Find and pair load/store instructions.
+ bool tryToPairLdStInst(MachineBasicBlock::iterator &MBBI);
+
+ // Convert load/store pairs to single instructions.
+ bool tryConvertToLdStPair(MachineBasicBlock::iterator First,
+MachineBasicBlock::iterator Second);
+
+ // Scan the instructions looking for a load/store that can be combined
+ // with the current instruction into a load/store pair.
+ // Return the matching instruction if one is found, else MBB->end().
+ MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
+ bool &MergeForward);
+
+ MachineBasicBlock::iterator
+ mergePairedInsns(MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator Paired, bool MergeForward);
+
+private:
+ AliasAnalysis *AA;
+ MachineRegisterInfo *MRI;
+ const RISCVInstrInfo *TII;
+ const RISCVRegisterInfo *TRI;
+ LiveRegUnits ModifiedRegUnits, UsedRegUnits;
+ bool UseLoadStorePair = false;
+};
+} // end anonymous namespace
+
+char RISCVLoadStoreOpt::ID = 0;
+INITIALIZE_PASS(RISCVLoadStoreOpt, DEBUG_TYPE, RISCV_LOAD_STORE_OPT_NAME,
false,
+false)
+
+bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+ if (skipFunction(Fn.getFunction()))
+return false;
+ const RISCVSubtarget &Subtarget = Fn.getSubtarget();
+
+ if (!Subtarget.useLoadStorePairs())
+return false;
+
+ bool MadeChange = false;
+ TII = Subtarget.getInstrInfo();
+ TRI = Subtarget.getRegisterInfo();
+ MRI = &Fn.getRegInfo();
+ AA = &getAnalysis().getAAResults();
+ ModifiedRegUnits.init(*TRI);
+ UsedRegUnits.init(*TRI);
+ UseLoadStorePair = Subtarget.useLoadStorePairs();
+
+ for (MachineBasicBlock &MBB : Fn) {
+LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
+
+for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+ MBBI != E;) {
+ if (TII->isPairableLdStInstOpc(MBBI->getOpcode()) &&
+ tryToPairLdStInst(MBBI))
+MadeChange = true;
+ else
+++MBBI;
+}
+ }
+ return MadeChange;
+}
+
+// Find loads and stores that can be merged into a single load or store pair
+// instruction.
+bool RISCVLoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
+ MachineInstr &MI = *MBBI;
+ MachineBasicBlock::iterator E = MI.getParent()->end();
+
+ if (!TII->isLdStSafeToPair(MI, TRI))
+return false;
+
+ // Look ahead for a pairable instruction.
+ bool MergeForward;
+ MachineBasicBlock::iterator Paired = findMatchingInsn(MBBI, MergeForward);
+ if (Paired != E) {
+MBBI = mergePairedInsns(MBBI, Paired, MergeForward);
+return true;
+ }
+ return false;
+}
+
+bool RISCVLoadStoreOpt::tryConvertToLdStPair(
+MachineBasicBlock::iterator First, MachineBasicBlock::iterator Second) {
+ if (!UseLoadStorePair)
+return false;
+
+ unsigned PairOpc;
+ switch (First->getOpcode()) {
+ default:
+return false;
+ case RISCV::SW:
+PairOpc = RISCV::SWP;
+break;
+ case RISCV::LW:
+PairOpc = RISCV::LWP;
+break;
+ case RISCV::SD:
+PairOpc = RISCV::SDP;
+break;
+ case RISCV::LD:
+PairOpc = RISCV::LDP;
+break;
+ }
+
+ MachineFunction *MF = First->getMF();
+ const MachineMemOperand *MMO = *First->memoperands_begin();
+ Align MMOAlign = MMO->getAlign();
+ if (const PseudoSourceValue *Sour
[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// Bundle loads and stores that operate on consecutive memory locations to take
+// the advantage of hardware load/store bonding.
+//
+//===--===//
+
+#include "RISCV.h"
+#include "RISCVTargetMachine.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-load-store-opt"
+#define RISCV_LOAD_STORE_OPT_NAME "RISCV Load / Store Optimizer"
+namespace {
+
+struct RISCVLoadStoreOpt : public MachineFunctionPass {
+ static char ID;
+ bool runOnMachineFunction(MachineFunction &Fn) override;
+
+ RISCVLoadStoreOpt() : MachineFunctionPass(ID) {}
+
+ MachineFunctionProperties getRequiredProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::NoVRegs);
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+AU.addRequired();
+MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
+ StringRef getPassName() const override { return RISCV_LOAD_STORE_OPT_NAME; }
+
+ // Find and pair load/store instructions.
+ bool tryToPairLdStInst(MachineBasicBlock::iterator &MBBI);
+
+ // Convert load/store pairs to single instructions.
+ bool tryConvertToLdStPair(MachineBasicBlock::iterator First,
+MachineBasicBlock::iterator Second);
+
+ // Scan the instructions looking for a load/store that can be combined
+ // with the current instruction into a load/store pair.
+ // Return the matching instruction if one is found, else MBB->end().
+ MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
+ bool &MergeForward);
+
+ MachineBasicBlock::iterator
+ mergePairedInsns(MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator Paired, bool MergeForward);
+
+private:
+ AliasAnalysis *AA;
+ MachineRegisterInfo *MRI;
+ const RISCVInstrInfo *TII;
+ const RISCVRegisterInfo *TRI;
+ LiveRegUnits ModifiedRegUnits, UsedRegUnits;
+ bool UseLoadStorePair = false;
+};
+} // end anonymous namespace
+
+char RISCVLoadStoreOpt::ID = 0;
+INITIALIZE_PASS(RISCVLoadStoreOpt, DEBUG_TYPE, RISCV_LOAD_STORE_OPT_NAME,
false,
+false)
+
+bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+ if (skipFunction(Fn.getFunction()))
+return false;
+ const RISCVSubtarget &Subtarget = Fn.getSubtarget();
+
+ if (!Subtarget.useLoadStorePairs())
+return false;
+
+ bool MadeChange = false;
+ TII = Subtarget.getInstrInfo();
+ TRI = Subtarget.getRegisterInfo();
+ MRI = &Fn.getRegInfo();
+ AA = &getAnalysis().getAAResults();
+ ModifiedRegUnits.init(*TRI);
+ UsedRegUnits.init(*TRI);
+ UseLoadStorePair = Subtarget.useLoadStorePairs();
+
+ for (MachineBasicBlock &MBB : Fn) {
+LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
+
+for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+ MBBI != E;) {
+ if (TII->isPairableLdStInstOpc(MBBI->getOpcode()) &&
+ tryToPairLdStInst(MBBI))
+MadeChange = true;
+ else
+++MBBI;
+}
+ }
+ return MadeChange;
+}
+
+// Find loads and stores that can be merged into a single load or store pair
+// instruction.
+bool RISCVLoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
+ MachineInstr &MI = *MBBI;
+ MachineBasicBlock::iterator E = MI.getParent()->end();
+
+ if (!TII->isLdStSafeToPair(MI, TRI))
+return false;
+
+ // Look ahead for a pairable instruction.
+ bool MergeForward;
+ MachineBasicBlock::iterator Paired = findMatchingInsn(MBBI, MergeForward);
+ if (Paired != E) {
+MBBI = mergePairedInsns(MBBI, Paired, MergeForward);
+return true;
+ }
+ return false;
+}
+
+bool RISCVLoadStoreOpt::tryConvertToLdStPair(
+MachineBasicBlock::iterator First, MachineBasicBlock::iterator Second) {
+ if (!UseLoadStorePair)
+return false;
+
+ unsigned PairOpc;
+ switch (First->getOpcode()) {
+ default:
+return false;
+ case RISCV::SW:
+PairOpc = RISCV::SWP;
+break;
+ case RISCV::LW:
+PairOpc = RISCV::LWP;
+break;
+ case RISCV::SD:
+PairOpc = RISCV::SDP;
+break;
+ case RISCV::LD:
+PairOpc = RISCV::LDP;
+break;
+ }
+
+ MachineFunction *MF = First->getMF();
+ const MachineMemOperand *MMO = *First->memoperands_begin();
+ Align MMOAlign = MMO->getAlign();
+ if (const PseudoSourceValue *Sour
[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// Bundle loads and stores that operate on consecutive memory locations to take
+// the advantage of hardware load/store bonding.
+//
+//===--===//
+
+#include "RISCV.h"
+#include "RISCVTargetMachine.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-load-store-opt"
+#define RISCV_LOAD_STORE_OPT_NAME "RISCV Load / Store Optimizer"
+namespace {
+
+struct RISCVLoadStoreOpt : public MachineFunctionPass {
+ static char ID;
+ bool runOnMachineFunction(MachineFunction &Fn) override;
+
+ RISCVLoadStoreOpt() : MachineFunctionPass(ID) {}
+
+ MachineFunctionProperties getRequiredProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::NoVRegs);
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+AU.addRequired();
+MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
+ StringRef getPassName() const override { return RISCV_LOAD_STORE_OPT_NAME; }
+
+ // Find and pair load/store instructions.
+ bool tryToPairLdStInst(MachineBasicBlock::iterator &MBBI);
+
+ // Convert load/store pairs to single instructions.
+ bool tryConvertToLdStPair(MachineBasicBlock::iterator First,
+MachineBasicBlock::iterator Second);
+
+ // Scan the instructions looking for a load/store that can be combined
+ // with the current instruction into a load/store pair.
+ // Return the matching instruction if one is found, else MBB->end().
+ MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
+ bool &MergeForward);
+
+ MachineBasicBlock::iterator
+ mergePairedInsns(MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator Paired, bool MergeForward);
+
+private:
+ AliasAnalysis *AA;
+ MachineRegisterInfo *MRI;
+ const RISCVInstrInfo *TII;
+ const RISCVRegisterInfo *TRI;
+ LiveRegUnits ModifiedRegUnits, UsedRegUnits;
+ bool UseLoadStorePair = false;
+};
+} // end anonymous namespace
+
+char RISCVLoadStoreOpt::ID = 0;
+INITIALIZE_PASS(RISCVLoadStoreOpt, DEBUG_TYPE, RISCV_LOAD_STORE_OPT_NAME,
false,
+false)
+
+bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+ if (skipFunction(Fn.getFunction()))
+return false;
+ const RISCVSubtarget &Subtarget = Fn.getSubtarget();
+
+ if (!Subtarget.useLoadStorePairs())
+return false;
+
+ bool MadeChange = false;
+ TII = Subtarget.getInstrInfo();
+ TRI = Subtarget.getRegisterInfo();
+ MRI = &Fn.getRegInfo();
+ AA = &getAnalysis().getAAResults();
+ ModifiedRegUnits.init(*TRI);
+ UsedRegUnits.init(*TRI);
+ UseLoadStorePair = Subtarget.useLoadStorePairs();
+
+ for (MachineBasicBlock &MBB : Fn) {
+LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
+
+for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
+ MBBI != E;) {
+ if (TII->isPairableLdStInstOpc(MBBI->getOpcode()) &&
+ tryToPairLdStInst(MBBI))
+MadeChange = true;
+ else
+++MBBI;
+}
+ }
+ return MadeChange;
+}
+
+// Find loads and stores that can be merged into a single load or store pair
+// instruction.
+bool RISCVLoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
+ MachineInstr &MI = *MBBI;
+ MachineBasicBlock::iterator E = MI.getParent()->end();
+
+ if (!TII->isLdStSafeToPair(MI, TRI))
+return false;
+
+ // Look ahead for a pairable instruction.
+ bool MergeForward;
+ MachineBasicBlock::iterator Paired = findMatchingInsn(MBBI, MergeForward);
+ if (Paired != E) {
+MBBI = mergePairedInsns(MBBI, Paired, MergeForward);
+return true;
+ }
+ return false;
+}
+
+bool RISCVLoadStoreOpt::tryConvertToLdStPair(
+MachineBasicBlock::iterator First, MachineBasicBlock::iterator Second) {
+ if (!UseLoadStorePair)
+return false;
+
+ unsigned PairOpc;
+ switch (First->getOpcode()) {
+ default:
+return false;
+ case RISCV::SW:
+PairOpc = RISCV::SWP;
+break;
+ case RISCV::LW:
+PairOpc = RISCV::LWP;
+break;
+ case RISCV::SD:
+PairOpc = RISCV::SDP;
+break;
+ case RISCV::LD:
+PairOpc = RISCV::LDP;
+break;
+ }
+
+ MachineFunction *MF = First->getMF();
+ const MachineMemOperand *MMO = *First->memoperands_begin();
+ Align MMOAlign = MMO->getAlign();
+ if (const PseudoSourceValue *Sour
