[clang] 66f332b - [X86] Add missing key feature for core2
Author: Freddy Ye
Date: 2022-09-02T16:06:07+08:00
New Revision: 66f332bc1ac04430580a8498ab5537b392f3ea1e
URL:
https://github.com/llvm/llvm-project/commit/66f332bc1ac04430580a8498ab5537b392f3ea1e
DIFF:
https://github.com/llvm/llvm-project/commit/66f332bc1ac04430580a8498ab5537b392f3ea1e.diff
LOG: [X86] Add missing key feature for core2
Reviewed By: erichkeane
Differential Revision: https://reviews.llvm.org/D133094
Added:
Modified:
clang/test/CodeGen/attr-target-mv.c
llvm/lib/Support/X86TargetParser.cpp
Removed:
diff --git a/clang/test/CodeGen/attr-target-mv.c
b/clang/test/CodeGen/attr-target-mv.c
index 8ab2f992fc1fe..07235eaeebdd5 100644
--- a/clang/test/CodeGen/attr-target-mv.c
+++ b/clang/test/CodeGen/attr-target-mv.c
@@ -14,6 +14,7 @@ int __attribute__((target("arch=tigerlake"))) foo(void)
{return 9;}
int __attribute__((target("arch=sapphirerapids"))) foo(void) {return 10;}
int __attribute__((target("arch=alderlake"))) foo(void) {return 11;}
int __attribute__((target("arch=rocketlake"))) foo(void) {return 12;}
+int __attribute__((target("arch=core2"))) foo(void) {return 13;}
int __attribute__((target("default"))) foo(void) { return 2; }
int bar(void) {
@@ -146,6 +147,8 @@ void calls_pr50025c(void) { pr50025c(); }
// LINUX: ret i32 11
// LINUX: define{{.*}} i32 @foo.arch_rocketlake()
// LINUX: ret i32 12
+// LINUX: define{{.*}} i32 @foo.arch_core2()
+// LINUX: ret i32 13
// LINUX: define{{.*}} i32 @foo()
// LINUX: ret i32 2
// LINUX: define{{.*}} i32 @bar()
@@ -175,6 +178,8 @@ void calls_pr50025c(void) { pr50025c(); }
// WINDOWS: ret i32 11
// WINDOWS: define dso_local i32 @foo.arch_rocketlake()
// WINDOWS: ret i32 12
+// WINDOWS: define dso_local i32 @foo.arch_core2()
+// WINDOWS: ret i32 13
// WINDOWS: define dso_local i32 @foo()
// WINDOWS: ret i32 2
// WINDOWS: define dso_local i32 @bar()
diff --git a/llvm/lib/Support/X86TargetParser.cpp
b/llvm/lib/Support/X86TargetParser.cpp
index 2567f3ed8034b..bb62102ba0aeb 100644
--- a/llvm/lib/Support/X86TargetParser.cpp
+++ b/llvm/lib/Support/X86TargetParser.cpp
@@ -321,7 +321,7 @@ constexpr ProcInfo Processors[] = {
{ {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
{ {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
// Core microarchitecture based processors.
- { {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
+ { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2 },
{ {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
// Atom processors
{ {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
___
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[clang] [clang] Add support for new loop attribute [[clang::code_align()]] (PR #70762)
@@ -7416,3 +7416,46 @@ that ``p->array`` must have at least ``p->count`` number
of elements available:
}];
}
+
+def CodeAlignAttrDocs : Documentation {
+ let Category = DocCatVariable;
+ let Heading = "clang::code_align";
+ let Content = [{
+The ``clang::code_align(N)`` attribute applies to a loop and it specifies the
+byte alignment for a loop. The attribute accepts a positive integer constant
+initialization expression indicating the number of bytes for the minimum
+alignment boundary. Its value must be a power of 2, between 1 and 4096, such as
+1, 2, 4, 8, and so on. This attribute sets ``llvm.loop.align`` loop metadata
+when it applies on a loop statement.
FreddyLeaf wrote:
Added consumption on this IR in MBBPlacement:
https://github.com/llvm/llvm-project/pull/71026
https://github.com/llvm/llvm-project/pull/70762
___
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[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
https://github.com/FreddyLeaf created
https://github.com/llvm/llvm-project/pull/75580
Since Knight Landing and Knight Mill microarchitectures are EOL, we
would like to remove its support in LLVM 19. In LLVM 18, we will first
emit a warning for the usage.
>From e16afbdc9f0c04bad0e8f80f90c0eb26c13d3326 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 15 Dec 2023 16:50:23 +0800
Subject: [PATCH] [X86] Emit Warnings for frontend options to enable knl/knm.
Since Knight Landing and Knight Mill microarchitectures are EOL, we
would like to remove its support in LLVM 19. In LLVM 18, we will first
emit a warning for the usage.
---
clang/include/clang/Basic/DiagnosticCommonKinds.td | 2 ++
clang/lib/Basic/Targets/X86.cpp| 3 +++
clang/test/CodeGen/X86/avx512er-builtins.c | 2 +-
clang/test/CodeGen/X86/avx512pf-builtins.c | 2 +-
clang/test/Driver/cl-x86-flags.c | 10 --
clang/test/Frontend/x86-target-cpu.c | 10 --
clang/test/Misc/warning-flags.c| 3 ++-
7 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td
b/clang/include/clang/Basic/DiagnosticCommonKinds.td
index 65a33f61a6948a..40841e9df547bc 100644
--- a/clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -349,6 +349,8 @@ def warn_invalid_feature_combination : Warning<
def warn_target_unrecognized_env : Warning<
"mismatch between architecture and environment in target triple '%0'; did
you mean '%1'?">,
InGroup;
+def warn_knl_knm_target_supports_remove : Warning<
+ "KNL/KNM's feature support will be removed in LLVM 19.">;
// Source manager
def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index b97f88647fa49f..dc56524d378104 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -295,11 +295,13 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasAVX512BF16 = true;
} else if (Feature == "+avx512er") {
HasAVX512ER = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512fp16") {
HasAVX512FP16 = true;
HasLegalHalfType = true;
} else if (Feature == "+avx512pf") {
HasAVX512PF = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512dq") {
HasAVX512DQ = true;
} else if (Feature == "+avx512bitalg") {
@@ -358,6 +360,7 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasPREFETCHI = true;
} else if (Feature == "+prefetchwt1") {
HasPREFETCHWT1 = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+clzero") {
HasCLZERO = true;
} else if (Feature == "+cldemote") {
diff --git a/clang/test/CodeGen/X86/avx512er-builtins.c
b/clang/test/CodeGen/X86/avx512er-builtins.c
index ee31236a3c01aa..11ec6aabec1e3f 100644
--- a/clang/test/CodeGen/X86/avx512er-builtins.c
+++ b/clang/test/CodeGen/X86/avx512er-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall | FileCheck %s
#include
diff --git a/clang/test/CodeGen/X86/avx512pf-builtins.c
b/clang/test/CodeGen/X86/avx512pf-builtins.c
index 4ca70f5787968b..3a117ed6a9460e 100644
--- a/clang/test/CodeGen/X86/avx512pf-builtins.c
+++ b/clang/test/CodeGen/X86/avx512pf-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall
-Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall |
FileCheck %s
#include
diff --git a/clang/test/Driver/cl-x86-flags.c b/clang/test/Driver/cl-x86-flags.c
index 51b16f0ce35463..ae35a312fe8a4b 100644
--- a/clang/test/Driver/cl-x86-flags.c
+++ b/clang/test/Driver/cl-x86-flags.c
@@ -69,7 +69,10 @@
// RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s |
FileCheck -check-prefix=avx2 %s
// avx2: invalid /arch: argument
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify -DTEST_32_ARCH_AVX512F -- %s
+// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature supp
[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
FreddyLeaf wrote: Let me first paste reasons I listed before: 1. INTEL has officially announced these products’ EOL on about Aug. 2017 1. Even for now, clang/llvm’s supports on these products are incomplete. For example, knm targets has AVX5124FMAPS instructions, while its intrinsic and assembly support is missing. And it is weird that avx5124fmaps is still listed at llvm/include/llvm/TargetParser/X86TargetParser.def. 1. It sometimes leads to bad performance by wrong usage of options. 1. We can claim this change on release notes to notify users intentionally support these targets to use older releases. https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
FreddyLeaf wrote: And here're two more reasons I collected from gcc: 1. previously ICC and ICX has removed the support and emitted errors 1. we would also like to remove the support in GCC to reduce maintainence effort. https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/75580
>From e16afbdc9f0c04bad0e8f80f90c0eb26c13d3326 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 15 Dec 2023 16:50:23 +0800
Subject: [PATCH 1/2] [X86] Emit Warnings for frontend options to enable
knl/knm.
Since Knight Landing and Knight Mill microarchitectures are EOL, we
would like to remove its support in LLVM 19. In LLVM 18, we will first
emit a warning for the usage.
---
clang/include/clang/Basic/DiagnosticCommonKinds.td | 2 ++
clang/lib/Basic/Targets/X86.cpp| 3 +++
clang/test/CodeGen/X86/avx512er-builtins.c | 2 +-
clang/test/CodeGen/X86/avx512pf-builtins.c | 2 +-
clang/test/Driver/cl-x86-flags.c | 10 --
clang/test/Frontend/x86-target-cpu.c | 10 --
clang/test/Misc/warning-flags.c| 3 ++-
7 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td
b/clang/include/clang/Basic/DiagnosticCommonKinds.td
index 65a33f61a6948a..40841e9df547bc 100644
--- a/clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -349,6 +349,8 @@ def warn_invalid_feature_combination : Warning<
def warn_target_unrecognized_env : Warning<
"mismatch between architecture and environment in target triple '%0'; did
you mean '%1'?">,
InGroup;
+def warn_knl_knm_target_supports_remove : Warning<
+ "KNL/KNM's feature support will be removed in LLVM 19.">;
// Source manager
def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index b97f88647fa49f..dc56524d378104 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -295,11 +295,13 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasAVX512BF16 = true;
} else if (Feature == "+avx512er") {
HasAVX512ER = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512fp16") {
HasAVX512FP16 = true;
HasLegalHalfType = true;
} else if (Feature == "+avx512pf") {
HasAVX512PF = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512dq") {
HasAVX512DQ = true;
} else if (Feature == "+avx512bitalg") {
@@ -358,6 +360,7 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasPREFETCHI = true;
} else if (Feature == "+prefetchwt1") {
HasPREFETCHWT1 = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+clzero") {
HasCLZERO = true;
} else if (Feature == "+cldemote") {
diff --git a/clang/test/CodeGen/X86/avx512er-builtins.c
b/clang/test/CodeGen/X86/avx512er-builtins.c
index ee31236a3c01aa..11ec6aabec1e3f 100644
--- a/clang/test/CodeGen/X86/avx512er-builtins.c
+++ b/clang/test/CodeGen/X86/avx512er-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall | FileCheck %s
#include
diff --git a/clang/test/CodeGen/X86/avx512pf-builtins.c
b/clang/test/CodeGen/X86/avx512pf-builtins.c
index 4ca70f5787968b..3a117ed6a9460e 100644
--- a/clang/test/CodeGen/X86/avx512pf-builtins.c
+++ b/clang/test/CodeGen/X86/avx512pf-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall
-Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall |
FileCheck %s
#include
diff --git a/clang/test/Driver/cl-x86-flags.c b/clang/test/Driver/cl-x86-flags.c
index 51b16f0ce35463..ae35a312fe8a4b 100644
--- a/clang/test/Driver/cl-x86-flags.c
+++ b/clang/test/Driver/cl-x86-flags.c
@@ -69,7 +69,10 @@
// RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s |
FileCheck -check-prefix=avx2 %s
// avx2: invalid /arch: argument
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify -DTEST_32_ARCH_AVX512F -- %s
+// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
#if defined(TEST_32_ARCH_AVX512F)
#if _M_IX86_FP !=
[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/75580
>From e16afbdc9f0c04bad0e8f80f90c0eb26c13d3326 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 15 Dec 2023 16:50:23 +0800
Subject: [PATCH 1/3] [X86] Emit Warnings for frontend options to enable
knl/knm.
Since Knight Landing and Knight Mill microarchitectures are EOL, we
would like to remove its support in LLVM 19. In LLVM 18, we will first
emit a warning for the usage.
---
clang/include/clang/Basic/DiagnosticCommonKinds.td | 2 ++
clang/lib/Basic/Targets/X86.cpp| 3 +++
clang/test/CodeGen/X86/avx512er-builtins.c | 2 +-
clang/test/CodeGen/X86/avx512pf-builtins.c | 2 +-
clang/test/Driver/cl-x86-flags.c | 10 --
clang/test/Frontend/x86-target-cpu.c | 10 --
clang/test/Misc/warning-flags.c| 3 ++-
7 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td
b/clang/include/clang/Basic/DiagnosticCommonKinds.td
index 65a33f61a6948a..40841e9df547bc 100644
--- a/clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -349,6 +349,8 @@ def warn_invalid_feature_combination : Warning<
def warn_target_unrecognized_env : Warning<
"mismatch between architecture and environment in target triple '%0'; did
you mean '%1'?">,
InGroup;
+def warn_knl_knm_target_supports_remove : Warning<
+ "KNL/KNM's feature support will be removed in LLVM 19.">;
// Source manager
def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index b97f88647fa49f..dc56524d378104 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -295,11 +295,13 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasAVX512BF16 = true;
} else if (Feature == "+avx512er") {
HasAVX512ER = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512fp16") {
HasAVX512FP16 = true;
HasLegalHalfType = true;
} else if (Feature == "+avx512pf") {
HasAVX512PF = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512dq") {
HasAVX512DQ = true;
} else if (Feature == "+avx512bitalg") {
@@ -358,6 +360,7 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasPREFETCHI = true;
} else if (Feature == "+prefetchwt1") {
HasPREFETCHWT1 = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+clzero") {
HasCLZERO = true;
} else if (Feature == "+cldemote") {
diff --git a/clang/test/CodeGen/X86/avx512er-builtins.c
b/clang/test/CodeGen/X86/avx512er-builtins.c
index ee31236a3c01aa..11ec6aabec1e3f 100644
--- a/clang/test/CodeGen/X86/avx512er-builtins.c
+++ b/clang/test/CodeGen/X86/avx512er-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall | FileCheck %s
#include
diff --git a/clang/test/CodeGen/X86/avx512pf-builtins.c
b/clang/test/CodeGen/X86/avx512pf-builtins.c
index 4ca70f5787968b..3a117ed6a9460e 100644
--- a/clang/test/CodeGen/X86/avx512pf-builtins.c
+++ b/clang/test/CodeGen/X86/avx512pf-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall
-Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall |
FileCheck %s
#include
diff --git a/clang/test/Driver/cl-x86-flags.c b/clang/test/Driver/cl-x86-flags.c
index 51b16f0ce35463..ae35a312fe8a4b 100644
--- a/clang/test/Driver/cl-x86-flags.c
+++ b/clang/test/Driver/cl-x86-flags.c
@@ -69,7 +69,10 @@
// RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s |
FileCheck -check-prefix=avx2 %s
// avx2: invalid /arch: argument
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify -DTEST_32_ARCH_AVX512F -- %s
+// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
#if defined(TEST_32_ARCH_AVX512F)
#if _M_IX86_FP !=
[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
@@ -349,6 +349,8 @@ def warn_invalid_feature_combination : Warning< def warn_target_unrecognized_env : Warning< "mismatch between architecture and environment in target triple '%0'; did you mean '%1'?">, InGroup; +def warn_knl_knm_target_supports_remove : Warning< FreddyLeaf wrote: Thanks review, addressed in 3eb6b009b14202d4c14bdc691d80550bac4c9aa7 https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/75580
>From e16afbdc9f0c04bad0e8f80f90c0eb26c13d3326 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 15 Dec 2023 16:50:23 +0800
Subject: [PATCH 1/4] [X86] Emit Warnings for frontend options to enable
knl/knm.
Since Knight Landing and Knight Mill microarchitectures are EOL, we
would like to remove its support in LLVM 19. In LLVM 18, we will first
emit a warning for the usage.
---
clang/include/clang/Basic/DiagnosticCommonKinds.td | 2 ++
clang/lib/Basic/Targets/X86.cpp| 3 +++
clang/test/CodeGen/X86/avx512er-builtins.c | 2 +-
clang/test/CodeGen/X86/avx512pf-builtins.c | 2 +-
clang/test/Driver/cl-x86-flags.c | 10 --
clang/test/Frontend/x86-target-cpu.c | 10 --
clang/test/Misc/warning-flags.c| 3 ++-
7 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td
b/clang/include/clang/Basic/DiagnosticCommonKinds.td
index 65a33f61a6948a..40841e9df547bc 100644
--- a/clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -349,6 +349,8 @@ def warn_invalid_feature_combination : Warning<
def warn_target_unrecognized_env : Warning<
"mismatch between architecture and environment in target triple '%0'; did
you mean '%1'?">,
InGroup;
+def warn_knl_knm_target_supports_remove : Warning<
+ "KNL/KNM's feature support will be removed in LLVM 19.">;
// Source manager
def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index b97f88647fa49f..dc56524d378104 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -295,11 +295,13 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasAVX512BF16 = true;
} else if (Feature == "+avx512er") {
HasAVX512ER = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512fp16") {
HasAVX512FP16 = true;
HasLegalHalfType = true;
} else if (Feature == "+avx512pf") {
HasAVX512PF = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512dq") {
HasAVX512DQ = true;
} else if (Feature == "+avx512bitalg") {
@@ -358,6 +360,7 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasPREFETCHI = true;
} else if (Feature == "+prefetchwt1") {
HasPREFETCHWT1 = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+clzero") {
HasCLZERO = true;
} else if (Feature == "+cldemote") {
diff --git a/clang/test/CodeGen/X86/avx512er-builtins.c
b/clang/test/CodeGen/X86/avx512er-builtins.c
index ee31236a3c01aa..11ec6aabec1e3f 100644
--- a/clang/test/CodeGen/X86/avx512er-builtins.c
+++ b/clang/test/CodeGen/X86/avx512er-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall | FileCheck %s
#include
diff --git a/clang/test/CodeGen/X86/avx512pf-builtins.c
b/clang/test/CodeGen/X86/avx512pf-builtins.c
index 4ca70f5787968b..3a117ed6a9460e 100644
--- a/clang/test/CodeGen/X86/avx512pf-builtins.c
+++ b/clang/test/CodeGen/X86/avx512pf-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall
-Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall |
FileCheck %s
#include
diff --git a/clang/test/Driver/cl-x86-flags.c b/clang/test/Driver/cl-x86-flags.c
index 51b16f0ce35463..ae35a312fe8a4b 100644
--- a/clang/test/Driver/cl-x86-flags.c
+++ b/clang/test/Driver/cl-x86-flags.c
@@ -69,7 +69,10 @@
// RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s |
FileCheck -check-prefix=avx2 %s
// avx2: invalid /arch: argument
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify -DTEST_32_ARCH_AVX512F -- %s
+// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
#if defined(TEST_32_ARCH_AVX512F)
#if _M_IX86_FP !=
[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
FreddyLeaf wrote: > Can you give me a better idea of the stages you intend to follow with this. > The patch title suggests removing all KNL/KNM handling but the patch itself > looks to be just about the KNL/KNM specific features. I have created a draft PR to do removal in next release: https://github.com/llvm/llvm-project/pull/76383. Comments are welcome there. For this PR, I added warnings to features only but not cpuname, mainly to reduce efforts. Especially when using `-march=native` on a knl machine, these warnings can also be emitted. https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/75580
>From e16afbdc9f0c04bad0e8f80f90c0eb26c13d3326 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 15 Dec 2023 16:50:23 +0800
Subject: [PATCH 1/5] [X86] Emit Warnings for frontend options to enable
knl/knm.
Since Knight Landing and Knight Mill microarchitectures are EOL, we
would like to remove its support in LLVM 19. In LLVM 18, we will first
emit a warning for the usage.
---
clang/include/clang/Basic/DiagnosticCommonKinds.td | 2 ++
clang/lib/Basic/Targets/X86.cpp| 3 +++
clang/test/CodeGen/X86/avx512er-builtins.c | 2 +-
clang/test/CodeGen/X86/avx512pf-builtins.c | 2 +-
clang/test/Driver/cl-x86-flags.c | 10 --
clang/test/Frontend/x86-target-cpu.c | 10 --
clang/test/Misc/warning-flags.c| 3 ++-
7 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td
b/clang/include/clang/Basic/DiagnosticCommonKinds.td
index 65a33f61a6948a..40841e9df547bc 100644
--- a/clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -349,6 +349,8 @@ def warn_invalid_feature_combination : Warning<
def warn_target_unrecognized_env : Warning<
"mismatch between architecture and environment in target triple '%0'; did
you mean '%1'?">,
InGroup;
+def warn_knl_knm_target_supports_remove : Warning<
+ "KNL/KNM's feature support will be removed in LLVM 19.">;
// Source manager
def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index b97f88647fa49f..dc56524d378104 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -295,11 +295,13 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasAVX512BF16 = true;
} else if (Feature == "+avx512er") {
HasAVX512ER = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512fp16") {
HasAVX512FP16 = true;
HasLegalHalfType = true;
} else if (Feature == "+avx512pf") {
HasAVX512PF = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512dq") {
HasAVX512DQ = true;
} else if (Feature == "+avx512bitalg") {
@@ -358,6 +360,7 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasPREFETCHI = true;
} else if (Feature == "+prefetchwt1") {
HasPREFETCHWT1 = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+clzero") {
HasCLZERO = true;
} else if (Feature == "+cldemote") {
diff --git a/clang/test/CodeGen/X86/avx512er-builtins.c
b/clang/test/CodeGen/X86/avx512er-builtins.c
index ee31236a3c01aa..11ec6aabec1e3f 100644
--- a/clang/test/CodeGen/X86/avx512er-builtins.c
+++ b/clang/test/CodeGen/X86/avx512er-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall | FileCheck %s
#include
diff --git a/clang/test/CodeGen/X86/avx512pf-builtins.c
b/clang/test/CodeGen/X86/avx512pf-builtins.c
index 4ca70f5787968b..3a117ed6a9460e 100644
--- a/clang/test/CodeGen/X86/avx512pf-builtins.c
+++ b/clang/test/CodeGen/X86/avx512pf-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall
-Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall |
FileCheck %s
#include
diff --git a/clang/test/Driver/cl-x86-flags.c b/clang/test/Driver/cl-x86-flags.c
index 51b16f0ce35463..ae35a312fe8a4b 100644
--- a/clang/test/Driver/cl-x86-flags.c
+++ b/clang/test/Driver/cl-x86-flags.c
@@ -69,7 +69,10 @@
// RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s |
FileCheck -check-prefix=avx2 %s
// avx2: invalid /arch: argument
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify -DTEST_32_ARCH_AVX512F -- %s
+// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
#if defined(TEST_32_ARCH_AVX512F)
#if _M_IX86_FP !=
[clang] [llvm] [X86] Correct operand order of UWRMSR. (PR #76389)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/76389
>From 36e618e3b4eb083510de80c9ee6c0732948f3bc5 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Tue, 26 Dec 2023 16:39:21 +0800
Subject: [PATCH 1/2] [X86] Correct operand order of UWRMSR.
---
llvm/lib/Target/X86/X86InstrSystem.td | 4 ++--
llvm/test/CodeGen/X86/usermsr-intrinsics.ll | 8
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td
b/llvm/lib/Target/X86/X86InstrSystem.td
index efb58c6102dd1d..699e5847e63fb9 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -446,11 +446,11 @@ let Predicates = [HasUSERMSR], mayLoad = 1 in {
}
let Predicates = [HasUSERMSR], mayStore = 1 in {
def UWRMSRrr : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
-"uwrmsr\t{$src1, $src2|$src2, $src1}",
+"uwrmsr\t{$src2, $src1|$src1, $src2}",
[(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, T8, XS;
def UWRMSRir : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
"uwrmsr\t{$src, $imm|$imm, $src}",
-[(int_x86_uwrmsr GR64:$src, i64immSExt32_su:$imm)]>, T_MAP7,
XS, VEX;
+[(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7,
XS, VEX;
}
let Defs = [RAX, RDX], Uses = [ECX] in
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
diff --git a/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
b/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
index 29801a494f498f..fa569affdd9ff3 100644
--- a/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/usermsr-intrinsics.ll
@@ -35,7 +35,7 @@ declare i64 @llvm.x86.urdmsr(i64 %A)
define void @test_int_x86_uwrmsr(i64 %A, i64 %B) nounwind {
; X64-LABEL: test_int_x86_uwrmsr:
; X64: # %bb.0:
-; X64-NEXT:uwrmsr %rdi, %rsi # encoding: [0xf3,0x0f,0x38,0xf8,0xfe]
+; X64-NEXT:uwrmsr %rsi, %rdi # encoding: [0xf3,0x0f,0x38,0xf8,0xfe]
; X64-NEXT:retq # encoding: [0xc3]
call void @llvm.x86.uwrmsr(i64 %A, i64 %B)
ret void
@@ -46,7 +46,7 @@ define void @test_int_x86_uwrmsr_const(i64 %A) nounwind {
; X64: # %bb.0:
; X64-NEXT:uwrmsr %rdi, $123 # encoding:
[0xc4,0xe7,0x7a,0xf8,0xc7,0x7b,0x00,0x00,0x00]
; X64-NEXT:retq # encoding: [0xc3]
- call void @llvm.x86.uwrmsr(i64 %A, i64 123)
+ call void @llvm.x86.uwrmsr(i64 123, i64 %A)
ret void
}
@@ -55,9 +55,9 @@ define void @test_int_x86_uwrmsr_const_i64(i64 %A) nounwind {
; X64: # %bb.0:
; X64-NEXT:movabsq $8589934591, %rax # encoding:
[0x48,0xb8,0xff,0xff,0xff,0xff,0x01,0x00,0x00,0x00]
; X64-NEXT:# imm = 0x1
-; X64-NEXT:uwrmsr %rdi, %rax # encoding: [0xf3,0x0f,0x38,0xf8,0xf8]
+; X64-NEXT:uwrmsr %rdi, %rax # encoding: [0xf3,0x0f,0x38,0xf8,0xc7]
; X64-NEXT:retq # encoding: [0xc3]
- call void @llvm.x86.uwrmsr(i64 %A, i64 8589934591)
+ call void @llvm.x86.uwrmsr(i64 8589934591, i64 %A)
ret void
}
>From 81181956e2f222711074ef00d66f8ffc20ef33a9 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Tue, 26 Dec 2023 17:52:45 +0800
Subject: [PATCH 2/2] Add doxygen
---
clang/lib/Headers/usermsrintrin.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/clang/lib/Headers/usermsrintrin.h
b/clang/lib/Headers/usermsrintrin.h
index 6d1424ad3b2edd..61388376706dc6 100644
--- a/clang/lib/Headers/usermsrintrin.h
+++ b/clang/lib/Headers/usermsrintrin.h
@@ -14,12 +14,33 @@
#define __USERMSRINTRIN_H
#ifdef __x86_64__
+/// Reads the contents of a 64-bit MSR specified in \a __A into \a dst.
+///
+/// This intrinsic corresponds to the URDMSR instruction.
+/// \param __A
+///An unsigned long long.
+///
+/// \code{.operation}
+///DEST := MSR[__A]
+/// \endcode
static __inline__ unsigned long long
__attribute__((__always_inline__, __nodebug__, __target__("usermsr")))
_urdmsr(unsigned long long __A) {
return __builtin_ia32_urdmsr(__A);
}
+/// Writes the contents of \a __B into the 64-bit MSR specified in \a __A.
+///
+/// This intrinsic corresponds to the UWRMSR instruction.
+///
+/// \param __A
+///An unsigned long long.
+/// \param __B
+///An unsigned long long.
+///
+/// \code{.operation}
+///MSR[__A] := __B
+/// \endcode
static __inline__ void
__attribute__((__always_inline__, __nodebug__, __target__("usermsr")))
_uwrmsr(unsigned long long __A, unsigned long long __B) {
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [X86] Correct operand order of UWRMSR. (PR #76389)
https://github.com/FreddyLeaf closed https://github.com/llvm/llvm-project/pull/76389 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Correct operand order of UWRMSR. (PR #76389)
FreddyLeaf wrote: https://github.com/llvm/llvm-project/assets/64940021/9b7acece-cbbe-453e-b913-9b13a6f79b56";> CCMP is already disclosed in https://cdrdv2.intel.com/v1/dl/getContent/784266 https://github.com/llvm/llvm-project/pull/76389 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Remove RAO-INT from Grandridge (PR #76420)
https://github.com/FreddyLeaf created
https://github.com/llvm/llvm-project/pull/76420
According to latest spec: https://cdrdv2.intel.com/v1/dl/getContent/671368
>From ae1d12c24facb36323b9b46a73a1fbc3edff4dc8 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Wed, 27 Dec 2023 10:33:30 +0800
Subject: [PATCH] [X86] Remove RAO-INT from Grandridge
According to latest spec: https://cdrdv2.intel.com/v1/dl/getContent/671368
---
clang/test/Preprocessor/predefined-arch-macros.c | 6 ++
llvm/lib/Target/X86/X86.td | 11 +++
llvm/lib/TargetParser/X86TargetParser.cpp| 4 +---
3 files changed, 6 insertions(+), 15 deletions(-)
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c
b/clang/test/Preprocessor/predefined-arch-macros.c
index 1ae6faea776785..27c7b4a271fee8 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -2515,7 +2515,7 @@
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
// RUN: %clang -march=grandridge -m32 -E -dM %s -o - 2>&1 \
// RUN: --target=i386 \
-// RUN: | FileCheck -match-full-lines %s
-check-prefixes=CHECK_SRF_M32,CHECK_GRR_M32
+// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M32
// RUN: %clang -march=arrowlake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
@@ -2572,7 +2572,6 @@
// CHECK_SRF_M32: #define __PRFCHW__ 1
// CHECK_SRF_M32: #define __PTWRITE__ 1
// CHECK_SRF_M32-NOT: #define __RAOINT__ 1
-// CHECK_GRR_M32: #define __RAOINT__ 1
// CHECK_SRF_M32: #define __RDPID__ 1
// CHECK_SRF_M32: #define __RDRND__ 1
// CHECK_SRF_M32: #define __RDSEED__ 1
@@ -2618,7 +2617,7 @@
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
// RUN: %clang -march=grandridge -m64 -E -dM %s -o - 2>&1 \
// RUN: --target=i386 \
-// RUN: | FileCheck -match-full-lines %s
-check-prefixes=CHECK_SRF_M64,CHECK_GRR_M64
+// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M64
// RUN: %clang -march=arrowlake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
@@ -2675,7 +2674,6 @@
// CHECK_SRF_M64: #define __PRFCHW__ 1
// CHECK_SRF_M64: #define __PTWRITE__ 1
// CHECK_SRF_M64-NOT: #define __RAOINT__ 1
-// CHECK_GRR_M64: #define __RAOINT__ 1
// CHECK_SRF_M64: #define __RDPID__ 1
// CHECK_SRF_M64: #define __RDRND__ 1
// CHECK_SRF_M64: #define __RDSEED__ 1
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 5fd6828f43129d..e89ddcc570c96c 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1256,11 +1256,6 @@ def ProcessorFeatures {
list SRFFeatures =
!listconcat(ADLFeatures, SRFAdditionalFeatures);
- // Grandridge
- list GRRAdditionalFeatures = [FeatureRAOINT];
- list GRRFeatures =
-!listconcat(SRFFeatures, GRRAdditionalFeatures);
-
// Arrowlake S
list ARLSAdditionalFeatures = [FeatureAVXVNNIINT16,
FeatureSHA512,
@@ -1706,10 +1701,10 @@ foreach P = ["goldmont_plus", "goldmont-plus"] in {
}
def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures,
ProcessorFeatures.TRMTuning>;
-def : ProcModel<"sierraforest", AlderlakePModel, ProcessorFeatures.SRFFeatures,
-ProcessorFeatures.TRMTuning>;
-def : ProcModel<"grandridge", AlderlakePModel, ProcessorFeatures.GRRFeatures,
+foreach P = ["sierraforest", "grandridge"] in {
+ def : ProcModel;
+}
// "Arrandale" along with corei3 and corei5
foreach P = ["nehalem", "corei7", "core_i7_sse4_2"] in {
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp
b/llvm/lib/TargetParser/X86TargetParser.cpp
index 085554f18b2b6b..d46ff07ec7340a 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -162,8 +162,6 @@ constexpr FeatureBitset FeaturesAlderlake =
constexpr FeatureBitset FeaturesSierraforest =
FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
-constexpr FeatureBitset FeaturesGrandridge =
-FeaturesSierraforest | FeatureRAOINT;
constexpr FeatureBitset FeaturesArrowlakeS = FeaturesSierraforest |
FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
constexpr FeatureBitset FeaturesPantherlake =
@@ -369,7 +367,7 @@ constexpr ProcInfo Processors[] = {
// Sierraforest microarchitecture based processors.
{ {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest,
'p', false },
// Grandridge microarchitecture based processors.
- { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p',
false },
+ { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesSierraforest, 'p',
false },
// Granite Rapids microarchitecture based processo
[compiler-rt] [clang] [llvm] [mlir] [lld] [flang] [clang-tools-extra] [X86] Remove RAO-INT from Grandridge (PR #76420)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/76420
>From ae1d12c24facb36323b9b46a73a1fbc3edff4dc8 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Wed, 27 Dec 2023 10:33:30 +0800
Subject: [PATCH] [X86] Remove RAO-INT from Grandridge
According to latest spec: https://cdrdv2.intel.com/v1/dl/getContent/671368
---
clang/test/Preprocessor/predefined-arch-macros.c | 6 ++
llvm/lib/Target/X86/X86.td | 11 +++
llvm/lib/TargetParser/X86TargetParser.cpp| 4 +---
3 files changed, 6 insertions(+), 15 deletions(-)
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c
b/clang/test/Preprocessor/predefined-arch-macros.c
index 1ae6faea776785..27c7b4a271fee8 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -2515,7 +2515,7 @@
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
// RUN: %clang -march=grandridge -m32 -E -dM %s -o - 2>&1 \
// RUN: --target=i386 \
-// RUN: | FileCheck -match-full-lines %s
-check-prefixes=CHECK_SRF_M32,CHECK_GRR_M32
+// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M32
// RUN: %clang -march=arrowlake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
@@ -2572,7 +2572,6 @@
// CHECK_SRF_M32: #define __PRFCHW__ 1
// CHECK_SRF_M32: #define __PTWRITE__ 1
// CHECK_SRF_M32-NOT: #define __RAOINT__ 1
-// CHECK_GRR_M32: #define __RAOINT__ 1
// CHECK_SRF_M32: #define __RDPID__ 1
// CHECK_SRF_M32: #define __RDRND__ 1
// CHECK_SRF_M32: #define __RDSEED__ 1
@@ -2618,7 +2617,7 @@
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
// RUN: %clang -march=grandridge -m64 -E -dM %s -o - 2>&1 \
// RUN: --target=i386 \
-// RUN: | FileCheck -match-full-lines %s
-check-prefixes=CHECK_SRF_M64,CHECK_GRR_M64
+// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M64
// RUN: %clang -march=arrowlake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
@@ -2675,7 +2674,6 @@
// CHECK_SRF_M64: #define __PRFCHW__ 1
// CHECK_SRF_M64: #define __PTWRITE__ 1
// CHECK_SRF_M64-NOT: #define __RAOINT__ 1
-// CHECK_GRR_M64: #define __RAOINT__ 1
// CHECK_SRF_M64: #define __RDPID__ 1
// CHECK_SRF_M64: #define __RDRND__ 1
// CHECK_SRF_M64: #define __RDSEED__ 1
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 5fd6828f43129d..e89ddcc570c96c 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1256,11 +1256,6 @@ def ProcessorFeatures {
list SRFFeatures =
!listconcat(ADLFeatures, SRFAdditionalFeatures);
- // Grandridge
- list GRRAdditionalFeatures = [FeatureRAOINT];
- list GRRFeatures =
-!listconcat(SRFFeatures, GRRAdditionalFeatures);
-
// Arrowlake S
list ARLSAdditionalFeatures = [FeatureAVXVNNIINT16,
FeatureSHA512,
@@ -1706,10 +1701,10 @@ foreach P = ["goldmont_plus", "goldmont-plus"] in {
}
def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures,
ProcessorFeatures.TRMTuning>;
-def : ProcModel<"sierraforest", AlderlakePModel, ProcessorFeatures.SRFFeatures,
-ProcessorFeatures.TRMTuning>;
-def : ProcModel<"grandridge", AlderlakePModel, ProcessorFeatures.GRRFeatures,
+foreach P = ["sierraforest", "grandridge"] in {
+ def : ProcModel;
+}
// "Arrandale" along with corei3 and corei5
foreach P = ["nehalem", "corei7", "core_i7_sse4_2"] in {
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp
b/llvm/lib/TargetParser/X86TargetParser.cpp
index 085554f18b2b6b..d46ff07ec7340a 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -162,8 +162,6 @@ constexpr FeatureBitset FeaturesAlderlake =
constexpr FeatureBitset FeaturesSierraforest =
FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
-constexpr FeatureBitset FeaturesGrandridge =
-FeaturesSierraforest | FeatureRAOINT;
constexpr FeatureBitset FeaturesArrowlakeS = FeaturesSierraforest |
FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
constexpr FeatureBitset FeaturesPantherlake =
@@ -369,7 +367,7 @@ constexpr ProcInfo Processors[] = {
// Sierraforest microarchitecture based processors.
{ {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest,
'p', false },
// Grandridge microarchitecture based processors.
- { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p',
false },
+ { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesSierraforest, 'p',
false },
// Granite Rapids microarchitecture based processors.
{ {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16,
FeaturesGr
[flang] [mlir] [clang-tools-extra] [clang] [llvm] [compiler-rt] [lld] [X86] Remove RAO-INT from Grandridge (PR #76420)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/76420
>From ae1d12c24facb36323b9b46a73a1fbc3edff4dc8 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Wed, 27 Dec 2023 10:33:30 +0800
Subject: [PATCH] [X86] Remove RAO-INT from Grandridge
According to latest spec: https://cdrdv2.intel.com/v1/dl/getContent/671368
---
clang/test/Preprocessor/predefined-arch-macros.c | 6 ++
llvm/lib/Target/X86/X86.td | 11 +++
llvm/lib/TargetParser/X86TargetParser.cpp| 4 +---
3 files changed, 6 insertions(+), 15 deletions(-)
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c
b/clang/test/Preprocessor/predefined-arch-macros.c
index 1ae6faea776785..27c7b4a271fee8 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -2515,7 +2515,7 @@
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
// RUN: %clang -march=grandridge -m32 -E -dM %s -o - 2>&1 \
// RUN: --target=i386 \
-// RUN: | FileCheck -match-full-lines %s
-check-prefixes=CHECK_SRF_M32,CHECK_GRR_M32
+// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M32
// RUN: %clang -march=arrowlake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
@@ -2572,7 +2572,6 @@
// CHECK_SRF_M32: #define __PRFCHW__ 1
// CHECK_SRF_M32: #define __PTWRITE__ 1
// CHECK_SRF_M32-NOT: #define __RAOINT__ 1
-// CHECK_GRR_M32: #define __RAOINT__ 1
// CHECK_SRF_M32: #define __RDPID__ 1
// CHECK_SRF_M32: #define __RDRND__ 1
// CHECK_SRF_M32: #define __RDSEED__ 1
@@ -2618,7 +2617,7 @@
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
// RUN: %clang -march=grandridge -m64 -E -dM %s -o - 2>&1 \
// RUN: --target=i386 \
-// RUN: | FileCheck -match-full-lines %s
-check-prefixes=CHECK_SRF_M64,CHECK_GRR_M64
+// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M64
// RUN: %clang -march=arrowlake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
@@ -2675,7 +2674,6 @@
// CHECK_SRF_M64: #define __PRFCHW__ 1
// CHECK_SRF_M64: #define __PTWRITE__ 1
// CHECK_SRF_M64-NOT: #define __RAOINT__ 1
-// CHECK_GRR_M64: #define __RAOINT__ 1
// CHECK_SRF_M64: #define __RDPID__ 1
// CHECK_SRF_M64: #define __RDRND__ 1
// CHECK_SRF_M64: #define __RDSEED__ 1
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 5fd6828f43129d..e89ddcc570c96c 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1256,11 +1256,6 @@ def ProcessorFeatures {
list SRFFeatures =
!listconcat(ADLFeatures, SRFAdditionalFeatures);
- // Grandridge
- list GRRAdditionalFeatures = [FeatureRAOINT];
- list GRRFeatures =
-!listconcat(SRFFeatures, GRRAdditionalFeatures);
-
// Arrowlake S
list ARLSAdditionalFeatures = [FeatureAVXVNNIINT16,
FeatureSHA512,
@@ -1706,10 +1701,10 @@ foreach P = ["goldmont_plus", "goldmont-plus"] in {
}
def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures,
ProcessorFeatures.TRMTuning>;
-def : ProcModel<"sierraforest", AlderlakePModel, ProcessorFeatures.SRFFeatures,
-ProcessorFeatures.TRMTuning>;
-def : ProcModel<"grandridge", AlderlakePModel, ProcessorFeatures.GRRFeatures,
+foreach P = ["sierraforest", "grandridge"] in {
+ def : ProcModel;
+}
// "Arrandale" along with corei3 and corei5
foreach P = ["nehalem", "corei7", "core_i7_sse4_2"] in {
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp
b/llvm/lib/TargetParser/X86TargetParser.cpp
index 085554f18b2b6b..d46ff07ec7340a 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -162,8 +162,6 @@ constexpr FeatureBitset FeaturesAlderlake =
constexpr FeatureBitset FeaturesSierraforest =
FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
-constexpr FeatureBitset FeaturesGrandridge =
-FeaturesSierraforest | FeatureRAOINT;
constexpr FeatureBitset FeaturesArrowlakeS = FeaturesSierraforest |
FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
constexpr FeatureBitset FeaturesPantherlake =
@@ -369,7 +367,7 @@ constexpr ProcInfo Processors[] = {
// Sierraforest microarchitecture based processors.
{ {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest,
'p', false },
// Grandridge microarchitecture based processors.
- { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p',
false },
+ { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesSierraforest, 'p',
false },
// Granite Rapids microarchitecture based processors.
{ {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16,
FeaturesGr
[compiler-rt] [flang] [libc] [lld] [mlir] [clang] [clang-tools-extra] [openmp] [llvm] [X86] Remove RAO-INT from Grandridge (PR #76420)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/76420
>From ae1d12c24facb36323b9b46a73a1fbc3edff4dc8 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Wed, 27 Dec 2023 10:33:30 +0800
Subject: [PATCH] [X86] Remove RAO-INT from Grandridge
According to latest spec: https://cdrdv2.intel.com/v1/dl/getContent/671368
---
clang/test/Preprocessor/predefined-arch-macros.c | 6 ++
llvm/lib/Target/X86/X86.td | 11 +++
llvm/lib/TargetParser/X86TargetParser.cpp| 4 +---
3 files changed, 6 insertions(+), 15 deletions(-)
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c
b/clang/test/Preprocessor/predefined-arch-macros.c
index 1ae6faea776785..27c7b4a271fee8 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -2515,7 +2515,7 @@
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
// RUN: %clang -march=grandridge -m32 -E -dM %s -o - 2>&1 \
// RUN: --target=i386 \
-// RUN: | FileCheck -match-full-lines %s
-check-prefixes=CHECK_SRF_M32,CHECK_GRR_M32
+// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M32
// RUN: %clang -march=arrowlake -m32 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
@@ -2572,7 +2572,6 @@
// CHECK_SRF_M32: #define __PRFCHW__ 1
// CHECK_SRF_M32: #define __PTWRITE__ 1
// CHECK_SRF_M32-NOT: #define __RAOINT__ 1
-// CHECK_GRR_M32: #define __RAOINT__ 1
// CHECK_SRF_M32: #define __RDPID__ 1
// CHECK_SRF_M32: #define __RDRND__ 1
// CHECK_SRF_M32: #define __RDSEED__ 1
@@ -2618,7 +2617,7 @@
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
// RUN: %clang -march=grandridge -m64 -E -dM %s -o - 2>&1 \
// RUN: --target=i386 \
-// RUN: | FileCheck -match-full-lines %s
-check-prefixes=CHECK_SRF_M64,CHECK_GRR_M64
+// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M64
// RUN: %clang -march=arrowlake -m64 -E -dM %s -o - 2>&1 \
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
@@ -2675,7 +2674,6 @@
// CHECK_SRF_M64: #define __PRFCHW__ 1
// CHECK_SRF_M64: #define __PTWRITE__ 1
// CHECK_SRF_M64-NOT: #define __RAOINT__ 1
-// CHECK_GRR_M64: #define __RAOINT__ 1
// CHECK_SRF_M64: #define __RDPID__ 1
// CHECK_SRF_M64: #define __RDRND__ 1
// CHECK_SRF_M64: #define __RDSEED__ 1
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 5fd6828f43129d..e89ddcc570c96c 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1256,11 +1256,6 @@ def ProcessorFeatures {
list SRFFeatures =
!listconcat(ADLFeatures, SRFAdditionalFeatures);
- // Grandridge
- list GRRAdditionalFeatures = [FeatureRAOINT];
- list GRRFeatures =
-!listconcat(SRFFeatures, GRRAdditionalFeatures);
-
// Arrowlake S
list ARLSAdditionalFeatures = [FeatureAVXVNNIINT16,
FeatureSHA512,
@@ -1706,10 +1701,10 @@ foreach P = ["goldmont_plus", "goldmont-plus"] in {
}
def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures,
ProcessorFeatures.TRMTuning>;
-def : ProcModel<"sierraforest", AlderlakePModel, ProcessorFeatures.SRFFeatures,
-ProcessorFeatures.TRMTuning>;
-def : ProcModel<"grandridge", AlderlakePModel, ProcessorFeatures.GRRFeatures,
+foreach P = ["sierraforest", "grandridge"] in {
+ def : ProcModel;
+}
// "Arrandale" along with corei3 and corei5
foreach P = ["nehalem", "corei7", "core_i7_sse4_2"] in {
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp
b/llvm/lib/TargetParser/X86TargetParser.cpp
index 085554f18b2b6b..d46ff07ec7340a 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -162,8 +162,6 @@ constexpr FeatureBitset FeaturesAlderlake =
constexpr FeatureBitset FeaturesSierraforest =
FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
-constexpr FeatureBitset FeaturesGrandridge =
-FeaturesSierraforest | FeatureRAOINT;
constexpr FeatureBitset FeaturesArrowlakeS = FeaturesSierraforest |
FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
constexpr FeatureBitset FeaturesPantherlake =
@@ -369,7 +367,7 @@ constexpr ProcInfo Processors[] = {
// Sierraforest microarchitecture based processors.
{ {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest,
'p', false },
// Grandridge microarchitecture based processors.
- { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p',
false },
+ { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesSierraforest, 'p',
false },
// Granite Rapids microarchitecture based processors.
{ {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16,
FeaturesGr
[mlir] [compiler-rt] [clang] [openmp] [llvm] [flang] [lld] [libc] [clang-tools-extra] [X86] Remove RAO-INT from Grandridge (PR #76420)
https://github.com/FreddyLeaf closed https://github.com/llvm/llvm-project/pull/76420 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
FreddyLeaf wrote: ping for review @RKSimon are we aligned on the direction to removing knl/knm supports in the end? https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
FreddyLeaf wrote: Keeping `-march` supports for knl/knm meanwhile removing the specific ISA's intrinsic supports doesn't sound quite good to me. And thanks @phoebewang mentioned, removing the KNL/KNM supports could make all other targets always support AVX512F and AVX512VL meanwhile. This can simplify large amounts of logic codes in backend, which is very beneficial. https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
FreddyLeaf wrote: @RKSimon @phoebewang Thanks comments! knm has AVX512_VPOPCNTDQ, I guess we also require it work without avx512vl? And we are going to keep -march/mtune/mcpu support for knl/knm, but removing some specific ISA's intrinsic and lowering supports? Did I get your point wrong? https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/75580
>From e16afbdc9f0c04bad0e8f80f90c0eb26c13d3326 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 15 Dec 2023 16:50:23 +0800
Subject: [PATCH 1/6] [X86] Emit Warnings for frontend options to enable
knl/knm.
Since Knight Landing and Knight Mill microarchitectures are EOL, we
would like to remove its support in LLVM 19. In LLVM 18, we will first
emit a warning for the usage.
---
clang/include/clang/Basic/DiagnosticCommonKinds.td | 2 ++
clang/lib/Basic/Targets/X86.cpp| 3 +++
clang/test/CodeGen/X86/avx512er-builtins.c | 2 +-
clang/test/CodeGen/X86/avx512pf-builtins.c | 2 +-
clang/test/Driver/cl-x86-flags.c | 10 --
clang/test/Frontend/x86-target-cpu.c | 10 --
clang/test/Misc/warning-flags.c| 3 ++-
7 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td
b/clang/include/clang/Basic/DiagnosticCommonKinds.td
index 65a33f61a6948a..40841e9df547bc 100644
--- a/clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -349,6 +349,8 @@ def warn_invalid_feature_combination : Warning<
def warn_target_unrecognized_env : Warning<
"mismatch between architecture and environment in target triple '%0'; did
you mean '%1'?">,
InGroup;
+def warn_knl_knm_target_supports_remove : Warning<
+ "KNL/KNM's feature support will be removed in LLVM 19.">;
// Source manager
def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index b97f88647fa49f..dc56524d378104 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -295,11 +295,13 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasAVX512BF16 = true;
} else if (Feature == "+avx512er") {
HasAVX512ER = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512fp16") {
HasAVX512FP16 = true;
HasLegalHalfType = true;
} else if (Feature == "+avx512pf") {
HasAVX512PF = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512dq") {
HasAVX512DQ = true;
} else if (Feature == "+avx512bitalg") {
@@ -358,6 +360,7 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasPREFETCHI = true;
} else if (Feature == "+prefetchwt1") {
HasPREFETCHWT1 = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+clzero") {
HasCLZERO = true;
} else if (Feature == "+cldemote") {
diff --git a/clang/test/CodeGen/X86/avx512er-builtins.c
b/clang/test/CodeGen/X86/avx512er-builtins.c
index ee31236a3c01aa..11ec6aabec1e3f 100644
--- a/clang/test/CodeGen/X86/avx512er-builtins.c
+++ b/clang/test/CodeGen/X86/avx512er-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall | FileCheck %s
#include
diff --git a/clang/test/CodeGen/X86/avx512pf-builtins.c
b/clang/test/CodeGen/X86/avx512pf-builtins.c
index 4ca70f5787968b..3a117ed6a9460e 100644
--- a/clang/test/CodeGen/X86/avx512pf-builtins.c
+++ b/clang/test/CodeGen/X86/avx512pf-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall
-Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall |
FileCheck %s
#include
diff --git a/clang/test/Driver/cl-x86-flags.c b/clang/test/Driver/cl-x86-flags.c
index 51b16f0ce35463..ae35a312fe8a4b 100644
--- a/clang/test/Driver/cl-x86-flags.c
+++ b/clang/test/Driver/cl-x86-flags.c
@@ -69,7 +69,10 @@
// RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s |
FileCheck -check-prefix=avx2 %s
// avx2: invalid /arch: argument
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify -DTEST_32_ARCH_AVX512F -- %s
+// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
#if defined(TEST_32_ARCH_AVX512F)
#if _M_IX86_FP !=
[clang] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
https://github.com/FreddyLeaf edited https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
FreddyLeaf wrote: > > @RKSimon @phoebewang Thanks comments! knm has AVX512_VPOPCNTDQ, I guess we > > also require it work without avx512vl? And we are going to keep > > -march/mtune/mcpu support for knl/knm, but removing some specific ISA's > > intrinsic and lowering supports? Did I get your point wrong? > > That's correct - we keep -march/mtune/mcpu support for knl/knm but reduce its > feature set to avx512f/avx512cd and we don't provide any support for xeon-phi > specific features (avx512pf etc.) apart from the minimal binutils/assembly > handling necessary. > > If we keep support for VPOPCNTDQ on knm then yes we will need to allow > non-VLX handling, but I don't know much about general availability of knm > workstations (knl cpus/machines do turn up on ebay etc. quite frequently). Thanks confirming! Modified the warning message and commit title. https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libcxx] [compiler-rt] [flang] [libc] [lldb] [clang] [clang-tools-extra] [llvm] [X86][BF16] Try to use `f16` for lowering (PR #76901)
@@ -22,10 +22,7 @@ define void @add(ptr %pa, ptr %pb, ptr %pc) nounwind {
; X86-NEXT:vaddss %xmm0, %xmm1, %xmm0
; X86-NEXT:vmovss %xmm0, (%esp)
; X86-NEXT:calll __truncsfbf2
-; X86-NEXT:fstps {{[0-9]+}}(%esp)
-; X86-NEXT:vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-NEXT:vmovd %xmm0, %eax
-; X86-NEXT:movw %ax, (%esi)
+; X86-NEXT:vmovsh %xmm0, (%esi)
FreddyLeaf wrote:
This change seems to will miss the truncate operation.
https://github.com/llvm/llvm-project/pull/76901
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[libc] [flang] [clang-tools-extra] [lldb] [llvm] [clang] [libcxx] [compiler-rt] [X86][BF16] Try to use `f16` for lowering (PR #76901)
@@ -22,10 +22,7 @@ define void @add(ptr %pa, ptr %pb, ptr %pc) nounwind {
; X86-NEXT:vaddss %xmm0, %xmm1, %xmm0
; X86-NEXT:vmovss %xmm0, (%esp)
; X86-NEXT:calll __truncsfbf2
-; X86-NEXT:fstps {{[0-9]+}}(%esp)
-; X86-NEXT:vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-NEXT:vmovd %xmm0, %eax
-; X86-NEXT:movw %ax, (%esi)
+; X86-NEXT:vmovsh %xmm0, (%esi)
FreddyLeaf wrote:
Sorry being not clear. I saw the original codes containing `; X86-NEXT: movw
%ax, (%esi)` seems like we are changing from a word store to a xmm store here.
https://github.com/llvm/llvm-project/pull/76901
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[clang] [flang] [compiler-rt] [clang-tools-extra] [libc] [libcxx] [lldb] [llvm] [X86][BF16] Try to use `f16` for lowering (PR #76901)
https://github.com/FreddyLeaf approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [compiler-rt] [clang-tools-extra] [libc] [libcxx] [lldb] [llvm] [X86][BF16] Try to use `f16` for lowering (PR #76901)
@@ -22,10 +22,7 @@ define void @add(ptr %pa, ptr %pb, ptr %pc) nounwind {
; X86-NEXT:vaddss %xmm0, %xmm1, %xmm0
; X86-NEXT:vmovss %xmm0, (%esp)
; X86-NEXT:calll __truncsfbf2
-; X86-NEXT:fstps {{[0-9]+}}(%esp)
-; X86-NEXT:vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X86-NEXT:vmovd %xmm0, %eax
-; X86-NEXT:movw %ax, (%esi)
+; X86-NEXT:vmovsh %xmm0, (%esi)
FreddyLeaf wrote:
Thanks for explaining.
https://github.com/llvm/llvm-project/pull/76901
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[clang] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
FreddyLeaf wrote: ping for review https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
@@ -69,7 +69,10 @@ // RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s | FileCheck -check-prefix=avx2 %s // avx2: invalid /arch: argument -// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj -Xclang -verify -DTEST_32_ARCH_AVX512F -- %s +// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj -Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s FreddyLeaf wrote: AVX512F will be handled as "knl" in driver https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
@@ -18,7 +18,7 @@ This test serves two purposes: The list of warnings below should NEVER grow. It should gradually shrink to 0. -CHECK: Warnings without flags (65): FreddyLeaf wrote: Emm, seems like increased six months ago: https://reviews.llvm.org/D154251. https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
@@ -18,7 +18,7 @@ This test serves two purposes: The list of warnings below should NEVER grow. It should gradually shrink to 0. -CHECK: Warnings without flags (65): FreddyLeaf wrote: Will fix https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
@@ -18,7 +18,7 @@ This test serves two purposes: The list of warnings below should NEVER grow. It should gradually shrink to 0. -CHECK: Warnings without flags (65): FreddyLeaf wrote: agree. Will add a warning group. sorry for misleading info above. https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/75580
>From e16afbdc9f0c04bad0e8f80f90c0eb26c13d3326 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 15 Dec 2023 16:50:23 +0800
Subject: [PATCH 1/7] [X86] Emit Warnings for frontend options to enable
knl/knm.
Since Knight Landing and Knight Mill microarchitectures are EOL, we
would like to remove its support in LLVM 19. In LLVM 18, we will first
emit a warning for the usage.
---
clang/include/clang/Basic/DiagnosticCommonKinds.td | 2 ++
clang/lib/Basic/Targets/X86.cpp| 3 +++
clang/test/CodeGen/X86/avx512er-builtins.c | 2 +-
clang/test/CodeGen/X86/avx512pf-builtins.c | 2 +-
clang/test/Driver/cl-x86-flags.c | 10 --
clang/test/Frontend/x86-target-cpu.c | 10 --
clang/test/Misc/warning-flags.c| 3 ++-
7 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td
b/clang/include/clang/Basic/DiagnosticCommonKinds.td
index 65a33f61a6948a..40841e9df547bc 100644
--- a/clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -349,6 +349,8 @@ def warn_invalid_feature_combination : Warning<
def warn_target_unrecognized_env : Warning<
"mismatch between architecture and environment in target triple '%0'; did
you mean '%1'?">,
InGroup;
+def warn_knl_knm_target_supports_remove : Warning<
+ "KNL/KNM's feature support will be removed in LLVM 19.">;
// Source manager
def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index b97f88647fa49f..dc56524d378104 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -295,11 +295,13 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasAVX512BF16 = true;
} else if (Feature == "+avx512er") {
HasAVX512ER = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512fp16") {
HasAVX512FP16 = true;
HasLegalHalfType = true;
} else if (Feature == "+avx512pf") {
HasAVX512PF = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512dq") {
HasAVX512DQ = true;
} else if (Feature == "+avx512bitalg") {
@@ -358,6 +360,7 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasPREFETCHI = true;
} else if (Feature == "+prefetchwt1") {
HasPREFETCHWT1 = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+clzero") {
HasCLZERO = true;
} else if (Feature == "+cldemote") {
diff --git a/clang/test/CodeGen/X86/avx512er-builtins.c
b/clang/test/CodeGen/X86/avx512er-builtins.c
index ee31236a3c01aa..11ec6aabec1e3f 100644
--- a/clang/test/CodeGen/X86/avx512er-builtins.c
+++ b/clang/test/CodeGen/X86/avx512er-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall | FileCheck %s
#include
diff --git a/clang/test/CodeGen/X86/avx512pf-builtins.c
b/clang/test/CodeGen/X86/avx512pf-builtins.c
index 4ca70f5787968b..3a117ed6a9460e 100644
--- a/clang/test/CodeGen/X86/avx512pf-builtins.c
+++ b/clang/test/CodeGen/X86/avx512pf-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall
-Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall |
FileCheck %s
#include
diff --git a/clang/test/Driver/cl-x86-flags.c b/clang/test/Driver/cl-x86-flags.c
index 51b16f0ce35463..ae35a312fe8a4b 100644
--- a/clang/test/Driver/cl-x86-flags.c
+++ b/clang/test/Driver/cl-x86-flags.c
@@ -69,7 +69,10 @@
// RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s |
FileCheck -check-prefix=avx2 %s
// avx2: invalid /arch: argument
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify -DTEST_32_ARCH_AVX512F -- %s
+// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
#if defined(TEST_32_ARCH_AVX512F)
#if _M_IX86_FP !=
[llvm] [clang] [clang-tools-extra] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/75580
>From e16afbdc9f0c04bad0e8f80f90c0eb26c13d3326 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 15 Dec 2023 16:50:23 +0800
Subject: [PATCH 1/7] [X86] Emit Warnings for frontend options to enable
knl/knm.
Since Knight Landing and Knight Mill microarchitectures are EOL, we
would like to remove its support in LLVM 19. In LLVM 18, we will first
emit a warning for the usage.
---
clang/include/clang/Basic/DiagnosticCommonKinds.td | 2 ++
clang/lib/Basic/Targets/X86.cpp| 3 +++
clang/test/CodeGen/X86/avx512er-builtins.c | 2 +-
clang/test/CodeGen/X86/avx512pf-builtins.c | 2 +-
clang/test/Driver/cl-x86-flags.c | 10 --
clang/test/Frontend/x86-target-cpu.c | 10 --
clang/test/Misc/warning-flags.c| 3 ++-
7 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td
b/clang/include/clang/Basic/DiagnosticCommonKinds.td
index 65a33f61a6948a..40841e9df547bc 100644
--- a/clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -349,6 +349,8 @@ def warn_invalid_feature_combination : Warning<
def warn_target_unrecognized_env : Warning<
"mismatch between architecture and environment in target triple '%0'; did
you mean '%1'?">,
InGroup;
+def warn_knl_knm_target_supports_remove : Warning<
+ "KNL/KNM's feature support will be removed in LLVM 19.">;
// Source manager
def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index b97f88647fa49f..dc56524d378104 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -295,11 +295,13 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasAVX512BF16 = true;
} else if (Feature == "+avx512er") {
HasAVX512ER = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512fp16") {
HasAVX512FP16 = true;
HasLegalHalfType = true;
} else if (Feature == "+avx512pf") {
HasAVX512PF = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512dq") {
HasAVX512DQ = true;
} else if (Feature == "+avx512bitalg") {
@@ -358,6 +360,7 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasPREFETCHI = true;
} else if (Feature == "+prefetchwt1") {
HasPREFETCHWT1 = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+clzero") {
HasCLZERO = true;
} else if (Feature == "+cldemote") {
diff --git a/clang/test/CodeGen/X86/avx512er-builtins.c
b/clang/test/CodeGen/X86/avx512er-builtins.c
index ee31236a3c01aa..11ec6aabec1e3f 100644
--- a/clang/test/CodeGen/X86/avx512er-builtins.c
+++ b/clang/test/CodeGen/X86/avx512er-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall | FileCheck %s
#include
diff --git a/clang/test/CodeGen/X86/avx512pf-builtins.c
b/clang/test/CodeGen/X86/avx512pf-builtins.c
index 4ca70f5787968b..3a117ed6a9460e 100644
--- a/clang/test/CodeGen/X86/avx512pf-builtins.c
+++ b/clang/test/CodeGen/X86/avx512pf-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall
-Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall |
FileCheck %s
#include
diff --git a/clang/test/Driver/cl-x86-flags.c b/clang/test/Driver/cl-x86-flags.c
index 51b16f0ce35463..ae35a312fe8a4b 100644
--- a/clang/test/Driver/cl-x86-flags.c
+++ b/clang/test/Driver/cl-x86-flags.c
@@ -69,7 +69,10 @@
// RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s |
FileCheck -check-prefix=avx2 %s
// avx2: invalid /arch: argument
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify -DTEST_32_ARCH_AVX512F -- %s
+// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
#if defined(TEST_32_ARCH_AVX512F)
#if _M_IX86_FP !=
[llvm] [clang-tools-extra] [clang] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
FreddyLeaf wrote: ping for review. https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang-tools-extra] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/75580
>From e16afbdc9f0c04bad0e8f80f90c0eb26c13d3326 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 15 Dec 2023 16:50:23 +0800
Subject: [PATCH 1/8] [X86] Emit Warnings for frontend options to enable
knl/knm.
Since Knight Landing and Knight Mill microarchitectures are EOL, we
would like to remove its support in LLVM 19. In LLVM 18, we will first
emit a warning for the usage.
---
clang/include/clang/Basic/DiagnosticCommonKinds.td | 2 ++
clang/lib/Basic/Targets/X86.cpp| 3 +++
clang/test/CodeGen/X86/avx512er-builtins.c | 2 +-
clang/test/CodeGen/X86/avx512pf-builtins.c | 2 +-
clang/test/Driver/cl-x86-flags.c | 10 --
clang/test/Frontend/x86-target-cpu.c | 10 --
clang/test/Misc/warning-flags.c| 3 ++-
7 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td
b/clang/include/clang/Basic/DiagnosticCommonKinds.td
index 65a33f61a6948a..40841e9df547bc 100644
--- a/clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -349,6 +349,8 @@ def warn_invalid_feature_combination : Warning<
def warn_target_unrecognized_env : Warning<
"mismatch between architecture and environment in target triple '%0'; did
you mean '%1'?">,
InGroup;
+def warn_knl_knm_target_supports_remove : Warning<
+ "KNL/KNM's feature support will be removed in LLVM 19.">;
// Source manager
def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index b97f88647fa49f..dc56524d378104 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -295,11 +295,13 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasAVX512BF16 = true;
} else if (Feature == "+avx512er") {
HasAVX512ER = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512fp16") {
HasAVX512FP16 = true;
HasLegalHalfType = true;
} else if (Feature == "+avx512pf") {
HasAVX512PF = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512dq") {
HasAVX512DQ = true;
} else if (Feature == "+avx512bitalg") {
@@ -358,6 +360,7 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasPREFETCHI = true;
} else if (Feature == "+prefetchwt1") {
HasPREFETCHWT1 = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+clzero") {
HasCLZERO = true;
} else if (Feature == "+cldemote") {
diff --git a/clang/test/CodeGen/X86/avx512er-builtins.c
b/clang/test/CodeGen/X86/avx512er-builtins.c
index ee31236a3c01aa..11ec6aabec1e3f 100644
--- a/clang/test/CodeGen/X86/avx512er-builtins.c
+++ b/clang/test/CodeGen/X86/avx512er-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall | FileCheck %s
#include
diff --git a/clang/test/CodeGen/X86/avx512pf-builtins.c
b/clang/test/CodeGen/X86/avx512pf-builtins.c
index 4ca70f5787968b..3a117ed6a9460e 100644
--- a/clang/test/CodeGen/X86/avx512pf-builtins.c
+++ b/clang/test/CodeGen/X86/avx512pf-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall
-Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall |
FileCheck %s
#include
diff --git a/clang/test/Driver/cl-x86-flags.c b/clang/test/Driver/cl-x86-flags.c
index 51b16f0ce35463..ae35a312fe8a4b 100644
--- a/clang/test/Driver/cl-x86-flags.c
+++ b/clang/test/Driver/cl-x86-flags.c
@@ -69,7 +69,10 @@
// RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s |
FileCheck -check-prefix=avx2 %s
// avx2: invalid /arch: argument
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify -DTEST_32_ARCH_AVX512F -- %s
+// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
#if defined(TEST_32_ARCH_AVX512F)
#if _M_IX86_FP !=
[llvm] [clang] [clang-tools-extra] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
@@ -933,6 +933,9 @@ X86 Support - Support ISA of ``AVX10.1``. - ``-march=pantherlake`` and ``-march=clearwaterforest`` are now supported. - Added ABI handling for ``__float128`` to match with GCC. +- Emit Warnings for clang options to enable knl/knm. From next version + (LLVM 19), all-end supports on knl/knm and other Xeon Phi targets will be + removed. FreddyLeaf wrote: addressed fef605e95d2ec8f5a3c2a339e014cb700d5b8a27 https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang-tools-extra] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
@@ -69,7 +69,10 @@ // RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s | FileCheck -check-prefix=avx2 %s // avx2: invalid /arch: argument -// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj -Xclang -verify -DTEST_32_ARCH_AVX512F -- %s +// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj -Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s FreddyLeaf wrote: https://github.com/llvm/llvm-project/blob/87d15d7ad6141d7492e9579928839408d60e8152/clang/lib/Driver/ToolChains/Arch/X86.cpp#L45 https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang-tools-extra] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/75580
>From e16afbdc9f0c04bad0e8f80f90c0eb26c13d3326 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 15 Dec 2023 16:50:23 +0800
Subject: [PATCH 1/9] [X86] Emit Warnings for frontend options to enable
knl/knm.
Since Knight Landing and Knight Mill microarchitectures are EOL, we
would like to remove its support in LLVM 19. In LLVM 18, we will first
emit a warning for the usage.
---
clang/include/clang/Basic/DiagnosticCommonKinds.td | 2 ++
clang/lib/Basic/Targets/X86.cpp| 3 +++
clang/test/CodeGen/X86/avx512er-builtins.c | 2 +-
clang/test/CodeGen/X86/avx512pf-builtins.c | 2 +-
clang/test/Driver/cl-x86-flags.c | 10 --
clang/test/Frontend/x86-target-cpu.c | 10 --
clang/test/Misc/warning-flags.c| 3 ++-
7 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td
b/clang/include/clang/Basic/DiagnosticCommonKinds.td
index 65a33f61a6948a..40841e9df547bc 100644
--- a/clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -349,6 +349,8 @@ def warn_invalid_feature_combination : Warning<
def warn_target_unrecognized_env : Warning<
"mismatch between architecture and environment in target triple '%0'; did
you mean '%1'?">,
InGroup;
+def warn_knl_knm_target_supports_remove : Warning<
+ "KNL/KNM's feature support will be removed in LLVM 19.">;
// Source manager
def err_cannot_open_file : Error<"cannot open file '%0': %1">, DefaultFatal;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index b97f88647fa49f..dc56524d378104 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -295,11 +295,13 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasAVX512BF16 = true;
} else if (Feature == "+avx512er") {
HasAVX512ER = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512fp16") {
HasAVX512FP16 = true;
HasLegalHalfType = true;
} else if (Feature == "+avx512pf") {
HasAVX512PF = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+avx512dq") {
HasAVX512DQ = true;
} else if (Feature == "+avx512bitalg") {
@@ -358,6 +360,7 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasPREFETCHI = true;
} else if (Feature == "+prefetchwt1") {
HasPREFETCHWT1 = true;
+ Diags.Report(diag::warn_knl_knm_target_supports_remove);
} else if (Feature == "+clzero") {
HasCLZERO = true;
} else if (Feature == "+cldemote") {
diff --git a/clang/test/CodeGen/X86/avx512er-builtins.c
b/clang/test/CodeGen/X86/avx512er-builtins.c
index ee31236a3c01aa..11ec6aabec1e3f 100644
--- a/clang/test/CodeGen/X86/avx512er-builtins.c
+++ b/clang/test/CodeGen/X86/avx512er-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512f -target-feature +avx512er
-emit-llvm -o - -Wall | FileCheck %s
#include
diff --git a/clang/test/CodeGen/X86/avx512pf-builtins.c
b/clang/test/CodeGen/X86/avx512pf-builtins.c
index 4ca70f5787968b..3a117ed6a9460e 100644
--- a/clang/test/CodeGen/X86/avx512pf-builtins.c
+++ b/clang/test/CodeGen/X86/avx512pf-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall
-Werror | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s
-triple=x86_64-apple-darwin -target-feature +avx512pf -emit-llvm -o - -Wall |
FileCheck %s
#include
diff --git a/clang/test/Driver/cl-x86-flags.c b/clang/test/Driver/cl-x86-flags.c
index 51b16f0ce35463..ae35a312fe8a4b 100644
--- a/clang/test/Driver/cl-x86-flags.c
+++ b/clang/test/Driver/cl-x86-flags.c
@@ -69,7 +69,10 @@
// RUN: %clang_cl -m32 -arch:avx2 --target=i386-pc-windows -### -- 2>&1 %s |
FileCheck -check-prefix=avx2 %s
// avx2: invalid /arch: argument
-// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify -DTEST_32_ARCH_AVX512F -- %s
+// RUN: %clang_cl -m32 -arch:AVX512F --target=i386-pc-windows /c /Fo%t.obj
-Xclang -verify=KNL1 -DTEST_32_ARCH_AVX512F -- %s
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
+// KNL1-warning@*:* {{KNL/KNM's feature support will be removed in LLVM 19.}}
#if defined(TEST_32_ARCH_AVX512F)
#if _M_IX86_FP !=
[llvm] [clang] [clang-tools-extra] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
https://github.com/FreddyLeaf edited https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [clang] [llvm] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
https://github.com/FreddyLeaf edited https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [clang] [llvm] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
FreddyLeaf wrote: Thank you all! https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [clang] [llvm] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
https://github.com/FreddyLeaf closed https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers][X86] Reformat ia32intrin.h doc to match the other headers (PR #77525)
https://github.com/FreddyLeaf approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/77525 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 5871298 - [NFC][X86] add missing tests in clang/test/CodeGen/attr-target-mv.c
Author: Freddy Ye
Date: 2021-07-29T13:28:10+08:00
New Revision: 58712987e56fb598ac49da7fbe6e6a78c787637b
URL:
https://github.com/llvm/llvm-project/commit/58712987e56fb598ac49da7fbe6e6a78c787637b
DIFF:
https://github.com/llvm/llvm-project/commit/58712987e56fb598ac49da7fbe6e6a78c787637b.diff
LOG: [NFC][X86] add missing tests in clang/test/CodeGen/attr-target-mv.c
Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D106849
Added:
Modified:
clang/test/CodeGen/attr-target-mv.c
Removed:
diff --git a/clang/test/CodeGen/attr-target-mv.c
b/clang/test/CodeGen/attr-target-mv.c
index a01cef58ffa83..9fa3e3b5f415e 100644
--- a/clang/test/CodeGen/attr-target-mv.c
+++ b/clang/test/CodeGen/attr-target-mv.c
@@ -129,6 +129,16 @@ void calls_pr50025c() { pr50025c(); }
// WINDOWS: ret i32 6
// WINDOWS: define dso_local i32 @foo.arch_icelake-server()
// WINDOWS: ret i32 7
+// WINDOWS: define dso_local i32 @foo.arch_cooperlake()
+// WINDOWS: ret i32 8
+// WINDOWS: define dso_local i32 @foo.arch_tigerlake()
+// WINDOWS: ret i32 9
+// WINDOWS: define dso_local i32 @foo.arch_sapphirerapids()
+// WINDOWS: ret i32 10
+// WINDOWS: define dso_local i32 @foo.arch_alderlake()
+// WINDOWS: ret i32 11
+// WINDOWS: define dso_local i32 @foo.arch_rocketlake()
+// WINDOWS: ret i32 12
// WINDOWS: define dso_local i32 @foo()
// WINDOWS: ret i32 2
// WINDOWS: define dso_local i32 @bar()
___
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[clang] [X86] Add missing MACROs in cpuid.h (PR #80815)
https://github.com/FreddyLeaf edited https://github.com/llvm/llvm-project/pull/80815 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Add missing MACROs in cpuid.h (PR #80815)
FreddyLeaf wrote: > Past the link of GCC files in description? Done. https://github.com/llvm/llvm-project/pull/80815 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Add missing MACROs in cpuid.h (PR #80815)
https://github.com/FreddyLeaf updated https://github.com/llvm/llvm-project/pull/80815 >From 2ed2333085d40ece903b2d70e0da7371b72209f4 Mon Sep 17 00:00:00 2001 From: Freddy Ye Date: Tue, 6 Feb 2024 17:20:31 +0800 Subject: [PATCH 1/2] [X86] Add missing MACROs in cpuid.h --- clang/lib/Headers/cpuid.h | 9 + 1 file changed, 9 insertions(+) diff --git a/clang/lib/Headers/cpuid.h b/clang/lib/Headers/cpuid.h index 1ad6853a97c9d2..1f3e28a3bfa61b 100644 --- a/clang/lib/Headers/cpuid.h +++ b/clang/lib/Headers/cpuid.h @@ -200,6 +200,9 @@ #define bit_AMXINT8 0x0200 /* Features in %eax for leaf 7 sub-leaf 1 */ +#define bit_SHA5120x0001 +#define bit_SM3 0x0002 +#define bit_SM4 0x0004 #define bit_RAOINT0x0008 #define bit_AVXVNNI 0x0010 #define bit_AVX512BF160x0020 @@ -211,7 +214,11 @@ /* Features in %edx for leaf 7 sub-leaf 1 */ #define bit_AVXVNNIINT8 0x0010 #define bit_AVXNECONVERT 0x0020 +#define bit_AMXCOMPLEX0x0100 +#define bit_AVXVNNIINT16 0x0400 #define bit_PREFETCHI 0x4000 +#define bit_USERMSR 0x8000 +#define bit_AVX10_256 0x0008 /* Features in %eax for leaf 13 sub-leaf 1 */ #define bit_XSAVEOPT0x0001 @@ -244,6 +251,8 @@ #define bit_RDPRU 0x0010 #define bit_WBNOINVD0x0200 +/* Features in %ebx for leaf 0x24 */ +#define bit_AVX10_512 0x0004 #if __i386__ #define __cpuid(__leaf, __eax, __ebx, __ecx, __edx) \ >From fd0c860aab3c78505222c281419a366a36104e37 Mon Sep 17 00:00:00 2001 From: Freddy Ye Date: Wed, 7 Feb 2024 10:42:40 +0800 Subject: [PATCH 2/2] address comment --- clang/lib/Headers/cpuid.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/clang/lib/Headers/cpuid.h b/clang/lib/Headers/cpuid.h index 1f3e28a3bfa61b..c968d37fb8cd64 100644 --- a/clang/lib/Headers/cpuid.h +++ b/clang/lib/Headers/cpuid.h @@ -218,7 +218,7 @@ #define bit_AVXVNNIINT16 0x0400 #define bit_PREFETCHI 0x4000 #define bit_USERMSR 0x8000 -#define bit_AVX10_256 0x0008 +#define bit_AVX10 0x0008 /* Features in %eax for leaf 13 sub-leaf 1 */ #define bit_XSAVEOPT0x0001 @@ -252,6 +252,7 @@ #define bit_WBNOINVD0x0200 /* Features in %ebx for leaf 0x24 */ +#define bit_AVX10_256 0x0002 #define bit_AVX10_512 0x0004 #if __i386__ ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Add missing MACROs in cpuid.h (PR #80815)
@@ -211,7 +214,11 @@ /* Features in %edx for leaf 7 sub-leaf 1 */ #define bit_AVXVNNIINT8 0x0010 #define bit_AVXNECONVERT 0x0020 +#define bit_AMXCOMPLEX0x0100 +#define bit_AVXVNNIINT16 0x0400 #define bit_PREFETCHI 0x4000 +#define bit_USERMSR 0x8000 +#define bit_AVX10_256 0x0008 FreddyLeaf wrote: I see. Aligned with gcc: [fd0c860](https://github.com/llvm/llvm-project/pull/80815/commits/fd0c860aab3c78505222c281419a366a36104e37) https://github.com/llvm/llvm-project/pull/80815 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
FreddyLeaf wrote: ping for review https://github.com/llvm/llvm-project/pull/80636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+ Features["apxf"] = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);
FreddyLeaf wrote:
This patch defined one in clang through
llvm/include/llvm/TargetParser/X86TargetParser.def. I think it's ok to do so.
https://github.com/llvm/llvm-project/pull/80636
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[clang] [X86] Add missing MACROs in cpuid.h (PR #80815)
FreddyLeaf wrote: Thanks review! https://github.com/llvm/llvm-project/pull/80815 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Add missing MACROs in cpuid.h (PR #80815)
https://github.com/FreddyLeaf closed https://github.com/llvm/llvm-project/pull/80815 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/80636
>From b131b0971d5c38a29c954b37c0da8fb3177e5c92 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Mon, 5 Feb 2024 14:07:29 +0800
Subject: [PATCH 1/3] [X86] Support APXF to enable __builtin_cpu_supports.
---
clang/test/CodeGen/target-builtin-noerror.c| 1 +
compiler-rt/lib/builtins/cpu_model/x86.c | 4 +++-
llvm/include/llvm/TargetParser/X86TargetParser.def | 3 ++-
llvm/lib/TargetParser/Host.cpp | 1 +
llvm/lib/TargetParser/X86TargetParser.cpp | 1 +
5 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/clang/test/CodeGen/target-builtin-noerror.c
b/clang/test/CodeGen/target-builtin-noerror.c
index 9608b5f37baaae..b438e50848a4b6 100644
--- a/clang/test/CodeGen/target-builtin-noerror.c
+++ b/clang/test/CodeGen/target-builtin-noerror.c
@@ -141,6 +141,7 @@ void verifyfeaturestrings(void) {
(void)__builtin_cpu_supports("sm3");
(void)__builtin_cpu_supports("sha512");
(void)__builtin_cpu_supports("sm4");
+ (void)__builtin_cpu_supports("apxf");
(void)__builtin_cpu_supports("usermsr");
(void)__builtin_cpu_supports("avx10.1-256");
(void)__builtin_cpu_supports("avx10.1-512");
diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c
b/compiler-rt/lib/builtins/cpu_model/x86.c
index 1afa468c4ae8c1..35375c6e8d55b6 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -217,7 +217,7 @@ enum ProcessorFeatures {
FEATURE_SM3,
FEATURE_SHA512,
FEATURE_SM4,
- // FEATURE_APXF,
+ FEATURE_APXF,
FEATURE_USERMSR = 112,
FEATURE_AVX10_1_256,
FEATURE_AVX10_1_512,
@@ -983,6 +983,8 @@ static void getAvailableFeatures(unsigned ECX, unsigned
EDX, unsigned MaxLeaf,
setFeature(FEATURE_USERMSR);
if (HasLeaf7Subleaf1 && ((EDX >> 19) & 1))
setFeature(FEATURE_AVX10_1_256);
+ if (HasLeaf7Subleaf1 && ((EDX >> 21) & 1))
+setFeature(FEATURE_APXF);
unsigned MaxLevel;
getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX);
diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def
b/llvm/include/llvm/TargetParser/X86TargetParser.def
index 4c630c1eb06e8c..ec52062a2baacf 100644
--- a/llvm/include/llvm/TargetParser/X86TargetParser.def
+++ b/llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -248,10 +248,11 @@ X86_FEATURE_COMPAT(AVXVNNIINT16,"avxvnniint16",
0)
X86_FEATURE_COMPAT(SM3, "sm3",0)
X86_FEATURE_COMPAT(SHA512, "sha512", 0)
X86_FEATURE_COMPAT(SM4, "sm4",0)
-X86_FEATURE (EGPR,"egpr")
+X86_FEATURE_COMPAT(APXF,"apxf", 0)
X86_FEATURE_COMPAT(USERMSR, "usermsr",0)
X86_FEATURE_COMPAT(AVX10_1, "avx10.1-256",0)
X86_FEATURE_COMPAT(AVX10_1_512, "avx10.1-512",0)
+X86_FEATURE (EGPR,"egpr")
X86_FEATURE (EVEX512, "evex512")
X86_FEATURE (CF, "cf")
// These features aren't really CPU features, but the frontend can set them.
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index f1197c29655380..233ee12a000962 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+ Features["apxf"] = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);
bool HasLeafD = MaxLevel >= 0xd &&
!getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp
b/llvm/lib/TargetParser/X86TargetParser.cpp
index 21f46f576490a8..ea1f8517bb3329 100644
--- a/llvm/lib/TargetParser/X86TargetParser.cpp
+++ b/llvm/lib/TargetParser/X86TargetParser.cpp
@@ -633,6 +633,7 @@ constexpr FeatureBitset ImpliedFeaturesPPX = {};
constexpr FeatureBitset ImpliedFeaturesNDD = {};
constexpr FeatureBitset ImpliedFeaturesCCMP = {};
constexpr FeatureBitset ImpliedFeaturesCF = {};
+constexpr FeatureBitset ImpliedFeaturesAPXF = {};
constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
#define X86_FEATURE(ENUM, STR) {{"+" STR}, ImpliedFeatures##ENUM},
>From a1ecdf5fe54cb03045748e3d49f23e24e9428973 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Tue, 6 Feb 2024 17:19:28 +0800
Subject: [PATCH 2/3] misc
---
compiler-rt/lib/builtins/cpu_model/x86.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c
b/compiler-rt/lib/builtins/cpu_model/x86.c
index 35375c6e8d55b6..7e8acb3e73eda9 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -218,7 +218,7 @@ enum ProcessorFeatures {
FEATURE_SHA512,
FEATU
[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+ Features["apxf"] = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);
FreddyLeaf wrote:
> My understanding is "apxf" here is used by front-end for FMV, right?
Yes, not only FMV, but also __builtin_cpu_supports.
> What would happen if there is "apxf" in the IR after this patch?
if llc read "apxf" in attribute, I think a warning will be given like:
```
'+apxf' is not a recognized feature for this target (ignoring feature)
```
But such attribute won't be generated from frontend, because we didn't add
logics for "apxf" in X86TargetInfo::hasFeature.
https://github.com/llvm/llvm-project/pull/80636
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[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+ Features["apxf"] = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);
FreddyLeaf wrote:
Emm, I happened to find an issue with this patch.
```
$ clang -march=native foo.c -S -emit-llvm
'-apxf' is not a recognized feature for this target (ignoring feature)
```
It turns out even not adding logics in X86TargetInfo::hasFeature it will still
return false for "apxf". I also found "-egpr" is not generated. How did you
handle this?
https://github.com/llvm/llvm-project/pull/80636
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[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+ Features["apxf"] = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);
FreddyLeaf wrote:
Yeah, that's another problem. For attribute/target, it seems more reasonable to
enable as "egpr" instead of "apxf" because apx needs such fine-grained
enabling. We need to discuss with gcc on this.
https://github.com/llvm/llvm-project/pull/80636
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[clang] [X86] Change target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2 (PR #84136)
https://github.com/FreddyLeaf created https://github.com/llvm/llvm-project/pull/84136 - [X86] Change target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2 - Handle attribute/target >From 2ba698b222fa1dc963d21850d5931562aa65533d Mon Sep 17 00:00:00 2001 From: Freddy Ye Date: Tue, 26 Sep 2023 16:44:01 +0800 Subject: [PATCH 1/2] [X86] Change target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2 --- clang/include/clang/Basic/BuiltinsX86.def | 8 +- clang/lib/Headers/avxintrin.h | 247 -- clang/lib/Headers/emmintrin.h | 121 + clang/lib/Headers/xmmintrin.h | 128 + clang/test/CodeGen/X86/avx-builtins.c | 96 --- .../test/CodeGen/X86/cmp-avx-builtins-error.c | 22 ++ clang/test/CodeGen/X86/sse-builtins.c | 54 clang/test/CodeGen/X86/sse2-builtins.c| 54 clang/test/CodeGen/target-features-error-2.c | 4 +- 9 files changed, 385 insertions(+), 349 deletions(-) create mode 100644 clang/test/CodeGen/X86/cmp-avx-builtins-error.c diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def index 207cde0414b54e..eafcc219c10966 100644 --- a/clang/include/clang/Basic/BuiltinsX86.def +++ b/clang/include/clang/Basic/BuiltinsX86.def @@ -226,6 +226,8 @@ TARGET_BUILTIN(__builtin_ia32_minps, "V4fV4fV4f", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_maxps, "V4fV4fV4f", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_minss, "V4fV4fV4f", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_maxss, "V4fV4fV4f", "ncV:128:", "sse") +TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "sse") +TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_cmpeqpd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpltpd, "V2dV2dV2d", "ncV:128:", "sse2") @@ -243,6 +245,8 @@ TARGET_BUILTIN(__builtin_ia32_cmpneqsd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpnltsd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpnlesd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpordsd, "V2dV2dV2d", "ncV:128:", "sse2") +TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "sse2") +TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_minpd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_maxpd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_minsd, "V2dV2dV2d", "ncV:128:", "sse2") @@ -462,12 +466,8 @@ TARGET_BUILTIN(__builtin_ia32_blendvps256, "V8fV8fV8fV8f", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufpd256, "V4dV4dV4dIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufps256, "V8fV8fV8fIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_dpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "avx") TARGET_BUILTIN(__builtin_ia32_cmppd256, "V4dV4dV4dIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "avx") TARGET_BUILTIN(__builtin_ia32_cmpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "avx") TARGET_BUILTIN(__builtin_ia32_vextractf128_pd256, "V2dV4dIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vextractf128_ps256, "V4fV8fIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vextractf128_si256, "V4iV8iIi", "ncV:256:", "avx") diff --git a/clang/lib/Headers/avxintrin.h b/clang/lib/Headers/avxintrin.h index f116d8bc3a94c7..d6192518ea24ba 100644 --- a/clang/lib/Headers/avxintrin.h +++ b/clang/lib/Headers/avxintrin.h @@ -1573,15 +1573,6 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) ((__m256d)__builtin_ia32_shufpd256((__v4df)(__m256d)(a), \ (__v4df)(__m256d)(b), (int)(mask))) -/* Compare */ -#define _CMP_EQ_OQ0x00 /* Equal (ordered, non-signaling) */ -#define _CMP_LT_OS0x01 /* Less-than (ordered, signaling) */ -#define _CMP_LE_OS0x02 /* Less-than-or-equal (ordered, signaling) */ -#define _CMP_UNORD_Q 0x03 /* Unordered (non-signaling) */ -#define _CMP_NEQ_UQ 0x04 /* Not-equal (unordered, non-signaling) */ -#define _CMP_NLT_US 0x05 /* Not-less-than (unordered, signaling) */ -#define _CMP_NLE_US 0x06 /* Not-less-than-or-equal (unordered, signaling) */ -#define _CMP_ORD_Q0x07 /* Ordered (non-signaling) */ #define _CMP_EQ_UQ0x08 /* Equal (unordered, non-signaling) */ #define _CMP_NGE_US 0x09 /* Not-greater-than-or-equal (unordered, signaling) */ #define _CMP_NGT_US 0x0a /* Not-greater-than (unordered, signaling) */ @@ -1607,126 +1598,6 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) #define _CMP_GT_OQ0x1e /* Greater-than (ordered, non-signaling) */ #define _CMP_TRUE_US 0x1f /* True (un
[clang] [X86] Change target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2 (PR #84136)
https://github.com/FreddyLeaf edited https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Change target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2 (PR #84136)
@@ -15,7 +15,7 @@ int baz(__m256i a) {
#if NEED_AVX_2
__m128 need_avx(__m128 a, __m128 b) {
- return _mm_cmp_ps(a, b, 0); // expected-error {{'__builtin_ia32_cmpps' needs
target feature avx}}
+ return _mm_cmp_ps(a, b, 8); // expected-error {{'__builtin_ia32_cmpps' needs
target feature avx}}
FreddyLeaf wrote:
@phoebewang @RKSimon @KanRobert
This change shows the behavior of compiling these intrinsics with parameter of
[8,31] after this PR.
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Change target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2 (PR #84136)
FreddyLeaf wrote: The difference with #67410 is here: 54c78b5ad694946186ba115576a6eea9c8992349 https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
https://github.com/FreddyLeaf edited https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -462,12 +462,12 @@ TARGET_BUILTIN(__builtin_ia32_blendvps256, "V8fV8fV8fV8f", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufpd256, "V4dV4dV4dIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufps256, "V8fV8fV8fIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_dpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "avx") +TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "avx|sse2") TARGET_BUILTIN(__builtin_ia32_cmppd256, "V4dV4dV4dIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "avx") +TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "avx|sse") TARGET_BUILTIN(__builtin_ia32_cmpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "avx") +TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "avx|sse2") +TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "avx|sse") FreddyLeaf wrote: Good catch. No strong objections. https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -462,12 +462,12 @@ TARGET_BUILTIN(__builtin_ia32_blendvps256, "V8fV8fV8fV8f", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufpd256, "V4dV4dV4dIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufps256, "V8fV8fV8fIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_dpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "avx") +TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "avx|sse2") TARGET_BUILTIN(__builtin_ia32_cmppd256, "V4dV4dV4dIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "avx") +TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "avx|sse") TARGET_BUILTIN(__builtin_ia32_cmpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "avx") +TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "avx|sse2") +TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "avx|sse") FreddyLeaf wrote: Good catch. No strong objections. https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
FreddyLeaf wrote: > My understanding is that you change the required feature of > __builtin_ia32_cmp[p|s][s|d] from avx to sse for some condition codes. The > title is not accurate. You are right. Updated. https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because they have different
+ // parameter ranges with different TargetAttribute of caller.
FreddyLeaf wrote:
Semachecking doesn't have the information of the caller of the intrinsic. While
here we require to know if caller has "avx" or not when the condition code is
[8, 31].
Considering such case:
```
#include
__attribute__((target("sse2")))
__m128 test1(__m128 a, __m128 b) {
return _mm_cmp_ps(a, b, 14); // shouldn't report error.
}
__attribute__((target("avx")))
__m128 test2(__m128 a, __m128 b) {
return _mm_cmp_ps(a, b, 14); // should report error.
}
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
https://github.com/FreddyLeaf edited https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
https://github.com/FreddyLeaf updated https://github.com/llvm/llvm-project/pull/84136 >From 2ba698b222fa1dc963d21850d5931562aa65533d Mon Sep 17 00:00:00 2001 From: Freddy Ye Date: Tue, 26 Sep 2023 16:44:01 +0800 Subject: [PATCH 1/3] [X86] Change target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2 --- clang/include/clang/Basic/BuiltinsX86.def | 8 +- clang/lib/Headers/avxintrin.h | 247 -- clang/lib/Headers/emmintrin.h | 121 + clang/lib/Headers/xmmintrin.h | 128 + clang/test/CodeGen/X86/avx-builtins.c | 96 --- .../test/CodeGen/X86/cmp-avx-builtins-error.c | 22 ++ clang/test/CodeGen/X86/sse-builtins.c | 54 clang/test/CodeGen/X86/sse2-builtins.c| 54 clang/test/CodeGen/target-features-error-2.c | 4 +- 9 files changed, 385 insertions(+), 349 deletions(-) create mode 100644 clang/test/CodeGen/X86/cmp-avx-builtins-error.c diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def index 207cde0414b54e..eafcc219c10966 100644 --- a/clang/include/clang/Basic/BuiltinsX86.def +++ b/clang/include/clang/Basic/BuiltinsX86.def @@ -226,6 +226,8 @@ TARGET_BUILTIN(__builtin_ia32_minps, "V4fV4fV4f", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_maxps, "V4fV4fV4f", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_minss, "V4fV4fV4f", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_maxss, "V4fV4fV4f", "ncV:128:", "sse") +TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "sse") +TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_cmpeqpd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpltpd, "V2dV2dV2d", "ncV:128:", "sse2") @@ -243,6 +245,8 @@ TARGET_BUILTIN(__builtin_ia32_cmpneqsd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpnltsd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpnlesd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpordsd, "V2dV2dV2d", "ncV:128:", "sse2") +TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "sse2") +TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_minpd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_maxpd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_minsd, "V2dV2dV2d", "ncV:128:", "sse2") @@ -462,12 +466,8 @@ TARGET_BUILTIN(__builtin_ia32_blendvps256, "V8fV8fV8fV8f", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufpd256, "V4dV4dV4dIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufps256, "V8fV8fV8fIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_dpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "avx") TARGET_BUILTIN(__builtin_ia32_cmppd256, "V4dV4dV4dIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "avx") TARGET_BUILTIN(__builtin_ia32_cmpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "avx") TARGET_BUILTIN(__builtin_ia32_vextractf128_pd256, "V2dV4dIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vextractf128_ps256, "V4fV8fIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vextractf128_si256, "V4iV8iIi", "ncV:256:", "avx") diff --git a/clang/lib/Headers/avxintrin.h b/clang/lib/Headers/avxintrin.h index f116d8bc3a94c7..d6192518ea24ba 100644 --- a/clang/lib/Headers/avxintrin.h +++ b/clang/lib/Headers/avxintrin.h @@ -1573,15 +1573,6 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) ((__m256d)__builtin_ia32_shufpd256((__v4df)(__m256d)(a), \ (__v4df)(__m256d)(b), (int)(mask))) -/* Compare */ -#define _CMP_EQ_OQ0x00 /* Equal (ordered, non-signaling) */ -#define _CMP_LT_OS0x01 /* Less-than (ordered, signaling) */ -#define _CMP_LE_OS0x02 /* Less-than-or-equal (ordered, signaling) */ -#define _CMP_UNORD_Q 0x03 /* Unordered (non-signaling) */ -#define _CMP_NEQ_UQ 0x04 /* Not-equal (unordered, non-signaling) */ -#define _CMP_NLT_US 0x05 /* Not-less-than (unordered, signaling) */ -#define _CMP_NLE_US 0x06 /* Not-less-than-or-equal (unordered, signaling) */ -#define _CMP_ORD_Q0x07 /* Ordered (non-signaling) */ #define _CMP_EQ_UQ0x08 /* Equal (unordered, non-signaling) */ #define _CMP_NGE_US 0x09 /* Not-greater-than-or-equal (unordered, signaling) */ #define _CMP_NGT_US 0x0a /* Not-greater-than (unordered, signaling) */ @@ -1607,126 +1598,6 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) #define _CMP_GT_OQ0x1e /* Greater-than (ordered, non-signaling) */ #define _CMP_TRUE_US 0x1f /* True (unordered, signaling) */ -/// Compares each of the corresponding double-precision values of two -///
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because they have different
+ // parameter ranges with different TargetAttribute of caller.
FreddyLeaf wrote:
[d8979e2](https://github.com/llvm/llvm-project/pull/84136/commits/d8979e29e1932b42bb54424e1c6aa97ba9ba07e7)
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
https://github.com/FreddyLeaf deleted https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because they have different
+ // parameter ranges with different TargetAttribute of caller.
FreddyLeaf wrote:
[d8979e2](https://github.com/llvm/llvm-project/pull/84136/commits/d8979e29e1932b42bb54424e1c6aa97ba9ba07e7)
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
https://github.com/FreddyLeaf deleted https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -1719,3 +1719,57 @@ __m128i test_mm_xor_si128(__m128i A, __m128i B) {
// CHECK: xor <2 x i64> %{{.*}}, %{{.*}}
return _mm_xor_si128(A, B);
}
+
+__m128d test_mm_cmp_pd_eq_oq(__m128d a, __m128d b) {
FreddyLeaf wrote:
[d8979e2](https://github.com/llvm/llvm-project/pull/84136/commits/d8979e29e1932b42bb54424e1c6aa97ba9ba07e7)
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -462,12 +462,12 @@ TARGET_BUILTIN(__builtin_ia32_blendvps256, "V8fV8fV8fV8f", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufpd256, "V4dV4dV4dIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufps256, "V8fV8fV8fIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_dpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "avx") +TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "avx|sse2") TARGET_BUILTIN(__builtin_ia32_cmppd256, "V4dV4dV4dIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "avx") +TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "avx|sse") TARGET_BUILTIN(__builtin_ia32_cmpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "avx") +TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "avx|sse2") +TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "avx|sse") FreddyLeaf wrote: [d8979e2](https://github.com/llvm/llvm-project/pull/84136/commits/d8979e29e1932b42bb54424e1c6aa97ba9ba07e7) https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -34,6 +34,60 @@ __m128 test_mm_andnot_ps(__m128 A, __m128 B) {
return _mm_andnot_ps(A, B);
}
+__m128 test_mm_cmp_ps_eq_oq(__m128 a, __m128 b) {
+ // CHECK-LABEL: test_mm_cmp_ps_eq_oq
+ // CHECK: fcmp oeq <4 x float> %{{.*}}, %{{.*}}
+ return _mm_cmp_ps(a, b, _CMP_EQ_OQ);
FreddyLeaf wrote:
These condition codes are [0,7], so they won't throw errors. What about adding
8 more tests to avx-builtins.c with condition codes of [8,15]?
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because they have different
+ // parameter ranges with different TargetAttribute of caller.
FreddyLeaf wrote:
because SDM defined so?
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -34,6 +34,60 @@ __m128 test_mm_andnot_ps(__m128 A, __m128 B) {
return _mm_andnot_ps(A, B);
}
+__m128 test_mm_cmp_ps_eq_oq(__m128 a, __m128 b) {
+ // CHECK-LABEL: test_mm_cmp_ps_eq_oq
+ // CHECK: fcmp oeq <4 x float> %{{.*}}, %{{.*}}
+ return _mm_cmp_ps(a, b, _CMP_EQ_OQ);
FreddyLeaf wrote:
Oh the remaining 24 are already there. So I only moved the first 8 from avx to
sse/sse2. which is expected.
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
https://github.com/FreddyLeaf updated https://github.com/llvm/llvm-project/pull/84136 >From 2ba698b222fa1dc963d21850d5931562aa65533d Mon Sep 17 00:00:00 2001 From: Freddy Ye Date: Tue, 26 Sep 2023 16:44:01 +0800 Subject: [PATCH 1/5] [X86] Change target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2 --- clang/include/clang/Basic/BuiltinsX86.def | 8 +- clang/lib/Headers/avxintrin.h | 247 -- clang/lib/Headers/emmintrin.h | 121 + clang/lib/Headers/xmmintrin.h | 128 + clang/test/CodeGen/X86/avx-builtins.c | 96 --- .../test/CodeGen/X86/cmp-avx-builtins-error.c | 22 ++ clang/test/CodeGen/X86/sse-builtins.c | 54 clang/test/CodeGen/X86/sse2-builtins.c| 54 clang/test/CodeGen/target-features-error-2.c | 4 +- 9 files changed, 385 insertions(+), 349 deletions(-) create mode 100644 clang/test/CodeGen/X86/cmp-avx-builtins-error.c diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def index 207cde0414b54e..eafcc219c10966 100644 --- a/clang/include/clang/Basic/BuiltinsX86.def +++ b/clang/include/clang/Basic/BuiltinsX86.def @@ -226,6 +226,8 @@ TARGET_BUILTIN(__builtin_ia32_minps, "V4fV4fV4f", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_maxps, "V4fV4fV4f", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_minss, "V4fV4fV4f", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_maxss, "V4fV4fV4f", "ncV:128:", "sse") +TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "sse") +TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_cmpeqpd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpltpd, "V2dV2dV2d", "ncV:128:", "sse2") @@ -243,6 +245,8 @@ TARGET_BUILTIN(__builtin_ia32_cmpneqsd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpnltsd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpnlesd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpordsd, "V2dV2dV2d", "ncV:128:", "sse2") +TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "sse2") +TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_minpd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_maxpd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_minsd, "V2dV2dV2d", "ncV:128:", "sse2") @@ -462,12 +466,8 @@ TARGET_BUILTIN(__builtin_ia32_blendvps256, "V8fV8fV8fV8f", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufpd256, "V4dV4dV4dIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufps256, "V8fV8fV8fIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_dpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "avx") TARGET_BUILTIN(__builtin_ia32_cmppd256, "V4dV4dV4dIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "avx") TARGET_BUILTIN(__builtin_ia32_cmpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "avx") TARGET_BUILTIN(__builtin_ia32_vextractf128_pd256, "V2dV4dIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vextractf128_ps256, "V4fV8fIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vextractf128_si256, "V4iV8iIi", "ncV:256:", "avx") diff --git a/clang/lib/Headers/avxintrin.h b/clang/lib/Headers/avxintrin.h index f116d8bc3a94c7..d6192518ea24ba 100644 --- a/clang/lib/Headers/avxintrin.h +++ b/clang/lib/Headers/avxintrin.h @@ -1573,15 +1573,6 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) ((__m256d)__builtin_ia32_shufpd256((__v4df)(__m256d)(a), \ (__v4df)(__m256d)(b), (int)(mask))) -/* Compare */ -#define _CMP_EQ_OQ0x00 /* Equal (ordered, non-signaling) */ -#define _CMP_LT_OS0x01 /* Less-than (ordered, signaling) */ -#define _CMP_LE_OS0x02 /* Less-than-or-equal (ordered, signaling) */ -#define _CMP_UNORD_Q 0x03 /* Unordered (non-signaling) */ -#define _CMP_NEQ_UQ 0x04 /* Not-equal (unordered, non-signaling) */ -#define _CMP_NLT_US 0x05 /* Not-less-than (unordered, signaling) */ -#define _CMP_NLE_US 0x06 /* Not-less-than-or-equal (unordered, signaling) */ -#define _CMP_ORD_Q0x07 /* Ordered (non-signaling) */ #define _CMP_EQ_UQ0x08 /* Equal (unordered, non-signaling) */ #define _CMP_NGE_US 0x09 /* Not-greater-than-or-equal (unordered, signaling) */ #define _CMP_NGT_US 0x0a /* Not-greater-than (unordered, signaling) */ @@ -1607,126 +1598,6 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) #define _CMP_GT_OQ0x1e /* Greater-than (ordered, non-signaling) */ #define _CMP_TRUE_US 0x1f /* True (unordered, signaling) */ -/// Compares each of the corresponding double-precision values of two -///
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -2940,6 +2940,134 @@ _mm_movemask_ps(__m128 __a) return __builtin_ia32_movmskps((__v4sf)__a); } +/* Compare */ +#define _CMP_EQ_OQ0x00 /* Equal (ordered, non-signaling) */ +#define _CMP_LT_OS0x01 /* Less-than (ordered, signaling) */ +#define _CMP_LE_OS0x02 /* Less-than-or-equal (ordered, signaling) */ +#define _CMP_UNORD_Q 0x03 /* Unordered (non-signaling) */ +#define _CMP_NEQ_UQ 0x04 /* Not-equal (unordered, non-signaling) */ +#define _CMP_NLT_US 0x05 /* Not-less-than (unordered, signaling) */ +#define _CMP_NLE_US 0x06 /* Not-less-than-or-equal (unordered, signaling) */ +#define _CMP_ORD_Q0x07 /* Ordered (non-signaling) */ + +/// Compares each of the corresponding values of two 128-bit vectors of +///[4 x float], using the operation specified by the immediate integer +///operand. +/// +///Returns a [4 x float] vector consisting of four floats corresponding to +///the four comparison results: zero if the comparison is false, and all 1's +///if the comparison is true. +/// +/// \headerfile +/// +/// \code +/// __m128 _mm_cmp_ps(__m128 a, __m128 b, const int c); +/// \endcode +/// +/// This intrinsic corresponds to the (V)CMPPS instruction. +/// +/// \param a +///A 128-bit vector of [4 x float]. +/// \param b +///A 128-bit vector of [4 x float]. +/// \param c +///An immediate integer operand, with bits [4:0] specifying which comparison +///operation to use: \n +///(Note that without avx enabled, only bits [2:0] are supported) \n +///0x00: Equal (ordered, non-signaling) \n +///0x01: Less-than (ordered, signaling) \n +///0x02: Less-than-or-equal (ordered, signaling) \n +///0x03: Unordered (non-signaling) \n +///0x04: Not-equal (unordered, non-signaling) \n +///0x05: Not-less-than (unordered, signaling) \n +///0x06: Not-less-than-or-equal (unordered, signaling) \n +///0x07: Ordered (non-signaling) \n +///0x08: Equal (unordered, non-signaling) \n +///0x09: Not-greater-than-or-equal (unordered, signaling) \n +///0x0A: Not-greater-than (unordered, signaling) \n +///0x0B: False (ordered, non-signaling) \n +///0x0C: Not-equal (ordered, non-signaling) \n +///0x0D: Greater-than-or-equal (ordered, signaling) \n +///0x0E: Greater-than (ordered, signaling) \n +///0x0F: True (unordered, non-signaling) \n +///0x10: Equal (ordered, signaling) \n +///0x11: Less-than (ordered, non-signaling) \n +///0x12: Less-than-or-equal (ordered, non-signaling) \n +///0x13: Unordered (signaling) \n +///0x14: Not-equal (unordered, signaling) \n +///0x15: Not-less-than (unordered, non-signaling) \n +///0x16: Not-less-than-or-equal (unordered, non-signaling) \n +///0x17: Ordered (signaling) \n +///0x18: Equal (unordered, signaling) \n +///0x19: Not-greater-than-or-equal (unordered, non-signaling) \n +///0x1A: Not-greater-than (unordered, non-signaling) \n +///0x1B: False (ordered, signaling) \n +///0x1C: Not-equal (ordered, signaling) \n +///0x1D: Greater-than-or-equal (ordered, non-signaling) \n +///0x1E: Greater-than (ordered, non-signaling) \n +///0x1F: True (unordered, signaling) FreddyLeaf wrote: Refined in 51eda069c797c91fd3072f347e1dd4a20ab53702 https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -4745,6 +4745,127 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_castsi128_pd(__m128i __a) {
return (__m128d)__a;
}
+/// Compares each of the corresponding double-precision values of two
+///128-bit vectors of [2 x double], using the operation specified by the
+///immediate integer operand.
+///
+///Returns a [2 x double] vector consisting of two doubles corresponding to
+///the two comparison results: zero if the comparison is false, and all 1's
+///if the comparison is true.
+///
+/// \headerfile
+///
+/// \code
+/// __m128d _mm_cmp_pd(__m128d a, __m128d b, const int c);
+/// \endcode
+///
+/// This intrinsic corresponds to the (V)CMPPD instruction.
+///
+/// \param a
+///A 128-bit vector of [2 x double].
+/// \param b
+///A 128-bit vector of [2 x double].
+/// \param c
+///An immediate integer operand, with bits [4:0] specifying which
comparison
FreddyLeaf wrote:
Refined in 51eda069c797c91fd3072f347e1dd4a20ab53702
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
https://github.com/FreddyLeaf edited https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because they have different
+ // parameter ranges with different TargetAttribute of caller.
FreddyLeaf wrote:
Updated in description.
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
FreddyLeaf wrote: > Still not understand. Shouldn't the target feature of the caller be passed to > the intrinsic when checking the argument of the intrinsic? The target features passing from option can be passed to Semachecking. It's special for attribute_target, which is handled in `handleTargetAttr`, which is after Sema::CheckBuiltinFunctionCall. https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
FreddyLeaf wrote: > > > Still not understand. Shouldn't the target feature of the caller be > > > passed to the intrinsic when checking the argument of the intrinsic? > > > > > > The target features passing from option can be passed to Semachecking. It's > > special for attribute_target, which is handled in `handleTargetAttr`, which > > is after Sema::CheckBuiltinFunctionCall. > > Then why not move the call `handleTargetAttr` before > `Sema::CheckBuiltinFunctionCall`? Mainly because all Sema::CheckBuiltinFunctionCall before doesn't dependent on target feature, right? We don't have any other builtins have different range limit of same const parameter. But clang::CodegenFunction has the information of the whole function, which I think is a more reasonable place to do the check. https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finally handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
FreddyLeaf wrote: ping for review https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finally handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
https://github.com/FreddyLeaf updated https://github.com/llvm/llvm-project/pull/84136 >From 2ba698b222fa1dc963d21850d5931562aa65533d Mon Sep 17 00:00:00 2001 From: Freddy Ye Date: Tue, 26 Sep 2023 16:44:01 +0800 Subject: [PATCH 1/6] [X86] Change target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2 --- clang/include/clang/Basic/BuiltinsX86.def | 8 +- clang/lib/Headers/avxintrin.h | 247 -- clang/lib/Headers/emmintrin.h | 121 + clang/lib/Headers/xmmintrin.h | 128 + clang/test/CodeGen/X86/avx-builtins.c | 96 --- .../test/CodeGen/X86/cmp-avx-builtins-error.c | 22 ++ clang/test/CodeGen/X86/sse-builtins.c | 54 clang/test/CodeGen/X86/sse2-builtins.c| 54 clang/test/CodeGen/target-features-error-2.c | 4 +- 9 files changed, 385 insertions(+), 349 deletions(-) create mode 100644 clang/test/CodeGen/X86/cmp-avx-builtins-error.c diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def index 207cde0414b54e..eafcc219c10966 100644 --- a/clang/include/clang/Basic/BuiltinsX86.def +++ b/clang/include/clang/Basic/BuiltinsX86.def @@ -226,6 +226,8 @@ TARGET_BUILTIN(__builtin_ia32_minps, "V4fV4fV4f", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_maxps, "V4fV4fV4f", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_minss, "V4fV4fV4f", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_maxss, "V4fV4fV4f", "ncV:128:", "sse") +TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "sse") +TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "sse") TARGET_BUILTIN(__builtin_ia32_cmpeqpd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpltpd, "V2dV2dV2d", "ncV:128:", "sse2") @@ -243,6 +245,8 @@ TARGET_BUILTIN(__builtin_ia32_cmpneqsd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpnltsd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpnlesd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_cmpordsd, "V2dV2dV2d", "ncV:128:", "sse2") +TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "sse2") +TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_minpd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_maxpd, "V2dV2dV2d", "ncV:128:", "sse2") TARGET_BUILTIN(__builtin_ia32_minsd, "V2dV2dV2d", "ncV:128:", "sse2") @@ -462,12 +466,8 @@ TARGET_BUILTIN(__builtin_ia32_blendvps256, "V8fV8fV8fV8f", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufpd256, "V4dV4dV4dIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufps256, "V8fV8fV8fIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_dpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "avx") TARGET_BUILTIN(__builtin_ia32_cmppd256, "V4dV4dV4dIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "avx") TARGET_BUILTIN(__builtin_ia32_cmpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "avx") TARGET_BUILTIN(__builtin_ia32_vextractf128_pd256, "V2dV4dIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vextractf128_ps256, "V4fV8fIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vextractf128_si256, "V4iV8iIi", "ncV:256:", "avx") diff --git a/clang/lib/Headers/avxintrin.h b/clang/lib/Headers/avxintrin.h index f116d8bc3a94c7..d6192518ea24ba 100644 --- a/clang/lib/Headers/avxintrin.h +++ b/clang/lib/Headers/avxintrin.h @@ -1573,15 +1573,6 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) ((__m256d)__builtin_ia32_shufpd256((__v4df)(__m256d)(a), \ (__v4df)(__m256d)(b), (int)(mask))) -/* Compare */ -#define _CMP_EQ_OQ0x00 /* Equal (ordered, non-signaling) */ -#define _CMP_LT_OS0x01 /* Less-than (ordered, signaling) */ -#define _CMP_LE_OS0x02 /* Less-than-or-equal (ordered, signaling) */ -#define _CMP_UNORD_Q 0x03 /* Unordered (non-signaling) */ -#define _CMP_NEQ_UQ 0x04 /* Not-equal (unordered, non-signaling) */ -#define _CMP_NLT_US 0x05 /* Not-less-than (unordered, signaling) */ -#define _CMP_NLE_US 0x06 /* Not-less-than-or-equal (unordered, signaling) */ -#define _CMP_ORD_Q0x07 /* Ordered (non-signaling) */ #define _CMP_EQ_UQ0x08 /* Equal (unordered, non-signaling) */ #define _CMP_NGE_US 0x09 /* Not-greater-than-or-equal (unordered, signaling) */ #define _CMP_NGT_US 0x0a /* Not-greater-than (unordered, signaling) */ @@ -1607,126 +1598,6 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) #define _CMP_GT_OQ0x1e /* Greater-than (ordered, non-signaling) */ #define _CMP_TRUE_US 0x1f /* True (unordered, signaling) */ -/// Compares each of the corresponding double-precision values of two -///
[clang] [X86] Finally handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -2940,6 +2940,84 @@ _mm_movemask_ps(__m128 __a) return __builtin_ia32_movmskps((__v4sf)__a); } +/* Compare */ +#define _CMP_EQ_OQ0x00 /* Equal (ordered, non-signaling) */ +#define _CMP_LT_OS0x01 /* Less-than (ordered, signaling) */ +#define _CMP_LE_OS0x02 /* Less-than-or-equal (ordered, signaling) */ +#define _CMP_UNORD_Q 0x03 /* Unordered (non-signaling) */ +#define _CMP_NEQ_UQ 0x04 /* Not-equal (unordered, non-signaling) */ +#define _CMP_NLT_US 0x05 /* Not-less-than (unordered, signaling) */ +#define _CMP_NLE_US 0x06 /* Not-less-than-or-equal (unordered, signaling) */ +#define _CMP_ORD_Q0x07 /* Ordered (non-signaling) */ + +/// Compares each of the corresponding values of two 128-bit vectors of +///[4 x float], using the operation specified by the immediate integer +///operand. +/// +///Returns a [4 x float] vector consisting of four floats corresponding to +///the four comparison results: zero if the comparison is false, and all 1's +///if the comparison is true. +/// +/// \headerfile +/// +/// \code +/// __m128 _mm_cmp_ps(__m128 a, __m128 b, const int c); +/// \endcode +/// +/// This intrinsic corresponds to the (V)CMPPS instruction. +/// +/// \param a +///A 128-bit vector of [4 x float]. +/// \param b +///A 128-bit vector of [4 x float]. +/// \param c +///An immediate integer operand, with bits [4:0] specifying which comparison +///operation to use: \n +///0x00: Equal (ordered, non-signaling) \n +///0x01: Less-than (ordered, signaling) \n +///0x02: Less-than-or-equal (ordered, signaling) \n +///0x03: Unordered (non-signaling) \n +///0x04: Not-equal (unordered, non-signaling) \n +///0x05: Not-less-than (unordered, signaling) \n +///0x06: Not-less-than-or-equal (unordered, signaling) \n +///0x07: Ordered (non-signaling) \n +/// \returns A 128-bit vector of [4 x float] containing the comparison results. +#define _mm_cmp_ps(a, b, c) \ + ((__m128)__builtin_ia32_cmpps((__v4sf)(__m128)(a), (__v4sf)(__m128)(b), (c))) + +/// Compares each of the corresponding scalar values of two 128-bit +///vectors of [4 x float], using the operation specified by the immediate +///integer operand. +/// +///If the result is true, all 32 bits of the destination vector are set; +///otherwise they are cleared. FreddyLeaf wrote: 71641346ebadf8d21a109813fcf66f78e0932955 https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finally handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -2940,6 +2940,84 @@ _mm_movemask_ps(__m128 __a) return __builtin_ia32_movmskps((__v4sf)__a); } +/* Compare */ +#define _CMP_EQ_OQ0x00 /* Equal (ordered, non-signaling) */ +#define _CMP_LT_OS0x01 /* Less-than (ordered, signaling) */ +#define _CMP_LE_OS0x02 /* Less-than-or-equal (ordered, signaling) */ +#define _CMP_UNORD_Q 0x03 /* Unordered (non-signaling) */ +#define _CMP_NEQ_UQ 0x04 /* Not-equal (unordered, non-signaling) */ +#define _CMP_NLT_US 0x05 /* Not-less-than (unordered, signaling) */ +#define _CMP_NLE_US 0x06 /* Not-less-than-or-equal (unordered, signaling) */ +#define _CMP_ORD_Q0x07 /* Ordered (non-signaling) */ + +/// Compares each of the corresponding values of two 128-bit vectors of +///[4 x float], using the operation specified by the immediate integer +///operand. +/// +///Returns a [4 x float] vector consisting of four floats corresponding to +///the four comparison results: zero if the comparison is false, and all 1's +///if the comparison is true. FreddyLeaf wrote: 71641346ebadf8d21a109813fcf66f78e0932955 https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finally handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -4745,6 +4745,77 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_castsi128_pd(__m128i __a) {
return (__m128d)__a;
}
+/// Compares each of the corresponding double-precision values of two
+///128-bit vectors of [2 x double], using the operation specified by the
+///immediate integer operand.
+///
+///Returns a [2 x double] vector consisting of two doubles corresponding to
+///the two comparison results: zero if the comparison is false, and all 1's
+///if the comparison is true.
+///
+/// \headerfile
+///
+/// \code
+/// __m128d _mm_cmp_pd(__m128d a, __m128d b, const int c);
+/// \endcode
+///
+/// This intrinsic corresponds to the (V)CMPPD instruction.
+///
+/// \param a
+///A 128-bit vector of [2 x double].
+/// \param b
+///A 128-bit vector of [2 x double].
+/// \param c
+///An immediate integer operand, with bits [4:0] specifying which
comparison
+///operation to use: \n
+///0x00: Equal (ordered, non-signaling) \n
+///0x01: Less-than (ordered, signaling) \n
+///0x02: Less-than-or-equal (ordered, signaling) \n
+///0x03: Unordered (non-signaling) \n
+///0x04: Not-equal (unordered, non-signaling) \n
+///0x05: Not-less-than (unordered, signaling) \n
+///0x06: Not-less-than-or-equal (unordered, signaling) \n
+///0x07: Ordered (non-signaling) \n
+/// \returns A 128-bit vector of [2 x double] containing the comparison
results.
+#define _mm_cmp_pd(a, b, c)
\
+ ((__m128d)__builtin_ia32_cmppd((__v2df)(__m128d)(a), (__v2df)(__m128d)(b),
\
+ (c)))
+
+/// Compares each of the corresponding scalar double-precision values of
+///two 128-bit vectors of [2 x double], using the operation specified by
the
+///immediate integer operand.
+///
+///If the result is true, all 64 bits of the destination vector are set;
+///otherwise they are cleared.
FreddyLeaf wrote:
71641346ebadf8d21a109813fcf66f78e0932955
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finally handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -4745,6 +4745,77 @@ static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_castsi128_pd(__m128i __a) {
return (__m128d)__a;
}
+/// Compares each of the corresponding double-precision values of two
+///128-bit vectors of [2 x double], using the operation specified by the
+///immediate integer operand.
+///
+///Returns a [2 x double] vector consisting of two doubles corresponding to
+///the two comparison results: zero if the comparison is false, and all 1's
+///if the comparison is true.
FreddyLeaf wrote:
71641346ebadf8d21a109813fcf66f78e0932955
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finally handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
FreddyLeaf wrote: > Thanks for the heads-up @RKSimon I've made suggestions for consistency with > existing practice in emmintrin.h which I've adopted in the latest revision to > #83316. > > I'm unsure how replacing a function declaration with an \fn directive will > play with our documentation tooling. But we can figure that out later. I've committed your suggestions. FYI \fn usage was referring https://github.com/llvm/llvm-project/blob/c58c8278f98c189d149d5f062b8d4f56efcada90/clang/lib/Headers/avxvnniintrin.h#L32 https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finally handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
https://github.com/FreddyLeaf closed https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[compiler-rt] [clang] [llvm] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)
FreddyLeaf wrote: ping for review https://github.com/llvm/llvm-project/pull/79086 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[compiler-rt] [clang] [llvm] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)
@@ -139,20 +139,77 @@ enum ProcessorFeatures {
FEATURE_AVX512BITALG,
FEATURE_AVX512BF16,
FEATURE_AVX512VP2INTERSECT,
+ FEATURE_3DNOW,
+ FEATURE_ADX = 40,
+ FEATURE_CLDEMOTE = 42,
FreddyLeaf wrote:
The missing features are ones I can't recognize in
https://github.com/gcc-mirror/gcc/blob/02948ced062b730e2859f718dd46bfcaa3c16c6b/gcc/common/config/i386/i386-cpuinfo.h#L154,
e.g. FEATURE_ABM, I can't find relate one in LLVM.
https://github.com/llvm/llvm-project/pull/79086
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[clang] [llvm] [compiler-rt] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)
https://github.com/FreddyLeaf updated
https://github.com/llvm/llvm-project/pull/79086
>From b5c8579c5c8e7ea1e8436348bbf60ecee9c3c799 Mon Sep 17 00:00:00 2001
From: Freddy Ye
Date: Fri, 19 Jan 2024 09:22:27 +0800
Subject: [PATCH 1/5] [X86] Support more ISAs to enable __builtin_cpu_supports
This patch will also expand supports for attribute/target, while
the priority of newly supported ISAs will be set to zero.
---
clang/test/CodeGen/target-builtin-noerror.c | 59 +
compiler-rt/lib/builtins/cpu_model/x86.c | 209 +-
.../llvm/TargetParser/X86TargetParser.def | 135 ++-
3 files changed, 324 insertions(+), 79 deletions(-)
diff --git a/clang/test/CodeGen/target-builtin-noerror.c
b/clang/test/CodeGen/target-builtin-noerror.c
index 06bb40a2b71ea..16097fa08cb9c 100644
--- a/clang/test/CodeGen/target-builtin-noerror.c
+++ b/clang/test/CodeGen/target-builtin-noerror.c
@@ -84,6 +84,65 @@ void verifyfeaturestrings(void) {
(void)__builtin_cpu_supports("avx512vp2intersect");
(void)__builtin_cpu_supports("f16c");
(void)__builtin_cpu_supports("avx512fp16");
+ (void)__builtin_cpu_supports("3dnow");
+ (void)__builtin_cpu_supports("adx");
+ (void)__builtin_cpu_supports("cldemote");
+ (void)__builtin_cpu_supports("clflushopt");
+ (void)__builtin_cpu_supports("clwb");
+ (void)__builtin_cpu_supports("clzero");
+ (void)__builtin_cpu_supports("cx16");
+ (void)__builtin_cpu_supports("cx8");
+ (void)__builtin_cpu_supports("enqcmd");
+ (void)__builtin_cpu_supports("fsgsbase");
+ (void)__builtin_cpu_supports("lwp");
+ (void)__builtin_cpu_supports("lzcnt");
+ (void)__builtin_cpu_supports("movbe");
+ (void)__builtin_cpu_supports("movdir64b");
+ (void)__builtin_cpu_supports("movdiri");
+ (void)__builtin_cpu_supports("mwaitx");
+ (void)__builtin_cpu_supports("pconfig");
+ (void)__builtin_cpu_supports("pku");
+ (void)__builtin_cpu_supports("prefetchwt1");
+ (void)__builtin_cpu_supports("prfchw");
+ (void)__builtin_cpu_supports("ptwrite");
+ (void)__builtin_cpu_supports("rdpid");
+ (void)__builtin_cpu_supports("rdrnd");
+ (void)__builtin_cpu_supports("rdseed");
+ (void)__builtin_cpu_supports("rtm");
+ (void)__builtin_cpu_supports("serialize");
+ (void)__builtin_cpu_supports("sgx");
+ (void)__builtin_cpu_supports("sha");
+ (void)__builtin_cpu_supports("shstk");
+ (void)__builtin_cpu_supports("tbm");
+ (void)__builtin_cpu_supports("tsxldtrk");
+ (void)__builtin_cpu_supports("vaes");
+ (void)__builtin_cpu_supports("waitpkg");
+ (void)__builtin_cpu_supports("wbnoinvd");
+ (void)__builtin_cpu_supports("xsave");
+ (void)__builtin_cpu_supports("xsavec");
+ (void)__builtin_cpu_supports("xsaveopt");
+ (void)__builtin_cpu_supports("xsaves");
+ (void)__builtin_cpu_supports("amx-tile");
+ (void)__builtin_cpu_supports("amx-int8");
+ (void)__builtin_cpu_supports("amx-bf16");
+ (void)__builtin_cpu_supports("uintr");
+ (void)__builtin_cpu_supports("hreset");
+ (void)__builtin_cpu_supports("kl");
+ (void)__builtin_cpu_supports("widekl");
+ (void)__builtin_cpu_supports("avxvnni");
+ (void)__builtin_cpu_supports("avxifma");
+ (void)__builtin_cpu_supports("avxvnniint8");
+ (void)__builtin_cpu_supports("avxneconvert");
+ (void)__builtin_cpu_supports("cmpccxadd");
+ (void)__builtin_cpu_supports("amx-fp16");
+ (void)__builtin_cpu_supports("prefetchi");
+ (void)__builtin_cpu_supports("raoint");
+ (void)__builtin_cpu_supports("amx-complex");
+ (void)__builtin_cpu_supports("avxvnniint16");
+ (void)__builtin_cpu_supports("sm3");
+ (void)__builtin_cpu_supports("sha512");
+ (void)__builtin_cpu_supports("sm4");
+ (void)__builtin_cpu_supports("usermsr");
}
void verifycpustrings(void) {
diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c
b/compiler-rt/lib/builtins/cpu_model/x86.c
index 0750e29f989a8..c499754890343 100644
--- a/compiler-rt/lib/builtins/cpu_model/x86.c
+++ b/compiler-rt/lib/builtins/cpu_model/x86.c
@@ -139,20 +139,77 @@ enum ProcessorFeatures {
FEATURE_AVX512BITALG,
FEATURE_AVX512BF16,
FEATURE_AVX512VP2INTERSECT,
+ FEATURE_3DNOW,
+ FEATURE_ADX = 40,
+ FEATURE_CLDEMOTE = 42,
+ FEATURE_CLFLUSHOPT,
+ FEATURE_CLWB,
+ FEATURE_CLZERO,
+ FEATURE_CMPXCHG16B,
+ FEATURE_CMPXCHG8B,
+ FEATURE_ENQCMD,
+ FEATURE_F16C,
+ FEATURE_FSGSBASE,
- FEATURE_CMPXCHG16B = 46,
- FEATURE_F16C = 49,
FEATURE_LAHF_LM = 54,
FEATURE_LM,
- FEATURE_WP,
+ FEATURE_LWP,
FEATURE_LZCNT,
FEATURE_MOVBE,
-
- FEATURE_AVX512FP16 = 94,
+ FEATURE_MOVDIR64B,
+ FEATURE_MOVDIRI,
+ FEATURE_MWAITX,
+
+ FEATURE_PCONFIG = 63,
+ FEATURE_PKU,
+ FEATURE_PREFETCHWT1,
+ FEATURE_PRFCHW,
+ FEATURE_PTWRITE,
+ FEATURE_RDPID,
+ FEATURE_RDRND,
+ FEATURE_RDSEED,
+ FEATURE_RTM,
+ FEATURE_SERIALIZE,
+ FEATURE_SGX,
+ FEATURE_SHA,
+ FEATURE_SHSTK,
+ FEATURE_TBM,
+ FEATURE_TSXLDTRK,
+ FEATURE_VAES,
+ FEATURE_WAITPKG,
+ FEATURE_WBNOINVD,
+ FEATURE_XSAVE,
+ FEATURE_XSAVEC,
+ FEATURE_XSAVEOPT,
+ FEATURE_XSAVES,
+ FEATURE_AMX_TILE,
+ FEATURE_AMX
[clang] [llvm] [compiler-rt] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)
@@ -139,20 +139,77 @@ enum ProcessorFeatures {
FEATURE_AVX512BITALG,
FEATURE_AVX512BF16,
FEATURE_AVX512VP2INTERSECT,
+ FEATURE_3DNOW,
+ FEATURE_ADX = 40,
+ FEATURE_CLDEMOTE = 42,
FreddyLeaf wrote:
agree, done in 10c2a7c
https://github.com/llvm/llvm-project/pull/79086
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[compiler-rt] [llvm] [clang] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)
FreddyLeaf wrote: ping for review https://github.com/llvm/llvm-project/pull/79086 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [polly] [X86] Remove Intel Xeon Phi Supports. (PR #76383)
https://github.com/FreddyLeaf closed https://github.com/llvm/llvm-project/pull/76383 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
