[PATCH] D37057: [clang] Require address space to be specified when creating functions (3/3)

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 136051.
dylanmckay added a comment.

Gentle rebase


Repository:
  rC Clang

https://reviews.llvm.org/D37057

Files:
  lib/CodeGen/CGBlocks.cpp
  lib/CodeGen/CGBuiltin.cpp
  lib/CodeGen/CGCUDANV.cpp
  lib/CodeGen/CGDeclCXX.cpp
  lib/CodeGen/CGException.cpp
  lib/CodeGen/CGExpr.cpp
  lib/CodeGen/CGGPUBuiltin.cpp
  lib/CodeGen/CGObjC.cpp
  lib/CodeGen/CGObjCGNU.cpp
  lib/CodeGen/CGObjCMac.cpp
  lib/CodeGen/CGOpenMPRuntime.cpp
  lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp
  lib/CodeGen/CGStmt.cpp
  lib/CodeGen/CGStmtOpenMP.cpp
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/ItaniumCXXABI.cpp
  lib/CodeGen/MicrosoftCXXABI.cpp
  lib/CodeGen/TargetInfo.cpp

Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -9137,7 +9137,7 @@
   std::string Name = Invoke->getName().str() + "_kernel";
   auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
   auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
-   &CGF.CGM.getModule());
+   CGF.CGM.getModule());
   auto IP = CGF.Builder.saveIP();
   auto *BB = llvm::BasicBlock::Create(C, "entry", F);
   auto &Builder = CGF.Builder;
@@ -9195,7 +9195,7 @@
   std::string Name = Invoke->getName().str() + "_kernel";
   auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
   auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
-   &CGF.CGM.getModule());
+   CGF.CGM.getModule());
   F->addFnAttr("enqueued-block");
   auto IP = CGF.Builder.saveIP();
   auto *BB = llvm::BasicBlock::Create(C, "entry", F);
Index: lib/CodeGen/MicrosoftCXXABI.cpp
===
--- lib/CodeGen/MicrosoftCXXABI.cpp
+++ lib/CodeGen/MicrosoftCXXABI.cpp
@@ -1950,7 +1950,7 @@
   llvm::FunctionType *ThunkTy = CGM.getTypes().GetFunctionType(FnInfo);
   llvm::Function *ThunkFn =
   llvm::Function::Create(ThunkTy, llvm::Function::ExternalLinkage,
- ThunkName.str(), &CGM.getModule());
+ ThunkName.str(), CGM.getModule());
   assert(ThunkFn->getName() == ThunkName && "name was uniqued!");
 
   ThunkFn->setLinkage(MD->isExternallyVisible()
@@ -3878,7 +3878,7 @@
   const CXXRecordDecl *RD = CD->getParent();
   QualType RecordTy = getContext().getRecordType(RD);
   llvm::Function *ThunkFn = llvm::Function::Create(
-  ThunkTy, getLinkageForRTTI(RecordTy), ThunkName.str(), &CGM.getModule());
+  ThunkTy, getLinkageForRTTI(RecordTy), ThunkName.str(), CGM.getModule());
   ThunkFn->setCallingConv(static_cast(
   FnInfo.getEffectiveCallingConvention()));
   if (ThunkFn->isWeakForLinker())
Index: lib/CodeGen/ItaniumCXXABI.cpp
===
--- lib/CodeGen/ItaniumCXXABI.cpp
+++ lib/CodeGen/ItaniumCXXABI.cpp
@@ -2298,7 +2298,7 @@
   llvm::FunctionType *FnTy = CGM.getTypes().GetFunctionType(FI);
   llvm::Function *Wrapper =
   llvm::Function::Create(FnTy, getThreadLocalWrapperLinkage(VD, CGM),
- WrapperName.str(), &CGM.getModule());
+ WrapperName.str(), CGM.getModule());
 
   CGM.SetLLVMFunctionAttributes(nullptr, FI, Wrapper);
 
@@ -2405,7 +2405,7 @@
   llvm::FunctionType *FnTy = llvm::FunctionType::get(CGM.VoidTy, false);
   Init = llvm::Function::Create(FnTy,
 llvm::GlobalVariable::ExternalWeakLinkage,
-InitFnName.str(), &CGM.getModule());
+InitFnName.str(), CGM.getModule());
   const CGFunctionInfo &FI = CGM.getTypes().arrangeNullaryFunction();
   CGM.SetLLVMFunctionAttributes(nullptr, FI, cast(Init));
 }
Index: lib/CodeGen/CodeGenModule.cpp
===
--- lib/CodeGen/CodeGenModule.cpp
+++ lib/CodeGen/CodeGenModule.cpp
@@ -2447,7 +2447,7 @@
 
   llvm::Function *F =
   llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, &getModule());
+ Entry ? StringRef() : MangledName, getModule());
 
   // If we already created a function with the same mangled name (but different
   // type) before, take its name and add it to the list of functions to be
Index: lib/CodeGen/CGStmtOpenMP.cpp
===
--- lib/CodeGen/CGStmtOpenMP.cpp
+++ lib/CodeGen/CGStmtOpenMP.cpp
@@ -454,7 +454,7 @@
 
   llvm::Function *F =
   llvm::Function::Create(FuncLLVMTy, llvm::GlobalValue::InternalLinkage,
- FO.FunctionName, &CGM.getModule());
+ FO.FunctionName, CGM.

[PATCH] D37057: [clang] Require address space to be specified when creating functions (3/3)

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 136734.
dylanmckay added a comment.

Rebase


Repository:
  rC Clang

https://reviews.llvm.org/D37057

Files:
  lib/CodeGen/CGBlocks.cpp
  lib/CodeGen/CGBuiltin.cpp
  lib/CodeGen/CGCUDANV.cpp
  lib/CodeGen/CGDeclCXX.cpp
  lib/CodeGen/CGException.cpp
  lib/CodeGen/CGExpr.cpp
  lib/CodeGen/CGGPUBuiltin.cpp
  lib/CodeGen/CGNonTrivialStruct.cpp
  lib/CodeGen/CGObjC.cpp
  lib/CodeGen/CGObjCGNU.cpp
  lib/CodeGen/CGObjCMac.cpp
  lib/CodeGen/CGOpenMPRuntime.cpp
  lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp
  lib/CodeGen/CGStmt.cpp
  lib/CodeGen/CGStmtOpenMP.cpp
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/ItaniumCXXABI.cpp
  lib/CodeGen/MicrosoftCXXABI.cpp
  lib/CodeGen/TargetInfo.cpp

Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -9137,7 +9137,7 @@
   std::string Name = Invoke->getName().str() + "_kernel";
   auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
   auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
-   &CGF.CGM.getModule());
+   CGF.CGM.getModule());
   auto IP = CGF.Builder.saveIP();
   auto *BB = llvm::BasicBlock::Create(C, "entry", F);
   auto &Builder = CGF.Builder;
@@ -9195,7 +9195,7 @@
   std::string Name = Invoke->getName().str() + "_kernel";
   auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
   auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
-   &CGF.CGM.getModule());
+   CGF.CGM.getModule());
   F->addFnAttr("enqueued-block");
   auto IP = CGF.Builder.saveIP();
   auto *BB = llvm::BasicBlock::Create(C, "entry", F);
Index: lib/CodeGen/MicrosoftCXXABI.cpp
===
--- lib/CodeGen/MicrosoftCXXABI.cpp
+++ lib/CodeGen/MicrosoftCXXABI.cpp
@@ -1948,7 +1948,7 @@
   llvm::FunctionType *ThunkTy = CGM.getTypes().GetFunctionType(FnInfo);
   llvm::Function *ThunkFn =
   llvm::Function::Create(ThunkTy, llvm::Function::ExternalLinkage,
- ThunkName.str(), &CGM.getModule());
+ ThunkName.str(), CGM.getModule());
   assert(ThunkFn->getName() == ThunkName && "name was uniqued!");
 
   ThunkFn->setLinkage(MD->isExternallyVisible()
@@ -3876,7 +3876,7 @@
   const CXXRecordDecl *RD = CD->getParent();
   QualType RecordTy = getContext().getRecordType(RD);
   llvm::Function *ThunkFn = llvm::Function::Create(
-  ThunkTy, getLinkageForRTTI(RecordTy), ThunkName.str(), &CGM.getModule());
+  ThunkTy, getLinkageForRTTI(RecordTy), ThunkName.str(), CGM.getModule());
   ThunkFn->setCallingConv(static_cast(
   FnInfo.getEffectiveCallingConvention()));
   if (ThunkFn->isWeakForLinker())
Index: lib/CodeGen/ItaniumCXXABI.cpp
===
--- lib/CodeGen/ItaniumCXXABI.cpp
+++ lib/CodeGen/ItaniumCXXABI.cpp
@@ -2287,7 +2287,7 @@
   llvm::FunctionType *FnTy = CGM.getTypes().GetFunctionType(FI);
   llvm::Function *Wrapper =
   llvm::Function::Create(FnTy, getThreadLocalWrapperLinkage(VD, CGM),
- WrapperName.str(), &CGM.getModule());
+ WrapperName.str(), CGM.getModule());
 
   CGM.SetLLVMFunctionAttributes(nullptr, FI, Wrapper);
 
@@ -2394,7 +2394,7 @@
   llvm::FunctionType *FnTy = llvm::FunctionType::get(CGM.VoidTy, false);
   Init = llvm::Function::Create(FnTy,
 llvm::GlobalVariable::ExternalWeakLinkage,
-InitFnName.str(), &CGM.getModule());
+InitFnName.str(), CGM.getModule());
   const CGFunctionInfo &FI = CGM.getTypes().arrangeNullaryFunction();
   CGM.SetLLVMFunctionAttributes(nullptr, FI, cast(Init));
 }
Index: lib/CodeGen/CodeGenModule.cpp
===
--- lib/CodeGen/CodeGenModule.cpp
+++ lib/CodeGen/CodeGenModule.cpp
@@ -2446,7 +2446,7 @@
 
   llvm::Function *F =
   llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, &getModule());
+ Entry ? StringRef() : MangledName, getModule());
 
   // If we already created a function with the same mangled name (but different
   // type) before, take its name and add it to the list of functions to be
Index: lib/CodeGen/CGStmtOpenMP.cpp
===
--- lib/CodeGen/CGStmtOpenMP.cpp
+++ lib/CodeGen/CGStmtOpenMP.cpp
@@ -452,7 +452,7 @@
 
   llvm::Function *F =
   llvm::Function::Create(FuncLLVMTy, llvm::GlobalValue::InternalLinkage,
- FO.FunctionName, &CGM.getModule());
+

[PATCH] D54334: [AVR] Automatically link CRT and libgcc from the system avr-gcc

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay created this revision.
dylanmckay added reviewers: aaron.ballman, kparzysz, asb, hfinkel.

This patch modifies the AVR toolchain so that if avr-gcc and avr-libc
are detected during compilation, the CRT, libgcc, libm, and libc anre
linked.

This matches avr-gcc's default behaviour, and the expected behaviour of
all C compilers - including the C runtime.

avr-gcc also needs a -mmcu specified in order to link runtime libraries.

The difference betwen this patch and avr-gcc is that this patch will
warn users whenever they compile without a runtime, as opposed to GCC,
which silently trims the runtime libs from the linker arguments when no
-mmcu is specified.


Repository:
  rC Clang

https://reviews.llvm.org/D54334

Files:
  include/clang/Basic/DiagnosticDriverKinds.td
  include/clang/Basic/DiagnosticGroups.td
  lib/Driver/ToolChains/AVR.cpp
  lib/Driver/ToolChains/AVR.h
  lib/Driver/ToolChains/Gnu.cpp
  test/Driver/avr-link-mcu-family-unimplemented.c
  test/Driver/avr-link-no-mcu-specified.c
  test/Driver/avr-link-nostdlib-nodefaultlibs.c

Index: test/Driver/avr-link-nostdlib-nodefaultlibs.c
===
--- /dev/null
+++ test/Driver/avr-link-nostdlib-nodefaultlibs.c
@@ -0,0 +1,8 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 -nostdlib %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 -nodefaultlibs %s 2>&1 | FileCheck %s
+
+// nostdlib and nodefaultlibs programs should compile fine.
+
+// CHECK: main
+int main() { return 0; }
+
Index: test/Driver/avr-link-no-mcu-specified.c
===
--- /dev/null
+++ test/Driver/avr-link-no-mcu-specified.c
@@ -0,0 +1,10 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps %s 2>&1 | FileCheck --check-prefix=WARN %s
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 %s 2>&1 | FileCheck --check-prefix=NOWARN %s
+
+// WARN: warning: no target microcontroller specified on command line, cannot link standard libraries, please pass -mmcu=
+// WARN: warning: standard library not linked and so no interrupt vector table or compiler runtime routines will be linked
+
+// NOWARN: main
+
+int main() { return 0; }
+
Index: test/Driver/avr-link-mcu-family-unimplemented.c
===
--- /dev/null
+++ test/Driver/avr-link-mcu-family-unimplemented.c
@@ -0,0 +1,7 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=attiny13a %s 2>&1 | FileCheck --check-prefix=WARN %s
+
+// WARN: warning: support for linking stdlibs for microcontroller 'attiny13a' is not implemented, please file an AVR backend bug at http://bugs.llvm.org/ with your mcu name
+// WARN: warning: standard library not linked and so no interrupt vector table or compiler runtime routines will be linked
+
+int main() { return 0; }
+
Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -1865,6 +1865,9 @@
   static const char *const ARMebHFTriples[] = {
   "armeb-linux-gnueabihf", "armebv7hl-redhat-linux-gnueabi"};
 
+  static const char *const AVRLibDirs[] = {"/lib"};
+  static const char *const AVRTriples[] = {"avr"};
+
   static const char *const X86_64LibDirs[] = {"/lib64", "/lib"};
   static const char *const X86_64Triples[] = {
   "x86_64-linux-gnu",   "x86_64-unknown-linux-gnu",
@@ -2077,6 +2080,10 @@
   TripleAliases.append(begin(ARMebTriples), end(ARMebTriples));
 }
 break;
+  case llvm::Triple::avr:
+LibDirs.append(begin(AVRLibDirs), end(AVRLibDirs));
+TripleAliases.append(begin(AVRTriples), end(AVRTriples));
+break;
   case llvm::Triple::x86_64:
 LibDirs.append(begin(X86_64LibDirs), end(X86_64LibDirs));
 TripleAliases.append(begin(X86_64Triples), end(X86_64Triples));
@@ -2205,6 +2212,8 @@
   return false;
   } else if (isRISCV(TargetArch)) {
 findRISCVMultilibs(D, TargetTriple, Path, Args, Detected);
+  } else if (TargetArch == llvm::Triple::avr) {
+// AVR has no multilibs.
   } else if (!findBiarchMultilibs(D, TargetTriple, Path, Args,
   NeedsBiarchSuffix, Detected)) {
 return false;
Index: lib/Driver/ToolChains/AVR.h
===
--- lib/Driver/ToolChains/AVR.h
+++ lib/Driver/ToolChains/AVR.h
@@ -20,26 +20,45 @@
 namespace toolchains {
 
 class LLVM_LIBRARY_VISIBILITY AVRToolChain : public Generic_ELF {
-protected:
-  Tool *buildLinker() const override;
 public:
   AVRToolChain(const Driver &D, const llvm::Triple &Triple,
const llvm::opt::ArgList &Args);
+protected:
+  Tool *buildLinker() const override;
+
+private:
+  /// Whether libgcc, libct, and friends should be linked.
+  ///
+  /// This is no

[PATCH] D54334: [AVR] Automatically link CRT and libgcc from the system avr-gcc

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 173722.
dylanmckay added a comment.

Add the search path that Ubuntu installs libc to.


Repository:
  rC Clang

https://reviews.llvm.org/D54334

Files:
  include/clang/Basic/DiagnosticDriverKinds.td
  include/clang/Basic/DiagnosticGroups.td
  lib/Driver/ToolChains/AVR.cpp
  lib/Driver/ToolChains/AVR.h
  lib/Driver/ToolChains/Gnu.cpp
  test/Driver/avr-link-mcu-family-unimplemented.c
  test/Driver/avr-link-no-mcu-specified.c
  test/Driver/avr-link-nostdlib-nodefaultlibs.c

Index: test/Driver/avr-link-nostdlib-nodefaultlibs.c
===
--- /dev/null
+++ test/Driver/avr-link-nostdlib-nodefaultlibs.c
@@ -0,0 +1,8 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 -nostdlib %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 -nodefaultlibs %s 2>&1 | FileCheck %s
+
+// nostdlib and nodefaultlibs programs should compile fine.
+
+// CHECK: main
+int main() { return 0; }
+
Index: test/Driver/avr-link-no-mcu-specified.c
===
--- /dev/null
+++ test/Driver/avr-link-no-mcu-specified.c
@@ -0,0 +1,10 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps %s 2>&1 | FileCheck --check-prefix=WARN %s
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 %s 2>&1 | FileCheck --check-prefix=NOWARN %s
+
+// WARN: warning: no target microcontroller specified on command line, cannot link standard libraries, please pass -mmcu=
+// WARN: warning: standard library not linked and so no interrupt vector table or compiler runtime routines will be linked
+
+// NOWARN: main
+
+int main() { return 0; }
+
Index: test/Driver/avr-link-mcu-family-unimplemented.c
===
--- /dev/null
+++ test/Driver/avr-link-mcu-family-unimplemented.c
@@ -0,0 +1,7 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=attiny13a %s 2>&1 | FileCheck --check-prefix=WARN %s
+
+// WARN: warning: support for linking stdlibs for microcontroller 'attiny13a' is not implemented, please file an AVR backend bug at http://bugs.llvm.org/ with your mcu name
+// WARN: warning: standard library not linked and so no interrupt vector table or compiler runtime routines will be linked
+
+int main() { return 0; }
+
Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -1865,6 +1865,9 @@
   static const char *const ARMebHFTriples[] = {
   "armeb-linux-gnueabihf", "armebv7hl-redhat-linux-gnueabi"};
 
+  static const char *const AVRLibDirs[] = {"/lib"};
+  static const char *const AVRTriples[] = {"avr"};
+
   static const char *const X86_64LibDirs[] = {"/lib64", "/lib"};
   static const char *const X86_64Triples[] = {
   "x86_64-linux-gnu",   "x86_64-unknown-linux-gnu",
@@ -2077,6 +2080,10 @@
   TripleAliases.append(begin(ARMebTriples), end(ARMebTriples));
 }
 break;
+  case llvm::Triple::avr:
+LibDirs.append(begin(AVRLibDirs), end(AVRLibDirs));
+TripleAliases.append(begin(AVRTriples), end(AVRTriples));
+break;
   case llvm::Triple::x86_64:
 LibDirs.append(begin(X86_64LibDirs), end(X86_64LibDirs));
 TripleAliases.append(begin(X86_64Triples), end(X86_64Triples));
@@ -2205,6 +2212,8 @@
   return false;
   } else if (isRISCV(TargetArch)) {
 findRISCVMultilibs(D, TargetTriple, Path, Args, Detected);
+  } else if (TargetArch == llvm::Triple::avr) {
+// AVR has no multilibs.
   } else if (!findBiarchMultilibs(D, TargetTriple, Path, Args,
   NeedsBiarchSuffix, Detected)) {
 return false;
Index: lib/Driver/ToolChains/AVR.h
===
--- lib/Driver/ToolChains/AVR.h
+++ lib/Driver/ToolChains/AVR.h
@@ -20,26 +20,45 @@
 namespace toolchains {
 
 class LLVM_LIBRARY_VISIBILITY AVRToolChain : public Generic_ELF {
-protected:
-  Tool *buildLinker() const override;
 public:
   AVRToolChain(const Driver &D, const llvm::Triple &Triple,
const llvm::opt::ArgList &Args);
+protected:
+  Tool *buildLinker() const override;
+
+private:
+  /// Whether libgcc, libct, and friends should be linked.
+  ///
+  /// This is not done if the user does not specify a
+  /// microcontroller on the command line.
+  bool LinkStdlib;
+
+  llvm::Optional findAVRLibcInstallation() const;
 };
 
 } // end namespace toolchains
 
 namespace tools {
 namespace AVR {
 class LLVM_LIBRARY_VISIBILITY Linker : public GnuTool {
 public:
-  Linker(const ToolChain &TC) : GnuTool("AVR::Linker", "avr-ld", TC) {}
+  Linker(const llvm::Triple &Triple,
+ const ToolChain &TC,
+ bool LinkStdlib)
+: GnuTool("AVR::Linker", "avr-ld", TC),
+  Triple(Triple),
+  LinkS

[PATCH] D54334: [AVR] Automatically link CRT and libgcc from the system avr-gcc

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

I'd like feedback on the new AVR-specific warnings, and the new warning group. 
I have not added a warning or error to clang before, but this seems consistent 
with how the other targets implement it.


Repository:
  rC Clang

https://reviews.llvm.org/D54334



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[PATCH] D54334: [AVR] Automatically link CRT and libgcc from the system avr-gcc

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 174359.
dylanmckay marked 6 inline comments as done.
dylanmckay added a comment.

- Remove link to BugZilla in diagnostic
- Use StringRef for a static string array rather than std::string
- Elide braces
- Dereference an Optional in-place rather than persisting it for one use
- Use llvm::None rather than explicit Optional() constructor


Repository:
  rC Clang

https://reviews.llvm.org/D54334

Files:
  include/clang/Basic/DiagnosticDriverKinds.td
  include/clang/Basic/DiagnosticGroups.td
  lib/Driver/ToolChains/AVR.cpp
  lib/Driver/ToolChains/AVR.h
  lib/Driver/ToolChains/Gnu.cpp
  test/Driver/avr-link-mcu-family-unimplemented.c
  test/Driver/avr-link-no-mcu-specified.c
  test/Driver/avr-link-nostdlib-nodefaultlibs.c

Index: test/Driver/avr-link-nostdlib-nodefaultlibs.c
===
--- /dev/null
+++ test/Driver/avr-link-nostdlib-nodefaultlibs.c
@@ -0,0 +1,8 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 -nostdlib %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 -nodefaultlibs %s 2>&1 | FileCheck %s
+
+// nostdlib and nodefaultlibs programs should compile fine.
+
+// CHECK: main
+int main() { return 0; }
+
Index: test/Driver/avr-link-no-mcu-specified.c
===
--- /dev/null
+++ test/Driver/avr-link-no-mcu-specified.c
@@ -0,0 +1,10 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps %s 2>&1 | FileCheck --check-prefix=WARN %s
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 %s 2>&1 | FileCheck --check-prefix=NOWARN %s
+
+// WARN: warning: no target microcontroller specified on command line, cannot link standard libraries, please pass -mmcu=
+// WARN: warning: standard library not linked and so no interrupt vector table or compiler runtime routines will be linked
+
+// NOWARN: main
+
+int main() { return 0; }
+
Index: test/Driver/avr-link-mcu-family-unimplemented.c
===
--- /dev/null
+++ test/Driver/avr-link-mcu-family-unimplemented.c
@@ -0,0 +1,7 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=attiny13a %s 2>&1 | FileCheck --check-prefix=WARN %s
+
+// WARN: warning: support for linking stdlibs for microcontroller 'attiny13a' is not implemented
+// WARN: warning: standard library not linked and so no interrupt vector table or compiler runtime routines will be linked
+
+int main() { return 0; }
+
Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -1865,6 +1865,9 @@
   static const char *const ARMebHFTriples[] = {
   "armeb-linux-gnueabihf", "armebv7hl-redhat-linux-gnueabi"};
 
+  static const char *const AVRLibDirs[] = {"/lib"};
+  static const char *const AVRTriples[] = {"avr"};
+
   static const char *const X86_64LibDirs[] = {"/lib64", "/lib"};
   static const char *const X86_64Triples[] = {
   "x86_64-linux-gnu",   "x86_64-unknown-linux-gnu",
@@ -2077,6 +2080,10 @@
   TripleAliases.append(begin(ARMebTriples), end(ARMebTriples));
 }
 break;
+  case llvm::Triple::avr:
+LibDirs.append(begin(AVRLibDirs), end(AVRLibDirs));
+TripleAliases.append(begin(AVRTriples), end(AVRTriples));
+break;
   case llvm::Triple::x86_64:
 LibDirs.append(begin(X86_64LibDirs), end(X86_64LibDirs));
 TripleAliases.append(begin(X86_64Triples), end(X86_64Triples));
@@ -2205,6 +2212,8 @@
   return false;
   } else if (isRISCV(TargetArch)) {
 findRISCVMultilibs(D, TargetTriple, Path, Args, Detected);
+  } else if (TargetArch == llvm::Triple::avr) {
+// AVR has no multilibs.
   } else if (!findBiarchMultilibs(D, TargetTriple, Path, Args,
   NeedsBiarchSuffix, Detected)) {
 return false;
Index: lib/Driver/ToolChains/AVR.h
===
--- lib/Driver/ToolChains/AVR.h
+++ lib/Driver/ToolChains/AVR.h
@@ -20,26 +20,45 @@
 namespace toolchains {
 
 class LLVM_LIBRARY_VISIBILITY AVRToolChain : public Generic_ELF {
-protected:
-  Tool *buildLinker() const override;
 public:
   AVRToolChain(const Driver &D, const llvm::Triple &Triple,
const llvm::opt::ArgList &Args);
+protected:
+  Tool *buildLinker() const override;
+
+private:
+  /// Whether libgcc, libct, and friends should be linked.
+  ///
+  /// This is not done if the user does not specify a
+  /// microcontroller on the command line.
+  bool LinkStdlib;
+
+  llvm::Optional findAVRLibcInstallation() const;
 };
 
 } // end namespace toolchains
 
 namespace tools {
 namespace AVR {
 class LLVM_LIBRARY_VISIBILITY Linker : public GnuTool {
 public:
-  Linker(const ToolChain &TC) : GnuTool("AVR::Linker", "avr-ld", TC) {}
+ 

[PATCH] D54334: [AVR] Automatically link CRT and libgcc from the system avr-gcc

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 174362.
dylanmckay marked an inline comment as done.
dylanmckay added a comment.

Run clang-format on the whole patch


Repository:
  rC Clang

https://reviews.llvm.org/D54334

Files:
  include/clang/Basic/DiagnosticDriverKinds.td
  include/clang/Basic/DiagnosticGroups.td
  lib/Driver/ToolChains/AVR.cpp
  lib/Driver/ToolChains/AVR.h
  lib/Driver/ToolChains/Gnu.cpp
  test/Driver/avr-link-mcu-family-unimplemented.c
  test/Driver/avr-link-no-mcu-specified.c
  test/Driver/avr-link-nostdlib-nodefaultlibs.c

Index: test/Driver/avr-link-nostdlib-nodefaultlibs.c
===
--- /dev/null
+++ test/Driver/avr-link-nostdlib-nodefaultlibs.c
@@ -0,0 +1,8 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 -nostdlib %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 -nodefaultlibs %s 2>&1 | FileCheck %s
+
+// nostdlib and nodefaultlibs programs should compile fine.
+
+// CHECK: main
+int main() { return 0; }
+
Index: test/Driver/avr-link-no-mcu-specified.c
===
--- /dev/null
+++ test/Driver/avr-link-no-mcu-specified.c
@@ -0,0 +1,10 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps %s 2>&1 | FileCheck --check-prefix=WARN %s
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 %s 2>&1 | FileCheck --check-prefix=NOWARN %s
+
+// WARN: warning: no target microcontroller specified on command line, cannot link standard libraries, please pass -mmcu=
+// WARN: warning: standard library not linked and so no interrupt vector table or compiler runtime routines will be linked
+
+// NOWARN: main
+
+int main() { return 0; }
+
Index: test/Driver/avr-link-mcu-family-unimplemented.c
===
--- /dev/null
+++ test/Driver/avr-link-mcu-family-unimplemented.c
@@ -0,0 +1,7 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=attiny13a %s 2>&1 | FileCheck --check-prefix=WARN %s
+
+// WARN: warning: support for linking stdlibs for microcontroller 'attiny13a' is not implemented
+// WARN: warning: standard library not linked and so no interrupt vector table or compiler runtime routines will be linked
+
+int main() { return 0; }
+
Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -1865,6 +1865,9 @@
   static const char *const ARMebHFTriples[] = {
   "armeb-linux-gnueabihf", "armebv7hl-redhat-linux-gnueabi"};
 
+  static const char *const AVRLibDirs[] = {"/lib"};
+  static const char *const AVRTriples[] = {"avr"};
+
   static const char *const X86_64LibDirs[] = {"/lib64", "/lib"};
   static const char *const X86_64Triples[] = {
   "x86_64-linux-gnu",   "x86_64-unknown-linux-gnu",
@@ -2077,6 +2080,10 @@
   TripleAliases.append(begin(ARMebTriples), end(ARMebTriples));
 }
 break;
+  case llvm::Triple::avr:
+LibDirs.append(begin(AVRLibDirs), end(AVRLibDirs));
+TripleAliases.append(begin(AVRTriples), end(AVRTriples));
+break;
   case llvm::Triple::x86_64:
 LibDirs.append(begin(X86_64LibDirs), end(X86_64LibDirs));
 TripleAliases.append(begin(X86_64Triples), end(X86_64Triples));
@@ -2205,6 +2212,8 @@
   return false;
   } else if (isRISCV(TargetArch)) {
 findRISCVMultilibs(D, TargetTriple, Path, Args, Detected);
+  } else if (TargetArch == llvm::Triple::avr) {
+// AVR has no multilibs.
   } else if (!findBiarchMultilibs(D, TargetTriple, Path, Args,
   NeedsBiarchSuffix, Detected)) {
 return false;
Index: lib/Driver/ToolChains/AVR.h
===
--- lib/Driver/ToolChains/AVR.h
+++ lib/Driver/ToolChains/AVR.h
@@ -20,26 +20,43 @@
 namespace toolchains {
 
 class LLVM_LIBRARY_VISIBILITY AVRToolChain : public Generic_ELF {
-protected:
-  Tool *buildLinker() const override;
 public:
   AVRToolChain(const Driver &D, const llvm::Triple &Triple,
const llvm::opt::ArgList &Args);
+
+protected:
+  Tool *buildLinker() const override;
+
+private:
+  /// Whether libgcc, libct, and friends should be linked.
+  ///
+  /// This is not done if the user does not specify a
+  /// microcontroller on the command line.
+  bool LinkStdlib;
+
+  llvm::Optional findAVRLibcInstallation() const;
 };
 
 } // end namespace toolchains
 
 namespace tools {
 namespace AVR {
 class LLVM_LIBRARY_VISIBILITY Linker : public GnuTool {
 public:
-  Linker(const ToolChain &TC) : GnuTool("AVR::Linker", "avr-ld", TC) {}
+  Linker(const llvm::Triple &Triple, const ToolChain &TC, bool LinkStdlib)
+  : GnuTool("AVR::Linker", "avr-ld", TC), Triple(Triple),
+LinkStdlib(LinkStdlib) {}
+
   bool hasIntegratedCPP() const override {

[PATCH] D54334: [AVR] Automatically link CRT and libgcc from the system avr-gcc

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added inline comments.



Comment at: include/clang/Basic/DiagnosticDriverKinds.td:44-45
+def warn_drv_avr_family_linking_stdlibs_not_implemented: Warning<
+  "support for linking stdlibs for microcontroller '%0' is not implemented, "
+  "please file an AVR backend bug at http://bugs.llvm.org/ with your mcu 
name">,
+  InGroup;

aaron.ballman wrote:
> This is novel for diagnostics -- we don't have any other diagnostics that 
> recommend filing bugs. This doesn't strike me as something a naive developer 
> will just happen across by accident, so I would probably drop from the comma 
> onward and assume the user knows they can report bugs if they really care.
I agree



Comment at: lib/Driver/ToolChains/AVR.cpp:40
+
+const std::string PossibleAVRLibcLocations[] = {
+  "/usr/avr",

aaron.ballman wrote:
> Why use `std::string` here when below you use it as a list of `StringRef`s?
Good point, have fixed.



Comment at: lib/Driver/ToolChains/AVR.cpp:162
+
+  return Optional();
+}

aaron.ballman wrote:
> `return llvm::None;`
Didn't know about that, thanks!



Comment at: lib/Driver/ToolChains/AVR.h:45-47
+  Linker(const llvm::Triple &Triple,
+ const ToolChain &TC,
+ bool LinkStdlib)

aaron.ballman wrote:
> Did clang-format produce this? For some reason, it looks off to my eyes.
I have now run clang-format on the whole patch.


Repository:
  rC Clang

https://reviews.llvm.org/D54334



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[PATCH] D54334: [AVR] Automatically link CRT and libgcc from the system avr-gcc

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.
Herald added a project: clang.

I'm very comfortable with the AVR changes at this point, I am going to go ahead 
and commit the patch.


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[PATCH] D54334: [AVR] Automatically link CRT and libgcc from the system avr-gcc

[Dylan McKay via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rC361116: [AVR] Automatically link CRT and libgcc from the 
system avr-gcc (authored by dylanmckay, committed by ).
Herald added a subscriber: ormris.

Changed prior to commit:
  https://reviews.llvm.org/D54334?vs=174362&id=200177#toc

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  include/clang/Basic/DiagnosticDriverKinds.td
  include/clang/Basic/DiagnosticGroups.td
  lib/Driver/ToolChains/AVR.cpp
  lib/Driver/ToolChains/AVR.h
  lib/Driver/ToolChains/Gnu.cpp
  test/Driver/avr-link-mcu-family-unimplemented.c
  test/Driver/avr-link-no-mcu-specified.c
  test/Driver/avr-link-nostdlib-nodefaultlibs.c

Index: include/clang/Basic/DiagnosticGroups.td
===
--- include/clang/Basic/DiagnosticGroups.td
+++ include/clang/Basic/DiagnosticGroups.td
@@ -1033,6 +1033,10 @@
 // compiling CUDA C/C++ but which is not compatible with the CUDA spec.
 def CudaCompat : DiagGroup<"cuda-compat">;
 
+// Warnings which cause linking of the runtime libraries like
+// libc and the CRT to be skipped.
+def AVRRtlibLinkingQuirks : DiagGroup<"avr-rtlib-linking-quirks">;
+
 // A warning group for things that will change semantics in the future.
 def FutureCompat : DiagGroup<"future-compat">;
 
Index: include/clang/Basic/DiagnosticDriverKinds.td
===
--- include/clang/Basic/DiagnosticDriverKinds.td
+++ include/clang/Basic/DiagnosticDriverKinds.td
@@ -27,6 +27,25 @@
   "invalid arch name '%0', %1">;
 def err_drv_invalid_riscv_ext_arch_name : Error<
   "invalid arch name '%0', %1 '%2'">;
+def warn_drv_avr_mcu_not_specified : Warning<
+  "no target microcontroller specified on command line, cannot "
+  "link standard libraries, please pass -mmcu=">,
+  InGroup;
+def warn_drv_avr_gcc_not_found: Warning<
+  "no avr-gcc installation can be found on the system, "
+  "cannot link standard libraries">,
+  InGroup;
+def warn_drv_avr_libc_not_found: Warning<
+  "no avr-libc installation can be found on the system, "
+  "cannot link standard libraries">,
+  InGroup;
+def warn_drv_avr_family_linking_stdlibs_not_implemented: Warning<
+  "support for linking stdlibs for microcontroller '%0' is not implemented">,
+  InGroup;
+def warn_drv_avr_stdlib_not_linked: Warning<
+  "standard library not linked and so no interrupt vector table or "
+  "compiler runtime routines will be linked">,
+  InGroup;
 def err_drv_cuda_bad_gpu_arch : Error<"Unsupported CUDA gpu architecture: %0">;
 def err_drv_no_cuda_installation : Error<
   "cannot find CUDA installation.  Provide its path via --cuda-path, or pass "
Index: test/Driver/avr-link-no-mcu-specified.c
===
--- test/Driver/avr-link-no-mcu-specified.c
+++ test/Driver/avr-link-no-mcu-specified.c
@@ -0,0 +1,10 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps %s 2>&1 | FileCheck --check-prefix=WARN %s
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 %s 2>&1 | FileCheck --check-prefix=NOWARN %s
+
+// WARN: warning: no target microcontroller specified on command line, cannot link standard libraries, please pass -mmcu=
+// WARN: warning: standard library not linked and so no interrupt vector table or compiler runtime routines will be linked
+
+// NOWARN: main
+
+int main() { return 0; }
+
Index: test/Driver/avr-link-nostdlib-nodefaultlibs.c
===
--- test/Driver/avr-link-nostdlib-nodefaultlibs.c
+++ test/Driver/avr-link-nostdlib-nodefaultlibs.c
@@ -0,0 +1,8 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 -nostdlib %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=atmega328 -nodefaultlibs %s 2>&1 | FileCheck %s
+
+// nostdlib and nodefaultlibs programs should compile fine.
+
+// CHECK: main
+int main() { return 0; }
+
Index: test/Driver/avr-link-mcu-family-unimplemented.c
===
--- test/Driver/avr-link-mcu-family-unimplemented.c
+++ test/Driver/avr-link-mcu-family-unimplemented.c
@@ -0,0 +1,7 @@
+// RUN: %clang -### -target avr -no-canonical-prefixes -save-temps -mmcu=attiny13a %s 2>&1 | FileCheck --check-prefix=WARN %s
+
+// WARN: warning: support for linking stdlibs for microcontroller 'attiny13a' is not implemented
+// WARN: warning: standard library not linked and so no interrupt vector table or compiler runtime routines will be linked
+
+int main() { return 0; }
+
Index: lib/Driver/ToolChains/AVR.cpp
===
--- lib/Driver/ToolChains/AVR.cpp
+++ lib/Driver/T

[PATCH] D54334: [AVR] Automatically link CRT and libgcc from the system avr-gcc

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay marked 3 inline comments as done.
dylanmckay added a comment.

> I'm not certain if it will be possible to devise test cases for the two 
> diagnostics I pointed out or not

I don't think it will be. The compile warning logic works by directly querying 
the physical filesystem using the `llvm::sys::fs` APIs 
, which don't appear 
to support mocking or virtual filesystems. The only way for the pragmatically 
trigger the warnings is to dangerously manipulate the filesystem, potentially 
destroying the user's avr-gcc installation.

> I don't know enough about AVR to sign off on whether the patch logic is 
> correct or not.

I've added some review comments to the AVR logic referencing the GCC manual and 
how this patch matches it. I've also added the only two LLVM reviewers I know 
have AVR experience so hopefully they will be able to comment on the accuracy 
of the AVR logic.




Comment at: lib/Driver/ToolChains/AVR.cpp:35
+  return llvm::StringSwitch>(MCU)
+  .Case("atmega328", Optional("avr5"))
+  .Case("atmega328p", Optional("avr5"))

Here is the avr-gcc list of devices and their architectures

`atmega328` and `atmega328p` are a part of the `avr5` family.

> avr5
>
>“Enhanced” devices with 16 KiB up to 64 KiB of program memory.
>mcu = ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, 
> ata6613c, ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega16hva, 
> atmega16hva2, atmega16hvb, atmega16hvbrevb, atmega16m1, atmega16u4, 
> atmega161, atmega162, atmega163, atmega164a, atmega164p, atmega164pa, 
> atmega165, atmega165a, atmega165p, atmega165pa, atmega168, atmega168a, 
> atmega168p, atmega168pa, atmega168pb, atmega169, atmega169a, atmega169p, 
> atmega169pa, atmega32, atmega32a, atmega32c1, atmega32hvb, atmega32hvbrevb, 
> atmega32m1, atmega32u4, atmega32u6, atmega323, atmega324a, atmega324p, 
> atmega324pa, atmega325, atmega325a, atmega325p, atmega325pa, atmega3250, 
> atmega3250a, atmega3250p, atmega3250pa, atmega328, atmega328p, atmega328pb, 
> atmega329, atmega329a, atmega329p, atmega329pa, atmega3290, atmega3290a, 
> atmega3290p, atmega3290pa, atmega406, atmega64, atmega64a, atmega64c1, 
> atmega64hve, atmega64hve2, atmega64m1, atmega64rfr2, atmega640, atmega644, 
> atmega644a, atmega644p, atmega644pa, atmega644rfr2, atmega645, atmega645a, 
> atmega645p, atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, 
> atmega649p, atmega6490, atmega6490a, atmega6490p, at90can32, at90can64, 
> at90pwm161, at90pwm216, at90pwm316, at90scr100, at90usb646, at90usb647, 
> at94k, m3000.


https://gcc.gnu.org/onlinedocs/gcc/AVR-Options.html



Comment at: lib/Driver/ToolChains/AVR.cpp:139
+// Add the link library specific to the MCU.
+CmdArgs.push_back(Args.MakeArgString(std::string("-l") + CPU));
+

Here is the avr-gcc manual documenting the filename of this particular 
libary[1].

> Options:
>
> -nodevicelib
>
> Don’t link against AVR-LibC’s device specific library lib.a. 

This patch follows the same conventions as avr-gcc and thus can link the same 
libraries as avr-gcc.

[1] - https://gcc.gnu.org/onlinedocs/gcc/AVR-Options.html



Comment at: lib/Driver/ToolChains/AVR.cpp:143
+// This is almost always required because otherwise avr-ld
+// will assume 'avr2' and warn about the program being larger
+// than the bare minimum supports.

This is an existing piece of avr-gcc logic also implemented by the LLVM AVR 
backend


> -mmcu=mcu
>
>Specify Atmel AVR instruction set architectures (ISA) or MCU type. 
> The default for this option is ‘avr2’. 

https://gcc.gnu.org/onlinedocs/gcc/AVR-Options.html


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[PATCH] D37057: [clang] Require address space to be specified when creating functions (3/3)

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay abandoned this revision.
dylanmckay added a comment.

Superseded by https://reviews.llvm.org/D47541


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[PATCH] D77334: [AVR] Remove duplicate specification of lib directory

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay accepted this revision.
dylanmckay added a comment.
This revision is now accepted and ready to land.

Nice catch, cheers.

Do you need someone to commit this for you?


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[PATCH] D77334: [AVR] Remove duplicate specification of lib directory

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

Sorry, I lost track of this. Committed in 
01741d6dbec11c0a0c8e610f0033831735c78d1e 



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[PATCH] D77334: [AVR] Remove duplicate specification of lib directory

[Dylan McKay via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG03b0831144a9: [AVR] Remove duplicate specification of lib 
directory (authored by dylanmckay).

Changed prior to commit:
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Files:
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Index: clang/lib/Driver/ToolChains/AVR.cpp
===
--- clang/lib/Driver/ToolChains/AVR.cpp
+++ clang/lib/Driver/ToolChains/AVR.cpp
@@ -79,8 +79,6 @@
 
 getFilePaths().push_back(LibcRoot + std::string("/lib/") +
  std::string(*FamilyName));
-getFilePaths().push_back(LibcRoot + std::string("/lib/") +
- std::string(*FamilyName));
 getFilePaths().push_back(GCCRoot + std::string("/") +
  std::string(*FamilyName));
 


Index: clang/lib/Driver/ToolChains/AVR.cpp
===
--- clang/lib/Driver/ToolChains/AVR.cpp
+++ clang/lib/Driver/ToolChains/AVR.cpp
@@ -79,8 +79,6 @@
 
 getFilePaths().push_back(LibcRoot + std::string("/lib/") +
  std::string(*FamilyName));
-getFilePaths().push_back(LibcRoot + std::string("/lib/") +
- std::string(*FamilyName));
 getFilePaths().push_back(GCCRoot + std::string("/") +
  std::string(*FamilyName));
 
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[PATCH] D77221: [AVR] Rework MCU family detection to support more AVR MCUs

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay requested changes to this revision.
dylanmckay added inline comments.
This revision now requires changes to proceed.



Comment at: clang/lib/Basic/Targets/AVR.h:21
 
+#include "llvm/Support/AVRTargetParser.h"
+

Order this `#include` alphabetically with the ones above it



Comment at: llvm/include/llvm/Support/AVRTargetParser.h:9
+//
+// This file implements a target parser to recognise AVR CPUs
+//

Add another sentence or two to this documentation, as this will be a new 
public-facing API that all frontends can use.



Comment at: llvm/lib/Support/AVRTargetParser.cpp:20
+// This list should be kept up-to-date with AVRDevices.td in LLVM.
+static constexpr AVR::MCUInfo AVRMcus[] = {
+{"avr1", "at90s1200", "__AVR_AT90S1200__"},

Add a comment like `FIXME: At some point, this list should removed and the 
logic directly driven from the definitions in `AVRDevices.td`.


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[PATCH] D78491: Avoid relying on address space zero default parameter in llvm/IR

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

> should help targets such as AVR than use a non-zero program address space.

It definitely will - we have the exact same problems in terms of every call to 
`getUnqual` on a function pointer becomes a ISel error.

> I think making such bugs a compilation failure should be beneficial for 
> everyone even if it means typing a few more characters to get a pointer type.

I agree, it's the only reasonable way to support AVR at a level on-par with 
other official backends, all of which do not place functions in nonzero address 
spaces.


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[PATCH] D78491: Avoid relying on address space zero default parameter in llvm/IR

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.
Herald added a project: LLVM.

I really like the idea behind this patch, but I suspect there is a better way 
to go about it.

The only drawbacks to upstreaming this patch as-is is the idea that because it 
is implemented as a compiler define directive, it effectively splinters the the 
core LLVM C++ API into two different versions. Of course, this is kind of the 
point, but my only worry is that the `LLVM_DEFAULT_AS_PARAM` macro adds an 
additional layer of complexity to all users of the API that will be encountered 
and must be considered.

I think, if we have already identified all the call sites that break under the 
`LLVM_DEFAULT_AS_PARAM` patch, then we should instead make two final patches 
that fix the root rather than add the `LLVM_DEFAULT_AS_PARAM` for retroactive 
discovery. 1) replace all calls to `getUnqual` with the appropriate logic, 
which it looks like you've already done, and 2) remove the default value of `0` 
from all address space parameters so the callers *must* explicitly pass the 
address space in. I think that 2) would be hard to swing in the past whilst AVR 
was an experimental target, but now that AVR is an officially supported LLVM 
target, it is invariably true that all calls to `getOrCreateInternalVariable` 
and friends without explicit address spaces will break an officially supported 
in-tree target. It no longer makes sense to default to zero, so let's fix the 
root cause.

This would the problem at the root, stopping all new LLVM code from implicitly 
defaulting to address space `0`. This still leaves open the problem of 
developers explicitly calling `getUnqual` when constructing pointers, but this 
problem is left open under this patch currently as regardless of the default 
parameter or not, calls to `getUnqual` are still allowed.

**tl;dr** I suggest removing the `LLVM_DEFAULT_AS_PARAM` directive from this 
patch, instead permanently removing the default value of `= 0`. This will 
achieve the same end result, but it will fix the broken API rather than just 
making it easier for downstream users like CHERI to discover.

What are your thoughts?


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[PATCH] D77221: [AVR] Rework MCU family detection to support more AVR MCUs

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

@aykevl

> A thought: should the AVR family be included in the target triple? Like 
> avr5-unknown-unknown (similar to armv6m-none-eabi, armv7m-none-eabi, etc).
>  The different variations do sometimes change the architecture in 
> incompatible ways, such as with the call instruction which pushes a return 
> address of two or three bytes depending on the architecture variant (and thus 
> makes it impossible to pass parameters on the stack reliably).

I've thought about this a few years ago, I suspect it is not possible. It seems 
like we really do need to compile a sysroot/stdlib/runtime libraries for each 
and every distinct MCU.

https://github.com/rust-lang/rust/issues/44036#issuecomment-324330757

>> Does each device have a subtly different ISA?
> 
> **tl;dr** Sometimes, yes
> 
> In general, all devices can be _more or less_ grouped into families.
> 
> For example, `avr1`, `avr2`, `avr25`, ... `avr5`, `avr51`, are all family 
> names. These families each define an subset of the full AVR ISA.
> 
> You can find the AVR backend's definition of these families in AVRDevices.td 
> .
>  You can see that in general, the families build up on top of each other in 
> terms of supported instructions/features.
> 
> The problem is that not every realised ISA can be cleanly separated into a 
> family.
> 
> For example, the ATtiny26 
> 
>  is a part of the `avr2` family, but it also happens to support the "LPMX" 
> set of instructions
> 
> Another example is the ATMega8515 
> ,
>  which _almost_ implements all of `avr4`, but not quite all, and so the 
> linked definition bases the device off `avr2` and adds the extra features 
> explicitly.
> 
>> Does the backend need to know about peripherals?
> 
> No
> 
>> Or why do you want the LLVM backend to know when it's targeting, for 
>> example, "atmega328"?
> 
> Solely for deciding what subset of the ISA is supported.All device-specific 
> information required (or used) by the backend can be found inside 
> AVRDevices.td 
> .

There is a bunch of other related discussion on 
https://github.com/rust-lang/rust/issues/44036 too.


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[PATCH] D37057: [clang] Require address space to be specified when creating functions (4/4)

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 125887.
dylanmckay added a comment.
Herald added a subscriber: cfe-commits.

- Remove the switch table stuff for a later patch
- Rebased on top of trunk


Repository:
  rC Clang

https://reviews.llvm.org/D37057

Files:
  lib/CodeGen/CGBlocks.cpp
  lib/CodeGen/CGBuiltin.cpp
  lib/CodeGen/CGCUDANV.cpp
  lib/CodeGen/CGDeclCXX.cpp
  lib/CodeGen/CGException.cpp
  lib/CodeGen/CGExpr.cpp
  lib/CodeGen/CGGPUBuiltin.cpp
  lib/CodeGen/CGObjC.cpp
  lib/CodeGen/CGObjCGNU.cpp
  lib/CodeGen/CGObjCMac.cpp
  lib/CodeGen/CGOpenMPRuntime.cpp
  lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp
  lib/CodeGen/CGStmt.cpp
  lib/CodeGen/CGStmtOpenMP.cpp
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/ItaniumCXXABI.cpp
  lib/CodeGen/MicrosoftCXXABI.cpp
  lib/CodeGen/TargetInfo.cpp

Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -8974,7 +8974,7 @@
   std::string Name = Invoke->getName().str() + "_kernel";
   auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
   auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
-   &CGF.CGM.getModule());
+   CGF.CGM.getModule());
   auto IP = CGF.Builder.saveIP();
   auto *BB = llvm::BasicBlock::Create(C, "entry", F);
   auto &Builder = CGF.Builder;
@@ -9032,7 +9032,7 @@
   std::string Name = Invoke->getName().str() + "_kernel";
   auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
   auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
-   &CGF.CGM.getModule());
+   CGF.CGM.getModule());
   F->addFnAttr("enqueued-block");
   auto IP = CGF.Builder.saveIP();
   auto *BB = llvm::BasicBlock::Create(C, "entry", F);
Index: lib/CodeGen/MicrosoftCXXABI.cpp
===
--- lib/CodeGen/MicrosoftCXXABI.cpp
+++ lib/CodeGen/MicrosoftCXXABI.cpp
@@ -1928,7 +1928,7 @@
   llvm::FunctionType *ThunkTy = CGM.getTypes().GetFunctionType(FnInfo);
   llvm::Function *ThunkFn =
   llvm::Function::Create(ThunkTy, llvm::Function::ExternalLinkage,
- ThunkName.str(), &CGM.getModule());
+ ThunkName.str(), CGM.getModule());
   assert(ThunkFn->getName() == ThunkName && "name was uniqued!");
 
   ThunkFn->setLinkage(MD->isExternallyVisible()
@@ -3856,7 +3856,7 @@
   const CXXRecordDecl *RD = CD->getParent();
   QualType RecordTy = getContext().getRecordType(RD);
   llvm::Function *ThunkFn = llvm::Function::Create(
-  ThunkTy, getLinkageForRTTI(RecordTy), ThunkName.str(), &CGM.getModule());
+  ThunkTy, getLinkageForRTTI(RecordTy), ThunkName.str(), CGM.getModule());
   ThunkFn->setCallingConv(static_cast(
   FnInfo.getEffectiveCallingConvention()));
   if (ThunkFn->isWeakForLinker())
Index: lib/CodeGen/ItaniumCXXABI.cpp
===
--- lib/CodeGen/ItaniumCXXABI.cpp
+++ lib/CodeGen/ItaniumCXXABI.cpp
@@ -2291,7 +2291,7 @@
   llvm::FunctionType *FnTy = CGM.getTypes().GetFunctionType(FI);
   llvm::Function *Wrapper =
   llvm::Function::Create(FnTy, getThreadLocalWrapperLinkage(VD, CGM),
- WrapperName.str(), &CGM.getModule());
+ WrapperName.str(), CGM.getModule());
 
   CGM.SetLLVMFunctionAttributes(nullptr, FI, Wrapper);
 
@@ -2398,7 +2398,7 @@
   llvm::FunctionType *FnTy = llvm::FunctionType::get(CGM.VoidTy, false);
   Init = llvm::Function::Create(FnTy,
 llvm::GlobalVariable::ExternalWeakLinkage,
-InitFnName.str(), &CGM.getModule());
+InitFnName.str(), CGM.getModule());
   const CGFunctionInfo &FI = CGM.getTypes().arrangeNullaryFunction();
   CGM.SetLLVMFunctionAttributes(nullptr, FI, cast(Init));
 }
Index: lib/CodeGen/CodeGenModule.cpp
===
--- lib/CodeGen/CodeGenModule.cpp
+++ lib/CodeGen/CodeGenModule.cpp
@@ -2124,7 +2124,7 @@
 
   llvm::Function *F =
   llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, &getModule());
+ Entry ? StringRef() : MangledName, getModule());
 
   // If we already created a function with the same mangled name (but different
   // type) before, take its name and add it to the list of functions to be
Index: lib/CodeGen/CGStmtOpenMP.cpp
===
--- lib/CodeGen/CGStmtOpenMP.cpp
+++ lib/CodeGen/CGStmtOpenMP.cpp
@@ -381,7 +381,7 @@
 
   llvm::Function *F =
   llvm::Function::Create(FuncLLVMTy, llvm::GlobalValue::InternalLinkage,
-  

[PATCH] D37057: [clang] Require address space to be specified when creating functions (3/3)

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 126270.
dylanmckay added a comment.

Rebase on trunk


Repository:
  rC Clang

https://reviews.llvm.org/D37057

Files:
  lib/CodeGen/CGBlocks.cpp
  lib/CodeGen/CGBuiltin.cpp
  lib/CodeGen/CGCUDANV.cpp
  lib/CodeGen/CGDeclCXX.cpp
  lib/CodeGen/CGException.cpp
  lib/CodeGen/CGExpr.cpp
  lib/CodeGen/CGGPUBuiltin.cpp
  lib/CodeGen/CGObjC.cpp
  lib/CodeGen/CGObjCGNU.cpp
  lib/CodeGen/CGObjCMac.cpp
  lib/CodeGen/CGOpenMPRuntime.cpp
  lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp
  lib/CodeGen/CGStmt.cpp
  lib/CodeGen/CGStmtOpenMP.cpp
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/ItaniumCXXABI.cpp
  lib/CodeGen/MicrosoftCXXABI.cpp
  lib/CodeGen/TargetInfo.cpp

Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -8974,7 +8974,7 @@
   std::string Name = Invoke->getName().str() + "_kernel";
   auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
   auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
-   &CGF.CGM.getModule());
+   CGF.CGM.getModule());
   auto IP = CGF.Builder.saveIP();
   auto *BB = llvm::BasicBlock::Create(C, "entry", F);
   auto &Builder = CGF.Builder;
@@ -9032,7 +9032,7 @@
   std::string Name = Invoke->getName().str() + "_kernel";
   auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
   auto *F = llvm::Function::Create(FT, llvm::GlobalValue::InternalLinkage, Name,
-   &CGF.CGM.getModule());
+   CGF.CGM.getModule());
   F->addFnAttr("enqueued-block");
   auto IP = CGF.Builder.saveIP();
   auto *BB = llvm::BasicBlock::Create(C, "entry", F);
Index: lib/CodeGen/MicrosoftCXXABI.cpp
===
--- lib/CodeGen/MicrosoftCXXABI.cpp
+++ lib/CodeGen/MicrosoftCXXABI.cpp
@@ -1928,7 +1928,7 @@
   llvm::FunctionType *ThunkTy = CGM.getTypes().GetFunctionType(FnInfo);
   llvm::Function *ThunkFn =
   llvm::Function::Create(ThunkTy, llvm::Function::ExternalLinkage,
- ThunkName.str(), &CGM.getModule());
+ ThunkName.str(), CGM.getModule());
   assert(ThunkFn->getName() == ThunkName && "name was uniqued!");
 
   ThunkFn->setLinkage(MD->isExternallyVisible()
@@ -3856,7 +3856,7 @@
   const CXXRecordDecl *RD = CD->getParent();
   QualType RecordTy = getContext().getRecordType(RD);
   llvm::Function *ThunkFn = llvm::Function::Create(
-  ThunkTy, getLinkageForRTTI(RecordTy), ThunkName.str(), &CGM.getModule());
+  ThunkTy, getLinkageForRTTI(RecordTy), ThunkName.str(), CGM.getModule());
   ThunkFn->setCallingConv(static_cast(
   FnInfo.getEffectiveCallingConvention()));
   if (ThunkFn->isWeakForLinker())
Index: lib/CodeGen/ItaniumCXXABI.cpp
===
--- lib/CodeGen/ItaniumCXXABI.cpp
+++ lib/CodeGen/ItaniumCXXABI.cpp
@@ -2291,7 +2291,7 @@
   llvm::FunctionType *FnTy = CGM.getTypes().GetFunctionType(FI);
   llvm::Function *Wrapper =
   llvm::Function::Create(FnTy, getThreadLocalWrapperLinkage(VD, CGM),
- WrapperName.str(), &CGM.getModule());
+ WrapperName.str(), CGM.getModule());
 
   CGM.SetLLVMFunctionAttributes(nullptr, FI, Wrapper);
 
@@ -2398,7 +2398,7 @@
   llvm::FunctionType *FnTy = llvm::FunctionType::get(CGM.VoidTy, false);
   Init = llvm::Function::Create(FnTy,
 llvm::GlobalVariable::ExternalWeakLinkage,
-InitFnName.str(), &CGM.getModule());
+InitFnName.str(), CGM.getModule());
   const CGFunctionInfo &FI = CGM.getTypes().arrangeNullaryFunction();
   CGM.SetLLVMFunctionAttributes(nullptr, FI, cast(Init));
 }
Index: lib/CodeGen/CodeGenModule.cpp
===
--- lib/CodeGen/CodeGenModule.cpp
+++ lib/CodeGen/CodeGenModule.cpp
@@ -2124,7 +2124,7 @@
 
   llvm::Function *F =
   llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
- Entry ? StringRef() : MangledName, &getModule());
+ Entry ? StringRef() : MangledName, getModule());
 
   // If we already created a function with the same mangled name (but different
   // type) before, take its name and add it to the list of functions to be
Index: lib/CodeGen/CGStmtOpenMP.cpp
===
--- lib/CodeGen/CGStmtOpenMP.cpp
+++ lib/CodeGen/CGStmtOpenMP.cpp
@@ -389,7 +389,7 @@
 
   llvm::Function *F =
   llvm::Function::Create(FuncLLVMTy, llvm::GlobalValue::InternalLinkage,
- FO.FunctionName, &CGM.getModule());
+ FO.FunctionName, CG

[PATCH] D86629: [AVR][clang] Pass the address of the data section to the linker for ATmega328

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

Hey @aykevl, could you please confirm that this patch looks okay?


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[PATCH] D86629: [AVR][clang] Pass the address of the data section to the linker for ATmega328

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay created this revision.
dylanmckay added a reviewer: aykevl.
Herald added a subscriber: Jim.
Herald added a project: clang.
dylanmckay requested review of this revision.

This patch modifies the Clang AVR toolchain so that it always passes
the '-Tdata=0x800100' to the linker for ATmega328 devices. This matches
AVR-GCC behaviour, and also corresponds to the address of the start of
the data section in data space according to the ATmega328 datasheet.

Without this, clang does not produce a valid ATmega328 binary.

When targeting all non-ATmega328 chips, a warning will be emitted due to
the fact that proper handling for the chips data section address is
not yet implemented.

I've held off adding other microcontrollers for now, mostly because the
AVR toolchain logic is smeared across LLVM core TableGen files, and two Clang
libraries. The 'family detection' logic is also only implemented for
ATmega328 at the moment, for similar reasons.

In the future, I aim to write an RFC to llvm-dev to find a better way
for LLVM to expose target-specific details such as these to compiler
frontends.


Repository:
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Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/lib/Driver/ToolChains/AVR.cpp


Index: clang/lib/Driver/ToolChains/AVR.cpp
===
--- clang/lib/Driver/ToolChains/AVR.cpp
+++ clang/lib/Driver/ToolChains/AVR.cpp
@@ -13,6 +13,7 @@
 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
 #include "llvm/ADT/Optional.h"
+#include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/SubtargetFeature.h"
@@ -36,6 +37,13 @@
   .Default(Optional());
 }
 
+llvm::Optional GetMcuSectionAddressData(StringRef MCU) {
+  return llvm::StringSwitch>(MCU)
+  .Case("atmega328", Optional(0x800100))
+  .Case("atmega328p", Optional(0x800100))
+  .Default(Optional());
+}
+
 const StringRef PossibleAVRLibcLocations[] = {
 "/usr/avr",
 "/usr/lib/avr",
@@ -103,6 +111,7 @@
   // Compute information about the target AVR.
   std::string CPU = getCPUName(Args, getToolChain().getTriple());
   llvm::Optional FamilyName = GetMcuFamilyName(CPU);
+  llvm::Optional SectionAddressData = GetMcuSectionAddressData(CPU);
 
   std::string Linker = getToolChain().GetProgramPath(getShortName());
   ArgStringList CmdArgs;
@@ -118,6 +127,17 @@
   Args.AddAllArgs(CmdArgs, options::OPT_L);
   getToolChain().AddFilePathLibArgs(Args, CmdArgs);
 
+  if (SectionAddressData.hasValue()) {
+std::string DataSectionArg = std::string("-Tdata=0x") +
+ 
llvm::utohexstr(SectionAddressData.getValue());
+CmdArgs.push_back(Args.MakeArgString(DataSectionArg));
+  } else {
+// We do not have an entry for this CPU in the address mapping table yet.
+getToolChain().getDriver().Diag(
+diag::warn_drv_avr_linker_section_addresses_not_implemented)
+<< CPU;
+  }
+
   // If the family name is known, we can link with the device-specific libgcc.
   // Without it, libgcc will simply not be linked. This matches avr-gcc
   // behavior.
Index: clang/include/clang/Basic/DiagnosticDriverKinds.td
===
--- clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -44,6 +44,10 @@
 def warn_drv_avr_family_linking_stdlibs_not_implemented: Warning<
   "support for linking stdlibs for microcontroller '%0' is not implemented">,
   InGroup;
+def warn_drv_avr_linker_section_addresses_not_implemented: Warning<
+  "support for passing the data section address to the linker for "
+  "microcontroller '%0' is not implemented">,
+  InGroup;
 def warn_drv_avr_stdlib_not_linked: Warning<
   "standard library not linked and so no interrupt vector table or "
   "compiler runtime routines will be linked">,


Index: clang/lib/Driver/ToolChains/AVR.cpp
===
--- clang/lib/Driver/ToolChains/AVR.cpp
+++ clang/lib/Driver/ToolChains/AVR.cpp
@@ -13,6 +13,7 @@
 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
 #include "llvm/ADT/Optional.h"
+#include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/SubtargetFeature.h"
@@ -36,6 +37,13 @@
   .Default(Optional());
 }
 
+llvm::Optional GetMcuSectionAddressData(StringRef MCU) {
+  return llvm::StringSwitch>(MCU)
+  .Case("atmega328", Optional(0x800100))
+  .Case("atmega328p", Optional(0x800100))
+  .Default(Optional());
+}
+
 const StringRef PossibleAVRLibcLocations[] = {
 "/usr/avr",
 "/usr/lib/avr",
@@ -103,6 +111,7 @@
   // Compute information about the target AVR.
   std::string CPU = getCPUName(Args, getToolChain().getTriple());
   llvm::Optional FamilyName = GetMcu

[PATCH] D78491: Avoid relying on address space zero default parameter in llvm/IR

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

Note to the readers: A recent-ish llvm-dev discussion around this patch can be 
found in here  
whrein a consensus is found on the way forward on this patch.


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[PATCH] D84345: [AMDGPU] Set the default globals address space to 1

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added inline comments.



Comment at: llvm/lib/IR/AutoUpgrade.cpp:4297
+  // address space of 1.
+  if (T.isAMDGPU() && !DL.contains("-G") && !DL.startswith("G")) {
+return DL.empty() ? std::string("G1") : (DL + "-G1").str();

arichardson wrote:
> akhuang wrote:
> > arichardson wrote:
> > > arsenm wrote:
> > > > I would expect datalayout upgrades to work by parsing the old string, 
> > > > and checking the field values inside. I guess directly checking the 
> > > > string isn't a new problem here
> > > I agree that would be less error prone. I wonder if there are cases where 
> > > the old string may fail to parse so you have to do the textual upgrade 
> > > first. I'm happy to make this change.
> > > 
> > > @akhuang is there a reason you used string parsing in D67631? Any 
> > > objections to changing the code to parse the datalayout and add missing 
> > > attributes?
> > I don't think so; parsing the datalayout sounds better to me too. 
> I just looked into parsing the DataLayout instead. Unfortunately the 
> resulting code is more complicated since there are no setters in DataLayout 
> and no way to create a normalized representation.
> There's also no way to differentiate between no `-G ` passed and `-G0` so  
> something like `e-p:64:64-G0` will be converted to `e-p:64:64-G0-G1`
> 
I suspect it would be possible to use the existing `DataLayout(StringRef)` 
constructor on the string, then call `getDefaultGlobalsAddressSpace()` on it, 
explicitly ignoring modifying the datalayout for the special case of an 
explicit `-G0`.

For example,

```cpp
  DataLayout ParsedDL = DataLayout(DL);
  if (T.isAMDGPU() && !DL.contains("-G0") 
&&ParsedDL.getDefaultGlobalsAddressSpace() != 1) {
return DL.empty() ? std::string("G1") : (DL + "-G1").str();
  }
```

As I understand it, this would cover the fact that we cannot distinguish 
between an explicit default globals space of zero, and a datalayout without a 
default globals space (also `DL::getDefaultGlobalsAddressSpace() == 0`) by 
explicitly excluding the special case `-G0`


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[PATCH] D84345: [AMDGPU] Set the default globals address space to 1

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added inline comments.



Comment at: llvm/lib/IR/AutoUpgrade.cpp:4297
+  // address space of 1.
+  if (T.isAMDGPU() && !DL.contains("-G") && !DL.startswith("G")) {
+return DL.empty() ? std::string("G1") : (DL + "-G1").str();

dylanmckay wrote:
> arichardson wrote:
> > akhuang wrote:
> > > arichardson wrote:
> > > > arsenm wrote:
> > > > > I would expect datalayout upgrades to work by parsing the old string, 
> > > > > and checking the field values inside. I guess directly checking the 
> > > > > string isn't a new problem here
> > > > I agree that would be less error prone. I wonder if there are cases 
> > > > where the old string may fail to parse so you have to do the textual 
> > > > upgrade first. I'm happy to make this change.
> > > > 
> > > > @akhuang is there a reason you used string parsing in D67631? Any 
> > > > objections to changing the code to parse the datalayout and add missing 
> > > > attributes?
> > > I don't think so; parsing the datalayout sounds better to me too. 
> > I just looked into parsing the DataLayout instead. Unfortunately the 
> > resulting code is more complicated since there are no setters in DataLayout 
> > and no way to create a normalized representation.
> > There's also no way to differentiate between no `-G ` passed and `-G0` so  
> > something like `e-p:64:64-G0` will be converted to `e-p:64:64-G0-G1`
> > 
> I suspect it would be possible to use the existing `DataLayout(StringRef)` 
> constructor on the string, then call `getDefaultGlobalsAddressSpace()` on it, 
> explicitly ignoring modifying the datalayout for the special case of an 
> explicit `-G0`.
> 
> For example,
> 
> ```cpp
>   DataLayout ParsedDL = DataLayout(DL);
>   if (T.isAMDGPU() && !DL.contains("-G0") 
> &&ParsedDL.getDefaultGlobalsAddressSpace() != 1) {
> return DL.empty() ? std::string("G1") : (DL + "-G1").str();
>   }
> ```
> 
> As I understand it, this would cover the fact that we cannot distinguish 
> between an explicit default globals space of zero, and a datalayout without a 
> default globals space (also `DL::getDefaultGlobalsAddressSpace() == 0`) by 
> explicitly excluding the special case `-G0`
To be completely correct it should not assume that the global address space is 
not at the very start of the data layout as my initial snippet did. I've 
removed the `-` prefix from the `contains` check

```
  DataLayout ParsedDL = DataLayout(DL);
  if (T.isAMDGPU() && !DL.contains("G0") 
&&ParsedDL.getDefaultGlobalsAddressSpace() != 1) {
return DL.empty() ? std::string("G1") : (DL + "-G1").str();
  }
```


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[PATCH] D88410: [clang][AVR] Improve avr-ld command line options

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay accepted this revision.
dylanmckay added a comment.
This revision is now accepted and ready to land.

Looks good to me, thanks for the patch @benshi001

NOTE: It looks like you will need to rebase this one prior to merge.


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[PATCH] D86629: [AVR][clang] Pass the address of the data section to the linker for ATmega328

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added inline comments.



Comment at: clang/lib/Driver/ToolChains/AVR.cpp:40
 
+llvm::Optional GetMcuSectionAddressData(StringRef MCU) {
+  return llvm::StringSwitch>(MCU)

benshi001 wrote:
> aykevl wrote:
> > I don't think the LLVM coding style says something about this, but coming 
> > from Go I'm more used to capitalized abbreviations (`MCU`, 
> > `GetMCUSectionAddressData`).
> > 
> > However, this is just a superficial thing, feel free to ignore.
> I prefer to "Mcu"
I will change, thanks for the suggestions. FWIW, Rust prefers the `Mcu` variant 
IIRC which is where I adapted this pattern


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[PATCH] D86629: [AVR][clang] Pass the address of the data section to the linker for ATmega328

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

Regarding TableGen; I would like to send an RFC to llvm-dev to come up with a 
proper API to expose backend-specific device-specific information and constants 
to LLVM frontends, as I can imagine that many backends could stand to benefit. 
I note that there is in general a lot of duplication in individual frontends 
defining information LLVM already knows about (off the top of my head, inline 
assembly constraints and registers is one of them but may not easily fit into 
the paradigm I have in mind).


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[PATCH] D88352: [clang][AVR] Add more devices

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay accepted this revision.
dylanmckay added a comment.
This revision is now accepted and ready to land.

Approved, thanks!


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[PATCH] D86629: [AVR][clang] Pass the address of the data section to the linker for ATmega328

[Dylan McKay via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rG88b7b76a0b23: [AVR][clang] Pass the address of the data 
section to the linker for ATmega328 (authored by dylanmckay).

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Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/lib/Driver/ToolChains/AVR.cpp


Index: clang/lib/Driver/ToolChains/AVR.cpp
===
--- clang/lib/Driver/ToolChains/AVR.cpp
+++ clang/lib/Driver/ToolChains/AVR.cpp
@@ -13,6 +13,7 @@
 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
 #include "llvm/ADT/Optional.h"
+#include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/SubtargetFeature.h"
@@ -29,13 +30,20 @@
 
 // TODO: Consider merging this into the AVR device table
 // array in Targets/AVR.cpp.
-llvm::Optional GetMcuFamilyName(StringRef MCU) {
+llvm::Optional GetMCUFamilyName(StringRef MCU) {
   return llvm::StringSwitch>(MCU)
   .Case("atmega328", Optional("avr5"))
   .Case("atmega328p", Optional("avr5"))
   .Default(Optional());
 }
 
+llvm::Optional GetMCUSectionAddressData(StringRef MCU) {
+  return llvm::StringSwitch>(MCU)
+  .Case("atmega328", Optional(0x800100))
+  .Case("atmega328p", Optional(0x800100))
+  .Default(Optional());
+}
+
 const StringRef PossibleAVRLibcLocations[] = {
 "/usr/avr",
 "/usr/lib/avr",
@@ -59,7 +67,7 @@
   // We cannot link any standard libraries without an MCU specified.
   D.Diag(diag::warn_drv_avr_mcu_not_specified);
 } else {
-  Optional FamilyName = GetMcuFamilyName(CPU);
+  Optional FamilyName = GetMCUFamilyName(CPU);
   Optional AVRLibcRoot = findAVRLibcInstallation();
 
   if (!FamilyName.hasValue()) {
@@ -102,7 +110,8 @@
const char *LinkingOutput) const {
   // Compute information about the target AVR.
   std::string CPU = getCPUName(Args, getToolChain().getTriple());
-  llvm::Optional FamilyName = GetMcuFamilyName(CPU);
+  llvm::Optional FamilyName = GetMCUFamilyName(CPU);
+  llvm::Optional SectionAddressData = GetMCUSectionAddressData(CPU);
 
   std::string Linker = getToolChain().GetProgramPath(getShortName());
   ArgStringList CmdArgs;
@@ -118,6 +127,17 @@
   Args.AddAllArgs(CmdArgs, options::OPT_L);
   getToolChain().AddFilePathLibArgs(Args, CmdArgs);
 
+  if (SectionAddressData.hasValue()) {
+std::string DataSectionArg = std::string("-Tdata=0x") +
+ 
llvm::utohexstr(SectionAddressData.getValue());
+CmdArgs.push_back(Args.MakeArgString(DataSectionArg));
+  } else {
+// We do not have an entry for this CPU in the address mapping table yet.
+getToolChain().getDriver().Diag(
+diag::warn_drv_avr_linker_section_addresses_not_implemented)
+<< CPU;
+  }
+
   // If the family name is known, we can link with the device-specific libgcc.
   // Without it, libgcc will simply not be linked. This matches avr-gcc
   // behavior.
Index: clang/include/clang/Basic/DiagnosticDriverKinds.td
===
--- clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -44,6 +44,10 @@
 def warn_drv_avr_family_linking_stdlibs_not_implemented: Warning<
   "support for linking stdlibs for microcontroller '%0' is not implemented">,
   InGroup;
+def warn_drv_avr_linker_section_addresses_not_implemented: Warning<
+  "support for passing the data section address to the linker for "
+  "microcontroller '%0' is not implemented">,
+  InGroup;
 def warn_drv_avr_stdlib_not_linked: Warning<
   "standard library not linked and so no interrupt vector table or "
   "compiler runtime routines will be linked">,


Index: clang/lib/Driver/ToolChains/AVR.cpp
===
--- clang/lib/Driver/ToolChains/AVR.cpp
+++ clang/lib/Driver/ToolChains/AVR.cpp
@@ -13,6 +13,7 @@
 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
 #include "llvm/ADT/Optional.h"
+#include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/SubtargetFeature.h"
@@ -29,13 +30,20 @@
 
 // TODO: Consider merging this into the AVR device table
 // array in Targets/AVR.cpp.
-llvm::Optional GetMcuFamilyName(StringRef MCU) {
+llvm::Optional GetMCUFamilyName(StringRef MCU) {
   return llvm::StringSwitch>(MCU)
   .Case("atmega328", Optional("avr5"))
   .Case("atmega328p", Optional("avr5"))
   .Default(Optional());
 }
 
+llvm::Optional GetMCUSectionA

[PATCH] D97669: [clang][AVR] Add avr-libc/include to clang system include paths

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay accepted this revision.
dylanmckay added a comment.
This revision is now accepted and ready to land.

Looks good, nice and simple. Thanks @benshi001


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[PATCH] D93579: [clang][AVR] Improve avr-ld command line options

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay accepted this revision.
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This revision is now accepted and ready to land.

Great patch!


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[PATCH] D103136: [AVR] Add support for the tinyAVR 0-series and tinyAVR 1-seriesø

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay accepted this revision.
dylanmckay added a comment.
This revision is now accepted and ready to land.

Nope, thank you!


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[PATCH] D111566: [SYCL] Fix function pointer address space

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

This will product correct code from an AVR perspective where (before this patch 
it would have failed codegen). It is consistent with how we construct function 
pointers in LLVM core as well.

I'm not very familiar with Clang internals, one thing that stick out to me:

**The logic instead belongs directly inside the existing 
`getTargetAddressSpace` method?**

Perhaps the new `if (is function) { set address space to the value from the 
data layout}` logic belongs directly inside `ASTContext::getTargetAddressSpace` 
or one of its descendants in the call tree. This would obviously increase the 
scope/possible impact of the change further. The reason I suspect it belongs in 
there is that in theory, if this is the correct way to get the address space 
for a `QualType` (which may be a function) **in this instance**, then I feel 
that same logic would hold for any other `QualType` that may be a function 
pointer that has `getTargetAddressSpace()` called on it because I don't see 
anything special or unique about this existing call to `getTargetAddressSpace` 
versus any other existing call to it inside clang. If you implement it at that 
lower level inside `getTargetAddressSpace`, your conditional would be something 
like `QualType.getTypePtr()->isFunctionType()` etc.

This patch fixes one callsite of  `getTargetAddressSpace` but there are several 
other existing callsites remaining which if called with a function, they *would 
not* return the appropriate address space.

If someone more familar with clang than me disagrees please chime in


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[PATCH] D111566: [SYCL] Fix function pointer address space

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay accepted this revision.
dylanmckay added a comment.

By the way, as this has already been approved by one, and you rightly applied 
the "speak now or forever hold your peace" principle re. OpenCL, and this 
clearly works better from my point of view than the old code, I wouldn't want 
to prevent you from committing this. **I have no objections to merging this in 
its current state**. If you do merge it as-is though it would be nice if a 
follow up PR moves the logic into `getTargetAddressSpace()` where I think it 
better belongs


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[PATCH] D112113: [ObjC] type method metadata `_imp`, messenger routine at callsite with program address space

[Dylan McKay via Phabricator via cfe-commits]

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This revision is now accepted and ready to land.

LGTM, nice work.


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[PATCH] D76182: [AVR] Support aliases in non-zero address space

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

I think we should add a test, it shouldn't be too hard I think.

Look in `clang/tests`, grep for `alias`. Look like it is `extern const int 
__mod_usb_device_table __attribute__ ((alias("wacom_usb_ids")));`. If you copy 
paste a new test (use `clang/test/CodeGen/alias.c` as a reference. You can also 
look for files with `avr` in the name under the `test` folder to see how to add 
an AVR-specific test.

You should be able to 1) define a function alias of another function and 2) 
`CHECK` that the final IR has address space attributes, even when the alias 
symbol is used instead of the original symbol.


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[PATCH] D76182: [AVR] Support aliases in non-zero address space

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

Nice patch by the way, the code looks fine, if we can get a basic test in here 
then it's good to go


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[PATCH] D77119: [AVR] Fix function pointer address space

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

Nice work @vlastik, do you need someone to commit this for you?


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[PATCH] D77119: [AVR] Fix function pointer address space

[Dylan McKay via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG57fd86de879c: [AVR] Fix function pointer address space 
(authored by vlastik, committed by dylanmckay).

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Files:
  clang/lib/CodeGen/CodeGenTypes.cpp


Index: clang/lib/CodeGen/CodeGenTypes.cpp
===
--- clang/lib/CodeGen/CodeGenTypes.cpp
+++ clang/lib/CodeGen/CodeGenTypes.cpp
@@ -595,7 +595,11 @@
 llvm::Type *PointeeType = ConvertTypeForMem(ETy);
 if (PointeeType->isVoidTy())
   PointeeType = llvm::Type::getInt8Ty(getLLVMContext());
-unsigned AS = Context.getTargetAddressSpace(ETy);
+
+unsigned AS = PointeeType->isFunctionTy()
+  ? getDataLayout().getProgramAddressSpace()
+  : Context.getTargetAddressSpace(ETy);
+
 ResultType = llvm::PointerType::get(PointeeType, AS);
 break;
   }


Index: clang/lib/CodeGen/CodeGenTypes.cpp
===
--- clang/lib/CodeGen/CodeGenTypes.cpp
+++ clang/lib/CodeGen/CodeGenTypes.cpp
@@ -595,7 +595,11 @@
 llvm::Type *PointeeType = ConvertTypeForMem(ETy);
 if (PointeeType->isVoidTy())
   PointeeType = llvm::Type::getInt8Ty(getLLVMContext());
-unsigned AS = Context.getTargetAddressSpace(ETy);
+
+unsigned AS = PointeeType->isFunctionTy()
+  ? getDataLayout().getProgramAddressSpace()
+  : Context.getTargetAddressSpace(ETy);
+
 ResultType = llvm::PointerType::get(PointeeType, AS);
 break;
   }
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[PATCH] D27123: Add AVR target and toolchain to Clang

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

Signed off by Jonathan Roelofs via cfe-commits


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[PATCH] D27123: Add AVR target and toolchain to Clang

[Dylan McKay via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL291082: Add AVR target and toolchain to Clang (authored by 
dylanmckay).

Changed prior to commit:
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Files:
  cfe/trunk/lib/Basic/Targets.cpp
  cfe/trunk/lib/Driver/Driver.cpp
  cfe/trunk/lib/Driver/ToolChains.cpp
  cfe/trunk/lib/Driver/ToolChains.h
  cfe/trunk/lib/Driver/Tools.cpp
  cfe/trunk/lib/Driver/Tools.h
  cfe/trunk/test/Driver/avr-toolchain.c
  cfe/trunk/test/Preprocessor/init.c

Index: cfe/trunk/lib/Driver/ToolChains.h
===
--- cfe/trunk/lib/Driver/ToolChains.h
+++ cfe/trunk/lib/Driver/ToolChains.h
@@ -1349,6 +1349,16 @@
   SanitizerMask getSupportedSanitizers() const override;
 };
 
+class LLVM_LIBRARY_VISIBILITY AVRToolChain : public Generic_ELF {
+protected:
+  Tool *buildLinker() const override;
+public:
+  AVRToolChain(const Driver &D, const llvm::Triple &Triple,
+   const llvm::opt::ArgList &Args);
+  bool IsIntegratedAssemblerDefault() const override { return true; }
+};
+
+
 } // end namespace toolchains
 } // end namespace driver
 } // end namespace clang
Index: cfe/trunk/lib/Driver/Tools.h
===
--- cfe/trunk/lib/Driver/Tools.h
+++ cfe/trunk/lib/Driver/Tools.h
@@ -990,6 +990,19 @@
 
 }  // end namespace NVPTX
 
+namespace AVR {
+class LLVM_LIBRARY_VISIBILITY Linker : public GnuTool {
+public:
+  Linker(const ToolChain &TC) : GnuTool("AVR::Linker", "avr-ld", TC) {}
+  bool hasIntegratedCPP() const override { return false; }
+  bool isLinkJob() const override { return true; }
+  void ConstructJob(Compilation &C, const JobAction &JA,
+const InputInfo &Output, const InputInfoList &Inputs,
+const llvm::opt::ArgList &TCArgs,
+const char *LinkingOutput) const override;
+};
+} // end namespace AVR
+
 } // end namespace tools
 } // end namespace driver
 } // end namespace clang
Index: cfe/trunk/lib/Driver/ToolChains.cpp
===
--- cfe/trunk/lib/Driver/ToolChains.cpp
+++ cfe/trunk/lib/Driver/ToolChains.cpp
@@ -5318,3 +5318,12 @@
 Res |= SanitizerKind::SafeStack;
   return Res;
 }
+
+/// AVR Toolchain
+AVRToolChain::AVRToolChain(const Driver &D, const llvm::Triple &Triple,
+   const ArgList &Args)
+  : Generic_ELF(D, Triple, Args) { }
+Tool *AVRToolChain::buildLinker() const {
+  return new tools::AVR::Linker(*this);
+}
+// End AVR
Index: cfe/trunk/lib/Driver/Tools.cpp
===
--- cfe/trunk/lib/Driver/Tools.cpp
+++ cfe/trunk/lib/Driver/Tools.cpp
@@ -12191,3 +12191,19 @@
   const char *Exec = Args.MakeArgString(TC.GetProgramPath("fatbinary"));
   C.addCommand(llvm::make_unique(JA, *this, Exec, CmdArgs, Inputs));
 }
+
+void AVR::Linker::ConstructJob(Compilation &C, const JobAction &JA,
+   const InputInfo &Output,
+   const InputInfoList &Inputs,
+   const ArgList &Args,
+   const char *LinkingOutput) const {
+
+  std::string Linker = getToolChain().GetProgramPath(getShortName());
+  ArgStringList CmdArgs;
+  AddLinkerInputs(getToolChain(), Inputs, Args, CmdArgs, JA);
+  CmdArgs.push_back("-o");
+  CmdArgs.push_back(Output.getFilename());
+  C.addCommand(llvm::make_unique(JA, *this, Args.MakeArgString(Linker),
+  CmdArgs, Inputs));
+}
+// AVR tools end.
Index: cfe/trunk/lib/Driver/Driver.cpp
===
--- cfe/trunk/lib/Driver/Driver.cpp
+++ cfe/trunk/lib/Driver/Driver.cpp
@@ -3764,6 +3764,9 @@
   case llvm::Triple::wasm64:
 TC = new toolchains::WebAssembly(*this, Target, Args);
 break;
+  case llvm::Triple::avr:
+TC = new toolchains::AVRToolChain(*this, Target, Args);
+break;
   default:
 if (Target.getVendor() == llvm::Triple::Myriad)
   TC = new toolchains::MyriadToolChain(*this, Target, Args);
Index: cfe/trunk/lib/Basic/Targets.cpp
===
--- cfe/trunk/lib/Basic/Targets.cpp
+++ cfe/trunk/lib/Basic/Targets.cpp
@@ -8385,6 +8385,97 @@
   }
 };
 
+
+// AVR Target
+class AVRTargetInfo : public TargetInfo {
+public:
+  AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
+  : TargetInfo(Triple) {
+TLSSupported = false;
+PointerWidth = 16;
+PointerAlign = 8;
+IntWidth = 16;
+IntAlign = 8;
+LongWidth = 32;
+LongAlign = 8;
+LongLongWidth = 64;
+LongLongAlign = 8;
+SuitableAlign = 8;
+DefaultAlignForAttributeAligned = 8;
+HalfWidth = 16;
+HalfAlign = 8;
+FloatWidth = 32;

[PATCH] D28343: [AVR] Fix register numbers for in getGCCAddlRegNames()

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay created this revision.
dylanmckay added a reviewer: saaadhu.
dylanmckay added a subscriber: cfe-commits.

These do not match up with the register numbers defined in LLVM's
AVRRegisterInfo.td

Adding Senthil as a reviewer as he originally implemented this.


https://reviews.llvm.org/D28343

Files:
  lib/Basic/Targets.cpp


Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -8459,9 +8459,9 @@
   ArrayRef getGCCAddlRegNames() const override {
 static const TargetInfo::AddlRegName AddlRegNames[] = {
   { { "r26", "r27"}, 26 },
-  { { "r28", "r29"}, 27 },
-  { { "r30", "r31"}, 28 },
-  { { "SPL", "SPH"}, 29 },
+  { { "r28", "r29"}, 28 },
+  { { "r30", "r31"}, 30 },
+  { { "SPL", "SPH"}, 32 },
 };
 return llvm::makeArrayRef(AddlRegNames);
   }


Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -8459,9 +8459,9 @@
   ArrayRef getGCCAddlRegNames() const override {
 static const TargetInfo::AddlRegName AddlRegNames[] = {
   { { "r26", "r27"}, 26 },
-  { { "r28", "r29"}, 27 },
-  { { "r30", "r31"}, 28 },
-  { { "SPL", "SPH"}, 29 },
+  { { "r28", "r29"}, 28 },
+  { { "r30", "r31"}, 30 },
+  { { "SPL", "SPH"}, 32 },
 };
 return llvm::makeArrayRef(AddlRegNames);
   }
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D28344: [AVR] Add support for the full set of inline asm constraints

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay created this revision.
dylanmckay added a reviewer: jroelofs.
dylanmckay added subscribers: cfe-commits, saaadhu.

Previously the method would simply return false, causing every single
inline assembly constraint to trigger a compile error.

This adds inline assembly constraint support for the AVR target.

This patch is derived from the code in
AVRISelLowering::getConstraintType.

More details can be found on the AVR-GCC reference wiki
http://www.nongnu.org/avr-libc/user-manual/inline_asm.html


https://reviews.llvm.org/D28344

Files:
  lib/Basic/Targets.cpp


Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -8468,7 +8468,53 @@
 
   bool validateAsmConstraint(const char *&Name,
  TargetInfo::ConstraintInfo &Info) const override {
-return false;
+// There aren't any multi-character AVR specific constraints.
+if (StringRef(Name).size() > 1) return false;
+
+switch (*Name) {
+  default: return false;
+  case 'a': // Simple upper registers
+  case 'b': // Base pointer registers pairs
+  case 'd': // Upper register
+  case 'l': // Lower registers
+  case 'e': // Pointer register pairs
+  case 'q': // Stack pointer register
+  case 'r': // Any register
+  case 'w': // Special upper register pairs
+  case 't': // Temporary register
+  case 'x': case 'X': // Pointer register pair X
+  case 'y': case 'Y': // Pointer register pair Y
+  case 'z': case 'Z': // Pointer register pair Z
+Info.setAllowsRegister();
+return true;
+  case 'I': // 6-bit positive integer constant
+Info.setRequiresImmediate(0, 63);
+return true;
+  case 'J': // 6-bit negative integer constant
+Info.setRequiresImmediate(-63, 0);
+return true;
+  case 'K': // Integer constant (Range: 2)
+Info.setRequiresImmediate(2);
+return true;
+  case 'L': // Integer constant (Range: 0)
+Info.setRequiresImmediate(0);
+return true;
+  case 'M': // 8-bit integer constant
+Info.setRequiresImmediate(0, 0xff);
+return true;
+  case 'N': // Integer constant (Range: -1)
+Info.setRequiresImmediate(-1);
+  case 'O': // Integer constant (Range: 8, 16, 24)
+Info.setRequiresImmediate({8, 16, 24});
+  case 'P': // Integer constant (Range: 1)
+Info.setRequiresImmediate(1);
+  case 'R': // Integer constant (Range: -6 to 5)
+Info.setRequiresImmediate(-6, 5);
+return true;
+  case 'G': // Floating point constant
+  case 'Q': // A memory address based on Y or Z pointer with displacement.
+return true;
+}
   }
 
   IntType getIntTypeByWidth(unsigned BitWidth,


Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -8468,7 +8468,53 @@
 
   bool validateAsmConstraint(const char *&Name,
  TargetInfo::ConstraintInfo &Info) const override {
-return false;
+// There aren't any multi-character AVR specific constraints.
+if (StringRef(Name).size() > 1) return false;
+
+switch (*Name) {
+  default: return false;
+  case 'a': // Simple upper registers
+  case 'b': // Base pointer registers pairs
+  case 'd': // Upper register
+  case 'l': // Lower registers
+  case 'e': // Pointer register pairs
+  case 'q': // Stack pointer register
+  case 'r': // Any register
+  case 'w': // Special upper register pairs
+  case 't': // Temporary register
+  case 'x': case 'X': // Pointer register pair X
+  case 'y': case 'Y': // Pointer register pair Y
+  case 'z': case 'Z': // Pointer register pair Z
+Info.setAllowsRegister();
+return true;
+  case 'I': // 6-bit positive integer constant
+Info.setRequiresImmediate(0, 63);
+return true;
+  case 'J': // 6-bit negative integer constant
+Info.setRequiresImmediate(-63, 0);
+return true;
+  case 'K': // Integer constant (Range: 2)
+Info.setRequiresImmediate(2);
+return true;
+  case 'L': // Integer constant (Range: 0)
+Info.setRequiresImmediate(0);
+return true;
+  case 'M': // 8-bit integer constant
+Info.setRequiresImmediate(0, 0xff);
+return true;
+  case 'N': // Integer constant (Range: -1)
+Info.setRequiresImmediate(-1);
+  case 'O': // Integer constant (Range: 8, 16, 24)
+Info.setRequiresImmediate({8, 16, 24});
+  case 'P': // Integer constant (Range: 1)
+Info.setRequiresImmediate(1);
+  case 'R': // Integer constant (Range: -6 to 5)
+Info.setRequiresImmediate(-6, 5);
+return true;
+  case 'G': // Floating point constant
+  case 'Q': // A memory address based on Y or Z pointer with displace

[PATCH] D28346: [AVR] Allow specifying the CPU on the command line

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay created this revision.
dylanmckay added a reviewer: jroelofs.
dylanmckay added a subscriber: cfe-commits.

This tells clang about all of the different AVR microcontrollers.

It also adds code to define the correct preprocessor macros for each
device.


https://reviews.llvm.org/D28346

Files:
  lib/Basic/Targets.cpp

Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -8385,6 +8385,254 @@
   }
 };
 
+/// Information about a specific microcontroller.
+struct MCUInfo {
+  const char *Name;
+  const char *DefineName;
+};
+
+// This list should be kept up-to-date with AVRDevices.td in LLVM.
+static ArrayRef AVRMcus = {
+  { "at90s1200", "__AVR_AT90S1200__" },
+  { "attiny11", "__AVR_ATtiny11" },
+  { "attiny12", "__AVR_ATtiny12" },
+  { "attiny15", "__AVR_ATtiny15" },
+  { "attiny28", "__AVR_ATtiny28" },
+  { "at90s2313", "__AVR_AT90S2313" },
+  { "at90s2323", "__AVR_AT90S2323" },
+  { "at90s2333", "__AVR_AT90S2333" },
+  { "at90s2343", "__AVR_AT90S2343" },
+  { "attiny22", "__AVR_ATtiny22" },
+  { "attiny26", "__AVR_ATtiny26" },
+  { "at86rf401", "__AVR_AT86RF401" },
+  { "at90s4414", "__AVR_AT90S4414" },
+  { "at90s4433", "__AVR_AT90S4433" },
+  { "at90s4434", "__AVR_AT90S4434" },
+  { "at90s8515", "__AVR_AT90S8515" },
+  { "at90c8534", "__AVR_AT90c8534" },
+  { "at90s8535", "__AVR_AT90S8535" },
+  { "ata5272", "__AVR_ATA5272" },
+  { "attiny13", "__AVR_ATtiny13" },
+  { "attiny13a", "__AVR_ATtiny13A" },
+  { "attiny2313", "__AVR_ATtiny2313" },
+  { "attiny2313a", "__AVR_ATtiny2313A" },
+  { "attiny24", "__AVR_ATtiny24" },
+  { "attiny24a", "__AVR_ATtiny24A" },
+  { "attiny4313", "__AVR_ATtiny4313" },
+  { "attiny44", "__AVR_ATtiny44" },
+  { "attiny44a", "__AVR_ATtiny44A" },
+  { "attiny84", "__AVR_ATtiny84" },
+  { "attiny84a", "__AVR_ATtiny84A" },
+  { "attiny25", "__AVR_ATtiny25" },
+  { "attiny45", "__AVR_ATtiny45" },
+  { "attiny85", "__AVR_ATtiny85" },
+  { "attiny261", "__AVR_ATtiny261" },
+  { "attiny261a", "__AVR_ATtiny261A" },
+  { "attiny461", "__AVR_ATtiny461" },
+  { "attiny461a", "__AVR_ATtiny461A" },
+  { "attiny861", "__AVR_ATtiny861" },
+  { "attiny861a", "__AVR_ATtiny861A" },
+  { "attiny87", "__AVR_ATtiny87" },
+  { "attiny43u", "__AVR_ATtiny43U" },
+  { "attiny48", "__AVR_ATtiny48" },
+  { "attiny88", "__AVR_ATtiny88" },
+  { "attiny828", "__AVR_ATtiny828" },
+  { "at43usb355", "__AVR_AT43USB355" },
+  { "at76c711", "__AVR_AT76C711" },
+  { "atmega103", "__AVR_ATmega103" },
+  { "at43usb320", "__AVR_AT43USB320" },
+  { "attiny167", "__AVR_ATtiny167" },
+  { "at90usb82", "__AVR_AT90USB82" },
+  { "at90usb162", "__AVR_AT90USB162" },
+  { "ata5505", "__AVR_ATA5505" },
+  { "atmega8u2", "__AVR_ATmega8U2" },
+  { "atmega16u2", "__AVR_ATmega16U2" },
+  { "atmega32u2", "__AVR_ATmega32U2" },
+  { "attiny1634", "__AVR_ATtiny1634" },
+  { "atmega8", "__AVR_ATmega8" },
+  { "ata6289", "__AVR_ATA6289" },
+  { "atmega8a", "__AVR_ATmega8A" },
+  { "ata6285", "__AVR_ATA6285" },
+  { "ata6286", "__AVR_ATA6286" },
+  { "atmega48", "__AVR_ATmega48" },
+  { "atmega48a", "__AVR_ATmega48A" },
+  { "atmega48pa", "__AVR_ATmega48PA" },
+  { "atmega48p", "__AVR_ATmega48P" },
+  { "atmega88", "__AVR_ATmega88" },
+  { "atmega88a", "__AVR_ATmega88A" },
+  { "atmega88p", "__AVR_ATmega88P" },
+  { "atmega88pa", "__AVR_ATmega88PA" },
+  { "atmega8515", "__AVR_ATmega8515" },
+  { "atmega8535", "__AVR_ATmega8535" },
+  { "atmega8hva", "__AVR_ATmega8HVA" },
+  { "at90pwm1", "__AVR_AT90PWM1" },
+  { "at90pwm2", "__AVR_AT90PWM2" },
+  { "at90pwm2b", "__AVR_AT90PWM2B" },
+  { "at90pwm3", "__AVR_AT90PWM3" },
+  { "at90pwm3b", "__AVR_AT90PWM3B" },
+  { "at90pwm81", "__AVR_AT90PWM81" },
+  { "ata5790", "__AVR_ATA5790" },
+  { "ata5795", "__AVR_ATA5795" },
+  { "atmega16", "__AVR_ATmega16" },
+  { "atmega16a", "__AVR_ATmega16A" },
+  { "atmega161", "__AVR_ATmega161" },
+  { "atmega162", "__AVR_ATmega162" },
+  { "atmega163", "__AVR_ATmega163" },
+  { "atmega164a", "__AVR_ATmega164A" },
+  { "atmega164p", "__AVR_ATmega164P" },
+  { "atmega164pa", "__AVR_ATmega164PA" },
+  { "atmega165", "__AVR_ATmega165" },
+  { "atmega165a", "__AVR_ATmega165A" },
+  { "atmega165p", "__AVR_ATmega165P" },
+  { "atmega165pa", "__AVR_ATmega165PA" },
+  { "atmega168", "__AVR_ATmega168" },
+  { "atmega168a", "__AVR_ATmega168A" },
+  { "atmega168p", "__AVR_ATmega168P" },
+  { "atmega168pa", "__AVR_ATmega168PA" },
+  { "atmega169", "__AVR_ATmega169" },
+  { "atmega169a", "__AVR_ATmega169A" },
+  { "atmega169p", "__AVR_ATmega169P" },
+  { "atmega169pa", "__AVR_ATmega169PA" },
+  { "atmega32", "__AVR_ATmega32" },
+  { "atmega32a", "__AVR_ATmega32A" },
+  { "atmega323", "__AVR_ATmega323" },
+  { "atmega324a", "__AVR_ATmega324A" },
+  { "atmega324p", "__AVR_ATmega324P" },
+  { "atmega324pa", "__AVR_ATmega324PA" },
+  { "atmega325", "__AVR_ATmega325" },
+  { "atmega325a", "__AVR_ATmega325A" },
+  { "atmega325p", "__AVR_ATmega325P" },
+  { "atmega325

[PATCH] D28346: [AVR] Allow specifying the CPU on the command line

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 83496.
dylanmckay added a comment.

Add tests

This also defines the '__AVR' and 'AVR' values for all devices, to match what 
AVR-GCC does.


https://reviews.llvm.org/D28346

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/avr/target-cpu-defines/atmega328p.c
  test/CodeGen/avr/target-cpu-defines/attiny104.c
  test/CodeGen/avr/target-cpu-defines/common.c
  test/CodeGen/avr/target-cpu-families.c
  test/CodeGen/avr/target-cpus.c

Index: test/CodeGen/avr/target-cpus.c
===
--- /dev/null
+++ test/CodeGen/avr/target-cpus.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -target-cpu atmega328p -emit-llvm %s -o - | FileCheck %s --check-prefix=ATMEGA328P
+// RUN: %clang_cc1 -triple avr-unknown-unknown -target-cpu atxmega192d3 -emit-llvm %s -o - | FileCheck %s --check-prefix=ATXMEGA192D3
+// RUN: %clang_cc1 -triple avr-unknown-unknown -target-cpu attiny104 -emit-llvm %s -o - | FileCheck %s --check-prefix=ATTINY104
+
+// ATMEGA328P: hello_world
+// ATXMEGA192D3: hello_world
+// ATTINY104: hello_world
+void hello_world() { }
Index: test/CodeGen/avr/target-cpu-families.c
===
--- /dev/null
+++ test/CodeGen/avr/target-cpu-families.c
@@ -0,0 +1,14 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -target-cpu avr1 -emit-llvm %s -o - | FileCheck %s --check-prefix=AVR1
+// RUN: %clang_cc1 -triple avr-unknown-unknown -target-cpu avr3 -emit-llvm %s -o - | FileCheck %s --check-prefix=AVR3
+// RUN: %clang_cc1 -triple avr-unknown-unknown -target-cpu avr31 -emit-llvm %s -o - | FileCheck %s --check-prefix=AVR31
+// RUN: %clang_cc1 -triple avr-unknown-unknown -target-cpu avr5 -emit-llvm %s -o - | FileCheck %s --check-prefix=AVR5
+// RUN: %clang_cc1 -triple avr-unknown-unknown -target-cpu avrxmega6 -emit-llvm %s -o - | FileCheck %s --check-prefix=XMEGA6
+// RUN: %clang_cc1 -triple avr-unknown-unknown -target-cpu avrtiny -emit-llvm %s -o - | FileCheck %s --check-prefix=TINY
+
+// AVR1: hello_world
+// AVR3: hello_world
+// AVR31: hello_world
+// AVR5: hello_world
+// XMEGA6: hello_world
+// TINY: hello_world
+void hello_world() { }
Index: test/CodeGen/avr/target-cpu-defines/common.c
===
--- /dev/null
+++ test/CodeGen/avr/target-cpu-defines/common.c
@@ -0,0 +1,16 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+#ifndef __AVR
+#error '__AVR' is not defined
+#endif
+
+#ifndef AVR
+#error 'AVR' is not defined
+#endif
+
+#ifndef __AVR__
+#error '__AVR__' is not defind
+#endif
+
+// CHECK-LABEL: hello_world
+void hello_world() { }
Index: test/CodeGen/avr/target-cpu-defines/attiny104.c
===
--- /dev/null
+++ test/CodeGen/avr/target-cpu-defines/attiny104.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -target-cpu attiny104 -emit-llvm %s -o - | FileCheck %s
+
+#ifndef __AVR_ATtiny104
+#error '__AVR_ATtiny104' is not defined
+#endif
+
+// CHECK-LABEL: hello
+void hello() { }
Index: test/CodeGen/avr/target-cpu-defines/atmega328p.c
===
--- /dev/null
+++ test/CodeGen/avr/target-cpu-defines/atmega328p.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -target-cpu atmega328p -emit-llvm %s -o - | FileCheck %s
+
+#ifndef __AVR_ATmega328P
+#error '__AVR_ATmega328P' is not defined
+#endif
+
+// CHECK-LABEL: hello
+void hello() { }
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -8385,6 +8385,254 @@
   }
 };
 
+/// Information about a specific microcontroller.
+struct MCUInfo {
+  const char *Name;
+  const char *DefineName;
+};
+
+// This list should be kept up-to-date with AVRDevices.td in LLVM.
+static ArrayRef AVRMcus = {
+  { "at90s1200", "__AVR_AT90S1200__" },
+  { "attiny11", "__AVR_ATtiny11" },
+  { "attiny12", "__AVR_ATtiny12" },
+  { "attiny15", "__AVR_ATtiny15" },
+  { "attiny28", "__AVR_ATtiny28" },
+  { "at90s2313", "__AVR_AT90S2313" },
+  { "at90s2323", "__AVR_AT90S2323" },
+  { "at90s2333", "__AVR_AT90S2333" },
+  { "at90s2343", "__AVR_AT90S2343" },
+  { "attiny22", "__AVR_ATtiny22" },
+  { "attiny26", "__AVR_ATtiny26" },
+  { "at86rf401", "__AVR_AT86RF401" },
+  { "at90s4414", "__AVR_AT90S4414" },
+  { "at90s4433", "__AVR_AT90S4433" },
+  { "at90s4434", "__AVR_AT90S4434" },
+  { "at90s8515", "__AVR_AT90S8515" },
+  { "at90c8534", "__AVR_AT90c8534" },
+  { "at90s8535", "__AVR_AT90S8535" },
+  { "ata5272", "__AVR_ATA5272" },
+  { "attiny13", "__AVR_ATtiny13" },
+  { "attiny13a", "__AVR_ATtiny13A" },
+  { "attiny2313", "__AVR_ATtiny2313" },
+  { "attiny2313a", "__AVR_ATtiny2313A" },
+  { "attiny24", "__AVR_ATtiny24" },
+  { "attiny24a", "__AVR_ATtiny24A" },
+  { "attiny4313", "__AVR_ATtiny4313" },
+  {

[PATCH] D28344: [AVR] Add support for the full set of inline asm constraints

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 83504.
dylanmckay added a comment.

Fix a few cases of unintentional switch fallthrough


https://reviews.llvm.org/D28344

Files:
  lib/Basic/Targets.cpp


Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -8468,7 +8468,56 @@
 
   bool validateAsmConstraint(const char *&Name,
  TargetInfo::ConstraintInfo &Info) const override {
-return false;
+// There aren't any multi-character AVR specific constraints.
+if (StringRef(Name).size() > 1) return false;
+
+switch (*Name) {
+  default: return false;
+  case 'a': // Simple upper registers
+  case 'b': // Base pointer registers pairs
+  case 'd': // Upper register
+  case 'l': // Lower registers
+  case 'e': // Pointer register pairs
+  case 'q': // Stack pointer register
+  case 'r': // Any register
+  case 'w': // Special upper register pairs
+  case 't': // Temporary register
+  case 'x': case 'X': // Pointer register pair X
+  case 'y': case 'Y': // Pointer register pair Y
+  case 'z': case 'Z': // Pointer register pair Z
+Info.setAllowsRegister();
+return true;
+  case 'I': // 6-bit positive integer constant
+Info.setRequiresImmediate(0, 63);
+return true;
+  case 'J': // 6-bit negative integer constant
+Info.setRequiresImmediate(-63, 0);
+return true;
+  case 'K': // Integer constant (Range: 2)
+Info.setRequiresImmediate(2);
+return true;
+  case 'L': // Integer constant (Range: 0)
+Info.setRequiresImmediate(0);
+return true;
+  case 'M': // 8-bit integer constant
+Info.setRequiresImmediate(0, 0xff);
+return true;
+  case 'N': // Integer constant (Range: -1)
+Info.setRequiresImmediate(-1);
+return true;
+  case 'O': // Integer constant (Range: 8, 16, 24)
+Info.setRequiresImmediate({8, 16, 24});
+return true;
+  case 'P': // Integer constant (Range: 1)
+Info.setRequiresImmediate(1);
+return true;
+  case 'R': // Integer constant (Range: -6 to 5)
+Info.setRequiresImmediate(-6, 5);
+return true;
+  case 'G': // Floating point constant
+  case 'Q': // A memory address based on Y or Z pointer with displacement.
+return true;
+}
   }
 
   IntType getIntTypeByWidth(unsigned BitWidth,


Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -8468,7 +8468,56 @@
 
   bool validateAsmConstraint(const char *&Name,
  TargetInfo::ConstraintInfo &Info) const override {
-return false;
+// There aren't any multi-character AVR specific constraints.
+if (StringRef(Name).size() > 1) return false;
+
+switch (*Name) {
+  default: return false;
+  case 'a': // Simple upper registers
+  case 'b': // Base pointer registers pairs
+  case 'd': // Upper register
+  case 'l': // Lower registers
+  case 'e': // Pointer register pairs
+  case 'q': // Stack pointer register
+  case 'r': // Any register
+  case 'w': // Special upper register pairs
+  case 't': // Temporary register
+  case 'x': case 'X': // Pointer register pair X
+  case 'y': case 'Y': // Pointer register pair Y
+  case 'z': case 'Z': // Pointer register pair Z
+Info.setAllowsRegister();
+return true;
+  case 'I': // 6-bit positive integer constant
+Info.setRequiresImmediate(0, 63);
+return true;
+  case 'J': // 6-bit negative integer constant
+Info.setRequiresImmediate(-63, 0);
+return true;
+  case 'K': // Integer constant (Range: 2)
+Info.setRequiresImmediate(2);
+return true;
+  case 'L': // Integer constant (Range: 0)
+Info.setRequiresImmediate(0);
+return true;
+  case 'M': // 8-bit integer constant
+Info.setRequiresImmediate(0, 0xff);
+return true;
+  case 'N': // Integer constant (Range: -1)
+Info.setRequiresImmediate(-1);
+return true;
+  case 'O': // Integer constant (Range: 8, 16, 24)
+Info.setRequiresImmediate({8, 16, 24});
+return true;
+  case 'P': // Integer constant (Range: 1)
+Info.setRequiresImmediate(1);
+return true;
+  case 'R': // Integer constant (Range: -6 to 5)
+Info.setRequiresImmediate(-6, 5);
+return true;
+  case 'G': // Floating point constant
+  case 'Q': // A memory address based on Y or Z pointer with displacement.
+return true;
+}
   }
 
   IntType getIntTypeByWidth(unsigned BitWidth,
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[PATCH] D28344: [AVR] Add support for the full set of inline asm constraints

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 83507.
dylanmckay added a comment.

Add tests for inline assembly constraints


https://reviews.llvm.org/D28344

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/avr-inline-asm-constraints.c

Index: test/CodeGen/avr-inline-asm-constraints.c
===
--- /dev/null
+++ test/CodeGen/avr-inline-asm-constraints.c
@@ -0,0 +1,114 @@
+// REQUIRES: avr-registered-target
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm -o - %s | FileCheck %s
+
+int data;
+
+void a() {
+  // CHECK: call void asm sideeffect "add r5, $0", "a"(i16 %0)
+  asm("add r5, %0" :: "a"(data));
+}
+
+void b() {
+  // CHECK: call void asm sideeffect "add r5, $0", "b"(i16 %0)
+  asm("add r5, %0" :: "b"(data));
+}
+
+void d() {
+  // CHECK: call void asm sideeffect "add r5, $0", "d"(i16 %0)
+  asm("add r5, %0" :: "d"(data));
+}
+
+void l() {
+  // CHECK: call void asm sideeffect "add r5, $0", "l"(i16 %0)
+  asm("add r5, %0" :: "l"(data));
+}
+
+void e() {
+  // CHECK: call void asm sideeffect "add r5, $0", "e"(i16 %0)
+  asm("add r5, %0" :: "e"(data));
+}
+
+void q() {
+  // CHECK: call void asm sideeffect "add r5, $0", "q"(i16 %0)
+  asm("add r5, %0" :: "q"(data));
+}
+
+void r() {
+  // CHECK: call void asm sideeffect "add r5, $0", "r"(i16 %0)
+  asm("add r5, %0" :: "r"(data));
+}
+
+void w() {
+  // CHECK: call void asm sideeffect "add r5, $0", "w"(i16 %0)
+  asm("add r5, %0" :: "w"(data));
+}
+
+void t() {
+  // CHECK: call void asm sideeffect "add r5, $0", "t"(i16 %0)
+  asm("add r5, %0" :: "t"(data));
+}
+
+void x() {
+  // CHECK: call void asm sideeffect "add r5, $0", "x"(i16 %0)
+  asm("add r5, %0" :: "x"(data));
+}
+
+void y() {
+  // CHECK: call void asm sideeffect "add r5, $0", "y"(i16 %0)
+  asm("add r5, %0" :: "y"(data));
+}
+
+void z() {
+  // CHECK: call void asm sideeffect "add r5, $0", "z"(i16 %0)
+  asm("add r5, %0" :: "z"(data));
+}
+
+void I() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "I"(i16 50)
+  asm("subi r30, %0" :: "I"(50));
+}
+
+void J() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "J"(i16 -50)
+  asm("subi r30, %0" :: "J"(-50));
+}
+
+void K() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "K"(i16 2)
+  asm("subi r30, %0" :: "K"(2));
+}
+
+void L() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "L"(i16 0)
+  asm("subi r30, %0" :: "L"(0));
+}
+
+void M() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "M"(i16 255)
+  asm("subi r30, %0" :: "M"(255));
+}
+
+void O() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "O"(i16 16)
+  asm("subi r30, %0" :: "O"(16));
+}
+
+void P() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "P"(i16 1)
+  asm("subi r30, %0" :: "P"(1));
+}
+
+void R() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "R"(i16 -3)
+  asm("subi r30, %0" :: "R"(-3));
+}
+
+void G() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "G"(i16 50)
+  asm("subi r30, %0" :: "G"(50));
+}
+
+void Q() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "Q"(i16 50)
+  asm("subi r30, %0" :: "Q"(50));
+}
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -8468,7 +8468,56 @@
 
   bool validateAsmConstraint(const char *&Name,
  TargetInfo::ConstraintInfo &Info) const override {
-return false;
+// There aren't any multi-character AVR specific constraints.
+if (StringRef(Name).size() > 1) return false;
+
+switch (*Name) {
+  default: return false;
+  case 'a': // Simple upper registers
+  case 'b': // Base pointer registers pairs
+  case 'd': // Upper register
+  case 'l': // Lower registers
+  case 'e': // Pointer register pairs
+  case 'q': // Stack pointer register
+  case 'r': // Any register
+  case 'w': // Special upper register pairs
+  case 't': // Temporary register
+  case 'x': case 'X': // Pointer register pair X
+  case 'y': case 'Y': // Pointer register pair Y
+  case 'z': case 'Z': // Pointer register pair Z
+Info.setAllowsRegister();
+return true;
+  case 'I': // 6-bit positive integer constant
+Info.setRequiresImmediate(0, 63);
+return true;
+  case 'J': // 6-bit negative integer constant
+Info.setRequiresImmediate(-63, 0);
+return true;
+  case 'K': // Integer constant (Range: 2)
+Info.setRequiresImmediate(2);
+return true;
+  case 'L': // Integer constant (Range: 0)
+Info.setRequiresImmediate(0);
+return true;
+  case 'M': // 8-bit integer constant
+Info.setRequiresImmediate(0, 0xff);
+return true;
+  case 'N': // Integer constant (Range: -1)
+Info.setRequiresImmediate(-1);
+return true;
+  case 'O': // Integer constant (Range: 8, 16, 24)
+Info.setRequiresImmediate({8, 16, 24});
+r

[PATCH] D28344: [AVR] Add support for the full set of inline asm constraints

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay marked an inline comment as done.
dylanmckay added inline comments.



Comment at: lib/Basic/Targets.cpp:8506
+  case 'N': // Integer constant (Range: -1)
+Info.setRequiresImmediate(-1);
+  case 'O': // Integer constant (Range: 8, 16, 24)

ahatanak wrote:
> Is this meant to fall through or do you need a "break" here?
Nice catch, fixed


https://reviews.llvm.org/D28344



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[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay created this revision.
dylanmckay added a reviewer: aaron.ballman.
dylanmckay added a subscriber: cfe-commits.

This teaches clang how to parse and lower the 'interrupt' and 'naked'
attributes.

This allows interrupt signal handlers to be written.


https://reviews.llvm.org/D28451

Files:
  include/clang/Basic/Attr.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGen/avr/attributes/interrupt.c
  test/CodeGen/avr/attributes/naked.c

Index: test/CodeGen/avr/attributes/naked.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/naked.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((naked)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*naked.*}}}
Index: test/CodeGen/avr/attributes/interrupt.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/interrupt.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((interrupt)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*interrupt.*}}}
Index: lib/Sema/SemaDeclAttr.cpp
===
--- lib/Sema/SemaDeclAttr.cpp
+++ lib/Sema/SemaDeclAttr.cpp
@@ -5042,6 +5042,20 @@
   D->addAttr(UsedAttr::CreateImplicit(S.Context));
 }
 
+static void handleAVRInterruptAttr(Sema &S, Decl *D,
+   const AttributeList &Attr) {
+  D->addAttr(::new (S.Context)
+ AVRInterruptAttr(Attr.getLoc(), S.Context,
+  Attr.getAttributeSpellingListIndex()));
+}
+
+static void handleAVRSignalAttr(Sema &S, Decl *D,
+const AttributeList &Attr) {
+  D->addAttr(::new (S.Context)
+ AVRSignalAttr(Attr.getLoc(), S.Context,
+   Attr.getAttributeSpellingListIndex()));
+}
+
 static void handleInterruptAttr(Sema &S, Decl *D, const AttributeList &Attr) {
   // Dispatch the interrupt attribute based on the current target.
   switch (S.Context.getTargetInfo().getTriple().getArch()) {
@@ -5056,6 +5070,9 @@
   case llvm::Triple::x86_64:
 handleAnyX86InterruptAttr(S, D, Attr);
 break;
+  case llvm::Triple::avr:
+handleAVRInterruptAttr(S, D, Attr);
+break;
   default:
 handleARMInterruptAttr(S, D, Attr);
 break;
@@ -5616,6 +5633,9 @@
   case AttributeList::AT_AMDGPUNumVGPR:
 handleAMDGPUNumVGPRAttr(S, D, Attr);
 break;
+  case AttributeList::AT_AVRSignal:
+handleAVRSignalAttr(S, D, Attr);
+break;
   case AttributeList::AT_IBAction:
 handleSimpleAttribute(S, D, Attr);
 break;
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6884,6 +6884,29 @@
 }
 
 //===--===//
+// AVR ABI Implementation.
+//===--===//
+
+namespace {
+class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
+public:
+  AVRTargetCodeGenInfo(CodeGenTypes &CGT)
+: TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
+
+  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
+   CodeGen::CodeGenModule &CGM) const override {
+const FunctionDecl *FD = dyn_cast_or_null(D);
+if (!FD) return;
+llvm::Function *Fn = cast(GV);
+
+if (FD->getAttr()) {
+  Fn->addFnAttr("interrupt");
+}
+  }
+};
+}
+
+//===--===//
 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
 // Currently subclassed only to implement custom OpenCL C function attribute
 // handling.
@@ -8386,6 +8409,9 @@
   case llvm::Triple::mips64el:
 return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
 
+  case llvm::Triple::avr:
+return SetCGInfo(new AVRTargetCodeGenInfo(Types));
+
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_be: {
 AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
Index: include/clang/Basic/Attr.td
===
--- include/clang/Basic/Attr.td
+++ include/clang/Basic/Attr.td
@@ -255,6 +255,7 @@
   list CXXABIs;
 }
 def TargetARM : TargetArch<["arm", "thumb", "armeb", "thumbeb"]>;
+def TargetAVR : TargetArch<["avr"]>;
 def TargetMips : TargetArch<["mips", "mipsel"]>;
 def TargetMSP430 : TargetArch<["msp430"]>;
 def TargetX86 : TargetArch<["x86"]>;
@@ -477,6 +478,18 @@
   let Documentation = [ARMInterruptDocs];
 }
 
+def AVRInterrupt : InheritableAttr, TargetSpecificAttr {
+  let Spellings = [GNU<"interrupt">];
+  let Subjects = SubjectList<[Function]>;
+  let ParseKind = "Interrupt";
+  let Documentation =

[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 83544.
dylanmckay added a comment.

Lower the 'signal' attribute correctly

I had forgotten to lower this attribute and so it would not have been lowered 
to IR at all.

Now it works fine.


https://reviews.llvm.org/D28451

Files:
  include/clang/Basic/Attr.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGen/avr/attributes/interrupt.c
  test/CodeGen/avr/attributes/naked.c
  test/CodeGen/avr/attributes/signal.c

Index: test/CodeGen/avr/attributes/signal.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/signal.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((signal)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*signal.*}}}
Index: test/CodeGen/avr/attributes/naked.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/naked.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((naked)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*naked.*}}}
Index: test/CodeGen/avr/attributes/interrupt.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/interrupt.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((interrupt)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*interrupt.*}}}
Index: lib/Sema/SemaDeclAttr.cpp
===
--- lib/Sema/SemaDeclAttr.cpp
+++ lib/Sema/SemaDeclAttr.cpp
@@ -5042,6 +5042,20 @@
   D->addAttr(UsedAttr::CreateImplicit(S.Context));
 }
 
+static void handleAVRInterruptAttr(Sema &S, Decl *D,
+   const AttributeList &Attr) {
+  D->addAttr(::new (S.Context)
+ AVRInterruptAttr(Attr.getLoc(), S.Context,
+  Attr.getAttributeSpellingListIndex()));
+}
+
+static void handleAVRSignalAttr(Sema &S, Decl *D,
+const AttributeList &Attr) {
+  D->addAttr(::new (S.Context)
+ AVRSignalAttr(Attr.getLoc(), S.Context,
+   Attr.getAttributeSpellingListIndex()));
+}
+
 static void handleInterruptAttr(Sema &S, Decl *D, const AttributeList &Attr) {
   // Dispatch the interrupt attribute based on the current target.
   switch (S.Context.getTargetInfo().getTriple().getArch()) {
@@ -5056,6 +5070,9 @@
   case llvm::Triple::x86_64:
 handleAnyX86InterruptAttr(S, D, Attr);
 break;
+  case llvm::Triple::avr:
+handleAVRInterruptAttr(S, D, Attr);
+break;
   default:
 handleARMInterruptAttr(S, D, Attr);
 break;
@@ -5616,6 +5633,9 @@
   case AttributeList::AT_AMDGPUNumVGPR:
 handleAMDGPUNumVGPRAttr(S, D, Attr);
 break;
+  case AttributeList::AT_AVRSignal:
+handleAVRSignalAttr(S, D, Attr);
+break;
   case AttributeList::AT_IBAction:
 handleSimpleAttribute(S, D, Attr);
 break;
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6884,6 +6884,31 @@
 }
 
 //===--===//
+// AVR ABI Implementation.
+//===--===//
+
+namespace {
+class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
+public:
+  AVRTargetCodeGenInfo(CodeGenTypes &CGT)
+: TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
+
+  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
+   CodeGen::CodeGenModule &CGM) const override {
+const FunctionDecl *FD = dyn_cast_or_null(D);
+if (!FD) return;
+llvm::Function *Fn = cast(GV);
+
+if (FD->getAttr())
+  Fn->addFnAttr("interrupt");
+
+if (FD->getAttr())
+  Fn->addFnAttr("signal");
+  }
+};
+}
+
+//===--===//
 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
 // Currently subclassed only to implement custom OpenCL C function attribute
 // handling.
@@ -8386,6 +8411,9 @@
   case llvm::Triple::mips64el:
 return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
 
+  case llvm::Triple::avr:
+return SetCGInfo(new AVRTargetCodeGenInfo(Types));
+
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_be: {
 AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
Index: include/clang/Basic/Attr.td
===
--- include/clang/Basic/Attr.td
+++ include/clang/Basic/Attr.td
@@ -255,6 +255,7 @@
   list CXXABIs;
 }
 def TargetARM : TargetArch<["arm", "thumb", "armeb

[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 83913.
dylanmckay marked 2 inline comments as done.
dylanmckay added a comment.

[AVR] Document the 'interrupt' and 'naked' attributes


https://reviews.llvm.org/D28451

Files:
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGen/avr/attributes/interrupt.c
  test/CodeGen/avr/attributes/naked.c
  test/CodeGen/avr/attributes/signal.c

Index: test/CodeGen/avr/attributes/signal.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/signal.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((signal)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*signal.*}}}
Index: test/CodeGen/avr/attributes/naked.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/naked.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((naked)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*naked.*}}}
Index: test/CodeGen/avr/attributes/interrupt.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/interrupt.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((interrupt)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*interrupt.*}}}
Index: lib/Sema/SemaDeclAttr.cpp
===
--- lib/Sema/SemaDeclAttr.cpp
+++ lib/Sema/SemaDeclAttr.cpp
@@ -5126,6 +5126,20 @@
   D->addAttr(UsedAttr::CreateImplicit(S.Context));
 }
 
+static void handleAVRInterruptAttr(Sema &S, Decl *D,
+   const AttributeList &Attr) {
+  D->addAttr(::new (S.Context)
+ AVRInterruptAttr(Attr.getLoc(), S.Context,
+  Attr.getAttributeSpellingListIndex()));
+}
+
+static void handleAVRSignalAttr(Sema &S, Decl *D,
+const AttributeList &Attr) {
+  D->addAttr(::new (S.Context)
+ AVRSignalAttr(Attr.getLoc(), S.Context,
+   Attr.getAttributeSpellingListIndex()));
+}
+
 static void handleInterruptAttr(Sema &S, Decl *D, const AttributeList &Attr) {
   // Dispatch the interrupt attribute based on the current target.
   switch (S.Context.getTargetInfo().getTriple().getArch()) {
@@ -5140,6 +5154,9 @@
   case llvm::Triple::x86_64:
 handleAnyX86InterruptAttr(S, D, Attr);
 break;
+  case llvm::Triple::avr:
+handleAVRInterruptAttr(S, D, Attr);
+break;
   default:
 handleARMInterruptAttr(S, D, Attr);
 break;
@@ -5700,6 +5717,9 @@
   case AttributeList::AT_AMDGPUNumVGPR:
 handleAMDGPUNumVGPRAttr(S, D, Attr);
 break;
+  case AttributeList::AT_AVRSignal:
+handleAVRSignalAttr(S, D, Attr);
+break;
   case AttributeList::AT_IBAction:
 handleSimpleAttribute(S, D, Attr);
 break;
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6884,6 +6884,31 @@
 }
 
 //===--===//
+// AVR ABI Implementation.
+//===--===//
+
+namespace {
+class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
+public:
+  AVRTargetCodeGenInfo(CodeGenTypes &CGT)
+: TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
+
+  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
+   CodeGen::CodeGenModule &CGM) const override {
+const FunctionDecl *FD = dyn_cast_or_null(D);
+if (!FD) return;
+llvm::Function *Fn = cast(GV);
+
+if (FD->getAttr())
+  Fn->addFnAttr("interrupt");
+
+if (FD->getAttr())
+  Fn->addFnAttr("signal");
+  }
+};
+}
+
+//===--===//
 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
 // Currently subclassed only to implement custom OpenCL C function attribute
 // handling.
@@ -8386,6 +8411,9 @@
   case llvm::Triple::mips64el:
 return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
 
+  case llvm::Triple::avr:
+return SetCGInfo(new AVRTargetCodeGenInfo(Types));
+
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_be: {
 AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
Index: include/clang/Basic/AttrDocs.td
===
--- include/clang/Basic/AttrDocs.td
+++ include/clang/Basic/AttrDocs.td
@@ -1181,6 +1181,33 @@
   }];
 }
 
+def AVRInterruptDocs : Documentation {
+  let Category = DocCat

[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added inline comments.



Comment at: include/clang/Basic/Attr.td:488
+
+def AVRSignal : InheritableAttr, TargetSpecificAttr {
+  let Spellings = [GNU<"signal">];

aaron.ballman wrote:
> Does this attribute appertain to any specific subjects, or can you apply it 
> to any declaration?
It can be applied to function definitions only.



Comment at: test/CodeGen/avr/attributes/naked.c:4
+// CHECK: define void @foo() #0
+__attribute__((naked)) void foo(void) { }
+

aaron.ballman wrote:
> This test seems unrelated as you didn't modify anything about the naked 
> attribute?
I didn't modify the naked attribute, but I did want to include a test for AVR.


https://reviews.llvm.org/D28451



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[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 85051.
dylanmckay marked 5 inline comments as done.
dylanmckay added a comment.

Code review from Aaron

- Use 'handleSimpleAttribute' rather than duplicating it
- Use 'auto' where a type is explicitly casted
- Add warnings for when the attribute is not on a function
- Add sema tests for when the attr is not on a function


https://reviews.llvm.org/D28451

Files:
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGen/avr/attributes/interrupt.c
  test/CodeGen/avr/attributes/naked.c
  test/CodeGen/avr/attributes/signal.c
  test/Sema/avr-interrupt-attr.c
  test/Sema/avr-signal-attr.c

Index: test/Sema/avr-signal-attr.c
===
--- /dev/null
+++ test/Sema/avr-signal-attr.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((signal)); // expected-warning {{'signal' attribute only applies to functions and methods}}
+
+__attribute__((signal)) void food() {}
Index: test/Sema/avr-interrupt-attr.c
===
--- /dev/null
+++ test/Sema/avr-interrupt-attr.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((interrupt)); // expected-warning {{'interrupt' attribute only applies to functions and methods}}
+
+__attribute__((interrupt)) void food() {}
Index: test/CodeGen/avr/attributes/signal.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/signal.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((signal)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*signal.*}}}
Index: test/CodeGen/avr/attributes/naked.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/naked.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((naked)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*naked.*}}}
Index: test/CodeGen/avr/attributes/interrupt.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/interrupt.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((interrupt)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*interrupt.*}}}
Index: lib/Sema/SemaDeclAttr.cpp
===
--- lib/Sema/SemaDeclAttr.cpp
+++ lib/Sema/SemaDeclAttr.cpp
@@ -5140,6 +5140,15 @@
   case llvm::Triple::x86_64:
 handleAnyX86InterruptAttr(S, D, Attr);
 break;
+  case llvm::Triple::avr:
+if (!isFunctionOrMethod(D)) {
+  S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+  << "'interrupt'" << ExpectedFunctionOrMethod;
+  return;
+}
+
+handleSimpleAttribute(S, D, Attr);
+break;
   default:
 handleARMInterruptAttr(S, D, Attr);
 break;
@@ -5700,6 +5709,14 @@
   case AttributeList::AT_AMDGPUNumVGPR:
 handleAMDGPUNumVGPRAttr(S, D, Attr);
 break;
+  case AttributeList::AT_AVRSignal:
+if (!isFunctionOrMethod(D)) {
+  S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+  << "'signal'" << ExpectedFunctionOrMethod;
+  return;
+}
+handleSimpleAttribute(S, D, Attr);
+break;
   case AttributeList::AT_IBAction:
 handleSimpleAttribute(S, D, Attr);
 break;
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6900,6 +6900,31 @@
 }
 
 //===--===//
+// AVR ABI Implementation.
+//===--===//
+
+namespace {
+class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
+public:
+  AVRTargetCodeGenInfo(CodeGenTypes &CGT)
+: TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
+
+  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
+   CodeGen::CodeGenModule &CGM) const override {
+const auto *FD = dyn_cast_or_null(D);
+if (!FD) return;
+llvm::Function *Fn = cast(GV);
+
+if (FD->getAttr())
+  Fn->addFnAttr("interrupt");
+
+if (FD->getAttr())
+  Fn->addFnAttr("signal");
+  }
+};
+}
+
+//===--===//
 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
 // Currently subclassed only to implement custom OpenCL C function 

[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 85052.
dylanmckay added a comment.

Remove a test for the 'naked' attribute


https://reviews.llvm.org/D28451

Files:
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGen/avr/attributes/interrupt.c
  test/CodeGen/avr/attributes/signal.c
  test/Sema/avr-interrupt-attr.c
  test/Sema/avr-signal-attr.c

Index: test/Sema/avr-signal-attr.c
===
--- /dev/null
+++ test/Sema/avr-signal-attr.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((signal)); // expected-warning {{'signal' attribute only applies to functions and methods}}
+
+__attribute__((signal)) void food() {}
Index: test/Sema/avr-interrupt-attr.c
===
--- /dev/null
+++ test/Sema/avr-interrupt-attr.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((interrupt)); // expected-warning {{'interrupt' attribute only applies to functions and methods}}
+
+__attribute__((interrupt)) void food() {}
Index: test/CodeGen/avr/attributes/signal.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/signal.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((signal)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*signal.*}}}
Index: test/CodeGen/avr/attributes/interrupt.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/interrupt.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((interrupt)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*interrupt.*}}}
Index: lib/Sema/SemaDeclAttr.cpp
===
--- lib/Sema/SemaDeclAttr.cpp
+++ lib/Sema/SemaDeclAttr.cpp
@@ -5140,6 +5140,15 @@
   case llvm::Triple::x86_64:
 handleAnyX86InterruptAttr(S, D, Attr);
 break;
+  case llvm::Triple::avr:
+if (!isFunctionOrMethod(D)) {
+  S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+  << "'interrupt'" << ExpectedFunctionOrMethod;
+  return;
+}
+
+handleSimpleAttribute(S, D, Attr);
+break;
   default:
 handleARMInterruptAttr(S, D, Attr);
 break;
@@ -5700,6 +5709,14 @@
   case AttributeList::AT_AMDGPUNumVGPR:
 handleAMDGPUNumVGPRAttr(S, D, Attr);
 break;
+  case AttributeList::AT_AVRSignal:
+if (!isFunctionOrMethod(D)) {
+  S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+  << "'signal'" << ExpectedFunctionOrMethod;
+  return;
+}
+handleSimpleAttribute(S, D, Attr);
+break;
   case AttributeList::AT_IBAction:
 handleSimpleAttribute(S, D, Attr);
 break;
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6900,6 +6900,31 @@
 }
 
 //===--===//
+// AVR ABI Implementation.
+//===--===//
+
+namespace {
+class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
+public:
+  AVRTargetCodeGenInfo(CodeGenTypes &CGT)
+: TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
+
+  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
+   CodeGen::CodeGenModule &CGM) const override {
+const auto *FD = dyn_cast_or_null(D);
+if (!FD) return;
+llvm::Function *Fn = cast(GV);
+
+if (FD->getAttr())
+  Fn->addFnAttr("interrupt");
+
+if (FD->getAttr())
+  Fn->addFnAttr("signal");
+  }
+};
+}
+
+//===--===//
 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
 // Currently subclassed only to implement custom OpenCL C function attribute
 // handling.
@@ -8402,6 +8427,9 @@
   case llvm::Triple::mips64el:
 return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
 
+  case llvm::Triple::avr:
+return SetCGInfo(new AVRTargetCodeGenInfo(Types));
+
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_be: {
 AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
Index: include/clang/Basic/AttrDocs.td
===
--- include/clang/Basic/AttrDocs.td
+++ include/clang/Basic/AttrDocs.td
@@ -1182,6 +1182,33 @@
   }];
 }
 
+def AVRInterruptDocs : Documentation {
+  let Category = DocCatFunction;
+  let Content = [{
+Clang su

[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 85053.
dylanmckay added a comment.

Add 'Subjects' field to 'AVRSignal'


https://reviews.llvm.org/D28451

Files:
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGen/avr/attributes/interrupt.c
  test/CodeGen/avr/attributes/signal.c
  test/Sema/avr-interrupt-attr.c
  test/Sema/avr-signal-attr.c

Index: test/Sema/avr-signal-attr.c
===
--- /dev/null
+++ test/Sema/avr-signal-attr.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((signal)); // expected-warning {{'signal' attribute only applies to functions and methods}}
+
+__attribute__((signal)) void food() {}
Index: test/Sema/avr-interrupt-attr.c
===
--- /dev/null
+++ test/Sema/avr-interrupt-attr.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((interrupt)); // expected-warning {{'interrupt' attribute only applies to functions and methods}}
+
+__attribute__((interrupt)) void food() {}
Index: test/CodeGen/avr/attributes/signal.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/signal.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((signal)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*signal.*}}}
Index: test/CodeGen/avr/attributes/interrupt.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/interrupt.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((interrupt)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*interrupt.*}}}
Index: lib/Sema/SemaDeclAttr.cpp
===
--- lib/Sema/SemaDeclAttr.cpp
+++ lib/Sema/SemaDeclAttr.cpp
@@ -5140,6 +5140,15 @@
   case llvm::Triple::x86_64:
 handleAnyX86InterruptAttr(S, D, Attr);
 break;
+  case llvm::Triple::avr:
+if (!isFunctionOrMethod(D)) {
+  S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+  << "'interrupt'" << ExpectedFunctionOrMethod;
+  return;
+}
+
+handleSimpleAttribute(S, D, Attr);
+break;
   default:
 handleARMInterruptAttr(S, D, Attr);
 break;
@@ -5700,6 +5709,14 @@
   case AttributeList::AT_AMDGPUNumVGPR:
 handleAMDGPUNumVGPRAttr(S, D, Attr);
 break;
+  case AttributeList::AT_AVRSignal:
+if (!isFunctionOrMethod(D)) {
+  S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+  << "'signal'" << ExpectedFunctionOrMethod;
+  return;
+}
+handleSimpleAttribute(S, D, Attr);
+break;
   case AttributeList::AT_IBAction:
 handleSimpleAttribute(S, D, Attr);
 break;
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6900,6 +6900,31 @@
 }
 
 //===--===//
+// AVR ABI Implementation.
+//===--===//
+
+namespace {
+class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
+public:
+  AVRTargetCodeGenInfo(CodeGenTypes &CGT)
+: TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
+
+  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
+   CodeGen::CodeGenModule &CGM) const override {
+const auto *FD = dyn_cast_or_null(D);
+if (!FD) return;
+llvm::Function *Fn = cast(GV);
+
+if (FD->getAttr())
+  Fn->addFnAttr("interrupt");
+
+if (FD->getAttr())
+  Fn->addFnAttr("signal");
+  }
+};
+}
+
+//===--===//
 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
 // Currently subclassed only to implement custom OpenCL C function attribute
 // handling.
@@ -8402,6 +8427,9 @@
   case llvm::Triple::mips64el:
 return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
 
+  case llvm::Triple::avr:
+return SetCGInfo(new AVRTargetCodeGenInfo(Types));
+
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_be: {
 AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
Index: include/clang/Basic/AttrDocs.td
===
--- include/clang/Basic/AttrDocs.td
+++ include/clang/Basic/AttrDocs.td
@@ -1182,6 +1182,33 @@
   }];
 }
 
+def AVRInterruptDocs : Documentation {
+  let Category = DocCatFunction;
+  let Content = [{
+Clang suppor

[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added inline comments.



Comment at: lib/Sema/SemaDeclAttr.cpp:5145
+if (!isFunctionOrMethod(D)) {
+  S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+  << "'interrupt'" << ExpectedFunctionOrMethod;

I'm pretty sure that this check shouldn't be necessary, because we define 
`Subjects = [Function]` in TableGen.

Without it though, the warning doesn't appear. Do you know why that is 
@aaron.ballman?


https://reviews.llvm.org/D28451



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[PATCH] D28346: [AVR] Allow specifying the CPU on the command line

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

Ping


https://reviews.llvm.org/D28346



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[PATCH] D28344: [AVR] Add support for the full set of inline asm constraints

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay marked an inline comment as done.
dylanmckay added a comment.

Ping


https://reviews.llvm.org/D28344



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[PATCH] D28344: [AVR] Add support for the full set of inline asm constraints

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay marked an inline comment as done.
dylanmckay added a comment.

Ping


https://reviews.llvm.org/D28344



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[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 87054.
dylanmckay marked 5 inline comments as done.
dylanmckay added a comment.

Code review comments

- Add 'Subjects = [ObjCMethod]' to attributes
- Use 'auto' keyword in one place
- Move complex attr parsing logic into static function


https://reviews.llvm.org/D28451

Files:
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGen/avr/attributes/interrupt.c
  test/CodeGen/avr/attributes/signal.c
  test/Sema/avr-interrupt-attr.c
  test/Sema/avr-signal-attr.c

Index: test/Sema/avr-signal-attr.c
===
--- /dev/null
+++ test/Sema/avr-signal-attr.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((signal)); // expected-warning {{'signal' attribute only applies to functions and methods}}
+
+__attribute__((signal)) void food() {}
Index: test/Sema/avr-interrupt-attr.c
===
--- /dev/null
+++ test/Sema/avr-interrupt-attr.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((interrupt)); // expected-warning {{'interrupt' attribute only applies to functions and methods}}
+
+__attribute__((interrupt)) void food() {}
Index: test/CodeGen/avr/attributes/signal.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/signal.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((signal)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*signal.*}}}
Index: test/CodeGen/avr/attributes/interrupt.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/interrupt.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((interrupt)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*interrupt.*}}}
Index: lib/Sema/SemaDeclAttr.cpp
===
--- lib/Sema/SemaDeclAttr.cpp
+++ lib/Sema/SemaDeclAttr.cpp
@@ -5126,6 +5126,26 @@
   D->addAttr(UsedAttr::CreateImplicit(S.Context));
 }
 
+static void handleAVRInterruptAttr(Sema &S, Decl *D, const AttributeList &Attr) {
+  if (!isFunctionOrMethod(D)) {
+S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+<< "'interrupt'" << ExpectedFunctionOrMethod;
+return;
+  }
+
+  handleSimpleAttribute(S, D, Attr);
+}
+
+static void handleAVRSignalAttr(Sema &S, Decl *D, const AttributeList &Attr) {
+  if (!isFunctionOrMethod(D)) {
+S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+<< "'signal'" << ExpectedFunctionOrMethod;
+return;
+  }
+
+  handleSimpleAttribute(S, D, Attr);
+}
+
 static void handleInterruptAttr(Sema &S, Decl *D, const AttributeList &Attr) {
   // Dispatch the interrupt attribute based on the current target.
   switch (S.Context.getTargetInfo().getTriple().getArch()) {
@@ -5140,6 +5160,9 @@
   case llvm::Triple::x86_64:
 handleAnyX86InterruptAttr(S, D, Attr);
 break;
+  case llvm::Triple::avr:
+handleAVRInterruptAttr(S, D, Attr);
+break;
   default:
 handleARMInterruptAttr(S, D, Attr);
 break;
@@ -5700,6 +5723,9 @@
   case AttributeList::AT_AMDGPUNumVGPR:
 handleAMDGPUNumVGPRAttr(S, D, Attr);
 break;
+  case AttributeList::AT_AVRSignal:
+handleAVRSignalAttr(S, D, Attr);
+break;
   case AttributeList::AT_IBAction:
 handleSimpleAttribute(S, D, Attr);
 break;
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6900,6 +6900,31 @@
 }
 
 //===--===//
+// AVR ABI Implementation.
+//===--===//
+
+namespace {
+class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
+public:
+  AVRTargetCodeGenInfo(CodeGenTypes &CGT)
+: TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
+
+  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
+   CodeGen::CodeGenModule &CGM) const override {
+const auto *FD = dyn_cast_or_null(D);
+if (!FD) return;
+auto *Fn = cast(GV);
+
+if (FD->getAttr())
+  Fn->addFnAttr("interrupt");
+
+if (FD->getAttr())
+  Fn->addFnAttr("signal");
+  }
+};
+}
+
+//===--===//
 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
 // Currently subclassed only to implement custom OpenCL C function at

[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 87164.
dylanmckay marked 2 inline comments as done.
dylanmckay added a comment.

Verify that no arguments are given to the attributes

Also adds a bunch of tests.


https://reviews.llvm.org/D28451

Files:
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGen/avr/attributes/interrupt-no-args.c
  test/CodeGen/avr/attributes/interrupt.c
  test/CodeGen/avr/attributes/interrupt.m
  test/CodeGen/avr/attributes/signal-no-args.c
  test/CodeGen/avr/attributes/signal.c
  test/CodeGen/avr/attributes/signal.m
  test/Sema/avr-interrupt-attr.c
  test/Sema/avr-signal-attr.c

Index: test/Sema/avr-signal-attr.c
===
--- /dev/null
+++ test/Sema/avr-signal-attr.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((signal)); // expected-warning {{'signal' attribute only applies to functions and methods}}
+
+__attribute__((signal)) void food() {}
Index: test/Sema/avr-interrupt-attr.c
===
--- /dev/null
+++ test/Sema/avr-interrupt-attr.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((interrupt)); // expected-warning {{'interrupt' attribute only applies to functions and methods}}
+
+__attribute__((interrupt)) void food() {}
Index: test/CodeGen/avr/attributes/signal.m
===
--- /dev/null
+++ test/CodeGen/avr/attributes/signal.m
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -x objective-c++ -emit-llvm -o - %s | FileCheck %s
+
+// CHECK: define void @_Z3foov() #0
+void foo() __attribute__((signal)) { }
+
+// CHECK: attributes #0 = {{{.*signal.*}}}
Index: test/CodeGen/avr/attributes/signal.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/signal.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((signal)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*signal.*}}}
Index: test/CodeGen/avr/attributes/signal-no-args.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/signal-no-args.c
@@ -0,0 +1,4 @@
+// RUN: not %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - 2>&1 | FileCheck %s
+
+// CHECK: error: 'signal' attribute takes no arguments
+__attribute__((signal(12))) void foo(void) { }
Index: test/CodeGen/avr/attributes/interrupt.m
===
--- /dev/null
+++ test/CodeGen/avr/attributes/interrupt.m
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -x objective-c++ -emit-llvm -o - %s | FileCheck %s
+
+// CHECK: define void @_Z3foov() #0
+void foo() __attribute__((interrupt)) { }
+
+// CHECK: attributes #0 = {{{.*interrupt.*}}}
Index: test/CodeGen/avr/attributes/interrupt.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/interrupt.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((interrupt)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*interrupt.*}}}
Index: test/CodeGen/avr/attributes/interrupt-no-args.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/interrupt-no-args.c
@@ -0,0 +1,4 @@
+// RUN: not %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - 2>&1 | FileCheck %s
+
+// CHECK: error: 'interrupt' attribute takes no arguments
+__attribute__((interrupt(12))) void foo(void) { }
Index: lib/Sema/SemaDeclAttr.cpp
===
--- lib/Sema/SemaDeclAttr.cpp
+++ lib/Sema/SemaDeclAttr.cpp
@@ -5126,6 +5126,32 @@
   D->addAttr(UsedAttr::CreateImplicit(S.Context));
 }
 
+static void handleAVRInterruptAttr(Sema &S, Decl *D, const AttributeList &Attr) {
+  if (!isFunctionOrMethod(D)) {
+S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+<< "'interrupt'" << ExpectedFunctionOrMethod;
+return;
+  }
+
+  if (!checkAttributeNumArgs(S, Attr, 0))
+Attr.setInvalid();
+
+  handleSimpleAttribute(S, D, Attr);
+}
+
+static void handleAVRSignalAttr(Sema &S, Decl *D, const AttributeList &Attr) {
+  if (!isFunctionOrMethod(D)) {
+S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+<< "'signal'" << ExpectedFunctionOrMethod;
+return;
+  }
+
+  if (!checkAttributeNumArgs(S, Attr, 0))
+Attr.setInvalid();
+
+  handleSimpleAttribute(S, D, Attr);
+}
+
 static void handleInterruptAttr(Sema &S, Dec

[PATCH] D28346: [AVR] Allow specifying the CPU on the command line

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay marked 2 inline comments as done.
dylanmckay added inline comments.



Comment at: test/CodeGen/avr/target-cpu-defines/atmega328p.c:1
+// RUN: %clang_cc1 -triple avr-unknown-unknown -target-cpu atmega328p 
-emit-llvm %s -o - | FileCheck %s
+

asl wrote:
> This looks wrong. How you're using FileCheck? Consider dumping pre-built 
> defines and checking the output.
That's a much better idea, fixed


https://reviews.llvm.org/D28346



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[PATCH] D28346: [AVR] Allow specifying the CPU on the command line

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 87172.
dylanmckay added a comment.

Clean up the tests

- Dump all defines and search for specific ones
- Remove some unrelated tests. I will commit them separately, as they don't 
actually test any behaviour modified in this change.


https://reviews.llvm.org/D28346

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/avr/target-cpu-defines/atmega328p.c
  test/CodeGen/avr/target-cpu-defines/attiny104.c
  test/CodeGen/avr/target-cpu-defines/common.c

Index: test/CodeGen/avr/target-cpu-defines/common.c
===
--- /dev/null
+++ test/CodeGen/avr/target-cpu-defines/common.c
@@ -0,0 +1,5 @@
+// RUN: %clang_cc1 -E -dM -triple avr-unknown-unknown /dev/null | FileCheck -match-full-lines %s
+
+// CHECK: #define AVR 1
+// CHECK: #define __AVR 1
+// CHECK: #define __AVR__ 1
Index: test/CodeGen/avr/target-cpu-defines/attiny104.c
===
--- /dev/null
+++ test/CodeGen/avr/target-cpu-defines/attiny104.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -E -dM -triple avr-unknown-unknown -target-cpu attiny104 /dev/null | FileCheck -match-full-lines %s
+
+// CHECK: #define AVR 1
+// CHECK: #define __AVR 1
+// CHECK: #define __AVR_ATtiny104 1
+// CHECK: #define __AVR__ 1
Index: test/CodeGen/avr/target-cpu-defines/atmega328p.c
===
--- /dev/null
+++ test/CodeGen/avr/target-cpu-defines/atmega328p.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -E -dM -triple avr-unknown-unknown -target-cpu atmega328p /dev/null | FileCheck -match-full-lines %s
+
+// CHECK: #define AVR 1
+// CHECK: #define __AVR 1
+// CHECK: #define __AVR_ATmega328P 1
+// CHECK: #define __AVR__ 1
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -8435,6 +8435,254 @@
   }
 };
 
+/// Information about a specific microcontroller.
+struct MCUInfo {
+  const char *Name;
+  const char *DefineName;
+};
+
+// This list should be kept up-to-date with AVRDevices.td in LLVM.
+static ArrayRef AVRMcus = {
+  { "at90s1200", "__AVR_AT90S1200__" },
+  { "attiny11", "__AVR_ATtiny11" },
+  { "attiny12", "__AVR_ATtiny12" },
+  { "attiny15", "__AVR_ATtiny15" },
+  { "attiny28", "__AVR_ATtiny28" },
+  { "at90s2313", "__AVR_AT90S2313" },
+  { "at90s2323", "__AVR_AT90S2323" },
+  { "at90s2333", "__AVR_AT90S2333" },
+  { "at90s2343", "__AVR_AT90S2343" },
+  { "attiny22", "__AVR_ATtiny22" },
+  { "attiny26", "__AVR_ATtiny26" },
+  { "at86rf401", "__AVR_AT86RF401" },
+  { "at90s4414", "__AVR_AT90S4414" },
+  { "at90s4433", "__AVR_AT90S4433" },
+  { "at90s4434", "__AVR_AT90S4434" },
+  { "at90s8515", "__AVR_AT90S8515" },
+  { "at90c8534", "__AVR_AT90c8534" },
+  { "at90s8535", "__AVR_AT90S8535" },
+  { "ata5272", "__AVR_ATA5272" },
+  { "attiny13", "__AVR_ATtiny13" },
+  { "attiny13a", "__AVR_ATtiny13A" },
+  { "attiny2313", "__AVR_ATtiny2313" },
+  { "attiny2313a", "__AVR_ATtiny2313A" },
+  { "attiny24", "__AVR_ATtiny24" },
+  { "attiny24a", "__AVR_ATtiny24A" },
+  { "attiny4313", "__AVR_ATtiny4313" },
+  { "attiny44", "__AVR_ATtiny44" },
+  { "attiny44a", "__AVR_ATtiny44A" },
+  { "attiny84", "__AVR_ATtiny84" },
+  { "attiny84a", "__AVR_ATtiny84A" },
+  { "attiny25", "__AVR_ATtiny25" },
+  { "attiny45", "__AVR_ATtiny45" },
+  { "attiny85", "__AVR_ATtiny85" },
+  { "attiny261", "__AVR_ATtiny261" },
+  { "attiny261a", "__AVR_ATtiny261A" },
+  { "attiny461", "__AVR_ATtiny461" },
+  { "attiny461a", "__AVR_ATtiny461A" },
+  { "attiny861", "__AVR_ATtiny861" },
+  { "attiny861a", "__AVR_ATtiny861A" },
+  { "attiny87", "__AVR_ATtiny87" },
+  { "attiny43u", "__AVR_ATtiny43U" },
+  { "attiny48", "__AVR_ATtiny48" },
+  { "attiny88", "__AVR_ATtiny88" },
+  { "attiny828", "__AVR_ATtiny828" },
+  { "at43usb355", "__AVR_AT43USB355" },
+  { "at76c711", "__AVR_AT76C711" },
+  { "atmega103", "__AVR_ATmega103" },
+  { "at43usb320", "__AVR_AT43USB320" },
+  { "attiny167", "__AVR_ATtiny167" },
+  { "at90usb82", "__AVR_AT90USB82" },
+  { "at90usb162", "__AVR_AT90USB162" },
+  { "ata5505", "__AVR_ATA5505" },
+  { "atmega8u2", "__AVR_ATmega8U2" },
+  { "atmega16u2", "__AVR_ATmega16U2" },
+  { "atmega32u2", "__AVR_ATmega32U2" },
+  { "attiny1634", "__AVR_ATtiny1634" },
+  { "atmega8", "__AVR_ATmega8" },
+  { "ata6289", "__AVR_ATA6289" },
+  { "atmega8a", "__AVR_ATmega8A" },
+  { "ata6285", "__AVR_ATA6285" },
+  { "ata6286", "__AVR_ATA6286" },
+  { "atmega48", "__AVR_ATmega48" },
+  { "atmega48a", "__AVR_ATmega48A" },
+  { "atmega48pa", "__AVR_ATmega48PA" },
+  { "atmega48p", "__AVR_ATmega48P" },
+  { "atmega88", "__AVR_ATmega88" },
+  { "atmega88a", "__AVR_ATmega88A" },
+  { "atmega88p", "__AVR_ATmega88P" },
+  { "atmega88pa", "__AVR_ATmega88PA" },
+  { "atmega8515", "__AVR_ATmega8515" },
+  { "atmega8535", "__AVR_ATmega8535" },
+  { "atmega8hva", "__AVR_ATmega8HVA" },
+  { "at90pwm1", "__AVR_AT90PWM1" },
+  { "at90pw

[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 87174.
dylanmckay marked 2 inline comments as done.
dylanmckay added a comment.

Code review

- Remove support for ObjC methods. We shouldn't do this as it doesn't really 
make sense
- Move some tests to `Sema`
- Don't attach invalid attributes when it isn't invalid


https://reviews.llvm.org/D28451

Files:
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGen/avr/attributes/interrupt.c
  test/CodeGen/avr/attributes/signal.c
  test/Sema/avr-interrupt-attr.c
  test/Sema/avr-signal-attr.c

Index: test/Sema/avr-signal-attr.c
===
--- /dev/null
+++ test/Sema/avr-signal-attr.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((signal)); // expected-warning {{'signal' attribute only applies to functions}}
+
+__attribute__((signal(12))) void foo(void) { } // expected-error {{'signal' attribute takes no arguments}}
+
+__attribute__((signal)) void food() {}
Index: test/Sema/avr-interrupt-attr.c
===
--- /dev/null
+++ test/Sema/avr-interrupt-attr.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((interrupt)); // expected-warning {{'interrupt' attribute only applies to functions}}
+
+__attribute__((interrupt(12))) void foo(void) { } // expected-error {{'interrupt' attribute takes no arguments}}
+
+__attribute__((interrupt)) void food() {}
Index: test/CodeGen/avr/attributes/signal.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/signal.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((signal)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*signal.*}}}
Index: test/CodeGen/avr/attributes/interrupt.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/interrupt.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((interrupt)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*interrupt.*}}}
Index: lib/Sema/SemaDeclAttr.cpp
===
--- lib/Sema/SemaDeclAttr.cpp
+++ lib/Sema/SemaDeclAttr.cpp
@@ -5126,6 +5126,36 @@
   D->addAttr(UsedAttr::CreateImplicit(S.Context));
 }
 
+static void handleAVRInterruptAttr(Sema &S, Decl *D, const AttributeList &Attr) {
+  if (!isFunctionOrMethod(D)) {
+S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+<< "'interrupt'" << ExpectedFunction;
+return;
+  }
+
+  if (!checkAttributeNumArgs(S, Attr, 0)) {
+Attr.setInvalid();
+return;
+  }
+
+  handleSimpleAttribute(S, D, Attr);
+}
+
+static void handleAVRSignalAttr(Sema &S, Decl *D, const AttributeList &Attr) {
+  if (!isFunctionOrMethod(D)) {
+S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+<< "'signal'" << ExpectedFunction;
+return;
+  }
+
+  if (!checkAttributeNumArgs(S, Attr, 0)) {
+Attr.setInvalid();
+return;
+  }
+
+  handleSimpleAttribute(S, D, Attr);
+}
+
 static void handleInterruptAttr(Sema &S, Decl *D, const AttributeList &Attr) {
   // Dispatch the interrupt attribute based on the current target.
   switch (S.Context.getTargetInfo().getTriple().getArch()) {
@@ -5140,6 +5170,9 @@
   case llvm::Triple::x86_64:
 handleAnyX86InterruptAttr(S, D, Attr);
 break;
+  case llvm::Triple::avr:
+handleAVRInterruptAttr(S, D, Attr);
+break;
   default:
 handleARMInterruptAttr(S, D, Attr);
 break;
@@ -5700,6 +5733,9 @@
   case AttributeList::AT_AMDGPUNumVGPR:
 handleAMDGPUNumVGPRAttr(S, D, Attr);
 break;
+  case AttributeList::AT_AVRSignal:
+handleAVRSignalAttr(S, D, Attr);
+break;
   case AttributeList::AT_IBAction:
 handleSimpleAttribute(S, D, Attr);
 break;
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6900,6 +6900,31 @@
 }
 
 //===--===//
+// AVR ABI Implementation.
+//===--===//
+
+namespace {
+class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
+public:
+  AVRTargetCodeGenInfo(CodeGenTypes &CGT)
+: TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
+
+  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
+   CodeGen::CodeGenModule &CGM) const override {
+const auto *FD = dyn_cast_or_null(D);
+if (!FD) return;

[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added inline comments.



Comment at: lib/Sema/SemaDeclAttr.cpp:5137
+  if (!checkAttributeNumArgs(S, Attr, 0))
+Attr.setInvalid();
+

aaron.ballman wrote:
> This should simply return rather than attempt to attach an invalid attribute 
> to the declaration (same below).
Nice catch



Comment at: test/CodeGen/avr/attributes/interrupt.c:3
+
+// CHECK: define void @foo() #0
+__attribute__((interrupt)) void foo(void) { }

aaron.ballman wrote:
> As should this.
It seems like this sort of test _does_ sit in `CodeGen` - see 
`test/CodeGen/{arm-interrupt-attr.c|mips-interrupt-attr.c}`.



https://reviews.llvm.org/D28451



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[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay marked 4 inline comments as done.
dylanmckay added inline comments.



Comment at: test/CodeGen/avr/attributes/interrupt.m:4
+// CHECK: define void @_Z3foov() #0
+void foo() __attribute__((interrupt)) { }
+

aaron.ballman wrote:
> This is not an Objective-C method decl, so it doesn't really test anything 
> new. The test I was envisioning was something like:
> ```
> @interface F // There's probably an expected warning here about a missing 
> base class
> -(void) foo __attribute__((interrupt));
> @end
> 
> @implementation F
> -(void) foo __attribute__((interrupt)) {}
> @end
> ```
Removed Obj-C method support.


https://reviews.llvm.org/D28451



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[PATCH] D28344: [AVR] Add support for the full set of inline asm constraints

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 87190.
dylanmckay marked an inline comment as done.
dylanmckay added a comment.

Add tests

- Add multichar constraint tests
- Add 'unsupported constraint' tests


https://reviews.llvm.org/D28344

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/avr-inline-asm-constraints.c
  test/CodeGen/avr-unsupported-inline-asm-constraints.c

Index: test/CodeGen/avr-unsupported-inline-asm-constraints.c
===
--- /dev/null
+++ test/CodeGen/avr-unsupported-inline-asm-constraints.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -verify %s
+
+const unsigned char val = 0;
+
+int foo() {
+  __asm__ volatile("foo %0, 1" : : "fo" (val)); // expected-error {{invalid input constraint 'fo' in asm}}
+  __asm__ volatile("foo %0, 1" : : "Nd" (val)); // expected-error {{invalid input constraint 'Nd' in asm}}
+}
Index: test/CodeGen/avr-inline-asm-constraints.c
===
--- /dev/null
+++ test/CodeGen/avr-inline-asm-constraints.c
@@ -0,0 +1,124 @@
+// REQUIRES: avr-registered-target
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm -o - %s | FileCheck %s
+
+int data;
+
+void a() {
+  // CHECK: call void asm sideeffect "add r5, $0", "a"(i16 %0)
+  asm("add r5, %0" :: "a"(data));
+}
+
+void b() {
+  // CHECK: call void asm sideeffect "add r5, $0", "b"(i16 %0)
+  asm("add r5, %0" :: "b"(data));
+}
+
+void d() {
+  // CHECK: call void asm sideeffect "add r5, $0", "d"(i16 %0)
+  asm("add r5, %0" :: "d"(data));
+}
+
+void l() {
+  // CHECK: call void asm sideeffect "add r5, $0", "l"(i16 %0)
+  asm("add r5, %0" :: "l"(data));
+}
+
+void e() {
+  // CHECK: call void asm sideeffect "add r5, $0", "e"(i16 %0)
+  asm("add r5, %0" :: "e"(data));
+}
+
+void q() {
+  // CHECK: call void asm sideeffect "add r5, $0", "q"(i16 %0)
+  asm("add r5, %0" :: "q"(data));
+}
+
+void r() {
+  // CHECK: call void asm sideeffect "add r5, $0", "r"(i16 %0)
+  asm("add r5, %0" :: "r"(data));
+}
+
+void w() {
+  // CHECK: call void asm sideeffect "add r5, $0", "w"(i16 %0)
+  asm("add r5, %0" :: "w"(data));
+}
+
+void t() {
+  // CHECK: call void asm sideeffect "add r5, $0", "t"(i16 %0)
+  asm("add r5, %0" :: "t"(data));
+}
+
+void x() {
+  // CHECK: call void asm sideeffect "add r5, $0", "x"(i16 %0)
+  asm("add r5, %0" :: "x"(data));
+}
+
+void y() {
+  // CHECK: call void asm sideeffect "add r5, $0", "y"(i16 %0)
+  asm("add r5, %0" :: "y"(data));
+}
+
+void z() {
+  // CHECK: call void asm sideeffect "add r5, $0", "z"(i16 %0)
+  asm("add r5, %0" :: "z"(data));
+}
+
+void I() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "I"(i16 50)
+  asm("subi r30, %0" :: "I"(50));
+}
+
+void J() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "J"(i16 -50)
+  asm("subi r30, %0" :: "J"(-50));
+}
+
+void K() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "K"(i16 2)
+  asm("subi r30, %0" :: "K"(2));
+}
+
+void L() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "L"(i16 0)
+  asm("subi r30, %0" :: "L"(0));
+}
+
+void M() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "M"(i16 255)
+  asm("subi r30, %0" :: "M"(255));
+}
+
+void O() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "O"(i16 16)
+  asm("subi r30, %0" :: "O"(16));
+}
+
+void P() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "P"(i16 1)
+  asm("subi r30, %0" :: "P"(1));
+}
+
+void R() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "R"(i16 -3)
+  asm("subi r30, %0" :: "R"(-3));
+}
+
+void G() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "G"(i16 50)
+  asm("subi r30, %0" :: "G"(50));
+}
+
+void Q() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "Q"(i16 50)
+  asm("subi r30, %0" :: "Q"(50));
+}
+
+void ra() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "ra"(i16 50)
+  asm("subi r30, %0" :: "ra"(50));
+}
+
+void ora() {
+  // CHECK: call i16 asm "subi r30, $0", "=ra"()
+  asm("subi r30, %0" : "=ra"(data));
+}
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -8517,7 +8517,56 @@
 
   bool validateAsmConstraint(const char *&Name,
  TargetInfo::ConstraintInfo &Info) const override {
-return false;
+// There aren't any multi-character AVR specific constraints.
+if (StringRef(Name).size() > 1) return false;
+
+switch (*Name) {
+  default: return false;
+  case 'a': // Simple upper registers
+  case 'b': // Base pointer registers pairs
+  case 'd': // Upper register
+  case 'l': // Lower registers
+  case 'e': // Pointer register pairs
+  case 'q': // Stack pointer register
+  case 'r': // Any register
+  case 'w': // Special upper register pairs
+  case 't': // Temporary register
+  case 'x': case 'X': // Pointer register pair X
+  case 'y': case 'Y': // Pointer regist

[PATCH] D28344: [AVR] Add support for the full set of inline asm constraints

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 87191.
dylanmckay removed a reviewer: asl.
dylanmckay added a comment.

Add tests

- Add multichar constraint tests
- Add 'unsupported constraint' tests


https://reviews.llvm.org/D28344

Files:
  lib/Basic/Targets.cpp
  test/CodeGen/avr-inline-asm-constraints.c
  test/CodeGen/avr-unsupported-inline-asm-constraints.c

Index: test/CodeGen/avr-unsupported-inline-asm-constraints.c
===
--- /dev/null
+++ test/CodeGen/avr-unsupported-inline-asm-constraints.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -verify %s
+
+const unsigned char val = 0;
+
+int foo() {
+  __asm__ volatile("foo %0, 1" : : "fo" (val)); // expected-error {{invalid input constraint 'fo' in asm}}
+  __asm__ volatile("foo %0, 1" : : "Nd" (val)); // expected-error {{invalid input constraint 'Nd' in asm}}
+}
Index: test/CodeGen/avr-inline-asm-constraints.c
===
--- /dev/null
+++ test/CodeGen/avr-inline-asm-constraints.c
@@ -0,0 +1,124 @@
+// REQUIRES: avr-registered-target
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm -o - %s | FileCheck %s
+
+int data;
+
+void a() {
+  // CHECK: call void asm sideeffect "add r5, $0", "a"(i16 %0)
+  asm("add r5, %0" :: "a"(data));
+}
+
+void b() {
+  // CHECK: call void asm sideeffect "add r5, $0", "b"(i16 %0)
+  asm("add r5, %0" :: "b"(data));
+}
+
+void d() {
+  // CHECK: call void asm sideeffect "add r5, $0", "d"(i16 %0)
+  asm("add r5, %0" :: "d"(data));
+}
+
+void l() {
+  // CHECK: call void asm sideeffect "add r5, $0", "l"(i16 %0)
+  asm("add r5, %0" :: "l"(data));
+}
+
+void e() {
+  // CHECK: call void asm sideeffect "add r5, $0", "e"(i16 %0)
+  asm("add r5, %0" :: "e"(data));
+}
+
+void q() {
+  // CHECK: call void asm sideeffect "add r5, $0", "q"(i16 %0)
+  asm("add r5, %0" :: "q"(data));
+}
+
+void r() {
+  // CHECK: call void asm sideeffect "add r5, $0", "r"(i16 %0)
+  asm("add r5, %0" :: "r"(data));
+}
+
+void w() {
+  // CHECK: call void asm sideeffect "add r5, $0", "w"(i16 %0)
+  asm("add r5, %0" :: "w"(data));
+}
+
+void t() {
+  // CHECK: call void asm sideeffect "add r5, $0", "t"(i16 %0)
+  asm("add r5, %0" :: "t"(data));
+}
+
+void x() {
+  // CHECK: call void asm sideeffect "add r5, $0", "x"(i16 %0)
+  asm("add r5, %0" :: "x"(data));
+}
+
+void y() {
+  // CHECK: call void asm sideeffect "add r5, $0", "y"(i16 %0)
+  asm("add r5, %0" :: "y"(data));
+}
+
+void z() {
+  // CHECK: call void asm sideeffect "add r5, $0", "z"(i16 %0)
+  asm("add r5, %0" :: "z"(data));
+}
+
+void I() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "I"(i16 50)
+  asm("subi r30, %0" :: "I"(50));
+}
+
+void J() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "J"(i16 -50)
+  asm("subi r30, %0" :: "J"(-50));
+}
+
+void K() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "K"(i16 2)
+  asm("subi r30, %0" :: "K"(2));
+}
+
+void L() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "L"(i16 0)
+  asm("subi r30, %0" :: "L"(0));
+}
+
+void M() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "M"(i16 255)
+  asm("subi r30, %0" :: "M"(255));
+}
+
+void O() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "O"(i16 16)
+  asm("subi r30, %0" :: "O"(16));
+}
+
+void P() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "P"(i16 1)
+  asm("subi r30, %0" :: "P"(1));
+}
+
+void R() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "R"(i16 -3)
+  asm("subi r30, %0" :: "R"(-3));
+}
+
+void G() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "G"(i16 50)
+  asm("subi r30, %0" :: "G"(50));
+}
+
+void Q() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "Q"(i16 50)
+  asm("subi r30, %0" :: "Q"(50));
+}
+
+void ra() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "ra"(i16 50)
+  asm("subi r30, %0" :: "ra"(50));
+}
+
+void ora() {
+  // CHECK: call i16 asm "subi r30, $0", "=ra"()
+  asm("subi r30, %0" : "=ra"(data));
+}
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -8517,7 +8517,56 @@
 
   bool validateAsmConstraint(const char *&Name,
  TargetInfo::ConstraintInfo &Info) const override {
-return false;
+// There aren't any multi-character AVR specific constraints.
+if (StringRef(Name).size() > 1) return false;
+
+switch (*Name) {
+  default: return false;
+  case 'a': // Simple upper registers
+  case 'b': // Base pointer registers pairs
+  case 'd': // Upper register
+  case 'l': // Lower registers
+  case 'e': // Pointer register pairs
+  case 'q': // Stack pointer register
+  case 'r': // Any register
+  case 'w': // Special upper register pairs
+  case 't': // Temporary register
+  case 'x': case 'X': // Pointer register pair X
+  case 'y': case 'Y': // Pointer register pair Y

[PATCH] D28344: [AVR] Add support for the full set of inline asm constraints

[Dylan McKay via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL294176: [AVR] Add support for the full set of inline asm 
constraints (authored by dylanmckay).

Changed prior to commit:
  https://reviews.llvm.org/D28344?vs=87191&id=87194#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D28344

Files:
  cfe/trunk/lib/Basic/Targets.cpp
  cfe/trunk/test/CodeGen/avr-inline-asm-constraints.c
  cfe/trunk/test/CodeGen/avr-unsupported-inline-asm-constraints.c

Index: cfe/trunk/lib/Basic/Targets.cpp
===
--- cfe/trunk/lib/Basic/Targets.cpp
+++ cfe/trunk/lib/Basic/Targets.cpp
@@ -8517,6 +8517,57 @@
 
   bool validateAsmConstraint(const char *&Name,
  TargetInfo::ConstraintInfo &Info) const override {
+// There aren't any multi-character AVR specific constraints.
+if (StringRef(Name).size() > 1) return false;
+
+switch (*Name) {
+  default: return false;
+  case 'a': // Simple upper registers
+  case 'b': // Base pointer registers pairs
+  case 'd': // Upper register
+  case 'l': // Lower registers
+  case 'e': // Pointer register pairs
+  case 'q': // Stack pointer register
+  case 'r': // Any register
+  case 'w': // Special upper register pairs
+  case 't': // Temporary register
+  case 'x': case 'X': // Pointer register pair X
+  case 'y': case 'Y': // Pointer register pair Y
+  case 'z': case 'Z': // Pointer register pair Z
+Info.setAllowsRegister();
+return true;
+  case 'I': // 6-bit positive integer constant
+Info.setRequiresImmediate(0, 63);
+return true;
+  case 'J': // 6-bit negative integer constant
+Info.setRequiresImmediate(-63, 0);
+return true;
+  case 'K': // Integer constant (Range: 2)
+Info.setRequiresImmediate(2);
+return true;
+  case 'L': // Integer constant (Range: 0)
+Info.setRequiresImmediate(0);
+return true;
+  case 'M': // 8-bit integer constant
+Info.setRequiresImmediate(0, 0xff);
+return true;
+  case 'N': // Integer constant (Range: -1)
+Info.setRequiresImmediate(-1);
+return true;
+  case 'O': // Integer constant (Range: 8, 16, 24)
+Info.setRequiresImmediate({8, 16, 24});
+return true;
+  case 'P': // Integer constant (Range: 1)
+Info.setRequiresImmediate(1);
+return true;
+  case 'R': // Integer constant (Range: -6 to 5)
+Info.setRequiresImmediate(-6, 5);
+return true;
+  case 'G': // Floating point constant
+  case 'Q': // A memory address based on Y or Z pointer with displacement.
+return true;
+}
+
 return false;
   }
 
Index: cfe/trunk/test/CodeGen/avr-inline-asm-constraints.c
===
--- cfe/trunk/test/CodeGen/avr-inline-asm-constraints.c
+++ cfe/trunk/test/CodeGen/avr-inline-asm-constraints.c
@@ -0,0 +1,124 @@
+// REQUIRES: avr-registered-target
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm -o - %s | FileCheck %s
+
+int data;
+
+void a() {
+  // CHECK: call void asm sideeffect "add r5, $0", "a"(i16 %0)
+  asm("add r5, %0" :: "a"(data));
+}
+
+void b() {
+  // CHECK: call void asm sideeffect "add r5, $0", "b"(i16 %0)
+  asm("add r5, %0" :: "b"(data));
+}
+
+void d() {
+  // CHECK: call void asm sideeffect "add r5, $0", "d"(i16 %0)
+  asm("add r5, %0" :: "d"(data));
+}
+
+void l() {
+  // CHECK: call void asm sideeffect "add r5, $0", "l"(i16 %0)
+  asm("add r5, %0" :: "l"(data));
+}
+
+void e() {
+  // CHECK: call void asm sideeffect "add r5, $0", "e"(i16 %0)
+  asm("add r5, %0" :: "e"(data));
+}
+
+void q() {
+  // CHECK: call void asm sideeffect "add r5, $0", "q"(i16 %0)
+  asm("add r5, %0" :: "q"(data));
+}
+
+void r() {
+  // CHECK: call void asm sideeffect "add r5, $0", "r"(i16 %0)
+  asm("add r5, %0" :: "r"(data));
+}
+
+void w() {
+  // CHECK: call void asm sideeffect "add r5, $0", "w"(i16 %0)
+  asm("add r5, %0" :: "w"(data));
+}
+
+void t() {
+  // CHECK: call void asm sideeffect "add r5, $0", "t"(i16 %0)
+  asm("add r5, %0" :: "t"(data));
+}
+
+void x() {
+  // CHECK: call void asm sideeffect "add r5, $0", "x"(i16 %0)
+  asm("add r5, %0" :: "x"(data));
+}
+
+void y() {
+  // CHECK: call void asm sideeffect "add r5, $0", "y"(i16 %0)
+  asm("add r5, %0" :: "y"(data));
+}
+
+void z() {
+  // CHECK: call void asm sideeffect "add r5, $0", "z"(i16 %0)
+  asm("add r5, %0" :: "z"(data));
+}
+
+void I() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "I"(i16 50)
+  asm("subi r30, %0" :: "I"(50));
+}
+
+void J() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "J"(i16 -50)
+  asm("subi r30, %0" :: "J"(-50));
+}
+
+void K() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "K"(i16 2)
+  asm("subi r30, %0" :: "K"(2));
+}
+
+void L() {
+  // CHECK: call void asm sideeffect "subi r30, $0", "L

[PATCH] D28346: [AVR] Allow specifying the CPU on the command line

[Dylan McKay via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
dylanmckay marked an inline comment as done.
Closed by commit rL294177: [AVR] Allow specifying the CPU on the command line 
(authored by dylanmckay).

Changed prior to commit:
  https://reviews.llvm.org/D28346?vs=87172&id=87195#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D28346

Files:
  cfe/trunk/lib/Basic/Targets.cpp
  cfe/trunk/test/CodeGen/avr/target-cpu-defines/atmega328p.c
  cfe/trunk/test/CodeGen/avr/target-cpu-defines/attiny104.c
  cfe/trunk/test/CodeGen/avr/target-cpu-defines/common.c

Index: cfe/trunk/test/CodeGen/avr/target-cpu-defines/attiny104.c
===
--- cfe/trunk/test/CodeGen/avr/target-cpu-defines/attiny104.c
+++ cfe/trunk/test/CodeGen/avr/target-cpu-defines/attiny104.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -E -dM -triple avr-unknown-unknown -target-cpu attiny104 /dev/null | FileCheck -match-full-lines %s
+
+// CHECK: #define AVR 1
+// CHECK: #define __AVR 1
+// CHECK: #define __AVR_ATtiny104 1
+// CHECK: #define __AVR__ 1
Index: cfe/trunk/test/CodeGen/avr/target-cpu-defines/atmega328p.c
===
--- cfe/trunk/test/CodeGen/avr/target-cpu-defines/atmega328p.c
+++ cfe/trunk/test/CodeGen/avr/target-cpu-defines/atmega328p.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -E -dM -triple avr-unknown-unknown -target-cpu atmega328p /dev/null | FileCheck -match-full-lines %s
+
+// CHECK: #define AVR 1
+// CHECK: #define __AVR 1
+// CHECK: #define __AVR_ATmega328P 1
+// CHECK: #define __AVR__ 1
Index: cfe/trunk/test/CodeGen/avr/target-cpu-defines/common.c
===
--- cfe/trunk/test/CodeGen/avr/target-cpu-defines/common.c
+++ cfe/trunk/test/CodeGen/avr/target-cpu-defines/common.c
@@ -0,0 +1,5 @@
+// RUN: %clang_cc1 -E -dM -triple avr-unknown-unknown /dev/null | FileCheck -match-full-lines %s
+
+// CHECK: #define AVR 1
+// CHECK: #define __AVR 1
+// CHECK: #define __AVR__ 1
Index: cfe/trunk/lib/Basic/Targets.cpp
===
--- cfe/trunk/lib/Basic/Targets.cpp
+++ cfe/trunk/lib/Basic/Targets.cpp
@@ -8435,6 +8435,254 @@
   }
 };
 
+/// Information about a specific microcontroller.
+struct MCUInfo {
+  const char *Name;
+  const char *DefineName;
+};
+
+// This list should be kept up-to-date with AVRDevices.td in LLVM.
+static ArrayRef AVRMcus = {
+  { "at90s1200", "__AVR_AT90S1200__" },
+  { "attiny11", "__AVR_ATtiny11" },
+  { "attiny12", "__AVR_ATtiny12" },
+  { "attiny15", "__AVR_ATtiny15" },
+  { "attiny28", "__AVR_ATtiny28" },
+  { "at90s2313", "__AVR_AT90S2313" },
+  { "at90s2323", "__AVR_AT90S2323" },
+  { "at90s2333", "__AVR_AT90S2333" },
+  { "at90s2343", "__AVR_AT90S2343" },
+  { "attiny22", "__AVR_ATtiny22" },
+  { "attiny26", "__AVR_ATtiny26" },
+  { "at86rf401", "__AVR_AT86RF401" },
+  { "at90s4414", "__AVR_AT90S4414" },
+  { "at90s4433", "__AVR_AT90S4433" },
+  { "at90s4434", "__AVR_AT90S4434" },
+  { "at90s8515", "__AVR_AT90S8515" },
+  { "at90c8534", "__AVR_AT90c8534" },
+  { "at90s8535", "__AVR_AT90S8535" },
+  { "ata5272", "__AVR_ATA5272" },
+  { "attiny13", "__AVR_ATtiny13" },
+  { "attiny13a", "__AVR_ATtiny13A" },
+  { "attiny2313", "__AVR_ATtiny2313" },
+  { "attiny2313a", "__AVR_ATtiny2313A" },
+  { "attiny24", "__AVR_ATtiny24" },
+  { "attiny24a", "__AVR_ATtiny24A" },
+  { "attiny4313", "__AVR_ATtiny4313" },
+  { "attiny44", "__AVR_ATtiny44" },
+  { "attiny44a", "__AVR_ATtiny44A" },
+  { "attiny84", "__AVR_ATtiny84" },
+  { "attiny84a", "__AVR_ATtiny84A" },
+  { "attiny25", "__AVR_ATtiny25" },
+  { "attiny45", "__AVR_ATtiny45" },
+  { "attiny85", "__AVR_ATtiny85" },
+  { "attiny261", "__AVR_ATtiny261" },
+  { "attiny261a", "__AVR_ATtiny261A" },
+  { "attiny461", "__AVR_ATtiny461" },
+  { "attiny461a", "__AVR_ATtiny461A" },
+  { "attiny861", "__AVR_ATtiny861" },
+  { "attiny861a", "__AVR_ATtiny861A" },
+  { "attiny87", "__AVR_ATtiny87" },
+  { "attiny43u", "__AVR_ATtiny43U" },
+  { "attiny48", "__AVR_ATtiny48" },
+  { "attiny88", "__AVR_ATtiny88" },
+  { "attiny828", "__AVR_ATtiny828" },
+  { "at43usb355", "__AVR_AT43USB355" },
+  { "at76c711", "__AVR_AT76C711" },
+  { "atmega103", "__AVR_ATmega103" },
+  { "at43usb320", "__AVR_AT43USB320" },
+  { "attiny167", "__AVR_ATtiny167" },
+  { "at90usb82", "__AVR_AT90USB82" },
+  { "at90usb162", "__AVR_AT90USB162" },
+  { "ata5505", "__AVR_ATA5505" },
+  { "atmega8u2", "__AVR_ATmega8U2" },
+  { "atmega16u2", "__AVR_ATmega16U2" },
+  { "atmega32u2", "__AVR_ATmega32U2" },
+  { "attiny1634", "__AVR_ATtiny1634" },
+  { "atmega8", "__AVR_ATmega8" },
+  { "ata6289", "__AVR_ATA6289" },
+  { "atmega8a", "__AVR_ATmega8A" },
+  { "ata6285", "__AVR_ATA6285" },
+  { "ata6286", "__AVR_ATA6286" },
+  { "atmega48", "__AVR_ATmega48" },
+  { "atmega48a", "__AVR_ATmega48A" },
+  { "atmega48pa", "__AVR_ATmega48PA" },
+  { "atmega48p", "__AVR_ATmega48P" },
+  

[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added inline comments.



Comment at: test/CodeGen/avr/attributes/interrupt.c:3
+
+// CHECK: define void @foo() #0
+__attribute__((interrupt)) void foo(void) { }

aaron.ballman wrote:
> dylanmckay wrote:
> > aaron.ballman wrote:
> > > As should this.
> > It seems like this sort of test _does_ sit in `CodeGen` - see 
> > `test/CodeGen/{arm-interrupt-attr.c|mips-interrupt-attr.c}`.
> > 
> You're correct, this test does belong here. I think I attached my comment to 
> the wrong thing (sorry about that).
No problems, thanks for the review!


https://reviews.llvm.org/D28451



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[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay updated this revision to Diff 87365.
dylanmckay marked 4 inline comments as done.
dylanmckay added a comment.

Remove 'Attr.setInvalid()'


https://reviews.llvm.org/D28451

Files:
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGen/avr/attributes/interrupt.c
  test/CodeGen/avr/attributes/signal.c
  test/Sema/avr-interrupt-attr.c
  test/Sema/avr-signal-attr.c

Index: test/Sema/avr-signal-attr.c
===
--- /dev/null
+++ test/Sema/avr-signal-attr.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((signal)); // expected-warning {{'signal' attribute only applies to functions}}
+
+__attribute__((signal(12))) void foo(void) { } // expected-error {{'signal' attribute takes no arguments}}
+
+__attribute__((signal)) void food() {}
Index: test/Sema/avr-interrupt-attr.c
===
--- /dev/null
+++ test/Sema/avr-interrupt-attr.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((interrupt)); // expected-warning {{'interrupt' attribute only applies to functions}}
+
+__attribute__((interrupt(12))) void foo(void) { } // expected-error {{'interrupt' attribute takes no arguments}}
+
+__attribute__((interrupt)) void food() {}
Index: test/CodeGen/avr/attributes/signal.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/signal.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((signal)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*signal.*}}}
Index: test/CodeGen/avr/attributes/interrupt.c
===
--- /dev/null
+++ test/CodeGen/avr/attributes/interrupt.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((interrupt)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*interrupt.*}}}
Index: lib/Sema/SemaDeclAttr.cpp
===
--- lib/Sema/SemaDeclAttr.cpp
+++ lib/Sema/SemaDeclAttr.cpp
@@ -5126,6 +5126,32 @@
   D->addAttr(UsedAttr::CreateImplicit(S.Context));
 }
 
+static void handleAVRInterruptAttr(Sema &S, Decl *D, const AttributeList &Attr) {
+  if (!isFunctionOrMethod(D)) {
+S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+<< "'interrupt'" << ExpectedFunction;
+return;
+  }
+
+  if (!checkAttributeNumArgs(S, Attr, 0))
+return;
+
+  handleSimpleAttribute(S, D, Attr);
+}
+
+static void handleAVRSignalAttr(Sema &S, Decl *D, const AttributeList &Attr) {
+  if (!isFunctionOrMethod(D)) {
+S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type)
+<< "'signal'" << ExpectedFunction;
+return;
+  }
+
+  if (!checkAttributeNumArgs(S, Attr, 0))
+return;
+
+  handleSimpleAttribute(S, D, Attr);
+}
+
 static void handleInterruptAttr(Sema &S, Decl *D, const AttributeList &Attr) {
   // Dispatch the interrupt attribute based on the current target.
   switch (S.Context.getTargetInfo().getTriple().getArch()) {
@@ -5140,6 +5166,9 @@
   case llvm::Triple::x86_64:
 handleAnyX86InterruptAttr(S, D, Attr);
 break;
+  case llvm::Triple::avr:
+handleAVRInterruptAttr(S, D, Attr);
+break;
   default:
 handleARMInterruptAttr(S, D, Attr);
 break;
@@ -5700,6 +5729,9 @@
   case AttributeList::AT_AMDGPUNumVGPR:
 handleAMDGPUNumVGPRAttr(S, D, Attr);
 break;
+  case AttributeList::AT_AVRSignal:
+handleAVRSignalAttr(S, D, Attr);
+break;
   case AttributeList::AT_IBAction:
 handleSimpleAttribute(S, D, Attr);
 break;
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -6900,6 +6900,31 @@
 }
 
 //===--===//
+// AVR ABI Implementation.
+//===--===//
+
+namespace {
+class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
+public:
+  AVRTargetCodeGenInfo(CodeGenTypes &CGT)
+: TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
+
+  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
+   CodeGen::CodeGenModule &CGM) const override {
+const auto *FD = dyn_cast_or_null(D);
+if (!FD) return;
+auto *Fn = cast(GV);
+
+if (FD->getAttr())
+  Fn->addFnAttr("interrupt");
+
+if (FD->getAttr())
+  Fn->addFnAttr("signal");
+  }
+};
+}
+
+//===---

[PATCH] D28451: [AVR] Add support for the 'interrupt' and 'naked' attributes

[Dylan McKay via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL294402: [AVR] Add support for the 'interrupt' and 'naked' 
attributes (authored by dylanmckay).

Changed prior to commit:
  https://reviews.llvm.org/D28451?vs=87365&id=87588#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D28451

Files:
  cfe/trunk/include/clang/Basic/Attr.td
  cfe/trunk/include/clang/Basic/AttrDocs.td
  cfe/trunk/lib/CodeGen/TargetInfo.cpp
  cfe/trunk/lib/Sema/SemaDeclAttr.cpp
  cfe/trunk/test/CodeGen/avr/attributes/interrupt.c
  cfe/trunk/test/CodeGen/avr/attributes/signal.c
  cfe/trunk/test/Sema/avr-interrupt-attr.c
  cfe/trunk/test/Sema/avr-signal-attr.c

Index: cfe/trunk/include/clang/Basic/AttrDocs.td
===
--- cfe/trunk/include/clang/Basic/AttrDocs.td
+++ cfe/trunk/include/clang/Basic/AttrDocs.td
@@ -1182,6 +1182,33 @@
   }];
 }
 
+def AVRInterruptDocs : Documentation {
+  let Category = DocCatFunction;
+  let Content = [{
+Clang supports the GNU style ``__attribute__((interrupt))`` attribute on
+AVR targets. This attribute may be attached to a function definition and instructs
+the backend to generate appropriate function entry/exit code so that it can be used
+directly as an interrupt service routine.
+
+On the AVR, the hardware globally disables interrupts when an interrupt is executed.
+The first instruction of an interrupt handler declared with this attribute is a SEI
+instruction to re-enable interrupts. See also the signal attribute that
+does not insert a SEI instruction.
+  }];
+}
+
+def AVRSignalDocs : Documentation {
+  let Category = DocCatFunction;
+  let Content = [{
+Clang supports the GNU style ``__attribute__((signal))`` attribute on
+AVR targets. This attribute may be attached to a function definition and instructs
+the backend to generate appropriate function entry/exit code so that it can be used
+directly as an interrupt service routine.
+
+Interrupt handler functions defined with the signal attribute do not re-enable interrupts.
+}];
+}
+
 def TargetDocs : Documentation {
   let Category = DocCatFunction;
   let Content = [{
Index: cfe/trunk/include/clang/Basic/Attr.td
===
--- cfe/trunk/include/clang/Basic/Attr.td
+++ cfe/trunk/include/clang/Basic/Attr.td
@@ -258,6 +258,7 @@
   list CXXABIs;
 }
 def TargetARM : TargetArch<["arm", "thumb", "armeb", "thumbeb"]>;
+def TargetAVR : TargetArch<["avr"]>;
 def TargetMips : TargetArch<["mips", "mipsel"]>;
 def TargetMSP430 : TargetArch<["msp430"]>;
 def TargetX86 : TargetArch<["x86"]>;
@@ -480,6 +481,19 @@
   let Documentation = [ARMInterruptDocs];
 }
 
+def AVRInterrupt : InheritableAttr, TargetSpecificAttr {
+  let Spellings = [GNU<"interrupt">];
+  let Subjects = SubjectList<[Function]>;
+  let ParseKind = "Interrupt";
+  let Documentation = [AVRInterruptDocs];
+}
+
+def AVRSignal : InheritableAttr, TargetSpecificAttr {
+  let Spellings = [GNU<"signal">];
+  let Subjects = SubjectList<[Function]>;
+  let Documentation = [AVRSignalDocs];
+}
+
 def AsmLabel : InheritableAttr {
   let Spellings = [Keyword<"asm">, Keyword<"__asm__">];
   let Args = [StringArgument<"Label">];
Index: cfe/trunk/test/CodeGen/avr/attributes/signal.c
===
--- cfe/trunk/test/CodeGen/avr/attributes/signal.c
+++ cfe/trunk/test/CodeGen/avr/attributes/signal.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((signal)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*signal.*}}}
Index: cfe/trunk/test/CodeGen/avr/attributes/interrupt.c
===
--- cfe/trunk/test/CodeGen/avr/attributes/interrupt.c
+++ cfe/trunk/test/CodeGen/avr/attributes/interrupt.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple avr-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define void @foo() #0
+__attribute__((interrupt)) void foo(void) { }
+
+// CHECK: attributes #0 = {{{.*interrupt.*}}}
Index: cfe/trunk/test/Sema/avr-signal-attr.c
===
--- cfe/trunk/test/Sema/avr-signal-attr.c
+++ cfe/trunk/test/Sema/avr-signal-attr.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify -fsyntax-only
+struct a { int b; };
+
+struct a test __attribute__((signal)); // expected-warning {{'signal' attribute only applies to functions}}
+
+__attribute__((signal(12))) void foo(void) { } // expected-error {{'signal' attribute takes no arguments}}
+
+__attribute__((signal)) void food() {}
Index: cfe/trunk/test/Sema/avr-interrupt-attr.c
===
--- cfe/trunk/test/Sema/avr-interrupt-attr.c
+++ cfe/trunk/test/Sema/avr-interrupt-attr.c
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 %s -triple avr-unknown-unknown -verify

[PATCH] D29817: [AVR] Fix __AVR_xxx macro definitions

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

Nice catch, unsure why I didn't catch this earlier.

Do we also need to modify the other tests inside `target-cpu-defines`?


https://reviews.llvm.org/D29817



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[PATCH] D29827: [AVR] Add -mmcu option to the driver

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added inline comments.



Comment at: include/clang/Driver/Options.td:1613
 def mcpu_EQ : Joined<["-"], "mcpu=">, Group;
+def mmcu_EQ : Joined<["-"], "mmcu=">, Group;
 def mdynamic_no_pic : Joined<["-"], "mdynamic-no-pic">, Group;

Lekensteyn wrote:
> jroelofs wrote:
> > Would it make sense to have mcu be an alias for mcpu instead?
> That would deviate from the GCC interface, so I have chosen for the current 
> situation:
> ```
> $ avr-gcc -mmcu=avr2 -o /dev/null x.c
> $ avr-gcc -mcpu=avr2 -o /dev/null x.c
> avr-gcc: error: unrecognized command line option '-mcpu=avr2'
> $ avr-gcc -march=avr2 -o /dev/null x.c
> avr-gcc: error: unrecognized command line option '-march=avr2'
> $ avr-gcc -v
> ...
> gcc version 6.3.0 (GCC)
> ```
I think @jroelofs  means that it is possible to make `mmcu` an alias of `mmcu` 
internally. This would mean we wouldn't need to add AVR-specific `getCPUName` 
handling.


https://reviews.llvm.org/D29827



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[PATCH] D29817: [AVR] Fix __AVR_xxx macro definitions

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

Do you have commit access @Lekensteyn?


https://reviews.llvm.org/D29817



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[PATCH] D29817: [AVR] Fix __AVR_xxx macro definitions

[Dylan McKay via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL294869: [AVR] Fix __AVR_xxx macro definitions; authored by 
Peter Wu (authored by dylanmckay).

Changed prior to commit:
  https://reviews.llvm.org/D29817?vs=88025&id=88104#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D29817

Files:
  cfe/trunk/lib/Basic/Targets.cpp
  cfe/trunk/test/CodeGen/avr/target-cpu-defines/atmega328p.c
  cfe/trunk/test/CodeGen/avr/target-cpu-defines/attiny104.c

Index: cfe/trunk/test/CodeGen/avr/target-cpu-defines/attiny104.c
===
--- cfe/trunk/test/CodeGen/avr/target-cpu-defines/attiny104.c
+++ cfe/trunk/test/CodeGen/avr/target-cpu-defines/attiny104.c
@@ -3,5 +3,5 @@
 
 // CHECK: #define AVR 1
 // CHECK: #define __AVR 1
-// CHECK: #define __AVR_ATtiny104 1
+// CHECK: #define __AVR_ATtiny104__ 1
 // CHECK: #define __AVR__ 1
Index: cfe/trunk/test/CodeGen/avr/target-cpu-defines/atmega328p.c
===
--- cfe/trunk/test/CodeGen/avr/target-cpu-defines/atmega328p.c
+++ cfe/trunk/test/CodeGen/avr/target-cpu-defines/atmega328p.c
@@ -3,5 +3,5 @@
 
 // CHECK: #define AVR 1
 // CHECK: #define __AVR 1
-// CHECK: #define __AVR_ATmega328P 1
+// CHECK: #define __AVR_ATmega328P__ 1
 // CHECK: #define __AVR__ 1
Index: cfe/trunk/lib/Basic/Targets.cpp
===
--- cfe/trunk/lib/Basic/Targets.cpp
+++ cfe/trunk/lib/Basic/Targets.cpp
@@ -8464,244 +8464,244 @@
 // This list should be kept up-to-date with AVRDevices.td in LLVM.
 static ArrayRef AVRMcus = {
   { "at90s1200", "__AVR_AT90S1200__" },
-  { "attiny11", "__AVR_ATtiny11" },
-  { "attiny12", "__AVR_ATtiny12" },
-  { "attiny15", "__AVR_ATtiny15" },
-  { "attiny28", "__AVR_ATtiny28" },
-  { "at90s2313", "__AVR_AT90S2313" },
-  { "at90s2323", "__AVR_AT90S2323" },
-  { "at90s2333", "__AVR_AT90S2333" },
-  { "at90s2343", "__AVR_AT90S2343" },
-  { "attiny22", "__AVR_ATtiny22" },
-  { "attiny26", "__AVR_ATtiny26" },
-  { "at86rf401", "__AVR_AT86RF401" },
-  { "at90s4414", "__AVR_AT90S4414" },
-  { "at90s4433", "__AVR_AT90S4433" },
-  { "at90s4434", "__AVR_AT90S4434" },
-  { "at90s8515", "__AVR_AT90S8515" },
-  { "at90c8534", "__AVR_AT90c8534" },
-  { "at90s8535", "__AVR_AT90S8535" },
-  { "ata5272", "__AVR_ATA5272" },
-  { "attiny13", "__AVR_ATtiny13" },
-  { "attiny13a", "__AVR_ATtiny13A" },
-  { "attiny2313", "__AVR_ATtiny2313" },
-  { "attiny2313a", "__AVR_ATtiny2313A" },
-  { "attiny24", "__AVR_ATtiny24" },
-  { "attiny24a", "__AVR_ATtiny24A" },
-  { "attiny4313", "__AVR_ATtiny4313" },
-  { "attiny44", "__AVR_ATtiny44" },
-  { "attiny44a", "__AVR_ATtiny44A" },
-  { "attiny84", "__AVR_ATtiny84" },
-  { "attiny84a", "__AVR_ATtiny84A" },
-  { "attiny25", "__AVR_ATtiny25" },
-  { "attiny45", "__AVR_ATtiny45" },
-  { "attiny85", "__AVR_ATtiny85" },
-  { "attiny261", "__AVR_ATtiny261" },
-  { "attiny261a", "__AVR_ATtiny261A" },
-  { "attiny461", "__AVR_ATtiny461" },
-  { "attiny461a", "__AVR_ATtiny461A" },
-  { "attiny861", "__AVR_ATtiny861" },
-  { "attiny861a", "__AVR_ATtiny861A" },
-  { "attiny87", "__AVR_ATtiny87" },
-  { "attiny43u", "__AVR_ATtiny43U" },
-  { "attiny48", "__AVR_ATtiny48" },
-  { "attiny88", "__AVR_ATtiny88" },
-  { "attiny828", "__AVR_ATtiny828" },
-  { "at43usb355", "__AVR_AT43USB355" },
-  { "at76c711", "__AVR_AT76C711" },
-  { "atmega103", "__AVR_ATmega103" },
-  { "at43usb320", "__AVR_AT43USB320" },
-  { "attiny167", "__AVR_ATtiny167" },
-  { "at90usb82", "__AVR_AT90USB82" },
-  { "at90usb162", "__AVR_AT90USB162" },
-  { "ata5505", "__AVR_ATA5505" },
-  { "atmega8u2", "__AVR_ATmega8U2" },
-  { "atmega16u2", "__AVR_ATmega16U2" },
-  { "atmega32u2", "__AVR_ATmega32U2" },
-  { "attiny1634", "__AVR_ATtiny1634" },
-  { "atmega8", "__AVR_ATmega8" },
-  { "ata6289", "__AVR_ATA6289" },
-  { "atmega8a", "__AVR_ATmega8A" },
-  { "ata6285", "__AVR_ATA6285" },
-  { "ata6286", "__AVR_ATA6286" },
-  { "atmega48", "__AVR_ATmega48" },
-  { "atmega48a", "__AVR_ATmega48A" },
-  { "atmega48pa", "__AVR_ATmega48PA" },
-  { "atmega48p", "__AVR_ATmega48P" },
-  { "atmega88", "__AVR_ATmega88" },
-  { "atmega88a", "__AVR_ATmega88A" },
-  { "atmega88p", "__AVR_ATmega88P" },
-  { "atmega88pa", "__AVR_ATmega88PA" },
-  { "atmega8515", "__AVR_ATmega8515" },
-  { "atmega8535", "__AVR_ATmega8535" },
-  { "atmega8hva", "__AVR_ATmega8HVA" },
-  { "at90pwm1", "__AVR_AT90PWM1" },
-  { "at90pwm2", "__AVR_AT90PWM2" },
-  { "at90pwm2b", "__AVR_AT90PWM2B" },
-  { "at90pwm3", "__AVR_AT90PWM3" },
-  { "at90pwm3b", "__AVR_AT90PWM3B" },
-  { "at90pwm81", "__AVR_AT90PWM81" },
-  { "ata5790", "__AVR_ATA5790" },
-  { "ata5795", "__AVR_ATA5795" },
-  { "atmega16", "__AVR_ATmega16" },
-  { "atmega16a", "__AVR_ATmega16A" },
-  { "atmega161", "__AVR_ATmega161" },
-  { "atmega162", "__AVR_ATmega162" },
-  { "atmega163", "__AVR_ATmega163" },
-  { "atmega164a", "__AVR_ATmega164A" },
-  { "atmega164p", "__AV

[PATCH] D29817: [AVR] Fix __AVR_xxx macro definitions

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added a comment.

Done, thanks for the patch @Lekensteyn!

If you plan on submitting more patches, feel free to ask for commit access 
.


Repository:
  rL LLVM

https://reviews.llvm.org/D29817



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[PATCH] D27123: Add AVR target and toolchain to Clang

[Dylan McKay via Phabricator via cfe-commits]

dylanmckay added inline comments.



Comment at: lib/Basic/Targets.cpp:8543
+  case llvm::Triple::avr:
+return new AVRTargetInfo(Triple, Opts);
   case llvm::Triple::bpfeb:

If we build clang without `LLVM_EXPERIMENTAL_TARGETS_TO_BUILD=AVR`, how will 
this work?

Will it fail compilation? Will `clang` report that AVR is supported? Will it 
crash if you try and run `clang`?


https://reviews.llvm.org/D27123



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