[PATCH] D33406: PR28129 expand vector oparation to an IR constant.

2017-05-24 Thread Dinar Temirbulatov via Phabricator via cfe-commits 
dtemirbulatov updated this revision to Diff 100089.
dtemirbulatov added a comment.

add _mm256_cmp_pd double version
add comments in lib/CodeGen/CGBuiltin.cpp
replaced 0xf to _CMP_TRUE_UQ in avx-builtins.c


https://reviews.llvm.org/D33406

Files:
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGen/avx-builtins.c


Index: test/CodeGen/avx-builtins.c
===
--- test/CodeGen/avx-builtins.c
+++ test/CodeGen/avx-builtins.c
@@ -1427,3 +1427,15 @@
  // CHECK: extractelement <8 x float> %{{.*}}, i32 0
  return _mm256_cvtss_f32(__a);
 }
+
+__m256 test_mm256_cmp_ps_true(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_ps_true
+ // CHECK: store <8 x float>  getType()->getVectorNumElements(),
+   llvm::Constant::getAllOnesValue(Builder.getInt32Ty()));
+ return Builder.CreateBitCast(Vec, Ops[0]->getType());
+  }
   ID = Intrinsic::x86_avx_cmp_ps_256;
   break;
 case X86::BI__builtin_ia32_cmppd:
   ID = Intrinsic::x86_sse2_cmp_pd;
   break;
 case X86::BI__builtin_ia32_cmppd256:
+  // _CMP_TRUE_UQ would produce -1,-1... vector on any input
+  if (CC == 0xf) {
+ Value *Vec = 
Builder.CreateVectorSplat(Ops[0]->getType()->getVectorNumElements(),
+   llvm::Constant::getAllOnesValue(Builder.getInt64Ty()));
+ return Builder.CreateBitCast(Vec, Ops[0]->getType());
+  }
   ID = Intrinsic::x86_avx_cmp_pd_256;
   break;
 }


Index: test/CodeGen/avx-builtins.c
===
--- test/CodeGen/avx-builtins.c
+++ test/CodeGen/avx-builtins.c
@@ -1427,3 +1427,15 @@
  // CHECK: extractelement <8 x float> %{{.*}}, i32 0
  return _mm256_cvtss_f32(__a);
 }
+
+__m256 test_mm256_cmp_ps_true(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_ps_true
+ // CHECK: store <8 x float>  getType()->getVectorNumElements(),
+   llvm::Constant::getAllOnesValue(Builder.getInt32Ty()));
+ return Builder.CreateBitCast(Vec, Ops[0]->getType());
+  }
   ID = Intrinsic::x86_avx_cmp_ps_256;
   break;
 case X86::BI__builtin_ia32_cmppd:
   ID = Intrinsic::x86_sse2_cmp_pd;
   break;
 case X86::BI__builtin_ia32_cmppd256:
+  // _CMP_TRUE_UQ would produce -1,-1... vector on any input
+  if (CC == 0xf) {
+ Value *Vec = Builder.CreateVectorSplat(Ops[0]->getType()->getVectorNumElements(),
+   llvm::Constant::getAllOnesValue(Builder.getInt64Ty()));
+ return Builder.CreateBitCast(Vec, Ops[0]->getType());
+  }
   ID = Intrinsic::x86_avx_cmp_pd_256;
   break;
 }
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[PATCH] D33406: PR28129 expand vector oparation to an IR constant.

2017-05-24 Thread Dinar Temirbulatov via Phabricator via cfe-commits 
dtemirbulatov added a comment.

> Should we handle the 'pd256' version the same way?
> How about the 0xb ('false') constant? It should produce a zero here?
> Can or should we deal with the signalling versions (0x1b, 0x1f) too?

hm looks like 0xb(_CMP_FALSE_OQ) is ordered, so it is not possible and 0x1b or 
0x1f might emit a signal.




Comment at: lib/CodeGen/CGBuiltin.cpp:7932
   break;
 case X86::BI__builtin_ia32_cmppd256:
   ID = Intrinsic::x86_avx_cmp_pd_256;

spatel wrote:
> 1. Should we handle the 'pd256' version the same way?
> 2. How about the 0xb ('false') constant? It should produce a zero here?
> 3. Can or should we deal with the signalling versions (0x1b, 0x1f) too?
> 
hm looks like 0xb(_CMP_FALSE_OQ) is ordered, so it is not possible and 0x1b or 
0x1f might emit a signal.


https://reviews.llvm.org/D33406



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[PATCH] D33406: PR28129 expand vector oparation to an IR constant.

2017-05-31 Thread Dinar Temirbulatov via Phabricator via cfe-commits 
dtemirbulatov added a comment.

> We should've asked this first: is that fold allowed in the default FPENV 
> state that we assume that clang is operating in?

I suppose it is FE_ALL_EXCEPT.


https://reviews.llvm.org/D33406



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[PATCH] D33406: PR28129 expand vector oparation to an IR constant.

2017-06-05 Thread Dinar Temirbulatov via Phabricator via cfe-commits 
dtemirbulatov added a comment.

Ping. [andrew.w.kaylor, scanon] Is it OK to assume that FP exceptions are off 
by default and allow such transformation to constants in the IR since we know 
that  we would have exception with "1.00  -nan" for _mm256_cmp_ps(a, b, 15)?


https://reviews.llvm.org/D33406



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[PATCH] D33406: PR28129 expand vector oparation to an IR constant.

2017-06-15 Thread Dinar Temirbulatov via Phabricator via cfe-commits 
dtemirbulatov updated this revision to Diff 102673.
dtemirbulatov added a reviewer: hfinkel.
dtemirbulatov added a comment.

Update after http://lists.llvm.org/pipermail/llvm-dev/2017-June/114120.html. 
Added 0x1b(_CMP_FALSE_OS), 0x1f(_CMP_TRUE_US) handling.


https://reviews.llvm.org/D33406

Files:
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGen/avx-builtins.c


Index: test/CodeGen/avx-builtins.c
===
--- test/CodeGen/avx-builtins.c
+++ test/CodeGen/avx-builtins.c
@@ -1427,3 +1427,51 @@
  // CHECK: extractelement <8 x float> %{{.*}}, i32 0
  return _mm256_cvtss_f32(__a);
 }
+
+__m256 test_mm256_cmp_ps_true(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_ps_true
+ // CHECK: store <8 x float>   zeroinitializer, <8 x float>* %tmp, align 32
+ return _mm256_cmp_ps(a, b, _CMP_FALSE_OQ);
+}
+
+__m256 test_mm256_cmp_pd_false(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_pd_false
+ // CHECK: store <4 x double> zeroinitializer, <4 x double>* %tmp, align 32
+  return _mm256_cmp_pd(a, b, _CMP_FALSE_OQ);
+}
+
+__m256 test_mm256_cmp_ps_strue(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_ps_strue
+ // CHECK: store <8 x float>   zeroinitializer, <8 x float>* %tmp, align 32
+ return _mm256_cmp_ps(a, b, _CMP_FALSE_OS);
+}
+
+__m256 test_mm256_cmp_pd_sfalse(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_pd_sfalse
+ // CHECK: store <4 x double> zeroinitializer, <4 x double>* %tmp, align 32
+  return _mm256_cmp_pd(a, b, _CMP_FALSE_OS);
+}
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -7930,12 +7930,32 @@
   ID = Intrinsic::x86_sse_cmp_ps;
   break;
 case X86::BI__builtin_ia32_cmpps256:
+  // _CMP_TRUE_UQ, _CMP_TRUE_US would produce -1,-1... vector
+  // on any input and _CMP_FALSE_OQ, _CMP_FALSE_OS produces 0, 0...
+  if (CC == 0xf || CC == 0xb || CC == 0x1b || CC == 0x1f) {
+ Value *Constant = (CC == 0xf || CC == 0x1f) ?
+llvm::Constant::getAllOnesValue(Builder.getInt32Ty()) :
+llvm::Constant::getNullValue(Builder.getInt32Ty());
+ Value *Vec = 
Builder.CreateVectorSplat(Ops[0]->getType()->getVectorNumElements(),
+   Constant);
+ return Builder.CreateBitCast(Vec, Ops[0]->getType());
+  }
   ID = Intrinsic::x86_avx_cmp_ps_256;
   break;
 case X86::BI__builtin_ia32_cmppd:
   ID = Intrinsic::x86_sse2_cmp_pd;
   break;
 case X86::BI__builtin_ia32_cmppd256:
+  // _CMP_TRUE_UQ, _CMP_TRUE_US would produce -1,-1... vector
+  // on any input and _CMP_FALSE_OQ, _CMP_FALSE_OS produces 0, 0...
+  if (CC == 0xf || CC == 0xb || CC == 0x1b || CC == 0x1f) {
+ Value *Constant = (CC == 0xf || CC == 0x1f) ?
+llvm::Constant::getAllOnesValue(Builder.getInt64Ty()) :
+llvm::Constant::getNullValue(Builder.getInt64Ty());
+ Value *Vec = 
Builder.CreateVectorSplat(Ops[0]->getType()->getVectorNumElements(),
+   Constant);
+ return Builder.CreateBitCast(Vec, Ops[0]->getType());
+  }
   ID = Intrinsic::x86_avx_cmp_pd_256;
   break;
 }


Index: test/CodeGen/avx-builtins.c
===
--- test/CodeGen/avx-builtins.c
+++ test/CodeGen/avx-builtins.c
@@ -1427,3 +1427,51 @@
  // CHECK: extractelement <8 x float> %{{.*}}, i32 0
  return _mm256_cvtss_f32(__a);
 }
+
+__m256 test_mm256_cmp_ps_true(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_ps_true
+ // CHECK: store <8 x float>   zeroinitializer, <8 x float>* %tmp, align 32
+ return _mm256_cmp_ps(a, b, _CMP_FALSE_OQ);
+}
+
+__m256 test_mm256_cmp_pd_false(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_pd_false
+ // CHECK: store <4 x double> zeroinitializer, <4 x double>* %tmp, align 32
+  return _mm256_cmp_pd(a, b, _CMP_FALSE_OQ);
+}
+
+__m256 test_mm256_cmp_ps_strue(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_ps_strue
+ // CHECK: store <8 x float>   zeroinitializer, <8 x float>* %tmp, align 32
+ return _mm256_cmp_ps(a, b, _CMP_FALSE_OS);
+}
+
+__m256 test_mm256_cmp_pd_sfalse(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_pd_sfalse
+ // CHECK: store <4 x double> zeroinitializer, <4 x double>* %tmp, align 32
+  return _mm256_cmp_pd(a, b, _CMP_FALSE_OS);
+}
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -7930,12 +7930,32 @@
   ID = Intrinsic::x86_sse_cmp_ps;
   break;
 case X86::BI__builtin_ia32_cmpps256:
+  // _CMP_TRUE_UQ, _CMP_TRUE_US would produce -1,-1... vector
+  // on any input and _CMP_FALSE_OQ, _CMP_FALSE_OS produces 0, 0...
+  if (CC == 0xf || CC == 0xb || CC == 0x1b || CC == 0x1f) {
+ Value *Constant = (CC == 0xf || CC == 0x1f) ?
+

[PATCH] D33406: PR28129 expand vector oparation to an IR constant.

2017-06-15 Thread Dinar Temirbulatov via Phabricator via cfe-commits 
dtemirbulatov updated this revision to Diff 102717.
dtemirbulatov added a comment.

Update formatting, comments


https://reviews.llvm.org/D33406

Files:
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGen/avx-builtins.c

Index: test/CodeGen/avx-builtins.c
===
--- test/CodeGen/avx-builtins.c
+++ test/CodeGen/avx-builtins.c
@@ -1427,3 +1427,51 @@
  // CHECK: extractelement <8 x float> %{{.*}}, i32 0
  return _mm256_cvtss_f32(__a);
 }
+
+__m256 test_mm256_cmp_ps_true(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_ps_true
+ // CHECK: store <8 x float>   zeroinitializer, <8 x float>* %tmp, align 32
+ return _mm256_cmp_ps(a, b, _CMP_FALSE_OQ);
+}
+
+__m256 test_mm256_cmp_pd_false(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_pd_false
+ // CHECK: store <4 x double> zeroinitializer, <4 x double>* %tmp, align 32
+  return _mm256_cmp_pd(a, b, _CMP_FALSE_OQ);
+}
+
+__m256 test_mm256_cmp_ps_strue(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_ps_strue
+ // CHECK: store <8 x float>   zeroinitializer, <8 x float>* %tmp, align 32
+ return _mm256_cmp_ps(a, b, _CMP_FALSE_OS);
+}
+
+__m256 test_mm256_cmp_pd_sfalse(__m256 a, __m256 b) {
+ // CHECK-LABEL: @test_mm256_cmp_pd_sfalse
+ // CHECK: store <4 x double> zeroinitializer, <4 x double>* %tmp, align 32
+  return _mm256_cmp_pd(a, b, _CMP_FALSE_OS);
+}
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -7923,19 +7923,40 @@
 }
 
 // We can't handle 8-31 immediates with native IR, use the intrinsic.
+// Except for predicates that create constants.
 Intrinsic::ID ID;
 switch (BuiltinID) {
 default: llvm_unreachable("Unsupported intrinsic!");
 case X86::BI__builtin_ia32_cmpps:
   ID = Intrinsic::x86_sse_cmp_ps;
   break;
 case X86::BI__builtin_ia32_cmpps256:
+  // _CMP_TRUE_UQ, _CMP_TRUE_US produce -1,-1... vector
+  // on any input and _CMP_FALSE_OQ, _CMP_FALSE_OS produce 0, 0...
+  if (CC == 0xf || CC == 0xb || CC == 0x1b || CC == 0x1f) {
+ Value *Constant = (CC == 0xf || CC == 0x1f) ?
+llvm::Constant::getAllOnesValue(Builder.getInt32Ty()) :
+llvm::Constant::getNullValue(Builder.getInt32Ty());
+ Value *Vec = Builder.CreateVectorSplat(
+Ops[0]->getType()->getVectorNumElements(), Constant);
+ return Builder.CreateBitCast(Vec, Ops[0]->getType());
+  }
   ID = Intrinsic::x86_avx_cmp_ps_256;
   break;
 case X86::BI__builtin_ia32_cmppd:
   ID = Intrinsic::x86_sse2_cmp_pd;
   break;
 case X86::BI__builtin_ia32_cmppd256:
+  // _CMP_TRUE_UQ, _CMP_TRUE_US produce -1,-1... vector
+  // on any input and _CMP_FALSE_OQ, _CMP_FALSE_OS produce 0, 0...
+  if (CC == 0xf || CC == 0xb || CC == 0x1b || CC == 0x1f) {
+ Value *Constant = (CC == 0xf || CC == 0x1f) ?
+llvm::Constant::getAllOnesValue(Builder.getInt64Ty()) :
+llvm::Constant::getNullValue(Builder.getInt64Ty());
+ Value *Vec = Builder.CreateVectorSplat(
+Ops[0]->getType()->getVectorNumElements(), Constant);
+ return Builder.CreateBitCast(Vec, Ops[0]->getType());
+  }
   ID = Intrinsic::x86_avx_cmp_pd_256;
   break;
 }
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[PATCH] D123303: [Clang][AArch64][SVE] Add shift operators for SVE vector types

2022-04-08 Thread Dinar Temirbulatov via Phabricator via cfe-commits 
dtemirbulatov added a comment.

LGTM, Any remarks from others?


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[PATCH] D151199: [Clang][SVE2.1] Add pfalse builtin

2023-10-18 Thread Dinar Temirbulatov via Phabricator via cfe-commits 
dtemirbulatov accepted this revision.
dtemirbulatov added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D151439: [Clang][SVE2.1] Add builtins for 2-way svdot (vectors, indexed)

2023-10-18 Thread Dinar Temirbulatov via Phabricator via cfe-commits 
dtemirbulatov added inline comments.



Comment at: clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp:112
+  svfloat32_t f32, svfloat16_t f16) {
+  svdot_lane_s32_s16_s16(s32, s16, s16, 1); // expected-error {{argument value 
4 is outside the valid range [0, 3]}}
+  svdot_lane_u32_u16_u16(u32, u16, u16, 1); // expected-error {{argument value 
4 is outside the valid range [0, 3]}}

It looks like an incorrect error report?


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[PATCH] D151439: [Clang][SVE2.1] Add builtins for 2-way svdot (vectors, indexed)

2023-10-18 Thread Dinar Temirbulatov via Phabricator via cfe-commits 
dtemirbulatov added inline comments.



Comment at: clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp:112
+  svfloat32_t f32, svfloat16_t f16) {
+  svdot_lane_s32_s16_s16(s32, s16, s16, 1); // expected-error {{argument value 
4 is outside the valid range [0, 3]}}
+  svdot_lane_u32_u16_u16(u32, u16, u16, 1); // expected-error {{argument value 
4 is outside the valid range [0, 3]}}

dtemirbulatov wrote:
> It looks like an incorrect error report?
Oh, I see this is only syntax test. Resolved.


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[PATCH] D151439: [Clang][SVE2.1] Add builtins for 2-way svdot (vectors, indexed)

2023-10-18 Thread Dinar Temirbulatov via Phabricator via cfe-commits 
dtemirbulatov accepted this revision.
dtemirbulatov added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D151709: [Clang][SVE2.1] Add builtins for svrevd

2023-05-31 Thread Dinar Temirbulatov via Phabricator via cfe-commits 
dtemirbulatov accepted this revision.
dtemirbulatov added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D151307: [Clang][SVE2.1] Add svwhile (predicate-as-counter) builtins

2023-05-31 Thread Dinar Temirbulatov via Phabricator via cfe-commits 
dtemirbulatov added inline comments.



Comment at: clang/include/clang/Basic/arm_sve.td:2129
 
+def SVWHILEGE_COUNT  : SInst<"svwhilege_{d}",  "}lli", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilege_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILEGT_COUNT  : SInst<"svwhilegt_{d}",  "}lli", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilegt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;

I could not find where ImmCheck2_4_Mul2 is defined?


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