[PATCH] D59924: [PowerPC][Clang] Port MMX intrinsics and basic test cases to Power

2019-03-28 Thread Chaofan Qiu via Phabricator via cfe-commits 
qiucf created this revision.
qiucf added reviewers: hfinkel, nemanjai, jsji, rsmith.
Herald added subscribers: cfe-commits, jdoerfert, kbarton, mgorny.
Herald added a project: clang.

This patch is for porting existing headers which include x86 intrinsics (MMX, 
SSE, SSE2, etc.) implementation to PowerPC platform (using Altivec).

Since x86 intrinsic headers (like mmintrin.h) are already at clang's header 
directory, I overrided PowerPC's toolchain class to insert new headers 
directory (named ppc_wrappers) into the path. This patch contains tests for 
several intrinsic functions. More complete tests will come in future patches.

To make this patch not too long, I only added mmintrin.h (MMX instruction set 
header).


Repository:
  rC Clang

https://reviews.llvm.org/D59924

Files:
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/PPCLinux.cpp
  clang/lib/Driver/ToolChains/PPCLinux.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/ppc_wrappers/mmintrin.h
  clang/test/CodeGen/ppc-mmintrin.c
  clang/test/Headers/ppc-intrinsics.c

Index: clang/test/Headers/ppc-intrinsics.c
===
--- /dev/null
+++ clang/test/Headers/ppc-intrinsics.c
@@ -0,0 +1,13 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -DTEST_MACRO -target powerpc64-gnu-linux %s -Xclang -verify -o - | FileCheck %s
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -target powerpc64-gnu-linux %s -Xclang -verify -x c++ -o - | FileCheck %s
+// expected-no-diagnostics
+
+// RUN: NOT %clang -S -emit-llvm -target powerpc64-gnu-linux %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-ERROR
+
+#include 
+// CHECK-ERROR: mmintrin.h:{{[0-9]+}}:{{[0-9]+}}: error: "Please read comment above. Use -DNO_WARN_X86_INTRINSICS to disable this error."
+
+// CHECK: target triple = "powerpc64-
+// CHECK: !llvm.module.flags =
Index: clang/test/CodeGen/ppc-mmintrin.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc-mmintrin.c
@@ -0,0 +1,39 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64le-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s
+
+#include 
+
+unsigned long long int ull1, ull2;
+__m64 m1, m2, res;
+
+void __attribute__((noinline))
+test_packs() {
+  res = _mm_packs_pu16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi32((__m64)ull1, (__m64)ull2);
+}
+
+// CHECK-LABEL: @test_packs
+
+// CHECK: i64 @_mm_packs_pu16(i64 {{[0-9a-zA-Z_%.]+}}, i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG1:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmplt
+// CHECK: store <8 x i16> [[REG1]], <8 x i16>* [[REG2:[0-9a-zA-Z_%.]+]], align 16
+// CHECK: [[REG3:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_packs
+// CHECK: store <16 x i8> [[REG3]], <16 x i8>* [[REG4:[0-9a-zA-Z_%.]+]], align 16
+// CHECK: [[REG5:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG2]], align 16
+// CHECK: [[REG6:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG2]], align 16
+// CHECK: [[REG7:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_pack(bool vector[8], bool vector[8])(<8 x i16> [[REG5]], <8 x i16> [[REG6]])
+// CHECK: store <16 x i8> [[REG7]], <16 x i8>* [[REG8:[0-9a-zA-Z_%.]+]], align 16
+// CHECK: [[REG9:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG4]], align 16
+// CHECK: [[REG10:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG8]], align 16
+// CHECK: call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], bool vector[16])(<16 x i8> [[REG9]], <16 x i8> zeroinitializer, <16 x i8> [[REG10]])
+
+// CHECK: i64 @_mm_packs_pi16(i64 {{[0-9a-zA-Z_%.]+}}, i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: call <16 x i8> @vec_packs(short vector[8], short vector[8])
+
+// CHECK: i64 @_mm_packs_pi32(i64 {{[0-9a-zA-Z_%.]+}}, i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: call <8 x i16> @vec_packs(int vector[4], int vector[4])
Index: clang/lib/Headers/ppc_wrappers/mmintrin.h
===
--- /dev/null
+++ clang/lib/Headers/ppc_wrappers/mmintrin.h
@@ -0,0 +1,1457 @@
+/*=== mmintrin.h - Implementation of MMX intrinsics on PowerPC -===
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+

[PATCH] D59924: [PowerPC][Clang] Port MMX intrinsics and basic test cases to Power

2019-04-08 Thread Chaofan Qiu via Phabricator via cfe-commits 
qiucf marked 2 inline comments as done.
qiucf added inline comments.



Comment at: clang/lib/Driver/ToolChains/PPCLinux.cpp:22
+  if (getArch() != llvm::Triple::ppc &&
+  !DriverArgs.hasArg(clang::driver::options::OPT_nostdinc) &&
+  !DriverArgs.hasArg(options::OPT_nobuiltininc)) {

jsji wrote:
> Why we want to exclude these includes when `nostdinc` is on? These include 
> files are NOT standard include files.
> `-nostdinc`: Do not search the standard system directories or compiler 
> builtin directories for include files.
> From Clang's man page

And on Windows toolchain (MSVC.cpp), if turning on `-nostdinc`, Windows SDK 
files will also not be added into path.



Comment at: clang/test/Headers/ppc-intrinsics.c:7
+
+// RUN: NOT %clang -S -emit-llvm -target powerpc64-gnu-linux %s -o /dev/null 
2>&1 | FileCheck %s -check-prefix=CHECK-ERROR
+

jsji wrote:
> NOT? 
> ` NOT: command not found ^`
It should be `not`, in downcase. This is what other test cases (see 
`test/CXX/temp/temp.spec/no-body.cpp`) use, to assert a non-zero exit code of a 
command. Otherwise, `llvm-lit` would complain and give a failure.


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59924/new/

https://reviews.llvm.org/D59924



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[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

2019-04-09 Thread Chaofan Qiu via Phabricator via cfe-commits 
qiucf updated this revision to Diff 194253.
qiucf retitled this revision from "[PowerPC][Clang] Port MMX intrinsics and 
basic test cases to Power" to "[PowerPC] [Clang] Port MMX intrinsics and basic 
test cases to Power".
qiucf edited the summary of this revision.
qiucf added a comment.

- Add more check of mmintrin generated IR against endianness.
- Fix typo in PPCLinux header.
- Fix command error in ppc intrinsics header test.


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59924/new/

https://reviews.llvm.org/D59924

Files:
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/PPCLinux.cpp
  clang/lib/Driver/ToolChains/PPCLinux.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/ppc_wrappers/mmintrin.h
  clang/test/CodeGen/ppc-mmintrin.c
  clang/test/Headers/ppc-intrinsics.c

Index: clang/test/Headers/ppc-intrinsics.c
===
--- /dev/null
+++ clang/test/Headers/ppc-intrinsics.c
@@ -0,0 +1,13 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -target powerpc64-gnu-linux %s -Xclang -verify -o - | FileCheck %s
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -target powerpc64-gnu-linux %s -Xclang -verify -x c++ -o - | FileCheck %s
+// expected-no-diagnostics
+
+// RUN: not %clang -S -emit-llvm -target powerpc64-gnu-linux %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-ERROR
+
+#include 
+// CHECK-ERROR: mmintrin.h:{{[0-9]+}}:{{[0-9]+}}: error: "Please read comment above. Use -DNO_WARN_X86_INTRINSICS to disable this error."
+
+// CHECK: target triple = "powerpc64-
+// CHECK: !llvm.module.flags =
Index: clang/test/CodeGen/ppc-mmintrin.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc-mmintrin.c
@@ -0,0 +1,60 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64le-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+
+#include 
+
+unsigned long long int ull1, ull2;
+__m64 m1, m2, res;
+
+void __attribute__((noinline))
+test_packs() {
+  res = _mm_packs_pu16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi32((__m64)ull1, (__m64)ull2);
+}
+
+// CHECK-LABEL: @test_packs
+
+// CHECK: i64 @_mm_packs_pu16(i64 [[REG1:[0-9a-zA-Z_%.]+]], i64 [[REG2:[0-9a-zA-Z_%.]+]])
+// CHECK: store i64 [[REG1]], i64* [[REG3:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-NEXT: store i64 [[REG2]], i64* [[REG4:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-LE: load i64, i64* [[REG3]], align 8
+// CHECK: load i64, i64* [[REG4]], align 8
+// CHECK-BE: load i64, i64* [[REG3]], align 8
+// CHECK: [[REG5:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmplt
+// CHECK-NEXT: store <8 x i16> [[REG5]], <8 x i16>* [[REG6:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG7:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG8:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG8]], align 16
+// CHECK-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_packs(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG7]], <8 x i16> [[REG9]])
+// CHECK-NEXT: store <16 x i8> [[REG10]], <16 x i8>* [[REG11:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG12:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG6]], align 16
+// CHECK-NEXT: [[REG13:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG6]], align 16
+// CHECK-NEXT: [[REG14:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_pack(bool vector[8], bool vector[8])(<8 x i16> [[REG12]], <8 x i16> [[REG13]])
+// CHECK-NEXT: store <16 x i8> [[REG14]], <16 x i8>* [[REG15:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG16:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG11]], align 16
+// CHECK-NEXT: [[REG17:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG15]], align 16
+// CHECK-NEXT: call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], bool vector[16])(<16 x i8> [[REG16]], <16 x i8> zeroinitializer, <16 x i8> [[REG17]])
+
+// CHECK: i64 @_mm_packs_pi16(i64 [[REG18:[0-9a-zA-Z_%.]+]], i64 [[REG19:[0-9a-zA-Z_%.]+]])
+// CHECK: store i64 [[REG18]], i64* [[REG20:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-NEXT: store i64 [[REG19]], i64* [[REG21:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-LE: load i64, i64* [[REG20]], align 8
+// CHECK: load i64, i64* [[REG21]], align 8
+// CHECK-BE: load i64, i64* [[REG20]], align 8
+// CHECK: [[REG22:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG23:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG24:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG23]], align 16
+/

[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

2019-04-09 Thread Chaofan Qiu via Phabricator via cfe-commits 
qiucf updated this revision to Diff 194446.
qiucf added a comment.

Fix error about a mismatch in mmintrin test cases.


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59924/new/

https://reviews.llvm.org/D59924

Files:
  clang/lib/Driver/CMakeLists.txt
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/PPCLinux.cpp
  clang/lib/Driver/ToolChains/PPCLinux.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/ppc_wrappers/mmintrin.h
  clang/test/CodeGen/ppc-mmintrin.c
  clang/test/Headers/ppc-intrinsics.c

Index: clang/test/Headers/ppc-intrinsics.c
===
--- /dev/null
+++ clang/test/Headers/ppc-intrinsics.c
@@ -0,0 +1,13 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -target powerpc64-gnu-linux %s -Xclang -verify -o - | FileCheck %s
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -target powerpc64-gnu-linux %s -Xclang -verify -x c++ -o - | FileCheck %s
+// expected-no-diagnostics
+
+// RUN: not %clang -S -emit-llvm -target powerpc64-gnu-linux %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-ERROR
+
+#include 
+// CHECK-ERROR: mmintrin.h:{{[0-9]+}}:{{[0-9]+}}: error: "Please read comment above. Use -DNO_WARN_X86_INTRINSICS to disable this error."
+
+// CHECK: target triple = "powerpc64-
+// CHECK: !llvm.module.flags =
Index: clang/test/CodeGen/ppc-mmintrin.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc-mmintrin.c
@@ -0,0 +1,60 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s --check-prefixes=CHECK,CHECK-BE
+// RUN: %clang -S -emit-llvm -DNO_WARN_X86_INTRINSICS -mcpu=pwr8 -target powerpc64le-gnu-linux %s \
+// RUN:-mllvm -disable-llvm-optzns -o - | llvm-cxxfilt | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+
+#include 
+
+unsigned long long int ull1, ull2;
+__m64 m1, m2, res;
+
+void __attribute__((noinline))
+test_packs() {
+  res = _mm_packs_pu16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi16((__m64)ull1, (__m64)ull2);
+  res = _mm_packs_pi32((__m64)ull1, (__m64)ull2);
+}
+
+// CHECK-LABEL: @test_packs
+
+// CHECK: define available_externally i64 @_mm_packs_pu16(i64 [[REG1:[0-9a-zA-Z_%.]+]], i64 [[REG2:[0-9a-zA-Z_%.]+]])
+// CHECK: store i64 [[REG1]], i64* [[REG3:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-NEXT: store i64 [[REG2]], i64* [[REG4:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-LE: load i64, i64* [[REG3]], align 8
+// CHECK: load i64, i64* [[REG4]], align 8
+// CHECK-BE: load i64, i64* [[REG3]], align 8
+// CHECK: [[REG5:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmplt
+// CHECK-NEXT: store <8 x i16> [[REG5]], <8 x i16>* [[REG6:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG7:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG8:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG8]], align 16
+// CHECK-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_packs(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG7]], <8 x i16> [[REG9]])
+// CHECK-NEXT: store <16 x i8> [[REG10]], <16 x i8>* [[REG11:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG12:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG6]], align 16
+// CHECK-NEXT: [[REG13:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG6]], align 16
+// CHECK-NEXT: [[REG14:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_pack(bool vector[8], bool vector[8])(<8 x i16> [[REG12]], <8 x i16> [[REG13]])
+// CHECK-NEXT: store <16 x i8> [[REG14]], <16 x i8>* [[REG15:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG16:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG11]], align 16
+// CHECK-NEXT: [[REG17:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG15]], align 16
+// CHECK-NEXT: call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], bool vector[16])(<16 x i8> [[REG16]], <16 x i8> zeroinitializer, <16 x i8> [[REG17]])
+
+// CHECK: define available_externally i64 @_mm_packs_pi16(i64 [[REG18:[0-9a-zA-Z_%.]+]], i64 [[REG19:[0-9a-zA-Z_%.]+]])
+// CHECK: store i64 [[REG18]], i64* [[REG20:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-NEXT: store i64 [[REG19]], i64* [[REG21:[0-9a-zA-Z_%.]+]], align 8
+// CHECK-LE: load i64, i64* [[REG20]], align 8
+// CHECK: load i64, i64* [[REG21]], align 8
+// CHECK-BE: load i64, i64* [[REG20]], align 8
+// CHECK: [[REG22:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG23:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: [[REG24:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG23]], align 16
+// CHECK-NEXT: call <16 x i8> @vec_packs(short vector[8], short vector[8])(<8 x i16> [[REG22]], <8 x i16> [[REG24]])
+
+// CHECK: define available_externally i64 @_mm_packs_pi32(i64 [[REG25:[0-9a-zA-Z_%.]+]], i64 [[REG26:[0-9a-zA-Z_%.]+]])
+// CHECK: store i64

[PATCH] D59924: [PowerPC] [Clang] Port MMX intrinsics and basic test cases to Power

2019-04-09 Thread Chaofan Qiu via Phabricator via cfe-commits 
qiucf marked an inline comment as done.
qiucf added a comment.

Part of a function signature can also match where it is called, so the test 
failed. I did the changes to pass the test but diff file was generated locally 
so it didn't contain this change. Sorry for the mistake.


Repository:
  rC Clang

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[PATCH] D64849: Add platform guards to PPC vector intrinsics headers.

2019-07-16 Thread Chaofan Qiu via Phabricator via cfe-commits 
qiucf created this revision.
qiucf added reviewers: jsji, hfinkel, nemanjai, wschmidt, kbarton, 
hubert.reinterpretcast.
qiucf added a project: clang.
Herald added subscribers: cfe-commits, MaskRay, krytarowski.

Intrinsic headers are supported only on 64-bit PowerPC. This patch is to move 
the platform check out of PPC Linux toolchain code and add platform guards to 
the intrinsic headers.


Repository:
  rC Clang

https://reviews.llvm.org/D64849

Files:
  clang/lib/Driver/ToolChains/PPCLinux.cpp
  clang/lib/Headers/ppc_wrappers/emmintrin.h
  clang/lib/Headers/ppc_wrappers/mm_malloc.h
  clang/lib/Headers/ppc_wrappers/mmintrin.h
  clang/lib/Headers/ppc_wrappers/xmmintrin.h

Index: clang/lib/Headers/ppc_wrappers/xmmintrin.h
===
--- clang/lib/Headers/ppc_wrappers/xmmintrin.h
+++ clang/lib/Headers/ppc_wrappers/xmmintrin.h
@@ -34,6 +34,8 @@
 #ifndef _XMMINTRIN_H_INCLUDED
 #define _XMMINTRIN_H_INCLUDED
 
+#if defined(__linux__) && defined(__ppc64__)
+
 /* Define four value permute mask */
 #define _MM_SHUFFLE(w,x,y,z) (((w) << 6) | ((x) << 4) | ((y) << 2) | (z))
 
@@ -1835,4 +1837,8 @@
 /* For backward source compatibility.  */
 //# include 
 
+#else
+#include_next 
+#endif /* defined(__linux__) && defined(__ppc64__) */
+
 #endif /* _XMMINTRIN_H_INCLUDED */
Index: clang/lib/Headers/ppc_wrappers/mmintrin.h
===
--- clang/lib/Headers/ppc_wrappers/mmintrin.h
+++ clang/lib/Headers/ppc_wrappers/mmintrin.h
@@ -35,6 +35,8 @@
 #ifndef _MMINTRIN_H_INCLUDED
 #define _MMINTRIN_H_INCLUDED
 
+#if defined(__linux__) && defined(__ppc64__)
+
 #include 
 /* The Intel API is flexible enough that we must allow aliasing with other
vector types, and their scalar components.  */
@@ -1440,4 +1442,9 @@
   return (res.as_m64);
 #endif
 }
+
+#else
+#include_next 
+#endif /* defined(__linux__) && defined(__ppc64__) */
+
 #endif /* _MMINTRIN_H_INCLUDED */
Index: clang/lib/Headers/ppc_wrappers/mm_malloc.h
===
--- clang/lib/Headers/ppc_wrappers/mm_malloc.h
+++ clang/lib/Headers/ppc_wrappers/mm_malloc.h
@@ -10,6 +10,8 @@
 #ifndef _MM_MALLOC_H_INCLUDED
 #define _MM_MALLOC_H_INCLUDED
 
+#if defined(__linux__) && defined(__ppc64__)
+
 #include 
 
 /* We can't depend on  since the prototype of posix_memalign
@@ -45,4 +47,8 @@
   free (ptr);
 }
 
+#else
+#include_next 
+#endif
+
 #endif /* _MM_MALLOC_H_INCLUDED */
Index: clang/lib/Headers/ppc_wrappers/emmintrin.h
===
--- clang/lib/Headers/ppc_wrappers/emmintrin.h
+++ clang/lib/Headers/ppc_wrappers/emmintrin.h
@@ -35,6 +35,8 @@
 #ifndef EMMINTRIN_H_
 #define EMMINTRIN_H_
 
+#if defined(__linux__) && defined(__ppc64__)
+
 #include 
 
 /* We need definitions from the SSE header files.  */
@@ -2315,4 +2317,8 @@
   return (__m128d) __A;
 }
 
+#else
+#include_next 
+#endif /* defined(__linux__) && defined(__ppc64__) */
+
 #endif /* EMMINTRIN_H_ */
Index: clang/lib/Driver/ToolChains/PPCLinux.cpp
===
--- clang/lib/Driver/ToolChains/PPCLinux.cpp
+++ clang/lib/Driver/ToolChains/PPCLinux.cpp
@@ -16,10 +16,7 @@
 
 void PPCLinuxToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs,
   ArgStringList &CC1Args) const {
-  // PPC wrapper headers are implementation of x86 intrinsics on PowerPC, which
-  // is not supported on PPC32 platform.
-  if (getArch() != llvm::Triple::ppc &&
-  !DriverArgs.hasArg(clang::driver::options::OPT_nostdinc) &&
+  if (!DriverArgs.hasArg(clang::driver::options::OPT_nostdinc) &&
   !DriverArgs.hasArg(options::OPT_nobuiltininc)) {
 const Driver &D = getDriver();
 SmallString<128> P(D.ResourceDir);
___
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[PATCH] D64850: Remove use of malloc in PPC mm_malloc.

2019-07-16 Thread Chaofan Qiu via Phabricator via cfe-commits 
qiucf created this revision.
qiucf added reviewers: hubert.reinterpretcast, jsji, wschmidt, nemanjai, 
kbarton.
qiucf added a project: clang.
Herald added a subscriber: cfe-commits.

Remove dependency of `malloc` in implementation of `mm_malloc` function and 
alignment assumption on glibc.


Repository:
  rC Clang

https://reviews.llvm.org/D64850

Files:
  clang/lib/Headers/ppc_wrappers/mm_malloc.h
  clang/test/CodeGen/ppc-mm-malloc-le.c
  clang/test/CodeGen/ppc-mm-malloc.c


Index: clang/test/CodeGen/ppc-mm-malloc.c
===
--- clang/test/CodeGen/ppc-mm-malloc.c
+++ clang/test/CodeGen/ppc-mm-malloc.c
@@ -24,30 +24,14 @@
 // CHECK: store i64 [[REG1]], i64* [[REG4:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: store i64 [[REG2]], i64* [[REG5:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: store i64 16, i64* [[REG6:[0-9a-zA-Z_%.]+]], align 8
-// CHECK-NEXT: store i64 16, i64* [[REG7:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: [[REG8:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG5]], align 8
-// CHECK-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG7]], align 8
-// CHECK-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = icmp eq i64 [[REG8]], [[REG9]]
-// CHECK-NEXT: br i1 [[REG10]], label %[[REG11:[0-9a-zA-Z_%.]+]], label 
%[[REG12:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG11]]:
-// CHECK-NEXT: [[REG13:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG5]], align 8
-// CHECK-NEXT: [[REG14:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG6]], align 8
-// CHECK-NEXT: [[REG15:[0-9a-zA-Z_%.]+]] = icmp eq i64 [[REG13]], [[REG14]]
-// CHECK-NEXT: br i1 [[REG15]], label %[[REG16:[0-9a-zA-Z_%.]+]], label 
%[[REG12:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG16]]:
-// CHECK-NEXT: [[REG17:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG4]], align 8
-// CHECK-NEXT: [[REG18:[0-9a-zA-Z_%.]+]] = call noalias i8* @malloc(i64 
[[REG17]])
-// CHECK-NEXT: store i8* [[REG18]], i8** [[REG3]], align 8
-// CHECK-NEXT: br label %[[REG19:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG12]]:
-// CHECK-NEXT: [[REG20:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG5]], align 8
-// CHECK-NEXT: [[REG21:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG6]], align 8
-// CHECK-NEXT: [[REG22:[0-9a-zA-Z_%.]+]] = icmp ult i64 [[REG20]], [[REG21]]
-// CHECK-NEXT: br i1 [[REG22]], label %[[REG23:[0-9a-zA-Z_%.]+]], label 
%[[REG24:[0-9a-zA-Z_%.]+]]
+// CHECK-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG6]], align 8
+// CHECK-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = icmp ult i64 [[REG8]], [[REG9]]
+// CHECK-NEXT: br i1 [[REG10]], label %[[REG23:[0-9a-zA-Z_%.]+]], label 
%[[REG24:[0-9a-zA-Z_%.]+]]
 // CHECK: [[REG23]]:
 // CHECK-NEXT: [[REG25:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG6]], align 8
 // CHECK-NEXT: store i64 [[REG25]], i64* [[REG5]], align 8
-// CHECK-NEXT: br label %[[REG12:[0-9a-zA-Z_%.]+]]4
+// CHECK-NEXT: br label %[[REG24:[0-9a-zA-Z_%.]+]]
 // CHECK: [[REG24]]:
 // CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG5]], align 8
 // CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG4]], align 8
Index: clang/test/CodeGen/ppc-mm-malloc-le.c
===
--- clang/test/CodeGen/ppc-mm-malloc-le.c
+++ clang/test/CodeGen/ppc-mm-malloc-le.c
@@ -24,30 +24,14 @@
 // CHECK: store i64 [[REG1]], i64* [[REG4:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: store i64 [[REG2]], i64* [[REG5:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: store i64 16, i64* [[REG6:[0-9a-zA-Z_%.]+]], align 8
-// CHECK-NEXT: store i64 16, i64* [[REG7:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: [[REG8:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG5]], align 8
-// CHECK-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG7]], align 8
-// CHECK-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = icmp eq i64 [[REG8]], [[REG9]]
-// CHECK-NEXT: br i1 [[REG10]], label %[[REG11:[0-9a-zA-Z_%.]+]], label 
%[[REG12:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG11]]:
-// CHECK-NEXT: [[REG13:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG5]], align 8
-// CHECK-NEXT: [[REG14:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG6]], align 8
-// CHECK-NEXT: [[REG15:[0-9a-zA-Z_%.]+]] = icmp eq i64 [[REG13]], [[REG14]]
-// CHECK-NEXT: br i1 [[REG15]], label %[[REG16:[0-9a-zA-Z_%.]+]], label 
%[[REG12:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG16]]:
-// CHECK-NEXT: [[REG17:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG4]], align 8
-// CHECK-NEXT: [[REG18:[0-9a-zA-Z_%.]+]] = call noalias i8* @malloc(i64 
[[REG17]])
-// CHECK-NEXT: store i8* [[REG18]], i8** [[REG3]], align 8
-// CHECK-NEXT: br label %[[REG19:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG12]]:
-// CHECK-NEXT: [[REG20:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG5]], align 8
-// CHECK-NEXT: [[REG21:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG6]], align 8
-// CHECK-NEXT: [[REG22:[0-9a-zA-Z_%.]+]] = icmp ult i64 [[REG20]], [[REG21]]
-// CHECK-NEXT: br i1 [[REG22]], label %[[REG23:[0-9a-zA-Z_%.]+]], label 
%[[REG24:[0-9a-zA-Z_%.]+]]
+// CHECK-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG6]], align 8
+// CHECK-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = icmp ult i64 [[REG8]], [[REG9]]
+// CHECK-NEXT: