[clang] 1b93e15 - [Clang][SVE2p1] Add svpsel builtins

2023-10-18 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2023-10-18T15:05:26Z
New Revision: 1b93e15bcd9a270e5d5233f548f402a6bd684177

URL: 
https://github.com/llvm/llvm-project/commit/1b93e15bcd9a270e5d5233f548f402a6bd684177
DIFF: 
https://github.com/llvm/llvm-project/commit/1b93e15bcd9a270e5d5233f548f402a6bd684177.diff

LOG: [Clang][SVE2p1] Add svpsel builtins

 As described in: https://github.com/ARM-software/acle/pull/257

Patch by : Sander de Smalen

Reviewed By: kmclaughlin

Differential Revision: https://reviews.llvm.org/D151197

Added: 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c

Modified: 
clang/include/clang/Basic/arm_sve.td
clang/lib/CodeGen/CGBuiltin.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index f54e65ef7119cc1..25a28052ed0d97f 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1865,10 +1865,21 @@ def SVPTRUE_COUNT  : SInst<"svptrue_{d}", "}v", 
"QcQsQiQl", MergeNone, "aarch64_
 
 def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_pext", [], [ImmCheck<1, ImmCheck0_3>]>;
 def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl", 
MergeNone, "aarch64_sve_pext_x2", [], [ImmCheck<1, ImmCheck0_1>]>;
+
+def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8",  "}}Pm", "Pc", MergeNone, 
"", [], []>;
+def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone, 
"", [], []>;
+def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone, 
"", [], []>;
+def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone, 
"", [], []>;
 }
 
 let TargetGuard = "sve2p1" in {
 def SVSCLAMP : SInst<"svclamp[_{d}]", "", "csil", MergeNone, 
"aarch64_sve_sclamp", [], []>;
 def SVUCLAMP : SInst<"svclamp[_{d}]", "", "UcUsUiUl", MergeNone, 
"aarch64_sve_uclamp", [], []>;
+
+def SVPSEL_B : SInst<"svpsel_lane_b8",  "PPPm", "Pc", MergeNone, "", [], []>;
+def SVPSEL_H : SInst<"svpsel_lane_b16", "PPPm", "Ps", MergeNone, "", [], []>;
+def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "", [], []>;
+def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "", [], []>;
+
 def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_cntp_{d}", [IsOverloadNone], [ImmCheck<1, ImmCheck2_4_Mul2>]>;
 }

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 116af1435fe6e40..3602c6564893d0a 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -10007,7 +10007,33 @@ Value 
*CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
   switch (BuiltinID) {
   default:
 return nullptr;
-
+  case SVE::BI__builtin_sve_svpsel_lane_b8:
+  case SVE::BI__builtin_sve_svpsel_lane_b16:
+  case SVE::BI__builtin_sve_svpsel_lane_b32:
+  case SVE::BI__builtin_sve_svpsel_lane_b64:
+  case SVE::BI__builtin_sve_svpsel_lane_c8:
+  case SVE::BI__builtin_sve_svpsel_lane_c16:
+  case SVE::BI__builtin_sve_svpsel_lane_c32:
+  case SVE::BI__builtin_sve_svpsel_lane_c64: {
+bool IsSVCount = isa(Ops[0]->getType());
+assert(((!IsSVCount || cast(Ops[0]->getType())->getName() ==
+   "aarch64.svcount")) &&
+   "Unexpected TargetExtType");
+auto SVCountTy =
+llvm::TargetExtType::get(getLLVMContext(), "aarch64.svcount");
+Function *CastFromSVCountF =
+CGM.getIntrinsic(Intrinsic::aarch64_sve_convert_to_svbool, SVCountTy);
+Function *CastToSVCountF =
+CGM.getIntrinsic(Intrinsic::aarch64_sve_convert_from_svbool, 
SVCountTy);
+
+auto OverloadedTy = getSVEType(SVETypeFlags(Builtin->TypeModifier));
+Function *F = CGM.getIntrinsic(Intrinsic::aarch64_sve_psel, OverloadedTy);
+llvm::Value *Ops0 =
+IsSVCount ? Builder.CreateCall(CastFromSVCountF, Ops[0]) : Ops[0];
+llvm::Value *Ops1 = EmitSVEPredicateCast(Ops[1], OverloadedTy);
+llvm::Value *PSel = Builder.CreateCall(F, {Ops0, Ops1, Ops[2]});
+return IsSVCount ? Builder.CreateCall(CastToSVCountF, PSel) : PSel;
+  }
   case SVE::BI__builtin_sve_svmov_b_z: {
 // svmov_b_z(pg, op) <=> svand_b_z(pg, op, op)
 SVETypeFlags TypeFlags(Builtin->TypeModifier);

diff  --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c
new file mode 100644
index 000..97354d75d7b8743
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_psel.c
@@ -0,0 +1,165 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \
+// RUN:   -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \
+// RUN:   -target-feature +sve2p1 -S -O1

[clang] ba47bc7 - [Clang][SVE2.1] Add pfalse builtin

2023-10-19 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2023-10-19T08:55:32Z
New Revision: ba47bc7fd41278926552becca758d42cf4f793c1

URL: 
https://github.com/llvm/llvm-project/commit/ba47bc7fd41278926552becca758d42cf4f793c1
DIFF: 
https://github.com/llvm/llvm-project/commit/ba47bc7fd41278926552becca758d42cf4f793c1.diff

LOG: [Clang][SVE2.1] Add pfalse builtin

As described in: https://github.com/ARM-software/acle/pull/257

Patch by : Sander de Smalen

Reviewed By: dtemirbulatov

Differential Revision: https://reviews.llvm.org/D151199

Added: 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pfalse.c

Modified: 
clang/include/clang/Basic/arm_sve.td
clang/lib/CodeGen/CGBuiltin.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 25a28052ed0d97f..8034cc0c2f04a2b 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1862,6 +1862,7 @@ def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", "UcUsUiUl", 
MergeNone, "aarch64_sv
 let TargetGuard = "sve2p1" in {
 def SVFCLAMP   : SInst<"svclamp[_{d}]", "", "hfd", MergeNone, 
"aarch64_sve_fclamp", [], []>;
 def SVPTRUE_COUNT  : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone, 
"aarch64_sve_ptrue_{d}", [IsOverloadNone], []>;
+def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "", 
[IsOverloadNone]>;
 
 def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_pext", [], [ImmCheck<1, ImmCheck0_3>]>;
 def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl", 
MergeNone, "aarch64_sve_pext_x2", [], [ImmCheck<1, ImmCheck0_1>]>;

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index db9f354fa8386d3..2b341b8090fad7d 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -10160,6 +10160,13 @@ Value 
*CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
   case SVE::BI__builtin_sve_svpfalse_b:
 return ConstantInt::getFalse(Ty);
 
+  case SVE::BI__builtin_sve_svpfalse_c: {
+auto SVBoolTy = ScalableVectorType::get(Builder.getInt1Ty(), 16);
+Function *CastToSVCountF =
+CGM.getIntrinsic(Intrinsic::aarch64_sve_convert_from_svbool, Ty);
+return Builder.CreateCall(CastToSVCountF, ConstantInt::getFalse(SVBoolTy));
+  }
+
   case SVE::BI__builtin_sve_svlen_bf16:
   case SVE::BI__builtin_sve_svlen_f16:
   case SVE::BI__builtin_sve_svlen_f32:

diff  --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pfalse.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pfalse.c
new file mode 100644
index 000..5432862dcf52734
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pfalse.c
@@ -0,0 +1,30 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S 
-passes=mem2reg,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S 
-passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s 
| opt -S -passes=mem2reg,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x 
c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -o /dev/null %s
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+// CHECK-LABEL: @test_svpfalse_c(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call target("aarch64.svcount") 
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt( 
zeroinitializer)
+// CHECK-NEXT:ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z15test_svpfalse_cv(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call target("aarch64.svcount") 
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt( 
zeroinitializer)
+// CPP-CHECK-NEXT:ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svpfalse_c()
+{
+  return SVE_ACLE_FUNC(svpfalse_c,,,)();
+}



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[clang] 4ed0dfe - [Clang][SVE2.1] Add svwhile (predicate-as-counter) builtins

2023-10-19 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2023-10-19T10:47:32Z
New Revision: 4ed0dfe6adfe2a8b7b1420fec313c4250542747e

URL: 
https://github.com/llvm/llvm-project/commit/4ed0dfe6adfe2a8b7b1420fec313c4250542747e
DIFF: 
https://github.com/llvm/llvm-project/commit/4ed0dfe6adfe2a8b7b1420fec313c4250542747e.diff

LOG: [Clang][SVE2.1] Add svwhile (predicate-as-counter) builtins

As described in: https://github.com/ARM-software/acle/pull/257

Patch by : David Sherwood 

Reviewed By: kmclaughlin

Differential Revision: https://reviews.llvm.org/D151307

Added: 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_while_pn.c

Modified: 
clang/include/clang/Basic/arm_sve.td
clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 8034cc0c2f04a2b..8f9bdd18829ff6b 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1871,6 +1871,15 @@ def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8",  
"}}Pm", "Pc", MergeNone, "",
 def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone, 
"", [], []>;
 def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone, 
"", [], []>;
 def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone, 
"", [], []>;
+
+def SVWHILEGE_COUNT  : SInst<"svwhilege_{d}",  "}lli", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilege_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILEGT_COUNT  : SInst<"svwhilegt_{d}",  "}lli", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilegt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILELE_COUNT  : SInst<"svwhilele_{d}",  "}lli", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilele_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILELT_COUNT  : SInst<"svwhilelt_{d}",  "}lli", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilelt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILELO_COUNT  : SInst<"svwhilelo_{d}",  "}nni", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilelo_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILELS_COUNT  : SInst<"svwhilels_{d}",  "}nni", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilels_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILEHI_COUNT  : SInst<"svwhilehi_{d}",  "}nni", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilehi_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
+def SVWHILEHS_COUNT  : SInst<"svwhilehs_{d}",  "}nni", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilehs_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
 }
 
 let TargetGuard = "sve2p1" in {

diff  --git 
a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_while_pn.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_while_pn.c
new file mode 100644
index 000..3dbb38582b676c3
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_while_pn.c
@@ -0,0 +1,992 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s 
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -o /dev/null %s
+
+// REQUIRES: aarch64-registered-target
+
+#include 
+
+
+// WHILEGE
+
+// CHECK-LABEL: @test_svwhilege_c8_vl2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call target("aarch64.svcount") 
@llvm.aarch64.sve.whilege.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CHECK-NEXT:ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilege_c8_vl2ll(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call target("aarch64.svcount") 
@llvm.aarch64.sve.whilege.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 2)
+// CPP-CHECK-NEXT:ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilege_c8_vl2(int64_t op1, int64_t op2)
+{
+  return svwhilege_c8(op1, op2, 2);
+}
+
+// CHECK-LABEL: @test_svwhilege_c8_vl4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call target("aarch64.svcount") 
@llvm.aarch64.sve.whilege.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CHECK-NEXT:ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z21test_svwhilege_c8_vl4ll(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call target("aarch64.svcount") 
@llvm.aarch64.sve.whilege.c8(i64 [[OP1:%.*]], i64 [[OP2:%.*]], i32 4)
+// CPP-CHECK-NEXT:ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svwhilege_c8_vl4(int64_t op1, int64_t op2)
+{
+  return svwhilege_c8(op1, op2, 4);
+}
+
+// CHECK-LABEL: @test_sv

[clang] 9f93a99 - [Clang][SVE2.1] Add builtins for 2-way svdot (vectors, indexed)

2023-10-19 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2023-10-19T16:10:51Z
New Revision: 9f93a99a096c093b5c205cf9143d88ba1b53

URL: 
https://github.com/llvm/llvm-project/commit/9f93a99a096c093b5c205cf9143d88ba1b53
DIFF: 
https://github.com/llvm/llvm-project/commit/9f93a99a096c093b5c205cf9143d88ba1b53.diff

LOG: [Clang][SVE2.1] Add builtins for 2-way svdot (vectors, indexed)

As described in: https://github.com/ARM-software/acle/pull/257

Patch by: David Sherwood 

Reviewed By: dtemirbulatov

Differential Revision: https://reviews.llvm.org/D151439

Added: 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c

Modified: 
clang/include/clang/Basic/arm_sve.td
clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 8684b4ff1b6053e..8750e75f2a777a6 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1952,6 +1952,13 @@ def SVSTNT1B_VNUM_X4 : MInst<"svstnt1_vnum[_{2}_x4]", 
"v}pl4", "cUc", [IsStructS
 def SVSTNT1H_VNUM_X4 : MInst<"svstnt1_vnum[_{2}_x4]", "v}pl4", "sUshb", 
[IsStructStore], MemEltTyDefault, "aarch64_sve_stnt1_pn_x4">;
 def SVSTNT1W_VNUM_X4 : MInst<"svstnt1_vnum[_{2}_x4]", "v}pl4", "iUif", 
[IsStructStore], MemEltTyDefault, "aarch64_sve_stnt1_pn_x4">;
 def SVSTNT1D_VNUM_X4 : MInst<"svstnt1_vnum[_{2}_x4]", "v}pl4", "lUld", 
[IsStructStore], MemEltTyDefault, "aarch64_sve_stnt1_pn_x4">;
+
+def SVDOT_X2_S : SInst<"svdot[_{d}_{2}_{3}]", "ddhh", "i",  MergeNone, 
"aarch64_sve_sdot_x2", [], []>;
+def SVDOT_X2_U : SInst<"svdot[_{d}_{2}_{3}]", "ddhh", "Ui", MergeNone, 
"aarch64_sve_udot_x2", [], []>;
+def SVDOT_X2_F : SInst<"svdot[_{d}_{2}_{3}]", "ddhh", "f",  MergeNone, 
"aarch64_sve_fdot_x2", [], []>;
+def SVDOT_LANE_X2_S : SInst<"svdot_lane[_{d}_{2}_{3}]", "ddhhi", "i",  
MergeNone, "aarch64_sve_sdot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>;
+def SVDOT_LANE_X2_U : SInst<"svdot_lane[_{d}_{2}_{3}]", "ddhhi", "Ui", 
MergeNone, "aarch64_sve_udot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>;
+def SVDOT_LANE_X2_F : SInst<"svdot_lane[_{d}_{2}_{3}]", "ddhhi", "f",  
MergeNone, "aarch64_sve_fdot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>;
 }
 
 let TargetGuard = "sve2p1" in {

diff  --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c
new file mode 100644
index 000..d50be9ae177d790
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c
@@ -0,0 +1,107 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p 
mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p 
mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s 
| opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x 
c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -o /dev/null %s
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3) A1##A2##A3
+#endif
+
+// CHECK-LABEL: @test_svdot_s32_x2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.sdot.x2.nxv4i32( [[OP1:%.*]],  [[OP2:%.*]],  [[OP3:%.*]])
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: 
@_Z17test_svdot_s32_x2u11__SVInt32_tu11__SVInt16_tu11__SVInt16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.sdot.x2.nxv4i32( [[OP1:%.*]],  [[OP2:%.*]],  [[OP3:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint32_t test_svdot_s32_x2(svint32_t op1, svint16_t op2, svint16_t op3)
+{
+  return SVE_ACLE_FUNC(svdot,_s32_s16_s16,)(op1, op2, op3);
+}
+
+// CHECK-LABEL: @test_svdot_u32_x2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.udot.x2.nxv4i32( [[OP1:%.*]],  [[OP2:%.*]],  [[OP3:%.*]])
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: 
@_Z17test_svdot_u32_x2u12__SVUint32_tu12__SVUint16_tu12__SVUint16_t(
+// CPP-CHECK-NEXT:

[clang] 200a925 - [Clang][SVE2.1] Add builtins and intrinsics for SVBFMLSLB/T

2023-10-19 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2023-10-19T16:44:39Z
New Revision: 200a92520c255c20c916c11e9c240f07b9218380

URL: 
https://github.com/llvm/llvm-project/commit/200a92520c255c20c916c11e9c240f07b9218380
DIFF: 
https://github.com/llvm/llvm-project/commit/200a92520c255c20c916c11e9c240f07b9218380.diff

LOG: [Clang][SVE2.1] Add builtins and intrinsics for SVBFMLSLB/T

As described in: https://github.com/ARM-software/acle/pull/257

Patch by: Kerry McLaughlin 

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D151461

Added: 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmls.ll

Modified: 
clang/include/clang/Basic/arm_sve.td
clang/include/clang/Basic/arm_sve_sme_incl.td
clang/utils/TableGen/SveEmitter.cpp
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 8750e75f2a777a6..a1585443e5fd229 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1959,6 +1959,12 @@ def SVDOT_X2_F : SInst<"svdot[_{d}_{2}_{3}]", "ddhh", 
"f",  MergeNone, "aarch64_
 def SVDOT_LANE_X2_S : SInst<"svdot_lane[_{d}_{2}_{3}]", "ddhhi", "i",  
MergeNone, "aarch64_sve_sdot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>;
 def SVDOT_LANE_X2_U : SInst<"svdot_lane[_{d}_{2}_{3}]", "ddhhi", "Ui", 
MergeNone, "aarch64_sve_udot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>;
 def SVDOT_LANE_X2_F : SInst<"svdot_lane[_{d}_{2}_{3}]", "ddhhi", "f",  
MergeNone, "aarch64_sve_fdot_lane_x2", [], [ImmCheck<3, ImmCheck0_3>]>;
+
+def SVBFMLSLB : SInst<"svbfmlslb[_{d}]", "dd$$", "f", MergeNone, 
"aarch64_sve_bfmlslb", [IsOverloadNone], []>;
+def SVBFMLSLT : SInst<"svbfmlslt[_{d}]", "dd$$", "f", MergeNone, 
"aarch64_sve_bfmlslt", [IsOverloadNone], []>;
+
+def SVBFMLSLB_LANE : SInst<"svbfmlslb_lane[_{d}]", "dd$$i", "f", MergeNone, 
"aarch64_sve_bfmlslb_lane", [IsOverloadNone], [ImmCheck<3, ImmCheck0_7>]>;
+def SVBFMLSLT_LANE : SInst<"svbfmlslt_lane[_{d}]", "dd$$i", "f", MergeNone, 
"aarch64_sve_bfmlslt_lane", [IsOverloadNone], [ImmCheck<3, ImmCheck0_7>]>;
 }
 
 let TargetGuard = "sve2p1" in {

diff  --git a/clang/include/clang/Basic/arm_sve_sme_incl.td 
b/clang/include/clang/Basic/arm_sve_sme_incl.td
index c3a6dc4e4d44abe..3a7a5b51b25801e 100644
--- a/clang/include/clang/Basic/arm_sve_sme_incl.td
+++ b/clang/include/clang/Basic/arm_sve_sme_incl.td
@@ -99,6 +99,7 @@
 // O: svfloat16_t
 // M: svfloat32_t
 // N: svfloat64_t
+// $: svbfloat16_t
 
 // J: Prefetch type (sv_prfop)
 

diff  --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmlsl.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
new file mode 100644
index 000..2955d4554da004e
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmlsl.c
@@ -0,0 +1,85 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p 
mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p 
mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s 
| opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x 
c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 
-target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+// BFMLSLB
+
+
+// CHECK-LABEL: @test_bfmlslb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.bfmlslb( [[ZDA:%.*]],  [[ZN:%.*]],  [[ZM:%.*]])
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: 
@_Z12test_bfmlslbu13__SVFloat32_tu14__SVBFloat16_tu14__SVBFloat16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.bfmlslb( [[ZDA:%.*]],  [[ZN:%.*]],  [[ZM:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svfloat32_t test_bfmlslb(svfloat32_t zda, svbfloat16_t

[clang] b9dae2f - [Clang][SVE2.1] Add builtins for svrevd

2023-10-20 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2023-10-20T08:35:13Z
New Revision: b9dae2fa22d3dd4d5c454c2b167428b027d7bc12

URL: 
https://github.com/llvm/llvm-project/commit/b9dae2fa22d3dd4d5c454c2b167428b027d7bc12
DIFF: 
https://github.com/llvm/llvm-project/commit/b9dae2fa22d3dd4d5c454c2b167428b027d7bc12.diff

LOG: [Clang][SVE2.1] Add builtins for svrevd

As described in: https://github.com/ARM-software/acle/pull/257

Patch by: Rosie Sumpter 

Reviewed By: dtemirbulatov

Differential Revision: https://reviews.llvm.org/D151709

Added: 
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c

Modified: 
clang/include/clang/Basic/arm_sve.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index a1585443e5fd229..b5baafedd139602 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1977,4 +1977,6 @@ def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", 
MergeNone, "", [], []>;
 def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "", [], []>;
 
 def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_cntp_{d}", [IsOverloadNone], [ImmCheck<1, ImmCheck2_4_Mul2>]>;
+
+defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
 }

diff  --git a/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c 
b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c
new file mode 100644
index 000..14d515e6d12bb70
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_revd.c
@@ -0,0 +1,390 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \
+// RUN:   -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu \
+// RUN:   -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \
+// RUN:   -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | 
FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu \
+// RUN:   -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | 
FileCheck %s -check-prefix=CPP-CHECK
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
+#endif
+
+// CHECK-LABEL: @test_svrevd_s8_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv16i8( zeroinitializer,  [[PG:%.*]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z16test_svrevd_s8_zu10__SVBool_tu10__SVInt8_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv16i8( zeroinitializer,  [[PG:%.*]],  [[OP:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svint8_t test_svrevd_s8_z(svbool_t pg, svint8_t op) {
+  return SVE_ACLE_FUNC(svrevd, _s8, _z, )(pg, op);
+}
+
+// CHECK-LABEL: @test_svrevd_s16_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8i16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z17test_svrevd_s16_zu10__SVBool_tu11__SVInt16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv8i16( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP1]]
+//
+svint16_t test_svrevd_s16_z(svbool_t pg, svint16_t op) {
+  return SVE_ACLE_FUNC(svrevd, _s16, _z, )(pg, op);
+}
+
+// CHECK-LABEL: @test_svrevd_s32_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv4i32( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CHECK-NEXT:ret  [[TMP1]]
+//
+// CPP-CHECK-LABEL: @_Z17test_svrevd_s32_zu10__SVBool_tu11__SVInt32_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.revd.nxv4i32( zeroinitializer,  [[TMP0]],  [[OP:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP1]]
+//
+svint32_t test_svrevd_s32_z(svbool_t pg, svint32_t op) {
+  return SVE_ACLE_FUNC(svrevd, _s32, _z, )(pg, op);
+}
+
+// CHECK-LABEL: @test_svrevd_s64_z(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%

[clang] 257b297 - [flang][driver] Add the new flang compiler and frontend drivers

2020-09-11 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2020-09-11T10:55:54+01:00
New Revision: 257b29715bb27b7d9f6c3c40c481b6a4af0b37e5

URL: 
https://github.com/llvm/llvm-project/commit/257b29715bb27b7d9f6c3c40c481b6a4af0b37e5
DIFF: 
https://github.com/llvm/llvm-project/commit/257b29715bb27b7d9f6c3c40c481b6a4af0b37e5.diff

LOG: [flang][driver] Add the new flang compiler and frontend drivers

Summary:

This is the first patch implementing the new Flang driver as outlined in [1],
[2] & [3]. It creates Flang driver (`flang-new`) and Flang frontend driver
(`flang-new -fc1`). These will be renamed as `flang` and `flang -fc1` once the
current Flang throwaway driver, `flang`, can be replaced with `flang-new`.

Currently only 2 options are supported: `-help` and `--version`.

`flang-new` is implemented in terms of libclangDriver, defaulting the driver
mode to `FlangMode` (added to libclangDriver in [4]). This ensures that the
driver runs in Flang mode regardless of the name of the binary inferred from
argv[0].

The design of the new Flang compiler and frontend drivers is inspired by it
counterparts in Clang [3]. Currently, the new Flang compiler and frontend
drivers re-use Clang libraries: clangBasic, clangDriver and clangFrontend.

To identify Flang options, this patch adds FlangOption/FC1Option enums.
Driver::printHelp is updated so that `flang-new` prints only Flang options.
The new Flang driver is disabled by default. To enable it, set
`-DBUILD_FLANG_NEW_DRIVER=ON` when configuring CMake and add clang to
`LLVM_ENABLE_PROJECTS` (e.g. -DLLVM_ENABLE_PROJECTS=“clang;flang;mlir”).

[1] “RFC: new Flang driver - next steps”
http://lists.llvm.org/pipermail/flang-dev/2020-July/000470.html
[2] “RFC: Adding a fortran mode to the clang driver for flang”
http://lists.llvm.org/pipermail/cfe-dev/2019-June/062669.html
[3] “RFC: refactoring libclangDriver/libclangFrontend to share with Flang”
http://lists.llvm.org/pipermail/cfe-dev/2020-July/066393.html
[4] https://reviews.llvm.org/rG6bf55804924d5a1d902925ad080b1a2b57c5c75c

co-authored-by: Andrzej Warzynski 

Reviewed By: richard.barton.arm, sameeranjoshi

Differential Revision: https://reviews.llvm.org/D86089

Added: 
flang/include/flang/Frontend/CompilerInstance.h
flang/include/flang/Frontend/CompilerInvocation.h
flang/include/flang/Frontend/FrontendOptions.h
flang/include/flang/FrontendTool/Utils.h
flang/lib/Frontend/CMakeLists.txt
flang/lib/Frontend/CompilerInstance.cpp
flang/lib/Frontend/CompilerInvocation.cpp
flang/lib/Frontend/FrontendOptions.cpp
flang/lib/FrontendTool/CMakeLists.txt
flang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
flang/test/Flang-Driver/driver-error-cc1.c
flang/test/Flang-Driver/driver-error-cc1.cpp
flang/test/Flang-Driver/driver-help.f90
flang/test/Flang-Driver/driver-version.f90
flang/test/Flang-Driver/emit-obj.f90
flang/test/Flang-Driver/missing-input.f90
flang/tools/flang-driver/CMakeLists.txt
flang/tools/flang-driver/driver.cpp
flang/tools/flang-driver/fc1_main.cpp
flang/unittests/Frontend/CMakeLists.txt
flang/unittests/Frontend/CompilerInstanceTest.cpp

Modified: 
clang/include/clang/Driver/Driver.h
clang/include/clang/Driver/Options.h
clang/include/clang/Driver/Options.td
clang/lib/Driver/Driver.cpp
clang/lib/Driver/ToolChains/Flang.cpp
clang/lib/Frontend/CreateInvocationFromCommandLine.cpp
clang/lib/Tooling/Tooling.cpp
clang/test/Driver/flang/flang.f90
clang/test/Driver/flang/flang_ucase.F90
clang/test/Driver/flang/multiple-inputs-mixed.f90
clang/test/Driver/flang/multiple-inputs.f90
clang/unittests/Driver/SanitizerArgsTest.cpp
clang/unittests/Driver/ToolChainTest.cpp
flang/CMakeLists.txt
flang/README.md
flang/lib/CMakeLists.txt
flang/test/CMakeLists.txt
flang/test/lit.cfg.py
flang/test/lit.site.cfg.py.in
flang/tools/CMakeLists.txt
flang/unittests/CMakeLists.txt
llvm/include/llvm/Option/OptTable.h

Removed: 




diff  --git a/clang/include/clang/Driver/Driver.h 
b/clang/include/clang/Driver/Driver.h
index dc18f1314f81..7a476199ff7f 100644
--- a/clang/include/clang/Driver/Driver.h
+++ b/clang/include/clang/Driver/Driver.h
@@ -301,7 +301,7 @@ class Driver {
   StringRef CustomResourceDir = "");
 
   Driver(StringRef ClangExecutable, StringRef TargetTriple,
- DiagnosticsEngine &Diags,
+ DiagnosticsEngine &Diags, std::string Title = "clang LLVM compiler",
  IntrusiveRefCntPtr VFS = nullptr);
 
   /// @name Accessors

diff  --git a/clang/include/clang/Driver/Options.h 
b/clang/include/clang/Driver/Options.h
index 9831efda4e58..06dd3652be94 100644
--- a/clang/include/clang/Driver/Options.h
+++ b/clang/include/clang/Driver/Options.h
@@ -34,7 +34,9 @@ enum ClangFlags {
   CC1AsOption = (1 << 11),
   NoDriverOption = (1 << 12),
   LinkOption = (1 << 13),
-

[clang] 33c554d - [clang][driver]Add quotation mark in test/fortran.f95 to avoid false positive

2020-08-19 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2020-08-19T17:54:32+01:00
New Revision: 33c554d8444a5ce1fb85def04de8c0ebfec643b9

URL: 
https://github.com/llvm/llvm-project/commit/33c554d8444a5ce1fb85def04de8c0ebfec643b9
DIFF: 
https://github.com/llvm/llvm-project/commit/33c554d8444a5ce1fb85def04de8c0ebfec643b9.diff

LOG: [clang][driver]Add quotation mark in test/fortran.f95  to avoid false 
positive

If a folder's name, where the test fortran.f95 is running, has cc1 the test
fails because of  CHECK-ASM-NOT: cc1.
The solution used in this patch is to add quotation mark around cc1 and cc1as
because the driver returns these flags with quotation marks ("")

Reviewed By: DavidTruby, echristo

Differential Revision: https://reviews.llvm.org/D86132

Added: 


Modified: 
clang/test/Driver/fortran.f95

Removed: 




diff  --git a/clang/test/Driver/fortran.f95 b/clang/test/Driver/fortran.f95
index 03ff99f9fbfb..db3ff2da17e8 100644
--- a/clang/test/Driver/fortran.f95
+++ b/clang/test/Driver/fortran.f95
@@ -6,14 +6,14 @@
 ! CHECK-OBJECT: gcc
 ! CHECK-OBJECT: "-c"
 ! CHECK-OBJECT: "-x" "f95"
-! CHECK-OBJECT-NOT: cc1as
+! CHECK-OBJECT-NOT: "-cc1as"
 
 ! RUN: %clang -target x86_64-unknown-linux-gnu -integrated-as -S %s -### 2>&1 \
 ! RUN:   | FileCheck --check-prefix=CHECK-ASM %s
 ! CHECK-ASM: gcc
 ! CHECK-ASM: "-S"
 ! CHECK-ASM: "-x" "f95"
-! CHECK-ASM-NOT: cc1
+! CHECK-ASM-NOT: "-cc1"
 
 ! RUN: %clang -Wall -target x86_64-unknown-linux-gnu -integrated-as %s -o %t 
-### 2>&1 | FileCheck --check-prefix=CHECK-WARN %s
 ! CHECK-WARN: gcc



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[clang] 145e44b - [SVE]Fix implicit TypeSize casts in EmitCheckValue

2020-10-15 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2020-10-15T13:25:46+01:00
New Revision: 145e44bb18853bc9beeac0e64fffd9e6895e71f9

URL: 
https://github.com/llvm/llvm-project/commit/145e44bb18853bc9beeac0e64fffd9e6895e71f9
DIFF: 
https://github.com/llvm/llvm-project/commit/145e44bb18853bc9beeac0e64fffd9e6895e71f9.diff

LOG: [SVE]Fix implicit TypeSize casts in EmitCheckValue

Using TypeSize::getFixedSize() instead of relying upon the implicit
TypeSize->uint64_cast as the type is always fixed width.

Differential Revision: https://reviews.llvm.org/D89313

Added: 


Modified: 
clang/lib/CodeGen/CGExpr.cpp

Removed: 




diff  --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 2f54097d9209..ed2c8e6a71f1 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -2996,7 +2996,7 @@ llvm::Value *CodeGenFunction::EmitCheckValue(llvm::Value 
*V) {
   // Floating-point types which fit into intptr_t are bitcast to integers
   // and then passed directly (after zero-extension, if necessary).
   if (V->getType()->isFloatingPointTy()) {
-unsigned Bits = V->getType()->getPrimitiveSizeInBits();
+unsigned Bits = V->getType()->getPrimitiveSizeInBits().getFixedSize();
 if (Bits <= TargetTy->getIntegerBitWidth())
   V = Builder.CreateBitCast(V, llvm::Type::getIntNTy(getLLVMContext(),
  Bits));



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[clang] e8d9ee9 - [SVE][CodeGen]Use getFixedSize() function for TypeSize comparison in clang

2020-10-16 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2020-10-16T10:56:39+01:00
New Revision: e8d9ee9c7cfe46d9b552111a27d866fce0498b0a

URL: 
https://github.com/llvm/llvm-project/commit/e8d9ee9c7cfe46d9b552111a27d866fce0498b0a
DIFF: 
https://github.com/llvm/llvm-project/commit/e8d9ee9c7cfe46d9b552111a27d866fce0498b0a.diff

LOG: [SVE][CodeGen]Use getFixedSize() function for TypeSize comparison in clang

This patch makes sure that the instance of TypeSize comparison operator
is done with a fixed type size.

Differential Revision: https://reviews.llvm.org/D89312

Added: 


Modified: 
clang/lib/CodeGen/CGBuiltin.cpp

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 90bfeefc9970..183a1a097709 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -5608,8 +5608,8 @@ static Value *EmitCommonNeonSISDBuiltinExpr(
 
   Value *Result = CGF.EmitNeonCall(F, Ops, s);
   llvm::Type *ResultType = CGF.ConvertType(E->getType());
-  if (ResultType->getPrimitiveSizeInBits() <
-  Result->getType()->getPrimitiveSizeInBits())
+  if (ResultType->getPrimitiveSizeInBits().getFixedSize() <
+  Result->getType()->getPrimitiveSizeInBits().getFixedSize())
 return CGF.Builder.CreateExtractElement(Result, C0);
 
   return CGF.Builder.CreateBitCast(Result, ResultType, s);



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[clang] 2186b01 - [Driver][AArch64]Add driver support for neoverse-512tvb target

2021-10-28 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2021-10-28T09:08:40+01:00
New Revision: 2186b011e96669b447896c103c10a07dd3aa6203

URL: 
https://github.com/llvm/llvm-project/commit/2186b011e96669b447896c103c10a07dd3aa6203
DIFF: 
https://github.com/llvm/llvm-project/commit/2186b011e96669b447896c103c10a07dd3aa6203.diff

LOG: [Driver][AArch64]Add driver support for neoverse-512tvb target

The support for  neoverse-512tvb mirrors the same option available in GCC[1].
There is no functional effect for this option yet.
This patch ensures the driver accepts "-mcpu=neoverse-512tvb", and enough
plumbing is in place to allow the new option to be used in the future.

[1]https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html

Differential Revision: https://reviews.llvm.org/D112406

Added: 


Modified: 
clang/test/Driver/aarch64-cpus.c
clang/test/Misc/target-invalid-cpu-note.c
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/test/CodeGen/AArch64/cpus.ll
llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
llvm/unittests/Support/TargetParserTest.cpp

Removed: 




diff  --git a/clang/test/Driver/aarch64-cpus.c 
b/clang/test/Driver/aarch64-cpus.c
index 55cef730ebe52..4f049c79dac1b 100644
--- a/clang/test/Driver/aarch64-cpus.c
+++ b/clang/test/Driver/aarch64-cpus.c
@@ -192,6 +192,9 @@
 // RUN: %clang -target aarch64 -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=NEOVERSE-N2 %s
 // NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-n2"
 
+// RUN: %clang -target aarch64 -mcpu=neoverse-512tvb -### -c %s 2>&1 | 
FileCheck -check-prefix=NEOVERSE-512TVB %s
+// NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" 
"neoverse-512tvb"
+
 // RUN: %clang -target aarch64 -mcpu=cortex-r82  -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEXR82 %s
 // CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
 

diff  --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 800910b749838..efdc92263e7e9 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
 
 // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix AARCH64
 // AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, 
cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, 
cortex-a78, cortex-a78c, cortex-r82, cortex-x1, neoverse-e1, neoverse-n1, 
neoverse-n2, neoverse-v1, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, 
apple-a11, apple-a12, apple-a13, apple-a14, apple-m1, apple-s4, apple-s5, 
exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, 
thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, 
carmel{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, 
cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, 
cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, 
cortex-a78, cortex-a78c, cortex-r82, cortex-x1, neoverse-e1, neoverse-n1, 
neoverse-n2, neoverse-512tvb, neoverse-v1, cyclone, apple-a7, apple-a8, 
apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-m1, 
apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, 
thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, 
tsv110, a64fx, carmel{{$}}
 
 // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
-// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, 
cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, 
cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, 
cortex-a77, cortex-a78, cortex-a78c, cortex-r82, cortex-x1, neoverse-e1, 
neoverse-n1, neoverse-n2, neoverse-v1, cyclone, apple-a7, apple-a8, apple-a9, 
apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-m1, apple-s4, 
apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, 
thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, 
carmel{{$}}
+// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, 
cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, 
cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, 
cortex-a77, cortex-a78, cortex-a78c, cortex-r82, cortex-x1, neoverse-e1, 
neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, cyclone, apple-a7, 
apple-a8, a

[clang] 81d8fa5 - [Clang][SVE2.1] Add svcntp prototype

2023-10-17 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2023-10-17T14:14:45Z
New Revision: 81d8fa5a1d01e1cd00865966957dba74b5e8613f

URL: 
https://github.com/llvm/llvm-project/commit/81d8fa5a1d01e1cd00865966957dba74b5e8613f
DIFF: 
https://github.com/llvm/llvm-project/commit/81d8fa5a1d01e1cd00865966957dba74b5e8613f.diff

LOG: [Clang][SVE2.1] Add svcntp prototype

As described in: https://github.com/ARM-software/acle/pull/257

Patch by : David Sherwood 

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D150961

Added: 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_cntp.c
clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp

Modified: 
clang/include/clang/Basic/arm_sve.td
clang/include/clang/Basic/arm_sve_sme_incl.td
clang/lib/Sema/SemaChecking.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 894a0a1296b0473..07dc8cdece990be 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1867,4 +1867,6 @@ def SVPTRUE_COUNT  : SInst<"svptrue_{d}", "}v", 
"QcQsQiQl", MergeNone, "aarch64_
 let TargetGuard = "sve2p1" in {
 def SVSCLAMP : SInst<"svclamp[_{d}]", "", "csil", MergeNone, 
"aarch64_sve_sclamp", [], []>;
 def SVUCLAMP : SInst<"svclamp[_{d}]", "", "UcUsUiUl", MergeNone, 
"aarch64_sve_uclamp", [], []>;
+def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_cntp_{d}", [IsOverloadNone], [ImmCheck<1, ImmCheck2_4_Mul2>]>;
+
 }

diff  --git a/clang/include/clang/Basic/arm_sve_sme_incl.td 
b/clang/include/clang/Basic/arm_sve_sme_incl.td
index 74c9b9266771b02..da15f1fb31847e6 100644
--- a/clang/include/clang/Basic/arm_sve_sme_incl.td
+++ b/clang/include/clang/Basic/arm_sve_sme_incl.td
@@ -246,6 +246,7 @@ def ImmCheck0_3 : ImmCheckType<15>; // 0..3
 def ImmCheck0_0 : ImmCheckType<16>; // 0..0
 def ImmCheck0_15: ImmCheckType<17>; // 0..15
 def ImmCheck0_255   : ImmCheckType<18>; // 0..255
+def ImmCheck2_4_Mul2: ImmCheckType<19>; // 2, 4
 
 class ImmCheck {
   int Arg = arg;

diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index e121da8fac6d9b4..31b7e6cc8b8922a 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3120,6 +3120,11 @@ bool Sema::CheckSVEBuiltinFunctionCall(unsigned 
BuiltinID, CallExpr *TheCall) {
   if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 255))
 HasError = true;
   break;
+case SVETypeFlags::ImmCheck2_4_Mul2:
+  if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 2, 4) ||
+  SemaBuiltinConstantArgMultiple(TheCall, ArgNum, 2))
+HasError = true;
+  break;
 }
   }
 

diff  --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_cntp.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_cntp.c
new file mode 100644
index 000..18973a6467450a2
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_cntp.c
@@ -0,0 +1,119 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -o /dev/null %s
+
+#include 
+
+// CHECK-LABEL: @test_svcntp_c8_vlx2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 
@llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z19test_svcntp_c8_vlx2u11__SVCount_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call i64 
@llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 2)
+// CPP-CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c8_vlx2(svcount_t pnn) {
+  return svcntp_c8(pnn, 2);
+}
+
+// CHECK-LABEL: @test_svcntp_c8_vlx4(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 
@llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z19test_svcntp_c8_vlx4u11__SVCount_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call i64 
@llvm.aarch64.sve.cntp.c8(target("aarch64.svcount") [[PNN:%.*]], i32 4)
+// CPP-CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntp_c8_vlx4(svcount_t pnn) {
+  return svcntp_c8(pnn, 4);
+}
+
+// CHECK-LABEL: @test_svcntp_c16_vlx2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 
@llvm.aarch64.sve.cntp.c16(target("a

[clang] 7cad5a9 - [Clang][SVE2.1] Add svpext builtins

2023-10-17 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2023-10-17T16:15:22Z
New Revision: 7cad5a9eb48e44a10121044d0342ccfbdd8df672

URL: 
https://github.com/llvm/llvm-project/commit/7cad5a9eb48e44a10121044d0342ccfbdd8df672
DIFF: 
https://github.com/llvm/llvm-project/commit/7cad5a9eb48e44a10121044d0342ccfbdd8df672.diff

LOG: [Clang][SVE2.1] Add svpext builtins

As described in: https://github.com/ARM-software/acle/pull/257

Reviewed By: hassnaa-arm

Differential Revision: https://reviews.llvm.org/D151081

Added: 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c

Modified: 
clang/include/clang/Basic/arm_sve.td
clang/include/clang/Basic/arm_sve_sme_incl.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/CodeGen/CodeGenFunction.h
clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_imm.cpp
clang/utils/TableGen/SveEmitter.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 07dc8cdece990be..f54e65ef7119cc1 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1862,11 +1862,13 @@ def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", 
"UcUsUiUl", MergeNone, "aarch64_sv
 let TargetGuard = "sve2p1" in {
 def SVFCLAMP   : SInst<"svclamp[_{d}]", "", "hfd", MergeNone, 
"aarch64_sve_fclamp", [], []>;
 def SVPTRUE_COUNT  : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone, 
"aarch64_sve_ptrue_{d}", [IsOverloadNone], []>;
+
+def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_pext", [], [ImmCheck<1, ImmCheck0_3>]>;
+def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl", 
MergeNone, "aarch64_sve_pext_x2", [], [ImmCheck<1, ImmCheck0_1>]>;
 }
 
 let TargetGuard = "sve2p1" in {
 def SVSCLAMP : SInst<"svclamp[_{d}]", "", "csil", MergeNone, 
"aarch64_sve_sclamp", [], []>;
 def SVUCLAMP : SInst<"svclamp[_{d}]", "", "UcUsUiUl", MergeNone, 
"aarch64_sve_uclamp", [], []>;
 def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_cntp_{d}", [IsOverloadNone], [ImmCheck<1, ImmCheck2_4_Mul2>]>;
-
 }

diff  --git a/clang/include/clang/Basic/arm_sve_sme_incl.td 
b/clang/include/clang/Basic/arm_sve_sme_incl.td
index da15f1fb31847e6..c3a6dc4e4d44abe 100644
--- a/clang/include/clang/Basic/arm_sve_sme_incl.td
+++ b/clang/include/clang/Basic/arm_sve_sme_incl.td
@@ -61,7 +61,8 @@
 // ---
 // prototype: return (arg, arg, ...)
 //
-// 2,3,4: array of default vectors
+// 2,3,4: array of vectors
+// .: indicator for multi-vector modifier that will follow (e.g. 2.x)
 // v: void
 // x: vector of signed integers
 // u: vector of unsigned integers

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index f1c199e165fca8c..116af1435fe6e40 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -9853,6 +9853,41 @@ Value *CodeGenFunction::EmitSVETupleCreate(const 
SVETypeFlags &TypeFlags,
   return Call;
 }
 
+Value *CodeGenFunction::FormSVEBuiltinResult(Value *Call) {
+  // Multi-vector results should be broken up into a single (wide) result
+  // vector.
+  auto *StructTy = dyn_cast(Call->getType());
+  if (!StructTy)
+return Call;
+
+  auto *VTy = dyn_cast(StructTy->getTypeAtIndex(0U));
+  if (!VTy)
+return Call;
+  unsigned N = StructTy->getNumElements();
+
+  // We may need to emit a cast to a svbool_t
+  bool IsPredTy = VTy->getElementType()->isIntegerTy(1);
+  unsigned MinElts = IsPredTy ? 16 : VTy->getMinNumElements();
+
+  ScalableVectorType *WideVTy =
+  ScalableVectorType::get(VTy->getElementType(), MinElts * N);
+  Value *Ret = llvm::PoisonValue::get(WideVTy);
+  for (unsigned I = 0; I < N; ++I) {
+Value *SRet = Builder.CreateExtractValue(Call, I);
+assert(SRet->getType() == VTy && "Unexpected type for result value");
+Value *Idx = ConstantInt::get(CGM.Int64Ty, I * MinElts);
+
+if (IsPredTy)
+  SRet = EmitSVEPredicateCast(
+  SRet, ScalableVectorType::get(Builder.getInt1Ty(), 16));
+
+Ret = Builder.CreateInsertVector(WideVTy, Ret, SRet, Idx);
+  }
+  Call = Ret;
+
+  return Call;
+}
+
 Value *CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
   const CallExpr *E) {
   // Find out if any arguments are required to be integer constant expressions.
@@ -9966,7 +10001,7 @@ Value 
*CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
   if (PredTy->getScalarType()->isIntegerTy(1))
 Call = EmitSVEPredicateCast(Call, cast(Ty));
 
-return Call;
+return FormSVEBuiltinResult(Call);
   }
 
   switch (BuiltinID) {

diff  --git a/clang/lib/CodeGen/CodeGenFunction.h 
b/clang/lib/CodeGen/CodeGenFunction.h
index 6bc6d244bee2080..e82115e2d706cf1 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -4292,6 +4292,11 @@ class CodeGen

[clang] ba1f31f - [CLANG][AArch64][SVE2.1] Add UCLAMP/SCLAMP/FCLAMP function prototypes

2023-05-19 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2023-05-19T15:36:22Z
New Revision: ba1f31fb066af2769634ebb2e23d683d8d409f37

URL: 
https://github.com/llvm/llvm-project/commit/ba1f31fb066af2769634ebb2e23d683d8d409f37
DIFF: 
https://github.com/llvm/llvm-project/commit/ba1f31fb066af2769634ebb2e23d683d8d409f37.diff

LOG: [CLANG][AArch64][SVE2.1] Add UCLAMP/SCLAMP/FCLAMP function prototypes

Submitting this patch in the name of: David Sherwood 

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D150863

Added: 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fclamp.c
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_sclamp.c
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_uclamp.c

Modified: 
clang/include/clang/Basic/arm_sve.td
llvm/include/llvm/TargetParser/AArch64TargetParser.h

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 8584e1741dac2..bd2db7ef17be8 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2104,3 +2104,12 @@ def SVBEXT_N : SInst<"svbext[_n_{d}]", "dda", 
"UcUsUiUl", MergeNone, "aarch64_sv
 def SVBGRP   : SInst<"svbgrp[_{d}]",   "ddd", "UcUsUiUl", MergeNone, 
"aarch64_sve_bgrp_x">;
 def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", "UcUsUiUl", MergeNone, 
"aarch64_sve_bgrp_x">;
 }
+
+let TargetGuard = "sve2p1" in {
+def SVFCLAMP   : SInst<"svclamp[_{d}]", "", "hfd", MergeNone, 
"aarch64_sve_fclamp", [], []>;
+}
+
+let TargetGuard = "sve2p1" in {
+def SVSCLAMP : SInst<"svclamp[_{d}]", "", "csil", MergeNone, 
"aarch64_sve_sclamp", [], []>;
+def SVUCLAMP : SInst<"svclamp[_{d}]", "", "UcUsUiUl", MergeNone, 
"aarch64_sve_uclamp", [], []>;
+}

diff  --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fclamp.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fclamp.c
new file mode 100644
index 0..e7085c94b255c
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fclamp.c
@@ -0,0 +1,64 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 \
+// RUN:   -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p 
mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 \
+// RUN:   -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p 
mem2reg,instcombine,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 \
+// RUN:   -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p 
mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 \
+// RUN:   -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p 
mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 \
+// RUN:   -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
+#endif
+
+// CHECK-LABEL: @test_svclamp_f16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.fclamp.nxv8f16( [[OP1:%.*]],  [[OP2:%.*]],  [[OP3:%.*]])
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: 
@_Z16test_svclamp_f16u13__SVFloat16_tu13__SVFloat16_tu13__SVFloat16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.fclamp.nxv8f16( [[OP1:%.*]],  [[OP2:%.*]],  [[OP3:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svfloat16_t test_svclamp_f16(svfloat16_t op1, svfloat16_t op2, svfloat16_t 
op3) {
+  return SVE_ACLE_FUNC(svclamp, _f16, , )(op1, op2, op3);
+}
+
+// CHECK-LABEL: @test_svclamp_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.fclamp.nxv4f32( [[OP1:%.*]],  [[OP2:%.*]],  [[OP3:%.*]])
+// CHECK-NEXT:ret  [[TMP0]]
+//
+// CPP-CHECK-LABEL: 
@_Z16test_svclamp_f32u13__SVFloat32_tu13__SVFloat32_tu13__SVFloat32_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.fclamp.nxv4f32( [[OP1:%.*]],  [[OP2:%.*]],  [[OP3:%.*]])
+// CPP-CHECK-NEXT:ret  [[TMP0]]
+//
+svfloat32_t test_svclamp_f32(svfloat32_t op1, svfloat32_t op2, svfloat32_t 
op3) {
+  return SVE_ACLE_FUNC(svclamp, _f32, , )(op1, op2, op3);
+}
+
+// CHECK-LABEL: @test_svclamp_f64(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.fclamp.nxv

[clang] fc8acb5 - [Clang][SVE2.1] Add clang support for builtins using svcount_t

2023-05-31 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2023-05-31T15:57:44Z
New Revision: fc8acb563ae019735e646f9964b254cab1efd529

URL: 
https://github.com/llvm/llvm-project/commit/fc8acb563ae019735e646f9964b254cab1efd529
DIFF: 
https://github.com/llvm/llvm-project/commit/fc8acb563ae019735e646f9964b254cab1efd529.diff

LOG: [Clang][SVE2.1] Add clang support for builtins  using svcount_t

In this patch it is used for the prototype:
  * svptrue_c8 (and _c16/_c32/_c64)

 As described in: https://github.com/ARM-software/acle/pull/257

Patch by: Sander de Smalen 

Reviewed By: sdesmalen, david-arm

Differential Revision: https://reviews.llvm.org/D150953

Added: 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c

Modified: 
clang/include/clang/Basic/Builtins.def
clang/include/clang/Basic/arm_sve.td
clang/include/clang/Basic/arm_sve_sme_incl.td
clang/lib/AST/ASTContext.cpp
clang/utils/TableGen/SveEmitter.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/Builtins.def 
b/clang/include/clang/Basic/Builtins.def
index e8cd200257c2a..c8f955a1f4b28 100644
--- a/clang/include/clang/Basic/Builtins.def
+++ b/clang/include/clang/Basic/Builtins.def
@@ -39,6 +39,8 @@
 //  A -> "reference" to __builtin_va_list
 //  V -> Vector, followed by the number of elements and the base type.
 //  q -> Scalable vector, followed by the number of elements and the base type.
+//  Q -> target builtin type, followed by a character to distinguish the 
builtin type
+//Qa -> AArch64 svcount_t builtin type.
 //  E -> ext_vector, followed by the number of elements and the base type.
 //  X -> _Complex, followed by the base type.
 //  Y -> ptr
diff _t

diff  --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index aa7c0553671a5..894a0a1296b04 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1861,6 +1861,7 @@ def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", "UcUsUiUl", 
MergeNone, "aarch64_sv
 
 let TargetGuard = "sve2p1" in {
 def SVFCLAMP   : SInst<"svclamp[_{d}]", "", "hfd", MergeNone, 
"aarch64_sve_fclamp", [], []>;
+def SVPTRUE_COUNT  : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone, 
"aarch64_sve_ptrue_{d}", [IsOverloadNone], []>;
 }
 
 let TargetGuard = "sve2p1" in {

diff  --git a/clang/include/clang/Basic/arm_sve_sme_incl.td 
b/clang/include/clang/Basic/arm_sve_sme_incl.td
index f68140d386473..6b1541d334a25 100644
--- a/clang/include/clang/Basic/arm_sve_sme_incl.td
+++ b/clang/include/clang/Basic/arm_sve_sme_incl.td
@@ -55,6 +55,7 @@
 // --
 // P: boolean
 // U: unsigned
+// Q: svcount
 
 // Prototype modifiers
 // ---
@@ -124,6 +125,9 @@
 // Y: const pointer to uint32_t
 // Z: const pointer to uint64_t
 
+// Prototype modifiers added for SVE2p1
+// }: svcount_t
+
 class MergeType {
   int Value = val;
   string Suffix = suffix;

diff  --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 7758c30725a3c..ef3242e81e65f 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -11455,6 +11455,17 @@ static QualType DecodeTypeFromStr(const char *&Str, 
const ASTContext &Context,
 Type = Context.getScalableVectorType(ElementType, NumElements);
 break;
   }
+  case 'Q': {
+switch (*Str++) {
+case 'a': {
+  Type = Context.SveCountTy;
+  break;
+}
+default:
+  llvm_unreachable("Unexpected target builtin type");
+}
+break;
+  }
   case 'V': {
 char *End;
 unsigned NumElements = strtoul(Str, &End, 10);

diff  --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c
new file mode 100644
index 0..c8fd843500560
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c
@@ -0,0 +1,62 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+
+#include 
+
+// CHECK-LABEL: @test_svptrue_c8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call target("aarch64.svcount") 
@llvm.aarch64.sve.ptrue.c8()
+// CHECK-NEXT:ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z15test_svptrue_c8v(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call target("aarch64.svcount") 
@llvm.aarch64.sve.ptrue.c8()
+// CPP-CHECK-NEXT:ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svptrue_c8(void) {
+  return svptrue_c8();
+}
+
+// CHECK-LABEL: @test_svptrue_c16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call targe

[clang] 5bb8ead - [AArch64][NFC] Rename AEK_SMEF64 and AEK_SMEI64 feature flags

2023-02-15 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2023-02-15T11:39:00Z
New Revision: 5bb8ead4e9dc4a03bddae1f7d3419e97eac37426

URL: 
https://github.com/llvm/llvm-project/commit/5bb8ead4e9dc4a03bddae1f7d3419e97eac37426
DIFF: 
https://github.com/llvm/llvm-project/commit/5bb8ead4e9dc4a03bddae1f7d3419e97eac37426.diff

LOG: [AArch64][NFC] Rename  AEK_SMEF64 and AEK_SMEI64 feature flags

Update feature flag names from:
AEK_SMEF64  to AEK_SMEF64F64
and
AEK_SMEI64 to AEK_SMEI16I64
These feature flags had their name changed in this previous patch
 https://reviews.llvm.org/D135974

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D143989

Added: 


Modified: 
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h

Removed: 




diff  --git a/clang/lib/Basic/Targets/AArch64.cpp 
b/clang/lib/Basic/Targets/AArch64.cpp
index a0eae3177e3ab..9b67becff9e75 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -663,8 +663,8 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const 
{
   .Case("sve2-sha3", FPU & SveMode && HasSVE2SHA3)
   .Case("sve2-sm4", FPU & SveMode && HasSVE2SM4)
   .Case("sme", HasSME)
-  .Case("sme-f64f64", HasSMEF64)
-  .Case("sme-i16i64", HasSMEI64)
+  .Case("sme-f64f64", HasSMEF64F64)
+  .Case("sme-i16i64", HasSMEI16I64)
   .Cases("memtag", "memtag2", HasMTE)
   .Case("sb", HasSB)
   .Case("predres", HasPredRes)
@@ -780,12 +780,12 @@ bool 
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
 }
 if (Feature == "+sme-f64f64") {
   HasSME = true;
-  HasSMEF64 = true;
+  HasSMEF64F64 = true;
   HasBFloat16 = true;
 }
 if (Feature == "+sme-i16i64") {
   HasSME = true;
-  HasSMEI64 = true;
+  HasSMEI16I64 = true;
   HasBFloat16 = true;
 }
 if (Feature == "+sb")

diff  --git a/clang/lib/Basic/Targets/AArch64.h 
b/clang/lib/Basic/Targets/AArch64.h
index 23cabc5885104..46bfb70a0d953 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -64,8 +64,8 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public 
TargetInfo {
   bool HasCCDP = false;
   bool HasFRInt3264 = false;
   bool HasSME = false;
-  bool HasSMEF64 = false;
-  bool HasSMEI64 = false;
+  bool HasSMEF64F64 = false;
+  bool HasSMEI16I64 = false;
   bool HasSB = false;
   bool HasPredRes = false;
   bool HasSSBS = false;



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[clang] 177cbd1 - [Clang][SME2.1] Add REQUIRES: aarch64-registered-target to test

2024-06-26 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2024-06-26T12:53:34Z
New Revision: 177cbd16663a2ca36d0d7145c3b62f2d756f8f7f

URL: 
https://github.com/llvm/llvm-project/commit/177cbd16663a2ca36d0d7145c3b62f2d756f8f7f
DIFF: 
https://github.com/llvm/llvm-project/commit/177cbd16663a2ca36d0d7145c3b62f2d756f8f7f.diff

LOG: [Clang][SME2.1] Add  REQUIRES: aarch64-registered-target to test

PR#88710 is failing because the test file needs
REQUIRES: aarch64-registered-target

Added: 


Modified: 
clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c

Removed: 




diff  --git a/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c 
b/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c
index 3f5337c2b23d2..d0c7230ade761 100644
--- a/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c
+++ b/clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c
@@ -1,5 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 4
- //RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2p1 
-target-feature +sme -target-feature +bf16 -disable-O0-optnone -Werror -Wall 
-emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
+// REQUIRES: aarch64-registered-target
+//RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2p1 
-target-feature +sme -target-feature +bf16 -disable-O0-optnone -Werror -Wall 
-emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2p1 
-target-feature +sme -target-feature +bf16 -disable-O0-optnone -Werror -Wall 
-emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | 
FileCheck %s -check-prefix=CPP-CHECK
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2p1 
-target-feature +sme -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall 
-o /dev/null %s
 



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[clang] b3703fa - [AArch64]Update test aarch64-debug-types.c

2024-10-25 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2024-10-25T13:30:16Z
New Revision: b3703fa50485cf90b04105e6a223ccdd1e29c9af

URL: 
https://github.com/llvm/llvm-project/commit/b3703fa50485cf90b04105e6a223ccdd1e29c9af
DIFF: 
https://github.com/llvm/llvm-project/commit/b3703fa50485cf90b04105e6a223ccdd1e29c9af.diff

LOG: [AArch64]Update test aarch64-debug-types.c

This patch fix the failing tests by adding
REQUIRES: aarch64-registered-target

This tests was failing in non aarch64 cpu.
The test was introduced by:
 [CLANG][AArch64] Add the  modal 8 bit floating-point scalar type (#97277)

Added: 


Modified: 
clang/test/CodeGen/aarch64-debug-types.c

Removed: 




diff  --git a/clang/test/CodeGen/aarch64-debug-types.c 
b/clang/test/CodeGen/aarch64-debug-types.c
index c109610023ed49..f1ab74c5c31bdb 100644
--- a/clang/test/CodeGen/aarch64-debug-types.c
+++ b/clang/test/CodeGen/aarch64-debug-types.c
@@ -1,5 +1,8 @@
 // RUN:  %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon  
-target-feature +fp8 \
 // RUN:  -emit-llvm -o - %s -debug-info-kind=limited 2>&1 | FileCheck %s
+
+// REQUIRES: aarch64-registered-target
+
 #include
 
 void test_locals(void) {



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[clang] 02f46d7 - Revert "[Clang][LLVM][AArch64] Add intrinsic for LUTI4 SME2 instruction (#97755)"

2024-09-25 Thread Caroline Concatto via cfe-commits 

Author: Caroline Concatto
Date: 2024-09-25T09:25:28Z
New Revision: 02f46d7fb8b2a2434b1597fb96f65d7f82f3aeac

URL: 
https://github.com/llvm/llvm-project/commit/02f46d7fb8b2a2434b1597fb96f65d7f82f3aeac
DIFF: 
https://github.com/llvm/llvm-project/commit/02f46d7fb8b2a2434b1597fb96f65d7f82f3aeac.diff

LOG: Revert "[Clang][LLVM][AArch64] Add intrinsic for LUTI4 SME2 instruction 
(#97755)"

Going to revert to Fix test in clang as it is failing

This reverts commit 445d8b2d10b2bb9a5f50e3fe0671045acd309a04.

Added: 


Modified: 
clang/include/clang/Basic/arm_sme.td
clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_imm.cpp
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

Removed: 
clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_zt.c
llvm/test/CodeGen/AArch64/sme2-intrinsics-write-zt.ll



diff  --git a/clang/include/clang/Basic/arm_sme.td 
b/clang/include/clang/Basic/arm_sme.td
index 9c9f31f3884069..ae6b55e98827ff 100644
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -817,9 +817,4 @@ multiclass ZAReadzArray{
 
 defm SVREADZ_VG2 :  ZAReadzArray<"2">;
 defm SVREADZ_VG4 :  ZAReadzArray<"4">;
-
-let SMETargetGuard = "sme2,sme-lutv2" in {
-  def SVLUTI4_ZT_X4 : SInst<"svluti4_zt_{d}_x4", "4i2.u", "cUc", MergeNone, 
"aarch64_sme_luti4_zt_x4", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>]>;
-}
-
 } // let SVETargetGuard = InvalidMode

diff  --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_zt.c 
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_zt.c
deleted file mode 100644
index 47f36a8b000c07..00
--- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_zt.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 5
-// RUN: %clang_cc1  -triple aarch64-none-linux-gnu -target-feature +bf16 
-target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -O2 
-Werror -Wall -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -x c++  -triple aarch64-none-linux-gnu -target-feature 
+bf16 -target-feature +sme -target-feature +sme2 -target-feature  +sme-lutv2  
-O2 -Werror -Wall -emit-llvm -o - %s | FileCheck %s -check-prefix CHECK-CXX
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS   -triple aarch64-none-linux-gnu 
-target-feature +bf16 -target-feature +sme -target-feature +sme2 
-target-feature  +sme-lutv2  -O2 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -x c++  -triple 
aarch64-none-linux-gnu -target-feature +bf16 -target-feature +sme 
-target-feature +sme2 -target-feature +sme-lutv2 -O2 -Werror -Wall -emit-llvm 
-o - %s | FileCheck %s -check-prefix CHECK-CXX
-
-// RUN: %clang_cc1  -triple aarch64-none-linux-gnu -target-feature +bf16 
-target-feature +sme -target-feature +sme2 -target-feature +sme-lutv2 -O2 -S 
-Werror -Wall -o /dev/null %s
-// REQUIRES: aarch64-registered-target
-
-#include 
-
-// CHECK-LABEL: define dso_local  @test_luti4_zt_u8_x4(
-// CHECK-SAME:  [[OP:%.*]]) local_unnamed_addr 
#[[ATTR0:[0-9]+]] {
-// CHECK-NEXT:  [[ENTRY:.*:]]
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.extract.nxv16i8.nxv32i8( [[OP]], i64 0)
-// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.vector.extract.nxv16i8.nxv32i8( [[OP]], i64 16)
-// CHECK-NEXT:[[TMP2:%.*]] = tail call { , , ,  } 
@llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0,  [[TMP0]], 
 [[TMP1]])
-// CHECK-NEXT:[[TMP3:%.*]] = extractvalue { , , ,  } [[TMP2]], 0
-// CHECK-NEXT:[[TMP4:%.*]] = tail call  
@llvm.vector.insert.nxv64i8.nxv16i8( poison,  [[TMP3]], i64 0)
-// CHECK-NEXT:[[TMP5:%.*]] = extractvalue { , , ,  } [[TMP2]], 1
-// CHECK-NEXT:[[TMP6:%.*]] = tail call  
@llvm.vector.insert.nxv64i8.nxv16i8( [[TMP4]],  [[TMP5]], i64 16)
-// CHECK-NEXT:[[TMP7:%.*]] = extractvalue { , , ,  } [[TMP2]], 2
-// CHECK-NEXT:[[TMP8:%.*]] = tail call  
@llvm.vector.insert.nxv64i8.nxv16i8( [[TMP6]],  [[TMP7]], i64 32)
-// CHECK-NEXT:[[TMP9:%.*]] = extractvalue { , , ,  } [[TMP2]], 3
-// CHECK-NEXT:[[TMP10:%.*]] = tail call  
@llvm.vector.insert.nxv64i8.nxv16i8( [[TMP8]],  [[TMP9]], i64 48)
-// CHECK-NEXT:ret  [[TMP10]]
-//
-// CHECK-CXX-LABEL: define dso_local  
@_Z19test_luti4_zt_u8_x411svuint8x2_t(
-// CHECK-CXX-SAME:  [[OP:%.*]]) local_unnamed_addr 
#[[ATTR0:[0-9]+]] {
-// CHECK-CXX-NEXT:  [[ENTRY:.*:]]
-// CHECK-CXX-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.extract.nxv16i8.nxv32i8( [[OP]], i64 0)
-// CHECK-CXX-NEXT:[[TMP1:%.*]] = tail call  
@llvm.vector.extract.nxv16i8.nxv32i8( [[OP]], i64 16)
-// CHECK-CXX-NEXT:[[TMP2:%.*]] = tail call { , , ,  } 
@llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0,  [[TMP0]], 
 [[TMP1]])
-// CHECK-CXX-NEXT:[[TMP3:%.*]] = extractvalue { , 
, ,  } [[TMP2]], 0
-/