from:"Bryan Chan via cfe\-commits"

r345344 - [AArch64] Implement FP16FML intrinsics

2018-10-26 Thread Bryan Chan via cfe-commits

Author: bryanpkc
Date: Thu Oct 25 16:47:00 2018
New Revision: 345344

URL: http://llvm.org/viewvc/llvm-project?rev=345344&view=rev
Log:
[AArch64] Implement FP16FML intrinsics

Generate the FP16FML intrinsics into arm_neon.h (AArch64 only for now).
Add two new type modifiers to NeonEmitter to handle the new prototypes.
Define __ARM_FEATURE_FP16FML when +fp16fml is enabled and guard the
intrinsics with the macro in arm_neon.h.

Based on a patch by Gao Yiling.

Differential Revision: https://reviews.llvm.org/D53633


Added:
cfe/trunk/test/CodeGen/aarch64-neon-fp16fml.c
Modified:
cfe/trunk/include/clang/Basic/arm_neon.td
cfe/trunk/include/clang/Basic/arm_neon_incl.td
cfe/trunk/lib/Basic/Targets/AArch64.cpp
cfe/trunk/lib/Basic/Targets/AArch64.h
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/test/Preprocessor/aarch64-target-features.c
cfe/trunk/utils/TableGen/NeonEmitter.cpp

Modified: cfe/trunk/include/clang/Basic/arm_neon.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=345344&r1=345343&r2=345344&view=diff
==
--- cfe/trunk/include/clang/Basic/arm_neon.td (original)
+++ cfe/trunk/include/clang/Basic/arm_neon.td Thu Oct 25 16:47:00 2018
@@ -206,6 +206,15 @@ def OP_DOT_LNQ
 : Op<(call "vdot", $p0, $p1,
   (bitcast $p1, (splat(bitcast "uint32x4_t", $p2), $p3)))>;
 
+def OP_FMLAL_LN : Op<(call "vfmlal_low", $p0, $p1,
+   (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
+def OP_FMLSL_LN : Op<(call "vfmlsl_low", $p0, $p1,
+   (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
+def OP_FMLAL_LN_Hi  : Op<(call "vfmlal_high", $p0, $p1,
+   (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
+def OP_FMLSL_LN_Hi  : Op<(call "vfmlsl_high", $p0, $p1,
+   (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
+
 
//===--===//
 // Instructions
 
//===--===//
@@ -1640,3 +1649,21 @@ let ArchGuard = "defined(__ARM_FEATURE_D
   // Variants indexing into a 128-bit vector are A64 only.
   def UDOT_LANEQ : SOpInst<"vdot_laneq", "dd89i", "iUiQiQUi", OP_DOT_LNQ>;
 }
+
+// v8.2-A FP16 fused multiply-add long instructions.
+let ArchGuard = "defined(__ARM_FEATURE_FP16FML) && defined(__aarch64__)" in {
+  def VFMLAL_LOW  : SInst<"vfmlal_low", "ffHH", "UiQUi">;
+  def VFMLSL_LOW  : SInst<"vfmlsl_low", "ffHH", "UiQUi">;
+  def VFMLAL_HIGH : SInst<"vfmlal_high", "ffHH", "UiQUi">;
+  def VFMLSL_HIGH : SInst<"vfmlsl_high", "ffHH", "UiQUi">;
+
+  def VFMLAL_LANE_LOW  : SOpInst<"vfmlal_lane_low", "ffH0i", "UiQUi", 
OP_FMLAL_LN>;
+  def VFMLSL_LANE_LOW  : SOpInst<"vfmlsl_lane_low", "ffH0i", "UiQUi", 
OP_FMLSL_LN>;
+  def VFMLAL_LANE_HIGH : SOpInst<"vfmlal_lane_high", "ffH0i", "UiQUi", 
OP_FMLAL_LN_Hi>;
+  def VFMLSL_LANE_HIGH : SOpInst<"vfmlsl_lane_high", "ffH0i", "UiQUi", 
OP_FMLSL_LN_Hi>;
+
+  def VFMLAL_LANEQ_LOW  : SOpInst<"vfmlal_laneq_low", "ffH1i", "UiQUi", 
OP_FMLAL_LN>;
+  def VFMLSL_LANEQ_LOW  : SOpInst<"vfmlsl_laneq_low", "ffH1i", "UiQUi", 
OP_FMLSL_LN>;
+  def VFMLAL_LANEQ_HIGH : SOpInst<"vfmlal_laneq_high", "ffH1i", "UiQUi", 
OP_FMLAL_LN_Hi>;
+  def VFMLSL_LANEQ_HIGH : SOpInst<"vfmlsl_laneq_high", "ffH1i", "UiQUi", 
OP_FMLSL_LN_Hi>;
+}

Modified: cfe/trunk/include/clang/Basic/arm_neon_incl.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon_incl.td?rev=345344&r1=345343&r2=345344&view=diff
==
--- cfe/trunk/include/clang/Basic/arm_neon_incl.td (original)
+++ cfe/trunk/include/clang/Basic/arm_neon_incl.td Thu Oct 25 16:47:00 2018
@@ -96,6 +96,11 @@ def bitcast;
 // example: (dup $p1) -> "(uint32x2_t) {__p1, __p1}" (assuming the base type
 //  is uint32x2_t).
 def dup;
+// dup_typed - Take a vector and a scalar argument, and create a new vector of
+// the same type by duplicating the scalar value into all lanes.
+// example: (dup_typed $p1, $p2) -> "(float16x4_t) {__p2, __p2, __p2, __p2}"
+//  (assuming __p1 is float16x4_t, and __p2 is a compatible scalar).
+def dup_typed;
 // splat - Take a vector and a lane index, and return a vector of the same type
 // containing repeated instances of the source vector at the lane 
index.
 // example: (splat $p0, $p1) ->
@@ -229,6 +234,8 @@ def OP_UNAVAILABLE : Operation {
 // f: float (int args)
 // F: double (int args)
 // H: half (int args)
+// 0: half (int args), ignore 'Q' size modifier.
+// 1: half (int args), force 'Q' size modifier.
 // d: default
 // g: default, ignore 'Q' size modifier.
 // j: default, force 'Q' size modifier.

Modified: cfe/trunk/lib/Basic/Targets/AArch64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AArch64.cpp?rev=345344

[llvm] [clang] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

2023-12-18 Thread Bryan Chan via cfe-commits


https://github.com/bryanpkc approved this pull request.

This looks reasonable to me, but I'll wait for other reviewers to look at this. 
Please rebase on main and make sure the CI workflows succeed.

https://github.com/llvm/llvm-project/pull/75516
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[llvm] [clang] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

2023-12-20 Thread Bryan Chan via cfe-commits



@@ -81,6 +81,15 @@ static bool DecodeAArch64Features(const Driver &D, StringRef 
text,
 else
   return false;
 
+// +jsconv and +complxnum implies +neon and +fp-armv8

bryanpkc wrote:

@momchil-velikov Thank you for your answer. It is strange that the wording in 
the Arm ARM is so strict. It is well understood that an Armv8.*x*-A processor 
can implement any feature from the next *.x* generation (see [Understanding the 
Armv8.x 
extensions](https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/Understanding%20the%20Armv8.x%20extensions.pdf)).

The rationale for this change is to enable the use of these ISA features on an 
Armv8.2-a processor (such as TSV110 and other similar chips), by making the 
command-line options available.

https://github.com/llvm/llvm-project/pull/75516
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[clang] [llvm] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

2024-01-12 Thread Bryan Chan via cfe-commits


bryanpkc wrote:

@davemgreen @ilinpv @DavidSpickett @hassnaaHamdi Gentle ping.

https://github.com/llvm/llvm-project/pull/75516
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[llvm] [clang] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

2024-01-14 Thread Bryan Chan via cfe-commits


https://github.com/bryanpkc updated 
https://github.com/llvm/llvm-project/pull/75516

>From a39cd3fba9cd8fb6757bfd297d57f6ab98b36405 Mon Sep 17 00:00:00 2001
From: Qi Hu 
Date: Thu, 14 Dec 2023 13:35:52 -0500
Subject: [PATCH] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110

We define AEK_JSCVT and AEK_FCMA for CPU features FEAT_JSCVT and FEAT_FCMA
respectively, and add them to the CpuInfo of tsv110.
---
 clang/test/CodeGen/aarch64-targetattr.c   |  12 +-
 .../Preprocessor/aarch64-target-features.c|  10 +-
 .../llvm/TargetParser/AArch64TargetParser.h   |  11 +-
 llvm/lib/Target/AArch64/AArch64.td|   3 +-
 .../TargetParser/TargetParserTest.cpp | 106 ++
 5 files changed, 82 insertions(+), 60 deletions(-)

diff --git a/clang/test/CodeGen/aarch64-targetattr.c 
b/clang/test/CodeGen/aarch64-targetattr.c
index 5f557532a4b4a7..02da18264da0a3 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -97,19 +97,19 @@ void minusarch() {}
 // CHECK: attributes #0 = { {{.*}} 
"target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
 // CHECK: attributes #1 = { {{.*}} 
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
 }
 // CHECK: attributes #2 = { {{.*}} 
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
 }
-// CHECK: attributes #3 = { {{.*}} 
"target-features"="+bf16,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+lse,+neon,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 }
-// CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" 
"target-features"="+bf16,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+lse,+mte,+neon,+pauth,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm"
 }
+// CHECK: attributes #3 = { {{.*}} 
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 }
+// CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" 
"target-features"="+bf16,+complxnum,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm"
 }
 // CHECK: attributes #5 = { {{.*}} "tune-cpu"="cortex-a710" }
 // CHECK: attributes #6 = { {{.*}} "target-cpu"="generic" }
 // CHECK: attributes #7 = { {{.*}} "tune-cpu"="generic" }
 // CHECK: attributes #8 = { {{.*}} "target-cpu"="neoverse-n1" 
"target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs"
 "tune-cpu"="cortex-a710" }
 // CHECK: attributes #9 = { {{.*}} 
"target-features"="+fp-armv8,+fullfp16,+neon,+sve" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" 
"target-features"="+aes,+bf16,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+lse,+neon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2"
 }
-// CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" 
"target-features"="+aes,+bf16,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+lse,+neon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,-sve"
 }
+// CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" 
"target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2"
 }
+// CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" 
"target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,-sve"
 }
 // CHECK: attributes #12 = { {{.*}} 
"target-features"="+fp-armv8,+fullfp16,+neon,+sve" }
 // CHECK: attributes #13 = { {{.*}} 
"target-features"="+fp-armv8,+fullfp16,+neon,+sve,-sve2" }
 // CHECK: attributes #14 = { {{.*}} "target-features"="+fullfp16" }
-// CHECK: attributes #15 = { {{.*}} "target-cpu"="neoverse-n1" 
"target-features"="+aes,+bf16,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 "tune-cpu"="cortex-a710" }
-// CHECK: attributes #16 = { {{.*}} "branch-target-enforcement"="true" 
"guarded-control-stack"="true" {{.*}} 
"target-features"="+aes,+bf16,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 "tune-cpu"="cortex-a710" }
+// CHECK: attributes #15 = { {{.*}} "target-cpu"="neoverse-n1" 
"target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 "tune-cpu"="cortex-a710" }
+// CHECK: attributes #16 = { {{.*}} "branch-target-enforcement"="true" 
"guarded-control-stack"="true" {{.*}} 
"target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+n

[clang] [llvm] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

2024-01-15 Thread Bryan Chan via cfe-commits


https://github.com/bryanpkc updated 
https://github.com/llvm/llvm-project/pull/75516

>From 581947adad14826e023731d9b7aa6e4161b46949 Mon Sep 17 00:00:00 2001
From: Qi Hu 
Date: Thu, 14 Dec 2023 13:35:52 -0500
Subject: [PATCH] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110

We define AEK_JSCVT and AEK_FCMA for CPU features FEAT_JSCVT and FEAT_FCMA
respectively, and add them to the CpuInfo of tsv110.
---
 clang/test/CodeGen/aarch64-targetattr.c   |  12 +-
 .../Preprocessor/aarch64-target-features.c|  10 +-
 .../llvm/TargetParser/AArch64TargetParser.h   |  11 +-
 llvm/lib/Target/AArch64/AArch64.td|   3 +-
 .../TargetParser/TargetParserTest.cpp | 106 ++
 5 files changed, 82 insertions(+), 60 deletions(-)

diff --git a/clang/test/CodeGen/aarch64-targetattr.c 
b/clang/test/CodeGen/aarch64-targetattr.c
index 5f557532a4b4a7..02da18264da0a3 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -97,19 +97,19 @@ void minusarch() {}
 // CHECK: attributes #0 = { {{.*}} 
"target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
 // CHECK: attributes #1 = { {{.*}} 
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a"
 }
 // CHECK: attributes #2 = { {{.*}} 
"target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a"
 }
-// CHECK: attributes #3 = { {{.*}} 
"target-features"="+bf16,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+lse,+neon,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 }
-// CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" 
"target-features"="+bf16,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+lse,+mte,+neon,+pauth,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm"
 }
+// CHECK: attributes #3 = { {{.*}} 
"target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 }
+// CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" 
"target-features"="+bf16,+complxnum,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm"
 }
 // CHECK: attributes #5 = { {{.*}} "tune-cpu"="cortex-a710" }
 // CHECK: attributes #6 = { {{.*}} "target-cpu"="generic" }
 // CHECK: attributes #7 = { {{.*}} "tune-cpu"="generic" }
 // CHECK: attributes #8 = { {{.*}} "target-cpu"="neoverse-n1" 
"target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs"
 "tune-cpu"="cortex-a710" }
 // CHECK: attributes #9 = { {{.*}} 
"target-features"="+fp-armv8,+fullfp16,+neon,+sve" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" 
"target-features"="+aes,+bf16,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+lse,+neon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2"
 }
-// CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" 
"target-features"="+aes,+bf16,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+lse,+neon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,-sve"
 }
+// CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" 
"target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2"
 }
+// CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" 
"target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,-sve"
 }
 // CHECK: attributes #12 = { {{.*}} 
"target-features"="+fp-armv8,+fullfp16,+neon,+sve" }
 // CHECK: attributes #13 = { {{.*}} 
"target-features"="+fp-armv8,+fullfp16,+neon,+sve,-sve2" }
 // CHECK: attributes #14 = { {{.*}} "target-features"="+fullfp16" }
-// CHECK: attributes #15 = { {{.*}} "target-cpu"="neoverse-n1" 
"target-features"="+aes,+bf16,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 "tune-cpu"="cortex-a710" }
-// CHECK: attributes #16 = { {{.*}} "branch-target-enforcement"="true" 
"guarded-control-stack"="true" {{.*}} 
"target-features"="+aes,+bf16,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 "tune-cpu"="cortex-a710" }
+// CHECK: attributes #15 = { {{.*}} "target-cpu"="neoverse-n1" 
"target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a"
 "tune-cpu"="cortex-a710" }
+// CHECK: attributes #16 = { {{.*}} "branch-target-enforcement"="true" 
"guarded-control-stack"="true" {{.*}} 
"target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+n

[llvm] [clang] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

2024-01-15 Thread Bryan Chan via cfe-commits


https://github.com/bryanpkc closed 
https://github.com/llvm/llvm-project/pull/75516
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[clang] 275ab24 - [Clang][test] Avoid FileCheck error when matching `-cc1`

2023-01-20 Thread Bryan Chan via cfe-commits


Author: hezuoqiang
Date: 2023-01-20T23:36:09-05:00
New Revision: 275ab246ee811507a2b1d2e42b2d655a25c8df6c

URL: 
https://github.com/llvm/llvm-project/commit/275ab246ee811507a2b1d2e42b2d655a25c8df6c
DIFF: 
https://github.com/llvm/llvm-project/commit/275ab246ee811507a2b1d2e42b2d655a25c8df6c.diff

LOG: [Clang][test] Avoid FileCheck error when matching `-cc1`

FileCheck patterns consisting of only `-cc1` on a line by itself often
cause mismatches, e.g. with version strings formed from commit hashes
such as "clang-cc1514432c58". They should be changed to contain more
context and match more precisely.

Differential Revision: https://reviews.llvm.org/D141886

Added: 


Modified: 
clang/test/Driver/modules-ts.cpp
clang/test/Driver/modules.cpp
clang/test/OpenMP/driver.c

Removed: 




diff  --git a/clang/test/Driver/modules-ts.cpp 
b/clang/test/Driver/modules-ts.cpp
index eb2f535f5e445..30bb9d7a5bf35 100644
--- a/clang/test/Driver/modules-ts.cpp
+++ b/clang/test/Driver/modules-ts.cpp
@@ -23,8 +23,7 @@
 // RUN: %clang -fmodules-ts -fmodule-file=%t.pcm -fintegrated-as -Dexport= %s 
-c -o %t.o -v 2>&1 | FileCheck %s --check-prefix=CHECK-USE
 //
 // CHECK-USE:  warning: the '-fmodules-ts' flag is deprecated and it will be 
removed in Clang 17; use '-std=c++20' or higher to use standard C++ modules 
instead [-Wdeprecated-module-ts]
-// CHECK-USE: -cc1
-// CHECK-USE-SAME: -emit-obj
+// CHECK-USE: -cc1 {{.*}} -emit-obj
 // CHECK-USE-SAME: -fmodule-file={{.*}}.pcm
 // CHECK-USE-SAME: -o {{.*}}.o{{"?}} {{.*}}-x c++
 // CHECK-USE-SAME: modules-ts.cpp

diff  --git a/clang/test/Driver/modules.cpp b/clang/test/Driver/modules.cpp
index d54ce393fe345..e63c946770d37 100644
--- a/clang/test/Driver/modules.cpp
+++ b/clang/test/Driver/modules.cpp
@@ -24,8 +24,7 @@
 // RUN: %clang -std=c++2a -fmodule-file=%t/module.pcm -Dexport= %s -S -o 
%t/module.o -v 2>&1 | FileCheck %s --check-prefix=CHECK-USE
 // RUN: %clang -std=c++20 -fmodule-file=%t/module.pcm -Dexport= %s -S -o 
%t/module.o -v 2>&1 | FileCheck %s --check-prefix=CHECK-USE
 //
-// CHECK-USE: -cc1
-// CHECK-USE-SAME: {{-emit-obj|-S}}
+// CHECK-USE: -cc1 {{.*}} {{-emit-obj|-S}}
 // CHECK-USE-SAME: -fmodule-file={{.*}}.pcm
 // CHECK-USE-SAME: -o {{.*}}.{{o|s}}{{"?}} {{.*}}-x c++
 // CHECK-USE-SAME: modules.cpp

diff  --git a/clang/test/OpenMP/driver.c b/clang/test/OpenMP/driver.c
index 2533ec7e05b60..568160d93a222 100644
--- a/clang/test/OpenMP/driver.c
+++ b/clang/test/OpenMP/driver.c
@@ -3,12 +3,12 @@
 //
 // RUN: %clang %s -### -o %t.o 2>&1 -fopenmp=libomp | FileCheck 
--check-prefix=CHECK-DEFAULT %s
 
-// CHECK-DEFAULT: -cc1
+// CHECK-DEFAULT: "-cc1"
 // CHECK-DEFAULT-NOT: -fnoopenmp-use-tls
 //
 // RUN: %clang %s -### -o %t.o 2>&1 -fopenmp=libomp -fnoopenmp-use-tls | 
FileCheck --check-prefix=CHECK-NO-TLS %s
 
-// CHECK-NO-TLS: -cc1
+// CHECK-NO-TLS: "-cc1"
 // CHECK-NO-TLS-SAME: -fnoopenmp-use-tls
 //
 // RUN: %clang %s -c -E -dM -fopenmp=libomp | FileCheck 
--check-prefix=CHECK-DEFAULT-VERSION %s



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[clang] 578b0bd - [Clang][AArch64][SME] Add ZA zeroing intrinsics

2023-07-20 Thread Bryan Chan via cfe-commits


Author: Bryan Chan
Date: 2023-07-20T06:06:34-04:00
New Revision: 578b0bd4e621304a1ce367e87a53e59e404dec9b

URL: 
https://github.com/llvm/llvm-project/commit/578b0bd4e621304a1ce367e87a53e59e404dec9b
DIFF: 
https://github.com/llvm/llvm-project/commit/578b0bd4e621304a1ce367e87a53e59e404dec9b.diff

LOG: [Clang][AArch64][SME] Add ZA zeroing intrinsics

 This patch adds support for the following SME ACLE intrinsics (as defined
 in https://arm-software.github.io/acle/main/acle.html):

   - svzero_mask_za
   - svzero_za

Co-authored-by: Sagar Kulkarni 

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D134677

Added: 
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c

Modified: 
clang/include/clang/Basic/arm_sme.td
clang/include/clang/Basic/arm_sve_sme_incl.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/CodeGen/CodeGenFunction.h
clang/lib/Sema/SemaChecking.cpp
clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sme.td 
b/clang/include/clang/Basic/arm_sme.td
index 4f82615bfb9d95..7c1daf46adfb13 100644
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -114,3 +114,14 @@ defm SVWRITE_ZA16 : ZAWrite<"za16", "sUshb", 
"aarch64_sme_write", [ImmCheck<0, I
 defm SVWRITE_ZA32 : ZAWrite<"za32", "iUif", "aarch64_sme_write", [ImmCheck<0, 
ImmCheck0_3>, ImmCheck<2, ImmCheck0_3>]>;
 defm SVWRITE_ZA64 : ZAWrite<"za64", "lUld", "aarch64_sme_write", [ImmCheck<0, 
ImmCheck0_7>, ImmCheck<2, ImmCheck0_1>]>;
 defm SVWRITE_ZA128 : ZAWrite<"za128", "csilUcUsUiUlhbfd", 
"aarch64_sme_writeq", [ImmCheck<0, ImmCheck0_15>, ImmCheck<2, ImmCheck0_0>]>;
+
+
+// SME - Zero
+
+let TargetGuard = "sme" in {
+  def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone, 
"aarch64_sme_zero",
+ [IsOverloadNone, IsStreamingCompatible, 
IsSharedZA],
+ [ImmCheck<0, ImmCheck0_255>]>;
+  def SVZERO_ZA  : SInst<"svzero_za", "v", "", MergeNone, 
"aarch64_sme_zero",
+ [IsOverloadNone, IsStreamingCompatible, 
IsSharedZA]>;
+}

diff  --git a/clang/include/clang/Basic/arm_sve_sme_incl.td 
b/clang/include/clang/Basic/arm_sve_sme_incl.td
index e664b8b3e3f63a..74c9b9266771b0 100644
--- a/clang/include/clang/Basic/arm_sve_sme_incl.td
+++ b/clang/include/clang/Basic/arm_sve_sme_incl.td
@@ -245,6 +245,7 @@ def ImmCheck0_2 : ImmCheckType<14>; // 0..2
 def ImmCheck0_3 : ImmCheckType<15>; // 0..3
 def ImmCheck0_0 : ImmCheckType<16>; // 0..0
 def ImmCheck0_15: ImmCheckType<17>; // 0..15
+def ImmCheck0_255   : ImmCheckType<18>; // 0..255
 
 class ImmCheck {
   int Arg = arg;

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 9d9ad162c6f5d3..599539e1fa4343 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -9495,6 +9495,16 @@ Value *CodeGenFunction::EmitSMEReadWrite(SVETypeFlags 
TypeFlags,
   return Builder.CreateCall(F, Ops);
 }
 
+Value *CodeGenFunction::EmitSMEZero(SVETypeFlags TypeFlags,
+SmallVectorImpl &Ops,
+unsigned IntID) {
+  // svzero_za() intrinsic zeros the entire za tile and has no paramters.
+  if (Ops.size() == 0)
+Ops.push_back(llvm::ConstantInt::get(Int32Ty, 255));
+  Function *F = CGM.getIntrinsic(IntID, {});
+  return Builder.CreateCall(F, Ops);
+}
+
 // Limit the usage of scalable llvm IR generated by the ACLE by using the
 // sve dup.x intrinsic instead of IRBuilder::CreateVectorSplat.
 Value *CodeGenFunction::EmitSVEDupX(Value *Scalar, llvm::Type *Ty) {
@@ -9955,6 +9965,9 @@ Value 
*CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
 return EmitSMELd1St1(TypeFlags, Ops, Builtin->LLVMIntrinsic);
   else if (TypeFlags.isReadZA() || TypeFlags.isWriteZA())
 return EmitSMEReadWrite(TypeFlags, Ops, Builtin->LLVMIntrinsic);
+  else if (BuiltinID == SME::BI__builtin_sme_svzero_mask_za ||
+   BuiltinID == SME::BI__builtin_sme_svzero_za)
+return EmitSMEZero(TypeFlags, Ops, Builtin->LLVMIntrinsic);
 
   /// Should not happen
   return nullptr;

diff  --git a/clang/lib/CodeGen/CodeGenFunction.h 
b/clang/lib/CodeGen/CodeGenFunction.h
index 246050b341d67b..8292163ab3365c 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -4283,6 +4283,9 @@ class CodeGenFunction : public CodeGenTypeCache {
   llvm::Value *EmitSMEReadWrite(SVETypeFlags TypeFlags,
 llvm::SmallVectorImpl &Ops,
 unsigned IntID);
+  llvm::Value *EmitSMEZero(SVETypeFlags TypeFlags,
+   llvm::SmallVectorImpl &Ops,
+

[clang] f225898 - [Clang][AArch64][SME] Add intrinsics for ZA array load/store (LDR/STR)

2023-07-20 Thread Bryan Chan via cfe-commits


Author: Bryan Chan
Date: 2023-07-20T06:06:35-04:00
New Revision: f225898a7c6105aa34e64f9c7dbfed7ce3443331

URL: 
https://github.com/llvm/llvm-project/commit/f225898a7c6105aa34e64f9c7dbfed7ce3443331
DIFF: 
https://github.com/llvm/llvm-project/commit/f225898a7c6105aa34e64f9c7dbfed7ce3443331.diff

LOG: [Clang][AArch64][SME] Add intrinsics for ZA array load/store (LDR/STR)

This patch adds support for the following SME ACLE intrinsics (as defined
in https://arm-software.github.io/acle/main/acle.html):

  - svldr_vnum_za
  - svstr_vnum_za

Co-authored-by: Sagar Kulkarni 

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D134678

Added: 
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c

Modified: 
clang/include/clang/Basic/arm_sme.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/CodeGen/CodeGenFunction.h
clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sme.td 
b/clang/include/clang/Basic/arm_sme.td
index 7c1daf46adfb13..945f212963d6c9 100644
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -44,6 +44,11 @@ defm SVLD1_ZA32 : ZALoad<"za32", "i", "aarch64_sme_ld1w", 
[ImmCheck<0, ImmCheck0
 defm SVLD1_ZA64 : ZALoad<"za64", "l", "aarch64_sme_ld1d", [ImmCheck<0, 
ImmCheck0_7>, ImmCheck<2, ImmCheck0_1>]>;
 defm SVLD1_ZA128 : ZALoad<"za128", "q", "aarch64_sme_ld1q", [ImmCheck<0, 
ImmCheck0_15>, ImmCheck<2, ImmCheck0_0>]>;
 
+def SVLDR_VNUM_ZA : MInst<"svldr_vnum_za", "vmiQ", "",
+  [IsOverloadNone, IsStreamingCompatible, IsSharedZA],
+  MemEltTyDefault, "aarch64_sme_ldr",
+  [ImmCheck<1, ImmCheck0_15>]>;
+
 

 // Stores
 
@@ -73,6 +78,11 @@ defm SVST1_ZA32 : ZAStore<"za32", "i", "aarch64_sme_st1w", 
[ImmCheck<0, ImmCheck
 defm SVST1_ZA64 : ZAStore<"za64", "l", "aarch64_sme_st1d", [ImmCheck<0, 
ImmCheck0_7>, ImmCheck<2, ImmCheck0_1>]>;
 defm SVST1_ZA128 : ZAStore<"za128", "q", "aarch64_sme_st1q", [ImmCheck<0, 
ImmCheck0_15>, ImmCheck<2, ImmCheck0_0>]>;
 
+def SVSTR_VNUM_ZA : MInst<"svstr_vnum_za", "vmi%", "",
+  [IsOverloadNone, IsStreamingCompatible, IsSharedZA, 
IsPreservesZA],
+  MemEltTyDefault, "aarch64_sme_str",
+  [ImmCheck<1, ImmCheck0_15>]>;
+
 

 // Read horizontal/vertical ZA slices
 

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 599539e1fa4343..416c220351267a 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -9505,6 +9505,22 @@ Value *CodeGenFunction::EmitSMEZero(SVETypeFlags 
TypeFlags,
   return Builder.CreateCall(F, Ops);
 }
 
+Value *CodeGenFunction::EmitSMELdrStr(SVETypeFlags TypeFlags,
+  SmallVectorImpl &Ops,
+  unsigned IntID) {
+  Function *Vscale = CGM.getIntrinsic(Intrinsic::vscale, Int64Ty);
+  llvm::Value *VscaleCall = Builder.CreateCall(Vscale, {}, "vscale");
+  llvm::Value *MulVL = Builder.CreateMul(
+  VscaleCall,
+  Builder.getInt64(16 * cast(Ops[1])->getZExtValue()),
+  "mulvl");
+  Ops[2] = Builder.CreateGEP(Int8Ty, Ops[2], MulVL);
+  Ops[0] = EmitTileslice(Ops[1], Ops[0]);
+  Ops.erase(&Ops[1]);
+  Function *F = CGM.getIntrinsic(IntID, {});
+  return Builder.CreateCall(F, Ops);
+}
+
 // Limit the usage of scalable llvm IR generated by the ACLE by using the
 // sve dup.x intrinsic instead of IRBuilder::CreateVectorSplat.
 Value *CodeGenFunction::EmitSVEDupX(Value *Scalar, llvm::Type *Ty) {
@@ -9968,6 +9984,9 @@ Value 
*CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
   else if (BuiltinID == SME::BI__builtin_sme_svzero_mask_za ||
BuiltinID == SME::BI__builtin_sme_svzero_za)
 return EmitSMEZero(TypeFlags, Ops, Builtin->LLVMIntrinsic);
+  else if (BuiltinID == SME::BI__builtin_sme_svldr_vnum_za ||
+   BuiltinID == SME::BI__builtin_sme_svstr_vnum_za)
+return EmitSMELdrStr(TypeFlags, Ops, Builtin->LLVMIntrinsic);
 
   /// Should not happen
   return nullptr;

diff  --git a/clang/lib/CodeGen/CodeGenFunction.h 
b/clang/lib/CodeGen/CodeGenFunction.h
index 8292163ab3365c..409f48a04906e2 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -4286,6 +4286,9 @@ class CodeGenFunction : public CodeGenTypeCache {
   llvm::Value *EmitSMEZero(SVETypeFlags TypeFlags,
llvm::SmallVectorImpl &Ops,
unsigned IntID);
+  llvm::Value *EmitSMELdrStr(SVETypeFlags TypeFlags,
+ llvm::SmallVectorImpl &Ops,
+

[clang] 15d16a7 - [Clang][AArch64][SME] Add intrinsics for reading streaming vector length

2023-07-20 Thread Bryan Chan via cfe-commits


Author: Bryan Chan
Date: 2023-07-20T06:06:35-04:00
New Revision: 15d16a79a01f4fac718556809ecd00914dd7d7a2

URL: 
https://github.com/llvm/llvm-project/commit/15d16a79a01f4fac718556809ecd00914dd7d7a2
DIFF: 
https://github.com/llvm/llvm-project/commit/15d16a79a01f4fac718556809ecd00914dd7d7a2.diff

LOG: [Clang][AArch64][SME] Add intrinsics for reading streaming vector length

This patch adds support for the following SME ACLE intrinsics (as defined
in https://arm-software.github.io/acle/main/acle.html):

  - svcntsb
  - svcntsh
  - svcntsw
  - svcntsd

Co-authored-by: Sagar Kulkarni 

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D134679

Added: 
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c

Modified: 
clang/include/clang/Basic/arm_sme.td
clang/lib/CodeGen/CGBuiltin.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sme.td 
b/clang/include/clang/Basic/arm_sme.td
index 945f212963d6c9..74ba023f4f42cf 100644
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -135,3 +135,19 @@ let TargetGuard = "sme" in {
   def SVZERO_ZA  : SInst<"svzero_za", "v", "", MergeNone, 
"aarch64_sme_zero",
  [IsOverloadNone, IsStreamingCompatible, 
IsSharedZA]>;
 }
+
+
+// SME - Counting elements in a streaming vector
+
+multiclass ZACount {
+  let TargetGuard = "sme" in {
+def NAME : SInst<"sv" # n_suffix, "nv", "", MergeNone,
+  "aarch64_sme_" # n_suffix,
+  [IsOverloadNone, IsStreamingCompatible, IsPreservesZA]>;
+  }
+}
+
+defm SVCNTSB : ZACount<"cntsb">;
+defm SVCNTSH : ZACount<"cntsh">;
+defm SVCNTSW : ZACount<"cntsw">;
+defm SVCNTSD : ZACount<"cntsd">;

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 416c220351267a..d8d1e7aa96ca7a 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -9955,6 +9955,7 @@ Value 
*CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
   getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
   assert(Error == ASTContext::GE_None && "Should not codegen an error");
 
+  llvm::Type *Ty = ConvertType(E->getType());
   llvm::SmallVector Ops;
   for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
 if ((ICEArguments & (1 << i)) == 0)
@@ -9987,6 +9988,12 @@ Value 
*CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
   else if (BuiltinID == SME::BI__builtin_sme_svldr_vnum_za ||
BuiltinID == SME::BI__builtin_sme_svstr_vnum_za)
 return EmitSMELdrStr(TypeFlags, Ops, Builtin->LLVMIntrinsic);
+  else if (Builtin->LLVMIntrinsic != 0) {
+Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic,
+   getSVEOverloadTypes(TypeFlags, Ty, Ops));
+Value *Call = Builder.CreateCall(F, Ops);
+return Call;
+  }
 
   /// Should not happen
   return nullptr;

diff  --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c 
b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
new file mode 100644
index 00..b3b2499a383033
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
@@ -0,0 +1,46 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s 
-check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s 
-check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-C-LABEL: @test_svcntsb(
+// CHECK-CXX-LABEL: @_Z12test_svcntsbv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsb() {
+  return svcntsb();
+}
+
+// CHECK-C-LABEL: @test_svcntsh(
+// CHECK-CXX-LABEL: @_Z12test_svcntshv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsh()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsh() {
+  return svcntsh();
+}
+
+// CHECK-C-LABEL: @test_svcntsw(
+// CHECK-CXX-LABEL: @_Z12test_svcntswv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsw()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsw() {
+  return svcntsw();
+}
+
+// CHECK-C-LABEL: @test_svcntsd(
+// CHECK-CXX-LABEL: @_Z12test_svcntsdv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsd()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsd() {
+  return svcntsd();
+}



__

[clang] 4ae900c - [Clang][AArch64][SME] Add intrinsics for adding vector elements to ZA tile

2023-07-20 Thread Bryan Chan via cfe-commits


Author: Bryan Chan
Date: 2023-07-20T06:06:36-04:00
New Revision: 4ae900c063634e19346b88913e28204a3fc47825

URL: 
https://github.com/llvm/llvm-project/commit/4ae900c063634e19346b88913e28204a3fc47825
DIFF: 
https://github.com/llvm/llvm-project/commit/4ae900c063634e19346b88913e28204a3fc47825.diff

LOG: [Clang][AArch64][SME] Add intrinsics for adding vector elements to ZA tile

This patch adds support for the following SME ACLE intrinsics (as defined
in https://arm-software.github.io/acle/main/acle.html):

  - svaddha_za32[_u32]_m // also for s32
  - svaddva_za32[_u32]_m // also for s32
  - svaddha_za64[_u64]_m // also for s64
  - svaddva_za64[_u64]_m // also for s64

The _za64 versions are available only when the sme-i16i64 feature is enabled.

Co-authored-by: Sagar Kulkarni 

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D134680

Added: 
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c

Modified: 
clang/include/clang/Basic/arm_sme.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sme.td 
b/clang/include/clang/Basic/arm_sme.td
index 74ba023f4f42cf..f6c2fb5fd7f6b6 100644
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -151,3 +151,23 @@ defm SVCNTSB : ZACount<"cntsb">;
 defm SVCNTSH : ZACount<"cntsh">;
 defm SVCNTSW : ZACount<"cntsw">;
 defm SVCNTSD : ZACount<"cntsd">;
+
+
+// SME - ADDHA/ADDVA
+
+multiclass ZAAdd {
+  let TargetGuard = "sme" in {
+def NAME # _ZA32: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPd", "iUi", 
MergeOp1,
+  "aarch64_sme_" # n_suffix, [IsStreaming, IsSharedZA],
+  [ImmCheck<0, ImmCheck0_3>]>;
+  }
+
+  let TargetGuard = "sme-i16i64" in {
+def NAME # _ZA64: SInst<"sv" # n_suffix # "_za64[_{d}]", "viPPd", "lUl", 
MergeOp1,
+ "aarch64_sme_" # n_suffix, [IsStreaming, IsSharedZA],
+ [ImmCheck<0, ImmCheck0_7>]>;
+  }
+}
+
+defm SVADDHA : ZAAdd<"addha">;
+defm SVADDVA : ZAAdd<"addva">;

diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index d8d1e7aa96ca7a..b7fbafda0e5336 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -9989,6 +9989,12 @@ Value 
*CodeGenFunction::EmitAArch64SMEBuiltinExpr(unsigned BuiltinID,
BuiltinID == SME::BI__builtin_sme_svstr_vnum_za)
 return EmitSMELdrStr(TypeFlags, Ops, Builtin->LLVMIntrinsic);
   else if (Builtin->LLVMIntrinsic != 0) {
+// Predicates must match the main datatype.
+for (unsigned i = 0, e = Ops.size(); i != e; ++i)
+  if (auto PredTy = dyn_cast(Ops[i]->getType()))
+if (PredTy->getElementType()->isIntegerTy(1))
+  Ops[i] = EmitSVEPredicateCast(Ops[i], getSVEType(TypeFlags));
+
 Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic,
getSVEOverloadTypes(TypeFlags, Ty, Ops));
 Value *Call = Builder.CreateCall(F, Ops);

diff  --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c 
b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c
new file mode 100644
index 00..b083df79f6
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c
@@ -0,0 +1,110 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s 
-check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s 
-check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | 
FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ 
%s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+#ifdef SME_OVERLOADED_FORMS
+#define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
+#else
+#define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3
+#endif
+
+// CHECK-C-LABEL: @test_svaddha_za32_u32(
+// CHECK-CXX-LABEL: 
@_Z21test_svaddha_za32_u32u10__SVBool_tu10__SVBool_tu12__SVUint32_t(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  
@llvm.aarch64.sve.convert.from.svb

[clang] aebde82 - [Clang][AArch64][SME] Add outer product intrinsics

2023-07-20 Thread Bryan Chan via cfe-commits


Author: Bryan Chan
Date: 2023-07-20T06:06:36-04:00
New Revision: aebde82b29a80b2849e2b5b1b0030f598edee9a4

URL: 
https://github.com/llvm/llvm-project/commit/aebde82b29a80b2849e2b5b1b0030f598edee9a4
DIFF: 
https://github.com/llvm/llvm-project/commit/aebde82b29a80b2849e2b5b1b0030f598edee9a4.diff

LOG: [Clang][AArch64][SME] Add outer product intrinsics

This patch adds support for the following SME ACLE intrinsics (as defined
in https://arm-software.github.io/acle/main/acle.html):

  - svmopa_za32[_bf16]_m  // also for s8, u8, f16, f32
  - svmops_za32[_bf16]_m  // also for s8, u8, f16, f32
  - svsumopa_za32[_s8]_m
  - svsumops_za32[_s8]_m
  - svusmopa_za32[_u8]_m
  - svusmops_za32[_u8]_m

When the sme-f64f64 feature is enabled, the following intrinsics are supported:

  - svmopa_za64_f64_m
  - svmops_za64_f64_m

When the sme-i16i64 feature is enabled, the following intrinsics are supported:

  - svmopa_za64[_s16]_m   // also for u16
  - svmops_za64[_s16]_m   // also for u16
  - svsumopa_za64[_s16]_m
  - svsumops_za64[_s16]_m
  - svusmopa_za64[_u16]_m
  - svusmops_za64[_u16]_m

Co-authored-by: Sagar Kulkarni 

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D134681

Added: 
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c

Modified: 
clang/include/clang/Basic/arm_sme.td
clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/arm_sme.td 
b/clang/include/clang/Basic/arm_sme.td
index f6c2fb5fd7f6b6..b950f5cb8acc20 100644
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -171,3 +171,89 @@ multiclass ZAAdd {
 
 defm SVADDHA : ZAAdd<"addha">;
 defm SVADDVA : ZAAdd<"addva">;
+
+
+// SME - SMOPA, SMOPS, UMOPA, UMOPS
+
+multiclass ZAIntOuterProd {
+  let TargetGuard = "sme" in {
+def NAME # _ZA32_B: SInst<"sv" # n_suffix2 # "_za32[_{d}]",
+  "viPPdd", !cond(!eq(n_suffix1, "s") : "", true: 
"U") # "c",
+  MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 
# "_wide",
+  [IsStreaming, IsSharedZA],
+  [ImmCheck<0, ImmCheck0_3>]>;
+  }
+
+  let TargetGuard = "sme-i16i64" in {
+def NAME # _ZA64_H: SInst<"sv" # n_suffix2 # "_za64[_{d}]",
+  "viPPdd", !cond(!eq(n_suffix1, "s") : "", true: 
"U") # "s",
+  MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 
# "_wide",
+  [IsStreaming, IsSharedZA],
+  [ImmCheck<0, ImmCheck0_7>]>;
+  }
+}
+
+defm SVSMOPA : ZAIntOuterProd<"s", "mopa">;
+defm SVSMOPS : ZAIntOuterProd<"s", "mops">;
+defm SVUMOPA : ZAIntOuterProd<"u", "mopa">;
+defm SVUMOPS : ZAIntOuterProd<"u", "mops">;
+
+
+// SME - SUMOPA, SUMOPS, USMOPA, USMOPS
+
+multiclass ZAIntOuterProdMixedSigns {
+  let TargetGuard = "sme" in {
+def NAME # _ZA32_B: SInst<"sv" # n_suffix1 # n_suffix2 # "_za32[_{d}]",
+  "viPPd" # !cond(!eq(n_suffix1, "su") : "u", 
true: "x"),
+  !cond(!eq(n_suffix1, "su") : "", true: "U") # 
"c",
+  MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 
# "_wide",
+  [IsStreaming, IsSharedZA],
+  [ImmCheck<0, ImmCheck0_3>]>;
+  }
+
+  let TargetGuard = "sme-i16i64" in {
+def NAME # _ZA64_H: SInst<"sv" # n_suffix1 # n_suffix2 # "_za64[_{d}]",
+  "viPPd" # !cond(!eq(n_suffix1, "su") : "u", 
true: "x"),
+  !cond(!eq(n_suffix1, "su") : "", true: "U") # 
"s",
+  MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 
# "_wide",
+  [IsStreaming, IsSharedZA],
+  [ImmCheck<0, ImmCheck0_7>]>;
+  }
+}
+
+defm SVSUMOPA : ZAIntOuterProdMixedSigns<"su", "mopa">;
+defm SVSUMOPS : ZAIntOuterProdMixedSigns<"su", "mops">;
+defm SVUSMOPA : ZAIntOuterProdMixedSigns<"us", "mopa">;
+defm SVUSMOPS : ZAIntOuterProdMixedSigns<"us", "mops">;
+
+
+// SME - FMOPA, FMOPS
+
+multiclass ZAFPOuterProd {
+  let TargetGuard = "sme" in {
+def NAME # _ZA32_B: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "h",
+  MergeOp1, "aarch64_sme_" # n_suffix # "_wide",
+  [IsStreaming, IsSharedZA],
+  [ImmCheck<0

[clang] 2c38740 - [Clang][AArch64][SME] Generate target features from +(no)sme.* options

2023-07-20 Thread Bryan Chan via cfe-commits


Author: Bryan Chan
Date: 2023-07-20T06:06:37-04:00
New Revision: 2c38740ca661a10866a796db105752e15372ddce

URL: 
https://github.com/llvm/llvm-project/commit/2c38740ca661a10866a796db105752e15372ddce
DIFF: 
https://github.com/llvm/llvm-project/commit/2c38740ca661a10866a796db105752e15372ddce.diff

LOG: [Clang][AArch64][SME] Generate target features from +(no)sme.* options

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D142702

Added: 
clang/test/Driver/aarch64-implied-sme-features.c

Modified: 
clang/lib/Driver/ToolChains/Arch/AArch64.cpp

Removed: 




diff  --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp 
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 35470316357951..507ad924770410 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -82,6 +82,25 @@ static bool DecodeAArch64Features(const Driver &D, StringRef 
text,
 else
   return false;
 
+// +sme implies +bf16.
+// +sme-f64f64 and +sme-i16i64 both imply +sme.
+if (Feature == "sme") {
+  Features.push_back("+bf16");
+} else if (Feature == "nosme") {
+  Features.push_back("-sme-f64f64");
+  Features.push_back("-sme-i16i64");
+} else if (Feature == "sme-f64f64") {
+  Features.push_back("+sme");
+  Features.push_back("+bf16");
+} else if (Feature == "sme-i16i64") {
+  Features.push_back("+sme");
+  Features.push_back("+bf16");
+} else if (Feature == "nobf16") {
+  Features.push_back("-sme");
+  Features.push_back("-sme-f64f64");
+  Features.push_back("-sme-i16i64");
+}
+
 if (Feature == "sve2")
   Features.push_back("+sve");
 else if (Feature == "sve2-bitperm" || Feature == "sve2-sha3" ||

diff  --git a/clang/test/Driver/aarch64-implied-sme-features.c 
b/clang/test/Driver/aarch64-implied-sme-features.c
new file mode 100644
index 00..2277aceb881d73
--- /dev/null
+++ b/clang/test/Driver/aarch64-implied-sme-features.c
@@ -0,0 +1,49 @@
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme %s -### 2>&1 | 
FileCheck %s --check-prefix=SME-IMPLY
+// SME-IMPLY: "-target-feature" "+sme" "-target-feature" "+bf16"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme %s -### 2>&1 | 
FileCheck %s --check-prefix=NOSME
+// NOSME: "-target-feature" "-sme"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+nosme %s -### 2>&1 
| FileCheck %s --check-prefix=SME-REVERT
+// SME-REVERT-NOT: "-target-feature" "+sme"
+// SME-REVERT: "-target-feature" "+bf16" "-target-feature" "-sme" 
"-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme+nobf16 %s -### 
2>&1 | FileCheck %s --check-prefix=SME-CONFLICT
+// SME-CONFLICT-NOT: "-target-feature" "+sme"
+// SME-CONFLICT-NOT: "-target-feature" "+bf16"
+// SME-CONFLICT: "-target-feature" "-bf16" "-target-feature" "-sme" 
"-target-feature" "-sme-f64f64" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64 %s -### 
2>&1 | FileCheck %s --check-prefix=SME-I16I64
+// SME-I16I64: "-target-feature" "+sme-i16i64" "-target-feature" "+sme" 
"-target-feature" "+bf16"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme-i16i64 %s -### 
2>&1 | FileCheck %s --check-prefix=NOSME-I16I64
+// NOSME-I16I64-NOT: "-target-feature" "+sme-i16i64"
+// NOSME-I16I64-NOT: "-target-feature" "+sme"
+// NOSME-I16I64-NOT: "-target-feature" "+bf16"
+// NOSME-I16I64: "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu 
-march=armv8-a+sme-i16i64+nosme-i16i64 %s -### 2>&1 | FileCheck %s 
--check-prefix=SME-I16I64-REVERT
+// SME-I16I64-REVERT: "-target-feature" "+sme" "-target-feature" "+bf16" 
"-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosme-f64f64 %s -### 
2>&1 | FileCheck %s --check-prefix=NOSME-F64F64
+// NOSME-F64F64-NOT: "-target-feature" "+sme-f64f64"
+// NOSME-F64F64-NOT: "-target-feature" "+sme"
+// NOSME-F64F64-NOT: "-target-feature" "+bf16"
+// NOSME-F64F64: "-target-feature" "-sme-f64f64"
+
+// RUN: %clang -target aarch64-linux-gnu 
-march=armv8-a+sme-f64f64+nosme-f64f64 %s -### 2>&1 | FileCheck %s 
--check-prefix=SME-F64F64-REVERT
+// SME-F64F64-REVERT: "-target-feature" "+sme" "-target-feature" "+bf16" 
"-target-feature" "-sme-f64f64"
+
+// RUN: %clang -target aarch64-linux-gnu 
-march=armv8-a+sme-f64f64+nosme-i16i64 %s -### 2>&1 | FileCheck %s 
--check-prefix=SME-SUBFEATURE-MIX
+// SME-SUBFEATURE-MIX: "-target-feature" "+sme-f64f64" "-target-feature" 
"+sme" "-target-feature" "+bf16" "-target-feature" "-sme-i16i64"
+
+// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sme-i16i64+nosme %s 
-### 2>&1 | FileCheck %s --check-prefix=SME-SUBFEATURE-CONFLICT1
+// SME-SUBFEATURE-CONFLICT1: "-target-feature" "+bf16" "-target-feature" 
"-sm

[clang] dc8e46c - [flang][driver] Mark -fuse-ld as visible in Flang

2023-08-23 Thread Bryan Chan via cfe-commits


Author: Hao Jin
Date: 2023-08-23T12:53:16-04:00
New Revision: dc8e46c7e5ea5f98218c9789164ff410cc14079c

URL: 
https://github.com/llvm/llvm-project/commit/dc8e46c7e5ea5f98218c9789164ff410cc14079c
DIFF: 
https://github.com/llvm/llvm-project/commit/dc8e46c7e5ea5f98218c9789164ff410cc14079c.diff

LOG: [flang][driver] Mark -fuse-ld as visible in Flang

The option fuse-ld is not visible in Flang. Flang reports
"Unknown argument: '-fuse-ld'" during link stage.

Reviewed By: awarzynski, kiranchandramohan

Differential Revision: https://reviews.llvm.org/D158430

Added: 


Modified: 
clang/include/clang/Driver/Options.td
flang/test/Driver/misc-flags.f90

Removed: 




diff  --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 619c418365c262..49bf5d6621b46f 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5887,7 +5887,7 @@ def fbinutils_version_EQ : Joined<["-"], 
"fbinutils-version=">,
   "generated assembly will consider GNU as support. 'none' means that all ELF "
   "features can be used, regardless of binutils support. Defaults to 2.26.">;
 def fuse_ld_EQ : Joined<["-"], "fuse-ld=">, Group,
-  Flags<[LinkOption]>, Visibility<[ClangOption, CLOption]>;
+  Flags<[LinkOption]>, Visibility<[ClangOption, FlangOption, CLOption]>;
 def ld_path_EQ : Joined<["--"], "ld-path=">, Group;
 
 defm align_labels : BooleanFFlag<"align-labels">, 
Group;

diff  --git a/flang/test/Driver/misc-flags.f90 
b/flang/test/Driver/misc-flags.f90
index 0c367b90b0b6c7..ab5ed7e93dc8a1 100644
--- a/flang/test/Driver/misc-flags.f90
+++ b/flang/test/Driver/misc-flags.f90
@@ -4,6 +4,9 @@
 ! Make sure that `-Wl` is "visible" to Flang's driver
 ! RUN: %flang -Wl,abs -### %s
 
+! Make sure that `-fuse-ld' is "visible" to Flang's driver
+! RUN: %flang -fuse-ld= -### %s
+
 program hello
   write(*,*), "Hello world!"
 end program hello



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[clang] 1561495 - [flang][driver] Mark -L as visible in Flang

2023-08-25 Thread Bryan Chan via cfe-commits


Author: Hao Jin
Date: 2023-08-25T13:01:49-04:00
New Revision: 1561495cd128a641b9efcbb9d19d36e5a9c5e952

URL: 
https://github.com/llvm/llvm-project/commit/1561495cd128a641b9efcbb9d19d36e5a9c5e952
DIFF: 
https://github.com/llvm/llvm-project/commit/1561495cd128a641b9efcbb9d19d36e5a9c5e952.diff

LOG: [flang][driver] Mark -L as visible in Flang

Reviewed By: awarzynski

Differential Revision: https://reviews.llvm.org/D158763

Added: 


Modified: 
clang/include/clang/Driver/Options.td
flang/test/Driver/driver-help-hidden.f90
flang/test/Driver/driver-help.f90
flang/test/Driver/misc-flags.f90

Removed: 




diff  --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 49bf5d6621b46f..da2dc934e37cfd 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -818,6 +818,7 @@ are searched. If the same directory is in the SYSTEM 
include search
 paths, for example if also specified with -isystem, the -I option
 will be ignored}]>;
 def L : JoinedOrSeparate<["-"], "L">, Flags<[RenderJoined]>, Group,
+Visibility<[ClangOption, FlangOption]>,
 MetaVarName<"">, HelpText<"Add directory to library search path">;
 def MD : Flag<["-"], "MD">, Group,
 HelpText<"Write a depfile containing user and system headers">;

diff  --git a/flang/test/Driver/driver-help-hidden.f90 
b/flang/test/Driver/driver-help-hidden.f90
index 80708a7cfafe4b..7f827026b9203d 100644
--- a/flang/test/Driver/driver-help-hidden.f90
+++ b/flang/test/Driver/driver-help-hidden.f90
@@ -102,6 +102,7 @@
 ! CHECK-NEXT: --help-hidden   Display help for hidden options
 ! CHECK-NEXT: -help   Display available options
 ! CHECK-NEXT: -I Add directory to the end of the list of 
include search paths
+! CHECK-NEXT: -L Add directory to library search path
 ! CHECK-NEXT: -march=  For a list of available architectures 
for the target use '-mcpu=help'
 ! CHECK-NEXT: -mcpu=   For a list of available CPUs for the 
target use '-mcpu=help'
 ! CHECK-NEXT: -mllvm=Alias for -mllvm

diff  --git a/flang/test/Driver/driver-help.f90 
b/flang/test/Driver/driver-help.f90
index 7e7d127188093f..b1da592ca0bd8a 100644
--- a/flang/test/Driver/driver-help.f90
+++ b/flang/test/Driver/driver-help.f90
@@ -90,6 +90,7 @@
 ! HELP-NEXT: --help-hidden   Display help for hidden options
 ! HELP-NEXT: -help   Display available options
 ! HELP-NEXT: -I Add directory to the end of the list of 
include search paths
+! HELP-NEXT: -L Add directory to library search path
 ! HELP-NEXT: -march=  For a list of available architectures for 
the target use '-mcpu=help'
 ! HELP-NEXT: -mcpu=   For a list of available CPUs for the 
target use '-mcpu=help'
 ! HELP-NEXT: -mllvm=Alias for -mllvm

diff  --git a/flang/test/Driver/misc-flags.f90 
b/flang/test/Driver/misc-flags.f90
index ab5ed7e93dc8a1..61d763c5b64dd2 100644
--- a/flang/test/Driver/misc-flags.f90
+++ b/flang/test/Driver/misc-flags.f90
@@ -7,6 +7,9 @@
 ! Make sure that `-fuse-ld' is "visible" to Flang's driver
 ! RUN: %flang -fuse-ld= -### %s
 
+! Make sure that `-L' is "visible" to Flang's driver
+! RUN: %flang -L/ -### %s
+
 program hello
   write(*,*), "Hello world!"
 end program hello



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[clang] 74e6ce2 - [Frontend] Allow OpenMP offloading to aarch64

2019-12-08 Thread Bryan Chan via cfe-commits


Author: Bryan Chan
Date: 2019-12-08T14:45:16-05:00
New Revision: 74e6ce2529fae2c3318731c6f4f77bfa92eb6eb7

URL: 
https://github.com/llvm/llvm-project/commit/74e6ce2529fae2c3318731c6f4f77bfa92eb6eb7
DIFF: 
https://github.com/llvm/llvm-project/commit/74e6ce2529fae2c3318731c6f4f77bfa92eb6eb7.diff

LOG: [Frontend] Allow OpenMP offloading to aarch64

Summary:
D30644 added OpenMP offloading to AArch64 targets, then D32035 changed the
frontend to throw an error when offloading is requested for an unsupported
target architecture. However the latter did not include AArch64 in the list
of supported architectures, causing the following unit tests to fail:

libomptarget :: api/omp_get_num_devices.c
libomptarget :: mapping/pr38704.c
libomptarget :: offloading/offloading_success.c
libomptarget :: offloading/offloading_success.cpp

Reviewers: pawosm01, gtbercea, jdoerfert, ABataev

Subscribers: kristof.beyls, guansong, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D70804

Added: 


Modified: 
clang/lib/Frontend/CompilerInvocation.cpp
clang/test/OpenMP/openmp_offload_registration.cpp

Removed: 




diff  --git a/clang/lib/Frontend/CompilerInvocation.cpp 
b/clang/lib/Frontend/CompilerInvocation.cpp
index 198ae69b7655..1af2bdab61e4 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -3070,7 +3070,8 @@ static void ParseLangArgs(LangOptions &Opts, ArgList 
&Args, InputKind IK,
   llvm::Triple TT(A->getValue(i));
 
   if (TT.getArch() == llvm::Triple::UnknownArch ||
-  !(TT.getArch() == llvm::Triple::ppc ||
+  !(TT.getArch() == llvm::Triple::aarch64 ||
+TT.getArch() == llvm::Triple::ppc ||
 TT.getArch() == llvm::Triple::ppc64 ||
 TT.getArch() == llvm::Triple::ppc64le ||
 TT.getArch() == llvm::Triple::nvptx ||

diff  --git a/clang/test/OpenMP/openmp_offload_registration.cpp 
b/clang/test/OpenMP/openmp_offload_registration.cpp
index b49af4d0e380..1aa2067ab8e8 100644
--- a/clang/test/OpenMP/openmp_offload_registration.cpp
+++ b/clang/test/OpenMP/openmp_offload_registration.cpp
@@ -1,5 +1,6 @@
-// Test for offload registration code for two targets
+// Test offload registration for two targets, and test offload target 
validation.
 // RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu 
-fopenmp-targets=x86_64-pc-linux-gnu,powerpc64le-ibm-linux-gnu -emit-llvm %s -o 
- | FileCheck %s
+// RUN: %clang_cc1 -verify -fopenmp -x c -triple x86_64-unknown-linux-gnu 
-fopenmp-targets=aarch64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
 // expected-no-diagnostics
 
 void foo() {



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[clang] 7b85bff - [clang][tests] Fix Flang driver tests for Windows

2023-04-24 Thread Bryan Chan via cfe-commits


Author: Ádám Kallai
Date: 2023-04-24T15:21:08-04:00
New Revision: 7b85bfffc486257361a598a3c9d4b6b67e3f6765

URL: 
https://github.com/llvm/llvm-project/commit/7b85bfffc486257361a598a3c9d4b6b67e3f6765
DIFF: 
https://github.com/llvm/llvm-project/commit/7b85bfffc486257361a598a3c9d4b6b67e3f6765.diff

LOG: [clang][tests] Fix Flang driver tests for Windows

Updated the regular expression in order to match '.exe' suffix,
if these Flang tests are running on Windows.

Differential Revision: https://reviews.llvm.org/D148211

Added: 


Modified: 
clang/test/Driver/flang/flang.f90
clang/test/Driver/flang/flang_ucase.F90
clang/test/Driver/flang/multiple-inputs.f90

Removed: 




diff  --git a/clang/test/Driver/flang/flang.f90 
b/clang/test/Driver/flang/flang.f90
index 9b16f233b231a..5d8edf6308b00 100644
--- a/clang/test/Driver/flang/flang.f90
+++ b/clang/test/Driver/flang/flang.f90
@@ -13,7 +13,7 @@
 ! * (no type specified, resulting in an object file)
 
 ! All invocations should begin with flang -fc1, consume up to here.
-! ALL-LABEL: "{{[^"]*}}flang-new" "-fc1"
+! ALL-LABEL: "{{[^"]*}}flang-new{{[^"/]*}}" "-fc1"
 
 ! Check that f90 files are not treated as "previously preprocessed"
 ! ... in --driver-mode=flang.

diff  --git a/clang/test/Driver/flang/flang_ucase.F90 
b/clang/test/Driver/flang/flang_ucase.F90
index 113ef75f45b87..50305ee337e10 100644
--- a/clang/test/Driver/flang/flang_ucase.F90
+++ b/clang/test/Driver/flang/flang_ucase.F90
@@ -13,7 +13,7 @@
 ! * (no type specified, resulting in an object file)
 
 ! All invocations should begin with flang -fc1, consume up to here.
-! ALL-LABEL: "{{[^"]*}}flang-new" "-fc1"
+! ALL-LABEL: "{{[^"]*}}flang-new{{[^"/]*}}" "-fc1"
 
 ! Check that f90 files are not treated as "previously preprocessed"
 ! ... in --driver-mode=flang.

diff  --git a/clang/test/Driver/flang/multiple-inputs.f90 
b/clang/test/Driver/flang/multiple-inputs.f90
index f6ee60e48fef3..ada999e927a6a 100644
--- a/clang/test/Driver/flang/multiple-inputs.f90
+++ b/clang/test/Driver/flang/multiple-inputs.f90
@@ -1,7 +1,7 @@
 ! Check that flang driver can handle multiple inputs at once.
 
 ! RUN: %clang --driver-mode=flang -### -fsyntax-only %S/Inputs/one.f90 
%S/Inputs/two.f90 2>&1 | FileCheck --check-prefixes=CHECK-SYNTAX-ONLY %s
-! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang-new" "-fc1"
+! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang-new{{[^"/]*}}" "-fc1"
 ! CHECK-SYNTAX-ONLY: "{{[^"]*}}/Inputs/one.f90"
-! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang-new" "-fc1"
+! CHECK-SYNTAX-ONLY-LABEL: "{{[^"]*}}flang-new{{[^"/]*}}" "-fc1"
 ! CHECK-SYNTAX-ONLY: "{{[^"]*}}/Inputs/two.f90"



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r267879 - [SystemZ] Support Swift calling convention

2016-04-28 Thread Bryan Chan via cfe-commits

Author: bryanpkc
Date: Thu Apr 28 08:56:43 2016
New Revision: 267879

URL: http://llvm.org/viewvc/llvm-project?rev=267879&view=rev
Log:
[SystemZ] Support Swift calling convention

Summary:
Port rL265324 to SystemZ to allow using the 'swiftcall' attribute on that 
architecture.

Depends on D19414.

Reviewers: kbarton, rjmccall, uweigand

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D19432

Modified:
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/lib/CodeGen/TargetInfo.cpp

Modified: cfe/trunk/lib/Basic/Targets.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=267879&r1=267878&r2=267879&view=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Thu Apr 28 08:56:43 2016
@@ -6548,6 +6548,16 @@ public:
 .Default(false);
   }
 
+  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override 
{
+switch (CC) {
+case CC_C:
+case CC_Swift:
+  return CCCR_OK;
+default:
+  return CCCR_Warning;
+}
+  }
+
   StringRef getABI() const override {
 if (HasVector)
   return "vector";

Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=267879&r1=267878&r2=267879&view=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Thu Apr 28 08:56:43 2016
@@ -5713,12 +5713,12 @@ void NVPTXTargetCodeGenInfo::addNVVMMeta
 
 namespace {
 
-class SystemZABIInfo : public ABIInfo {
+class SystemZABIInfo : public SwiftABIInfo {
   bool HasVector;
 
 public:
   SystemZABIInfo(CodeGenTypes &CGT, bool HV)
-: ABIInfo(CGT), HasVector(HV) {}
+: SwiftABIInfo(CGT), HasVector(HV) {}
 
   bool isPromotableIntegerType(QualType Ty) const;
   bool isCompoundType(QualType Ty) const;
@@ -5738,6 +5738,12 @@ public:
 
   Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
 QualType Ty) const override;
+
+  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
+ArrayRef scalars,
+bool asReturnValue) const override {
+return occupiesMoreThan(CGT, scalars, /*total*/ 4);
+  }
 };
 
 class SystemZTargetCodeGenInfo : public TargetCodeGenInfo {


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Re: [PATCH] D19432: [SystemZ] Support Swift calling convention

2016-04-28 Thread Bryan Chan via cfe-commits

bryanpkc added a comment.

Thank you for the reviews.


http://reviews.llvm.org/D19432



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[PATCH] D19432: [SystemZ] Support Swift calling convention

2016-04-22 Thread Bryan Chan via cfe-commits

bryanpkc created this revision.
bryanpkc added reviewers: rjmccall, kbarton.
bryanpkc added a subscriber: cfe-commits.
bryanpkc added a dependency: D19414: [SystemZ] Support Swift Calling Convention.

Port rL265324 to SystemZ to allow using the 'swiftcall' attribute on that 
architecture.

Depends on D19414.

http://reviews.llvm.org/D19432

Files:
  lib/Basic/Targets.cpp
  lib/CodeGen/TargetInfo.cpp

Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -5702,12 +5702,12 @@
 
 namespace {
 
-class SystemZABIInfo : public ABIInfo {
+class SystemZABIInfo : public SwiftABIInfo {
   bool HasVector;
 
 public:
   SystemZABIInfo(CodeGenTypes &CGT, bool HV)
-: ABIInfo(CGT), HasVector(HV) {}
+: SwiftABIInfo(CGT), HasVector(HV) {}
 
   bool isPromotableIntegerType(QualType Ty) const;
   bool isCompoundType(QualType Ty) const;
@@ -5727,6 +5727,12 @@
 
   Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
 QualType Ty) const override;
+
+  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
+ArrayRef scalars,
+bool asReturnValue) const override {
+return occupiesMoreThan(CGT, scalars, /*total*/ 4);
+  }
 };
 
 class SystemZTargetCodeGenInfo : public TargetCodeGenInfo {
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -6543,6 +6543,16 @@
 .Default(false);
   }
 
+  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override 
{
+switch (CC) {
+case CC_C:
+case CC_Swift:
+  return CCCR_OK;
+default:
+  return CCCR_Warning;
+}
+  }
+
   StringRef getABI() const override {
 if (HasVector)
   return "vector";


Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -5702,12 +5702,12 @@
 
 namespace {
 
-class SystemZABIInfo : public ABIInfo {
+class SystemZABIInfo : public SwiftABIInfo {
   bool HasVector;
 
 public:
   SystemZABIInfo(CodeGenTypes &CGT, bool HV)
-: ABIInfo(CGT), HasVector(HV) {}
+: SwiftABIInfo(CGT), HasVector(HV) {}
 
   bool isPromotableIntegerType(QualType Ty) const;
   bool isCompoundType(QualType Ty) const;
@@ -5727,6 +5727,12 @@
 
   Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
 QualType Ty) const override;
+
+  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
+ArrayRef scalars,
+bool asReturnValue) const override {
+return occupiesMoreThan(CGT, scalars, /*total*/ 4);
+  }
 };
 
 class SystemZTargetCodeGenInfo : public TargetCodeGenInfo {
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -6543,6 +6543,16 @@
 .Default(false);
   }
 
+  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
+switch (CC) {
+case CC_C:
+case CC_Swift:
+  return CCCR_OK;
+default:
+  return CCCR_Warning;
+}
+  }
+
   StringRef getABI() const override {
 if (HasVector)
   return "vector";
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Re: [PATCH] D14727: [Driver] Adapt Linux::GCCVersion::Parse to match GCC 5 installations

2016-05-26 Thread Bryan Chan via cfe-commits

bryanpkc updated this revision to Diff 58722.
bryanpkc added a comment.

Fixed the code to set GoodVersion.MajorStr before returning, and removed an 
unnecessary file 
(test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/4.9.2/crtbegin.o).


http://reviews.llvm.org/D14727

Files:
  lib/Driver/ToolChains.cpp
  test/Driver/Inputs/gcc_version_parsing5/
  test/Driver/Inputs/gcc_version_parsing5/bin/
  test/Driver/Inputs/gcc_version_parsing5/bin/.keep
  test/Driver/Inputs/gcc_version_parsing5/lib/
  test/Driver/Inputs/gcc_version_parsing5/lib/gcc/
  test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/
  test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/5/
  
test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/5/crtbegin.o
  test/Driver/linux-ld.c

Index: test/Driver/linux-ld.c
===
--- test/Driver/linux-ld.c
+++ test/Driver/linux-ld.c
@@ -388,6 +388,15 @@
 // CHECK-GCC-VERSION4: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
 // CHECK-GCC-VERSION4: 
"{{.*}}/Inputs/gcc_version_parsing4/bin/../lib/gcc/i386-unknown-linux/4.7.99{{/|}}crtbegin.o"
 // CHECK-GCC-VERSION4: 
"-L{{.*}}/Inputs/gcc_version_parsing4/bin/../lib/gcc/i386-unknown-linux/4.7.99"
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=i386-unknown-linux -m32 \
+// RUN: -ccc-install-dir %S/Inputs/gcc_version_parsing5/bin \
+// RUN: --gcc-toolchain="" \
+// RUN: --sysroot=%S/Inputs/basic_linux_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-GCC-VERSION5 %s
+// CHECK-GCC-VERSION5: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-GCC-VERSION5: 
"{{.*}}/Inputs/gcc_version_parsing5/bin/../lib/gcc/i386-unknown-linux/5{{/|}}crtbegin.o"
+// CHECK-GCC-VERSION5: 
"-L{{.*}}/Inputs/gcc_version_parsing5/bin/../lib/gcc/i386-unknown-linux/5"
 //
 // Test a simulated installation of libc++ on Linux, both through sysroot and
 // the installation path of Clang.
Index: lib/Driver/ToolChains.cpp
===
--- lib/Driver/ToolChains.cpp
+++ lib/Driver/ToolChains.cpp
@@ -1298,13 +1298,16 @@
   if (First.first.getAsInteger(10, GoodVersion.Major) || GoodVersion.Major < 0)
 return BadVersion;
   GoodVersion.MajorStr = First.first.str();
+  if (First.second.empty())
+return GoodVersion;
   if (Second.first.getAsInteger(10, GoodVersion.Minor) || GoodVersion.Minor < 
0)
 return BadVersion;
   GoodVersion.MinorStr = Second.first.str();
 
   // First look for a number prefix and parse that if present. Otherwise just
   // stash the entire patch string in the suffix, and leave the number
   // unspecified. This covers versions strings such as:
+  //   5(handled above)
   //   4.4
   //   4.4.0
   //   4.4.x


Index: test/Driver/linux-ld.c
===
--- test/Driver/linux-ld.c
+++ test/Driver/linux-ld.c
@@ -388,6 +388,15 @@
 // CHECK-GCC-VERSION4: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
 // CHECK-GCC-VERSION4: "{{.*}}/Inputs/gcc_version_parsing4/bin/../lib/gcc/i386-unknown-linux/4.7.99{{/|}}crtbegin.o"
 // CHECK-GCC-VERSION4: "-L{{.*}}/Inputs/gcc_version_parsing4/bin/../lib/gcc/i386-unknown-linux/4.7.99"
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=i386-unknown-linux -m32 \
+// RUN: -ccc-install-dir %S/Inputs/gcc_version_parsing5/bin \
+// RUN: --gcc-toolchain="" \
+// RUN: --sysroot=%S/Inputs/basic_linux_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-GCC-VERSION5 %s
+// CHECK-GCC-VERSION5: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-GCC-VERSION5: "{{.*}}/Inputs/gcc_version_parsing5/bin/../lib/gcc/i386-unknown-linux/5{{/|}}crtbegin.o"
+// CHECK-GCC-VERSION5: "-L{{.*}}/Inputs/gcc_version_parsing5/bin/../lib/gcc/i386-unknown-linux/5"
 //
 // Test a simulated installation of libc++ on Linux, both through sysroot and
 // the installation path of Clang.
Index: lib/Driver/ToolChains.cpp
===
--- lib/Driver/ToolChains.cpp
+++ lib/Driver/ToolChains.cpp
@@ -1298,13 +1298,16 @@
   if (First.first.getAsInteger(10, GoodVersion.Major) || GoodVersion.Major < 0)
 return BadVersion;
   GoodVersion.MajorStr = First.first.str();
+  if (First.second.empty())
+return GoodVersion;
   if (Second.first.getAsInteger(10, GoodVersion.Minor) || GoodVersion.Minor < 0)
 return BadVersion;
   GoodVersion.MinorStr = Second.first.str();
 
   // First look for a number prefix and parse that if present. Otherwise just
   // stash the entire patch string in the suffix, and leave the number
   // unspecified. This covers versions strings such as:
+  //   5(handled above)
   //   4.4
   //   4.4.0
   //   4.4.x
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Re: [PATCH] D14727: [Driver] Adapt Linux::GCCVersion::Parse to match GCC 5 installations

2016-05-26 Thread Bryan Chan via cfe-commits

bryanpkc updated this revision to Diff 58723.
bryanpkc added a comment.

Re-added 
test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/4.9.2/crtbegin.o.


http://reviews.llvm.org/D14727

Files:
  lib/Driver/ToolChains.cpp
  test/Driver/Inputs/gcc_version_parsing5/
  test/Driver/Inputs/gcc_version_parsing5/bin/
  test/Driver/Inputs/gcc_version_parsing5/bin/.keep
  test/Driver/Inputs/gcc_version_parsing5/lib/
  test/Driver/Inputs/gcc_version_parsing5/lib/gcc/
  test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/
  test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/4.9.2/
  
test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/4.9.2/crtbegin.o
  test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/5/
  
test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/5/crtbegin.o
  test/Driver/linux-ld.c

Index: test/Driver/linux-ld.c
===
--- test/Driver/linux-ld.c
+++ test/Driver/linux-ld.c
@@ -388,6 +388,15 @@
 // CHECK-GCC-VERSION4: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
 // CHECK-GCC-VERSION4: 
"{{.*}}/Inputs/gcc_version_parsing4/bin/../lib/gcc/i386-unknown-linux/4.7.99{{/|}}crtbegin.o"
 // CHECK-GCC-VERSION4: 
"-L{{.*}}/Inputs/gcc_version_parsing4/bin/../lib/gcc/i386-unknown-linux/4.7.99"
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=i386-unknown-linux -m32 \
+// RUN: -ccc-install-dir %S/Inputs/gcc_version_parsing5/bin \
+// RUN: --gcc-toolchain="" \
+// RUN: --sysroot=%S/Inputs/basic_linux_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-GCC-VERSION5 %s
+// CHECK-GCC-VERSION5: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-GCC-VERSION5: 
"{{.*}}/Inputs/gcc_version_parsing5/bin/../lib/gcc/i386-unknown-linux/5{{/|}}crtbegin.o"
+// CHECK-GCC-VERSION5: 
"-L{{.*}}/Inputs/gcc_version_parsing5/bin/../lib/gcc/i386-unknown-linux/5"
 //
 // Test a simulated installation of libc++ on Linux, both through sysroot and
 // the installation path of Clang.
Index: lib/Driver/ToolChains.cpp
===
--- lib/Driver/ToolChains.cpp
+++ lib/Driver/ToolChains.cpp
@@ -1298,13 +1298,16 @@
   if (First.first.getAsInteger(10, GoodVersion.Major) || GoodVersion.Major < 0)
 return BadVersion;
   GoodVersion.MajorStr = First.first.str();
+  if (First.second.empty())
+return GoodVersion;
   if (Second.first.getAsInteger(10, GoodVersion.Minor) || GoodVersion.Minor < 
0)
 return BadVersion;
   GoodVersion.MinorStr = Second.first.str();
 
   // First look for a number prefix and parse that if present. Otherwise just
   // stash the entire patch string in the suffix, and leave the number
   // unspecified. This covers versions strings such as:
+  //   5(handled above)
   //   4.4
   //   4.4.0
   //   4.4.x


Index: test/Driver/linux-ld.c
===
--- test/Driver/linux-ld.c
+++ test/Driver/linux-ld.c
@@ -388,6 +388,15 @@
 // CHECK-GCC-VERSION4: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
 // CHECK-GCC-VERSION4: "{{.*}}/Inputs/gcc_version_parsing4/bin/../lib/gcc/i386-unknown-linux/4.7.99{{/|}}crtbegin.o"
 // CHECK-GCC-VERSION4: "-L{{.*}}/Inputs/gcc_version_parsing4/bin/../lib/gcc/i386-unknown-linux/4.7.99"
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=i386-unknown-linux -m32 \
+// RUN: -ccc-install-dir %S/Inputs/gcc_version_parsing5/bin \
+// RUN: --gcc-toolchain="" \
+// RUN: --sysroot=%S/Inputs/basic_linux_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-GCC-VERSION5 %s
+// CHECK-GCC-VERSION5: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-GCC-VERSION5: "{{.*}}/Inputs/gcc_version_parsing5/bin/../lib/gcc/i386-unknown-linux/5{{/|}}crtbegin.o"
+// CHECK-GCC-VERSION5: "-L{{.*}}/Inputs/gcc_version_parsing5/bin/../lib/gcc/i386-unknown-linux/5"
 //
 // Test a simulated installation of libc++ on Linux, both through sysroot and
 // the installation path of Clang.
Index: lib/Driver/ToolChains.cpp
===
--- lib/Driver/ToolChains.cpp
+++ lib/Driver/ToolChains.cpp
@@ -1298,13 +1298,16 @@
   if (First.first.getAsInteger(10, GoodVersion.Major) || GoodVersion.Major < 0)
 return BadVersion;
   GoodVersion.MajorStr = First.first.str();
+  if (First.second.empty())
+return GoodVersion;
   if (Second.first.getAsInteger(10, GoodVersion.Minor) || GoodVersion.Minor < 0)
 return BadVersion;
   GoodVersion.MinorStr = Second.first.str();
 
   // First look for a number prefix and parse that if present. Otherwise just
   // stash the entire patch string in the suffix, and leave the number
   // unspecified. This covers versions strings such as:
+  //   5(handled above)
   //   4.4
   //   4.4.0
   //   4.4.x
___

Re: [PATCH] D14727: [Driver] Adapt Linux::GCCVersion::Parse to match GCC 5 installations

2016-06-14 Thread Bryan Chan via cfe-commits

bryanpkc added a comment.

Ping?


http://reviews.llvm.org/D14727



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r273012 - [Driver] Adapt Linux::GCCVersion::Parse to match GCC 5 installations

2016-06-17 Thread Bryan Chan via cfe-commits

Author: bryanpkc
Date: Fri Jun 17 11:47:14 2016
New Revision: 273012

URL: http://llvm.org/viewvc/llvm-project?rev=273012&view=rev
Log:
[Driver] Adapt Linux::GCCVersion::Parse to match GCC 5 installations

Summary:
Some GCC 5 installations store the libstdc++ includes and GCC-specific files in 
paths without 
the minor part of the version number, such as

  /usr/include/c++/5
  /usr/lib64/gcc/x86_64-suse-linux/5

Reviewers: cfe-commits, thiagomacieira, jroelofs

Subscribers: tinti, jroelofs

Differential Revision: http://reviews.llvm.org/D14727

Added:
cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/
cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/bin/
cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/bin/.keep
cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/lib/
cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/lib/gcc/

cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/

cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/4.9.2/

cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/4.9.2/crtbegin.o

cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/5/

cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/5/crtbegin.o
Modified:
cfe/trunk/lib/Driver/ToolChains.cpp
cfe/trunk/test/Driver/linux-ld.c

Modified: cfe/trunk/lib/Driver/ToolChains.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains.cpp?rev=273012&r1=273011&r2=273012&view=diff
==
--- cfe/trunk/lib/Driver/ToolChains.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains.cpp Fri Jun 17 11:47:14 2016
@@ -1298,6 +1298,8 @@ Generic_GCC::GCCVersion Linux::GCCVersio
   if (First.first.getAsInteger(10, GoodVersion.Major) || GoodVersion.Major < 0)
 return BadVersion;
   GoodVersion.MajorStr = First.first.str();
+  if (First.second.empty())
+return GoodVersion;
   if (Second.first.getAsInteger(10, GoodVersion.Minor) || GoodVersion.Minor < 
0)
 return BadVersion;
   GoodVersion.MinorStr = Second.first.str();
@@ -1305,6 +1307,7 @@ Generic_GCC::GCCVersion Linux::GCCVersio
   // First look for a number prefix and parse that if present. Otherwise just
   // stash the entire patch string in the suffix, and leave the number
   // unspecified. This covers versions strings such as:
+  //   5(handled above)
   //   4.4
   //   4.4.0
   //   4.4.x

Added: cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/bin/.keep
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/bin/.keep?rev=273012&view=auto
==
(empty)

Added: 
cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/4.9.2/crtbegin.o
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/4.9.2/crtbegin.o?rev=273012&view=auto
==
(empty)

Added: 
cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/5/crtbegin.o
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/Inputs/gcc_version_parsing5/lib/gcc/i386-unknown-linux/5/crtbegin.o?rev=273012&view=auto
==
(empty)

Modified: cfe/trunk/test/Driver/linux-ld.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/linux-ld.c?rev=273012&r1=273011&r2=273012&view=diff
==
--- cfe/trunk/test/Driver/linux-ld.c (original)
+++ cfe/trunk/test/Driver/linux-ld.c Fri Jun 17 11:47:14 2016
@@ -388,6 +388,15 @@
 // CHECK-GCC-VERSION4: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
 // CHECK-GCC-VERSION4: 
"{{.*}}/Inputs/gcc_version_parsing4/bin/../lib/gcc/i386-unknown-linux/4.7.99{{/|}}crtbegin.o"
 // CHECK-GCC-VERSION4: 
"-L{{.*}}/Inputs/gcc_version_parsing4/bin/../lib/gcc/i386-unknown-linux/4.7.99"
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=i386-unknown-linux -m32 \
+// RUN: -ccc-install-dir %S/Inputs/gcc_version_parsing5/bin \
+// RUN: --gcc-toolchain="" \
+// RUN: --sysroot=%S/Inputs/basic_linux_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-GCC-VERSION5 %s
+// CHECK-GCC-VERSION5: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-GCC-VERSION5: 
"{{.*}}/Inputs/gcc_version_parsing5/bin/../lib/gcc/i386-unknown-linux/5{{/|}}crtbegin.o"
+// CHECK-GCC-VERSION5: 
"-L{{.*}}/Inputs/gcc_version_parsing5/bin/../lib/gcc/i386-unknown-linux/5"
 //
 // Test a simulated installation of libc++ on Linux, both through sysroot and
 // the installation path of Clang.


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Re: [PATCH] D14727: [Driver] Adapt Linux::GCCVersion::Parse to match GCC 5 installations

2016-06-17 Thread Bryan Chan via cfe-commits

bryanpkc added a comment.

Thanks for the review! I have committed the patch.


http://reviews.llvm.org/D14727



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[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

2025-06-12 Thread Bryan Chan via cfe-commits


https://github.com/bryanpkc edited 
https://github.com/llvm/llvm-project/pull/143915
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[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

2025-06-12 Thread Bryan Chan via cfe-commits



@@ -5146,10 +5146,16 @@ def mno_fix_cortex_a72_aes_1655431 : Flag<["-"], 
"mno-fix-cortex-a72-aes-1655431
   Alias;
 def mfix_cortex_a53_835769 : Flag<["-"], "mfix-cortex-a53-835769">,
   Group,
-  HelpText<"Workaround Cortex-A53 erratum 835769 (AArch64 only)">;
+  HelpText<"Work around Cortex-A53 erratum 835769 (AArch64 only)">;

bryanpkc wrote:

I changed the spelling here to make the messages consistent across all 
`-mfix-cortex-*` options. 

https://github.com/llvm/llvm-project/pull/143915
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[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

2025-06-12 Thread Bryan Chan via cfe-commits


https://github.com/bryanpkc edited 
https://github.com/llvm/llvm-project/pull/143915
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[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

2025-06-12 Thread Bryan Chan via cfe-commits


https://github.com/bryanpkc updated 
https://github.com/llvm/llvm-project/pull/143915

>From 6e55f9af33afd33d87ab2629bf1b5df7d21a09d0 Mon Sep 17 00:00:00 2001
From: Bryan Chan 
Date: Thu, 12 Jun 2025 11:09:43 -0400
Subject: [PATCH] [Driver] Add options to control workaround for Cortex-A53
 Erratum 843419

Implement the -mfix-cortex-a53-843419 and -mno-fix-cortex-a53-843419 options,
which have been introduced to GCC to allow the user to control the workaround
for the erratum. If the option is enabled (which is the default, unchanged by
this patch), Clang passes --fix-cortex-a53-843419 to the linker when it cannot
ensure that the target is not a Cortex A53, otherwise it doesn't.

See 
https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mfix-cortex-a53-843419
for information on the GCC options.
---
 clang/include/clang/Driver/Options.td   | 10 --
 clang/lib/Driver/ToolChains/Fuchsia.cpp |  4 +++-
 clang/lib/Driver/ToolChains/Gnu.cpp |  4 +++-
 clang/test/Driver/android-link.cpp  | 12 
 4 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 152df89118a6a..af17287aafd51 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5146,10 +5146,16 @@ def mno_fix_cortex_a72_aes_1655431 : Flag<["-"], 
"mno-fix-cortex-a72-aes-1655431
   Alias;
 def mfix_cortex_a53_835769 : Flag<["-"], "mfix-cortex-a53-835769">,
   Group,
-  HelpText<"Workaround Cortex-A53 erratum 835769 (AArch64 only)">;
+  HelpText<"Work around Cortex-A53 erratum 835769 (AArch64 only)">;
 def mno_fix_cortex_a53_835769 : Flag<["-"], "mno-fix-cortex-a53-835769">,
   Group,
-  HelpText<"Don't workaround Cortex-A53 erratum 835769 (AArch64 only)">;
+  HelpText<"Don't work around Cortex-A53 erratum 835769 (AArch64 only)">;
+def mfix_cortex_a53_843419 : Flag<["-"], "mfix-cortex-a53-843419">,
+  Group,
+  HelpText<"Work around Cortex-A53 erratum 843419 (AArch64 only)">;
+def mno_fix_cortex_a53_843419 : Flag<["-"], "mno-fix-cortex-a53-843419">,
+  Group,
+  HelpText<"Don't work around Cortex-A53 erratum 843419 (AArch64 only)">;
 def mmark_bti_property : Flag<["-"], "mmark-bti-property">,
   Group,
   HelpText<"Add .note.gnu.property with BTI to assembly files (AArch64 only)">;
diff --git a/clang/lib/Driver/ToolChains/Fuchsia.cpp 
b/clang/lib/Driver/ToolChains/Fuchsia.cpp
index 1c165bbfe84f5..146dc8bbd5313 100644
--- a/clang/lib/Driver/ToolChains/Fuchsia.cpp
+++ b/clang/lib/Driver/ToolChains/Fuchsia.cpp
@@ -91,7 +91,9 @@ void fuchsia::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 CmdArgs.push_back("--execute-only");
 
 std::string CPU = getCPUName(D, Args, Triple);
-if (CPU.empty() || CPU == "generic" || CPU == "cortex-a53")
+if (Args.hasFlag(options::OPT_mfix_cortex_a53_843419,
+ options::OPT_mno_fix_cortex_a53_843419, true) &&
+(CPU.empty() || CPU == "generic" || CPU == "cortex-a53"))
   CmdArgs.push_back("--fix-cortex-a53-843419");
   }
 
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp 
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 9c68c5c6de2b2..9203bbc91b0bb 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -402,7 +402,9 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C, 
const JobAction &JA,
 
   // Most Android ARM64 targets should enable the linker fix for erratum
   // 843419. Only non-Cortex-A53 devices are allowed to skip this flag.
-  if (Arch == llvm::Triple::aarch64 && (isAndroid || isOHOSFamily)) {
+  if (Arch == llvm::Triple::aarch64 && (isAndroid || isOHOSFamily) &&
+  Args.hasFlag(options::OPT_mfix_cortex_a53_843419,
+   options::OPT_mno_fix_cortex_a53_843419, true)) {
 std::string CPU = getCPUName(D, Args, Triple);
 if (CPU.empty() || CPU == "generic" || CPU == "cortex-a53")
   CmdArgs.push_back("--fix-cortex-a53-843419");
diff --git a/clang/test/Driver/android-link.cpp 
b/clang/test/Driver/android-link.cpp
index ab7dae5405587..b103263cdd3f0 100644
--- a/clang/test/Driver/android-link.cpp
+++ b/clang/test/Driver/android-link.cpp
@@ -16,6 +16,16 @@
 // RUN: FileCheck -check-prefix=CORTEX-A57 < %t %s
 
 // RUN: %clang --target=aarch64-none-linux-android \
+// RUN:   -mno-fix-cortex-a53-843419 \
+// RUN:   -### -v %s 2> %t
+// RUN: FileCheck -check-prefix=OVERRIDDEN < %t %s
+//
+// RUN: %clang -target aarch64-none-linux-android \
+// RUN:   -mno-fix-cortex-a53-843419 -mfix-cortex-a53-843419 \
+// RUN:   -### -v %s 2> %t
+// RUN: FileCheck -check-prefix=OVERRIDDEN2 < %t %s
+//
+// RUN: %clang -target aarch64-none-linux-android \
 // RUN:   -### -v %s 2> %t
 // RUN: FileCheck -check-prefix=MAX-PAGE-SIZE-16KB < %t %s
 
@@ -31,6 +41,8 @@
 // GENERIC-ARM: --fix-cortex-a53-843419
 // CORTEX-A53: --fix-cortex-a53-843419
 // CORTEX-A57-NOT: --fix-cortex-a53-843419
+// OVERRIDDEN-NOT: --fix-cortex-a53-843419
+// OVERRIDDEN2: --fix-cortex

[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

2025-06-12 Thread Bryan Chan via cfe-commits


https://github.com/bryanpkc created 
https://github.com/llvm/llvm-project/pull/143915

Implement the -mfix-cortex-a53-843419 and -mno-fix-cortex-a53-843419 options, 
which have been introduced to GCC to allow the user to control the workaround 
for the erratum. If the option is enabled (which is the default, unchanged by 
this patch), Clang passes --fix-cortex-a53-843419 to the linker when it cannot 
assure that the target is not a Cortex A53, otherwise it doesn't.

See 
https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mfix-cortex-a53-843419
 for information on the GCC options.

>From 641290b7dd420f91f1054e97925c0f7bc9bc0cbe Mon Sep 17 00:00:00 2001
From: Bryan Chan 
Date: Thu, 12 Jun 2025 11:09:43 -0400
Subject: [PATCH] [Driver] Add options to control workaround for Cortex-A53
 Erratum 843419

Implement the -mfix-cortex-a53-843419 and -mno-fix-cortex-a53-843419 options,
which have been introduced to GCC to allow the user to control the workaround
for the erratum. If the option is enabled (which is the default, unchanged by
this patch), Clang passes --fix-cortex-a53-843419 to the linker when it cannot
assure that the target is not a Cortex A53, otherwise it doesn't.

See 
https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mfix-cortex-a53-843419
for information on the GCC options.
---
 clang/include/clang/Driver/Options.td   | 10 --
 clang/lib/Driver/ToolChains/Fuchsia.cpp |  4 +++-
 clang/lib/Driver/ToolChains/Gnu.cpp |  4 +++-
 clang/test/Driver/android-link.cpp  | 12 
 4 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 152df89118a6a..af17287aafd51 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5146,10 +5146,16 @@ def mno_fix_cortex_a72_aes_1655431 : Flag<["-"], 
"mno-fix-cortex-a72-aes-1655431
   Alias;
 def mfix_cortex_a53_835769 : Flag<["-"], "mfix-cortex-a53-835769">,
   Group,
-  HelpText<"Workaround Cortex-A53 erratum 835769 (AArch64 only)">;
+  HelpText<"Work around Cortex-A53 erratum 835769 (AArch64 only)">;
 def mno_fix_cortex_a53_835769 : Flag<["-"], "mno-fix-cortex-a53-835769">,
   Group,
-  HelpText<"Don't workaround Cortex-A53 erratum 835769 (AArch64 only)">;
+  HelpText<"Don't work around Cortex-A53 erratum 835769 (AArch64 only)">;
+def mfix_cortex_a53_843419 : Flag<["-"], "mfix-cortex-a53-843419">,
+  Group,
+  HelpText<"Work around Cortex-A53 erratum 843419 (AArch64 only)">;
+def mno_fix_cortex_a53_843419 : Flag<["-"], "mno-fix-cortex-a53-843419">,
+  Group,
+  HelpText<"Don't work around Cortex-A53 erratum 843419 (AArch64 only)">;
 def mmark_bti_property : Flag<["-"], "mmark-bti-property">,
   Group,
   HelpText<"Add .note.gnu.property with BTI to assembly files (AArch64 only)">;
diff --git a/clang/lib/Driver/ToolChains/Fuchsia.cpp 
b/clang/lib/Driver/ToolChains/Fuchsia.cpp
index 1c165bbfe84f5..146dc8bbd5313 100644
--- a/clang/lib/Driver/ToolChains/Fuchsia.cpp
+++ b/clang/lib/Driver/ToolChains/Fuchsia.cpp
@@ -91,7 +91,9 @@ void fuchsia::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 CmdArgs.push_back("--execute-only");
 
 std::string CPU = getCPUName(D, Args, Triple);
-if (CPU.empty() || CPU == "generic" || CPU == "cortex-a53")
+if (Args.hasFlag(options::OPT_mfix_cortex_a53_843419,
+ options::OPT_mno_fix_cortex_a53_843419, true) &&
+(CPU.empty() || CPU == "generic" || CPU == "cortex-a53"))
   CmdArgs.push_back("--fix-cortex-a53-843419");
   }
 
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp 
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 9c68c5c6de2b2..9203bbc91b0bb 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -402,7 +402,9 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C, 
const JobAction &JA,
 
   // Most Android ARM64 targets should enable the linker fix for erratum
   // 843419. Only non-Cortex-A53 devices are allowed to skip this flag.
-  if (Arch == llvm::Triple::aarch64 && (isAndroid || isOHOSFamily)) {
+  if (Arch == llvm::Triple::aarch64 && (isAndroid || isOHOSFamily) &&
+  Args.hasFlag(options::OPT_mfix_cortex_a53_843419,
+   options::OPT_mno_fix_cortex_a53_843419, true)) {
 std::string CPU = getCPUName(D, Args, Triple);
 if (CPU.empty() || CPU == "generic" || CPU == "cortex-a53")
   CmdArgs.push_back("--fix-cortex-a53-843419");
diff --git a/clang/test/Driver/android-link.cpp 
b/clang/test/Driver/android-link.cpp
index ab7dae5405587..b103263cdd3f0 100644
--- a/clang/test/Driver/android-link.cpp
+++ b/clang/test/Driver/android-link.cpp
@@ -16,6 +16,16 @@
 // RUN: FileCheck -check-prefix=CORTEX-A57 < %t %s
 
 // RUN: %clang --target=aarch64-none-linux-android \
+// RUN:   -mno-fix-cortex-a53-843419 \
+// RUN:   -### -v %s 2> %t
+// RUN: FileCheck -check-prefix=OVERRIDDEN < %t %s
+//
+// RUN: %clang -target aarch64-none-linux-androi

[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

2025-06-16 Thread Bryan Chan via cfe-commits


https://github.com/bryanpkc updated 
https://github.com/llvm/llvm-project/pull/143915

>From 6e55f9af33afd33d87ab2629bf1b5df7d21a09d0 Mon Sep 17 00:00:00 2001
From: Bryan Chan 
Date: Thu, 12 Jun 2025 11:09:43 -0400
Subject: [PATCH] [Driver] Add options to control workaround for Cortex-A53
 Erratum 843419

Implement the -mfix-cortex-a53-843419 and -mno-fix-cortex-a53-843419 options,
which have been introduced to GCC to allow the user to control the workaround
for the erratum. If the option is enabled (which is the default, unchanged by
this patch), Clang passes --fix-cortex-a53-843419 to the linker when it cannot
ensure that the target is not a Cortex A53, otherwise it doesn't.

See 
https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mfix-cortex-a53-843419
for information on the GCC options.
---
 clang/include/clang/Driver/Options.td   | 10 --
 clang/lib/Driver/ToolChains/Fuchsia.cpp |  4 +++-
 clang/lib/Driver/ToolChains/Gnu.cpp |  4 +++-
 clang/test/Driver/android-link.cpp  | 12 
 4 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 152df89118a6a..af17287aafd51 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5146,10 +5146,16 @@ def mno_fix_cortex_a72_aes_1655431 : Flag<["-"], 
"mno-fix-cortex-a72-aes-1655431
   Alias;
 def mfix_cortex_a53_835769 : Flag<["-"], "mfix-cortex-a53-835769">,
   Group,
-  HelpText<"Workaround Cortex-A53 erratum 835769 (AArch64 only)">;
+  HelpText<"Work around Cortex-A53 erratum 835769 (AArch64 only)">;
 def mno_fix_cortex_a53_835769 : Flag<["-"], "mno-fix-cortex-a53-835769">,
   Group,
-  HelpText<"Don't workaround Cortex-A53 erratum 835769 (AArch64 only)">;
+  HelpText<"Don't work around Cortex-A53 erratum 835769 (AArch64 only)">;
+def mfix_cortex_a53_843419 : Flag<["-"], "mfix-cortex-a53-843419">,
+  Group,
+  HelpText<"Work around Cortex-A53 erratum 843419 (AArch64 only)">;
+def mno_fix_cortex_a53_843419 : Flag<["-"], "mno-fix-cortex-a53-843419">,
+  Group,
+  HelpText<"Don't work around Cortex-A53 erratum 843419 (AArch64 only)">;
 def mmark_bti_property : Flag<["-"], "mmark-bti-property">,
   Group,
   HelpText<"Add .note.gnu.property with BTI to assembly files (AArch64 only)">;
diff --git a/clang/lib/Driver/ToolChains/Fuchsia.cpp 
b/clang/lib/Driver/ToolChains/Fuchsia.cpp
index 1c165bbfe84f5..146dc8bbd5313 100644
--- a/clang/lib/Driver/ToolChains/Fuchsia.cpp
+++ b/clang/lib/Driver/ToolChains/Fuchsia.cpp
@@ -91,7 +91,9 @@ void fuchsia::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 CmdArgs.push_back("--execute-only");
 
 std::string CPU = getCPUName(D, Args, Triple);
-if (CPU.empty() || CPU == "generic" || CPU == "cortex-a53")
+if (Args.hasFlag(options::OPT_mfix_cortex_a53_843419,
+ options::OPT_mno_fix_cortex_a53_843419, true) &&
+(CPU.empty() || CPU == "generic" || CPU == "cortex-a53"))
   CmdArgs.push_back("--fix-cortex-a53-843419");
   }
 
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp 
b/clang/lib/Driver/ToolChains/Gnu.cpp
index 9c68c5c6de2b2..9203bbc91b0bb 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -402,7 +402,9 @@ void tools::gnutools::Linker::ConstructJob(Compilation &C, 
const JobAction &JA,
 
   // Most Android ARM64 targets should enable the linker fix for erratum
   // 843419. Only non-Cortex-A53 devices are allowed to skip this flag.
-  if (Arch == llvm::Triple::aarch64 && (isAndroid || isOHOSFamily)) {
+  if (Arch == llvm::Triple::aarch64 && (isAndroid || isOHOSFamily) &&
+  Args.hasFlag(options::OPT_mfix_cortex_a53_843419,
+   options::OPT_mno_fix_cortex_a53_843419, true)) {
 std::string CPU = getCPUName(D, Args, Triple);
 if (CPU.empty() || CPU == "generic" || CPU == "cortex-a53")
   CmdArgs.push_back("--fix-cortex-a53-843419");
diff --git a/clang/test/Driver/android-link.cpp 
b/clang/test/Driver/android-link.cpp
index ab7dae5405587..b103263cdd3f0 100644
--- a/clang/test/Driver/android-link.cpp
+++ b/clang/test/Driver/android-link.cpp
@@ -16,6 +16,16 @@
 // RUN: FileCheck -check-prefix=CORTEX-A57 < %t %s
 
 // RUN: %clang --target=aarch64-none-linux-android \
+// RUN:   -mno-fix-cortex-a53-843419 \
+// RUN:   -### -v %s 2> %t
+// RUN: FileCheck -check-prefix=OVERRIDDEN < %t %s
+//
+// RUN: %clang -target aarch64-none-linux-android \
+// RUN:   -mno-fix-cortex-a53-843419 -mfix-cortex-a53-843419 \
+// RUN:   -### -v %s 2> %t
+// RUN: FileCheck -check-prefix=OVERRIDDEN2 < %t %s
+//
+// RUN: %clang -target aarch64-none-linux-android \
 // RUN:   -### -v %s 2> %t
 // RUN: FileCheck -check-prefix=MAX-PAGE-SIZE-16KB < %t %s
 
@@ -31,6 +41,8 @@
 // GENERIC-ARM: --fix-cortex-a53-843419
 // CORTEX-A53: --fix-cortex-a53-843419
 // CORTEX-A57-NOT: --fix-cortex-a53-843419
+// OVERRIDDEN-NOT: --fix-cortex-a53-843419
+// OVERRIDDEN2: --fix-cortex

[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

2025-06-16 Thread Bryan Chan via cfe-commits


https://github.com/bryanpkc closed 
https://github.com/llvm/llvm-project/pull/143915
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[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

2025-06-16 Thread Bryan Chan via cfe-commits


bryanpkc wrote:

Thanks for the reviews @davemgreen and @smithp35.

https://github.com/llvm/llvm-project/pull/143915
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[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

2025-06-16 Thread Bryan Chan via cfe-commits



@@ -91,7 +91,9 @@ void fuchsia::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 CmdArgs.push_back("--execute-only");
 
 std::string CPU = getCPUName(D, Args, Triple);
-if (CPU.empty() || CPU == "generic" || CPU == "cortex-a53")
+if (Args.hasFlag(options::OPT_mfix_cortex_a53_843419,
+ options::OPT_mno_fix_cortex_a53_843419, true) &&

bryanpkc wrote:

The GCC docs say that these options are "ignored if an architecture or cpu is 
specified on the command line which does not need the workaround". So I think 
what we have in this PR mostly matches that description.

I could submit a new PR to add a condition to check whether the architecture is 
armv8.1-a or later.

https://github.com/llvm/llvm-project/pull/143915
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[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

2025-06-16 Thread Bryan Chan via cfe-commits


https://github.com/bryanpkc edited 
https://github.com/llvm/llvm-project/pull/143915
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r345344 - [AArch64] Implement FP16FML intrinsics

[llvm] [clang] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

[llvm] [clang] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

[clang] [llvm] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

[llvm] [clang] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

[clang] [llvm] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

[llvm] [clang] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

[clang] 275ab24 - [Clang][test] Avoid FileCheck error when matching `-cc1`

[clang] 578b0bd - [Clang][AArch64][SME] Add ZA zeroing intrinsics

[clang] f225898 - [Clang][AArch64][SME] Add intrinsics for ZA array load/store (LDR/STR)

[clang] 15d16a7 - [Clang][AArch64][SME] Add intrinsics for reading streaming vector length

[clang] 4ae900c - [Clang][AArch64][SME] Add intrinsics for adding vector elements to ZA tile

[clang] aebde82 - [Clang][AArch64][SME] Add outer product intrinsics

[clang] 2c38740 - [Clang][AArch64][SME] Generate target features from +(no)sme.* options

[clang] dc8e46c - [flang][driver] Mark -fuse-ld as visible in Flang

[clang] 1561495 - [flang][driver] Mark -L as visible in Flang

[clang] 74e6ce2 - [Frontend] Allow OpenMP offloading to aarch64

[clang] 7b85bff - [clang][tests] Fix Flang driver tests for Windows

r267879 - [SystemZ] Support Swift calling convention

Re: [PATCH] D19432: [SystemZ] Support Swift calling convention

[PATCH] D19432: [SystemZ] Support Swift calling convention

Re: [PATCH] D14727: [Driver] Adapt Linux::GCCVersion::Parse to match GCC 5 installations

Re: [PATCH] D14727: [Driver] Adapt Linux::GCCVersion::Parse to match GCC 5 installations

Re: [PATCH] D14727: [Driver] Adapt Linux::GCCVersion::Parse to match GCC 5 installations

r273012 - [Driver] Adapt Linux::GCCVersion::Parse to match GCC 5 installations

Re: [PATCH] D14727: [Driver] Adapt Linux::GCCVersion::Parse to match GCC 5 installations

[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

[clang] [Driver] Add options to control workaround for Cortex-A53 Erratum 843419 (PR #143915)

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