[clang] 60c9b5f - [AArch64][SVE] Improve codegen for dupq SVE ACLE intrinsics
Author: Bradley Smith
Date: 2021-06-07T12:21:38+01:00
New Revision: 60c9b5f35caeb555f66d261bf5a657ab02a35fef
URL:
https://github.com/llvm/llvm-project/commit/60c9b5f35caeb555f66d261bf5a657ab02a35fef
DIFF:
https://github.com/llvm/llvm-project/commit/60c9b5f35caeb555f66d261bf5a657ab02a35fef.diff
LOG: [AArch64][SVE] Improve codegen for dupq SVE ACLE intrinsics
Use llvm.experimental.vector.insert instead of storing into an alloca
when generating code for these intrinsics. This defers the codegen of
the generated vector to instruction selection, allowing existing
shufflevector style optimizations to apply.
Additionally, introduce a new target transform that can recognise fixed
predicate patterns in the svbool variants of these intrinsics.
Differential Revision: https://reviews.llvm.org/D103082
Added:
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq_const.c
llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-cmpne.ll
Modified:
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq.c
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 9fdf1df9734e2..1b30d44937f3e 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -9061,33 +9061,32 @@ Value
*CodeGenFunction::EmitAArch64SVEBuiltinExpr(unsigned BuiltinID,
if (IsBoolTy)
EltTy = IntegerType::get(getLLVMContext(), SVEBitsPerBlock / NumOpnds);
-Address Alloca = CreateTempAlloca(llvm::ArrayType::get(EltTy, NumOpnds),
- CharUnits::fromQuantity(16));
+SmallVector VecOps;
for (unsigned I = 0; I < NumOpnds; ++I)
- Builder.CreateDefaultAlignedStore(
- IsBoolTy ? Builder.CreateZExt(Ops[I], EltTy) : Ops[I],
- Builder.CreateGEP(Alloca.getElementType(), Alloca.getPointer(),
-{Builder.getInt64(0), Builder.getInt64(I)}));
+VecOps.push_back(Builder.CreateZExt(Ops[I], EltTy));
+Value *Vec = BuildVector(VecOps);
SVETypeFlags TypeFlags(Builtin->TypeModifier);
Value *Pred = EmitSVEAllTruePred(TypeFlags);
llvm::Type *OverloadedTy = getSVEVectorForElementType(EltTy);
-Function *F = CGM.getIntrinsic(Intrinsic::aarch64_sve_ld1rq, OverloadedTy);
-Value *Alloca0 = Builder.CreateGEP(
-Alloca.getElementType(), Alloca.getPointer(),
-{Builder.getInt64(0), Builder.getInt64(0)});
-Value *LD1RQ = Builder.CreateCall(F, {Pred, Alloca0});
+Value *InsertSubVec = Builder.CreateInsertVector(
+OverloadedTy, UndefValue::get(OverloadedTy), Vec, Builder.getInt64(0));
+
+Function *F =
+CGM.getIntrinsic(Intrinsic::aarch64_sve_dupq_lane, OverloadedTy);
+Value *DupQLane =
+Builder.CreateCall(F, {InsertSubVec, Builder.getInt64(0)});
if (!IsBoolTy)
- return LD1RQ;
+ return DupQLane;
// For svdupq_n_b* we need to add an additional 'cmpne' with '0'.
F = CGM.getIntrinsic(NumOpnds == 2 ? Intrinsic::aarch64_sve_cmpne
: Intrinsic::aarch64_sve_cmpne_wide,
OverloadedTy);
-Value *Call =
-Builder.CreateCall(F, {Pred, LD1RQ, EmitSVEDupX(Builder.getInt64(0))});
+Value *Call = Builder.CreateCall(
+F, {Pred, DupQLane, EmitSVEDupX(Builder.getInt64(0))});
return EmitSVEPredicateCast(Call, cast(Ty));
}
diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c
b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c
index 05223d59ea1e9..086d753870ec8 100644
--- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c
+++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c
@@ -24,16 +24,13 @@ svbfloat16_t test_svdupq_lane_bf16(svbfloat16_t data,
uint64_t index) {
svbfloat16_t test_svdupq_n_bf16(bfloat16_t x0, bfloat16_t x1, bfloat16_t x2,
bfloat16_t x3,
bfloat16_t x4, bfloat16_t x5, bfloat16_t x6,
bfloat16_t x7) {
// CHECK-LABEL: test_svdupq_n_bf16
- // CHECK: %[[ALLOCA:.*]] = alloca [8 x bfloat], align 16
- // CHECK-DAG: %[[BASE:.*]] = getelementptr inbounds [8 x bfloat], [8 x
bfloat]* %[[ALLOCA]], i64 0, i64 0
- // CHECK-DAG: store bfloat %x0, bfloat* %[[BASE]], align 16
- //
- // CHECK-DAG: %[[GEP:.*]] = getelementptr inbounds [8 x bfloat], [8 x
bfloat]* %[[ALLOCA]], i64 0, i64 7
- // CHECK: store bfloat %x7, bfloat* %[[GEP]], align 2
- // CHECK-NOT: store
- // CHECK: call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
- // CHECK: %[[LOAD:.*]] = call
@llvm.aarch64.sve.ld1rq.nxv8bf16( %{{.*}}, bfloat* nonnull
%[[BASE]])
- // CHECK: ret %[[LOAD]]
+ // CHECK: insertelement <8 x bfloat
[clang] 325b670 - [Sema][SVE] Properly match builtin ID when using aux target
Author: Bradley Smith
Date: 2021-06-21T12:52:18+01:00
New Revision: 325b6707942dc295a0d7fc9bc23a8242d7a3824f
URL:
https://github.com/llvm/llvm-project/commit/325b6707942dc295a0d7fc9bc23a8242d7a3824f
DIFF:
https://github.com/llvm/llvm-project/commit/325b6707942dc295a0d7fc9bc23a8242d7a3824f.diff
LOG: [Sema][SVE] Properly match builtin ID when using aux target
Differential Revision: https://reviews.llvm.org/D104539
Added:
clang/test/Sema/aarch64-sve-alias-attribute.c
Modified:
clang/lib/Sema/SemaDeclAttr.cpp
Removed:
diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index 17fe8c0713457..d8416c6b5769a 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -5163,7 +5163,10 @@ static bool ArmCdeAliasValid(unsigned BuiltinID,
StringRef AliasName) {
return ArmBuiltinAliasValid(BuiltinID, AliasName, Map, IntrinNames);
}
-static bool ArmSveAliasValid(unsigned BuiltinID, StringRef AliasName) {
+static bool ArmSveAliasValid(ASTContext &Context, unsigned BuiltinID,
+ StringRef AliasName) {
+ if (Context.BuiltinInfo.isAuxBuiltinID(BuiltinID))
+BuiltinID = Context.BuiltinInfo.getAuxBuiltinID(BuiltinID);
return BuiltinID >= AArch64::FirstSVEBuiltin &&
BuiltinID <= AArch64::LastSVEBuiltin;
}
@@ -5180,7 +5183,7 @@ static void handleArmBuiltinAliasAttr(Sema &S, Decl *D,
const ParsedAttr &AL) {
StringRef AliasName = cast(D)->getIdentifier()->getName();
bool IsAArch64 = S.Context.getTargetInfo().getTriple().isAArch64();
- if ((IsAArch64 && !ArmSveAliasValid(BuiltinID, AliasName)) ||
+ if ((IsAArch64 && !ArmSveAliasValid(S.Context, BuiltinID, AliasName)) ||
(!IsAArch64 && !ArmMveAliasValid(BuiltinID, AliasName) &&
!ArmCdeAliasValid(BuiltinID, AliasName))) {
S.Diag(AL.getLoc(), diag::err_attribute_arm_builtin_alias);
@@ -5210,7 +5213,7 @@ static void handleBuiltinAliasAttr(Sema &S, Decl *D,
bool IsAArch64 = S.Context.getTargetInfo().getTriple().isAArch64();
bool IsARM = S.Context.getTargetInfo().getTriple().isARM();
bool IsRISCV = S.Context.getTargetInfo().getTriple().isRISCV();
- if ((IsAArch64 && !ArmSveAliasValid(BuiltinID, AliasName)) ||
+ if ((IsAArch64 && !ArmSveAliasValid(S.Context, BuiltinID, AliasName)) ||
(IsARM && !ArmMveAliasValid(BuiltinID, AliasName) &&
!ArmCdeAliasValid(BuiltinID, AliasName)) ||
(IsRISCV && !RISCVAliasValid(BuiltinID, AliasName)) ||
diff --git a/clang/test/Sema/aarch64-sve-alias-attribute.c
b/clang/test/Sema/aarch64-sve-alias-attribute.c
new file mode 100644
index 0..306d98d27ac97
--- /dev/null
+++ b/clang/test/Sema/aarch64-sve-alias-attribute.c
@@ -0,0 +1,5 @@
+// RUN: %clang_cc1 -triple aarch64-unknown-linux-gnu -aux-triple
aarch64-none-unknown-eabi -target-feature +sve -fopenmp-is-device -fopenmp
-verify -fsyntax-only %s
+
+static __inline__
__attribute__((__clang_arm_builtin_alias(__builtin_sve_svabd_n_f64_m))) //
expected-no-diagnostics
+void
+nop(void);
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 9e7329e - [AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries
Author: Bradley Smith
Date: 2021-06-21T13:00:36+01:00
New Revision: 9e7329e37edee0b4e6e212c90c76014a09dc6d90
URL:
https://github.com/llvm/llvm-project/commit/9e7329e37edee0b4e6e212c90c76014a09dc6d90
DIFF:
https://github.com/llvm/llvm-project/commit/9e7329e37edee0b4e6e212c90c76014a09dc6d90.diff
LOG: [AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries
Differential Revision: https://reviews.llvm.org/D103702
Added:
clang/test/CodeGen/aarch64-sve-vector-bits-codegen.c
llvm/test/CodeGen/AArch64/sve-vscale-attr.ll
Modified:
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
Removed:
diff --git a/clang/test/CodeGen/aarch64-sve-vector-bits-codegen.c
b/clang/test/CodeGen/aarch64-sve-vector-bits-codegen.c
new file mode 100644
index 0..fbae8c261703b
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve-vector-bits-codegen.c
@@ -0,0 +1,17 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-fallow-half-arguments-and-returns -O2 -S -o - %s -msve-vector-bits=256 |
FileCheck %s --check-prefixes=CHECK,CHECK256
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-fallow-half-arguments-and-returns -O2 -S -o - %s -msve-vector-bits=512 |
FileCheck %s --check-prefixes=CHECK,CHECK512
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-fallow-half-arguments-and-returns -O2 -S -o - %s -msve-vector-bits=1024 |
FileCheck %s --check-prefixes=CHECK,CHECK1024
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-fallow-half-arguments-and-returns -O2 -S -o - %s -msve-vector-bits=2048 |
FileCheck %s --check-prefixes=CHECK,CHECK2048
+
+#include
+
+void func(int *restrict a, int *restrict b) {
+// CHECK-LABEL: func
+// CHECK256-COUNT-8: st1w
+// CHECK512-COUNT-4: st1w
+// CHECK1024-COUNT-2: st1w
+// CHECK2048-COUNT-1: st1w
+#pragma clang loop vectorize(enable)
+ for (int i = 0; i < 64; ++i)
+a[i] += b[i];
+}
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index 480600dcd9321..b22eb3b154f54 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -47,18 +47,6 @@ static cl::opt
cl::desc("Call nonlazybind functions via direct GOT load"),
cl::init(false), cl::Hidden);
-static cl::opt SVEVectorBitsMax(
-"aarch64-sve-vector-bits-max",
-cl::desc("Assume SVE vector registers are at most this big, "
- "with zero meaning no maximum size is assumed."),
-cl::init(0), cl::Hidden);
-
-static cl::opt SVEVectorBitsMin(
-"aarch64-sve-vector-bits-min",
-cl::desc("Assume SVE vector registers are at least this big, "
- "with zero meaning no minimum size is assumed."),
-cl::init(0), cl::Hidden);
-
static cl::opt UseAA("aarch64-use-aa", cl::init(true),
cl::desc("Enable the use of AA during codegen."));
@@ -210,14 +198,17 @@ void AArch64Subtarget::initializeProperties() {
AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,
- const TargetMachine &TM, bool LittleEndian)
+ const TargetMachine &TM, bool LittleEndian,
+ unsigned MinSVEVectorSizeInBitsOverride,
+ unsigned MaxSVEVectorSizeInBitsOverride)
: AArch64GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
IsLittle(LittleEndian),
- TargetTriple(TT), FrameLowering(),
- InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
- TLInfo(TM, *this) {
+ MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
+ MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
+ FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS, CPU)),
+ TSInfo(), TLInfo(TM, *this) {
if (AArch64::isX18ReservedByDefault(TT))
ReserveXRegister.set(18);
@@ -356,28 +347,6 @@ void AArch64Subtarget::mirFileLoaded(MachineFunction &MF)
const {
MFI.computeMaxCallFrameSize(MF);
}
-unsigned AArch64Subtarget::getMaxSVEVectorSizeInBits() const {
- assert(HasSVE && "Tried to get SVE vector length without SVE support!");
- assert(SVEVectorBitsMax % 128 == 0 &&
- "SVE requires vector length in multiples of 128!");
- assert((SVEVectorBitsMax >= SVEVectorBitsMin || SVEVectorBitsMax == 0) &&
- "Minimum SVE vector size should not be larger than its maximum!");
- if (SVEVectorBitsMax == 0)
-return 0;
- return (std::max(SVEVec
[clang] ed31ff9 - [AArch64][SVE] Add missing target require to test
Author: Bradley Smith Date: 2021-06-21T15:36:44+01:00 New Revision: ed31ff9c7a9e538ead1fa4feecf09987998621b4 URL: https://github.com/llvm/llvm-project/commit/ed31ff9c7a9e538ead1fa4feecf09987998621b4 DIFF: https://github.com/llvm/llvm-project/commit/ed31ff9c7a9e538ead1fa4feecf09987998621b4.diff LOG: [AArch64][SVE] Add missing target require to test Differential revision: https://reviews.llvm.org/D104643 Added: Modified: clang/test/CodeGen/aarch64-sve-vector-bits-codegen.c Removed: diff --git a/clang/test/CodeGen/aarch64-sve-vector-bits-codegen.c b/clang/test/CodeGen/aarch64-sve-vector-bits-codegen.c index fbae8c261703..2ef8698d3dda 100644 --- a/clang/test/CodeGen/aarch64-sve-vector-bits-codegen.c +++ b/clang/test/CodeGen/aarch64-sve-vector-bits-codegen.c @@ -2,6 +2,7 @@ // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -O2 -S -o - %s -msve-vector-bits=512 | FileCheck %s --check-prefixes=CHECK,CHECK512 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -O2 -S -o - %s -msve-vector-bits=1024 | FileCheck %s --check-prefixes=CHECK,CHECK1024 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -O2 -S -o - %s -msve-vector-bits=2048 | FileCheck %s --check-prefixes=CHECK,CHECK2048 +// REQUIRES: aarch64-registered-target #include ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] e57e1e4 - [clang][AArch64][SVE] Avoid going through memory for fixed/scalable predicate casts
Author: Bradley Smith
Date: 2021-08-04T16:10:37Z
New Revision: e57e1e4e00264b77b2b35ad2bf419a48aecdd6bc
URL:
https://github.com/llvm/llvm-project/commit/e57e1e4e00264b77b2b35ad2bf419a48aecdd6bc
DIFF:
https://github.com/llvm/llvm-project/commit/e57e1e4e00264b77b2b35ad2bf419a48aecdd6bc.diff
LOG: [clang][AArch64][SVE] Avoid going through memory for fixed/scalable
predicate casts
For fixed SVE types, predicates are represented using vectors of i8,
where as for scalable types they are represented using vectors of i1. We
can avoid going through memory for casts between these by bitcasting the
i1 scalable vectors to/from a scalable i8 vector of matching size, which
can then use the existing vector insert/extract logic.
Differential Revision: https://reviews.llvm.org/D106860
Added:
Modified:
clang/lib/CodeGen/CGCall.cpp
clang/lib/CodeGen/CGExprScalar.cpp
clang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
Removed:
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 47a4ed35be85e..1296dfa18b9a5 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -1271,12 +1271,26 @@ static llvm::Value *CreateCoercedLoad(Address Src,
llvm::Type *Ty,
// perform the conversion.
if (auto *ScalableDst = dyn_cast(Ty)) {
if (auto *FixedSrc = dyn_cast(SrcTy)) {
+ // If we are casting a fixed i8 vector to a scalable 16 x i1 predicate
+ // vector, use a vector insert and bitcast the result.
+ bool NeedsBitcast = false;
+ auto PredType =
+ llvm::ScalableVectorType::get(CGF.Builder.getInt1Ty(), 16);
+ llvm::Type *OrigType = Ty;
+ if (ScalableDst == PredType &&
+ FixedSrc->getElementType() == CGF.Builder.getInt8Ty()) {
+ScalableDst = llvm::ScalableVectorType::get(CGF.Builder.getInt8Ty(),
2);
+NeedsBitcast = true;
+ }
if (ScalableDst->getElementType() == FixedSrc->getElementType()) {
auto *Load = CGF.Builder.CreateLoad(Src);
auto *UndefVec = llvm::UndefValue::get(ScalableDst);
auto *Zero = llvm::Constant::getNullValue(CGF.CGM.Int64Ty);
-return CGF.Builder.CreateInsertVector(ScalableDst, UndefVec, Load,
Zero,
- "castScalableSve");
+llvm::Value *Result = CGF.Builder.CreateInsertVector(
+ScalableDst, UndefVec, Load, Zero, "castScalableSve");
+if (NeedsBitcast)
+ Result = CGF.Builder.CreateBitCast(Result, OrigType);
+return Result;
}
}
}
@@ -2857,9 +2871,18 @@ void CodeGenFunction::EmitFunctionProlog(const
CGFunctionInfo &FI,
// llvm.experimental.vector.extract to convert back to the original
// VLST.
if (auto *VecTyTo = dyn_cast(ConvertType(Ty))) {
-auto *Coerced = Fn->getArg(FirstIRArg);
+llvm::Value *Coerced = Fn->getArg(FirstIRArg);
if (auto *VecTyFrom =
dyn_cast(Coerced->getType())) {
+ // If we are casting a scalable 16 x i1 predicate vector to a fixed
i8
+ // vector, bitcast the source and use a vector extract.
+ auto PredType =
+ llvm::ScalableVectorType::get(Builder.getInt1Ty(), 16);
+ if (VecTyFrom == PredType &&
+ VecTyTo->getElementType() == Builder.getInt8Ty()) {
+VecTyFrom = llvm::ScalableVectorType::get(Builder.getInt8Ty(), 2);
+Coerced = Builder.CreateBitCast(Coerced, VecTyFrom);
+ }
if (VecTyFrom->getElementType() == VecTyTo->getElementType()) {
llvm::Value *Zero = llvm::Constant::getNullValue(CGM.Int64Ty);
diff --git a/clang/lib/CodeGen/CGExprScalar.cpp
b/clang/lib/CodeGen/CGExprScalar.cpp
index 418f23bd1a97b..e47701915f2f4 100644
--- a/clang/lib/CodeGen/CGExprScalar.cpp
+++ b/clang/lib/CodeGen/CGExprScalar.cpp
@@ -2063,11 +2063,25 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) {
// perform the bitcast.
if (const auto *FixedSrc = dyn_cast(SrcTy)) {
if (const auto *ScalableDst = dyn_cast(DstTy))
{
+// If we are casting a fixed i8 vector to a scalable 16 x i1 predicate
+// vector, use a vector insert and bitcast the result.
+bool NeedsBitCast = false;
+auto PredType = llvm::ScalableVectorType::get(Builder.getInt1Ty(), 16);
+llvm::Type *OrigType = DstTy;
+if (ScalableDst == PredType &&
+FixedSrc->getElementType() == Builder.getInt8Ty()) {
+ DstTy = llvm::ScalableVectorType::get(Builder.getInt8Ty(), 2);
+ ScalableDst = dyn_cast(DstTy);
+ NeedsBitCast = true;
+}
if (FixedSrc->getElementType() == Scala
[clang] 26f5643 - [Clang][SVE] Properly enable/disable dependant SVE target features based upon +(no)sve.* options
Author: Bradley Smith
Date: 2021-11-18T15:52:28Z
New Revision: 26f56438e3dab44cea4c8f16d4cb16e9424b02c6
URL:
https://github.com/llvm/llvm-project/commit/26f56438e3dab44cea4c8f16d4cb16e9424b02c6
DIFF:
https://github.com/llvm/llvm-project/commit/26f56438e3dab44cea4c8f16d4cb16e9424b02c6.diff
LOG: [Clang][SVE] Properly enable/disable dependant SVE target features based
upon +(no)sve.* options
Co-authored-by: Graham Hunter
Differential Revision: https://reviews.llvm.org/D113776
Added:
clang/test/Driver/aarch64-implied-sve-features.c
Modified:
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
clang/test/Driver/aarch64-cpus.c
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index b43edbe1b080b..0b60d097b9ca3 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -79,6 +79,25 @@ static bool DecodeAArch64Features(const Driver &D, StringRef
text,
else
return false;
+if (Feature == "sve2")
+ Features.push_back("+sve");
+else if (Feature == "sve2-bitperm" || Feature == "sve2-sha3" ||
+ Feature == "sve2-aes" || Feature == "sve2-sm4") {
+ Features.push_back("+sve");
+ Features.push_back("+sve2");
+} else if (Feature == "nosve") {
+ Features.push_back("-sve2");
+ Features.push_back("-sve2-bitperm");
+ Features.push_back("-sve2-sha3");
+ Features.push_back("-sve2-aes");
+ Features.push_back("-sve2-sm4");
+} else if (Feature == "nosve2") {
+ Features.push_back("-sve2-bitperm");
+ Features.push_back("-sve2-sha3");
+ Features.push_back("-sve2-aes");
+ Features.push_back("-sve2-sm4");
+}
+
// +sve implies +f32mm if the base architecture is v8.6A, v8.7A, v9.1A or
// v9.2A. It isn't the case in general that sve implies both f64mm and
f32mm
if ((ArchKind == llvm::AArch64::ArchKind::ARMV8_6A ||
@@ -130,8 +149,20 @@ getAArch64ArchFeaturesFromMarch(const Driver &D, StringRef
March,
llvm::AArch64::ArchKind ArchKind = llvm::AArch64::parseArch(Split.first);
if (ArchKind == llvm::AArch64::ArchKind::INVALID ||
- !llvm::AArch64::getArchFeatures(ArchKind, Features) ||
- (Split.second.size() &&
+ !llvm::AArch64::getArchFeatures(ArchKind, Features))
+return false;
+
+ // Enable SVE2 by default on Armv9-A.
+ // It can still be disabled if +nosve2 is present.
+ // We must do this early so that DecodeAArch64Features has the correct state
+ if ((ArchKind == llvm::AArch64::ArchKind::ARMV9A ||
+ ArchKind == llvm::AArch64::ArchKind::ARMV9_1A ||
+ ArchKind == llvm::AArch64::ArchKind::ARMV9_2A)) {
+Features.push_back("+sve");
+Features.push_back("+sve2");
+ }
+
+ if ((Split.second.size() &&
!DecodeAArch64Features(D, Split.second, Features, ArchKind)))
return false;
@@ -419,14 +450,6 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
if (Pos != std::end(Features))
Pos = Features.insert(std::next(Pos), {"+i8mm", "+bf16"});
- // Enable SVE2 by default on Armv9-A.
- // It can still be disabled if +nosve2 is present.
- const char *SVE2Archs[] = {"+v9a", "+v9.1a", "+v9.2a"};
- Pos = std::find_first_of(Features.begin(), Features.end(),
- std::begin(SVE2Archs), std::end(SVE2Archs));
- if (Pos != Features.end())
-Features.insert(++Pos, "+sve2");
-
if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
options::OPT_munaligned_access)) {
if (A->getOption().matches(options::OPT_mno_unaligned_access))
diff --git a/clang/test/Driver/aarch64-cpus.c
b/clang/test/Driver/aarch64-cpus.c
index 89cfb7e99a57e..4a377df99f925 100644
--- a/clang/test/Driver/aarch64-cpus.c
+++ b/clang/test/Driver/aarch64-cpus.c
@@ -809,7 +809,7 @@
// RUN: %clang -target aarch64 -mlittle-endian -march=armv9-a -### -c %s 2>&1
| FileCheck -check-prefix=GENERICV9A %s
// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9a -### -c %s
2>&1 | FileCheck -check-prefix=GENERICV9A %s
// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9-a -### -c %s
2>&1 | FileCheck -check-prefix=GENERICV9A %s
-// GENERICV9A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
"-target-feature" "+neon" "-target-feature" "+v9a" "-target-feature" "+sve2"
+// GENERICV9A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
"-target-feature" "+neon" "-target-feature" "+v9a" "-target-feature" "+sve"
"-target-feature" "+sve2"
// SVE2 is enabled by default on Armv9-A but it can be disabled
// RUN: %clang -target aarch64 -march=armv9a+nosve2 -### -c %s 2>&1 |
FileCheck -check-prefix=GENERICV9A-NOSVE2 %s
@@ -818,7 +818,7 @@
// RUN: %clang -target aarch64
[clang] 45e102a - [Clang][SVE] Fix windows test breakage in 26f56438e3dab44cea4c8f16d4cb16e9424b02c6
Author: Bradley Smith Date: 2021-11-18T16:52:32Z New Revision: 45e102a173680fd3c90def79a7f0766ed2786ff0 URL: https://github.com/llvm/llvm-project/commit/45e102a173680fd3c90def79a7f0766ed2786ff0 DIFF: https://github.com/llvm/llvm-project/commit/45e102a173680fd3c90def79a7f0766ed2786ff0.diff LOG: [Clang][SVE] Fix windows test breakage in 26f56438e3dab44cea4c8f16d4cb16e9424b02c6 Added: Modified: clang/test/Driver/aarch64-implied-sve-features.c Removed: diff --git a/clang/test/Driver/aarch64-implied-sve-features.c b/clang/test/Driver/aarch64-implied-sve-features.c index 5eebc66749ba..d26b7a07c16e 100644 --- a/clang/test/Driver/aarch64-implied-sve-features.c +++ b/clang/test/Driver/aarch64-implied-sve-features.c @@ -1,78 +1,78 @@ -// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve %s -### |& FileCheck %s --check-prefix=SVE-ONLY +// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve %s -### 2>&1 | FileCheck %s --check-prefix=SVE-ONLY // SVE-ONLY: "-target-feature" "+sve" -// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosve %s -### |& FileCheck %s --check-prefix=NOSVE +// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosve %s -### 2>&1 | FileCheck %s --check-prefix=NOSVE // NOSVE: "-target-feature" "-sve" -// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve+nosve %s -### |& FileCheck %s --check-prefix=SVE-REVERT +// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve+nosve %s -### 2>&1 | FileCheck %s --check-prefix=SVE-REVERT // SVE-REVERT-NOT: "-target-feature" "+sve" // SVE-REVERT: "-target-feature" "-sve" -// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve2 %s -### |& FileCheck %s --check-prefix=SVE2-IMPLY +// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve2 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-IMPLY // SVE2-IMPLY: "-target-feature" "+sve2" "-target-feature" "+sve" -// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve2+nosve2 %s -### |& FileCheck %s --check-prefix=SVE2-REVERT +// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve2+nosve2 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-REVERT // SVE2-REVERT: "-target-feature" "+sve" "-target-feature" "-sve2" -// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve2+nosve %s -### |& FileCheck %s --check-prefix=SVE2-CONFLICT +// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve2+nosve %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-CONFLICT // SVE2-CONFLICT: "-target-feature" "-sve" "-target-feature" "-sve2" "-target-feature" "-sve2-bitperm" "-target-feature" "-sve2-sha3" "-target-feature" "-sve2-aes" "-target-feature" "-sve2-sm4" -// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosve+sve2 %s -### |& FileCheck %s --check-prefix=SVE2-CONFLICT-REV +// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosve+sve2 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-CONFLICT-REV // SVE2-CONFLICT-REV: "-target-feature" "+sve2" "-target-feature" "+sve" -// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve+sve2 %s -### |& FileCheck %s --check-prefix=SVE-SVE2 +// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve+sve2 %s -### 2>&1 | FileCheck %s --check-prefix=SVE-SVE2 // SVE-SVE2: "-target-feature" "+sve2" "-target-feature" "+sve" -// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve2-bitperm %s -### |& FileCheck %s --check-prefix=SVE2-BITPERM +// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve2-bitperm %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-BITPERM // SVE2-BITPERM: "-target-feature" "+sve2-bitperm" "-target-feature" "+sve" "-target-feature" "+sve2" -// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosve2-bitperm %s -### |& FileCheck %s --check-prefix=NOSVE2-BITPERM +// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+nosve2-bitperm %s -### 2>&1 | FileCheck %s --check-prefix=NOSVE2-BITPERM // NOSVE2-BITPERM-NOT: "-target-feature" "+sve2-bitperm" // NOSVE2-BITPERM-NOT: "-target-feature" "+sve2" // NOSVE2-BITPERM-NOT: "-target-feature" "+sve" // NOSVE2-BITPERM: "-target-feature" "-sve2-bitperm" -// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve2-bitperm+nosve2-bitperm %s -### |& FileCheck %s --check-prefix=SVE2-BITPERM-REVERT +// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve2-bitperm+nosve2-bitperm %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-BITPERM-REVERT // SVE2-BITPERM-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-bitperm" -// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve2-aes+nosve2-aes %s -### |& FileCheck %s --check-prefix=SVE2-AES-REVERT +// RUN: %clang -target aarch64-linux-gnu -march=armv8-a+sve2-aes+nosve2-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-AES-REVERT // SVE2-AES-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-ae
Re: [PATCH] D15283: [ARMv8-M] Add Clang targeting for ARMv8-M Baseline/Mainline
bsmith added a comment. Ping. Repository: rL LLVM http://reviews.llvm.org/D15283 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D15283: [ARMv8-M] Add Clang targeting for ARMv8-M Baseline/Mainline
bsmith added a comment. Ping, it would be nice to get this committed to complete ARMv8-M support. Repository: rL LLVM http://reviews.llvm.org/D15283 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20089: Adding a TargetParser for AArch64
bsmith added a comment.
There is an awful lot of duplication/passing through to another class in this,
it strikes me that this whole thing could benefit from some level of
inheritance. I think it would be good to have a base class that defines the
interface and have both ARM/AArch64 (and any other architectures that want to
use this in the future) implement this interface. That way all of this code can
be called generically from clang/wherever.
Comment at: lib/Support/TargetParser.cpp:441
@@ +440,3 @@
+ if (Extensions & AArch64::AEK_PROFILE)
+Features.push_back("+spe");
+
For ARM there is a table that defines these extensions and how they map to
backend features, it would be good to do this in a similar manner.
Comment at: lib/Support/TargetParser.cpp:471
@@ +470,3 @@
+ if (ArchKind >= ARM::AK_LAST)
+return ARMBuildAttrs::CPUArch::Pre_v4;
+ return AArch64ARCHNames[ArchKind].ArchAttr;
This doesn't make sense for AArch64
Comment at: lib/Support/TargetParser.cpp:770
@@ +769,3 @@
+ if (A.ID == ARM::AK_ARMV8_2A)
+Features.push_back("+v8.2a");
+ return A.ID;
Why do we need to add these features explicitly, can't we just pass through the
correct triple?
Repository:
rL LLVM
http://reviews.llvm.org/D20089
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20088: Using AArch64TargetParser in clang
bsmith added inline comments.
Comment at: lib/Driver/Tools.cpp:707
@@ -696,3 +706,3 @@
std::string MArch = arm::getARMArch(ArchName, Triple);
- if (llvm::ARM::parseArch(MArch) == llvm::ARM::AK_INVALID ||
+ if (!checkARMArchValid(MArch) || llvm::ARM::parseArch(MArch) ==
llvm::ARM::AK_INVALID ||
(Split.second.size() && !DecodeARMFeatures(D, Split.second, Features)))
Why do we need the call to checkARMArchValid here? Isn't is sufficient that
parseArch returns a valid architecture?
Comment at: lib/Driver/Tools.cpp:2280
@@ -2276,12 +2279,3 @@
- if (Split.first == "armv8-a" || Split.first == "armv8a") {
-// ok, no additional features.
- } else if (Split.first == "armv8.1-a" || Split.first == "armv8.1a") {
-Features.push_back("+v8.1a");
- } else if (Split.first == "armv8.2-a" || Split.first == "armv8.2a" ) {
-Features.push_back("+v8.2a");
- } else {
-return false;
- }
-
- if (Split.second.size() && !DecodeAArch64Features(D, Split.second, Features))
+ if (!checkAArch64ArchValid(Split.first) ||
llvm::AArch64::parseArch(Split.first, Features) == llvm::ARM::AK_INVALID ||
+ (Split.second.size() && !DecodeAArch64Features(D, Split.second,
Features)))
Same here, why do we need checkAArch64ArchValid?
Repository:
rL LLVM
http://reviews.llvm.org/D20088
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20089: Adding a TargetParser for AArch64
bsmith added a comment. In http://reviews.llvm.org/D20089#425541, @rengolin wrote: > http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20150824/296862.html > > One option is to add the duplication, solve all the platform problems first, > then move to a class based design. > > Another is to go directly to a class based design, but that would mean a much > bigger move. > > I'm ok with either, but I'd prefer a slow and steady change stream. I think that made sense when we only had ARM using this, but not so much now since we essentially have two implementations of the same thing. Repository: rL LLVM http://reviews.llvm.org/D20089 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D15283: [ARMv8-M] Add Clang targeting for ARMv8-M Baseline/Mainline
bsmith added a comment. Ping. This change has been waiting for review for over a month now, it would be great to get this committed. Thanks. Repository: rL LLVM http://reviews.llvm.org/D15283 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D15283: [ARMv8-M] Add Clang targeting for ARMv8-M Baseline/Mainline
bsmith closed this revision. bsmith added a comment. Committed as r262619. Repository: rL LLVM http://reviews.llvm.org/D15283 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r262619 - [ARM] Add Clang targeting for ARMv8-M Baseline/Mainline
Author: brasmi01
Date: Thu Mar 3 07:52:22 2016
New Revision: 262619
URL: http://llvm.org/viewvc/llvm-project?rev=262619&view=rev
Log:
[ARM] Add Clang targeting for ARMv8-M Baseline/Mainline
Modified:
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/lib/Driver/Tools.cpp
cfe/trunk/test/Driver/arm-alignment.c
cfe/trunk/test/Driver/arm-cortex-cpus.c
cfe/trunk/test/Driver/arm-features.c
cfe/trunk/test/Preprocessor/arm-target-features.c
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=262619&r1=262618&r2=262619&view=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Thu Mar 3 07:52:22 2016
@@ -4536,7 +4536,8 @@ class ARMTargetInfo : public TargetInfo
}
bool supportsThumb2() const {
-return CPUAttr.equals("6T2") || ArchVersion >= 7;
+return CPUAttr.equals("6T2") ||
+ (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE"));
}
StringRef getCPUAttr() const {
@@ -4563,6 +4564,10 @@ class ARMTargetInfo : public TargetInfo
return "8_1A";
case llvm::ARM::AK_ARMV8_2A:
return "8_2A";
+case llvm::ARM::AK_ARMV8MBaseline:
+ return "8M_BASE";
+case llvm::ARM::AK_ARMV8MMainline:
+ return "8M_MAIN";
}
}
@@ -4852,13 +4857,14 @@ public:
// __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
// is not defined for the M-profile.
-// NOTE that the deffault profile is assumed to be 'A'
-if (CPUProfile.empty() || CPUProfile != "M")
+// NOTE that the default profile is assumed to be 'A'
+if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M)
Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
-// __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
-// Thumb ISA (including v6-M). It is set to 2 if the core supports the
-// Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
+// __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original
+// Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the
+// core supports the Thumb-2 ISA as found in the v6T2 architecture and all
+// v7 and v8 architectures excluding v8-M Baseline.
if (supportsThumb2())
Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
else if (supportsThumb())
@@ -4978,7 +4984,7 @@ public:
Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
Opts.ShortEnums ? "1" : "4");
-if (ArchVersion >= 6 && CPUAttr != "6M") {
+if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
Modified: cfe/trunk/lib/Driver/Tools.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.cpp?rev=262619&r1=262618&r2=262619&view=diff
==
--- cfe/trunk/lib/Driver/Tools.cpp (original)
+++ cfe/trunk/lib/Driver/Tools.cpp Thu Mar 3 07:52:22 2016
@@ -963,6 +963,10 @@ static void getARMTargetFeatures(const T
// No v6M core supports unaligned memory access (v6M ARM ARM A3.2).
if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
D.Diag(diag::err_target_unsupported_unaligned) << "v6m";
+ // v8M Baseline follows on from v6M, so doesn't support unaligned memory
+ // access either.
+ else if (Triple.getSubArch() ==
llvm::Triple::SubArchType::ARMSubArch_v8m_baseline)
+D.Diag(diag::err_target_unsupported_unaligned) << "v8m.base";
} else
Features.push_back("+strict-align");
} else {
Modified: cfe/trunk/test/Driver/arm-alignment.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-alignment.c?rev=262619&r1=262618&r2=262619&view=diff
==
--- cfe/trunk/test/Driver/arm-alignment.c (original)
+++ cfe/trunk/test/Driver/arm-alignment.c Thu Mar 3 07:52:22 2016
@@ -83,11 +83,13 @@
// CHECK-ALIGNED-ARM: "-target-feature" "+strict-align"
// CHECK-ALIGNED-AARCH64: "-target-feature" "+strict-align"
-// Make sure that v6M cores always trigger the unsupported aligned accesses
error
-// for all supported architecture triples.
+// Make sure that v6M cores and v8M Baseline always trigger the unsupported
+// aligned accesses error for all supported architecture triples.
// RUN: not %clang -c -target thumbv6m-none-gnueabi -mcpu=cortex-m0
-munaligned-access %s 2>&1 | \
// RUN: FileCheck --check-prefix CHECK-UNALIGN-NOT-SUPPORTED %s
// RUN: not %clang -c -target thumb-none-gnueabi -mcpu=cortex-m0
-munaligned-access %s 2>&1 | \
// RUN: FileCheck --check-prefix CHECK-UNALIGN-NOT-SUPPORTED %
Re: [PATCH] D15283: [ARMv8-M] Add Clang targeting for ARMv8-M Baseline/Mainline
bsmith updated this revision to Diff 43884.
bsmith added a comment.
Rebase patch against latest changes made to ARMv8-M targeting, specifically the
removal of 'B' as a profile.
Repository:
rL LLVM
http://reviews.llvm.org/D15283
Files:
lib/Basic/Targets.cpp
lib/Driver/Tools.cpp
test/Driver/arm-alignment.c
test/Driver/arm-cortex-cpus.c
test/Driver/arm-features.c
test/Preprocessor/arm-target-features.c
Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -95,6 +95,42 @@
// THUMBV8A-EABI:#define __ARM_ARCH_EXT_IDIV__ 1
// THUMBV8A-EABI: #define __ARM_FP 0xE
+// RUN: %clang -target armv8m.base-none-linux-gnu -x c -E -dM %s -o - | FileCheck --check-prefix=V8M_BASELINE %s
+// V8M_BASELINE: __ARM_ARCH 8
+// V8M_BASELINE: __ARM_ARCH_8M_BASE__ 1
+// V8M_BASELINE: __ARM_ARCH_EXT_IDIV__ 1
+// V8M_BASELINE-NOT: __ARM_ARCH_ISA_ARM
+// V8M_BASELINE: __ARM_ARCH_ISA_THUMB 1
+// V8M_BASELINE: __ARM_ARCH_PROFILE 'M'
+// V8M_BASELINE-NOT: __ARM_FEATURE_CRC32
+// V8M_BASELINE-NOT: __ARM_FEATURE_DSP
+// V8M_BASELINE-NOT: __ARM_FP 0x{{.*}}
+// V8M_BASELINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+
+// RUN: %clang -target armv8m.main-none-linux-gnu -x c -E -dM %s -o - | FileCheck --check-prefix=V8M_MAINLINE %s
+// V8M_MAINLINE: __ARM_ARCH 8
+// V8M_MAINLINE: __ARM_ARCH_8M_MAIN__ 1
+// V8M_MAINLINE: __ARM_ARCH_EXT_IDIV__ 1
+// V8M_MAINLINE-NOT: __ARM_ARCH_ISA_ARM
+// V8M_MAINLINE: __ARM_ARCH_ISA_THUMB 2
+// V8M_MAINLINE: __ARM_ARCH_PROFILE 'M'
+// V8M_MAINLINE-NOT: __ARM_FEATURE_CRC32
+// V8M_MAINLINE-NOT: __ARM_FEATURE_DSP
+// V8M_MAINLINE: __ARM_FP 0xE
+// V8M_MAINLINE: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+
+// RUN: %clang -target arm-none-linux-gnu -march=armv8-m.main+dsp -x c -E -dM %s -o - | FileCheck --check-prefix=V8M_MAINLINE_DSP %s
+// V8M_MAINLINE_DSP: __ARM_ARCH 8
+// V8M_MAINLINE_DSP: __ARM_ARCH_8M_MAIN__ 1
+// V8M_MAINLINE_DSP: __ARM_ARCH_EXT_IDIV__ 1
+// V8M_MAINLINE_DSP-NOT: __ARM_ARCH_ISA_ARM
+// V8M_MAINLINE_DSP: __ARM_ARCH_ISA_THUMB 2
+// V8M_MAINLINE_DSP: __ARM_ARCH_PROFILE 'M'
+// V8M_MAINLINE_DSP-NOT: __ARM_FEATURE_CRC32
+// V8M_MAINLINE_DSP: __ARM_FEATURE_DSP 1
+// V8M_MAINLINE_DSP: __ARM_FP 0xE
+// V8M_MAINLINE_DSP: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+
// RUN: %clang -target arm-none-linux-gnu -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-DEFS %s
// CHECK-DEFS:#define __ARM_PCS 1
// CHECK-DEFS:#define __ARM_SIZEOF_MINIMAL_ENUM 4
Index: test/Driver/arm-features.c
===
--- test/Driver/arm-features.c
+++ test/Driver/arm-features.c
@@ -4,10 +4,16 @@
// RUN: %clang -target arm-none-none-eabi -mcpu=generic+crypto -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO %s
// RUN: %clang -target arm-none-none-eabi -mcpu=generic -march=armv8a+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO %s
// CHECK-CRYPTO: "-cc1"{{.*}} "-triple" "armv8-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "+crypto"
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic+dsp -march=armv8m.main -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-DSP %s
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic -march=armv8m.main+dsp -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-DSP %s
+// CHECK-DSP: "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "+dsp"
// RUN: %clang -target arm-none-none-eabi -mcpu=generic+nocrc -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRC %s
// RUN: %clang -target arm-none-none-eabi -mcpu=generic -march=armv8a+nocrc -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRC %s
// CHECK-NOCRC: "-cc1"{{.*}} "-triple" "armv8-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "-crc"
// RUN: %clang -target arm-none-none-eabi -mcpu=generic+nocrypto -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO %s
// RUN: %clang -target arm-none-none-eabi -mcpu=generic -march=armv8a+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO %s
// CHECK-NOCRYPTO: "-cc1"{{.*}} "-triple" "armv8-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "-crypto"
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic+nodsp -march=armv8m.main -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NODSP %s
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic -march=armv8m.main+nodsp -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NODSP %s
+// CHECK-NODSP: "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "-dsp"
Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -230,6 +230,24 @@
// RUN: %clang -target arm -march=armebv8.1-a -mbig-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-V81A-
Re: [PATCH] D15283: [ARMv8-M] Add Clang targeting for ARMv8-M Baseline/Mainline
bsmith added a comment. Now that the LLVM side of this is committed, it would be great to get this reviewed also, thanks. Repository: rL LLVM http://reviews.llvm.org/D15283 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D14662: [ARM] Pass architecture to TargetParser defaulting to cope with API change
bsmith created this revision.
bsmith added a reviewer: rengolin.
bsmith added a subscriber: cfe-commits.
bsmith set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.
The TargetParser API to get the default FPU and extensions will change in
D14661, this is so it can fall back to the architecture in case of a generic
CPU. This patch adjusts calls to the changed functions to pass in the correct
information.
Repository:
rL LLVM
http://reviews.llvm.org/D14662
Files:
lib/Basic/Targets.cpp
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -4501,13 +4501,14 @@
const std::vector &FeaturesVec) const override {
std::vector TargetFeatures;
+unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
// get default FPU features
-unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU);
+unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
// get default Extension features
-unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU);
+unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
for (const char *Feature : TargetFeatures)
Index: lib/Basic/Targets.cpp
===
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -4501,13 +4501,14 @@
const std::vector &FeaturesVec) const override {
std::vector TargetFeatures;
+unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
// get default FPU features
-unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU);
+unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
// get default Extension features
-unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU);
+unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
for (const char *Feature : TargetFeatures)
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D14662: [ARM] Pass architecture to TargetParser defaulting to cope with API change
bsmith closed this revision. bsmith added a comment. Thanks, committed as r253199. Repository: rL LLVM http://reviews.llvm.org/D14662 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r253199 - [ARM] Pass in the architecture to TargetParser to cope with API change
Author: brasmi01
Date: Mon Nov 16 05:16:36 2015
New Revision: 253199
URL: http://llvm.org/viewvc/llvm-project?rev=253199&view=rev
Log:
[ARM] Pass in the architecture to TargetParser to cope with API change
The TargetParser API to get the default FPU and default extensions has
changed so that it can fall back to the architecture in case of a
generic CPU.
Modified:
cfe/trunk/lib/Basic/Targets.cpp
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=253199&r1=253198&r2=253199&view=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Mon Nov 16 05:16:36 2015
@@ -4501,13 +4501,14 @@ public:
const std::vector &FeaturesVec) const override {
std::vector TargetFeatures;
+unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName());
// get default FPU features
-unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU);
+unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch);
llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
// get default Extension features
-unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU);
+unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
for (const char *Feature : TargetFeatures)
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D14773: [ARM] Support +feature targeting in -mcpu/-march
bsmith created this revision.
bsmith added a reviewer: rengolin.
bsmith added a subscriber: cfe-commits.
bsmith set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.
For AArch64 it is possible to specify various optional extensions by using
options such as '-mcpu=cortex-a53+crc', we would like to add the same support
to the ARM targeting to allow specifying of extensions in this manner. We use
TargetParser to do this rather than a StringSwitch to avoid hard-coding
extension names.
Repository:
rL LLVM
http://reviews.llvm.org/D14773
Files:
lib/Driver/Tools.cpp
test/Driver/arm-features.c
Index: test/Driver/arm-features.c
===
--- /dev/null
+++ test/Driver/arm-features.c
@@ -0,0 +1,7 @@
+// RUN: %clang -target arm -mcpu=generic+crc -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRC %s
+// RUN: %clang -target arm -mcpu=generic -march=armv8a+crc -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRC %s
+// CHECK-CRC: "-cc1"{{.*}} "-triple" "armv8-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "+crc"
+
+// RUN: %clang -target arm -mcpu=generic+nocrc -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRC %s
+// RUN: %clang -target arm -mcpu=generic -march=armv8a+nocrc -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRC %s
+// CHECK-NOCRC: "-cc1"{{.*}} "-triple" "armv8-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "-crc"
Index: lib/Driver/Tools.cpp
===
--- lib/Driver/Tools.cpp
+++ lib/Driver/Tools.cpp
@@ -574,23 +574,47 @@
D.Diag(diag::err_drv_clang_unsupported) << A->getAsString(Args);
}
+// Decode ARM features from string like +[no]featureA+[no]featureB+...
+static bool DecodeARMFeatures(const Driver &D, StringRef text,
+ std::vector &Features) {
+ SmallVector Split;
+ text.split(Split, StringRef("+"), -1, false);
+
+ for (StringRef Feature : Split) {
+const char *FeatureName = llvm::ARM::getArchExtFeature(Feature);
+if (FeatureName)
+ Features.push_back(FeatureName);
+else
+ return false;
+ }
+ return true;
+}
+
// Check if -march is valid by checking if it can be canonicalised and parsed.
// getARMArch is used here instead of just checking the -march value in order
// to handle -march=native correctly.
static void checkARMArchName(const Driver &D, const Arg *A, const ArgList &Args,
llvm::StringRef ArchName,
+ std::vector &Features,
const llvm::Triple &Triple) {
+ std::pair Split = ArchName.split("+");
+
std::string MArch = arm::getARMArch(ArchName, Triple);
- if (llvm::ARM::parseArch(MArch) == llvm::ARM::AK_INVALID)
+ if (llvm::ARM::parseArch(MArch) == llvm::ARM::AK_INVALID ||
+ (Split.second.size() && !DecodeARMFeatures(D, Split.second, Features)))
D.Diag(diag::err_drv_clang_unsupported) << A->getAsString(Args);
}
// Check -mcpu=. Needs ArchName to handle -mcpu=generic.
static void checkARMCPUName(const Driver &D, const Arg *A, const ArgList &Args,
llvm::StringRef CPUName, llvm::StringRef ArchName,
+std::vector &Features,
const llvm::Triple &Triple) {
+ std::pair Split = CPUName.split("+");
+
std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
- if (arm::getLLVMArchSuffixForARM(CPU, ArchName, Triple).empty())
+ if (arm::getLLVMArchSuffixForARM(CPU, ArchName, Triple).empty() ||
+ (Split.second.size() && !DecodeARMFeatures(D, Split.second, Features)))
D.Diag(diag::err_drv_clang_unsupported) << A->getAsString(Args);
}
@@ -756,12 +780,12 @@
D.Diag(clang::diag::warn_drv_unused_argument)
<< ArchArg->getAsString(Args);
ArchName = StringRef(WaArch->getValue()).substr(7);
-checkARMArchName(D, WaArch, Args, ArchName, Triple);
+checkARMArchName(D, WaArch, Args, ArchName, Features, Triple);
// FIXME: Set Arch.
D.Diag(clang::diag::warn_drv_unused_argument) << WaArch->getAsString(Args);
} else if (ArchArg) {
ArchName = ArchArg->getValue();
-checkARMArchName(D, ArchArg, Args, ArchName, Triple);
+checkARMArchName(D, ArchArg, Args, ArchName, Features, Triple);
}
// Check -mcpu. ClangAs gives preference to -Wa,-mcpu=.
@@ -772,10 +796,10 @@
D.Diag(clang::diag::warn_drv_unused_argument)
<< CPUArg->getAsString(Args);
CPUName = StringRef(WaCPU->getValue()).substr(6);
-checkARMCPUName(D, WaCPU, Args, CPUName, ArchName, Triple);
+checkARMCPUName(D, WaCPU, Args, CPUName, ArchName, Features, Triple);
} else if (CPUArg) {
CPUName = CPUArg->getValue();
-checkARMCPUName(D, CPUArg, Args, CPUName, ArchName, Triple);
+checkARMCPUName(D, CPUArg, Args, CPUName, ArchName, Features, Triple);
}
// Add CPU features
Re: [PATCH] D14773: [ARM] Support +feature targeting in -mcpu/-march
bsmith updated this revision to Diff 40515.
bsmith added a comment.
Add +crypto to testing.
Repository:
rL LLVM
http://reviews.llvm.org/D14773
Files:
lib/Driver/Tools.cpp
test/Driver/arm-features.c
Index: test/Driver/arm-features.c
===
--- /dev/null
+++ test/Driver/arm-features.c
@@ -0,0 +1,13 @@
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic+crc -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRC %s
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic -march=armv8a+crc -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRC %s
+// CHECK-CRC: "-cc1"{{.*}} "-triple" "armv8-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "+crc"
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic+crypto -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO %s
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic -march=armv8a+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO %s
+// CHECK-CRYPTO: "-cc1"{{.*}} "-triple" "armv8-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "+crypto"
+
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic+nocrc -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRC %s
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic -march=armv8a+nocrc -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRC %s
+// CHECK-NOCRC: "-cc1"{{.*}} "-triple" "armv8-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "-crc"
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic+nocrypto -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO %s
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic -march=armv8a+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO %s
+// CHECK-NOCRYPTO: "-cc1"{{.*}} "-triple" "armv8-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "-crypto"
Index: lib/Driver/Tools.cpp
===
--- lib/Driver/Tools.cpp
+++ lib/Driver/Tools.cpp
@@ -589,23 +589,47 @@
D.Diag(diag::err_drv_clang_unsupported) << A->getAsString(Args);
}
+// Decode ARM features from string like +[no]featureA+[no]featureB+...
+static bool DecodeARMFeatures(const Driver &D, StringRef text,
+ std::vector &Features) {
+ SmallVector Split;
+ text.split(Split, StringRef("+"), -1, false);
+
+ for (StringRef Feature : Split) {
+const char *FeatureName = llvm::ARM::getArchExtFeature(Feature);
+if (FeatureName)
+ Features.push_back(FeatureName);
+else
+ return false;
+ }
+ return true;
+}
+
// Check if -march is valid by checking if it can be canonicalised and parsed.
// getARMArch is used here instead of just checking the -march value in order
// to handle -march=native correctly.
static void checkARMArchName(const Driver &D, const Arg *A, const ArgList &Args,
llvm::StringRef ArchName,
+ std::vector &Features,
const llvm::Triple &Triple) {
+ std::pair Split = ArchName.split("+");
+
std::string MArch = arm::getARMArch(ArchName, Triple);
- if (llvm::ARM::parseArch(MArch) == llvm::ARM::AK_INVALID)
+ if (llvm::ARM::parseArch(MArch) == llvm::ARM::AK_INVALID ||
+ (Split.second.size() && !DecodeARMFeatures(D, Split.second, Features)))
D.Diag(diag::err_drv_clang_unsupported) << A->getAsString(Args);
}
// Check -mcpu=. Needs ArchName to handle -mcpu=generic.
static void checkARMCPUName(const Driver &D, const Arg *A, const ArgList &Args,
llvm::StringRef CPUName, llvm::StringRef ArchName,
+std::vector &Features,
const llvm::Triple &Triple) {
+ std::pair Split = CPUName.split("+");
+
std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
- if (arm::getLLVMArchSuffixForARM(CPU, ArchName, Triple).empty())
+ if (arm::getLLVMArchSuffixForARM(CPU, ArchName, Triple).empty() ||
+ (Split.second.size() && !DecodeARMFeatures(D, Split.second, Features)))
D.Diag(diag::err_drv_clang_unsupported) << A->getAsString(Args);
}
@@ -771,12 +795,12 @@
D.Diag(clang::diag::warn_drv_unused_argument)
<< ArchArg->getAsString(Args);
ArchName = StringRef(WaArch->getValue()).substr(7);
-checkARMArchName(D, WaArch, Args, ArchName, Triple);
+checkARMArchName(D, WaArch, Args, ArchName, Features, Triple);
// FIXME: Set Arch.
D.Diag(clang::diag::warn_drv_unused_argument) << WaArch->getAsString(Args);
} else if (ArchArg) {
ArchName = ArchArg->getValue();
-checkARMArchName(D, ArchArg, Args, ArchName, Triple);
+checkARMArchName(D, ArchArg, Args, ArchName, Features, Triple);
}
// Check -mcpu. ClangAs gives preference to -Wa,-mcpu=.
@@ -787,10 +811,10 @@
D.Diag(clang::diag::warn_drv_unused_argument)
<< CPUArg->getAsString(Args);
CPUName = StringRe
Re: [PATCH] D14773: [ARM] Support +feature targeting in -mcpu/-march
bsmith closed this revision. bsmith added a comment. Thanks, committed as r253471. Repository: rL LLVM http://reviews.llvm.org/D14773 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r253471 - [ARM] Support +feature targeting in -mcpu/-march
Author: brasmi01
Date: Wed Nov 18 10:33:48 2015
New Revision: 253471
URL: http://llvm.org/viewvc/llvm-project?rev=253471&view=rev
Log:
[ARM] Support +feature targeting in -mcpu/-march
Added:
cfe/trunk/test/Driver/arm-features.c (with props)
Modified:
cfe/trunk/lib/Driver/Tools.cpp
Modified: cfe/trunk/lib/Driver/Tools.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.cpp?rev=253471&r1=253470&r2=253471&view=diff
==
--- cfe/trunk/lib/Driver/Tools.cpp (original)
+++ cfe/trunk/lib/Driver/Tools.cpp Wed Nov 18 10:33:48 2015
@@ -589,23 +589,47 @@ static void getARMFPUFeatures(const Driv
D.Diag(diag::err_drv_clang_unsupported) << A->getAsString(Args);
}
+// Decode ARM features from string like +[no]featureA+[no]featureB+...
+static bool DecodeARMFeatures(const Driver &D, StringRef text,
+ std::vector &Features) {
+ SmallVector Split;
+ text.split(Split, StringRef("+"), -1, false);
+
+ for (StringRef Feature : Split) {
+const char *FeatureName = llvm::ARM::getArchExtFeature(Feature);
+if (FeatureName)
+ Features.push_back(FeatureName);
+else
+ return false;
+ }
+ return true;
+}
+
// Check if -march is valid by checking if it can be canonicalised and parsed.
// getARMArch is used here instead of just checking the -march value in order
// to handle -march=native correctly.
static void checkARMArchName(const Driver &D, const Arg *A, const ArgList
&Args,
llvm::StringRef ArchName,
+ std::vector &Features,
const llvm::Triple &Triple) {
+ std::pair Split = ArchName.split("+");
+
std::string MArch = arm::getARMArch(ArchName, Triple);
- if (llvm::ARM::parseArch(MArch) == llvm::ARM::AK_INVALID)
+ if (llvm::ARM::parseArch(MArch) == llvm::ARM::AK_INVALID ||
+ (Split.second.size() && !DecodeARMFeatures(D, Split.second, Features)))
D.Diag(diag::err_drv_clang_unsupported) << A->getAsString(Args);
}
// Check -mcpu=. Needs ArchName to handle -mcpu=generic.
static void checkARMCPUName(const Driver &D, const Arg *A, const ArgList &Args,
llvm::StringRef CPUName, llvm::StringRef ArchName,
+std::vector &Features,
const llvm::Triple &Triple) {
+ std::pair Split = CPUName.split("+");
+
std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
- if (arm::getLLVMArchSuffixForARM(CPU, ArchName, Triple).empty())
+ if (arm::getLLVMArchSuffixForARM(CPU, ArchName, Triple).empty() ||
+ (Split.second.size() && !DecodeARMFeatures(D, Split.second, Features)))
D.Diag(diag::err_drv_clang_unsupported) << A->getAsString(Args);
}
@@ -771,12 +795,12 @@ static void getARMTargetFeatures(const T
D.Diag(clang::diag::warn_drv_unused_argument)
<< ArchArg->getAsString(Args);
ArchName = StringRef(WaArch->getValue()).substr(7);
-checkARMArchName(D, WaArch, Args, ArchName, Triple);
+checkARMArchName(D, WaArch, Args, ArchName, Features, Triple);
// FIXME: Set Arch.
D.Diag(clang::diag::warn_drv_unused_argument) << WaArch->getAsString(Args);
} else if (ArchArg) {
ArchName = ArchArg->getValue();
-checkARMArchName(D, ArchArg, Args, ArchName, Triple);
+checkARMArchName(D, ArchArg, Args, ArchName, Features, Triple);
}
// Check -mcpu. ClangAs gives preference to -Wa,-mcpu=.
@@ -787,10 +811,10 @@ static void getARMTargetFeatures(const T
D.Diag(clang::diag::warn_drv_unused_argument)
<< CPUArg->getAsString(Args);
CPUName = StringRef(WaCPU->getValue()).substr(6);
-checkARMCPUName(D, WaCPU, Args, CPUName, ArchName, Triple);
+checkARMCPUName(D, WaCPU, Args, CPUName, ArchName, Features, Triple);
} else if (CPUArg) {
CPUName = CPUArg->getValue();
-checkARMCPUName(D, CPUArg, Args, CPUName, ArchName, Triple);
+checkARMCPUName(D, CPUArg, Args, CPUName, ArchName, Features, Triple);
}
// Add CPU features for generic CPUs
@@ -6274,7 +6298,7 @@ const std::string arm::getARMArch(String
MArch = Arch;
else
MArch = Triple.getArchName();
- MArch = StringRef(MArch).lower();
+ MArch = StringRef(MArch).split("+").first.lower();
// Handle -march=native.
if (MArch == "native") {
@@ -6313,7 +6337,7 @@ std::string arm::getARMTargetCPU(StringR
// FIXME: Warn on inconsistent use of -mcpu and -march.
// If we have -mcpu=, use that.
if (!CPU.empty()) {
-std::string MCPU = StringRef(CPU).lower();
+std::string MCPU = StringRef(CPU).split("+").first.lower();
// Handle -mcpu=native.
if (MCPU == "native")
return llvm::sys::getHostCPUName();
Added: cfe/trunk/test/Driver/arm-features.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-features.c?rev=253471&view=auto
Re: [PATCH] D15040: [ARM] Add command-line options for ARMv8.2-A
bsmith added a subscriber: bsmith.
Comment at: lib/Driver/Tools.cpp:868-876
@@ -867,4 +867,11 @@
- if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v8_1a) {
+ switch (Triple.getSubArch()) {
+ case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
Features.insert(Features.begin(), "+v8.1a");
+break;
+ case llvm::Triple::SubArchType::ARMSubArch_v8_2a:
+Features.insert(Features.begin(), "+v8.2a");
+break;
+ default:
+break;
}
Now that -mcpu=generic works correctly and isn't hardcoded to ARMv8.1-A, I
don't believe we need this hardcoded logic to add these features.
Repository:
rL LLVM
http://reviews.llvm.org/D15040
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D15283: [ARMv8-M] Add Clang targeting for ARMv8-M Baseline/Mainline
bsmith created this revision.
bsmith added a reviewer: t.p.northover.
bsmith added a subscriber: cfe-commits.
bsmith set the repository for this revision to rL LLVM.
Herald added subscribers: rengolin, aemerson.
This patch forms part of the ARMv8-M Baseline/Mainline support, adding Clang
targeting for ARMv8-M Baseline/Mainline.
ARMv8-M Mainline is a superset of ARMv7-M, containing all ARMv7-M instructions
plus ARMv8-A semaphores and atomics and the ARMv8-M security extensions.
ARMv8-M Baseline is a superset of ARMv6-M, containing all ARMv6-M instructions
plus ARMv8-A semaphores and atomics, ARMv7-M exclusives, various code
optimization instructions (wide branches, CBZ, hardware divide), MOVW/MOVT and
the ARMv8-M security extensions.
Repository:
rL LLVM
http://reviews.llvm.org/D15283
Files:
lib/Basic/Targets.cpp
lib/Driver/ToolChain.cpp
lib/Driver/Tools.cpp
test/Driver/arm-alignment.c
test/Driver/arm-cortex-cpus.c
test/Driver/arm-features.c
test/Preprocessor/arm-target-features.c
Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -95,6 +95,43 @@
// THUMBV8A-EABI:#define __ARM_ARCH_EXT_IDIV__ 1
// THUMBV8A-EABI: #define __ARM_FP 0xE
+// RUN: %clang -target armv8m.base-none-linux-gnu -x c -E -dM %s -o - | FileCheck --check-prefix=V8M_BASELINE %s
+// V8M_BASELINE: __ARM_ARCH 8
+// V8M_BASELINE: __ARM_ARCH_8M__ 1
+// V8M_BASELINE: __ARM_ARCH_EXT_IDIV__ 1
+// V8M_BASELINE-NOT: __ARM_ARCH_ISA_ARM
+// FIXME: ABI-85 might change __ARM_ARCH_ISA_THUMB
+// V8M_BASELINE: __ARM_ARCH_ISA_THUMB 1
+// V8M_BASELINE: __ARM_ARCH_PROFILE 'B'
+// V8M_BASELINE-NOT: __ARM_FEATURE_CRC32
+// V8M_BASELINE-NOT: __ARM_FEATURE_DSP
+// V8M_BASELINE-NOT: __ARM_FP 0x{{.*}}
+// V8M_BASELINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+
+// RUN: %clang -target armv8m.main-none-linux-gnu -x c -E -dM %s -o - | FileCheck --check-prefix=V8M_MAINLINE %s
+// V8M_MAINLINE: __ARM_ARCH 8
+// V8M_MAINLINE: __ARM_ARCH_8M__ 1
+// V8M_MAINLINE: __ARM_ARCH_EXT_IDIV__ 1
+// V8M_MAINLINE-NOT: __ARM_ARCH_ISA_ARM
+// V8M_MAINLINE: __ARM_ARCH_ISA_THUMB 2
+// V8M_MAINLINE: __ARM_ARCH_PROFILE 'M'
+// V8M_MAINLINE-NOT: __ARM_FEATURE_CRC32
+// V8M_MAINLINE-NOT: __ARM_FEATURE_DSP
+// V8M_MAINLINE: __ARM_FP 0xE
+// V8M_MAINLINE: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+
+// RUN: %clang -target arm-none-linux-gnu -march=armv8-m.main+dsp -x c -E -dM %s -o - | FileCheck --check-prefix=V8M_MAINLINE_DSP %s
+// V8M_MAINLINE_DSP: __ARM_ARCH 8
+// V8M_MAINLINE_DSP: __ARM_ARCH_8M__ 1
+// V8M_MAINLINE_DSP: __ARM_ARCH_EXT_IDIV__ 1
+// V8M_MAINLINE_DSP-NOT: __ARM_ARCH_ISA_ARM
+// V8M_MAINLINE_DSP: __ARM_ARCH_ISA_THUMB 2
+// V8M_MAINLINE_DSP: __ARM_ARCH_PROFILE 'M'
+// V8M_MAINLINE_DSP-NOT: __ARM_FEATURE_CRC32
+// V8M_MAINLINE_DSP: __ARM_FEATURE_DSP 1
+// V8M_MAINLINE_DSP: __ARM_FP 0xE
+// V8M_MAINLINE_DSP: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+
// RUN: %clang -target arm-none-linux-gnu -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-DEFS %s
// CHECK-DEFS:#define __ARM_PCS 1
// CHECK-DEFS:#define __ARM_SIZEOF_MINIMAL_ENUM 4
Index: test/Driver/arm-features.c
===
--- test/Driver/arm-features.c
+++ test/Driver/arm-features.c
@@ -4,6 +4,9 @@
// RUN: %clang -target arm-none-none-eabi -mcpu=generic+crypto -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO %s
// RUN: %clang -target arm-none-none-eabi -mcpu=generic -march=armv8a+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO %s
// CHECK-CRYPTO: "-cc1"{{.*}} "-triple" "armv8-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "+crypto"
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic+dsp -march=armv8m.main -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-DSP %s
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic -march=armv8m.main+dsp -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-DSP %s
+// CHECK-DSP: "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "+dsp"
// RUN: %clang -target arm-none-none-eabi -mcpu=generic+nocrc -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRC %s
// RUN: %clang -target arm-none-none-eabi -mcpu=generic -march=armv8a+nocrc -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRC %s
@@ -11,3 +14,6 @@
// RUN: %clang -target arm-none-none-eabi -mcpu=generic+nocrypto -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO %s
// RUN: %clang -target arm-none-none-eabi -mcpu=generic -march=armv8a+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO %s
// CHECK-NOCRYPTO: "-cc1"{{.*}} "-triple" "armv8-{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "-crypto"
+// RUN: %clang -target arm-none-none-eabi -mcpu=generic+nodsp -march=armv8m.main -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NODSP %s
+// RUN: %clang -target arm-none
[clang] cf0da91 - [AArch64][SVE/NEON] Add support for FROUNDEVEN for both NEON and fixed length SVE
Author: Bradley Smith
Date: 2021-03-17T11:41:22Z
New Revision: cf0da91ba5e192920809e30dbb359042c2f2112a
URL:
https://github.com/llvm/llvm-project/commit/cf0da91ba5e192920809e30dbb359042c2f2112a
DIFF:
https://github.com/llvm/llvm-project/commit/cf0da91ba5e192920809e30dbb359042c2f2112a.diff
LOG: [AArch64][SVE/NEON] Add support for FROUNDEVEN for both NEON and fixed
length SVE
Previously NEON used a target specific intrinsic for frintn, given that
the FROUNDEVEN ISD node now exists, move over to that instead and add
codegen support for that node for both NEON and fixed length SVE.
Differential Revision: https://reviews.llvm.org/D98487
Added:
llvm/test/CodeGen/AArch64/frintn.ll
Modified:
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/aarch64-neon-intrinsics.c
clang/test/CodeGen/aarch64-neon-misc.c
clang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics.c
clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c
clang/test/CodeGen/arm-neon-directed-rounding.c
clang/test/CodeGen/arm64-vrnd.c
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/include/llvm/Target/TargetSelectionDAG.td
llvm/lib/IR/AutoUpgrade.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/arm64-vcvt.ll
llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll
llvm/test/CodeGen/AArch64/f16-instructions.ll
llvm/test/CodeGen/AArch64/fp-intrinsics.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll
llvm/test/CodeGen/AArch64/vec-libcalls.ll
Removed:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index e5778c0c78f7..8d1d3c50870c 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -10620,17 +10620,23 @@ Value
*CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
}
case NEON::BI__builtin_neon_vrndnh_f16: {
Ops.push_back(EmitScalarExpr(E->getArg(0)));
-Int = Intrinsic::aarch64_neon_frintn;
+Int = Builder.getIsFPConstrained()
+ ? Intrinsic::experimental_constrained_roundeven
+ : Intrinsic::roundeven;
return EmitNeonCall(CGM.getIntrinsic(Int, HalfTy), Ops, "vrndn");
}
case NEON::BI__builtin_neon_vrndn_v:
case NEON::BI__builtin_neon_vrndnq_v: {
-Int = Intrinsic::aarch64_neon_frintn;
+Int = Builder.getIsFPConstrained()
+ ? Intrinsic::experimental_constrained_roundeven
+ : Intrinsic::roundeven;
return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrndn");
}
case NEON::BI__builtin_neon_vrndns_f32: {
Ops.push_back(EmitScalarExpr(E->getArg(0)));
-Int = Intrinsic::aarch64_neon_frintn;
+Int = Builder.getIsFPConstrained()
+ ? Intrinsic::experimental_constrained_roundeven
+ : Intrinsic::roundeven;
return EmitNeonCall(CGM.getIntrinsic(Int, FloatTy), Ops, "vrndn");
}
case NEON::BI__builtin_neon_vrndph_f16: {
diff --git a/clang/test/CodeGen/aarch64-neon-intrinsics.c
b/clang/test/CodeGen/aarch64-neon-intrinsics.c
index a56080bace0f..76f5cfd3aaa8 100644
--- a/clang/test/CodeGen/aarch64-neon-intrinsics.c
+++ b/clang/test/CodeGen/aarch64-neon-intrinsics.c
@@ -18155,7 +18155,7 @@ float64x1_t test_vcvt_n_f64_u64(uint64x1_t a) {
// CHECK-LABEL: @test_vrndn_f64(
// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
-// CHECK: [[VRNDN1_I:%.*]] = call <1 x double>
@llvm.aarch64.neon.frintn.v1f64(<1 x double> %a)
+// CHECK: [[VRNDN1_I:%.*]] = call <1 x double> @llvm.roundeven.v1f64(<1 x
double> %a)
// CHECK: ret <1 x double> [[VRNDN1_I]]
float64x1_t test_vrndn_f64(float64x1_t a) {
return vrndn_f64(a);
diff --git a/clang/test/CodeGen/aarch64-neon-misc.c
b/clang/test/CodeGen/aarch64-neon-misc.c
index 4f85f67cdaec..ed9af88b56c1 100644
--- a/clang/test/CodeGen/aarch64-neon-misc.c
+++ b/clang/test/CodeGen/aarch64-neon-misc.c
@@ -2287,7 +2287,7 @@ float64x2_t test_vcvt_high_f64_f32(float32x4_t a) {
// CHECK-LABEL: @test_vrndnq_f64(
// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
-// CHECK: [[VRNDN1_I:%.*]] = call <2 x double>
@llvm.aarch64.neon.frintn.v2f64(<2 x double> %a)
+// CHECK: [[VRNDN1_I:%.*]] = call <2 x double> @llvm.roundeven.v2f64(<2 x
double> %a)
// CHECK: ret <2 x double> [[VRNDN1_I]]
float64x2_t test_vrndnq_f64(float64x2_t a) {
return vrndnq_f64(a);
diff --git a/clang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics.c
b/clang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics.c
index 32161146ef45..01df5b0d1930 100644
--- a/clang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics.c
+++ b/clang/test/CodeGen/aarch64-v8.2a-fp16-intrinsics.c
@@ -366,7 +366,7 @@ float16_t test_vrndmh_f16(float16_t a) {
}
// CHECK-LABEL: test_vrndnh_f16
-// CHECK: [[RND:%.*]] = call half @llvm.aarch64.neon.frintn.f16(half %a)
+// CHECK: [[RND:%.*]] = call half @llvm.roundeven.f16(ha
[clang] 48f5a39 - [IR] Add vscale_range IR function attribute
Author: Bradley Smith
Date: 2021-03-22T12:05:06Z
New Revision: 48f5a392cb73d99a58f01448926f6964ab5b0d0a
URL:
https://github.com/llvm/llvm-project/commit/48f5a392cb73d99a58f01448926f6964ab5b0d0a
DIFF:
https://github.com/llvm/llvm-project/commit/48f5a392cb73d99a58f01448926f6964ab5b0d0a.diff
LOG: [IR] Add vscale_range IR function attribute
This attribute represents the minimum and maximum values vscale can
take. For now this attribute is not hooked up to anything during
codegen, this will be added in the future when such codegen is
considered stable.
Additionally hook up the -msve-vector-bits= clang option to emit this
attribute.
Differential Revision: https://reviews.llvm.org/D98030
Added:
clang/test/CodeGen/arm-sve-vector-bits-vscale-range.c
llvm/test/Verifier/vscale_range.ll
Modified:
clang/lib/CodeGen/CodeGenFunction.cpp
llvm/docs/BitCodeFormat.rst
llvm/docs/LangRef.rst
llvm/include/llvm/Bitcode/LLVMBitCodes.h
llvm/include/llvm/IR/Attributes.h
llvm/include/llvm/IR/Attributes.td
llvm/lib/AsmParser/LLLexer.cpp
llvm/lib/AsmParser/LLParser.cpp
llvm/lib/AsmParser/LLParser.h
llvm/lib/AsmParser/LLToken.h
llvm/lib/Bitcode/Reader/BitcodeReader.cpp
llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
llvm/lib/IR/AttributeImpl.h
llvm/lib/IR/Attributes.cpp
llvm/lib/IR/Verifier.cpp
llvm/lib/Transforms/IPO/ForceFunctionAttrs.cpp
llvm/lib/Transforms/Utils/CodeExtractor.cpp
llvm/test/Bitcode/attributes.ll
Removed:
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp
b/clang/lib/CodeGen/CodeGenFunction.cpp
index fd708849e609..e3fdf54716ab 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -496,6 +496,13 @@ void CodeGenFunction::FinishFunction(SourceLocation
EndLoc) {
if (LargestVectorWidth)
CurFn->addFnAttr("min-legal-vector-width",
llvm::utostr(LargestVectorWidth));
+ // Add vscale attribute if appropriate.
+ if (getLangOpts().ArmSveVectorBits) {
+unsigned VScale = getLangOpts().ArmSveVectorBits / 128;
+CurFn->addFnAttr(llvm::Attribute::getWithVScaleRangeArgs(getLLVMContext(),
+ VScale, VScale));
+ }
+
// If we generated an unreachable return block, delete it now.
if (ReturnBlock.isValid() && ReturnBlock.getBlock()->use_empty()) {
Builder.ClearInsertionPoint();
diff --git a/clang/test/CodeGen/arm-sve-vector-bits-vscale-range.c
b/clang/test/CodeGen/arm-sve-vector-bits-vscale-range.c
new file mode 100644
index ..84541f9cb12d
--- /dev/null
+++ b/clang/test/CodeGen/arm-sve-vector-bits-vscale-range.c
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-msve-vector-bits=128 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=128
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-msve-vector-bits=256 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=256
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-msve-vector-bits=512 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=512
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-msve-vector-bits=1024 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=1024
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-msve-vector-bits=2048 -S -emit-llvm -o - %s | FileCheck %s -D#VBITS=2048
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve
-msve-vector-bits=scalable -S -emit-llvm -o - %s | FileCheck %s
--check-prefix=CHECK-NONE
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-NONE
+
+// CHECK-LABEL: @func() #0
+// CHECK: attributes #0 = { {{.*}}
vscale_range([[#div(VBITS,128)]],[[#div(VBITS,128)]]) {{.*}} }
+// CHECK-NONE-NOT: vscale_range
+void func() {}
diff --git a/llvm/docs/BitCodeFormat.rst b/llvm/docs/BitCodeFormat.rst
index df0e195c6809..eff9d2866a8f 100644
--- a/llvm/docs/BitCodeFormat.rst
+++ b/llvm/docs/BitCodeFormat.rst
@@ -1070,6 +1070,7 @@ The integer codes are mapped to well-known attributes as
follows.
* code 68: ``noundef``
* code 69: ``byref``
* code 70: ``mustprogress``
+* code 74: ``vscale_range([, ])``
.. note::
The ``allocsize`` attribute has a special encoding for its arguments. Its two
@@ -1077,6 +1078,12 @@ The integer codes are mapped to well-known attributes as
follows.
(i.e. ``(EltSizeParam << 32) | NumEltsParam``), with ``NumEltsParam`` taking
on
the sentinel value -1 if it is not specified.
+.. note::
+ The ``vscale_range`` attribute has a special encoding for its arguments. Its
two
+ arguments, which are 32-bit integers, are packed into one 64-bit integer
value
+ (i.e. ``(Min << 32) | Max``), with ``Max`` taking on the value of ``Min`` if
+ it is not specified.
+
.. _TYPE_BLOCK:
TYPE_BLOCK Contents
[clang] 0ce46a1 - [AArch64][Driver][SVE] Allow -msve-vector-bits=+ syntax to mean no maximum vscale
Author: Bradley Smith
Date: 2021-10-25T11:10:52Z
New Revision: 0ce46a1d43c6c2e0df429a6a80848d4acc781eb6
URL:
https://github.com/llvm/llvm-project/commit/0ce46a1d43c6c2e0df429a6a80848d4acc781eb6
DIFF:
https://github.com/llvm/llvm-project/commit/0ce46a1d43c6c2e0df429a6a80848d4acc781eb6.diff
LOG: [AArch64][Driver][SVE] Allow -msve-vector-bits=+ syntax to mean no
maximum vscale
This patch splits the existing SveVectorBits LangOpt into VScaleMin and
VScaleMax LangOpts such that we can represent such an option. The cc1
option has also been split into -mvscale-{min,max}= options so that the
cc1 arguments better reflect the vscale_range IR attribute.
Differential Revision: https://reviews.llvm.org/D111790
Added:
Modified:
clang/include/clang/Basic/LangOptions.def
clang/include/clang/Driver/Options.td
clang/lib/AST/ASTContext.cpp
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Sema/SemaType.cpp
clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
clang/test/CodeGen/aarch64-sve-vector-bits-codegen.c
clang/test/CodeGen/arm-sve-vector-bits-vscale-range.c
clang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
clang/test/CodeGen/attr-arm-sve-vector-bits-codegen.c
clang/test/CodeGen/attr-arm-sve-vector-bits-globals.c
clang/test/CodeGen/attr-arm-sve-vector-bits-types.c
clang/test/CodeGenCXX/aarch64-mangle-sve-fixed-vectors.cpp
clang/test/CodeGenCXX/aarch64-sve-fixedtypeinfo.cpp
clang/test/Driver/aarch64-sve-vector-bits.c
clang/test/Preprocessor/aarch64-target-features.c
clang/test/Sema/aarch64-sve-explicit-casts-fixed-size.c
clang/test/Sema/aarch64-sve-lax-vector-conversions.c
clang/test/Sema/attr-arm-sve-vector-bits.c
clang/test/SemaCXX/aarch64-sve-explicit-casts-fixed-size.cpp
clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp
clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
Removed:
diff --git a/clang/include/clang/Basic/LangOptions.def
b/clang/include/clang/Basic/LangOptions.def
index 912fd0ec18961..4651f4fff6aa0 100644
--- a/clang/include/clang/Basic/LangOptions.def
+++ b/clang/include/clang/Basic/LangOptions.def
@@ -425,7 +425,8 @@ LANGOPT(SpeculativeLoadHardening, 1, 0, "Speculative load
hardening enabled")
LANGOPT(RelativeCXXABIVTables, 1, 0,
"Use an ABI-incompatible v-table layout that uses relative references")
-LANGOPT(ArmSveVectorBits, 32, 0, "SVE vector size in bits")
+LANGOPT(VScaleMin, 32, 0, "Minimum vscale value")
+LANGOPT(VScaleMax, 32, 0, "Maximum vscale value")
ENUM_LANGOPT(ExtendIntArgs, ExtendArgsKind, 1, ExtendArgsKind::ExtendTo32,
"Controls how scalar integer arguments are extended in calls "
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 25f3ddd97f12a..b4a2411fa5c5c 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -3331,13 +3331,20 @@ foreach i = {8-15,18} in
def fcall_saved_x#i : Flag<["-"], "fcall-saved-x"#i>,
Group,
HelpText<"Make the x"#i#" register call-saved (AArch64 only)">;
-def msve_vector_bits_EQ : Joined<["-"], "msve-vector-bits=">,
- Group, Flags<[NoXarchOption,CC1Option]>,
+def msve_vector_bits_EQ : Joined<["-"], "msve-vector-bits=">,
Group,
HelpText<"Specify the size in bits of an SVE vector register. Defaults to
the"
- " vector length agnostic value of \"scalable\". (AArch64 only)">,
- Values<"128,256,512,1024,2048,scalable">,
- NormalizedValues<["128", "256", "512", "1024", "2048", "0"]>,
- MarshallingInfoEnum, "0">;
+ " vector length agnostic value of \"scalable\". (AArch64 only)">;
+
+def mvscale_min_EQ : Joined<["-"], "mvscale-min=">,
+ Group, Flags<[NoXarchOption,CC1Option]>,
+ HelpText<"Specify the vscale minimum. Defaults to the"
+ " vector length agnostic value of \"0\". (AArch64 only)">,
+ MarshallingInfoInt>;
+def mvscale_max_EQ : Joined<["-"], "mvscale-max=">,
+ Group, Flags<[NoXarchOption,CC1Option]>,
+ HelpText<"Specify the vscale maximum. Defaults to the"
+ " vector length agnostic value of \"0\". (AArch64 only)">,
+ MarshallingInfoInt>;
def msign_return_address_EQ : Joined<["-"], "msign-return-address=">,
Flags<[CC1Option]>, Group, Values<"none,all,non-leaf">,
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 84b09dcf16a0e..796a737b8c6dd 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -8768,8 +8768,8 @@ bool ASTContext::areCompatibleVectorTypes(QualType
FirstVec,
static uint64_t getSVETypeSize(ASTContext &Context, const BuiltinType *Ty) {
assert(Ty->isVLSTBui
