from:"Amy Kwan via cfe\-commits"

[clang] fc55308 - [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.

2020-07-15 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2020-07-16T00:30:24-05:00
New Revision: fc55308628709bfc64b100dadf9a030fbb2afaee

URL: 
https://github.com/llvm/llvm-project/commit/fc55308628709bfc64b100dadf9a030fbb2afaee
DIFF: 
https://github.com/llvm/llvm-project/commit/fc55308628709bfc64b100dadf9a030fbb2afaee.diff

LOG: [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions 
to have i32 arguments.

Previously, the vins* intrinsic was incorrectly defined to have its second and
third argument arguments as an i64. This patch fixes the second and third
argument of the vins* instruction and intrinsic to have i32s instead.

Differential Revision: https://reviews.llvm.org/D83497

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 6b291e6b0806..5d445c253a85 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -321,12 +321,12 @@ BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "")
 BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "")
 
 // P10 Vector Insert built-ins.
-BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcULLiULLi", "")
-BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcULLiULLi", "")
-BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsULLiULLi", "")
-BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsULLiULLi", "")
-BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiULLiULLi", "")
-BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcUiUi", "")
+BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcUiUi", "")
+BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsUiUi", "")
+BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsUiUi", "")
+BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiUiUi", "")
+BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiUiUi", "")
 BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "")
 BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "")
 BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcULLiV16Uc", "")

diff  --git a/clang/test/CodeGen/builtins-ppc-p10vector.c 
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index c51c24f25986..4e804fbafb30 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -402,25 +402,25 @@ vector double test_vec_blend_d(void) {
 }
 
 vector unsigned char test_vec_insertl_uc(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
+  // CHECK-BE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32
   // CHECK-BE-NEXT: ret <16 x i8>
-  // CHECK-LE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
+  // CHECK-LE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32
   // CHECK-LE-NEXT: ret <16 x i8>
   return vec_insertl(uca, vuca, uia);
 }
 
 vector unsigned short test_vec_insertl_us(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
+  // CHECK-BE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32
   // CHECK-BE-NEXT: ret <8 x i16>
-  // CHECK-LE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
+  // CHECK-LE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32
   // CHECK-LE-NEXT: ret <8 x i16>
   return vec_insertl(usa, vusa, uia);
 }
 
 vector unsigned int test_vec_insertl_ui(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
+  // CHECK-BE: @llvm.ppc.altivec.vinswlx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32
   // CHECK-BE-NEXT: ret <4 x i32>
-  // CHECK-LE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i64 %{{.+}}, i64
+  // CHECK-LE: @llvm.ppc.altivec.vinswrx(<4 x i32> %{{.+}}, i32 %{{.+}}, i32
   // CHECK-LE-NEXT: ret <4 x i32>
   return vec_insertl(uib, vuia, uia);
 }
@@ -458,25 +458,25 @@ vector unsigned int test_vec_insertl_uiv(void) {
 }
 
 vector unsigned char test_vec_inserth_uc(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
+  // CHECK-BE: @llvm.ppc.altivec.vinsbrx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32
   // CHECK-BE-NEXT: ret <16 x i8>
-  // CHECK-LE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i64 %{{.+}}, i64
+  // CHECK-LE: @llvm.ppc.altivec.vinsblx(<16 x i8> %{{.+}}, i32 %{{.+}}, i32
   // CHECK-LE-NEXT: ret <16 x i8>
   return vec_inserth(uca, vuca, uia);
 }
 
 vector unsigned short test_vec_inserth_us(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
+  // CHECK-BE: @llvm.ppc.altivec.vinshrx(<8 x i16> %{{.+}}, i32 %{{.+}}, i32
   // CHECK-BE-NEXT: ret <8 x i16>
-  // CHECK-LE: @llvm.ppc.altivec.vinshlx(<8 x i16> %{{.+}}, i64 %{{.+}}, i64
+  // CHECK-LE: @llvm.ppc.altivec.v

[clang] 08b4a50 - [PowerPC][Power10] Fix the Test LSB by Byte (xvtlsbb) Builtins Implementation

2020-07-22 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2020-07-22T13:27:05-05:00
New Revision: 08b4a50e39d8b8db17b8eddacba795e99304e418

URL: 
https://github.com/llvm/llvm-project/commit/08b4a50e39d8b8db17b8eddacba795e99304e418
DIFF: 
https://github.com/llvm/llvm-project/commit/08b4a50e39d8b8db17b8eddacba795e99304e418.diff

LOG: [PowerPC][Power10] Fix the Test LSB by Byte (xvtlsbb) Builtins 
Implementation

The implementation of the xvtlsbb builtins/intrinsics were not correct as the
intrinsics previously used i1 as an argument type. This patch changes the i1
argument type used in these intrinsics to be i32 instead, as having the second
as an i1 can lead to issues in the backend.

Differential Revision: https://reviews.llvm.org/D84291

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 5d445c253a85..b74cb8df78ba 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -467,7 +467,7 @@ BUILTIN(__builtin_vsx_xxsldwi, "v.", "t")
 
 BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "")
 
-BUILTIN(__builtin_vsx_xvtlsbb, "iV16Ucb", "")
+BUILTIN(__builtin_vsx_xvtlsbb, "iV16UcUi", "")
 
 // P10 Vector Permute Extended built-in.
 BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi", "")

diff  --git a/clang/test/CodeGen/builtins-ppc-p10vector.c 
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index 4e804fbafb30..0d084c6eed85 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -583,13 +583,13 @@ vector float test_vec_vec_splati_ins_f(void) {
 }
 
 int test_vec_test_lsbb_all_ones(void) {
-  // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i1 true
+  // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i32 1
   // CHECK-NEXT: ret i32
   return vec_test_lsbb_all_ones(vuca);
 }
 
 int test_vec_test_lsbb_all_zeros(void) {
-  // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i1 false
+  // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i32 0
   // CHECK-NEXT: ret i32
   return vec_test_lsbb_all_zeros(vuca);
 }

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 2abb6b4e55fe..d2d418bc2d64 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1069,7 +1069,7 @@ def int_ppc_vsx_xxinsertw :
 [IntrNoMem]>;
 def int_ppc_vsx_xvtlsbb :
   PowerPC_VSX_Intrinsic<"xvtlsbb", [llvm_i32_ty],
-[llvm_v16i8_ty, llvm_i1_ty], [IntrNoMem]>;
+[llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xxeval :
   PowerPC_VSX_Intrinsic<"xxeval", [llvm_v2i64_ty],
[llvm_v2i64_ty, llvm_v2i64_ty,

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td 
b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 6bf8475a7947..4c9f9e8bb083 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1085,7 +1085,7 @@ let Predicates = [IsISA3_1] in {
 (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
 (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
-  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, -1)),
+  def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)),
 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
   def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
 (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;

diff  --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll 
b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
index d4e71d18c6eb..2ac1b2b7514b 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
@@ -2,11 +2,14 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O0 \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
 
 ; These test cases aims to test the builtins for the Power10 VSX vector
 ; instructions introduced in ISA 3.1.
 
-declare i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8>, i1)
+declare i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8>, i32)
 
 define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> %vuca) {
 ; CHECK-LABEL: test_vec_test_lsbb_all_ones:
@@ -17,7 +20,7 @@ define signext i32 @test_vec_test_lsbb_all_

[clang] 5f11027 - [PowerPC][Power10] Fix vins*vlx instructions to have i32 arguments.

2020-07-22 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2020-07-22T17:58:14-05:00
New Revision: 5f110273954ac152c9690b6cdf2a2e46f8908f0a

URL: 
https://github.com/llvm/llvm-project/commit/5f110273954ac152c9690b6cdf2a2e46f8908f0a
DIFF: 
https://github.com/llvm/llvm-project/commit/5f110273954ac152c9690b6cdf2a2e46f8908f0a.diff

LOG: [PowerPC][Power10] Fix vins*vlx instructions to have i32 arguments.

Previously, the vins*vlx instructions were incorrectly defined with i64 as the
second argument. This patches fixes this issue by correcting the second argument
of the vins*vlx instructions/intrinsics to be i32.

Differential Revision: https://reviews.llvm.org/D84277

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index b74cb8df78ba..5aed03f74f65 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -329,12 +329,12 @@ BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiUiUi", "")
 BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiUiUi", "")
 BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "")
 BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "")
-BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcULLiV16Uc", "")
-BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcULLiV16Uc", "")
-BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsULLiV8Us", "")
-BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsULLiV8Us", "")
-BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiULLiV4Ui", "")
-BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiULLiV4Ui", "")
+BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcUiV16Uc", "")
+BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcUiV16Uc", "")
+BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsUiV8Us", "")
+BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsUiV8Us", "")
+BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiUiV4Ui", "")
+BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiUiV4Ui", "")
 
 // VSX built-ins.
 

diff  --git a/clang/test/CodeGen/builtins-ppc-p10vector.c 
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index 0d084c6eed85..6f38ac77ee24 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -434,25 +434,25 @@ vector unsigned long long test_vec_insertl_ul(void) {
 }
 
 vector unsigned char test_vec_insertl_ucv(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 
x i8>
+  // CHECK-BE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 
x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
-  // CHECK-LE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 
x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 
x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
   return vec_insertl(vuca, vucb, uia);
 }
 
 vector unsigned short test_vec_insertl_usv(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x 
i16>
+  // CHECK-BE: @llvm.ppc.altivec.vinshvlx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x 
i16>
   // CHECK-BE-NEXT: ret <8 x i16>
-  // CHECK-LE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x 
i16>
+  // CHECK-LE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x 
i16>
   // CHECK-LE-NEXT: ret <8 x i16>
   return vec_insertl(vusa, vusb, uia);
 }
 
 vector unsigned int test_vec_insertl_uiv(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x 
i32>
+  // CHECK-BE: @llvm.ppc.altivec.vinswvlx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x 
i32>
   // CHECK-BE-NEXT: ret <4 x i32>
-  // CHECK-LE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i64 %{{.+}}, <4 x 
i32>
+  // CHECK-LE: @llvm.ppc.altivec.vinswvrx(<4 x i32> %{{.+}}, i32 %{{.+}}, <4 x 
i32>
   // CHECK-LE-NEXT: ret <4 x i32>
   return vec_insertl(vuia, vuib, uia);
 }
@@ -490,25 +490,25 @@ vector unsigned long long test_vec_inserth_ul(void) {
 }
 
 vector unsigned char test_vec_inserth_ucv(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 
x i8>
+  // CHECK-BE: @llvm.ppc.altivec.vinsbvrx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 
x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
-  // CHECK-LE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i64 %{{.+}}, <16 
x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vinsbvlx(<16 x i8> %{{.+}}, i32 %{{.+}}, <16 
x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
   return vec_inserth(vuca, vucb, uia);
 }
 
 vector unsigned short test_vec_inserth_usv(void) {
-  // CHECK-BE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i64 %{{.+}}, <8 x 
i16>
+  // CHECK-BE: @llvm.ppc.altivec.vinshvrx(<8 x i16> %{{.+}}, i32 %{{.+}}, <8 x 
i16>
   // CHECK-BE-NEXT: ret <8 x i16>
-  // CHECK-LE: @llvm.ppc.altivec.vin

[clang] 74790a5 - [PowerPC] Implement Truncate and Store VSX Vector Builtins

2020-07-24 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2020-07-24T19:22:39-05:00
New Revision: 74790a5dde9ae01b7e96bea0b2596ef37b5325bd

URL: 
https://github.com/llvm/llvm-project/commit/74790a5dde9ae01b7e96bea0b2596ef37b5325bd
DIFF: 
https://github.com/llvm/llvm-project/commit/74790a5dde9ae01b7e96bea0b2596ef37b5325bd.diff

LOG: [PowerPC] Implement Truncate and Store VSX Vector Builtins

This patch implements the `vec_xst_trunc` function in altivec.h in  order to
utilize the Store VSX Vector Rightmost [byte | half | word | doubleword] Indexed
instructions introduced in Power10.

Differential Revision: https://reviews.llvm.org/D82467

Added: 


Modified: 
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll

Removed: 




diff  --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index ac5f43836316..4e25ec118072 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16597,6 +16597,58 @@ static inline __ATTRS_o_ai void vec_xst(vector 
unsigned __int128 __vec,
 }
 #endif
 
+/* vec_xst_trunc */
+
+#if defined(__POWER10_VECTOR__) && defined(__VSX__)
+static inline __ATTRS_o_ai void vec_xst_trunc(vector signed __int128 __vec,
+  signed long long __offset,
+  signed char *__ptr) {
+  *(__ptr + __offset) = (signed char)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector unsigned __int128 __vec,
+  signed long long __offset,
+  unsigned char *__ptr) {
+  *(__ptr + __offset) = (unsigned char)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector signed __int128 __vec,
+  signed long long __offset,
+  signed short *__ptr) {
+  *(__ptr + __offset) = (signed short)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector unsigned __int128 __vec,
+  signed long long __offset,
+  unsigned short *__ptr) {
+  *(__ptr + __offset) = (unsigned short)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector signed __int128 __vec,
+  signed long long __offset,
+  signed int *__ptr) {
+  *(__ptr + __offset) = (signed int)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector unsigned __int128 __vec,
+  signed long long __offset,
+  unsigned int *__ptr) {
+  *(__ptr + __offset) = (unsigned int)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector signed __int128 __vec,
+  signed long long __offset,
+  signed long long *__ptr) {
+  *(__ptr + __offset) = (signed long long)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector unsigned __int128 __vec,
+  signed long long __offset,
+  unsigned long long *__ptr) {
+  *(__ptr + __offset) = (unsigned long long)__vec[0];
+}
+#endif
+
 /* vec_xst_be */
 
 #ifdef __LITTLE_ENDIAN__

diff  --git a/clang/test/CodeGen/builtins-ppc-p10vector.c 
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index 6f38ac77ee24..2182a19f2452 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -582,6 +582,54 @@ vector float test_vec_vec_splati_ins_f(void) {
   return vec_splati_ins(vfa, 0, 1.0f);
 }
 
+void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b,
+   signed char *__c) {
+  // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1
+  vec_xst_trunc(__a, __b, __c);
+}
+
+void test_vec_xst_trunc_uc(vector unsigned __int128 __a, signed long long __b,
+   unsigned char *__c) {
+  // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1
+  vec_xst_trunc(__a, __b, __c);
+}
+
+void test_vec_xst_trunc_ss(vector signed __int128 __a, signed long long __b,
+   signed short *__c) {
+  // CHECK: store i16 %{{.+}}, i16* %{{.+}}, align 2
+  vec_xst_trunc(__a, __b, __c);
+}
+
+void test_vec_xst_trunc_us(vector unsigned __int128 __a, signed long long __b,
+   unsigned short *__c) {
+  // CHECK: store i16 %{{.+}}, i16* %{{.+}}, align 2
+  vec_xst_trunc(__a, __b, __c);
+}
+
+void test_vec_xst_trunc_si(vector signed __int128 __a, signed long long __b,
+   signed int *__c) {
+  // CHECK: store i32 %{{.+}}, i32* %{{.+}}, align 4
+  vec_xst_trunc(__a

[clang] 62f5ba6 - [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

2020-07-13 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2020-07-13T22:47:47-05:00
New Revision: 62f5ba624bfba5ccf4446737ad2bfb1fc013b376

URL: 
https://github.com/llvm/llvm-project/commit/62f5ba624bfba5ccf4446737ad2bfb1fc013b376
DIFF: 
https://github.com/llvm/llvm-project/commit/62f5ba624bfba5ccf4446737ad2bfb1fc013b376.diff

LOG: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

This patch implements builtins for the Test LSB by Byte instruction introduced
in Power10.

Differential Revision: https://reviews.llvm.org/D82431

Added: 
llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index d0df5fcd1552..6b291e6b0806 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -467,6 +467,8 @@ BUILTIN(__builtin_vsx_xxsldwi, "v.", "t")
 
 BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "")
 
+BUILTIN(__builtin_vsx_xvtlsbb, "iV16Ucb", "")
+
 // P10 Vector Permute Extended built-in.
 BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi", "")
 

diff  --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 9a4009216930..ac5f43836316 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -17146,6 +17146,20 @@ vec_splati_ins(vector float __a, const unsigned int 
__b, const float __c) {
 #endif
   return __a;
 }
+
+/* vec_test_lsbb_all_ones */
+
+static __inline__ int __ATTRS_o_ai
+vec_test_lsbb_all_ones(vector unsigned char __a) {
+  return __builtin_vsx_xvtlsbb(__a, 1);
+}
+
+/* vec_test_lsbb_all_zeros */
+
+static __inline__ int __ATTRS_o_ai
+vec_test_lsbb_all_zeros(vector unsigned char __a) {
+  return __builtin_vsx_xvtlsbb(__a, 0);
+}
 #endif /* __VSX__ */
 #endif /* __POWER10_VECTOR__ */
 

diff  --git a/clang/test/CodeGen/builtins-ppc-p10vector.c 
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index 22b4e7a6f3ec..c51c24f25986 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -581,3 +581,15 @@ vector float test_vec_vec_splati_ins_f(void) {
   // CHECK: ret <4 x float>
   return vec_splati_ins(vfa, 0, 1.0f);
 }
+
+int test_vec_test_lsbb_all_ones(void) {
+  // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i1 true
+  // CHECK-NEXT: ret i32
+  return vec_test_lsbb_all_ones(vuca);
+}
+
+int test_vec_test_lsbb_all_zeros(void) {
+  // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i1 false
+  // CHECK-NEXT: ret i32
+  return vec_test_lsbb_all_zeros(vuca);
+}

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 12f4a3ce8e28..614a29049686 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1067,6 +1067,9 @@ def int_ppc_vsx_xxinsertw :
   PowerPC_VSX_Intrinsic<"xxinsertw",[llvm_v4i32_ty],
 [llvm_v4i32_ty,llvm_v2i64_ty,llvm_i32_ty],
 [IntrNoMem]>;
+def int_ppc_vsx_xvtlsbb :
+  PowerPC_VSX_Intrinsic<"xvtlsbb", [llvm_i32_ty],
+[llvm_v16i8_ty, llvm_i1_ty], [IntrNoMem]>;
 def int_ppc_vsx_xxeval :
   PowerPC_VSX_Intrinsic<"xxeval", [llvm_v2i64_ty],
[llvm_v2i64_ty, llvm_v2i64_ty,

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td 
b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 2d12a72e29ae..2bab73418e10 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -396,6 +396,25 @@ class 8RR_XX4Form_IMM3_XTABC6 opcode, bits<2> xo, 
dag OOL, dag IOL,
   let Inst{63} = XT{5};
 }
 
+// [PO BF / XO2 B XO BX /]
+class XX2_BF3_XO5_XB6_XO9 opcode, bits<5> xo2, bits<9> xo, dag OOL,
+  dag IOL, string asmstr, InstrItinClass itin,
+  list pattern>
+  : I {
+  bits<3> BF;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6-8}   = BF;
+  let Inst{9-10}  = 0;
+  let Inst{11-15} = xo2;
+  let Inst{16-20} = XB{4-0};
+  let Inst{21-29} = xo;
+  let Inst{30}= XB{5};
+  let Inst{31}= 0;
+}
+
 multiclass MLS_DForm_R_SI34_RTA5_MEM_p opcode, dag OOL, dag IOL,
dag PCRel_IOL, string asmstr,
InstrItinClass itin> {
@@ -943,6 +962,9 @@ let Predicates = [IsISA3_1] in {
  [(set v16i8:$vD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
 
+  def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins 
vsrc:$XB),
+"xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
+
   // The X

[clang] c45c161 - [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang

2020-06-18 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2020-06-18T16:23:56-05:00
New Revision: c45c1611303b4609016fa69c1c987ede3bf92006

URL: 
https://github.com/llvm/llvm-project/commit/c45c1611303b4609016fa69c1c987ede3bf92006
DIFF: 
https://github.com/llvm/llvm-project/commit/c45c1611303b4609016fa69c1c987ede3bf92006.diff

LOG: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in 
LLVM/Clang

This patch implements builtins for the following prototypes:

vector unsigned long long vec_pdep(vector unsigned long long, vector unsigned 
long long);
vector unsigned long long vec_pext(vector unsigned long long, vector unsigned 
long long __b);
unsigned long long __builtin_pdepd (unsigned long long, unsigned long long);
unsigned long long __builtin_pextd (unsigned long long, unsigned long long);

Revision Depends on D80758

Differential Revision: https://reviews.llvm.org/D80935

Added: 
clang/test/CodeGen/builtins-ppc-p10.c
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
llvm/test/MC/Disassembler/PowerPC/p10insts.txt
llvm/test/MC/PowerPC/p10.s

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 314e1cc05907..30077e2e8d03 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -298,6 +298,10 @@ BUILTIN(__builtin_altivec_vrldmi, 
"V2ULLiV2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vrlwnm, "V4UiV4UiV4Ui", "")
 BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "")
 
+// P10 Vector Parallel Bits built-ins.
+BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "")
+BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "")
+
 // VSX built-ins.
 
 BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
@@ -470,6 +474,8 @@ BUILTIN(__builtin_divweu, "UiUiUi", "")
 BUILTIN(__builtin_divde, "SLLiSLLiSLLi", "")
 BUILTIN(__builtin_divdeu, "ULLiULLiULLi", "")
 BUILTIN(__builtin_bpermd, "SLLiSLLiSLLi", "")
+BUILTIN(__builtin_pdepd, "ULLiULLiULLi", "")
+BUILTIN(__builtin_pextd, "ULLiULLiULLi", "")
 
 // Vector int128 (un)pack
 BUILTIN(__builtin_unpack_vector_int128, "ULLiV1LLLii", "")

diff  --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 7e231a2a428e..1e1e57cd1ffc 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16761,6 +16761,23 @@ static vector signed short __ATTRS_o_ai 
vec_nabs(vector signed short __a) {
 static vector signed char __ATTRS_o_ai vec_nabs(vector signed char __a) {
   return __builtin_altivec_vminsb(__a, -__a);
 }
+
+#ifdef __POWER10_VECTOR__
+/* vec_pdep */
+
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_pdep(vector unsigned long long __a, vector unsigned long long __b) {
+  return __builtin_altivec_vpdepd(__a, __b);
+}
+
+/* vec_pext */
+
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_pext(vector unsigned long long __a, vector unsigned long long __b) {
+  return __builtin_altivec_vpextd(__a, __b);
+}
+#endif /* __POWER10_VECTOR__ */
+
 #undef __ATTRS_o_ai
 
 #endif /* __ALTIVEC_H */

diff  --git a/clang/test/CodeGen/builtins-ppc-p10.c 
b/clang/test/CodeGen/builtins-ppc-p10.c
new file mode 100644
index ..c21e8026d0c9
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-p10.c
@@ -0,0 +1,15 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+
+unsigned long long ulla, ullb;
+
+unsigned long long test_pdepd(void) {
+  // CHECK: @llvm.ppc.pdepd
+  return __builtin_pdepd(ulla, ullb);
+}
+
+unsigned long long test_pextd(void) {
+  // CHECK: @llvm.ppc.pextd
+  return __builtin_pextd(ulla, ullb);
+}

diff  --git a/clang/test/CodeGen/builtins-ppc-p10vector.c 
b/clang/test/CodeGen/builtins-ppc-p10vector.c
new file mode 100644
index ..31c24f382f1e
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -0,0 +1,20 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
+// RUN:   -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN:   -o - | FileCheck %s
+
+#include 
+
+vector unsigned long long vulla, vullb;
+
+vector unsigned long long test_vpdepd(void) {
+  // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_pdep(vulla, vullb);
+}
+
+vector unsigned long long test_vpextd(void) {
+  // CHECK: @llvm.ppc.altivec.vpextd(<2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_pext(vulla, vullb);
+}

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index

[clang] cc95635 - [PowerPC][Power10] Implement Vector Clear Left/Rightmost Bytes Builtins in LLVM/Clang

2020-06-20 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2020-06-20T18:29:16-05:00
New Revision: cc95635b1bf28e626b4c2ac296b0a0ca22ab3c91

URL: 
https://github.com/llvm/llvm-project/commit/cc95635b1bf28e626b4c2ac296b0a0ca22ab3c91
DIFF: 
https://github.com/llvm/llvm-project/commit/cc95635b1bf28e626b4c2ac296b0a0ca22ab3c91.diff

LOG: [PowerPC][Power10] Implement Vector Clear Left/Rightmost Bytes Builtins in 
LLVM/Clang

This patch implements builtins for the following prototypes:
```
vector signed char vec_clrl (vector signed char a, unsigned int n);
vector unsigned char vec_clrl (vector unsigned char a, unsigned int n);
vector signed char vec_clrr (vector signed char a, unsigned int n);
vector signed char vec_clrr (vector unsigned char a, unsigned int n);
```

Differential Revision: https://reviews.llvm.org/D81707

Added: 
llvm/test/CodeGen/PowerPC/p10-string-ops.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/MC/Disassembler/PowerPC/p10insts.txt
llvm/test/MC/PowerPC/p10.s

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 30077e2e8d03..238e56b6dfce 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -302,6 +302,10 @@ BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "")
 
+// P10 Vector Clear Bytes built-ins.
+BUILTIN(__builtin_altivec_vclrlb, "V16cV16cUi", "")
+BUILTIN(__builtin_altivec_vclrrb, "V16cV16cUi", "")
+
 // VSX built-ins.
 
 BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")

diff  --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 1e1e57cd1ffc..385828aceced 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16776,6 +16776,46 @@ static __inline__ vector unsigned long long 
__ATTRS_o_ai
 vec_pext(vector unsigned long long __a, vector unsigned long long __b) {
   return __builtin_altivec_vpextd(__a, __b);
 }
+
+/* vec_clrl */
+
+static __inline__ vector signed char __ATTRS_o_ai
+vec_clrl(vector signed char __a, unsigned int __n) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vclrrb(__a, __n);
+#else
+  return __builtin_altivec_vclrlb( __a, __n);
+#endif
+}
+
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_clrl(vector unsigned char __a, unsigned int __n) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vclrrb((vector signed char)__a, __n);
+#else
+  return __builtin_altivec_vclrlb((vector signed char)__a, __n);
+#endif
+}
+
+/* vec_clrr */
+
+static __inline__ vector signed char __ATTRS_o_ai
+vec_clrr(vector signed char __a, unsigned int __n) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vclrlb(__a, __n);
+#else
+  return __builtin_altivec_vclrrb( __a, __n);
+#endif
+}
+
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_clrr(vector unsigned char __a, unsigned int __n) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vclrlb((vector signed char)__a, __n);
+#else
+  return __builtin_altivec_vclrrb((vector signed char)__a, __n);
+#endif
+}
 #endif /* __POWER10_VECTOR__ */
 
 #undef __ATTRS_o_ai

diff  --git a/clang/test/CodeGen/builtins-ppc-p10vector.c 
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index 31c24f382f1e..829ef97435eb 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -5,7 +5,10 @@
 
 #include 
 
+vector signed char vsca;
+vector unsigned char vuca;
 vector unsigned long long vulla, vullb;
+unsigned int uia;
 
 vector unsigned long long test_vpdepd(void) {
   // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
@@ -18,3 +21,35 @@ vector unsigned long long test_vpextd(void) {
   // CHECK-NEXT: ret <2 x i64>
   return vec_pext(vulla, vullb);
 }
+
+vector signed char test_vec_vclrl_sc(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
+  // CHECK-LE-NEXT: ret <16 x i8>
+  return vec_clrl(vsca, uia);
+}
+
+vector unsigned char test_vec_clrl_uc(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vclrrb(<16 x i8>
+  // CHECK-LE-NEXT: ret <16 x i8>
+  return vec_clrl(vuca, uia);
+}
+
+vector signed char test_vec_vclrr_sc(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
+  // CHECK-LE-NEXT: ret <16 x i8>
+  return vec_clrr(vsca, uia);
+}
+
+vector unsigned char test_vec_clrr_uc(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.p

[clang] 19df9e2 - [PowerPC][Power10] Implement VSX PCV Generate Operations in LLVM/Clang

2020-06-22 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2020-06-22T21:09:34-05:00
New Revision: 19df9e2959cfa3f25d798bd842df798e2b75f1b2

URL: 
https://github.com/llvm/llvm-project/commit/19df9e2959cfa3f25d798bd842df798e2b75f1b2
DIFF: 
https://github.com/llvm/llvm-project/commit/19df9e2959cfa3f25d798bd842df798e2b75f1b2.diff

LOG: [PowerPC][Power10] Implement VSX PCV Generate Operations in LLVM/Clang

This patch implements builtins for the following prototypes for the VSX Permute
Control Vector Generate with Mask Instructions:

vector unsigned char vec_genpcvm (vector unsigned char, const int);
vector unsigned short vec_genpcvm (vector unsigned short, const int);
vector unsigned int vec_genpcvm (vector unsigned int, const int);
vector unsigned long long vec_genpcvm (vector unsigned long long, const int);

Differential Revision: https://reviews.llvm.org/D81774

Added: 
llvm/test/CodeGen/PowerPC/p10-vsx-pcv.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/MC/Disassembler/PowerPC/p10insts.txt
llvm/test/MC/PowerPC/p10.s

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 238e56b6dfce..d16c2d239064 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -399,6 +399,11 @@ BUILTIN(__builtin_vsx_xvcpsgnsp, "V4fV4fV4f", "")
 BUILTIN(__builtin_vsx_xvabssp, "V4fV4f", "")
 BUILTIN(__builtin_vsx_xvabsdp, "V2dV2d", "")
 
+BUILTIN(__builtin_vsx_xxgenpcvbm, "V16UcV16Uci", "")
+BUILTIN(__builtin_vsx_xxgenpcvhm, "V8UsV8Usi", "")
+BUILTIN(__builtin_vsx_xxgenpcvwm, "V4UiV4Uii", "")
+BUILTIN(__builtin_vsx_xxgenpcvdm, "V2ULLiV2ULLii", "")
+
 // vector Insert/Extract exponent/significand builtins
 BUILTIN(__builtin_vsx_xviexpdp, "V2dV2ULLiV2ULLi", "")
 BUILTIN(__builtin_vsx_xviexpsp, "V4fV4UiV4Ui", "")

diff  --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 385828aceced..d9ad3e331c5c 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16777,6 +16777,20 @@ vec_pext(vector unsigned long long __a, vector 
unsigned long long __b) {
   return __builtin_altivec_vpextd(__a, __b);
 }
 
+/* vec_genpcvm */
+
+#ifdef __VSX__
+#define vec_genpcvm(__a, __imm)
\
+  _Generic((__a), vector unsigned char 
\
+   : __builtin_vsx_xxgenpcvbm((__a), (int)(__imm)),
\
+ vector unsigned short 
\
+   : __builtin_vsx_xxgenpcvhm((__a), (int)(__imm)),
\
+ vector unsigned int   
\
+   : __builtin_vsx_xxgenpcvwm((__a), (int)(__imm)),
\
+ vector unsigned long long 
\
+   : __builtin_vsx_xxgenpcvdm((__a), (int)(__imm)))
+#endif /* __VSX__ */
+
 /* vec_clrl */
 
 static __inline__ vector signed char __ATTRS_o_ai

diff  --git a/clang/test/CodeGen/builtins-ppc-p10vector.c 
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index 829ef97435eb..be4a1b59bfe5 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -7,6 +7,8 @@
 
 vector signed char vsca;
 vector unsigned char vuca;
+vector unsigned short vusa;
+vector unsigned int vuia;
 vector unsigned long long vulla, vullb;
 unsigned int uia;
 
@@ -22,6 +24,30 @@ vector unsigned long long test_vpextd(void) {
   return vec_pext(vulla, vullb);
 }
 
+vector unsigned char test_xxgenpcvbm(void) {
+  // CHECK: @llvm.ppc.vsx.xxgenpcvbm(<16 x i8> %{{.+}}, i32
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_genpcvm(vuca, 0);
+}
+
+vector unsigned short test_xxgenpcvhm(void) {
+  // CHECK: @llvm.ppc.vsx.xxgenpcvhm(<8 x i16> %{{.+}}, i32
+  // CHECK-NEXT: ret <8 x i16>
+  return vec_genpcvm(vusa, 0);
+}
+
+vector unsigned int test_xxgenpcvwm(void) {
+  // CHECK: @llvm.ppc.vsx.xxgenpcvwm(<4 x i32> %{{.+}}, i32
+  // CHECK-NEXT: ret <4 x i32>
+  return vec_genpcvm(vuia, 0);
+}
+
+vector unsigned long long test_xxgenpcvdm(void) {
+  // CHECK: @llvm.ppc.vsx.xxgenpcvdm(<2 x i64> %{{.+}}, i32
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_genpcvm(vulla, 0);
+}
+
 vector signed char test_vec_vclrl_sc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 2ca77d90e13c..43bd706cf104 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -953,6 +953,18 @@ def int_ppc_vsx_xxinsertw :
   PowerPC_VSX_Intrinsic<"xxinsertw",[llvm_v4i32_ty],

[clang] d82f26c - [PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins under bit Mask in LLVM/Clang

2020-06-24 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2020-06-24T16:03:45-05:00
New Revision: d82f26cc4bc7cb78f7ef327fa43a93e3d0ff9706

URL: 
https://github.com/llvm/llvm-project/commit/d82f26cc4bc7cb78f7ef327fa43a93e3d0ff9706
DIFF: 
https://github.com/llvm/llvm-project/commit/d82f26cc4bc7cb78f7ef327fa43a93e3d0ff9706.diff

LOG: [PowerPC][Power10] Implement Count Leading/Trailing Zeroes Builtins under 
bit Mask in LLVM/Clang

This patch implements builtins for the following prototypes:

unsigned long long __builtin_cntlzdm (unsigned long long, unsigned long long)
unsigned long long __builtin_cnttzdm (unsigned long long, unsigned long long)
vector unsigned long long vec_cntlzm (vector unsigned long long, vector 
unsigned long long)
vector unsigned long long vec_cnttzm (vector unsigned long long, vector 
unsigned long long)

Differential Revision: https://reviews.llvm.org/D80941

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10.c
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
llvm/test/MC/Disassembler/PowerPC/p10insts.txt
llvm/test/MC/PowerPC/p10.s

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index d16c2d239064..5bc41c9d6cea 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -306,6 +306,10 @@ BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vclrlb, "V16cV16cUi", "")
 BUILTIN(__builtin_altivec_vclrrb, "V16cV16cUi", "")
 
+// P10 Vector Count Leading / Trailing Zeroes under bit Mask built-ins.
+BUILTIN(__builtin_altivec_vclzdm, "V2ULLiV2ULLiV2ULLi", "")
+BUILTIN(__builtin_altivec_vctzdm, "V2ULLiV2ULLiV2ULLi", "")
+
 // VSX built-ins.
 
 BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
@@ -485,6 +489,8 @@ BUILTIN(__builtin_divdeu, "ULLiULLiULLi", "")
 BUILTIN(__builtin_bpermd, "SLLiSLLiSLLi", "")
 BUILTIN(__builtin_pdepd, "ULLiULLiULLi", "")
 BUILTIN(__builtin_pextd, "ULLiULLiULLi", "")
+BUILTIN(__builtin_cntlzdm, "ULLiULLiULLi", "")
+BUILTIN(__builtin_cnttzdm, "ULLiULLiULLi", "")
 
 // Vector int128 (un)pack
 BUILTIN(__builtin_unpack_vector_int128, "ULLiV1LLLii", "")

diff  --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index d9ad3e331c5c..f9fd3e2e50eb 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16830,6 +16830,21 @@ vec_clrr(vector unsigned char __a, unsigned int __n) {
   return __builtin_altivec_vclrrb((vector signed char)__a, __n);
 #endif
 }
+
+/* vec_cntlzm */
+
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_cntlzm(vector unsigned long long __a, vector unsigned long long __b) {
+  return __builtin_altivec_vclzdm(__a, __b);
+}
+
+/* vec_cnttzm */
+
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_cnttzm(vector unsigned long long __a, vector unsigned long long __b) {
+  return __builtin_altivec_vctzdm(__a, __b);
+}
+
 #endif /* __POWER10_VECTOR__ */
 
 #undef __ATTRS_o_ai

diff  --git a/clang/test/CodeGen/builtins-ppc-p10.c 
b/clang/test/CodeGen/builtins-ppc-p10.c
index c21e8026d0c9..5776dfae66dc 100644
--- a/clang/test/CodeGen/builtins-ppc-p10.c
+++ b/clang/test/CodeGen/builtins-ppc-p10.c
@@ -13,3 +13,13 @@ unsigned long long test_pextd(void) {
   // CHECK: @llvm.ppc.pextd
   return __builtin_pextd(ulla, ullb);
 }
+
+unsigned long long test_cntlzdm(void) {
+  // CHECK: @llvm.ppc.cntlzdm
+  return __builtin_cntlzdm(ulla, ullb);
+}
+
+unsigned long long test_cnttzdm(void) {
+  // CHECK: @llvm.ppc.cnttzdm
+  return __builtin_cnttzdm(ulla, ullb);
+}

diff  --git a/clang/test/CodeGen/builtins-ppc-p10vector.c 
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index be4a1b59bfe5..42c0ed917801 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -79,3 +79,15 @@ vector unsigned char test_vec_clrr_uc(void) {
   // CHECK-LE-NEXT: ret <16 x i8>
   return vec_clrr(vuca, uia);
 }
+
+vector unsigned long long test_vclzdm(void) {
+  // CHECK: @llvm.ppc.altivec.vclzdm(<2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_cntlzm(vulla, vullb);
+}
+
+vector unsigned long long test_vctzdm(void) {
+  // CHECK: @llvm.ppc.altivec.vctzdm(<2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_cnttzm(vulla, vullb);
+}

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 43bd706cf104..0f8521e5b6c5 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -68,6 +68,14 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with 
"llvm.ppc.".
   : GCCBuiltin<"__builtin_pextd">,
 Intrinsic <[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],

[clang] e0c02dc - [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

2020-06-25 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2020-06-25T21:34:41-05:00
New Revision: e0c02dc9800ebd317d1369848f4e74c8f783533a

URL: 
https://github.com/llvm/llvm-project/commit/e0c02dc9800ebd317d1369848f4e74c8f783533a
DIFF: 
https://github.com/llvm/llvm-project/commit/e0c02dc9800ebd317d1369848f4e74c8f783533a.diff

LOG: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, 
vector evaluate Builtins in LLVM/Clang

This patch implements builtins for the following prototypes:

unsigned long long __builtin_cfuged (unsigned long long, unsigned long long);
vector unsigned long long vec_cfuge (vector unsigned long long, vector unsigned 
long long);
unsigned long long vec_gnb (vector unsigned __int128, const unsigned int);
vector unsigned char vec_ternarylogic (vector unsigned char, vector unsigned 
char, vector unsigned char, const unsigned int);
vector unsigned short vec_ternarylogic (vector unsigned short, vector unsigned 
short, vector unsigned short, const unsigned int);
vector unsigned int vec_ternarylogic (vector unsigned int, vector unsigned int, 
vector unsigned int, const unsigned int);
vector unsigned long long vec_ternarylogic (vector unsigned long long, vector 
unsigned long long, vector unsigned long long, const unsigned int);
vector unsigned __int128 vec_ternarylogic (vector unsigned __int128, vector 
unsigned __int128, vector unsigned __int128, const unsigned int);

Differential Revision: https://reviews.llvm.org/D80970

Added: 


Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-p10.c
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
llvm/test/MC/Disassembler/PowerPC/p10insts.txt
llvm/test/MC/PowerPC/p10.s

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 5bc41c9d6cea..fa5b0b9d0920 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -302,6 +302,12 @@ BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "")
 
+// P10 Vector Centrifuge built-in.
+BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "")
+
+// P10 Vector Gather Every N-th Bit built-in.
+BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "")
+
 // P10 Vector Clear Bytes built-ins.
 BUILTIN(__builtin_altivec_vclrlb, "V16cV16cUi", "")
 BUILTIN(__builtin_altivec_vclrrb, "V16cV16cUi", "")
@@ -439,6 +445,8 @@ BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "")
 BUILTIN(__builtin_vsx_xxpermdi, "v.", "t")
 BUILTIN(__builtin_vsx_xxsldwi, "v.", "t")
 
+BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "")
+
 // Float 128 built-ins
 BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd", "")
 BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd", "")
@@ -489,6 +497,7 @@ BUILTIN(__builtin_divdeu, "ULLiULLiULLi", "")
 BUILTIN(__builtin_bpermd, "SLLiSLLiSLLi", "")
 BUILTIN(__builtin_pdepd, "ULLiULLiULLi", "")
 BUILTIN(__builtin_pextd, "ULLiULLiULLi", "")
+BUILTIN(__builtin_cfuged, "ULLiULLiULLi", "")
 BUILTIN(__builtin_cntlzdm, "ULLiULLiULLi", "")
 BUILTIN(__builtin_cnttzdm, "ULLiULLiULLi", "")
 

diff  --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index f9fd3e2e50eb..91279119630d 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16777,6 +16777,42 @@ vec_pext(vector unsigned long long __a, vector 
unsigned long long __b) {
   return __builtin_altivec_vpextd(__a, __b);
 }
 
+/* vec_cfuge */
+
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_cfuge(vector unsigned long long __a, vector unsigned long long __b) {
+  return __builtin_altivec_vcfuged(__a, __b);
+}
+
+/* vec_gnb */
+
+#define vec_gnb(__a, __b) __builtin_altivec_vgnb(__a, __b)
+
+/* vec_ternarylogic */
+#ifdef __VSX__
+#define vec_ternarylogic(__a, __b, __c, __imm) 
\
+  _Generic((__a), vector unsigned char 
\
+   : __builtin_vsx_xxeval((vector unsigned long long)(__a),
\
+  (vector unsigned long long)(__b),
\
+  (vector unsigned long long)(__c), (__imm)),  
\
+ vector unsigned short 
\
+   : __builtin_vsx_xxeval((vector unsigned long long)(__a),
\
+  (vector unsigned long long)(__b),
\
+  (vector unsigned long long)(__c), (__imm)),  
\
+ vector unsigned int   
\
+

[clang] c4e5743 - [PowerPC] Implement low-order Vector Modulus Builtins, and add Vector Multiply/Divide/Modulus Builtins Tests

2020-07-31 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2020-07-31T10:58:07-05:00
New Revision: c4e574323210feda1a3988e85fdd93b90a63d1b1

URL: 
https://github.com/llvm/llvm-project/commit/c4e574323210feda1a3988e85fdd93b90a63d1b1
DIFF: 
https://github.com/llvm/llvm-project/commit/c4e574323210feda1a3988e85fdd93b90a63d1b1.diff

LOG: [PowerPC] Implement low-order Vector Modulus Builtins, and add Vector 
Multiply/Divide/Modulus Builtins Tests

Power10 introduces new instructions for vector multiply, divide and modulus.
These instructions can be exploited by the builtin functions: vec_mul, vec_div,
and vec_mod, respectively.

This patch aims adds the function prototype, vec_mod, as vec_mul and vec_div
been previously implemented in altivec.h.

This patch also adds the following front end tests:
vec_mul for v2i64
vec_div for v4i32 and v2i64
vec_mod for v4i32 and v2i64

Differential Revision: https://reviews.llvm.org/D82576

Added: 


Modified: 
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c

Removed: 




diff  --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 4e25ec118072..f42200f5bd4e 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16933,6 +16933,28 @@ vec_cnttzm(vector unsigned long long __a, vector 
unsigned long long __b) {
   return __builtin_altivec_vctzdm(__a, __b);
 }
 
+/* vec_mod */
+
+static __inline__ vector signed int __ATTRS_o_ai
+vec_mod(vector signed int __a, vector signed int __b) {
+  return __a % __b;
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai
+vec_mod(vector unsigned int __a, vector unsigned int __b) {
+  return __a % __b;
+}
+
+static __inline__ vector signed long long __ATTRS_o_ai
+vec_mod(vector signed long long __a, vector signed long long __b) {
+  return __a % __b;
+}
+
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_mod(vector unsigned long long __a, vector unsigned long long __b) {
+  return __a % __b;
+}
+
 /* vec_sldbi */
 
 #define vec_sldb(__a, __b, __c) __builtin_altivec_vsldbi(__a, __b, (__c & 0x7))

diff  --git a/clang/test/CodeGen/builtins-ppc-p10vector.c 
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index e67018b06214..571d33d34a22 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -25,6 +25,66 @@ unsigned char uca;
 unsigned short usa;
 unsigned long long ulla;
 
+vector signed long long test_vec_mul_sll(void) {
+  // CHECK: mul <2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_mul(vslla, vsllb);
+}
+
+vector unsigned long long test_vec_mul_ull(void) {
+  // CHECK: mul <2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_mul(vulla, vullb);
+}
+
+vector signed int test_vec_div_si(void) {
+  // CHECK: sdiv <4 x i32>
+  // CHECK-NEXT: ret <4 x i32>
+  return vec_div(vsia, vsib);
+}
+
+vector unsigned int test_vec_div_ui(void) {
+  // CHECK: udiv <4 x i32>
+  // CHECK-NEXT: ret <4 x i32>
+  return vec_div(vuia, vuib);
+}
+
+vector signed long long test_vec_div_sll(void) {
+  // CHECK: sdiv <2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_div(vslla, vsllb);
+}
+
+vector unsigned long long test_vec_div_ull(void) {
+  // CHECK: udiv <2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_div(vulla, vullb);
+}
+
+vector signed int test_vec_mod_si(void) {
+  // CHECK: srem <4 x i32>
+  // CHECK-NEXT: ret <4 x i32>
+  return vec_mod(vsia, vsib);
+}
+
+vector unsigned int test_vec_mod_ui(void) {
+  // CHECK: urem <4 x i32>
+  // CHECK-NEXT: ret <4 x i32>
+  return vec_mod(vuia, vuib);
+}
+
+vector signed long long test_vec_mod_sll(void) {
+  // CHECK: srem <2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_mod(vslla, vsllb);
+}
+
+vector unsigned long long test_vec_mod_ull(void) {
+  // CHECK: urem <2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_mod(vulla, vullb);
+}
+
 vector unsigned long long test_vpdepd(void) {
   // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
   // CHECK-NEXT: ret <2 x i64>



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[clang] c7ec3a7 - [PowerPC] Implement Vector Extract Mask builtins in LLVM/Clang

2020-08-17 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2020-08-17T21:14:17-05:00
New Revision: c7ec3a7e338cd8e58424a66d29162e9b6a5847f7

URL: 
https://github.com/llvm/llvm-project/commit/c7ec3a7e338cd8e58424a66d29162e9b6a5847f7
DIFF: 
https://github.com/llvm/llvm-project/commit/c7ec3a7e338cd8e58424a66d29162e9b6a5847f7.diff

LOG: [PowerPC] Implement Vector Extract Mask builtins in LLVM/Clang

This patch implements the vec_extractm function prototypes in altivec.h in
order to utilize the vector extract with mask instructions introduced in 
Power10.

Differential Revision: https://reviews.llvm.org/D82675

Added: 
llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index b79ed41284ac..73c607800415 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -298,6 +298,13 @@ BUILTIN(__builtin_altivec_vrldmi, 
"V2ULLiV2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vrlwnm, "V4UiV4UiV4Ui", "")
 BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "")
 
+// P10 Vector Extract with Mask built-ins.
+BUILTIN(__builtin_altivec_vextractbm, "UiV16Uc", "")
+BUILTIN(__builtin_altivec_vextracthm, "UiV8Us", "")
+BUILTIN(__builtin_altivec_vextractwm, "UiV4Ui", "")
+BUILTIN(__builtin_altivec_vextractdm, "UiV2ULLi", "")
+BUILTIN(__builtin_altivec_vextractqm, "UiV1ULLLi", "")
+
 // P10 Vector Parallel Bits built-ins.
 BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "")

diff  --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index ac4182613cdd..b1e70f6c41bb 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16815,6 +16815,34 @@ static vector signed char __ATTRS_o_ai vec_nabs(vector 
signed char __a) {
 }
 
 #ifdef __POWER10_VECTOR__
+
+/* vec_extractm */
+
+static __inline__ unsigned int __ATTRS_o_ai
+vec_extractm(vector unsigned char __a) {
+  return __builtin_altivec_vextractbm(__a);
+}
+
+static __inline__ unsigned int __ATTRS_o_ai
+vec_extractm(vector unsigned short __a) {
+  return __builtin_altivec_vextracthm(__a);
+}
+
+static __inline__ unsigned int __ATTRS_o_ai
+vec_extractm(vector unsigned int __a) {
+  return __builtin_altivec_vextractwm(__a);
+}
+
+static __inline__ unsigned int __ATTRS_o_ai
+vec_extractm(vector unsigned long long __a) {
+  return __builtin_altivec_vextractdm(__a);
+}
+
+static __inline__ unsigned int __ATTRS_o_ai
+vec_extractm(vector unsigned __int128 __a) {
+  return __builtin_altivec_vextractqm(__a);
+}
+
 /* vec_pdep */
 
 static __inline__ vector unsigned long long __ATTRS_o_ai

diff  --git a/clang/test/CodeGen/builtins-ppc-p10vector.c 
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index a575f5a924c5..fe3e678a5794 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -97,6 +97,36 @@ vector unsigned long long test_vpextd(void) {
   return vec_pext(vulla, vullb);
 }
 
+unsigned int test_vec_extractm_uc(void) {
+  // CHECK: @llvm.ppc.altivec.vextractbm(<16 x i8> %{{.+}})
+  // CHECK-NEXT: ret i32
+  return vec_extractm(vuca);
+}
+
+unsigned int test_vec_extractm_us(void) {
+  // CHECK: @llvm.ppc.altivec.vextracthm(<8 x i16> %{{.+}})
+  // CHECK-NEXT: ret i32
+  return vec_extractm(vusa);
+}
+
+unsigned int test_vec_extractm_ui(void) {
+  // CHECK: @llvm.ppc.altivec.vextractwm(<4 x i32> %{{.+}})
+  // CHECK-NEXT: ret i32
+  return vec_extractm(vuia);
+}
+
+unsigned int test_vec_extractm_ull(void) {
+  // CHECK: @llvm.ppc.altivec.vextractdm(<2 x i64> %{{.+}})
+  // CHECK-NEXT: ret i32
+  return vec_extractm(vulla);
+}
+
+unsigned int test_vec_extractm_u128(void) {
+  // CHECK: @llvm.ppc.altivec.vextractqm(<1 x i128> %{{.+}})
+  // CHECK-NEXT: ret i32
+  return vec_extractm(vui128a);
+}
+
 vector unsigned long long test_vcfuged(void) {
   // CHECK: @llvm.ppc.altivec.vcfuged(<2 x i64>
   // CHECK-NEXT: ret <2 x i64>

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index ae25bb400e46..ce4c98968a7b 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -434,6 +434,18 @@ let TargetPrefix = "ppc" in {  // All intrinsics start 
with "llvm.ppc.".
   def int_ppc_altivec_vprtybq : GCCBuiltin<"__builtin_altivec_vprtybq">,
   Intrinsic<[llvm_v1i128_ty],[llvm_v1i128_ty],[IntrNoMem]>;
 
+  // P10 Vector Extract with Mask
+  def int_ppc_altivec_vextractbm : GCCBuiltin<"__builtin_altivec_vextractbm">,
+  Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
+  def int_ppc_altive

[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-08 Thread Amy Kwan via cfe-commits



@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S, 
SourceLocation Loc,
   return false;
 }
 
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI,
+   const TargetInfo *AuxTI, CallExpr *TheCall) 
{
+  Expr *Arg = TheCall->getArg(0);
+
+  const TargetInfo *TheTI = nullptr;
+  if (TI.supportsCpuSupports())
+TheTI = &TI;
+  else if (AuxTI && AuxTI->supportsCpuSupports())
+TheTI = AuxTI;
+  else
+return S.Diag(TheCall->getBeginLoc(), diag::err_builtin_target_unsupported)
+   << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc());
+
+  // Check if the argument is a string literal.
+  if (!isa(Arg->IgnoreParenImpCasts()))
+return S.Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal)
+   << Arg->getSourceRange();
+
+  // Check the contents of the string.
+  StringRef Feature =
+  cast(Arg->IgnoreParenImpCasts())->getString();
+  if (!TheTI->validateCpuSupports(Feature))
+return S.Diag(TheCall->getBeginLoc(), diag::err_invalid_cpu_supports)
+   << Arg->getSourceRange();
+  return false;
+}
+
+/// SemaBuiltinCpuIs - Handle __builtin_cpu_is(char *).
+/// This checks that the target supports __builtin_cpu_is and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuIs(Sema &S, const TargetInfo &TI,
+ const TargetInfo *AuxTI, CallExpr *TheCall) {
+  Expr *Arg = TheCall->getArg(0);
+
+  const TargetInfo *TheTI = nullptr;
+  if (TI.supportsCpuIs())
+TheTI = &TI;
+  else if (AuxTI && AuxTI->supportsCpuIs())
+TheTI = AuxTI;
+  else
+return S.Diag(TheCall->getBeginLoc(), diag::err_builtin_target_unsupported)
+   << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc());
+
+  // Check if the argument is a string literal.
+  if (!isa(Arg->IgnoreParenImpCasts()))

amy-kwan wrote:

Likewise here, perhaps we can pull out some of the calls that we call more than 
once.

https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-08 Thread Amy Kwan via cfe-commits



@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S, 
SourceLocation Loc,
   return false;
 }
 
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI,
+   const TargetInfo *AuxTI, CallExpr *TheCall) 
{
+  Expr *Arg = TheCall->getArg(0);
+
+  const TargetInfo *TheTI = nullptr;
+  if (TI.supportsCpuSupports())
+TheTI = &TI;
+  else if (AuxTI && AuxTI->supportsCpuSupports())
+TheTI = AuxTI;
+  else
+return S.Diag(TheCall->getBeginLoc(), diag::err_builtin_target_unsupported)
+   << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc());
+
+  // Check if the argument is a string literal.
+  if (!isa(Arg->IgnoreParenImpCasts()))

amy-kwan wrote:

It seems like we can pull out some of the calls are are repeated, such as 
`Arg->IgnoreParenImpCasts()`.

https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-08 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan commented:

Initial group code review comments.

https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-08 Thread Amy Kwan via cfe-commits



@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S, 
SourceLocation Loc,
   return false;
 }
 
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI,
+   const TargetInfo *AuxTI, CallExpr *TheCall) 
{

amy-kwan wrote:

Question:
Just wondering, what is and why are we checking an auxiliary target?

https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-08 Thread Amy Kwan via cfe-commits



@@ -359,6 +359,13 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   bool isSPRegName(StringRef RegName) const override {
 return RegName.equals("r1") || RegName.equals("x1");
   }
+
+  // We support __builtin_cpu_supports/__builtin_cpu_is on targets that

amy-kwan wrote:

Is it possible for `isOSGlibc()` to return true, but not have access to glibc?
The implementation for this function is as follows:
``` C++
  /// Tests whether the OS uses glibc.
  bool isOSGlibc() const {
return (getOS() == Triple::Linux || getOS() == Triple::KFreeBSD ||
getOS() == Triple::Hurd) &&
   !isAndroid();
  }
```
But for example, Alpine Linux doesn't have glibc.

https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-08 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-13 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-13 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan commented:

Additional group code review comments.

https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-13 Thread Amy Kwan via cfe-commits



@@ -2110,6 +2110,66 @@ static bool checkFPMathBuiltinElementType(Sema &S, 
SourceLocation Loc,
   return false;
 }
 
+/// SemaBuiltinCpuSupports - Handle __builtin_cpu_supports(char *).
+/// This checks that the target supports __builtin_cpu_supports and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuSupports(Sema &S, const TargetInfo &TI,
+   const TargetInfo *AuxTI, CallExpr *TheCall) 
{
+  Expr *Arg = TheCall->getArg(0);
+
+  const TargetInfo *TheTI = nullptr;
+  if (TI.supportsCpuSupports())
+TheTI = &TI;
+  else if (AuxTI && AuxTI->supportsCpuSupports())
+TheTI = AuxTI;
+  else
+return S.Diag(TheCall->getBeginLoc(), diag::err_builtin_target_unsupported)
+   << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc());
+
+  // Check if the argument is a string literal.
+  if (!isa(Arg->IgnoreParenImpCasts()))
+return S.Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal)
+   << Arg->getSourceRange();
+
+  // Check the contents of the string.
+  StringRef Feature =
+  cast(Arg->IgnoreParenImpCasts())->getString();
+  if (!TheTI->validateCpuSupports(Feature))
+return S.Diag(TheCall->getBeginLoc(), diag::err_invalid_cpu_supports)
+   << Arg->getSourceRange();
+  return false;
+}
+
+/// SemaBuiltinCpuIs - Handle __builtin_cpu_is(char *).
+/// This checks that the target supports __builtin_cpu_is and
+/// that the string argument is constant and valid.
+static bool SemaBuiltinCpuIs(Sema &S, const TargetInfo &TI,
+ const TargetInfo *AuxTI, CallExpr *TheCall) {
+  Expr *Arg = TheCall->getArg(0);
+
+  const TargetInfo *TheTI = nullptr;
+  if (TI.supportsCpuIs())
+TheTI = &TI;
+  else if (AuxTI && AuxTI->supportsCpuIs())
+TheTI = AuxTI;
+  else
+return S.Diag(TheCall->getBeginLoc(), diag::err_builtin_target_unsupported)
+   << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc());
+
+  // Check if the argument is a string literal.
+  if (!isa(Arg->IgnoreParenImpCasts()))
+return S.Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal)
+   << Arg->getSourceRange();
+
+  // Check the contents of the string.
+  StringRef Feature =

amy-kwan wrote:

Is it more accurate to call this `CPU` instead of `Feature` here?

https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-13 Thread Amy Kwan via cfe-commits



@@ -873,3 +873,17 @@ ArrayRef PPCTargetInfo::getTargetBuiltins() 
const {
   return llvm::ArrayRef(BuiltinInfo,
 clang::PPC::LastTSBuiltin - Builtin::FirstTSBuiltin);
 }
+
+bool PPCTargetInfo::validateCpuSupports(StringRef FeatureStr) const {

amy-kwan wrote:

Should this be `CPU` instead of `Cpu` for both of these validate functions?

https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2023-12-06 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/66316
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[clang] [llvm] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2023-12-06 Thread Amy Kwan via cfe-commits



@@ -145,9 +160,78 @@ namespace {
   .addImm(0);
 
 if (IsAIX) {
-  // The variable offset and region handle are copied in r4 and r3. The
-  // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX.
-  if (!IsTLSTPRelMI) {
+  if (IsTLSLDAIXMI) {
+// The relative order between the LoadOffset@toc node, and the
+// ._tls_get_mod node is being tuned here. It is better to put the
+// LoadOffset@toc node after the call, since the LoadOffset@toc 
node
+// can use clobbers r4/r5. Search for the pattern of two Load@toc
+// nodes, and then move the LoadOffset@toc node right before the
+// node that uses the OutReg of the ._tls_get_mod node.
+unsigned LDTocOp =
+Is64Bit ? (IsLargeModel ? PPC::LDtocL : PPC::LDtoc)
+: (IsLargeModel ? PPC::LWZtocL : PPC::LWZtoc);
+if (!RegInfo.use_empty(OutReg)) {
+  std::set Uses;
+  // Collect all instructions that use the OutReg.
+  for (MachineOperand &MO : RegInfo.use_operands(OutReg))
+Uses.insert(MO.getParent());
+  // Find the first user (e.g.: lwax/stfdx) within the current BB.
+  MachineBasicBlock::iterator UseIter = MBB.begin();
+  for (MachineBasicBlock::iterator IE = MBB.end(); UseIter != IE;
+   ++UseIter)
+if (Uses.count(&*UseIter))
+  break;
+
+  if (UseIter != MBB.end()) {
+// Collect associated Load@toc nodes.
+std::set LoadFromTocs;
+for (MachineOperand &MO : UseIter->operands())
+  if (MO.isReg() && MO.isUse()) {
+if (RegInfo.hasOneDef(MO.getReg())) {
+  MachineInstr *Temp =
+  RegInfo.getOneDef(MO.getReg())->getParent();
+  if (Temp == &MI && RegInfo.hasOneDef(InReg))
+Temp = RegInfo.getOneDef(InReg)->getParent();
+  if (Temp->getOpcode() == LDTocOp)
+LoadFromTocs.insert(Temp);
+} else {
+  // FIXME: analyze this scenario if there is one.
+  LoadFromTocs.clear();
+  break;
+}
+  }
+
+// Check the two Load@toc: one should be _$TLSML, and the other
+// will be moved before the node that uses the OutReg of the
+// ._tls_get_mod node.

amy-kwan wrote:

```suggestion
// .__tls_get_mod node.
```

https://github.com/llvm/llvm-project/pull/66316
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[llvm] [clang] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2023-12-06 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan commented:

I imagine this will be updated after 4b932d84f48e0f3f42c769a5ca7ce6623ab62f2e 
so I plan to review again after.

https://github.com/llvm/llvm-project/pull/66316
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[clang] [llvm] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2023-12-06 Thread Amy Kwan via cfe-commits



@@ -1356,6 +1382,11 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr 
*MI) {
.addExpr(SymGotTlsGD));
 return;
   }
+  case PPC::GETtlsMOD32AIX:
+  case PPC::GETtlsMOD64AIX:
+// Transform: %r3 = GETtlsMODNNAIX %r3 (for NN == 32/64).
+// Into: BLA .__tls_get_mod()
+// Input parameter is a module handle (__TLSML[TC]@ml) for all variables.

amy-kwan wrote:

```suggestion
// Input parameter is a module handle (_TLSML[TC]@ml) for all variables.
```
Single `_`?

https://github.com/llvm/llvm-project/pull/66316
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[clang] [llvm] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2023-12-06 Thread Amy Kwan via cfe-commits



@@ -231,12 +231,19 @@ class PPCTargetAsmStreamer : public PPCTargetStreamer {
   MCSymbolXCOFF *TCSym =
   cast(Streamer.getCurrentSectionOnly())
   ->getQualNameSymbol();
-  // On AIX, we have a region handle (symbol@m) and the variable offset
-  // (symbol@{gd|ie|le}) for TLS variables, depending on the TLS model.
+  // On AIX, we have TLS variable offsets (symbol@({gd|ie|le|ld}) depending
+  // on the TLS access method (or model). For the general-dynamic access
+  // method, we also have region handle (symbol@m) for each variable. For
+  // local-dynamic, there is a module handle (__TLSML[TC]@ml) for all

amy-kwan wrote:

```suggestion
  // local-dynamic, there is a module handle (_TLSML[TC]@ml) for all
```
Single `_` I think?

https://github.com/llvm/llvm-project/pull/66316
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[clang] [llvm] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2023-12-06 Thread Amy Kwan via cfe-commits



@@ -145,9 +160,78 @@ namespace {
   .addImm(0);
 
 if (IsAIX) {
-  // The variable offset and region handle are copied in r4 and r3. The
-  // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX.
-  if (!IsTLSTPRelMI) {
+  if (IsTLSLDAIXMI) {
+// The relative order between the LoadOffset@toc node, and the
+// ._tls_get_mod node is being tuned here. It is better to put the
+// LoadOffset@toc node after the call, since the LoadOffset@toc 
node
+// can use clobbers r4/r5. Search for the pattern of two Load@toc
+// nodes, and then move the LoadOffset@toc node right before the
+// node that uses the OutReg of the ._tls_get_mod node.

amy-kwan wrote:

```suggestion
// node that uses the OutReg of the .__tls_get_mod node.
```

https://github.com/llvm/llvm-project/pull/66316
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[llvm] [clang] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2023-12-06 Thread Amy Kwan via cfe-commits



@@ -145,9 +160,78 @@ namespace {
   .addImm(0);
 
 if (IsAIX) {
-  // The variable offset and region handle are copied in r4 and r3. The
-  // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX.
-  if (!IsTLSTPRelMI) {
+  if (IsTLSLDAIXMI) {
+// The relative order between the LoadOffset@toc node, and the
+// ._tls_get_mod node is being tuned here. It is better to put the
+// LoadOffset@toc node after the call, since the LoadOffset@toc 
node
+// can use clobbers r4/r5. Search for the pattern of two Load@toc
+// nodes, and then move the LoadOffset@toc node right before the
+// node that uses the OutReg of the ._tls_get_mod node.
+unsigned LDTocOp =
+Is64Bit ? (IsLargeModel ? PPC::LDtocL : PPC::LDtoc)
+: (IsLargeModel ? PPC::LWZtocL : PPC::LWZtoc);
+if (!RegInfo.use_empty(OutReg)) {
+  std::set Uses;
+  // Collect all instructions that use the OutReg.
+  for (MachineOperand &MO : RegInfo.use_operands(OutReg))
+Uses.insert(MO.getParent());
+  // Find the first user (e.g.: lwax/stfdx) within the current BB.
+  MachineBasicBlock::iterator UseIter = MBB.begin();
+  for (MachineBasicBlock::iterator IE = MBB.end(); UseIter != IE;
+   ++UseIter)
+if (Uses.count(&*UseIter))
+  break;
+
+  if (UseIter != MBB.end()) {
+// Collect associated Load@toc nodes.
+std::set LoadFromTocs;
+for (MachineOperand &MO : UseIter->operands())
+  if (MO.isReg() && MO.isUse()) {
+if (RegInfo.hasOneDef(MO.getReg())) {
+  MachineInstr *Temp =
+  RegInfo.getOneDef(MO.getReg())->getParent();
+  if (Temp == &MI && RegInfo.hasOneDef(InReg))
+Temp = RegInfo.getOneDef(InReg)->getParent();
+  if (Temp->getOpcode() == LDTocOp)
+LoadFromTocs.insert(Temp);
+} else {
+  // FIXME: analyze this scenario if there is one.
+  LoadFromTocs.clear();
+  break;
+}
+  }
+
+// Check the two Load@toc: one should be _$TLSML, and the other
+// will be moved before the node that uses the OutReg of the
+// ._tls_get_mod node.
+if (LoadFromTocs.size() == 2) {
+  MachineBasicBlock::iterator TLSMLIter = MBB.end();
+  MachineBasicBlock::iterator OffsetIter = MBB.end();
+  for (MachineBasicBlock::iterator I = MBB.begin(),
+   IE = MBB.end();
+   I != IE; ++I)
+if (LoadFromTocs.count(&*I)) {
+  if (I->getOperand(1).isGlobal() &&

amy-kwan wrote:

Pull out `I->getOperand(1)` maybe?

https://github.com/llvm/llvm-project/pull/66316
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[llvm] [clang] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2023-12-06 Thread Amy Kwan via cfe-commits



@@ -2058,6 +2089,10 @@ void PPCAIXAsmPrinter::emitLinkage(const GlobalValue *GV,
 }
   }
 
+  // Do not emit the _$TLSML symbol.
+  if (GVSym->getName() == "_Renamed..5f24__TLSML[TC]")

amy-kwan wrote:

Maybe a silly question, but will this always contain the `5f24`?

https://github.com/llvm/llvm-project/pull/66316
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[llvm] [clang] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2023-12-06 Thread Amy Kwan via cfe-commits



@@ -2385,6 +2385,13 @@ MCSection 
*TargetLoweringObjectFileXCOFF::getSectionForExternalReference(
   SmallString<128> Name;
   getNameWithPrefix(Name, GO, TM);
 
+  // AIX TLS local-dynamic requires the setting for the specific symbol name.

amy-kwan wrote:

Maybe we can clarify a bit on what we're setting here rather than just saying 
"the setting". It looks like `XMC_TC` here.

https://github.com/llvm/llvm-project/pull/66316
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[llvm] [clang] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2023-12-06 Thread Amy Kwan via cfe-commits



@@ -145,9 +160,78 @@ namespace {
   .addImm(0);
 
 if (IsAIX) {
-  // The variable offset and region handle are copied in r4 and r3. The
-  // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX.
-  if (!IsTLSTPRelMI) {
+  if (IsTLSLDAIXMI) {
+// The relative order between the LoadOffset@toc node, and the
+// ._tls_get_mod node is being tuned here. It is better to put the

amy-kwan wrote:

```suggestion
// .__tls_get_mod node is being tuned here. It is better to put the
```

https://github.com/llvm/llvm-project/pull/66316
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-14 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-14 Thread Amy Kwan via cfe-commits



@@ -1830,6 +1830,10 @@ void PPCLinuxAsmPrinter::emitEndOfAsmFile(Module &M) {
   PPCTargetStreamer *TS =
   static_cast(OutStreamer->getTargetStreamer());
 
+  if (static_cast(TM).hasGlibcHWCAPAccess())

amy-kwan wrote:

Can we add more documentation regarding what we're doing here?

https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-14 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan commented:

Additional group review comments.

https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-14 Thread Amy Kwan via cfe-commits



@@ -32,6 +32,7 @@ class PPCTargetMachine final : public LLVMTargetMachine {
   std::unique_ptr TLOF;
   PPCABI TargetABI;
   Endian Endianness = Endian::NOT_DETECTED;
+  mutable bool HasGlibcHWCAPAccess = false;

amy-kwan wrote:

Question: Why does this need to be mutable?

https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-15 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-15 Thread Amy Kwan via cfe-commits



@@ -1,11 +1,16 @@
-// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s| FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-pc-linux-gnu -emit-llvm < %s | FileCheck %s \
+// RUN:   --check-prefix=CHECK-X86
+// RUN: %clang_cc1 -triple ppc64le-linux-gnu -emit-llvm < %s | FileCheck %s \
+// RUN:   --check-prefix=CHECK-PPC
+
+#ifndef __PPC__

amy-kwan wrote:

It might be better to have the PPC checks in a separate file from the x86 RUN 
lines so we don't need to do the `ifndef`/`else`.

https://github.com/llvm/llvm-project/pull/68919
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[llvm] [clang] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-15 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan commented:

Additional group review comments.

https://github.com/llvm/llvm-project/pull/68919
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[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)

2023-11-15 Thread Amy Kwan via cfe-commits



@@ -15,38 +20,57 @@ int main(void) {
   if (__builtin_cpu_supports("sse4.2"))
 a("sse4.2");
 
-  // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0)
-  // CHECK: [[AND:%[^ ]+]] = and i32 [[LOAD]], 256
-  // CHECK: = icmp eq i32 [[AND]], 256
+  // CHECK-X86: [[LOAD:%[^ ]+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0)
+  // CHECK-X86: [[AND:%[^ ]+]] = and i32 [[LOAD]], 256
+  // CHECK-X86: = icmp eq i32 [[AND]], 256
 
   if (__builtin_cpu_supports("gfni"))
 a("gfni");
 
-  // CHECK: [[LOAD:%[^ ]+]] = load i32, ptr @__cpu_features2
-  // CHECK: [[AND:%[^ ]+]] = and i32 [[LOAD]], 1
-  // CHECK: = icmp eq i32 [[AND]], 1
+  // CHECK-X86: [[LOAD:%[^ ]+]] = load i32, ptr @__cpu_features2
+  // CHECK-X86: [[AND:%[^ ]+]] = and i32 [[LOAD]], 1
+  // CHECK-X86: = icmp eq i32 [[AND]], 1
 
   return 0;
 }
 
-// CHECK: declare dso_local void @__cpu_indicator_init()
+// CHECK-X86: declare dso_local void @__cpu_indicator_init()
 
-// CHECK-LABEL: define{{.*}} @baseline(
-// CHECK: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] 
x i32], ptr @__cpu_features2, i32 0, i32 1)
-// CHECK-NEXT:and i32 [[LOAD]], -2147483648
+// CHECK-X86-LABEL: define{{.*}} @baseline(
+// CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds 
([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 1)
+// CHECK-X86-NEXT:and i32 [[LOAD]], -2147483648
 int baseline() { return __builtin_cpu_supports("x86-64"); }
 
-// CHECK-LABEL: define{{.*}} @v2(
-// CHECK: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] 
x i32], ptr @__cpu_features2, i32 0, i32 2)
-// CHECK-NEXT:and i32 [[LOAD]], 1
+// CHECK-X86-LABEL: define{{.*}} @v2(
+// CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds 
([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
+// CHECK-X86-NEXT:and i32 [[LOAD]], 1
 int v2() { return __builtin_cpu_supports("x86-64-v2"); }
 
-// CHECK-LABEL: define{{.*}} @v3(
-// CHECK: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] 
x i32], ptr @__cpu_features2, i32 0, i32 2)
-// CHECK-NEXT:and i32 [[LOAD]], 2
+// CHECK-X86-LABEL: define{{.*}} @v3(
+// CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds 
([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
+// CHECK-X86-NEXT:and i32 [[LOAD]], 2
 int v3() { return __builtin_cpu_supports("x86-64-v3"); }
 
-// CHECK-LABEL: define{{.*}} @v4(
-// CHECK: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds ([[[#]] 
x i32], ptr @__cpu_features2, i32 0, i32 2)
-// CHECK-NEXT:and i32 [[LOAD]], 4
+// CHECK-X86-LABEL: define{{.*}} @v4(
+// CHECK-X86: [[LOAD:%.*]] = load i32, ptr getelementptr inbounds 
([[[#]] x i32], ptr @__cpu_features2, i32 0, i32 2)
+// CHECK-X86-NEXT:and i32 [[LOAD]], 4
 int v4() { return __builtin_cpu_supports("x86-64-v4"); }
+#else
+int test(int a) {

amy-kwan wrote:

Minor nit: Can we add a `CHECK-LABEL` as well? So that we know that we're 
actually inside `test`.

https://github.com/llvm/llvm-project/pull/68919
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[clang] [clang][Module] Mark test unsupported since objc doesn't have xcoff/g… (PR #70661)

2023-10-30 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/70661
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[clang] 4e1fe96 - Revert "[Clang][Attribute] Introduce maybe_undef attribute for function arguments which accepts undef values"

2022-07-29 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2022-07-29T13:28:48-05:00
New Revision: 4e1fe968c9de73507a1bf0c8aa57e06be457816e

URL: 
https://github.com/llvm/llvm-project/commit/4e1fe968c9de73507a1bf0c8aa57e06be457816e
DIFF: 
https://github.com/llvm/llvm-project/commit/4e1fe968c9de73507a1bf0c8aa57e06be457816e.diff

LOG: Revert "[Clang][Attribute] Introduce maybe_undef attribute for function 
arguments which accepts undef values"

This reverts commit a35c64ce23b7c7e4972c89b224b9363639dddea2.

Reverting this commit as it causes various failures on LE and BE PPC bots.

Added: 


Modified: 
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/lib/CodeGen/CGCall.cpp
clang/lib/Sema/SemaDeclAttr.cpp
clang/test/Misc/pragma-attribute-supported-attributes-list.test

Removed: 
clang/test/CodeGen/attr-maybeundef-template.cpp
clang/test/CodeGen/attr-maybeundef.c
clang/test/CodeGenHIP/maybe_undef-attr-verify.hip
clang/test/Sema/attr-maybeundef.c



diff  --git a/clang/include/clang/Basic/Attr.td 
b/clang/include/clang/Basic/Attr.td
index a94829698ad91..0460371d26c94 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -2023,13 +2023,6 @@ def NoEscape : Attr {
   let Documentation = [NoEscapeDocs];
 }
 
-def MaybeUndef : InheritableAttr {
-  let Spellings = [Clang<"maybe_undef">];
-  let Subjects = SubjectList<[ParmVar]>;
-  let Documentation = [MaybeUndefDocs];
-  let SimpleHandler = 1;
-}
-
 def AssumeAligned : InheritableAttr {
   let Spellings = [GCC<"assume_aligned">];
   let Subjects = SubjectList<[ObjCMethod, Function]>;

diff  --git a/clang/include/clang/Basic/AttrDocs.td 
b/clang/include/clang/Basic/AttrDocs.td
index f61a5a8d5b523..5c84e2fc5b77d 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -257,28 +257,6 @@ applies to copies of the block. For example:
   }];
 }
 
-def MaybeUndefDocs : Documentation {
-  let Category = DocCatVariable;
-  let Content = [{
-The ``maybe_undef`` attribute can be placed on a function parameter. It 
indicates
-that the parameter is allowed to use undef values. It informs the compiler
-to insert a freeze LLVM IR instruction on the function parameter.
-Please note that this is an attribute that is used as an internal
-implementation detail and not intended to be used by external users.
-
-In languages HIP, CUDA etc., some functions have multi-threaded semantics and
-it is enough for only one or some threads to provide defined arguments.
-Depending on semantics, undef arguments in some threads don't produce
-undefined results in the function call. Since, these functions accept undefined
-arguments, ``maybe_undef`` attribute can be placed.
-
-Sample usage:
-.. code-block:: c
-
-  void maybeundeffunc(int __attribute__((maybe_undef))param);
-  }];
-}
-
 def CarriesDependencyDocs : Documentation {
   let Category = DocCatFunction;
   let Content = [{

diff  --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index ee37e762dc759..7853695f1f0cb 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -2046,27 +2046,6 @@ static bool DetermineNoUndef(QualType QTy, CodeGenTypes 
&Types,
   return false;
 }
 
-/// Check if the argument of a function has maybe_undef attribute.
-static bool IsArgumentMaybeUndef(const Decl *TargetDecl,
- unsigned NumRequiredArgs, unsigned ArgNo) {
-  const auto *FD = dyn_cast_or_null(TargetDecl);
-  if (!FD)
-return false;
-
-  // Assume variadic arguments do not have maybe_undef attribute.
-  if (ArgNo >= NumRequiredArgs)
-return false;
-
-  // Check if argument has maybe_undef attribute.
-  if (ArgNo < FD->getNumParams()) {
-const ParmVarDecl *Param = FD->getParamDecl(ArgNo);
-if (Param && Param->hasAttr())
-  return true;
-  }
-
-  return false;
-}
-
 /// Construct the IR attribute list of a function or call.
 ///
 /// When adding an attribute, please consider where it should be handled:
@@ -4842,9 +4821,6 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo 
&CallInfo,
 unsigned FirstIRArg, NumIRArgs;
 std::tie(FirstIRArg, NumIRArgs) = IRFunctionArgs.getIRArgs(ArgNo);
 
-bool ArgHasMaybeUndefAttr =
-IsArgumentMaybeUndef(TargetDecl, CallInfo.getNumRequiredArgs(), ArgNo);
-
 switch (ArgInfo.getKind()) {
 case ABIArgInfo::InAlloca: {
   assert(NumIRArgs == 0);
@@ -4903,11 +4879,7 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo 
&CallInfo,
 // Make a temporary alloca to pass the argument.
 Address Addr = CreateMemTempWithoutCast(
 I->Ty, ArgInfo.getIndirectAlign(), "indirect-arg-temp");
-
-llvm::Value *Val = Addr.getPointer();
-if (ArgHasMaybeUndefAttr)
-  Val = Builder.CreateFreeze(Addr.getPointer());
-IRCallArgs[FirstIRArg] = Val;
+IRCallArgs[FirstIRArg] =

[clang] dd5aa65 - [PowerPC] Implement vector bool/pixel initialization under -faltivec-src-compat=xl

2021-07-19 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2021-07-19T09:10:06-05:00
New Revision: dd5aa657a520adcff84bb6149dd20cd8a2c8c6c6

URL: 
https://github.com/llvm/llvm-project/commit/dd5aa657a520adcff84bb6149dd20cd8a2c8c6c6
DIFF: 
https://github.com/llvm/llvm-project/commit/dd5aa657a520adcff84bb6149dd20cd8a2c8c6c6.diff

LOG: [PowerPC] Implement vector bool/pixel initialization under 
-faltivec-src-compat=xl

This patch implements the initialization of vectors under the
-faltivec-src-compat=xl option introduced in https://reviews.llvm.org/D103615.

Under this option, the initialization of scalar vectors, vector bool, and vector
pixel are treated the same, where the initialization value is splatted across
the whole vector.

This patch does not change the behaviour of the -faltivec-src-compat=mixed 
option,
which is the current default for Clang.

Differential Revision: https://reviews.llvm.org/D106120

Added: 
clang/test/CodeGen/vector-bool-pixel-altivec-init-no-parentheses.c
clang/test/CodeGen/vector-bool-pixel-altivec-init.c

Modified: 
clang/include/clang/Sema/Sema.h
clang/lib/Sema/SemaCast.cpp
clang/lib/Sema/SemaExpr.cpp

Removed: 




diff  --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 8201e61fa63d8..4ade04992a5f4 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -6090,6 +6090,12 @@ class Sema final {
   void CheckCompatibleReinterpretCast(QualType SrcType, QualType DestType,
   bool IsDereference, SourceRange Range);
 
+  // Checks that the vector type should be initialized from a scalar
+  // by splatting the value rather than populating a single element.
+  // This is the case for AltiVecVector types as well as with
+  // AltiVecPixel and AltiVecBool when -faltivec-src-compat=xl is specified.
+  bool ShouldSplatAltivecScalarInCast(const VectorType *VecTy);
+
   /// ActOnCXXNamedCast - Parse
   /// {dynamic,static,reinterpret,const,addrspace}_cast's.
   ExprResult ActOnCXXNamedCast(SourceLocation OpLoc,

diff  --git a/clang/lib/Sema/SemaCast.cpp b/clang/lib/Sema/SemaCast.cpp
index 869e414c70959..cac43075f860c 100644
--- a/clang/lib/Sema/SemaCast.cpp
+++ b/clang/lib/Sema/SemaCast.cpp
@@ -2624,6 +2624,19 @@ void CastOperation::checkAddressSpaceCast(QualType 
SrcType, QualType DestType) {
   }
 }
 
+bool Sema::ShouldSplatAltivecScalarInCast(const VectorType *VecTy) {
+  bool SrcCompatXL = this->getLangOpts().getAltivecSrcCompat() ==
+ LangOptions::AltivecSrcCompatKind::XL;
+  VectorType::VectorKind VKind = VecTy->getVectorKind();
+
+  if ((VKind == VectorType::AltiVecVector) ||
+  (SrcCompatXL && ((VKind == VectorType::AltiVecBool) ||
+   (VKind == VectorType::AltiVecPixel {
+return true;
+  }
+  return false;
+}
+
 void CastOperation::CheckCXXCStyleCast(bool FunctionalStyle,
bool ListInitialization) {
   assert(Self.getLangOpts().CPlusPlus);
@@ -2678,9 +2691,9 @@ void CastOperation::CheckCXXCStyleCast(bool 
FunctionalStyle,
 
   // AltiVec vector initialization with a single literal.
   if (const VectorType *vecTy = DestType->getAs())
-if (vecTy->getVectorKind() == VectorType::AltiVecVector
-&& (SrcExpr.get()->getType()->isIntegerType()
-|| SrcExpr.get()->getType()->isFloatingType())) {
+if (Self.ShouldSplatAltivecScalarInCast(vecTy) &&
+(SrcExpr.get()->getType()->isIntegerType() ||
+ SrcExpr.get()->getType()->isFloatingType())) {
   Kind = CK_VectorSplat;
   SrcExpr = Self.prepareVectorSplat(DestType, SrcExpr.get());
   return;
@@ -2963,8 +2976,8 @@ void CastOperation::CheckCStyleCast() {
   }
 
   if (const VectorType *DestVecTy = DestType->getAs()) {
-if (DestVecTy->getVectorKind() == VectorType::AltiVecVector &&
-  (SrcType->isIntegerType() || SrcType->isFloatingType())) {
+if (Self.ShouldSplatAltivecScalarInCast(DestVecTy) &&
+(SrcType->isIntegerType() || SrcType->isFloatingType())) {
   Kind = CK_VectorSplat;
   SrcExpr = Self.prepareVectorSplat(DestType, SrcExpr.get());
 } else if (Self.CheckVectorCast(OpRange, DestType, SrcType, Kind)) {

diff  --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index a3a26d21422f0..f1c49eb082c20 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -7707,7 +7707,7 @@ ExprResult Sema::BuildVectorLiteral(SourceLocation 
LParenLoc,
   // initializers must be one or must match the size of the vector.
   // If a single value is specified in the initializer then it will be
   // replicated to all the components of the vector
-  if (VTy->getVectorKind() == VectorType::AltiVecVector) {
+  if (ShouldSplatAltivecScalarInCast(VTy)) {
 // The number of initializers must be one or must match the size of the
 // vector. If a single value is specified in the initializer

[clang] 356300a - [NFC][PowerPC] Update builtins-ppc-altivec.c to be run under `-faltivec-src-compat=mixed`

2021-07-19 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2021-07-19T11:20:21-05:00
New Revision: 356300a3510c48f1f446cbdf580294b577435589

URL: 
https://github.com/llvm/llvm-project/commit/356300a3510c48f1f446cbdf580294b577435589
DIFF: 
https://github.com/llvm/llvm-project/commit/356300a3510c48f1f446cbdf580294b577435589.diff

LOG: [NFC][PowerPC] Update builtins-ppc-altivec.c to be run under 
`-faltivec-src-compat=mixed`

This patch adds the `-faltivec-src-compat=mixed` option to the
`builtins-ppc-altivec.c` test.

Currently, the default for `-faltivec-src-compat` is `mixed`. The reason we
explicitly specify `mixed` to the RUN lines of this test is because eventually,
the default will set to `xl`.

Having the default as `xl` changes the CHECKs of this test slightly, as it
reorders some of the `vector bool` and `vector pixel` CHECKs (since under the
`xl` option, `vector bool` and `vector pixel` are treated in the same way as
other vector scalars). Explicitly specifying `mixed` ensures that we are testing
pre-existing Clang behaviour.

Differential Revision: https://reviews.llvm.org/D106282

Added: 


Modified: 
clang/test/CodeGen/builtins-ppc-altivec.c

Removed: 




diff  --git a/clang/test/CodeGen/builtins-ppc-altivec.c 
b/clang/test/CodeGen/builtins-ppc-altivec.c
index 8aefafb61993..5c896ebada7b 100644
--- a/clang/test/CodeGen/builtins-ppc-altivec.c
+++ b/clang/test/CodeGen/builtins-ppc-altivec.c
@@ -1,12 +1,16 @@
 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -target-feature +altivec -triple powerpc-unknown-unknown 
-emit-llvm %s \
-// RUN:-flax-vector-conversions=none -o - | FileCheck %s
+// RUN:-flax-vector-conversions=none  -faltivec-src-compat=mixed \
+// RUN:-o - | FileCheck %s
 // RUN: %clang_cc1 -target-feature +altivec -triple powerpcle-unknown-unknown 
-emit-llvm %s \
-// RUN:-flax-vector-conversions=none -o - | FileCheck %s 
-check-prefix=CHECK-LE
+// RUN:-flax-vector-conversions=none  -faltivec-src-compat=mixed \
+// RUN:-o - | FileCheck %s -check-prefix=CHECK-LE
 // RUN: %clang_cc1 -target-feature +altivec -triple powerpc64-unknown-unknown 
-emit-llvm %s \
-// RUN:-flax-vector-conversions=none -o - | FileCheck %s
+// RUN:-flax-vector-conversions=none  -faltivec-src-compat=mixed \
+// RUN:-o - | FileCheck %s
 // RUN: %clang_cc1 -target-feature +altivec -triple 
powerpc64le-unknown-unknown -emit-llvm %s \
-// RUN:-flax-vector-conversions=none -o - | FileCheck %s 
-check-prefix=CHECK-LE
+// RUN:-flax-vector-conversions=none  -faltivec-src-compat=mixed \
+// RUN:-o - | FileCheck %s -check-prefix=CHECK-LE
 // RUN: not %clang_cc1 -triple powerpc64le-unknown-unknown -emit-llvm %s \
 // RUN:-ferror-limit 0 -DNO_ALTIVEC -o - 2>&1 \
 // RUN:| FileCheck %s -check-prefix=CHECK-NOALTIVEC



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[clang] 5dc0a16 - [PowerPC] Fix __builtin_pdepd and __builtin_pextd to be 64-bit and P10 only.

2022-02-15 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2022-02-15T12:30:50-06:00
New Revision: 5dc0a1657be14df68bfc33deb2fb75476acdaec8

URL: 
https://github.com/llvm/llvm-project/commit/5dc0a1657be14df68bfc33deb2fb75476acdaec8
DIFF: 
https://github.com/llvm/llvm-project/commit/5dc0a1657be14df68bfc33deb2fb75476acdaec8.diff

LOG: [PowerPC] Fix __builtin_pdepd and __builtin_pextd to be 64-bit and P10 
only.

The `__builtin_pdepd` and `__builtin_pextd` are P10 builtins that are meant to
be used under 64-bit only. For instance, when the builtins are compiled under
32-bit mode:
```
$ cat t.c
unsigned long long foo(unsigned long long a, unsigned long long b) {
  return __builtin_pextd(a,b);
}

$ clang -c t.c -mcpu=pwr10 -m32
ExpandIntegerResult #0: t31: i64 = llvm.ppc.pextd TargetConstant:i32<6928>, 
t28, t29

fatal error: error in backend: Do not know how to expand the result of this 
operator!
```
This patch adds sema checking for these builtins to compile under 64-bit
mode only and on P10. The builtins will emit a diagnostic when they are 
compiled on
non-P10 compilations and on 32-bit mode.

Differential Revision: https://reviews.llvm.org/D118753

Added: 
clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c

Modified: 
clang/lib/Sema/SemaChecking.cpp
llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll

Removed: 




diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index c422981a1a2e6..cb65991cbe2e9 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3604,6 +3604,8 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
   case PPC::BI__builtin_divde:
   case PPC::BI__builtin_divdeu:
   case PPC::BI__builtin_bpermd:
+  case PPC::BI__builtin_pdepd:
+  case PPC::BI__builtin_pextd:
   case PPC::BI__builtin_ppc_ldarx:
   case PPC::BI__builtin_ppc_stdcx:
   case PPC::BI__builtin_ppc_tdw:
@@ -3763,6 +3765,10 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI, unsigned BuiltinID,
   case PPC::BI__builtin_pack_vector_int128:
 return SemaFeatureCheck(*this, TheCall, "vsx",
 diag::err_ppc_builtin_only_on_arch, "7");
+  case PPC::BI__builtin_pdepd:
+  case PPC::BI__builtin_pextd:
+return SemaFeatureCheck(*this, TheCall, "isa-v31-instructions",
+diag::err_ppc_builtin_only_on_arch, "10");
   case PPC::BI__builtin_altivec_vgnb:
  return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7);
   case PPC::BI__builtin_altivec_vec_replace_elt:

diff  --git a/clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c 
b/clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c
new file mode 100644
index 0..c6922eae6bf58
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-pwr10-64bit.c
@@ -0,0 +1,34 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm %s \
+// RUN:   -target-cpu pwr10 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm %s \
+// RUN:   -target-cpu pwr10 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
+// RUN:   -target-cpu pwr10 -o - | FileCheck %s
+// RUN: not %clang_cc1 -triple powerpc-unknown-aix -emit-llvm-only %s \
+// RUN:   -target-cpu pwr8 2>&1 | FileCheck %s --check-prefix=CHECK-32-ERROR
+// RUN: not %clang_cc1 -triple powerpc-unknown-linux-gnu -emit-llvm-only %s \
+// RUN:   -target-cpu pwr9 2>&1 | FileCheck %s --check-prefix=CHECK-32-ERROR
+// RUN: not %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm-only %s \
+// RUN:   -target-cpu pwr9 2>&1 | FileCheck %s 
--check-prefix=CHECK-NONPWR10-ERR
+// RUN: not %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm-only %s \
+// RUN:   -target-cpu pwr8 2>&1 | FileCheck %s 
--check-prefix=CHECK-NONPWR10-ERR
+
+extern unsigned long long ull;
+
+unsigned long long test_builtin_pextd() {
+  // CHECK-LABEL:@test_builtin_pextd(
+  // CHECK:  %2 = call i64 @llvm.ppc.pextd(i64 %0, i64 %1)
+  // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+  // CHECK-NONPWR10-ERR:  error: this builtin is only valid on POWER10 or 
later CPUs
+  return __builtin_pextd(ull, ull);
+}
+
+unsigned long long test_builtin_pdepd() {
+  // CHECK-LABEL:@test_builtin_pdepd(
+  // CHECK:  %2 = call i64 @llvm.ppc.pdepd(i64 %0, i64 %1)
+  // CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
+  // CHECK-NONPWR10-ERR:  error: this builtin is only valid on POWER10 or 
later CPUs
+  return __builtin_pdepd(ull, ull);
+}
+

diff  --git a/llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll 
b/llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
index 901b449bb5c39..4643faee88db1 100644
--- a/llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-bit-manip-ops.ll
@@ -2,6 +2,9 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc

[clang] 2534dc1 - [PowerPC] Enable CR bits support for Power8 and above.

2022-05-02 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2022-05-02T12:06:15-05:00
New Revision: 2534dc120a4c9468d9a0044665a50361089f0a4d

URL: 
https://github.com/llvm/llvm-project/commit/2534dc120a4c9468d9a0044665a50361089f0a4d
DIFF: 
https://github.com/llvm/llvm-project/commit/2534dc120a4c9468d9a0044665a50361089f0a4d.diff

LOG: [PowerPC] Enable CR bits support for Power8 and above.

This patch turns on support for CR bit accesses for Power8 and above. The reason
why CR bits are turned on as the default for Power8 and above is that because
later architectures make use of builtins and instructions that require CR bit
accesses (such as the use of setbc in the vector string isolate predicate
and bcd builtins on Power10).

This patch also adds the clang portion to allow for turning on CR bits in the
front end if the user so desires to.

Differential Revision: https://reviews.llvm.org/D124060

Added: 
clang/test/Driver/ppc-crbits.cpp

Modified: 
clang/docs/ClangCommandLineReference.rst
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
llvm/lib/Target/PowerPC/PPC.td
llvm/test/CodeGen/PowerPC/addegluecrash.ll
llvm/test/CodeGen/PowerPC/f128-branch-cond.ll
llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll

Removed: 




diff  --git a/clang/docs/ClangCommandLineReference.rst 
b/clang/docs/ClangCommandLineReference.rst
index 384b092389c87..d8fa4b33baf0f 100644
--- a/clang/docs/ClangCommandLineReference.rst
+++ b/clang/docs/ClangCommandLineReference.rst
@@ -3575,6 +3575,8 @@ PowerPC
 
 .. option:: -mcrbits, -mno-crbits
 
+Control the CR-bit tracking feature on PowerPC. ``-mcrbits`` (the enablement 
of CR-bit tracking support) is the default for POWER8 and above, as well as for 
all other CPUs when optimization is applied (-O2 and above).
+
 .. option:: -mcrypto, -mno-crypto
 
 .. option:: -mdirect-move, -mno-direct-move

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e3ee68cd1fa30..a2e50f37d854f 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -36,6 +36,8 @@ bool 
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
   HasAltivec = true;
 } else if (Feature == "+vsx") {
   HasVSX = true;
+} else if (Feature == "+crbits") {
+  UseCRBits = true;
 } else if (Feature == "+bpermd") {
   HasBPERMD = true;
 } else if (Feature == "+extdiv") {
@@ -515,6 +517,11 @@ bool PPCTargetInfo::initFeatureMap(
 .Case("pwr9", true)
 .Case("pwr8", true)
 .Default(false);
+  Features["crbits"] = llvm::StringSwitch(CPU)
+.Case("ppc64le", true)
+.Case("pwr9", true)
+.Case("pwr8", true)
+.Default(false);
   Features["vsx"] = llvm::StringSwitch(CPU)
 .Case("ppc64le", true)
 .Case("pwr9", true)
@@ -649,6 +656,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
   .Case("powerpc", true)
   .Case("altivec", HasAltivec)
   .Case("vsx", HasVSX)
+  .Case("crbits", UseCRBits)
   .Case("power8-vector", HasP8Vector)
   .Case("crypto", HasP8Crypto)
   .Case("direct-move", HasDirectMove)

diff  --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 44489d06307f2..8148762f446b0 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -62,6 +62,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public 
TargetInfo {
   bool HasROPProtect = false;
   bool HasPrivileged = false;
   bool HasVSX = false;
+  bool UseCRBits = false;
   bool HasP8Vector = false;
   bool HasP8Crypto = false;
   bool HasDirectMove = false;

diff  --git a/clang/test/Driver/ppc-crbits.cpp 
b/clang/test/Driver/ppc-crbits.cpp
new file mode 100644
index 0..3ed56308cb526
--- /dev/null
+++ b/clang/test/Driver/ppc-crbits.cpp
@@ -0,0 +1,112 @@
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr10 \
+// RUN:   -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr10 \
+// RUN:   -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr9 \
+// RUN:   -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr9 \
+// RUN:   -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr8 \
+// RUN:   -mcrbits -o %t.o 2>&1 | FileCheck -check-prefi

[clang] c35ca3a - [PowerPC] Implement XL compat fnabs and fnabss builtins.

2022-05-19 Thread Amy Kwan via cfe-commits


Author: Amy Kwan
Date: 2022-05-19T11:28:40-05:00
New Revision: c35ca3a1c78f693b749ad11742350b7fc6c5cd89

URL: 
https://github.com/llvm/llvm-project/commit/c35ca3a1c78f693b749ad11742350b7fc6c5cd89
DIFF: 
https://github.com/llvm/llvm-project/commit/c35ca3a1c78f693b749ad11742350b7fc6c5cd89.diff

LOG: [PowerPC] Implement XL compat __fnabs and __fnabss builtins.

This patch implements the following floating point negative absolute value
builtins that required for compatibility with the XL compiler:
```
double __fnabs(double);
float __fnabss(float);
```

These builtins will emit :
- fnabs on PWR6 and below, or if VSX is disabled.
- xsnabsdp on PWR7 and above, if VSX is enabled.

Differential Revision: https://reviews.llvm.org/D125506

Added: 
clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll

Modified: 
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/P10InstrResources.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td

Removed: 




diff  --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index 8a4c5b4eead27..923215cc3e5d0 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -159,6 +159,9 @@ BUILTIN(__builtin_ppc_maxfs, ".", "t")
 BUILTIN(__builtin_ppc_minfe, "LdLdLdLd.", "t")
 BUILTIN(__builtin_ppc_minfl, ".", "t")
 BUILTIN(__builtin_ppc_minfs, ".", "t")
+// Floating Negative Absolute Value
+BUILTIN(__builtin_ppc_fnabs, "dd", "")
+BUILTIN(__builtin_ppc_fnabss, "ff", "")
 
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 

diff  --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index dacb7eeea12a8..7de40b5db04a3 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -252,6 +252,8 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
   Builder.defineMacro("__test_data_class", "__builtin_ppc_test_data_class");
   Builder.defineMacro("__swdiv", "__builtin_ppc_swdiv");
   Builder.defineMacro("__swdivs", "__builtin_ppc_swdivs");
+  Builder.defineMacro("__fnabs", "__builtin_ppc_fnabs");
+  Builder.defineMacro("__fnabss", "__builtin_ppc_fnabss");
   Builder.defineMacro("__builtin_maxfe", "__builtin_ppc_maxfe");
   Builder.defineMacro("__builtin_maxfl", "__builtin_ppc_maxfl");
   Builder.defineMacro("__builtin_maxfs", "__builtin_ppc_maxfs");

diff  --git a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.c 
b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.c
new file mode 100644
index 0..2889f38f01068
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.c
@@ -0,0 +1,36 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
+// RUN:   -emit-llvm %s -target-cpu pwr8 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -target-cpu pwr8 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
+// RUN:   -emit-llvm %s -target-cpu pwr7 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -target-cpu pwr7 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
+// RUN:   -emit-llvm %s -target-cpu pwr6 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
+// RUN:   -emit-llvm %s -target-cpu pwr6 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -target-cpu pwr6 -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -target-cpu pwr6 -o - | FileCheck %s
+
+extern float f;
+extern double d;
+
+// CHECK-LABEL: @test_fnabs(
+// CHECK:   [[TMP0:%.*]] = load double, ptr @d
+// CHECK-NEXT:  [[TMP1:%.*]] = call double @llvm.ppc.fnabs(double [[TMP0]])
+// CHECK-NEXT:  ret double [[TMP1]]
+double test_fnabs() {
+  return __fnabs (d);
+}
+
+// CHECK-LABEL: @test_fnabss(
+// CHECK:   [[TMP0:%.*]] = load float, ptr @f
+// CHECK-NEXT:  [[TMP1:%.*]] = call float @llvm.ppc.fnabss(float [[TMP0]])
+// CHECK-NEXT:  ret float [[TMP1]]
+float test_fnabss() {
+  return __fnabss (f);
+}

diff  --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 8082b457242de..963f4c2dc475c 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1801,6 +1801,12 @@ let TargetPrefix = "ppc" in {
   def int_ppc_test_data_class_f : Intrinsic<[llvm_i32_ty],
 [llvm_float_ty, llvm_i32_ty],

[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)

2024-03-18 Thread Amy Kwan via cfe-commits



@@ -141,46 +149,98 @@ PPC_LNX_CPU("power10",47)
   #define AIX_BUILTIN_PPC_TRUE 1
   #define AIX_BUILTIN_PPC_FALSE 0
   #define USE_SYS_CONF 2
-
-  // Supported COMPARE_OP values.
-  #define COMP_EQ  0
-
+  #define SYS_CALL 3
 #endif
 
 // The value of SUPPORT_METHOD can be AIX_BUILTIN_PPC_TRUE,
-// AIX_BUILTIN_PPC_FALSE, or USE_SYS_CONF.
-// When the value of SUPPORT_METHOD is USE_SYS_CONF, the return value
-// depends on the result of comparing the data member of
-// _system_configuration specified by INDEX with a certain value.
+// AIX_BUILTIN_PPC_FALSE, USE_SYS_CONF, SYS_CALL.
+// When the value of SUPPORT_METHOD is set to USE_SYS_CONF, the return value
+// depends on comparing VALUE with the specified data member of
+// _system_configuration at INDEX, where the data member is masked by Mask.
+// When the SUPPORT_METHOD value is set to SYS_CALL, the return value depends
+// on comparing a VALUE with the return value of calling `getsystemcfg`
+//  with the parameter INDEX, which is then masked by Mask.
+// AIX_BUILTIN_PPC_TRUE and AIX_BUILTIN_PPC_FALSE are for features
+// that are supported or unsupported on all systems respectively.
 
 #ifndef PPC_AIX_CPU
   #define PPC_AIX_CPU(NAME, SUPPORT_METHOD, INDEX, COMPARE_OP, VALUE)
 #endif
 
-// __builtin_cpu_is() is supported only on Power7 and up.
-PPC_AIX_CPU("power4",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppc970",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("power5",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("power5+",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("power6",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppc-cell-be",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("power6x",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppca2",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppc405",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppc440",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppc464",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("ppc476",AIX_BUILTIN_PPC_FALSE,0,0,0)
-PPC_AIX_CPU("power7",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,COMP_EQ,AIX_PPC7_VALUE)
-PPC_AIX_CPU("power8",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,COMP_EQ,AIX_PPC8_VALUE)
-PPC_AIX_CPU("power9",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,COMP_EQ,AIX_PPC9_VALUE)
-PPC_AIX_CPU("power10",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,COMP_EQ,AIX_PPC10_VALUE)
+// __builtin_cpu_is() and __builtin_cpu_supports() are supported only on 
Power7 and up.
+PPC_AIX_CPU("power4",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppc970",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("power5",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("power5+",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("power6",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppc-cell-be",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("power6x",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppca2",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppc405",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppc440",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppc464",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("ppc476",AIX_BUILTIN_PPC_FALSE,0,CmpInst::Predicate(),0)
+PPC_AIX_CPU("power7",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,ICmpInst::ICMP_EQ,AIX_PPC7_VALUE)
+PPC_AIX_CPU("power8",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,ICmpInst::ICMP_EQ,AIX_PPC8_VALUE)
+PPC_AIX_CPU("power9",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,ICmpInst::ICMP_EQ,AIX_PPC9_VALUE)
+PPC_AIX_CPU("power10",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,ICmpInst::ICMP_EQ,AIX_PPC10_VALUE)
 #undef PPC_AIX_CPU
 
+#ifndef PPC_AIX_FEATURE
+#define PPC_AIX_FEATURE(NAME,DESC,SUPPORT_METHOD,INDEX,MASK,COMPARE_OP,VALUE)
+#endif
+
+PPC_AIX_FEATURE("4xxmac","4xx CPU has a Multiply 
Accumulator",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("altivec","CPU has a SIMD/Vector 
Unit",USE_SYS_CONF,AIX_SYSCON_VMX_IDX,0,ICmpInst::ICMP_UGT,0)
+PPC_AIX_FEATURE("arch_2_05","CPU supports ISA 205 (eg, 
POWER6)",AIX_BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("arch_2_06","CPU supports ISA 206 (eg, 
POWER7)",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC7_VALUE)
+PPC_AIX_FEATURE("arch_2_07","CPU supports ISA 207 (eg, 
POWER8)",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC8_VALUE)
+PPC_AIX_FEATURE("arch_3_00","CPU supports ISA 30 (eg, POWER9)", 
USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC9_VALUE)
+PPC_AIX_FEATURE("arch_3_1","CPU supports ISA 31 (eg, POWER10)", 
USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC10_VALUE)
+PPC_AIX_FEATURE("booke","CPU supports the Embedded ISA 
category",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("cellbe","CPU has a CELL broadband 
engine",AIX_BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0)
+PPC_AIX_FEATURE("darn","CPU supports the darn (deliver a random number) 
instruction",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC10_VALUE)
+PPC_AIX_FEATURE("dfp",

[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)

2024-03-18 Thread Amy Kwan via cfe-commits



@@ -16570,32 +16570,53 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 
 #include "llvm/TargetParser/PPCTargetParser.def"
   auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned CompOp,
+ unsigned Mask, CmpInst::Predicate CompOp,
  unsigned OpValue) -> Value * {
 if (SupportMethod == AIX_BUILTIN_PPC_FALSE)
   return llvm::ConstantInt::getFalse(ConvertType(E->getType()));
 
 if (SupportMethod == AIX_BUILTIN_PPC_TRUE)
   return llvm::ConstantInt::getTrue(ConvertType(E->getType()));
 
-assert(SupportMethod <= USE_SYS_CONF && "Invalid value for 
SupportMethod.");
-assert((CompOp == COMP_EQ) && "Only equal comparisons are supported.");
+assert(SupportMethod <= SYS_CALL && "Invalid value for SupportMethod.");
+
+llvm::Value *FieldValue = nullptr;
+if (SupportMethod == USE_SYS_CONF) {
+  llvm::Type *STy = llvm::StructType::get(PPC_SYSTEMCONFIG_TYPE);
+  llvm::Constant *SysConf =
+  CGM.CreateRuntimeVariable(STy, "_system_configuration");
+
+  // Grab the appropriate field from _system_configuration.
+  llvm::Value *Idxs[] = {ConstantInt::get(Int32Ty, 0),
+ ConstantInt::get(Int32Ty, FieldIdx)};
+
+  FieldValue = Builder.CreateGEP(STy, SysConf, Idxs);
+  FieldValue = Builder.CreateAlignedLoad(Int32Ty, FieldValue,
+ CharUnits::fromQuantity(4));
+} else if (SupportMethod == SYS_CALL) {
+  llvm::FunctionType *FTy =
+  llvm::FunctionType::get(Int64Ty, Int32Ty, false);
+  llvm::FunctionCallee Func =
+  CGM.CreateRuntimeFunction(FTy, "getsystemcfg");
+
+  FieldValue =
+  Builder.CreateCall(Func, {ConstantInt::get(Int32Ty, FieldIdx)});
+}
+assert((FieldValue != nullptr) &&

amy-kwan wrote:

I think we can probably just do `assert(FieldValue && "SupportMethod value is 
not defined in PPCTargetParser.def.");`?

https://github.com/llvm/llvm-project/pull/82809
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[clang] [clang] move -Wcast-function-type under -Wextra (PR #77178)

2024-03-20 Thread Amy Kwan via cfe-commits


amy-kwan wrote:

I believe this patch is causing some issues on two PPC bots. Would you be able 
to help take a look?
https://lab.llvm.org/buildbot/#/builders/57/builds/33601/steps/5/logs/stdio
https://lab.llvm.org/buildbot/#/builders/36/builds/43759/steps/12/logs/stdio

https://github.com/llvm/llvm-project/pull/77178
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[clang] [clang] move -Wcast-function-type under -Wextra (PR #77178)

2024-03-21 Thread Amy Kwan via cfe-commits


amy-kwan wrote:

> I'm confused as to how this code ever compiled in the first place... In each 
> case, this is C++ code that's failing:
> 
> ```
> /home/buildbots/llvm-external-buildbots/workers/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm-project/compiler-rt/lib/sanitizer_common/sanitizer_posix_libcdep.cpp:219:25:
>  error: cast from 'SignalHandlerType' (aka 'void (*)(int, void *, void *)') 
> to 'sa_sigaction_t' (aka 'void (*)(int, siginfo_t *, void *)') converts to 
> incompatible function type [-Werror,-Wcast-function-type-strict]
> 
> /home/buildbots/llvm-external-buildbots/workers/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm-project/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp:437:4:
>  error: cast from 'void (*)()' to 'void (*)(void *)' converts to incompatible 
> function type [-Werror,-Wcast-function-type-strict]
> 
> /home/buildbots/llvm-external-buildbots/workers/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm-project/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp:460:54:
>  error: cast from 'void (*)(void *)' to 'void (*)()' converts to incompatible 
> function type [-Werror,-Wcast-function-type-strict]
> ```
> 
> All of which is being compiled in `-std=c++17` and none of which are valid in 
> C++ and the behavior is the same between Clang 18, trunk, and GCC: 
> https://godbolt.org/z/WY9zvsa8z
> 
> @amy-kwan we may need some help from you with investigating this; but in the 
> meantime, this commit can be reverted to get the bots back to green if that's 
> blocking you.

@AaronBallman Sounds good. I am ok with this commit being reverted and we can 
investigate on the side.


https://github.com/llvm/llvm-project/pull/77178
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[clang] Split -Wcast-function-type into a separate group (PR #86131)

2024-03-21 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan approved this pull request.

I've also tested this locally, and it resolves the issue I saw earlier on the 
PPC bots.

https://github.com/llvm/llvm-project/pull/86131
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[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level by heuristic (PR #84132)

2024-03-21 Thread Amy Kwan via cfe-commits



@@ -4958,6 +4958,10 @@ def maix_small_local_exec_tls : Flag<["-"], 
"maix-small-local-exec-tls">,
"where the offset from the TLS base is encoded as an "
"immediate operand (AIX 64-bit only). "
"This access sequence is not used for variables larger than 32KB.">;
+def maix_shared_library_tls_model_heuristic : Flag<["-"], 
"maix-shared-library-tls-model-heuristic">,
+  Group,
+  HelpText<"For shared library loaded with the main program, use heuristic to "
+   "tune TLS model at function level (AIX 64-bit only).">;

amy-kwan wrote:

```suggestion
  HelpText<"For shared library loaded with the main program, use heuristics to "
   "tune the TLS model at the function level (AIX 64-bit only).">;
```

https://github.com/llvm/llvm-project/pull/84132
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[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level by heuristic (PR #84132)

2024-03-21 Thread Amy Kwan via cfe-commits



@@ -3369,6 +3369,48 @@ SDValue 
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
   bool Is64Bit = Subtarget.isPPC64();
   bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
   TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+  // Initialize heuristic setting lazily:
+  // (1) Use initial-exec for single TLS var reference within current function.
+  // (2) Use local-dynamic for multiple TLS var references within current func.
+  PPCFunctionInfo *FuncInfo =
+  DAG.getMachineFunction().getInfo();
+  if (Subtarget.hasAIXShLibTLSModelHeuristic() &&
+  !FuncInfo->isAIXFuncUseInitDone()) {
+std::set TLSGV;
+for (SDNode &Node : DAG.allnodes()) {
+  SDNode *N = &Node;
+  if (N->getOpcode() == ISD::GlobalTLSAddress) {
+if (GlobalAddressSDNode *GA = cast(N)) {
+  const GlobalValue *GV = GA->getGlobal();
+  TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+  if (Model == TLSModel::InitialExec ||
+  Model == TLSModel::LocalDynamic) {
+TLSGV.insert(GV);
+  }
+}
+  }
+}
+LLVM_DEBUG(dbgs() << format("TLSGV count:%d\n", TLSGV.size()));
+if (TLSGV.size() == 1) {
+  FuncInfo->setAIXFuncUseTLSIE();
+} else if (TLSGV.size() > 1) {
+  FuncInfo->setAIXFuncUseTLSLD();
+}
+FuncInfo->setAIXFuncUseInitDone();
+  }
+
+  if (FuncInfo->isAIXFuncUseTLSLD()) {
+LLVM_DEBUG(
+dbgs() << DAG.getMachineFunction().getName()
+   << " function use TLS-LD model for TLS IE/LD accesses.\n");
+Model = TLSModel::LocalDynamic;
+  } else if (FuncInfo->isAIXFuncUseTLSIE()) {
+LLVM_DEBUG(
+dbgs() << DAG.getMachineFunction().getName()
+   << " function use TLS-IE model for TLS IE/LD accesses.\n");

amy-kwan wrote:

Minor nit on comments.
```suggestion
   << " function is using the TLS-LD model for TLS IE/LD 
accesses.\n");
Model = TLSModel::LocalDynamic;
  } else if (FuncInfo->isAIXFuncUseTLSIE()) {
LLVM_DEBUG(
dbgs() << DAG.getMachineFunction().getName()
   << " function is using the TLS-IE model for TLS IE/LD 
accesses.\n");
```

https://github.com/llvm/llvm-project/pull/84132
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[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level by heuristic (PR #84132)

2024-03-21 Thread Amy Kwan via cfe-commits



@@ -3369,6 +3369,48 @@ SDValue 
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
   bool Is64Bit = Subtarget.isPPC64();
   bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
   TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+  // Initialize heuristic setting lazily:
+  // (1) Use initial-exec for single TLS var reference within current function.
+  // (2) Use local-dynamic for multiple TLS var references within current func.
+  PPCFunctionInfo *FuncInfo =
+  DAG.getMachineFunction().getInfo();
+  if (Subtarget.hasAIXShLibTLSModelHeuristic() &&
+  !FuncInfo->isAIXFuncUseInitDone()) {
+std::set TLSGV;
+for (SDNode &Node : DAG.allnodes()) {
+  SDNode *N = &Node;
+  if (N->getOpcode() == ISD::GlobalTLSAddress) {
+if (GlobalAddressSDNode *GA = cast(N)) {
+  const GlobalValue *GV = GA->getGlobal();
+  TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+  if (Model == TLSModel::InitialExec ||
+  Model == TLSModel::LocalDynamic) {
+TLSGV.insert(GV);
+  }
+}
+  }
+}
+LLVM_DEBUG(dbgs() << format("TLSGV count:%d\n", TLSGV.size()));

amy-kwan wrote:

`TLSGV.size()` is used more than once and can be pulled out.

https://github.com/llvm/llvm-project/pull/84132
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[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level by heuristic (PR #84132)

2024-03-21 Thread Amy Kwan via cfe-commits



@@ -848,6 +848,14 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr 
*MI) {
 return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE;
   if (Model == TLSModel::InitialExec)
 return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSIE;
+  // On AIX, TLS model heuristic may have turned local-dynamic access into
+  // initial-exec access.

amy-kwan wrote:

```suggestion
  // On AIX, TLS model heuristics may have turned local-dynamic accesses 
into
  // initial-exec accesses.
```

https://github.com/llvm/llvm-project/pull/84132
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[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level by heuristic (PR #84132)

2024-03-21 Thread Amy Kwan via cfe-commits



@@ -848,6 +848,14 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr 
*MI) {
 return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE;
   if (Model == TLSModel::InitialExec)
 return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSIE;
+  // On AIX, TLS model heuristic may have turned local-dynamic access into
+  // initial-exec access.
+  PPCFunctionInfo *FuncInfo = MF->getInfo();
+  if (Model == TLSModel::LocalDynamic && FuncInfo->isAIXFuncUseTLSIE()) {
+LLVM_DEBUG(
+dbgs() << "Current function use IE access for default LD vars.\n");

amy-kwan wrote:

```suggestion
dbgs() << "Current function uses IE access for default LD vars.\n");
```

https://github.com/llvm/llvm-project/pull/84132
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[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level by heuristic (PR #84132)

2024-03-21 Thread Amy Kwan via cfe-commits



@@ -3369,6 +3369,48 @@ SDValue 
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
   bool Is64Bit = Subtarget.isPPC64();
   bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
   TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+  // Initialize heuristic setting lazily:
+  // (1) Use initial-exec for single TLS var reference within current function.
+  // (2) Use local-dynamic for multiple TLS var references within current func.

amy-kwan wrote:

```suggestion
  // (1) Use initial-exec for single TLS var references within current function.
  // (2) Use local-dynamic for multiple TLS var references within current 
function.
```
Just wanted to be consistent for the comment.

https://github.com/llvm/llvm-project/pull/84132
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[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level by heuristic (PR #84132)

2024-03-21 Thread Amy Kwan via cfe-commits



@@ -3369,6 +3369,48 @@ SDValue 
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
   bool Is64Bit = Subtarget.isPPC64();
   bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
   TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+  // Initialize heuristic setting lazily:
+  // (1) Use initial-exec for single TLS var reference within current function.
+  // (2) Use local-dynamic for multiple TLS var references within current func.
+  PPCFunctionInfo *FuncInfo =
+  DAG.getMachineFunction().getInfo();
+  if (Subtarget.hasAIXShLibTLSModelHeuristic() &&
+  !FuncInfo->isAIXFuncUseInitDone()) {
+std::set TLSGV;
+for (SDNode &Node : DAG.allnodes()) {
+  SDNode *N = &Node;
+  if (N->getOpcode() == ISD::GlobalTLSAddress) {
+if (GlobalAddressSDNode *GA = cast(N)) {
+  const GlobalValue *GV = GA->getGlobal();
+  TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+  if (Model == TLSModel::InitialExec ||
+  Model == TLSModel::LocalDynamic) {

amy-kwan wrote:

Can omit { } for conditions with one line inside (here and below).

https://github.com/llvm/llvm-project/pull/84132
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[clang] Split -Wcast-function-type into a separate group (PR #86131)

2024-03-21 Thread Amy Kwan via cfe-commits


amy-kwan wrote:

Thanks @AaronBallman.
Not sure how I missed it, but I just noticed in my local build of 
check-runtimes/check-all. This is also present on the following bot:
https://lab.llvm.org/buildbot/#/builders/57/builds/33656


https://github.com/llvm/llvm-project/pull/86131
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[clang] Split -Wcast-function-type into a separate group (PR #86131)

2024-03-22 Thread Amy Kwan via cfe-commits


amy-kwan wrote:

I have also found one more that is not related to the sanitizers, but when 
`llvm-project/llvm/lib/IR/Core.cpp`: 
https://lab.llvm.org/buildbot/#/builders/36/builds/43840/steps/12/logs/stdio

Would it be possible to also resolve this one, as well?


https://github.com/llvm/llvm-project/pull/86131
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[clang] Split -Wcast-function-type into a separate group (PR #86131)

2024-03-22 Thread Amy Kwan via cfe-commits


amy-kwan wrote:

Thanks @Abhinkop for the patch! I have approved the compiler-rt patch since it 
does appear to resolve the check-runtimes/check-all issue for the asan test 
case.

If you also would like me to test a follow up patch for 
`llvm-project/llvm/lib/IR/Core.cpp`, I would be happy to do so, as well.

https://github.com/llvm/llvm-project/pull/86131
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[clang] Split -Wcast-function-type into a separate group (PR #86131)

2024-03-22 Thread Amy Kwan via cfe-commits


amy-kwan wrote:

> @amy-kwan I'm looking at it now. I will most probably raise a review some 
> time later in the evening or tomorrow if I am not able to complete it today.

Sounds good, thank you so much, @Abhinkop!

https://github.com/llvm/llvm-project/pull/86131
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[clang] Split -Wcast-function-type into a separate group (PR #86131)

2024-03-25 Thread Amy Kwan via cfe-commits


amy-kwan wrote:

Hi @Abhinkop!
I was wondering if there was any progress regarding the patch to resolve the 
stage 2 failure, as our bot is still red 
(https://lab.llvm.org/buildbot/#/builders/36/builds/43929/steps/12/logs/stdio).
Please let me know if you would also like me to test any patches, as well. 

https://github.com/llvm/llvm-project/pull/86131
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[clang] [clang-repl] Factor out CreateJITBuilder() and allow specialization in derived classes (PR #84461)

2024-03-25 Thread Amy Kwan via cfe-commits

Stefan =?utf-8?q?Gränitz?= 
Message-ID:
In-Reply-To: 


amy-kwan wrote:

Hi @weliveindetail!
I just wanted to give a heads up, that I believe 
13078cbc3eeb0ae91c370ce0f604f7165b26e0c8 is causing a failure of the 
clang-ppc64le-rhel bot: 
https://lab.llvm.org/buildbot/#/builders/57/builds/33764/steps/7/logs/stdio

Would you be able to help take a look?

https://github.com/llvm/llvm-project/pull/84461
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[clang] Fix printing of templated records. (PR #86339)

2024-03-26 Thread Amy Kwan via cfe-commits


amy-kwan wrote:

This also fails on PPC, as well: 
https://lab.llvm.org/buildbot/#/builders/36/builds/43998/steps/12/logs/stdio

https://github.com/llvm/llvm-project/pull/86339
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[clang] [llvm] [PowerPC] Tune AIX shared library TLS model at function level by heuristic (PR #84132)

2024-04-02 Thread Amy Kwan via cfe-commits



@@ -3369,6 +3369,59 @@ SDValue 
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
   bool Is64Bit = Subtarget.isPPC64();
   bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
   TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+  // Initialize TLS model opt setting lazily:

amy-kwan wrote:

This primarily sets the TLS model per function. Not sure if it is possible, but 
can it/does it make sense for this part to be separated into its own function?

https://github.com/llvm/llvm-project/pull/84132
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits



@@ -0,0 +1,83 @@
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc970\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc-cell-be\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppca2\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc405\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc440\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc464\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc476\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power4\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power5\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power5+\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power6\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power6x\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power7\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s -DVALUE=32768 \
+// RUN:   --check-prefixes=CHECKOP
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power8\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s -DVALUE=65536 \
+// RUN:   --check-prefixes=CHECKOP
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power9\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s -DVALUE=131072\
+// RUN:   --check-prefixes=CHECKOP
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power10\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s -DVALUE=262144 \
+// RUN:   --check-prefixes=CHECKOP
+
+// CHECKBOOL: define i32 @main() #0 {
+// CHECKBOOL-NEXT: entry:
+// CHECKBOOL-NEXT:   %retval = alloca i32, align 4
+// CHECKBOOL-NEXT:   store i32 0, ptr %retval, align 4
+// CHECKBOOL-NEXT:   ret i32 0 
+// CHECKBOOL-NEXT: }
+
+// CHECKOP: @_system_configuration = external global { i32, i32, i32 }
+// CHECKOP:   define i32 @main() #0 {
+// CHECKOP-NEXT: entry:
+// CHECKOP-NEXT:   %retval = alloca i32, align 4
+// CHECKOP-NEXT:   store i32 0, ptr %retval, align 4
+// CHECKOP-NEXT:   %0 = load i32, ptr getelementptr inbounds ({ i32, i32, i32 
}, ptr @_system_configuration, i32 0, i32 1), align 4

amy-kwan wrote:

Do we need a test case for when we create the `and` (in 16650 in 
`CGBuiltin.cpp` for the mask, as well?

https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits



@@ -126,4 +126,57 @@ PPC_LNX_CPU("power10",47)
 #undef PPC_LNX_DEFINE_OFFSETS
 #undef PPC_LNX_FEATURE
 #undef PPC_LNX_CPU
+
+// Definition of following value are found in the AIX header file 
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF

amy-kwan wrote:

Can we indent the `#define` lines?

https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits



@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 
+#include "llvm/TargetParser/PPCTargetParser.def"
+  auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op,
+  unsigned Op_Value) -> Value * {
+Value *Value1 = FieldValue;
+if (Mask)
+  Value1 = Builder.CreateAnd(Value1, Mask);
+assert((Op == OP_EQ) && "Only support equal comparision");
+return Builder.CreateICmp(ICmpInst::ICMP_EQ, FieldValue,
+  ConstantInt::get(Int32Ty, Op_Value));
+  };
+
+  auto ConvBuiltinCpu = [&](unsigned SupportOP, unsigned FieldIdx,
+unsigned Op_Mask, unsigned Op,
+unsigned Op_Value) -> Value * {
+if (SupportOP == AIX_BUILTIN_PPC_FALSE)
+  return llvm::ConstantInt::getFalse(ConvertType(E->getType()));
+
+if (SupportOP == AIX_BUILTIN_PPC_TRUE)
+  return llvm::ConstantInt::getTrue(ConvertType(E->getType()));
+
+assert(SupportOP <= COMP_OP && "Invalid value for SupportOP.");
+llvm::Type *STy = llvm::StructType::get(PPC_SYSTEMCONFIG_TYPE);
+
+llvm::Constant *SysConf =
+CGM.CreateRuntimeVariable(STy, "_system_configuration");
+
+// Grab the appropriate field from _system_configuration.
+llvm::Value *Idxs[] = {ConstantInt::get(Int32Ty, 0),
+   ConstantInt::get(Int32Ty, FieldIdx)};
+
+llvm::Value *FieldValue = Builder.CreateGEP(STy, SysConf, Idxs);
+FieldValue = Builder.CreateAlignedLoad(Int32Ty, FieldValue,
+   CharUnits::fromQuantity(4));
+
+return GetOpRes(FieldValue, Op_Mask, Op, Op_Value);
+  };
+
   switch (BuiltinID) {
   default: return nullptr;
 
   case Builtin::BI__builtin_cpu_is: {
 const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
 StringRef CPUStr = cast(CPUExpr)->getString();
-unsigned NumCPUID = StringSwitch(CPUStr)
+llvm::Triple Triple = getTarget().getTriple();
+if (Triple.isOSLinux()) {
+  unsigned NumCPUID = StringSwitch(CPUStr)
 #define PPC_LNX_CPU(Name, NumericID) .Case(Name, NumericID)
 #include "llvm/TargetParser/PPCTargetParser.def"
-.Default(-1U);
+  .Default(-1U);
 assert(NumCPUID < -1U && "Invalid CPU name. Missed by SemaChecking?");
 Value *Op0 = llvm::ConstantInt::get(Int32Ty, PPC_FAWORD_CPUID);
 llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_fixed_addr_ld);
 Value *TheCall = Builder.CreateCall(F, {Op0}, "cpu_is");
 return Builder.CreateICmpEQ(TheCall,
 llvm::ConstantInt::get(Int32Ty, NumCPUID));
+} else if (Triple.isOSAIX()) {
+  unsigned IsCpuSupport, FieldIdx, CpuIdMask, CpuIdOp, CpuIdValue;
+  typedef std::tuple
+  CPUType;
+  std::tie(IsCpuSupport, FieldIdx, CpuIdMask, CpuIdOp, CpuIdValue) =
+  static_cast(StringSwitch(CPUStr)
+#define PPC_AIX_CPU(NAME, SUPPORT, MASK, INDEX, OP, VALUE) 
\

amy-kwan wrote:

```suggestion
#define PPC_AIX_CPU(NAME, SUPPORT, MASK, INDEX, COMPARE_OP, VALUE)  
   \
```
It seems like `OP` should be called a compare op (here and throughout the 
patch).

https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits



@@ -126,4 +126,57 @@ PPC_LNX_CPU("power10",47)
 #undef PPC_LNX_DEFINE_OFFSETS
 #undef PPC_LNX_FEATURE
 #undef PPC_LNX_CPU
+
+// Definition of following value are found in the AIX header file 
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF
+#define AIX_SYSCON_IMPL_IDX 1
+#define AIX_PPC7_VALUE 0x8000
+#define AIX_PPC8_VALUE 0x0001
+#define AIX_PPC9_VALUE 0x0002
+#define AIX_PPC10_VALUE 0x0004
+
+#define AIX_BUILTIN_PPC_TRUE 1
+#define AIX_BUILTIN_PPC_FALSE 0
+#define COMP_OP 2

amy-kwan wrote:

As discussed previously with the squad, we may want to rename these names if we 
can think of a better name to better represent these.

https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits



@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 
+#include "llvm/TargetParser/PPCTargetParser.def"
+  auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op,
+  unsigned Op_Value) -> Value * {
+Value *Value1 = FieldValue;
+if (Mask)
+  Value1 = Builder.CreateAnd(Value1, Mask);
+assert((Op == OP_EQ) && "Only support equal comparision");
+return Builder.CreateICmp(ICmpInst::ICMP_EQ, FieldValue,
+  ConstantInt::get(Int32Ty, Op_Value));
+  };
+
+  auto ConvBuiltinCpu = [&](unsigned SupportOP, unsigned FieldIdx,
+unsigned Op_Mask, unsigned Op,
+unsigned Op_Value) -> Value * {
+if (SupportOP == AIX_BUILTIN_PPC_FALSE)
+  return llvm::ConstantInt::getFalse(ConvertType(E->getType()));
+
+if (SupportOP == AIX_BUILTIN_PPC_TRUE)
+  return llvm::ConstantInt::getTrue(ConvertType(E->getType()));
+
+assert(SupportOP <= COMP_OP && "Invalid value for SupportOP.");
+llvm::Type *STy = llvm::StructType::get(PPC_SYSTEMCONFIG_TYPE);
+
+llvm::Constant *SysConf =
+CGM.CreateRuntimeVariable(STy, "_system_configuration");
+
+// Grab the appropriate field from _system_configuration.
+llvm::Value *Idxs[] = {ConstantInt::get(Int32Ty, 0),
+   ConstantInt::get(Int32Ty, FieldIdx)};
+
+llvm::Value *FieldValue = Builder.CreateGEP(STy, SysConf, Idxs);
+FieldValue = Builder.CreateAlignedLoad(Int32Ty, FieldValue,
+   CharUnits::fromQuantity(4));
+
+return GetOpRes(FieldValue, Op_Mask, Op, Op_Value);
+  };
+
   switch (BuiltinID) {
   default: return nullptr;
 
   case Builtin::BI__builtin_cpu_is: {
 const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts();
 StringRef CPUStr = cast(CPUExpr)->getString();
-unsigned NumCPUID = StringSwitch(CPUStr)
+llvm::Triple Triple = getTarget().getTriple();
+if (Triple.isOSLinux()) {
+  unsigned NumCPUID = StringSwitch(CPUStr)
 #define PPC_LNX_CPU(Name, NumericID) .Case(Name, NumericID)
 #include "llvm/TargetParser/PPCTargetParser.def"
-.Default(-1U);
+  .Default(-1U);
 assert(NumCPUID < -1U && "Invalid CPU name. Missed by SemaChecking?");
 Value *Op0 = llvm::ConstantInt::get(Int32Ty, PPC_FAWORD_CPUID);
 llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_fixed_addr_ld);
 Value *TheCall = Builder.CreateCall(F, {Op0}, "cpu_is");
 return Builder.CreateICmpEQ(TheCall,
 llvm::ConstantInt::get(Int32Ty, NumCPUID));
+} else if (Triple.isOSAIX()) {
+  unsigned IsCpuSupport, FieldIdx, CpuIdMask, CpuIdOp, CpuIdValue;
+  typedef std::tuple
+  CPUType;
+  std::tie(IsCpuSupport, FieldIdx, CpuIdMask, CpuIdOp, CpuIdValue) =
+  static_cast(StringSwitch(CPUStr)
+#define PPC_AIX_CPU(NAME, SUPPORT, MASK, INDEX, OP, VALUE) 
\
+  .Case(NAME, {SUPPORT, MASK, INDEX, OP, VALUE})
+#include "llvm/TargetParser/PPCTargetParser.def"
+  );
+  return ConvBuiltinCpu(IsCpuSupport, FieldIdx, CpuIdMask, CpuIdOp,

amy-kwan wrote:

Rename `CpuIdOp` -> `CompareOp`.


https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-07 Thread Amy Kwan via cfe-commits



@@ -126,4 +126,57 @@ PPC_LNX_CPU("power10",47)
 #undef PPC_LNX_DEFINE_OFFSETS
 #undef PPC_LNX_FEATURE
 #undef PPC_LNX_CPU
+
+// Definition of following value are found in the AIX header file 
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF
+#define AIX_SYSCON_IMPL_IDX 1
+#define AIX_PPC7_VALUE 0x8000
+#define AIX_PPC8_VALUE 0x0001
+#define AIX_PPC9_VALUE 0x0002
+#define AIX_PPC10_VALUE 0x0004
+
+#define AIX_BUILTIN_PPC_TRUE 1
+#define AIX_BUILTIN_PPC_FALSE 0
+#define COMP_OP 2
+
+#define OP_EQ  0
+
+#endif
+
+//The value of SUPPORT is COMP_OP, it means the feature depend on the 
V(INDEX)&MASK OP VALUE
+//If the value of MASK is zero, it means we do not need to do mask, just check 
V(INDEX) OP VALUE.
+

amy-kwan wrote:

Remove this new line, to clearly show that the comment is applicable to this 
define specifically.

https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-08 Thread Amy Kwan via cfe-commits



@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 
+#include "llvm/TargetParser/PPCTargetParser.def"
+  auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op,
+  unsigned Op_Value) -> Value * {
+Value *Value1 = FieldValue;
+if (Mask)
+  Value1 = Builder.CreateAnd(Value1, Mask);
+assert((Op == OP_EQ) && "Only support equal comparision");
+return Builder.CreateICmp(ICmpInst::ICMP_EQ, FieldValue,
+  ConstantInt::get(Int32Ty, Op_Value));
+  };
+
+  auto ConvBuiltinCpu = [&](unsigned SupportOP, unsigned FieldIdx,
+unsigned Op_Mask, unsigned Op,
+unsigned Op_Value) -> Value * {
+if (SupportOP == AIX_BUILTIN_PPC_FALSE)
+  return llvm::ConstantInt::getFalse(ConvertType(E->getType()));
+
+if (SupportOP == AIX_BUILTIN_PPC_TRUE)
+  return llvm::ConstantInt::getTrue(ConvertType(E->getType()));
+
+assert(SupportOP <= COMP_OP && "Invalid value for SupportOP.");

amy-kwan wrote:

Please move this assert to the top.

https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-08 Thread Amy Kwan via cfe-commits



@@ -10347,6 +10347,8 @@ def err_x86_builtin_tile_arg_duplicate : Error<
 
 def err_builtin_target_unsupported : Error<
   "builtin is not supported on this target">;
+def err_builtin_aix_os_unsupported : Error<
+  "this builtin is available only in AIX 7.2 and later operating systems">;

amy-kwan wrote:

```suggestion
  "builtin is available only in AIX 7.2 and later operating systems">;
```

https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-08 Thread Amy Kwan via cfe-commits



@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 
+#include "llvm/TargetParser/PPCTargetParser.def"
+  auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op,

amy-kwan wrote:

Combine these two lambdas into one lambda, and please document the lambda.

https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-08 Thread Amy Kwan via cfe-commits



@@ -904,8 +904,17 @@ bool PPCTargetInfo::validateCpuSupports(StringRef 
FeatureStr) const {
 }
 
 bool PPCTargetInfo::validateCpuIs(StringRef CPUName) const {
+  llvm::Triple Triple = getTriple();
+  if (Triple.isOSLinux()) {

amy-kwan wrote:

Can if we do something like:
```
if (Triple.isOSAIX()) {
. . . 
}
// Default Linux Behaviour
. . . 
```

https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-08 Thread Amy Kwan via cfe-commits



@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 
+#include "llvm/TargetParser/PPCTargetParser.def"
+  auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op,
+  unsigned Op_Value) -> Value * {
+Value *Value1 = FieldValue;
+if (Mask)
+  Value1 = Builder.CreateAnd(Value1, Mask);
+assert((Op == OP_EQ) && "Only support equal comparision");
+return Builder.CreateICmp(ICmpInst::ICMP_EQ, FieldValue,
+  ConstantInt::get(Int32Ty, Op_Value));
+  };
+
+  auto ConvBuiltinCpu = [&](unsigned SupportOP, unsigned FieldIdx,
+unsigned Op_Mask, unsigned Op,
+unsigned Op_Value) -> Value * {
+if (SupportOP == AIX_BUILTIN_PPC_FALSE)
+  return llvm::ConstantInt::getFalse(ConvertType(E->getType()));
+
+if (SupportOP == AIX_BUILTIN_PPC_TRUE)
+  return llvm::ConstantInt::getTrue(ConvertType(E->getType()));
+
+assert(SupportOP <= COMP_OP && "Invalid value for SupportOP.");
+llvm::Type *STy = llvm::StructType::get(PPC_SYSTEMCONFIG_TYPE);
+
+llvm::Constant *SysConf =
+CGM.CreateRuntimeVariable(STy, "_system_configuration");
+
+// Grab the appropriate field from _system_configuration.
+llvm::Value *Idxs[] = {ConstantInt::get(Int32Ty, 0),
+   ConstantInt::get(Int32Ty, FieldIdx)};
+
+llvm::Value *FieldValue = Builder.CreateGEP(STy, SysConf, Idxs);
+FieldValue = Builder.CreateAlignedLoad(Int32Ty, FieldValue,
+   CharUnits::fromQuantity(4));
+
+return GetOpRes(FieldValue, Op_Mask, Op, Op_Value);

amy-kwan wrote:

We should rename `Op` since `Op` seems overloaded and misleading in this 
context.

https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-08 Thread Amy Kwan via cfe-commits



@@ -0,0 +1,83 @@
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc970\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc-cell-be\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppca2\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc405\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc440\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc464\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc476\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power4\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power5\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power5+\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power6\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power6x\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power7\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s -DVALUE=32768 \
+// RUN:   --check-prefixes=CHECKOP

amy-kwan wrote:

This can be the default check, rather than a prefix.

https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-08 Thread Amy Kwan via cfe-commits



@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 
+#include "llvm/TargetParser/PPCTargetParser.def"
+  auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op,
+  unsigned Op_Value) -> Value * {
+Value *Value1 = FieldValue;
+if (Mask)
+  Value1 = Builder.CreateAnd(Value1, Mask);

amy-kwan wrote:

No need for Value1?


https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-08 Thread Amy Kwan via cfe-commits



@@ -0,0 +1,83 @@
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc970\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc-cell-be\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppca2\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc405\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc440\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc464\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"ppc476\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefix=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power4\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power5\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power5+\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power6\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL
+
+// RUN: echo "int main() { return __builtin_cpu_is(\"power6x\");}" > %t.c 
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %t.c | 
FileCheck %s \
+// RUN:   --check-prefixes=CHECKBOOL

amy-kwan wrote:

Change `BOOL` to `BUILTIN` or something similar.

https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)

2024-02-08 Thread Amy Kwan via cfe-commits



@@ -16542,22 +16542,75 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned 
BuiltinID,
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 
+#include "llvm/TargetParser/PPCTargetParser.def"
+  auto GetOpRes = [&](Value *FieldValue, unsigned Mask, unsigned Op,
+  unsigned Op_Value) -> Value * {
+Value *Value1 = FieldValue;
+if (Mask)
+  Value1 = Builder.CreateAnd(Value1, Mask);
+assert((Op == OP_EQ) && "Only support equal comparision");
+return Builder.CreateICmp(ICmpInst::ICMP_EQ, FieldValue,
+  ConstantInt::get(Int32Ty, Op_Value));
+  };
+
+  auto ConvBuiltinCpu = [&](unsigned SupportOP, unsigned FieldIdx,
+unsigned Op_Mask, unsigned Op,
+unsigned Op_Value) -> Value * {
+if (SupportOP == AIX_BUILTIN_PPC_FALSE)
+  return llvm::ConstantInt::getFalse(ConvertType(E->getType()));

amy-kwan wrote:

That is a good point. I am OK if you would like to keep the code as it is.

https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2024-02-12 Thread Amy Kwan via cfe-commits



@@ -145,9 +164,94 @@ namespace {
   .addImm(0);
 
 if (IsAIX) {
-  // The variable offset and region handle are copied in r4 and r3. The
-  // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX.
-  if (!IsTLSTPRelMI) {
+  if (IsTLSLDAIXMI) {
+// The relative order between the LoadOffset@toc node (for the
+// variable offset), and the .__tls_get_mod node is being tuned
+// here. It is better to put the LoadOffset@toc node after the 
call,
+// since the LoadOffset@toc node can use clobbers r4/r5. Search for
+// the pattern of two Load@toc nodes (either for the variable 
offset
+// or for the module handle), and then move the LoadOffset@toc node
+// right before the node that uses the OutReg of the .__tls_get_mod
+// node.
+unsigned LDTocOp =
+Is64Bit ? (IsLargeModel ? PPC::LDtocL : PPC::LDtoc)
+: (IsLargeModel ? PPC::LWZtocL : PPC::LWZtoc);
+if (!RegInfo.use_empty(OutReg)) {
+  std::set Uses;
+  // Collect all instructions that use the OutReg.
+  for (MachineOperand &MO : RegInfo.use_operands(OutReg))
+Uses.insert(MO.getParent());
+  // Find the first user (e.g.: lwax/stfdx) of the OutReg within 
the
+  // current BB.
+  MachineBasicBlock::iterator UseIter = MBB.begin();
+  for (MachineBasicBlock::iterator IE = MBB.end(); UseIter != IE;
+   ++UseIter)
+if (Uses.count(&*UseIter))
+  break;
+
+  // Additional handling is required when UserIter (the first user
+  // of OutReg) is pointing to a valid node. Check the pattern and
+  // do the movement if the pattern matches.
+  if (UseIter != MBB.end()) {
+// Collect associated Load@toc nodes. Use hasOneDef() to guard
+// against unexpected scenarios.
+std::set LoadFromTocs;
+for (MachineOperand &MO : UseIter->operands())
+  if (MO.isReg() && MO.isUse()) {
+Register MOReg = MO.getReg();
+if (RegInfo.hasOneDef(MOReg)) {
+  MachineInstr *Temp =
+  RegInfo.getOneDef(MOReg)->getParent();
+  // For the current TLSLDAIX node, get the Load@toc node
+  // for the InReg. Otherwise, Temp probably pointed to the
+  // LoadOffset@toc node that we would like to move.
+  if (Temp == &MI && RegInfo.hasOneDef(InReg))
+Temp = RegInfo.getOneDef(InReg)->getParent();
+  if (Temp->getOpcode() == LDTocOp)
+LoadFromTocs.insert(Temp);
+} else {
+  // FIXME: analyze this scenario if there is one.
+  LoadFromTocs.clear();
+  break;
+}
+  }
+
+// Check the two Load@toc: one should be _$TLSML, and the other
+// will be moved before the node that uses the OutReg of the
+// .__tls_get_mod node.
+if (LoadFromTocs.size() == 2) {
+  MachineBasicBlock::iterator TLSMLIter = MBB.end();
+  MachineBasicBlock::iterator OffsetIter = MBB.end();
+  // Make sure the two LoadFromTocs are within current BB, and
+  // one of them from the "_$TLSML" pseudo symbol, while the
+  // other from the variable.
+  for (MachineBasicBlock::iterator I = MBB.begin(),
+   IE = MBB.end();
+   I != IE; ++I)
+if (LoadFromTocs.count(&*I)) {
+  MachineOperand MO = I->getOperand(1);
+  if (MO.isGlobal() && MO.getGlobal()->hasName() &&
+  MO.getGlobal()->getName() == "_$TLSML")
+TLSMLIter = I;
+  else
+OffsetIter = I;
+}
+  // If both two iterators are valid, we should have identified
+  // the scenario, and do the movement.
+  if (TLSMLIter != MBB.end() && OffsetIter != MBB.end())
+OffsetIter->moveBefore(&*UseIter);
+}
+  }
+}
+// The module-handle is copied into r3. The copy is followed by
+// GETtlsMOD32AIX/GETtlsMOD64AIX.
+BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3)
+.addReg(InReg);
+// The call to .__tls_get_mod.
+BuildMI(MBB, I, DL, TII->get(Opc2), G

[clang] [llvm] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2024-02-12 Thread Amy Kwan via cfe-commits



@@ -145,9 +164,94 @@ namespace {
   .addImm(0);
 
 if (IsAIX) {
-  // The variable offset and region handle are copied in r4 and r3. The
-  // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX.
-  if (!IsTLSTPRelMI) {
+  if (IsTLSLDAIXMI) {
+// The relative order between the LoadOffset@toc node (for the
+// variable offset), and the .__tls_get_mod node is being tuned
+// here. It is better to put the LoadOffset@toc node after the 
call,
+// since the LoadOffset@toc node can use clobbers r4/r5. Search for
+// the pattern of two Load@toc nodes (either for the variable 
offset
+// or for the module handle), and then move the LoadOffset@toc node
+// right before the node that uses the OutReg of the .__tls_get_mod
+// node.
+unsigned LDTocOp =
+Is64Bit ? (IsLargeModel ? PPC::LDtocL : PPC::LDtoc)
+: (IsLargeModel ? PPC::LWZtocL : PPC::LWZtoc);
+if (!RegInfo.use_empty(OutReg)) {
+  std::set Uses;
+  // Collect all instructions that use the OutReg.
+  for (MachineOperand &MO : RegInfo.use_operands(OutReg))
+Uses.insert(MO.getParent());
+  // Find the first user (e.g.: lwax/stfdx) of the OutReg within 
the
+  // current BB.
+  MachineBasicBlock::iterator UseIter = MBB.begin();
+  for (MachineBasicBlock::iterator IE = MBB.end(); UseIter != IE;
+   ++UseIter)
+if (Uses.count(&*UseIter))
+  break;
+
+  // Additional handling is required when UserIter (the first user
+  // of OutReg) is pointing to a valid node. Check the pattern and
+  // do the movement if the pattern matches.
+  if (UseIter != MBB.end()) {
+// Collect associated Load@toc nodes. Use hasOneDef() to guard
+// against unexpected scenarios.
+std::set LoadFromTocs;
+for (MachineOperand &MO : UseIter->operands())
+  if (MO.isReg() && MO.isUse()) {
+Register MOReg = MO.getReg();
+if (RegInfo.hasOneDef(MOReg)) {
+  MachineInstr *Temp =
+  RegInfo.getOneDef(MOReg)->getParent();
+  // For the current TLSLDAIX node, get the Load@toc node
+  // for the InReg. Otherwise, Temp probably pointed to the
+  // LoadOffset@toc node that we would like to move.
+  if (Temp == &MI && RegInfo.hasOneDef(InReg))
+Temp = RegInfo.getOneDef(InReg)->getParent();
+  if (Temp->getOpcode() == LDTocOp)
+LoadFromTocs.insert(Temp);
+} else {
+  // FIXME: analyze this scenario if there is one.
+  LoadFromTocs.clear();
+  break;
+}
+  }
+
+// Check the two Load@toc: one should be _$TLSML, and the other
+// will be moved before the node that uses the OutReg of the
+// .__tls_get_mod node.
+if (LoadFromTocs.size() == 2) {
+  MachineBasicBlock::iterator TLSMLIter = MBB.end();
+  MachineBasicBlock::iterator OffsetIter = MBB.end();
+  // Make sure the two LoadFromTocs are within current BB, and
+  // one of them from the "_$TLSML" pseudo symbol, while the
+  // other from the variable.

amy-kwan wrote:

```suggestion
  // Make sure the two LoadFromTocs nodes are within the 
current BB, and
  // that one of them is from the "_$TLSML" pseudo symbol, 
while the
  // other from the variable.
```

https://github.com/llvm/llvm-project/pull/66316
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[clang] [llvm] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2024-02-12 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan commented:

I believe some of the test cases also require updates as a result of 
https://github.com/llvm/llvm-project/pull/80162.

https://github.com/llvm/llvm-project/pull/66316
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[clang] [llvm] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2024-02-12 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/66316
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[clang] [llvm] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2024-02-12 Thread Amy Kwan via cfe-commits



@@ -145,9 +164,94 @@ namespace {
   .addImm(0);
 
 if (IsAIX) {
-  // The variable offset and region handle are copied in r4 and r3. The
-  // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX.
-  if (!IsTLSTPRelMI) {
+  if (IsTLSLDAIXMI) {
+// The relative order between the LoadOffset@toc node (for the
+// variable offset), and the .__tls_get_mod node is being tuned
+// here. It is better to put the LoadOffset@toc node after the 
call,
+// since the LoadOffset@toc node can use clobbers r4/r5. Search for
+// the pattern of two Load@toc nodes (either for the variable 
offset
+// or for the module handle), and then move the LoadOffset@toc node
+// right before the node that uses the OutReg of the .__tls_get_mod
+// node.
+unsigned LDTocOp =
+Is64Bit ? (IsLargeModel ? PPC::LDtocL : PPC::LDtoc)
+: (IsLargeModel ? PPC::LWZtocL : PPC::LWZtoc);
+if (!RegInfo.use_empty(OutReg)) {
+  std::set Uses;
+  // Collect all instructions that use the OutReg.
+  for (MachineOperand &MO : RegInfo.use_operands(OutReg))
+Uses.insert(MO.getParent());
+  // Find the first user (e.g.: lwax/stfdx) of the OutReg within 
the
+  // current BB.
+  MachineBasicBlock::iterator UseIter = MBB.begin();
+  for (MachineBasicBlock::iterator IE = MBB.end(); UseIter != IE;
+   ++UseIter)
+if (Uses.count(&*UseIter))
+  break;
+
+  // Additional handling is required when UserIter (the first user
+  // of OutReg) is pointing to a valid node. Check the pattern and
+  // do the movement if the pattern matches.
+  if (UseIter != MBB.end()) {
+// Collect associated Load@toc nodes. Use hasOneDef() to guard
+// against unexpected scenarios.
+std::set LoadFromTocs;
+for (MachineOperand &MO : UseIter->operands())
+  if (MO.isReg() && MO.isUse()) {
+Register MOReg = MO.getReg();
+if (RegInfo.hasOneDef(MOReg)) {
+  MachineInstr *Temp =
+  RegInfo.getOneDef(MOReg)->getParent();
+  // For the current TLSLDAIX node, get the Load@toc node
+  // for the InReg. Otherwise, Temp probably pointed to the
+  // LoadOffset@toc node that we would like to move.
+  if (Temp == &MI && RegInfo.hasOneDef(InReg))
+Temp = RegInfo.getOneDef(InReg)->getParent();
+  if (Temp->getOpcode() == LDTocOp)
+LoadFromTocs.insert(Temp);
+} else {
+  // FIXME: analyze this scenario if there is one.
+  LoadFromTocs.clear();
+  break;
+}
+  }
+
+// Check the two Load@toc: one should be _$TLSML, and the other

amy-kwan wrote:

```suggestion
// Check the two Load@toc nodes: one should be _$TLSML, and the 
other
```

https://github.com/llvm/llvm-project/pull/66316
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[clang] [llvm] [PowerPC] Support local-dynamic TLS relocation on AIX (PR #66316)

2024-02-12 Thread Amy Kwan via cfe-commits



@@ -145,9 +164,94 @@ namespace {
   .addImm(0);
 
 if (IsAIX) {
-  // The variable offset and region handle are copied in r4 and r3. The
-  // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX.
-  if (!IsTLSTPRelMI) {
+  if (IsTLSLDAIXMI) {
+// The relative order between the LoadOffset@toc node (for the
+// variable offset), and the .__tls_get_mod node is being tuned
+// here. It is better to put the LoadOffset@toc node after the 
call,
+// since the LoadOffset@toc node can use clobbers r4/r5. Search for
+// the pattern of two Load@toc nodes (either for the variable 
offset
+// or for the module handle), and then move the LoadOffset@toc node
+// right before the node that uses the OutReg of the .__tls_get_mod
+// node.
+unsigned LDTocOp =
+Is64Bit ? (IsLargeModel ? PPC::LDtocL : PPC::LDtoc)
+: (IsLargeModel ? PPC::LWZtocL : PPC::LWZtoc);
+if (!RegInfo.use_empty(OutReg)) {
+  std::set Uses;
+  // Collect all instructions that use the OutReg.
+  for (MachineOperand &MO : RegInfo.use_operands(OutReg))
+Uses.insert(MO.getParent());
+  // Find the first user (e.g.: lwax/stfdx) of the OutReg within 
the
+  // current BB.
+  MachineBasicBlock::iterator UseIter = MBB.begin();
+  for (MachineBasicBlock::iterator IE = MBB.end(); UseIter != IE;
+   ++UseIter)
+if (Uses.count(&*UseIter))
+  break;
+
+  // Additional handling is required when UserIter (the first user
+  // of OutReg) is pointing to a valid node. Check the pattern and
+  // do the movement if the pattern matches.
+  if (UseIter != MBB.end()) {
+// Collect associated Load@toc nodes. Use hasOneDef() to guard
+// against unexpected scenarios.
+std::set LoadFromTocs;
+for (MachineOperand &MO : UseIter->operands())
+  if (MO.isReg() && MO.isUse()) {
+Register MOReg = MO.getReg();
+if (RegInfo.hasOneDef(MOReg)) {
+  MachineInstr *Temp =
+  RegInfo.getOneDef(MOReg)->getParent();
+  // For the current TLSLDAIX node, get the Load@toc node
+  // for the InReg. Otherwise, Temp probably pointed to the
+  // LoadOffset@toc node that we would like to move.
+  if (Temp == &MI && RegInfo.hasOneDef(InReg))
+Temp = RegInfo.getOneDef(InReg)->getParent();
+  if (Temp->getOpcode() == LDTocOp)
+LoadFromTocs.insert(Temp);
+} else {
+  // FIXME: analyze this scenario if there is one.
+  LoadFromTocs.clear();
+  break;
+}
+  }
+
+// Check the two Load@toc: one should be _$TLSML, and the other
+// will be moved before the node that uses the OutReg of the
+// .__tls_get_mod node.
+if (LoadFromTocs.size() == 2) {
+  MachineBasicBlock::iterator TLSMLIter = MBB.end();
+  MachineBasicBlock::iterator OffsetIter = MBB.end();
+  // Make sure the two LoadFromTocs are within current BB, and
+  // one of them from the "_$TLSML" pseudo symbol, while the
+  // other from the variable.
+  for (MachineBasicBlock::iterator I = MBB.begin(),
+   IE = MBB.end();
+   I != IE; ++I)
+if (LoadFromTocs.count(&*I)) {
+  MachineOperand MO = I->getOperand(1);
+  if (MO.isGlobal() && MO.getGlobal()->hasName() &&
+  MO.getGlobal()->getName() == "_$TLSML")
+TLSMLIter = I;
+  else
+OffsetIter = I;
+}
+  // If both two iterators are valid, we should have identified
+  // the scenario, and do the movement.

amy-kwan wrote:

```suggestion
  // Perform the movement when the desired scenario has been
  // identified, which should be when both of the iterators are 
valid.
```
This may sound a bit better.

https://github.com/llvm/llvm-project/pull/66316
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[clang] [clang][PowerPC] Add flag to enable compatibility with GNU for complex arguments (PR #77732)

2024-02-23 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan edited 
https://github.com/llvm/llvm-project/pull/77732
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[clang] [clang][PowerPC] Add flag to enable compatibility with GNU for complex arguments (PR #77732)

2024-02-23 Thread Amy Kwan via cfe-commits


https://github.com/amy-kwan commented:

I think the braces can also be omitted on the conditions within the `clang/*` 
files.

https://github.com/llvm/llvm-project/pull/77732
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[clang] [clang][PowerPC] Add flag to enable compatibility with GNU for complex arguments (PR #77732)

2024-02-23 Thread Amy Kwan via cfe-commits



@@ -337,12 +350,77 @@ CharUnits 
PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
   return CharUnits::fromQuantity(4);
 }
 
+ABIArgInfo PPC32_SVR4_ABIInfo::handleComplex(QualType Ty,
+ uint64_t &TypeSize) const {
+
+  assert(Ty->isAnyComplexType());

amy-kwan wrote:

It would also be good if the assert has a message.
Additionally, for people who do not do assert builds, since `Ty` is only used 
for the assert, they may get an unused variable warning.

https://github.com/llvm/llvm-project/pull/77732
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