[PATCH] D104931: [AArch64] Wire up ILP32 ABI support in Clang

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Amanieu added a comment.

Ping.


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[PATCH] D95745: Support unwinding from inline assembly

[Amanieu d'Antras via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8ec9fd483949: Support unwinding from inline assembly 
(authored by cynecx, committed by Amanieu).

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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/TargetInfo.cpp
  clang/lib/CodeGen/CGStmt.cpp
  clang/lib/Sema/SemaStmtAsm.cpp
  clang/test/CodeGenCXX/unwind-inline-asm.cpp
  llvm/bindings/go/llvm/ir.go
  llvm/include/llvm-c/Core.h
  llvm/include/llvm/Bitcode/LLVMBitCodes.h
  llvm/include/llvm/IR/InlineAsm.h
  llvm/lib/AsmParser/LLParser.cpp
  llvm/lib/Bitcode/Reader/BitcodeReader.cpp
  llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
  llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
  llvm/lib/IR/AsmWriter.cpp
  llvm/lib/IR/ConstantsContext.h
  llvm/lib/IR/Core.cpp
  llvm/lib/IR/InlineAsm.cpp
  llvm/lib/IR/Verifier.cpp
  llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
  llvm/lib/Transforms/Utils/InlineFunction.cpp
  llvm/lib/Transforms/Utils/ValueMapper.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-unwind-inline-asm.ll
  llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
  llvm/test/CodeGen/AArch64/GlobalISel/unwind-inline-asm.ll
  llvm/test/CodeGen/X86/no-seh-unwind-inline-asm-codegen.ll
  llvm/test/CodeGen/X86/no-unwind-inline-asm-codegen.ll
  llvm/test/CodeGen/X86/seh-unwind-inline-asm-codegen.ll
  llvm/test/CodeGen/X86/sjlj-unwind-inline-asm-codegen.ll
  llvm/test/CodeGen/X86/unwind-inline-asm-codegen.ll
  llvm/test/Transforms/Inline/no-unwind-inline-asm.ll
  llvm/test/Transforms/Inline/unwind-inline-asm.ll
  llvm/test/Transforms/InstCombine/no-unwind-inline-asm.ll
  llvm/test/Transforms/InstCombine/unwind-inline-asm.ll

Index: llvm/test/Transforms/InstCombine/unwind-inline-asm.ll
===
--- /dev/null
+++ llvm/test/Transforms/InstCombine/unwind-inline-asm.ll
@@ -0,0 +1,38 @@
+; RUN: opt < %s -O2 -S | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@.str.2 = private unnamed_addr constant [7 x i8] c"Boom!\0A\00", align 1
+
+define dso_local void @trap() {
+entry:
+  unreachable
+}
+
+define dso_local void @test() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+entry:
+; CHECK: define dso_local void @test()
+; CHECK-NEXT: entry:
+; CHECK-NEXT: invoke void asm sideeffect unwind
+
+  invoke void asm sideeffect unwind "call trap", "~{dirflag},~{fpsr},~{flags}"()
+  to label %invoke.cont unwind label %lpad
+
+invoke.cont:
+  ret void
+
+lpad:
+; CHECK: %0 = landingpad { i8*, i32 }
+; CHECK: resume { i8*, i32 } %0
+
+  %0 = landingpad { i8*, i32 }
+  cleanup
+  call void (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str.2, i64 0, i64 0))
+  resume { i8*, i32 } %0
+
+}
+
+declare dso_local i32 @__gxx_personality_v0(...)
+
+declare dso_local void @printf(i8*, ...)
Index: llvm/test/Transforms/InstCombine/no-unwind-inline-asm.ll
===
--- /dev/null
+++ llvm/test/Transforms/InstCombine/no-unwind-inline-asm.ll
@@ -0,0 +1,36 @@
+; RUN: opt < %s -O2 -S | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@.str.2 = private unnamed_addr constant [7 x i8] c"Boom!\0A\00", align 1
+
+define dso_local void @trap() {
+entry:
+  unreachable
+}
+
+define dso_local void @test() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+entry:
+; CHECK: define dso_local void @test()
+; CHECK-NEXT: entry:
+; CHECK-NEXT: tail call void asm sideeffect
+; CHECK-NEXT: ret void
+
+  invoke void asm sideeffect "call trap", "~{dirflag},~{fpsr},~{flags}"()
+  to label %invoke.cont unwind label %lpad
+
+invoke.cont:
+  ret void
+
+lpad:
+  %0 = landingpad { i8*, i32 }
+  cleanup
+  call void (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str.2, i64 0, i64 0))
+  resume { i8*, i32 } %0
+
+}
+
+declare dso_local i32 @__gxx_personality_v0(...)
+
+declare dso_local void @printf(i8*, ...)
Index: llvm/test/Transforms/Inline/unwind-inline-asm.ll
===
--- /dev/null
+++ llvm/test/Transforms/Inline/unwind-inline-asm.ll
@@ -0,0 +1,46 @@
+; RUN: opt < %s -inline -S | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@.str.2 = private unnamed_addr constant [7 x i8] c"Boom!\0A\00", align 1
+
+define dso_local

[PATCH] D104931: [AArch64] Wire up ILP32 ABI support in Clang

[Amanieu d'Antras via Phabricator via cfe-commits]

Amanieu created this revision.
Amanieu added reviewers: t.p.northover, aemerson, kristof.beyls.
Herald added a subscriber: danielkiss.
Amanieu requested review of this revision.
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This is a follow-up to D94143  which added the 
necessary support in LLVM.

ILP32 mode is enabled by specifying an ILP32 target (aarch64[_be]-*-gnu_ilp32) 
with -target.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D104931

Files:
  clang/lib/Basic/Targets/AArch64.cpp


Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -43,7 +43,8 @@
 AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
  const TargetOptions &Opts)
 : TargetInfo(Triple), ABI("aapcs") {
-  if (getTriple().isOSOpenBSD()) {
+  if (getTriple().isOSOpenBSD() ||
+  getTriple().getEnvironment() == llvm::Triple::GNUILP32) {
 Int64Type = SignedLongLong;
 IntMaxType = SignedLongLong;
   } else {
@@ -58,7 +59,8 @@
   HasLegalHalfType = true;
   HasFloat16 = true;
 
-  if (Triple.isArch64Bit())
+  if (Triple.isArch64Bit() &&
+  getTriple().getEnvironment() != llvm::Triple::GNUILP32)
 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
   else
 LongWidth = LongAlign = PointerWidth = PointerAlign = 32;
@@ -213,10 +215,15 @@
 Builder.defineMacro("__ELF__");
 
   // Target properties.
-  if (!getTriple().isOSWindows() && getTriple().isArch64Bit()) {
+  if (!getTriple().isOSWindows() && getTriple().isArch64Bit() &&
+  getTriple().getEnvironment() != llvm::Triple::GNUILP32) {
 Builder.defineMacro("_LP64");
 Builder.defineMacro("__LP64__");
   }
+  if (getTriple().getEnvironment() == llvm::Triple::GNUILP32) {
+Builder.defineMacro("_ILP32");
+Builder.defineMacro("__ILP32__");
+  }
 
   std::string CodeModel = getTargetOpts().CodeModel;
   if (CodeModel == "default")
@@ -780,8 +787,13 @@
   resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128", "_");
 else
   resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128", "_");
-  } else
-resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
+  } else {
+if (getTriple().getEnvironment() == llvm::Triple::GNUILP32)
+  resetDataLayout(
+  "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
+else
+  resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
+  }
 }
 
 void AArch64leTargetInfo::getTargetDefines(const LangOptions &Opts,
@@ -804,7 +816,11 @@
 
 void AArch64beTargetInfo::setDataLayout() {
   assert(!getTriple().isOSBinFormatMachO());
-  resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
+  if (getTriple().getEnvironment() == llvm::Triple::GNUILP32)
+resetDataLayout(
+"E-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
+  else
+resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
 }
 
 WindowsARM64TargetInfo::WindowsARM64TargetInfo(const llvm::Triple &Triple,


Index: clang/lib/Basic/Targets/AArch64.cpp
===
--- clang/lib/Basic/Targets/AArch64.cpp
+++ clang/lib/Basic/Targets/AArch64.cpp
@@ -43,7 +43,8 @@
 AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple,
  const TargetOptions &Opts)
 : TargetInfo(Triple), ABI("aapcs") {
-  if (getTriple().isOSOpenBSD()) {
+  if (getTriple().isOSOpenBSD() ||
+  getTriple().getEnvironment() == llvm::Triple::GNUILP32) {
 Int64Type = SignedLongLong;
 IntMaxType = SignedLongLong;
   } else {
@@ -58,7 +59,8 @@
   HasLegalHalfType = true;
   HasFloat16 = true;
 
-  if (Triple.isArch64Bit())
+  if (Triple.isArch64Bit() &&
+  getTriple().getEnvironment() != llvm::Triple::GNUILP32)
 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
   else
 LongWidth = LongAlign = PointerWidth = PointerAlign = 32;
@@ -213,10 +215,15 @@
 Builder.defineMacro("__ELF__");
 
   // Target properties.
-  if (!getTriple().isOSWindows() && getTriple().isArch64Bit()) {
+  if (!getTriple().isOSWindows() && getTriple().isArch64Bit() &&
+  getTriple().getEnvironment() != llvm::Triple::GNUILP32) {
 Builder.defineMacro("_LP64");
 Builder.defineMacro("__LP64__");
   }
+  if (getTriple().getEnvironment() == llvm::Triple::GNUILP32) {
+Builder.defineMacro("_ILP32");
+Builder.defineMacro("__ILP32__");
+  }
 
   std::string CodeModel = getTargetOpts().CodeModel;
   if (CodeModel == "default")
@@ -780,8 +787,13 @@
   resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128", "_");
 else
   resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128", "_");
-  } else
-resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
+  } else {
+

[PATCH] D134717: [Clang][AArch64] Fix va_arg with -mgeneral-regs-only

[Amanieu d'Antras via Phabricator via cfe-commits]

Amanieu created this revision.
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With -mgeneral-regs-only, all arguments are passed in GPRs, so we should use 
__gr_top/__gr_offs in va_list even for floating-point types.


Repository:
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https://reviews.llvm.org/D134717

Files:
  clang/lib/CodeGen/TargetInfo.cpp


Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -5988,7 +5988,8 @@
 BaseTy = ArrTy->getElementType();
 NumRegs = ArrTy->getNumElements();
   }
-  bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
+  bool IsFPR = CGF.getTarget().hasFeature("fp-armv8") &&
+  (BaseTy->isFloatingPointTy() || BaseTy->isVectorTy());
 
   // The AArch64 va_list type and handling is specified in the Procedure Call
   // Standard, section B.4:


Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -5988,7 +5988,8 @@
 BaseTy = ArrTy->getElementType();
 NumRegs = ArrTy->getNumElements();
   }
-  bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
+  bool IsFPR = CGF.getTarget().hasFeature("fp-armv8") &&
+  (BaseTy->isFloatingPointTy() || BaseTy->isVectorTy());
 
   // The AArch64 va_list type and handling is specified in the Procedure Call
   // Standard, section B.4:
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[PATCH] D134717: [Clang][AArch64] Fix va_arg with -mgeneral-regs-only

[Amanieu d'Antras via Phabricator via cfe-commits]

Amanieu added a comment.

Currently using Clang with -mgeneral-regs-only generates perfectly fine 
soft-float AArch64, with the except of the va_arg() implementation which is 
fixed here. In fact Rust even has a aarch64-unknown-none-softfloat which relies 
on this behavior in LLVM. I believe this behavior is *more* useful than GCC's 
which simply rejects float/double types, and it makes sense to keep it and fix 
it.


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[PATCH] D134717: [Clang][AArch64] Fix va_arg with -mgeneral-regs-only

[Amanieu d'Antras via Phabricator via cfe-commits]

Amanieu added a comment.

I fully agree that this likely wasn't intentional, but this is still very 
useful for code that can't use FP registers for whatever reason (e.g. kernels). 
Regarding the ABI, it doesn't need to be officially defined: it just needs to 
be compatible with other code compiled with -mgeneral-regs-only.


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[PATCH] D104931: [AArch64] Wire up ILP32 ABI support in Clang

[Amanieu d'Antras via Phabricator via cfe-commits]

Amanieu added a comment.

The situation around -mabi for AArch64 is a bit awkward: Clang uses it to 
select the ARM64 calling convention (`-mabi=aapcs` vs `-mabi=darwinpcs`) while 
GCC uses it to select between LP64 and ILP32. I'm not sure how we should be 
handling this.


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[PATCH] D127460: Rename GCCBuiltin into ClangBuiltin

[Amanieu d'Antras via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd0a4450ecdaf: Rename GCCBuiltin into ClangBuiltin (authored 
by GuillaumeGomez, committed by Amanieu).

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Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/IR/Intrinsics.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/include/llvm/IR/IntrinsicsAMDGPU.td
  llvm/include/llvm/IR/IntrinsicsARM.td
  llvm/include/llvm/IR/IntrinsicsBPF.td
  llvm/include/llvm/IR/IntrinsicsHexagon.td
  llvm/include/llvm/IR/IntrinsicsMips.td
  llvm/include/llvm/IR/IntrinsicsNVVM.td
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/include/llvm/IR/IntrinsicsSystemZ.td
  llvm/include/llvm/IR/IntrinsicsVE.td
  llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/IR/IntrinsicsXCore.td
  llvm/lib/IR/Function.cpp
  llvm/utils/TableGen/CodeGenIntrinsics.h
  llvm/utils/TableGen/CodeGenTarget.cpp
  llvm/utils/TableGen/IntrinsicEmitter.cpp

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[PATCH] D104931: [AArch64] Wire up ILP32 ABI support in Clang

[Amanieu d'Antras via Phabricator via cfe-commits]

Amanieu added a comment.

Ping.


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[PATCH] D95745: Support unwinding from inline assembly

[Amanieu d'Antras via Phabricator via cfe-commits]

Amanieu accepted this revision.
Amanieu added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D95745: Support unwinding from inline assembly

[Amanieu d'Antras via Phabricator via cfe-commits]

Amanieu added a comment.

The new operand to InlineAsm needs to be handled in 
llvm/lib/Transforms/Utils/ValueMapper.cpp otherwise you will end up with a bug 
similar to https://bugs.llvm.org/show_bug.cgi?id=45291.

Some tests with other unwinding models such as SJLJ and SEH would be nice.




Comment at: clang/lib/CodeGen/CGStmt.cpp:2522
+  assert(!(HasUnwindClobber && IsGCCAsmGoto) &&
+ "unwind clobber can't be used with asm goto");
+

This should be a compiler error diagnostic in SemaAsmStmt.cpp rather than an 
assert.



Comment at: llvm/lib/AsmParser/LLParser.cpp:5471
(ID.UIntVal >> 1) & 1,
-   (InlineAsm::AsmDialect(ID.UIntVal >> 2)));
+   (InlineAsm::AsmDialect(ID.UIntVal >> 2)),
+   (ID.UIntVal >> 3) & 1);





Comment at: llvm/lib/Bitcode/Reader/BitcodeReader.cpp:2857
+  bool IsAlignStack = (Record[0] >> 1) & 1;
+  unsigned AsmDialect = Record[0] >> 2;
+  bool CanThrow = (Record[0] >> 3) & 1;





Comment at: llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp:2446
+if (!IA->canThrow()) {
+  // Fast path without emitting EH_LABELs.
+

Is this fast path actually useful? The frontend will almost never emit an 
invoke instruction for inline asm that can't unwind.



Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:8347
+Chain = DAG.getEHLabel(getCurSDLoc(), Chain, BeginLabel);
+  }
+

This code is likely to get out of sync with the one in visitInvokable. It would 
be nice to share the code in a single place, but if that is not practical then 
at least add a comment in visitInvokable to remind anyone modifying that code 
to apply the same changes here as well.


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