[clang] [llvm] Add f8E4M3 IEEE 754 type to llvm (PR #97179)
https://github.com/apivovarov created
https://github.com/llvm/llvm-project/pull/97179
This PR adds `f8E4M3` type to llvm.
`f8E4M3` type follows IEEE 754 convention
```c
f8E4M3 (IEEE 754)
- Exponent: 4
- Mantissa: 3
- Exponent bias: 7
- Follows IEEE 754 conventions for representation of special values
- Has Positive and Negative zero
- Has Positive and Negative infinity
- Has NaNs
Additional details:
- Max exp (unbiased): 7
- Min exp (unbiased): -6
- Infinities (+/-): S..000
- Zeros (+/-): S..000
- NaNs: S..{001, 010, 011, 100, 101, 110, 111}
- Max normal number: S.1110.111 = +/-240
- Min normal number: S.0001.000 = +/-2^(-6)
- Max subnormal number: S..111 = +/-2^(-6) x 0.875 = +/-2^(-9) x 7
- Min subnormal number: S..001 = +/-2^(-6) x 0.125 = +/-2^(-9)
```
Related PRs:
- [PR-97118](https://github.com/llvm/llvm-project/pull/97118) Add f8E4M3 IEEE
754 type to mlir
>From 38a885014046f5e696a98361586919d14362dbed Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH] Add f8E4M3 IEEE 754 type to llvm
---
clang/include/clang/AST/Stmt.h | 6 ++---
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h| 6 +
llvm/lib/Support/APFloat.cpp | 20
llvm/unittests/ADT/APFloatTest.cpp | 38 ++
5 files changed, 68 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/AST/Stmt.h b/clang/include/clang/AST/Stmt.h
index 9cd7a364cd3f1..4edb04502f83e 100644
--- a/clang/include/clang/AST/Stmt.h
+++ b/clang/include/clang/AST/Stmt.h
@@ -460,10 +460,10 @@ class alignas(void *) Stmt {
unsigned : NumExprBits;
static_assert(
-llvm::APFloat::S_MaxSemantics < 16,
-"Too many Semantics enum values to fit in bitfield of size 4");
+llvm::APFloat::S_MaxSemantics < 32,
+"Too many Semantics enum values to fit in bitfield of size 5");
LLVM_PREFERRED_TYPE(llvm::APFloat::Semantics)
-unsigned Semantics : 4; // Provides semantics for APFloat construction
+unsigned Semantics : 5; // Provides semantics for APFloat construction
LLVM_PREFERRED_TYPE(bool)
unsigned IsExact : 1;
};
diff --git a/clang/lib/AST/MicrosoftMangle.cpp
b/clang/lib/AST/MicrosoftMangle.cpp
index 7f1e9ab02ec26..a2e270df276cb 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -946,6 +946,7 @@ void MicrosoftCXXNameMangler::mangleFloat(llvm::APFloat
Number) {
case APFloat::S_IEEEquad: Out << 'Y'; break;
case APFloat::S_PPCDoubleDouble: Out << 'Z'; break;
case APFloat::S_Float8E5M2:
+ case APFloat::S_Float8E4M3:
case APFloat::S_Float8E4M3FN:
case APFloat::S_Float8E5M2FNUZ:
case APFloat::S_Float8E4M3FNUZ:
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index db2fa480655c6..bff8e6490d1de 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -166,6 +166,9 @@ struct APFloatBase {
// This format's exponent bias is 16, instead of the 15 (2 ** (5 - 1) - 1)
// that IEEE precedent would imply.
S_Float8E5M2FNUZ,
+// 8-bit floating point number following IEEE-754 conventions with bit
+// layout S1E4M3.
+S_Float8E4M3,
// 8-bit floating point number mostly following IEEE-754 conventions with
// bit layout S1E4M3 as described in https://arxiv.org/abs/2209.05433.
// Unlike IEEE-754 types, there are no infinity values, and NaN is
@@ -217,6 +220,7 @@ struct APFloatBase {
static const fltSemantics &PPCDoubleDouble() LLVM_READNONE;
static const fltSemantics &Float8E5M2() LLVM_READNONE;
static const fltSemantics &Float8E5M2FNUZ() LLVM_READNONE;
+ static const fltSemantics &Float8E4M3() LLVM_READNONE;
static const fltSemantics &Float8E4M3FN() LLVM_READNONE;
static const fltSemantics &Float8E4M3FNUZ() LLVM_READNONE;
static const fltSemantics &Float8E4M3B11FNUZ() LLVM_READNONE;
@@ -638,6 +642,7 @@ class IEEEFloat final : public APFloatBase {
APInt convertPPCDoubleDoubleAPFloatToAPInt() const;
APInt convertFloat8E5M2APFloatToAPInt() const;
APInt convertFloat8E5M2FNUZAPFloatToAPInt() const;
+ APInt convertFloat8E4M3APFloatToAPInt() const;
APInt convertFloat8E4M3FNAPFloatToAPInt() const;
APInt convertFloat8E4M3FNUZAPFloatToAPInt() const;
APInt convertFloat8E4M3B11FNUZAPFloatToAPInt() const;
@@ -656,6 +661,7 @@ class IEEEFloat final : public APFloatBase {
void initFromPPCDoubleDoubleAPInt(const APInt &api);
void initFromFloat8E5M2APInt(const APInt &api);
void initFromFloat8E5M2FNUZAPInt(const APInt &api);
+ void initFromFloat8E4M3APInt(const APInt &api);
void initFromFloat8E4M3FNAPInt(const APInt &api);
void initFromFloat8E4M3FNUZAPInt(const APInt &api);
void initFromFloat8E4M3B11FNUZAPInt(const APInt &api);
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 3017a9b976658..79e0094b243b2 100644
--- a/llvm/lib/Support/APFloat.
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/97118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type to mlir (PR #97118)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/97118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type to mlir (PR #97118)
apivovarov wrote: > If this is a new float type, could you please split out the apfloat changes > in separate PR. Sure - [PR-97179](https://github.com/llvm/llvm-project/pull/97179) Add f8E4M3 IEEE 754 type to llvm https://github.com/llvm/llvm-project/pull/97118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type to mlir (PR #97118)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/97118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type to mlir (PR #97118)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/97118
>From 38a885014046f5e696a98361586919d14362dbed Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH 1/2] Add f8E4M3 IEEE 754 type to llvm
---
clang/include/clang/AST/Stmt.h | 6 ++---
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h| 6 +
llvm/lib/Support/APFloat.cpp | 20
llvm/unittests/ADT/APFloatTest.cpp | 38 ++
5 files changed, 68 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/AST/Stmt.h b/clang/include/clang/AST/Stmt.h
index 9cd7a364cd3f1..4edb04502f83e 100644
--- a/clang/include/clang/AST/Stmt.h
+++ b/clang/include/clang/AST/Stmt.h
@@ -460,10 +460,10 @@ class alignas(void *) Stmt {
unsigned : NumExprBits;
static_assert(
-llvm::APFloat::S_MaxSemantics < 16,
-"Too many Semantics enum values to fit in bitfield of size 4");
+llvm::APFloat::S_MaxSemantics < 32,
+"Too many Semantics enum values to fit in bitfield of size 5");
LLVM_PREFERRED_TYPE(llvm::APFloat::Semantics)
-unsigned Semantics : 4; // Provides semantics for APFloat construction
+unsigned Semantics : 5; // Provides semantics for APFloat construction
LLVM_PREFERRED_TYPE(bool)
unsigned IsExact : 1;
};
diff --git a/clang/lib/AST/MicrosoftMangle.cpp
b/clang/lib/AST/MicrosoftMangle.cpp
index 7f1e9ab02ec26..a2e270df276cb 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -946,6 +946,7 @@ void MicrosoftCXXNameMangler::mangleFloat(llvm::APFloat
Number) {
case APFloat::S_IEEEquad: Out << 'Y'; break;
case APFloat::S_PPCDoubleDouble: Out << 'Z'; break;
case APFloat::S_Float8E5M2:
+ case APFloat::S_Float8E4M3:
case APFloat::S_Float8E4M3FN:
case APFloat::S_Float8E5M2FNUZ:
case APFloat::S_Float8E4M3FNUZ:
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index db2fa480655c6..bff8e6490d1de 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -166,6 +166,9 @@ struct APFloatBase {
// This format's exponent bias is 16, instead of the 15 (2 ** (5 - 1) - 1)
// that IEEE precedent would imply.
S_Float8E5M2FNUZ,
+// 8-bit floating point number following IEEE-754 conventions with bit
+// layout S1E4M3.
+S_Float8E4M3,
// 8-bit floating point number mostly following IEEE-754 conventions with
// bit layout S1E4M3 as described in https://arxiv.org/abs/2209.05433.
// Unlike IEEE-754 types, there are no infinity values, and NaN is
@@ -217,6 +220,7 @@ struct APFloatBase {
static const fltSemantics &PPCDoubleDouble() LLVM_READNONE;
static const fltSemantics &Float8E5M2() LLVM_READNONE;
static const fltSemantics &Float8E5M2FNUZ() LLVM_READNONE;
+ static const fltSemantics &Float8E4M3() LLVM_READNONE;
static const fltSemantics &Float8E4M3FN() LLVM_READNONE;
static const fltSemantics &Float8E4M3FNUZ() LLVM_READNONE;
static const fltSemantics &Float8E4M3B11FNUZ() LLVM_READNONE;
@@ -638,6 +642,7 @@ class IEEEFloat final : public APFloatBase {
APInt convertPPCDoubleDoubleAPFloatToAPInt() const;
APInt convertFloat8E5M2APFloatToAPInt() const;
APInt convertFloat8E5M2FNUZAPFloatToAPInt() const;
+ APInt convertFloat8E4M3APFloatToAPInt() const;
APInt convertFloat8E4M3FNAPFloatToAPInt() const;
APInt convertFloat8E4M3FNUZAPFloatToAPInt() const;
APInt convertFloat8E4M3B11FNUZAPFloatToAPInt() const;
@@ -656,6 +661,7 @@ class IEEEFloat final : public APFloatBase {
void initFromPPCDoubleDoubleAPInt(const APInt &api);
void initFromFloat8E5M2APInt(const APInt &api);
void initFromFloat8E5M2FNUZAPInt(const APInt &api);
+ void initFromFloat8E4M3APInt(const APInt &api);
void initFromFloat8E4M3FNAPInt(const APInt &api);
void initFromFloat8E4M3FNUZAPInt(const APInt &api);
void initFromFloat8E4M3B11FNUZAPInt(const APInt &api);
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 3017a9b976658..79e0094b243b2 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -136,6 +136,7 @@ static constexpr fltSemantics semIEEEquad = {16383, -16382,
113, 128};
static constexpr fltSemantics semFloat8E5M2 = {15, -14, 3, 8};
static constexpr fltSemantics semFloat8E5M2FNUZ = {
15, -15, 3, 8, fltNonfiniteBehavior::NanOnly,
fltNanEncoding::NegativeZero};
+static constexpr fltSemantics semFloat8E4M3 = {7, -6, 4, 8};
static constexpr fltSemantics semFloat8E4M3FN = {
8, -6, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::AllOnes};
static constexpr fltSemantics semFloat8E4M3FNUZ = {
@@ -208,6 +209,8 @@ const llvm::fltSemantics
&APFloatBase::EnumToSemantics(Semantics S) {
return Float8E5M2();
case S_Float8E5M2FNUZ:
return Float8E5M2FNUZ();
+ case S_Float8E4M3:
+return Float8E4M3();
case S_Float8E4M3
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type to mlir (PR #97118)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/97118
>From 38a885014046f5e696a98361586919d14362dbed Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH 1/2] Add f8E4M3 IEEE 754 type to llvm
---
clang/include/clang/AST/Stmt.h | 6 ++---
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h| 6 +
llvm/lib/Support/APFloat.cpp | 20
llvm/unittests/ADT/APFloatTest.cpp | 38 ++
5 files changed, 68 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/AST/Stmt.h b/clang/include/clang/AST/Stmt.h
index 9cd7a364cd3f1..4edb04502f83e 100644
--- a/clang/include/clang/AST/Stmt.h
+++ b/clang/include/clang/AST/Stmt.h
@@ -460,10 +460,10 @@ class alignas(void *) Stmt {
unsigned : NumExprBits;
static_assert(
-llvm::APFloat::S_MaxSemantics < 16,
-"Too many Semantics enum values to fit in bitfield of size 4");
+llvm::APFloat::S_MaxSemantics < 32,
+"Too many Semantics enum values to fit in bitfield of size 5");
LLVM_PREFERRED_TYPE(llvm::APFloat::Semantics)
-unsigned Semantics : 4; // Provides semantics for APFloat construction
+unsigned Semantics : 5; // Provides semantics for APFloat construction
LLVM_PREFERRED_TYPE(bool)
unsigned IsExact : 1;
};
diff --git a/clang/lib/AST/MicrosoftMangle.cpp
b/clang/lib/AST/MicrosoftMangle.cpp
index 7f1e9ab02ec26..a2e270df276cb 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -946,6 +946,7 @@ void MicrosoftCXXNameMangler::mangleFloat(llvm::APFloat
Number) {
case APFloat::S_IEEEquad: Out << 'Y'; break;
case APFloat::S_PPCDoubleDouble: Out << 'Z'; break;
case APFloat::S_Float8E5M2:
+ case APFloat::S_Float8E4M3:
case APFloat::S_Float8E4M3FN:
case APFloat::S_Float8E5M2FNUZ:
case APFloat::S_Float8E4M3FNUZ:
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index db2fa480655c6..bff8e6490d1de 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -166,6 +166,9 @@ struct APFloatBase {
// This format's exponent bias is 16, instead of the 15 (2 ** (5 - 1) - 1)
// that IEEE precedent would imply.
S_Float8E5M2FNUZ,
+// 8-bit floating point number following IEEE-754 conventions with bit
+// layout S1E4M3.
+S_Float8E4M3,
// 8-bit floating point number mostly following IEEE-754 conventions with
// bit layout S1E4M3 as described in https://arxiv.org/abs/2209.05433.
// Unlike IEEE-754 types, there are no infinity values, and NaN is
@@ -217,6 +220,7 @@ struct APFloatBase {
static const fltSemantics &PPCDoubleDouble() LLVM_READNONE;
static const fltSemantics &Float8E5M2() LLVM_READNONE;
static const fltSemantics &Float8E5M2FNUZ() LLVM_READNONE;
+ static const fltSemantics &Float8E4M3() LLVM_READNONE;
static const fltSemantics &Float8E4M3FN() LLVM_READNONE;
static const fltSemantics &Float8E4M3FNUZ() LLVM_READNONE;
static const fltSemantics &Float8E4M3B11FNUZ() LLVM_READNONE;
@@ -638,6 +642,7 @@ class IEEEFloat final : public APFloatBase {
APInt convertPPCDoubleDoubleAPFloatToAPInt() const;
APInt convertFloat8E5M2APFloatToAPInt() const;
APInt convertFloat8E5M2FNUZAPFloatToAPInt() const;
+ APInt convertFloat8E4M3APFloatToAPInt() const;
APInt convertFloat8E4M3FNAPFloatToAPInt() const;
APInt convertFloat8E4M3FNUZAPFloatToAPInt() const;
APInt convertFloat8E4M3B11FNUZAPFloatToAPInt() const;
@@ -656,6 +661,7 @@ class IEEEFloat final : public APFloatBase {
void initFromPPCDoubleDoubleAPInt(const APInt &api);
void initFromFloat8E5M2APInt(const APInt &api);
void initFromFloat8E5M2FNUZAPInt(const APInt &api);
+ void initFromFloat8E4M3APInt(const APInt &api);
void initFromFloat8E4M3FNAPInt(const APInt &api);
void initFromFloat8E4M3FNUZAPInt(const APInt &api);
void initFromFloat8E4M3B11FNUZAPInt(const APInt &api);
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 3017a9b976658..79e0094b243b2 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -136,6 +136,7 @@ static constexpr fltSemantics semIEEEquad = {16383, -16382,
113, 128};
static constexpr fltSemantics semFloat8E5M2 = {15, -14, 3, 8};
static constexpr fltSemantics semFloat8E5M2FNUZ = {
15, -15, 3, 8, fltNonfiniteBehavior::NanOnly,
fltNanEncoding::NegativeZero};
+static constexpr fltSemantics semFloat8E4M3 = {7, -6, 4, 8};
static constexpr fltSemantics semFloat8E4M3FN = {
8, -6, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::AllOnes};
static constexpr fltSemantics semFloat8E4M3FNUZ = {
@@ -208,6 +209,8 @@ const llvm::fltSemantics
&APFloatBase::EnumToSemantics(Semantics S) {
return Float8E5M2();
case S_Float8E5M2FNUZ:
return Float8E5M2FNUZ();
+ case S_Float8E4M3:
+return Float8E4M3();
case S_Float8E4M3
[clang] [llvm] Add f8E4M3 IEEE 754 type to llvm (PR #97179)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/97179
>From 639ca43f1c57657ecaeb43a097664bae008093fd Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH] Add f8E4M3 IEEE 754 type to llvm
---
clang/include/clang/AST/Stmt.h | 6 +--
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h| 6 +++
llvm/lib/Support/APFloat.cpp | 20 +
llvm/unittests/ADT/APFloatTest.cpp | 66 ++
5 files changed, 96 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/AST/Stmt.h b/clang/include/clang/AST/Stmt.h
index 9cd7a364cd3f1..4edb04502f83e 100644
--- a/clang/include/clang/AST/Stmt.h
+++ b/clang/include/clang/AST/Stmt.h
@@ -460,10 +460,10 @@ class alignas(void *) Stmt {
unsigned : NumExprBits;
static_assert(
-llvm::APFloat::S_MaxSemantics < 16,
-"Too many Semantics enum values to fit in bitfield of size 4");
+llvm::APFloat::S_MaxSemantics < 32,
+"Too many Semantics enum values to fit in bitfield of size 5");
LLVM_PREFERRED_TYPE(llvm::APFloat::Semantics)
-unsigned Semantics : 4; // Provides semantics for APFloat construction
+unsigned Semantics : 5; // Provides semantics for APFloat construction
LLVM_PREFERRED_TYPE(bool)
unsigned IsExact : 1;
};
diff --git a/clang/lib/AST/MicrosoftMangle.cpp
b/clang/lib/AST/MicrosoftMangle.cpp
index 7f1e9ab02ec26..a2e270df276cb 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -946,6 +946,7 @@ void MicrosoftCXXNameMangler::mangleFloat(llvm::APFloat
Number) {
case APFloat::S_IEEEquad: Out << 'Y'; break;
case APFloat::S_PPCDoubleDouble: Out << 'Z'; break;
case APFloat::S_Float8E5M2:
+ case APFloat::S_Float8E4M3:
case APFloat::S_Float8E4M3FN:
case APFloat::S_Float8E5M2FNUZ:
case APFloat::S_Float8E4M3FNUZ:
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index db2fa480655c6..bff8e6490d1de 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -166,6 +166,9 @@ struct APFloatBase {
// This format's exponent bias is 16, instead of the 15 (2 ** (5 - 1) - 1)
// that IEEE precedent would imply.
S_Float8E5M2FNUZ,
+// 8-bit floating point number following IEEE-754 conventions with bit
+// layout S1E4M3.
+S_Float8E4M3,
// 8-bit floating point number mostly following IEEE-754 conventions with
// bit layout S1E4M3 as described in https://arxiv.org/abs/2209.05433.
// Unlike IEEE-754 types, there are no infinity values, and NaN is
@@ -217,6 +220,7 @@ struct APFloatBase {
static const fltSemantics &PPCDoubleDouble() LLVM_READNONE;
static const fltSemantics &Float8E5M2() LLVM_READNONE;
static const fltSemantics &Float8E5M2FNUZ() LLVM_READNONE;
+ static const fltSemantics &Float8E4M3() LLVM_READNONE;
static const fltSemantics &Float8E4M3FN() LLVM_READNONE;
static const fltSemantics &Float8E4M3FNUZ() LLVM_READNONE;
static const fltSemantics &Float8E4M3B11FNUZ() LLVM_READNONE;
@@ -638,6 +642,7 @@ class IEEEFloat final : public APFloatBase {
APInt convertPPCDoubleDoubleAPFloatToAPInt() const;
APInt convertFloat8E5M2APFloatToAPInt() const;
APInt convertFloat8E5M2FNUZAPFloatToAPInt() const;
+ APInt convertFloat8E4M3APFloatToAPInt() const;
APInt convertFloat8E4M3FNAPFloatToAPInt() const;
APInt convertFloat8E4M3FNUZAPFloatToAPInt() const;
APInt convertFloat8E4M3B11FNUZAPFloatToAPInt() const;
@@ -656,6 +661,7 @@ class IEEEFloat final : public APFloatBase {
void initFromPPCDoubleDoubleAPInt(const APInt &api);
void initFromFloat8E5M2APInt(const APInt &api);
void initFromFloat8E5M2FNUZAPInt(const APInt &api);
+ void initFromFloat8E4M3APInt(const APInt &api);
void initFromFloat8E4M3FNAPInt(const APInt &api);
void initFromFloat8E4M3FNUZAPInt(const APInt &api);
void initFromFloat8E4M3B11FNUZAPInt(const APInt &api);
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 3017a9b976658..79e0094b243b2 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -136,6 +136,7 @@ static constexpr fltSemantics semIEEEquad = {16383, -16382,
113, 128};
static constexpr fltSemantics semFloat8E5M2 = {15, -14, 3, 8};
static constexpr fltSemantics semFloat8E5M2FNUZ = {
15, -15, 3, 8, fltNonfiniteBehavior::NanOnly,
fltNanEncoding::NegativeZero};
+static constexpr fltSemantics semFloat8E4M3 = {7, -6, 4, 8};
static constexpr fltSemantics semFloat8E4M3FN = {
8, -6, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::AllOnes};
static constexpr fltSemantics semFloat8E4M3FNUZ = {
@@ -208,6 +209,8 @@ const llvm::fltSemantics
&APFloatBase::EnumToSemantics(Semantics S) {
return Float8E5M2();
case S_Float8E5M2FNUZ:
return Float8E5M2FNUZ();
+ case S_Float8E4M3:
+return Float8E4M3();
case S_Float8E4M3FN:
return
[clang] [llvm] Add f8E4M3 IEEE 754 type to llvm (PR #97179)
apivovarov wrote: Thorsten, Matt, What you think about adding the following tests? ```c // E4M3 <-> E5M2 ConvertE4M3ToE5M2 ConvertE5M2ToE4M3 // E4M3 <-> E4M3FN ConvertE4M3ToE4M3FN ConvertE4M3FNToE4M3 ``` @tschuett @arsenm https://github.com/llvm/llvm-project/pull/97179 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E4M3 IEEE 754 type (PR #97179)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/97179
>From 2c5a29ebe92a8352c31e34a36ff73959ce04a557 Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH] [APFloat] Add support for f8E4M3 IEEE 754 type
---
clang/include/clang/AST/Stmt.h | 6 +--
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h| 6 +++
llvm/lib/Support/APFloat.cpp | 20 +
llvm/unittests/ADT/APFloatTest.cpp | 66 ++
5 files changed, 96 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/AST/Stmt.h b/clang/include/clang/AST/Stmt.h
index 9cd7a364cd3f1..4edb04502f83e 100644
--- a/clang/include/clang/AST/Stmt.h
+++ b/clang/include/clang/AST/Stmt.h
@@ -460,10 +460,10 @@ class alignas(void *) Stmt {
unsigned : NumExprBits;
static_assert(
-llvm::APFloat::S_MaxSemantics < 16,
-"Too many Semantics enum values to fit in bitfield of size 4");
+llvm::APFloat::S_MaxSemantics < 32,
+"Too many Semantics enum values to fit in bitfield of size 5");
LLVM_PREFERRED_TYPE(llvm::APFloat::Semantics)
-unsigned Semantics : 4; // Provides semantics for APFloat construction
+unsigned Semantics : 5; // Provides semantics for APFloat construction
LLVM_PREFERRED_TYPE(bool)
unsigned IsExact : 1;
};
diff --git a/clang/lib/AST/MicrosoftMangle.cpp
b/clang/lib/AST/MicrosoftMangle.cpp
index 7f1e9ab02ec26..a2e270df276cb 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -946,6 +946,7 @@ void MicrosoftCXXNameMangler::mangleFloat(llvm::APFloat
Number) {
case APFloat::S_IEEEquad: Out << 'Y'; break;
case APFloat::S_PPCDoubleDouble: Out << 'Z'; break;
case APFloat::S_Float8E5M2:
+ case APFloat::S_Float8E4M3:
case APFloat::S_Float8E4M3FN:
case APFloat::S_Float8E5M2FNUZ:
case APFloat::S_Float8E4M3FNUZ:
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index db2fa480655c6..bff8e6490d1de 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -166,6 +166,9 @@ struct APFloatBase {
// This format's exponent bias is 16, instead of the 15 (2 ** (5 - 1) - 1)
// that IEEE precedent would imply.
S_Float8E5M2FNUZ,
+// 8-bit floating point number following IEEE-754 conventions with bit
+// layout S1E4M3.
+S_Float8E4M3,
// 8-bit floating point number mostly following IEEE-754 conventions with
// bit layout S1E4M3 as described in https://arxiv.org/abs/2209.05433.
// Unlike IEEE-754 types, there are no infinity values, and NaN is
@@ -217,6 +220,7 @@ struct APFloatBase {
static const fltSemantics &PPCDoubleDouble() LLVM_READNONE;
static const fltSemantics &Float8E5M2() LLVM_READNONE;
static const fltSemantics &Float8E5M2FNUZ() LLVM_READNONE;
+ static const fltSemantics &Float8E4M3() LLVM_READNONE;
static const fltSemantics &Float8E4M3FN() LLVM_READNONE;
static const fltSemantics &Float8E4M3FNUZ() LLVM_READNONE;
static const fltSemantics &Float8E4M3B11FNUZ() LLVM_READNONE;
@@ -638,6 +642,7 @@ class IEEEFloat final : public APFloatBase {
APInt convertPPCDoubleDoubleAPFloatToAPInt() const;
APInt convertFloat8E5M2APFloatToAPInt() const;
APInt convertFloat8E5M2FNUZAPFloatToAPInt() const;
+ APInt convertFloat8E4M3APFloatToAPInt() const;
APInt convertFloat8E4M3FNAPFloatToAPInt() const;
APInt convertFloat8E4M3FNUZAPFloatToAPInt() const;
APInt convertFloat8E4M3B11FNUZAPFloatToAPInt() const;
@@ -656,6 +661,7 @@ class IEEEFloat final : public APFloatBase {
void initFromPPCDoubleDoubleAPInt(const APInt &api);
void initFromFloat8E5M2APInt(const APInt &api);
void initFromFloat8E5M2FNUZAPInt(const APInt &api);
+ void initFromFloat8E4M3APInt(const APInt &api);
void initFromFloat8E4M3FNAPInt(const APInt &api);
void initFromFloat8E4M3FNUZAPInt(const APInt &api);
void initFromFloat8E4M3B11FNUZAPInt(const APInt &api);
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 3017a9b976658..79e0094b243b2 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -136,6 +136,7 @@ static constexpr fltSemantics semIEEEquad = {16383, -16382,
113, 128};
static constexpr fltSemantics semFloat8E5M2 = {15, -14, 3, 8};
static constexpr fltSemantics semFloat8E5M2FNUZ = {
15, -15, 3, 8, fltNonfiniteBehavior::NanOnly,
fltNanEncoding::NegativeZero};
+static constexpr fltSemantics semFloat8E4M3 = {7, -6, 4, 8};
static constexpr fltSemantics semFloat8E4M3FN = {
8, -6, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::AllOnes};
static constexpr fltSemantics semFloat8E4M3FNUZ = {
@@ -208,6 +209,8 @@ const llvm::fltSemantics
&APFloatBase::EnumToSemantics(Semantics S) {
return Float8E5M2();
case S_Float8E5M2FNUZ:
return Float8E5M2FNUZ();
+ case S_Float8E4M3:
+return Float8E4M3();
case S_Float8E4M3F
[clang] [llvm] [APFloat] Add support for f8E4M3 IEEE 754 type (PR #97179)
apivovarov wrote: Changed commit message to "[APFloat] Add support for f8E4M3 IEEE 754 type" to match PR title. And Rebased https://github.com/llvm/llvm-project/pull/97179 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type to mlir (PR #97118)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/97118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E4M3 IEEE 754 type (PR #97179)
@@ -136,6 +136,7 @@ static constexpr fltSemantics semIEEEquad = {16383, -16382,
113, 128};
static constexpr fltSemantics semFloat8E5M2 = {15, -14, 3, 8};
static constexpr fltSemantics semFloat8E5M2FNUZ = {
15, -15, 3, 8, fltNonfiniteBehavior::NanOnly,
fltNanEncoding::NegativeZero};
+static constexpr fltSemantics semFloat8E4M3 = {7, -6, 4, 8};
apivovarov wrote:
`f8E4M3` type follows IEEE 754 convention:
- Exponent bias: 7
- Maximum stored exponent value: 14 (binary 1110)
- Maximum unbiased exponent value: 14 - 7 = 7
- Minimum stored exponent value: 1 (binary 0001)
- Minimum unbiased exponent value: 1 − 7 = −6
- Precision specifies the total number of bits used for the significand
(mantisa), including implicit leading integer bit = 3 + 1 = 4
`fltSemantics semFloat8E4M3 = {7, -6, 4, 8};`:
- maxExponent = 7
- minExponent = -6
- precision = 4
- sizeInBits = 8
- nonFiniteBehavior = fltNonfiniteBehavior::IEEE754
- nanEncoding = fltNanEncoding::IEEE
https://github.com/llvm/llvm-project/pull/97179
___
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[clang] [llvm] [APFloat] Add support for f8E4M3 IEEE 754 type (PR #97179)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/97179 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E4M3 IEEE 754 type (PR #97179)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/97179 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [MLIR] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/97118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [MLIR] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/97118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [MLIR] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/97118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [MLIR] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/97118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E4M3 IEEE 754 type (PR #97179)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/97179 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E4M3 IEEE 754 type (PR #97179)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/97179
>From 42cfec8242442119df7f64e3bcfbdc4de66cc13d Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH] [APFloat] Add support for f8E4M3 IEEE 754 type
---
clang/include/clang/AST/Stmt.h | 6 +--
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h| 6 +++
llvm/lib/Support/APFloat.cpp | 20 +
llvm/unittests/ADT/APFloatTest.cpp | 66 ++
5 files changed, 96 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/AST/Stmt.h b/clang/include/clang/AST/Stmt.h
index 9cd7a364cd3f1..4edb04502f83e 100644
--- a/clang/include/clang/AST/Stmt.h
+++ b/clang/include/clang/AST/Stmt.h
@@ -460,10 +460,10 @@ class alignas(void *) Stmt {
unsigned : NumExprBits;
static_assert(
-llvm::APFloat::S_MaxSemantics < 16,
-"Too many Semantics enum values to fit in bitfield of size 4");
+llvm::APFloat::S_MaxSemantics < 32,
+"Too many Semantics enum values to fit in bitfield of size 5");
LLVM_PREFERRED_TYPE(llvm::APFloat::Semantics)
-unsigned Semantics : 4; // Provides semantics for APFloat construction
+unsigned Semantics : 5; // Provides semantics for APFloat construction
LLVM_PREFERRED_TYPE(bool)
unsigned IsExact : 1;
};
diff --git a/clang/lib/AST/MicrosoftMangle.cpp
b/clang/lib/AST/MicrosoftMangle.cpp
index 7f1e9ab02ec26..a2e270df276cb 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -946,6 +946,7 @@ void MicrosoftCXXNameMangler::mangleFloat(llvm::APFloat
Number) {
case APFloat::S_IEEEquad: Out << 'Y'; break;
case APFloat::S_PPCDoubleDouble: Out << 'Z'; break;
case APFloat::S_Float8E5M2:
+ case APFloat::S_Float8E4M3:
case APFloat::S_Float8E4M3FN:
case APFloat::S_Float8E5M2FNUZ:
case APFloat::S_Float8E4M3FNUZ:
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index db2fa480655c6..bff8e6490d1de 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -166,6 +166,9 @@ struct APFloatBase {
// This format's exponent bias is 16, instead of the 15 (2 ** (5 - 1) - 1)
// that IEEE precedent would imply.
S_Float8E5M2FNUZ,
+// 8-bit floating point number following IEEE-754 conventions with bit
+// layout S1E4M3.
+S_Float8E4M3,
// 8-bit floating point number mostly following IEEE-754 conventions with
// bit layout S1E4M3 as described in https://arxiv.org/abs/2209.05433.
// Unlike IEEE-754 types, there are no infinity values, and NaN is
@@ -217,6 +220,7 @@ struct APFloatBase {
static const fltSemantics &PPCDoubleDouble() LLVM_READNONE;
static const fltSemantics &Float8E5M2() LLVM_READNONE;
static const fltSemantics &Float8E5M2FNUZ() LLVM_READNONE;
+ static const fltSemantics &Float8E4M3() LLVM_READNONE;
static const fltSemantics &Float8E4M3FN() LLVM_READNONE;
static const fltSemantics &Float8E4M3FNUZ() LLVM_READNONE;
static const fltSemantics &Float8E4M3B11FNUZ() LLVM_READNONE;
@@ -638,6 +642,7 @@ class IEEEFloat final : public APFloatBase {
APInt convertPPCDoubleDoubleAPFloatToAPInt() const;
APInt convertFloat8E5M2APFloatToAPInt() const;
APInt convertFloat8E5M2FNUZAPFloatToAPInt() const;
+ APInt convertFloat8E4M3APFloatToAPInt() const;
APInt convertFloat8E4M3FNAPFloatToAPInt() const;
APInt convertFloat8E4M3FNUZAPFloatToAPInt() const;
APInt convertFloat8E4M3B11FNUZAPFloatToAPInt() const;
@@ -656,6 +661,7 @@ class IEEEFloat final : public APFloatBase {
void initFromPPCDoubleDoubleAPInt(const APInt &api);
void initFromFloat8E5M2APInt(const APInt &api);
void initFromFloat8E5M2FNUZAPInt(const APInt &api);
+ void initFromFloat8E4M3APInt(const APInt &api);
void initFromFloat8E4M3FNAPInt(const APInt &api);
void initFromFloat8E4M3FNUZAPInt(const APInt &api);
void initFromFloat8E4M3B11FNUZAPInt(const APInt &api);
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 3017a9b976658..79e0094b243b2 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -136,6 +136,7 @@ static constexpr fltSemantics semIEEEquad = {16383, -16382,
113, 128};
static constexpr fltSemantics semFloat8E5M2 = {15, -14, 3, 8};
static constexpr fltSemantics semFloat8E5M2FNUZ = {
15, -15, 3, 8, fltNonfiniteBehavior::NanOnly,
fltNanEncoding::NegativeZero};
+static constexpr fltSemantics semFloat8E4M3 = {7, -6, 4, 8};
static constexpr fltSemantics semFloat8E4M3FN = {
8, -6, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::AllOnes};
static constexpr fltSemantics semFloat8E4M3FNUZ = {
@@ -208,6 +209,8 @@ const llvm::fltSemantics
&APFloatBase::EnumToSemantics(Semantics S) {
return Float8E5M2();
case S_Float8E5M2FNUZ:
return Float8E5M2FNUZ();
+ case S_Float8E4M3:
+return Float8E4M3();
case S_Float8E4M3F
[clang] [llvm] [mlir] [MLIR] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/97118
>From 42cfec8242442119df7f64e3bcfbdc4de66cc13d Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH 1/2] [APFloat] Add support for f8E4M3 IEEE 754 type
---
clang/include/clang/AST/Stmt.h | 6 +--
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h| 6 +++
llvm/lib/Support/APFloat.cpp | 20 +
llvm/unittests/ADT/APFloatTest.cpp | 66 ++
5 files changed, 96 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/AST/Stmt.h b/clang/include/clang/AST/Stmt.h
index 9cd7a364cd3f1..4edb04502f83e 100644
--- a/clang/include/clang/AST/Stmt.h
+++ b/clang/include/clang/AST/Stmt.h
@@ -460,10 +460,10 @@ class alignas(void *) Stmt {
unsigned : NumExprBits;
static_assert(
-llvm::APFloat::S_MaxSemantics < 16,
-"Too many Semantics enum values to fit in bitfield of size 4");
+llvm::APFloat::S_MaxSemantics < 32,
+"Too many Semantics enum values to fit in bitfield of size 5");
LLVM_PREFERRED_TYPE(llvm::APFloat::Semantics)
-unsigned Semantics : 4; // Provides semantics for APFloat construction
+unsigned Semantics : 5; // Provides semantics for APFloat construction
LLVM_PREFERRED_TYPE(bool)
unsigned IsExact : 1;
};
diff --git a/clang/lib/AST/MicrosoftMangle.cpp
b/clang/lib/AST/MicrosoftMangle.cpp
index 7f1e9ab02ec26..a2e270df276cb 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -946,6 +946,7 @@ void MicrosoftCXXNameMangler::mangleFloat(llvm::APFloat
Number) {
case APFloat::S_IEEEquad: Out << 'Y'; break;
case APFloat::S_PPCDoubleDouble: Out << 'Z'; break;
case APFloat::S_Float8E5M2:
+ case APFloat::S_Float8E4M3:
case APFloat::S_Float8E4M3FN:
case APFloat::S_Float8E5M2FNUZ:
case APFloat::S_Float8E4M3FNUZ:
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index db2fa480655c6..bff8e6490d1de 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -166,6 +166,9 @@ struct APFloatBase {
// This format's exponent bias is 16, instead of the 15 (2 ** (5 - 1) - 1)
// that IEEE precedent would imply.
S_Float8E5M2FNUZ,
+// 8-bit floating point number following IEEE-754 conventions with bit
+// layout S1E4M3.
+S_Float8E4M3,
// 8-bit floating point number mostly following IEEE-754 conventions with
// bit layout S1E4M3 as described in https://arxiv.org/abs/2209.05433.
// Unlike IEEE-754 types, there are no infinity values, and NaN is
@@ -217,6 +220,7 @@ struct APFloatBase {
static const fltSemantics &PPCDoubleDouble() LLVM_READNONE;
static const fltSemantics &Float8E5M2() LLVM_READNONE;
static const fltSemantics &Float8E5M2FNUZ() LLVM_READNONE;
+ static const fltSemantics &Float8E4M3() LLVM_READNONE;
static const fltSemantics &Float8E4M3FN() LLVM_READNONE;
static const fltSemantics &Float8E4M3FNUZ() LLVM_READNONE;
static const fltSemantics &Float8E4M3B11FNUZ() LLVM_READNONE;
@@ -638,6 +642,7 @@ class IEEEFloat final : public APFloatBase {
APInt convertPPCDoubleDoubleAPFloatToAPInt() const;
APInt convertFloat8E5M2APFloatToAPInt() const;
APInt convertFloat8E5M2FNUZAPFloatToAPInt() const;
+ APInt convertFloat8E4M3APFloatToAPInt() const;
APInt convertFloat8E4M3FNAPFloatToAPInt() const;
APInt convertFloat8E4M3FNUZAPFloatToAPInt() const;
APInt convertFloat8E4M3B11FNUZAPFloatToAPInt() const;
@@ -656,6 +661,7 @@ class IEEEFloat final : public APFloatBase {
void initFromPPCDoubleDoubleAPInt(const APInt &api);
void initFromFloat8E5M2APInt(const APInt &api);
void initFromFloat8E5M2FNUZAPInt(const APInt &api);
+ void initFromFloat8E4M3APInt(const APInt &api);
void initFromFloat8E4M3FNAPInt(const APInt &api);
void initFromFloat8E4M3FNUZAPInt(const APInt &api);
void initFromFloat8E4M3B11FNUZAPInt(const APInt &api);
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 3017a9b976658..79e0094b243b2 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -136,6 +136,7 @@ static constexpr fltSemantics semIEEEquad = {16383, -16382,
113, 128};
static constexpr fltSemantics semFloat8E5M2 = {15, -14, 3, 8};
static constexpr fltSemantics semFloat8E5M2FNUZ = {
15, -15, 3, 8, fltNonfiniteBehavior::NanOnly,
fltNanEncoding::NegativeZero};
+static constexpr fltSemantics semFloat8E4M3 = {7, -6, 4, 8};
static constexpr fltSemantics semFloat8E4M3FN = {
8, -6, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::AllOnes};
static constexpr fltSemantics semFloat8E4M3FNUZ = {
@@ -208,6 +209,8 @@ const llvm::fltSemantics
&APFloatBase::EnumToSemantics(Semantics S) {
return Float8E5M2();
case S_Float8E5M2FNUZ:
return Float8E5M2FNUZ();
+ case S_Float8E4M3:
+return Float8E4M3();
case S_Float8E
[clang] [llvm] [mlir] [MLIR] Add f8E4M3 IEEE 754 type (PR #97118)
apivovarov wrote: > Hey @apivovarov I think this needs a rebase on top #97179? Just rebased https://github.com/llvm/llvm-project/pull/97118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [MLIR] Add f8E4M3 IEEE 754 type (PR #97118)
apivovarov wrote: > Hey @apivovarov I just wanted to say my bad for not getting to this yet - I'm > buried at work but I haven't forgotten. If it's hipri I can find someone else > to review. Otherwise ~couple of days I think and I'll be clear to review. Hi Maksim, I think it has standard priority. APFloat PR is quiet for the last 4 days... https://github.com/llvm/llvm-project/pull/97179 . 4th of July week... https://github.com/llvm/llvm-project/pull/97118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E4M3 IEEE 754 type (PR #97179)
apivovarov wrote: Thorsten, Matt, looks like this PR was lost. Can you look at this PR one more time? @tschuett @arsenm https://github.com/llvm/llvm-project/pull/97179 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E3M4 IEEE 754 type (PR #99698)
apivovarov wrote: @tschuett, Could you please help review this change? https://github.com/llvm/llvm-project/pull/99698 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E3M4 IEEE 754 type (PR #99698)
apivovarov wrote: If there are no further questions, comments, or objections, I will merge this PR in a few hours. https://github.com/llvm/llvm-project/pull/99698 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E4M3 IEEE 754 type (PR #97179)
apivovarov wrote: @ThomasRaoux Could you please help with reviewing this PR? It seems that this PR was overlooked. https://github.com/llvm/llvm-project/pull/97179 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E4M3 IEEE 754 type (PR #97179)
apivovarov wrote: If there are no further questions, comments, or objections, I will merge this PR in a few hours. https://github.com/llvm/llvm-project/pull/97179 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E4M3 IEEE 754 type (PR #97179)
https://github.com/apivovarov closed https://github.com/llvm/llvm-project/pull/97179 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E3M4 IEEE 754 type (PR #99698)
https://github.com/apivovarov created
https://github.com/llvm/llvm-project/pull/99698
This PR adds `f8E4M3` type to APFloat.
`f8E3M4` type follows IEEE 754 convention
```c
f8E3M4 (IEEE 754)
- Exponent bias: 3
- Maximum stored exponent value: 6 (binary 110)
- Maximum unbiased exponent value: 6 - 3 = 3
- Minimum stored exponent value: 1 (binary 001)
- Minimum unbiased exponent value: 1 − 3 = −2
- Precision specifies the total number of bits used for the significand
(mantissa),
including implicit leading integer bit = 4 + 1 = 5
- Follows IEEE 754 conventions for representation of special values
- Has Positive and Negative zero
- Has Positive and Negative infinity
- Has NaNs
Additional details:
- Max exp (unbiased): 3
- Min exp (unbiased): -2
- Infinities (+/-): S..000
- Zeros (+/-): S..000
- NaNs: S.111.{0,1}⁴ except S.111.
- Max normal number: S.110. = +/-2^(6-3) x (1 + 15/16) = +/-2^3 x 31 x
2^(-4) = +/-15.5
- Min normal number: S.001. = +/-2^(1-3) x (1 + 0) = +/-2^(-2)
- Max subnormal number: S.000. = +/-2^(-2) x 15/16 = +/-2^(-2) x 15 x
2^(-4) = +/-15 x 2^(-6)
- Min subnormal number: S.000.0001 = +/-2^(-2) x 1/16 = +/-2^(-2) x 2^(-4) =
+/-2^(-6)
```
Related PRs:
- [PR-97179](https://github.com/llvm/llvm-project/pull/97179) [APFloat] Add
support for f8E4M3 IEEE 754 type
>From fdcc285cf016d2dfd7883ad6fd100d676ff9ff52 Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 19 Jul 2024 19:28:33 +
Subject: [PATCH] [APFloat] Add support for f8E3M4 IEEE 754 type
---
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h| 6 +++
llvm/lib/Support/APFloat.cpp | 20
llvm/unittests/ADT/APFloatTest.cpp | 79 ++
4 files changed, 106 insertions(+)
diff --git a/clang/lib/AST/MicrosoftMangle.cpp
b/clang/lib/AST/MicrosoftMangle.cpp
index 4016043df62ed..75627b5d4f4f7 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -986,6 +986,7 @@ void MicrosoftCXXNameMangler::mangleFloat(llvm::APFloat
Number) {
case APFloat::S_Float8E5M2FNUZ:
case APFloat::S_Float8E4M3FNUZ:
case APFloat::S_Float8E4M3B11FNUZ:
+ case APFloat::S_Float8E3M4:
case APFloat::S_FloatTF32:
case APFloat::S_Float6E3M2FN:
case APFloat::S_Float6E2M3FN:
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index bff8e6490d1de..7039e961bff82 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -188,6 +188,9 @@ struct APFloatBase {
// This format's exponent bias is 11, instead of the 7 (2 ** (4 - 1) - 1)
// that IEEE precedent would imply.
S_Float8E4M3B11FNUZ,
+// 8-bit floating point number following IEEE-754 conventions with bit
+// layout S1E3M4.
+S_Float8E3M4,
// Floating point number that occupies 32 bits or less of storage,
providing
// improved range compared to half (16-bit) formats, at (potentially)
// greater throughput than single precision (32-bit) formats.
@@ -224,6 +227,7 @@ struct APFloatBase {
static const fltSemantics &Float8E4M3FN() LLVM_READNONE;
static const fltSemantics &Float8E4M3FNUZ() LLVM_READNONE;
static const fltSemantics &Float8E4M3B11FNUZ() LLVM_READNONE;
+ static const fltSemantics &Float8E3M4() LLVM_READNONE;
static const fltSemantics &FloatTF32() LLVM_READNONE;
static const fltSemantics &Float6E3M2FN() LLVM_READNONE;
static const fltSemantics &Float6E2M3FN() LLVM_READNONE;
@@ -646,6 +650,7 @@ class IEEEFloat final : public APFloatBase {
APInt convertFloat8E4M3FNAPFloatToAPInt() const;
APInt convertFloat8E4M3FNUZAPFloatToAPInt() const;
APInt convertFloat8E4M3B11FNUZAPFloatToAPInt() const;
+ APInt convertFloat8E3M4APFloatToAPInt() const;
APInt convertFloatTF32APFloatToAPInt() const;
APInt convertFloat6E3M2FNAPFloatToAPInt() const;
APInt convertFloat6E2M3FNAPFloatToAPInt() const;
@@ -665,6 +670,7 @@ class IEEEFloat final : public APFloatBase {
void initFromFloat8E4M3FNAPInt(const APInt &api);
void initFromFloat8E4M3FNUZAPInt(const APInt &api);
void initFromFloat8E4M3B11FNUZAPInt(const APInt &api);
+ void initFromFloat8E3M4APInt(const APInt &api);
void initFromFloatTF32APInt(const APInt &api);
void initFromFloat6E3M2FNAPInt(const APInt &api);
void initFromFloat6E2M3FNAPInt(const APInt &api);
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 26b4f8e55448f..7f68c5ab9b7cf 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -143,6 +143,7 @@ static constexpr fltSemantics semFloat8E4M3FNUZ = {
7, -7, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::NegativeZero};
static constexpr fltSemantics semFloat8E4M3B11FNUZ = {
4, -10, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::NegativeZero};
+static constexpr fltSemantics semFloat8E3M4 = {3, -2, 5, 8};
static constexpr fltSemantics semFloatTF32 = {127, -126, 11, 19};
static constexpr f
[clang] [llvm] [APFloat] Add support for f8E3M4 IEEE 754 type (PR #99698)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/99698
>From 1bddc5cd8414453fd1e3b4f1ef297194f54eaa6c Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 19 Jul 2024 19:28:33 +
Subject: [PATCH] [APFloat] Add support for f8E3M4 IEEE 754 type
---
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h| 6 +++
llvm/lib/Support/APFloat.cpp | 20
llvm/unittests/ADT/APFloatTest.cpp | 81 ++
4 files changed, 108 insertions(+)
diff --git a/clang/lib/AST/MicrosoftMangle.cpp
b/clang/lib/AST/MicrosoftMangle.cpp
index 4016043df62ed..75627b5d4f4f7 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -986,6 +986,7 @@ void MicrosoftCXXNameMangler::mangleFloat(llvm::APFloat
Number) {
case APFloat::S_Float8E5M2FNUZ:
case APFloat::S_Float8E4M3FNUZ:
case APFloat::S_Float8E4M3B11FNUZ:
+ case APFloat::S_Float8E3M4:
case APFloat::S_FloatTF32:
case APFloat::S_Float6E3M2FN:
case APFloat::S_Float6E2M3FN:
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index bff8e6490d1de..7039e961bff82 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -188,6 +188,9 @@ struct APFloatBase {
// This format's exponent bias is 11, instead of the 7 (2 ** (4 - 1) - 1)
// that IEEE precedent would imply.
S_Float8E4M3B11FNUZ,
+// 8-bit floating point number following IEEE-754 conventions with bit
+// layout S1E3M4.
+S_Float8E3M4,
// Floating point number that occupies 32 bits or less of storage,
providing
// improved range compared to half (16-bit) formats, at (potentially)
// greater throughput than single precision (32-bit) formats.
@@ -224,6 +227,7 @@ struct APFloatBase {
static const fltSemantics &Float8E4M3FN() LLVM_READNONE;
static const fltSemantics &Float8E4M3FNUZ() LLVM_READNONE;
static const fltSemantics &Float8E4M3B11FNUZ() LLVM_READNONE;
+ static const fltSemantics &Float8E3M4() LLVM_READNONE;
static const fltSemantics &FloatTF32() LLVM_READNONE;
static const fltSemantics &Float6E3M2FN() LLVM_READNONE;
static const fltSemantics &Float6E2M3FN() LLVM_READNONE;
@@ -646,6 +650,7 @@ class IEEEFloat final : public APFloatBase {
APInt convertFloat8E4M3FNAPFloatToAPInt() const;
APInt convertFloat8E4M3FNUZAPFloatToAPInt() const;
APInt convertFloat8E4M3B11FNUZAPFloatToAPInt() const;
+ APInt convertFloat8E3M4APFloatToAPInt() const;
APInt convertFloatTF32APFloatToAPInt() const;
APInt convertFloat6E3M2FNAPFloatToAPInt() const;
APInt convertFloat6E2M3FNAPFloatToAPInt() const;
@@ -665,6 +670,7 @@ class IEEEFloat final : public APFloatBase {
void initFromFloat8E4M3FNAPInt(const APInt &api);
void initFromFloat8E4M3FNUZAPInt(const APInt &api);
void initFromFloat8E4M3B11FNUZAPInt(const APInt &api);
+ void initFromFloat8E3M4APInt(const APInt &api);
void initFromFloatTF32APInt(const APInt &api);
void initFromFloat6E3M2FNAPInt(const APInt &api);
void initFromFloat6E2M3FNAPInt(const APInt &api);
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 26b4f8e55448f..7f68c5ab9b7cf 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -143,6 +143,7 @@ static constexpr fltSemantics semFloat8E4M3FNUZ = {
7, -7, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::NegativeZero};
static constexpr fltSemantics semFloat8E4M3B11FNUZ = {
4, -10, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::NegativeZero};
+static constexpr fltSemantics semFloat8E3M4 = {3, -2, 5, 8};
static constexpr fltSemantics semFloatTF32 = {127, -126, 11, 19};
static constexpr fltSemantics semFloat6E3M2FN = {
4, -2, 3, 6, fltNonfiniteBehavior::FiniteOnly};
@@ -217,6 +218,8 @@ const llvm::fltSemantics
&APFloatBase::EnumToSemantics(Semantics S) {
return Float8E4M3FNUZ();
case S_Float8E4M3B11FNUZ:
return Float8E4M3B11FNUZ();
+ case S_Float8E3M4:
+return Float8E3M4();
case S_FloatTF32:
return FloatTF32();
case S_Float6E3M2FN:
@@ -257,6 +260,8 @@ APFloatBase::SemanticsToEnum(const llvm::fltSemantics &Sem)
{
return S_Float8E4M3FNUZ;
else if (&Sem == &llvm::APFloat::Float8E4M3B11FNUZ())
return S_Float8E4M3B11FNUZ;
+ else if (&Sem == &llvm::APFloat::Float8E3M4())
+return S_Float8E3M4;
else if (&Sem == &llvm::APFloat::FloatTF32())
return S_FloatTF32;
else if (&Sem == &llvm::APFloat::Float6E3M2FN())
@@ -287,6 +292,7 @@ const fltSemantics &APFloatBase::Float8E4M3FNUZ() { return
semFloat8E4M3FNUZ; }
const fltSemantics &APFloatBase::Float8E4M3B11FNUZ() {
return semFloat8E4M3B11FNUZ;
}
+const fltSemantics &APFloatBase::Float8E3M4() { return semFloat8E3M4; }
const fltSemantics &APFloatBase::FloatTF32() { return semFloatTF32; }
const fltSemantics &APFloatBase::Float6E3M2FN() { return semFloat6E3M2FN; }
const fltSemantics &APFloatBase::Float6E2M3
[clang] [llvm] [APFloat] Add support for f8E3M4 IEEE 754 type (PR #99698)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/99698 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E3M4 IEEE 754 type (PR #99698)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/99698 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [APFloat] Add support for f8E3M4 IEEE 754 type (PR #99698)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/99698 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] [MLIR] Add f8E4M3 IEEE 754 type (PR #97118)
@@ -136,6 +136,7 @@ static constexpr fltSemantics semIEEEquad = {16383, -16382,
113, 128};
static constexpr fltSemantics semFloat8E5M2 = {15, -14, 3, 8};
static constexpr fltSemantics semFloat8E5M2FNUZ = {
15, -15, 3, 8, fltNonfiniteBehavior::NanOnly,
fltNanEncoding::NegativeZero};
+static constexpr fltSemantics semFloat8E4M3 = {7, -6, 4, 8};
apivovarov wrote:
Maksim, Adding f8E4M3 IEE754 dtype was split into two PRs:
1. llvm/clang/APFloat changes
[PR-97179](https://github.com/llvm/llvm-project/pull/97179)
2. MLIR changes [PR-97118](https://github.com/llvm/llvm-project/pull/97118)
(this PR)
PR-97118 depends on PR-97179.
Currently you see two commits in PR-97118.
Once PR-97179 is merged - I'll rebase PR-97118 and it will contain just one
commit - just MLIR changes.
Can you review just MLIR changes in this PR (PR-97118). All comments for
llvm/clang/APFloat should go to
[PR-97179](https://github.com/llvm/llvm-project/pull/97179).
https://github.com/llvm/llvm-project/pull/97118
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[clang] [llvm] [mlir] [MLIR] Add f8E4M3 IEEE 754 type (PR #97118)
@@ -460,10 +460,10 @@ class alignas(void *) Stmt {
unsigned : NumExprBits;
static_assert(
-llvm::APFloat::S_MaxSemantics < 16,
-"Too many Semantics enum values to fit in bitfield of size 4");
+llvm::APFloat::S_MaxSemantics < 32,
+"Too many Semantics enum values to fit in bitfield of size 5");
LLVM_PREFERRED_TYPE(llvm::APFloat::Semantics)
-unsigned Semantics : 4; // Provides semantics for APFloat construction
apivovarov wrote:
This code is from [PR-97179](https://github.com/llvm/llvm-project/pull/97179).
Need to use one additional byte to store new item with id 16 (total 17 items)
https://github.com/llvm/llvm-project/pull/97118
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[clang] [llvm] [APFloat] Add support for f8E4M3 IEEE 754 type (PR #97179)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/97179
>From 9b2e06f794ce810e9a7e68be64c46c2a31d695d9 Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH] [APFloat] Add support for f8E4M3 IEEE 754 type
---
clang/include/clang/AST/Stmt.h | 6 +--
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h| 6 +++
llvm/lib/Support/APFloat.cpp | 20 +
llvm/unittests/ADT/APFloatTest.cpp | 66 ++
5 files changed, 96 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/AST/Stmt.h b/clang/include/clang/AST/Stmt.h
index 257a61c97c9c6..ba14d6c64f025 100644
--- a/clang/include/clang/AST/Stmt.h
+++ b/clang/include/clang/AST/Stmt.h
@@ -460,10 +460,10 @@ class alignas(void *) Stmt {
unsigned : NumExprBits;
static_assert(
-llvm::APFloat::S_MaxSemantics < 16,
-"Too many Semantics enum values to fit in bitfield of size 4");
+llvm::APFloat::S_MaxSemantics < 32,
+"Too many Semantics enum values to fit in bitfield of size 5");
LLVM_PREFERRED_TYPE(llvm::APFloat::Semantics)
-unsigned Semantics : 4; // Provides semantics for APFloat construction
+unsigned Semantics : 5; // Provides semantics for APFloat construction
LLVM_PREFERRED_TYPE(bool)
unsigned IsExact : 1;
};
diff --git a/clang/lib/AST/MicrosoftMangle.cpp
b/clang/lib/AST/MicrosoftMangle.cpp
index fac14ce1dce8c..4016043df62ed 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -981,6 +981,7 @@ void MicrosoftCXXNameMangler::mangleFloat(llvm::APFloat
Number) {
case APFloat::S_IEEEquad: Out << 'Y'; break;
case APFloat::S_PPCDoubleDouble: Out << 'Z'; break;
case APFloat::S_Float8E5M2:
+ case APFloat::S_Float8E4M3:
case APFloat::S_Float8E4M3FN:
case APFloat::S_Float8E5M2FNUZ:
case APFloat::S_Float8E4M3FNUZ:
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index db2fa480655c6..bff8e6490d1de 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -166,6 +166,9 @@ struct APFloatBase {
// This format's exponent bias is 16, instead of the 15 (2 ** (5 - 1) - 1)
// that IEEE precedent would imply.
S_Float8E5M2FNUZ,
+// 8-bit floating point number following IEEE-754 conventions with bit
+// layout S1E4M3.
+S_Float8E4M3,
// 8-bit floating point number mostly following IEEE-754 conventions with
// bit layout S1E4M3 as described in https://arxiv.org/abs/2209.05433.
// Unlike IEEE-754 types, there are no infinity values, and NaN is
@@ -217,6 +220,7 @@ struct APFloatBase {
static const fltSemantics &PPCDoubleDouble() LLVM_READNONE;
static const fltSemantics &Float8E5M2() LLVM_READNONE;
static const fltSemantics &Float8E5M2FNUZ() LLVM_READNONE;
+ static const fltSemantics &Float8E4M3() LLVM_READNONE;
static const fltSemantics &Float8E4M3FN() LLVM_READNONE;
static const fltSemantics &Float8E4M3FNUZ() LLVM_READNONE;
static const fltSemantics &Float8E4M3B11FNUZ() LLVM_READNONE;
@@ -638,6 +642,7 @@ class IEEEFloat final : public APFloatBase {
APInt convertPPCDoubleDoubleAPFloatToAPInt() const;
APInt convertFloat8E5M2APFloatToAPInt() const;
APInt convertFloat8E5M2FNUZAPFloatToAPInt() const;
+ APInt convertFloat8E4M3APFloatToAPInt() const;
APInt convertFloat8E4M3FNAPFloatToAPInt() const;
APInt convertFloat8E4M3FNUZAPFloatToAPInt() const;
APInt convertFloat8E4M3B11FNUZAPFloatToAPInt() const;
@@ -656,6 +661,7 @@ class IEEEFloat final : public APFloatBase {
void initFromPPCDoubleDoubleAPInt(const APInt &api);
void initFromFloat8E5M2APInt(const APInt &api);
void initFromFloat8E5M2FNUZAPInt(const APInt &api);
+ void initFromFloat8E4M3APInt(const APInt &api);
void initFromFloat8E4M3FNAPInt(const APInt &api);
void initFromFloat8E4M3FNUZAPInt(const APInt &api);
void initFromFloat8E4M3B11FNUZAPInt(const APInt &api);
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 3664de71d06df..26b4f8e55448f 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -136,6 +136,7 @@ static constexpr fltSemantics semIEEEquad = {16383, -16382,
113, 128};
static constexpr fltSemantics semFloat8E5M2 = {15, -14, 3, 8};
static constexpr fltSemantics semFloat8E5M2FNUZ = {
15, -15, 3, 8, fltNonfiniteBehavior::NanOnly,
fltNanEncoding::NegativeZero};
+static constexpr fltSemantics semFloat8E4M3 = {7, -6, 4, 8};
static constexpr fltSemantics semFloat8E4M3FN = {
8, -6, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::AllOnes};
static constexpr fltSemantics semFloat8E4M3FNUZ = {
@@ -208,6 +209,8 @@ const llvm::fltSemantics
&APFloatBase::EnumToSemantics(Semantics S) {
return Float8E5M2();
case S_Float8E5M2FNUZ:
return Float8E5M2FNUZ();
+ case S_Float8E4M3:
+return Float8E4M3();
case S_Float8E4M3F
[clang] [llvm] [mlir] [MLIR] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/97118
>From 9b2e06f794ce810e9a7e68be64c46c2a31d695d9 Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH 1/2] [APFloat] Add support for f8E4M3 IEEE 754 type
---
clang/include/clang/AST/Stmt.h | 6 +--
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h| 6 +++
llvm/lib/Support/APFloat.cpp | 20 +
llvm/unittests/ADT/APFloatTest.cpp | 66 ++
5 files changed, 96 insertions(+), 3 deletions(-)
diff --git a/clang/include/clang/AST/Stmt.h b/clang/include/clang/AST/Stmt.h
index 257a61c97c9c6..ba14d6c64f025 100644
--- a/clang/include/clang/AST/Stmt.h
+++ b/clang/include/clang/AST/Stmt.h
@@ -460,10 +460,10 @@ class alignas(void *) Stmt {
unsigned : NumExprBits;
static_assert(
-llvm::APFloat::S_MaxSemantics < 16,
-"Too many Semantics enum values to fit in bitfield of size 4");
+llvm::APFloat::S_MaxSemantics < 32,
+"Too many Semantics enum values to fit in bitfield of size 5");
LLVM_PREFERRED_TYPE(llvm::APFloat::Semantics)
-unsigned Semantics : 4; // Provides semantics for APFloat construction
+unsigned Semantics : 5; // Provides semantics for APFloat construction
LLVM_PREFERRED_TYPE(bool)
unsigned IsExact : 1;
};
diff --git a/clang/lib/AST/MicrosoftMangle.cpp
b/clang/lib/AST/MicrosoftMangle.cpp
index fac14ce1dce8c..4016043df62ed 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -981,6 +981,7 @@ void MicrosoftCXXNameMangler::mangleFloat(llvm::APFloat
Number) {
case APFloat::S_IEEEquad: Out << 'Y'; break;
case APFloat::S_PPCDoubleDouble: Out << 'Z'; break;
case APFloat::S_Float8E5M2:
+ case APFloat::S_Float8E4M3:
case APFloat::S_Float8E4M3FN:
case APFloat::S_Float8E5M2FNUZ:
case APFloat::S_Float8E4M3FNUZ:
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index db2fa480655c6..bff8e6490d1de 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -166,6 +166,9 @@ struct APFloatBase {
// This format's exponent bias is 16, instead of the 15 (2 ** (5 - 1) - 1)
// that IEEE precedent would imply.
S_Float8E5M2FNUZ,
+// 8-bit floating point number following IEEE-754 conventions with bit
+// layout S1E4M3.
+S_Float8E4M3,
// 8-bit floating point number mostly following IEEE-754 conventions with
// bit layout S1E4M3 as described in https://arxiv.org/abs/2209.05433.
// Unlike IEEE-754 types, there are no infinity values, and NaN is
@@ -217,6 +220,7 @@ struct APFloatBase {
static const fltSemantics &PPCDoubleDouble() LLVM_READNONE;
static const fltSemantics &Float8E5M2() LLVM_READNONE;
static const fltSemantics &Float8E5M2FNUZ() LLVM_READNONE;
+ static const fltSemantics &Float8E4M3() LLVM_READNONE;
static const fltSemantics &Float8E4M3FN() LLVM_READNONE;
static const fltSemantics &Float8E4M3FNUZ() LLVM_READNONE;
static const fltSemantics &Float8E4M3B11FNUZ() LLVM_READNONE;
@@ -638,6 +642,7 @@ class IEEEFloat final : public APFloatBase {
APInt convertPPCDoubleDoubleAPFloatToAPInt() const;
APInt convertFloat8E5M2APFloatToAPInt() const;
APInt convertFloat8E5M2FNUZAPFloatToAPInt() const;
+ APInt convertFloat8E4M3APFloatToAPInt() const;
APInt convertFloat8E4M3FNAPFloatToAPInt() const;
APInt convertFloat8E4M3FNUZAPFloatToAPInt() const;
APInt convertFloat8E4M3B11FNUZAPFloatToAPInt() const;
@@ -656,6 +661,7 @@ class IEEEFloat final : public APFloatBase {
void initFromPPCDoubleDoubleAPInt(const APInt &api);
void initFromFloat8E5M2APInt(const APInt &api);
void initFromFloat8E5M2FNUZAPInt(const APInt &api);
+ void initFromFloat8E4M3APInt(const APInt &api);
void initFromFloat8E4M3FNAPInt(const APInt &api);
void initFromFloat8E4M3FNUZAPInt(const APInt &api);
void initFromFloat8E4M3B11FNUZAPInt(const APInt &api);
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 3664de71d06df..26b4f8e55448f 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -136,6 +136,7 @@ static constexpr fltSemantics semIEEEquad = {16383, -16382,
113, 128};
static constexpr fltSemantics semFloat8E5M2 = {15, -14, 3, 8};
static constexpr fltSemantics semFloat8E5M2FNUZ = {
15, -15, 3, 8, fltNonfiniteBehavior::NanOnly,
fltNanEncoding::NegativeZero};
+static constexpr fltSemantics semFloat8E4M3 = {7, -6, 4, 8};
static constexpr fltSemantics semFloat8E4M3FN = {
8, -6, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::AllOnes};
static constexpr fltSemantics semFloat8E4M3FNUZ = {
@@ -208,6 +209,8 @@ const llvm::fltSemantics
&APFloatBase::EnumToSemantics(Semantics S) {
return Float8E5M2();
case S_Float8E5M2FNUZ:
return Float8E5M2FNUZ();
+ case S_Float8E4M3:
+return Float8E4M3();
case S_Float8E
[clang] [llvm] [APFloat] Add support for f8E4M3 IEEE 754 type (PR #97179)
apivovarov wrote: Hi @tschuett, @arsenm I wanted to kindly request your review on this f8E4M3 PR when you have a moment. https://github.com/llvm/llvm-project/pull/97179 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 6cd4b50 - [RISCV] Add SiFive core S51
Author: Alexander Pivovarov
Date: 2021-09-02T18:45:25-07:00
New Revision: 6cd4b508a8a51ecd16d2b0297dfeb445ab41b42e
URL:
https://github.com/llvm/llvm-project/commit/6cd4b508a8a51ecd16d2b0297dfeb445ab41b42e
DIFF:
https://github.com/llvm/llvm-project/commit/6cd4b508a8a51ecd16d2b0297dfeb445ab41b42e.diff
LOG: [RISCV] Add SiFive core S51
Add SiFive core s51 as rv64imac RocketModel
Reviewed-By: MaskRay, evandro
Differential Revision: https://reviews.llvm.org/D108886
Added:
Modified:
clang/docs/ReleaseNotes.rst
clang/test/Driver/riscv-cpus.c
clang/test/Misc/target-invalid-cpu-note.c
llvm/include/llvm/Support/RISCVTargetParser.def
llvm/lib/Target/RISCV/RISCV.td
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 8bae1ed29eeb8..c62cefc54a663 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -71,7 +71,9 @@ Deprecated Compiler Flags
Modified Compiler Flags
---
-- ...
+- Support has been added for the following processors (``-mcpu`` identifiers
in parentheses):
+
+ - RISC-V SiFive S51 (``sifive-s51``).
Removed Compiler Flags
-
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index bca25059fd21d..4c26bf8751c27 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -45,6 +45,13 @@
// RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series |
FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
// MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 |
FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
+// MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
+// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
+
// mcpu with default march
// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck
-check-prefix=MCPU-SIFIVE-U54 %s
// MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 837ec4a6a4427..8963c309e6dbe 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -196,7 +196,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-7-rv64, sifive-u54, sifive-u74
+// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -204,4 +204,4 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-7-rv64, sifive-u54, sifive-u74, generic, rocket, sifive-7-series
+// TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64,
sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74, generic, rocket,
sifive-7-series
diff --git a/llvm/include/llvm/Support/RISCVTargetParser.def
b/llvm/include/llvm/Support/RISCVTargetParser.def
index 6a06f9258105c..01f560ae99a0e 100644
--- a/llvm/include/llvm/Support/RISCVTargetParser.def
+++ b/llvm/include/llvm/Support/RISCVTargetParser.def
@@ -20,6 +20,7 @@ PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""})
PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 52e8d8cdc7742..61034fd7295c7 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -254,6 +254,11 @@ def : ProcessorModel<"sifive-e31", RocketModel,
[FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtC]>;
+def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
+ FeatureStdExtM,
+ Fea
[clang] 4bc8dbe - [RISCV] Add SiFive cores E and S series
Author: Alexander Pivovarov Date: 2021-09-08T23:59:04-07:00 New Revision: 4bc8dbe0cae32f15008c1e98e7dd7d128e9dcbb6 URL: https://github.com/llvm/llvm-project/commit/4bc8dbe0cae32f15008c1e98e7dd7d128e9dcbb6 DIFF: https://github.com/llvm/llvm-project/commit/4bc8dbe0cae32f15008c1e98e7dd7d128e9dcbb6.diff LOG: [RISCV] Add SiFive cores E and S series Add SiFive cores E20, E21, E24, E34, S21, S54 and S76 Differential Revision: https://reviews.llvm.org/D109260 Added: Modified: clang/docs/ReleaseNotes.rst clang/test/Driver/riscv-cpus.c clang/test/Misc/target-invalid-cpu-note.c llvm/include/llvm/Support/RISCVTargetParser.def llvm/lib/Target/RISCV/RISCV.td Removed: diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 6caf24ca4ef77..56f91b4e5877f 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -73,7 +73,14 @@ Modified Compiler Flags - Support has been added for the following processors (``-mcpu`` identifiers in parentheses): + - RISC-V SiFive E20 (``sifive-e20``). + - RISC-V SiFive E21 (``sifive-e21``). + - RISC-V SiFive E24 (``sifive-e24``). + - RISC-V SiFive E34 (``sifive-e34``). + - RISC-V SiFive S21 (``sifive-s21``). - RISC-V SiFive S51 (``sifive-s51``). + - RISC-V SiFive S54 (``sifive-s54``). + - RISC-V SiFive S76 (``sifive-s76``). Removed Compiler Flags - diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 4c26bf8751c27..444b0aef623a1 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -45,6 +45,39 @@ // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64" +// mcpu with default march +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e20 | FileCheck -check-prefix=MCPU-SIFIVE-E20 %s +// MCPU-SIFIVE-E20: "-nostdsysteminc" "-target-cpu" "sifive-e20" +// MCPU-SIFIVE-E20: "-target-feature" "+m" "-target-feature" "+c" +// MCPU-SIFIVE-E20: "-target-abi" "ilp32" + +// mcpu with default march +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e21 | FileCheck -check-prefix=MCPU-SIFIVE-E21 %s +// MCPU-SIFIVE-E21: "-nostdsysteminc" "-target-cpu" "sifive-e21" +// MCPU-SIFIVE-E21: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+c" +// MCPU-SIFIVE-E21: "-target-abi" "ilp32" + +// mcpu with default march +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e24 | FileCheck -check-prefix=MCPU-SIFIVE-E24 %s +// MCPU-SIFIVE-E24: "-nostdsysteminc" "-target-cpu" "sifive-e24" +// MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" +// MCPU-SIFIVE-E24: "-target-feature" "+c" +// MCPU-SIFIVE-E24: "-target-abi" "ilp32" + +// mcpu with default march +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s +// MCPU-SIFIVE-E34: "-nostdsysteminc" "-target-cpu" "sifive-e34" +// MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" +// MCPU-SIFIVE-E34: "-target-feature" "+c" +// MCPU-SIFIVE-E34: "-target-abi" "ilp32" + +// mcpu with mabi option +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s +// MCPU-ABI-SIFIVE-S21: "-nostdsysteminc" "-target-cpu" "sifive-s21" +// MCPU-ABI-SIFIVE-S21: "-target-feature" "+m" "-target-feature" "+a" +// MCPU-ABI-SIFIVE-S21: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-ABI-SIFIVE-S21: "-target-abi" "lp64" + // mcpu with mabi option // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s // MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51" @@ -52,6 +85,20 @@ // MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit" // MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64" +// mcpu with default march +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s54 | FileCheck -check-prefix=MCPU-SIFIVE-S54 %s +// MCPU-SIFIVE-S54: "-nostdsysteminc" "-target-cpu" "sifive-s54" +// MCPU-SIFIVE-S54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" +// MCPU-SIFIVE-S54: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-SIFIVE-S54: "-target-abi" "lp64d" + +// mcpu with mabi option +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s76 | FileCheck -check-prefix=MCPU-SIFIVE-S76 %s +// MCPU-SIFIVE-S76: "-nostdsysteminc" "-target-cpu" "sifive-s76" +// MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" +// MCPU-SIFIVE-S76: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-SIFIVE-S76: "-target-abi" "lp64d" + // mcpu with default march //
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov created
https://github.com/llvm/llvm-project/pull/97118
This PR adds `f8E4M3` type which follows IEEE 754 convention
```c
f8E4M3 (IEEE 754)
- Exponent: 4
- Mantissa: 3
- Exponent bias: 7
- Follows IEEE 754 conventions for representation of special values
- Has Positive and Negative zero
- Has Positive and Negative infinity
- Has NaNs
Additional details:
- Max exp (unbiased): 7
- Min exp (unbiased): -6
- Infinities (+/-): S..000
- Zeros (+/-): S..000
- NaNs: S..{001, 010, 011, 100, 101, 110, 111}
- Max normal number: S.1110.111 = +/-240
- Min normal number: S.0001.000 = +/-2^(-6)
- Max subnormal number: S..111 = +/-2^(-6) x 0.875
- Min subnormal number: S..001 = +/-2^(-6) x 0.125 = +/-2^(-9)
```
>From f6d1c7120bbb382a5b38bd2172e743e7808e304c Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 19:33:21 +
Subject: [PATCH 1/2] Rename f8E4M3 to f8E4M3FN in mlir.extras.types py package
---
llvm/lib/Support/APFloat.cpp | 4 ++--
llvm/unittests/ADT/APFloatTest.cpp | 12 ++--
mlir/python/mlir/extras/types.py | 2 +-
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 47618bc325951..3017a9b976658 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -83,8 +83,8 @@ enum class fltNanEncoding {
// exponent is all 1s and the significand is non-zero.
IEEE,
- // Represents the behavior in the Float8E4M3 floating point type where NaN is
- // represented by having the exponent and mantissa set to all 1s.
+ // Represents the behavior in the Float8E4M3FN floating point type where NaN
+ // is represented by having the exponent and mantissa set to all 1s.
// This behavior matches the FP8 E4M3 type described in
// https://arxiv.org/abs/2209.05433. We treat both signed and unsigned NaNs
// as non-signalling, although the paper does not state whether the NaN
diff --git a/llvm/unittests/ADT/APFloatTest.cpp
b/llvm/unittests/ADT/APFloatTest.cpp
index cf6bbd313c6c6..86a25f4394e19 100644
--- a/llvm/unittests/ADT/APFloatTest.cpp
+++ b/llvm/unittests/ADT/APFloatTest.cpp
@@ -5508,8 +5508,8 @@ TEST(APFloatTest, ConvertE4M3FNToE5M2) {
EXPECT_TRUE(losesInfo);
EXPECT_EQ(status, APFloat::opInexact);
- // Convert E4M3 denormal to E5M2 normal. Should not be truncated, despite the
- // destination format having one fewer significand bit
+ // Convert E4M3FN denormal to E5M2 normal. Should not be truncated, despite
+ // the destination format having one fewer significand bit
test = APFloat(APFloat::Float8E4M3FN(), "0x1.Cp-7");
status = test.convert(APFloat::Float8E5M2(), APFloat::rmNearestTiesToEven,
&losesInfo);
@@ -5647,8 +5647,8 @@ TEST(APFloatTest, Float8E4M3FNAdd) {
int category;
APFloat::roundingMode roundingMode = APFloat::rmNearestTiesToEven;
} AdditionTests[] = {
- // Test addition operations involving NaN, overflow, and the max E4M3
- // value (448) because E4M3 differs from IEEE-754 types in these regards
+ // Test addition operations involving NaN, overflow, and the max E4M3FN
+ // value (448) because E4M3FN differs from IEEE-754 types in these
regards
{FromStr("448"), FromStr("16"), "448", APFloat::opInexact,
APFloat::fcNormal},
{FromStr("448"), FromStr("18"), "NaN",
@@ -6278,8 +6278,8 @@ TEST(APFloatTest, ConvertE4M3FNUZToE5M2FNUZ) {
EXPECT_TRUE(losesInfo);
EXPECT_EQ(status, APFloat::opInexact);
- // Convert E4M3 denormal to E5M2 normal. Should not be truncated, despite the
- // destination format having one fewer significand bit
+ // Convert E4M3FNUZ denormal to E5M2 normal. Should not be truncated, despite
+ // the destination format having one fewer significand bit
losesInfo = true;
test = APFloat(APFloat::Float8E4M3FNUZ(), "0x1.Cp-8");
status = test.convert(APFloat::Float8E5M2FNUZ(),
APFloat::rmNearestTiesToEven,
diff --git a/mlir/python/mlir/extras/types.py b/mlir/python/mlir/extras/types.py
index db9e8229fb288..b93c46b172a9a 100644
--- a/mlir/python/mlir/extras/types.py
+++ b/mlir/python/mlir/extras/types.py
@@ -68,7 +68,7 @@ def ui(width):
bf16 = lambda: BF16Type.get()
f8E5M2 = lambda: Float8E5M2Type.get()
-f8E4M3 = lambda: Float8E4M3FNType.get()
+f8E4M3FN = lambda: Float8E4M3FNType.get()
f8E4M3B11FNUZ = lambda: Float8E4M3B11FNUZType.get()
none = lambda: NoneType.get()
>From e1e100548b17cab0596e388621a9e07f82cfc64e Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH 2/2] Add f8E4M3 IEEE 754 type
---
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h | 6 +++
llvm/lib/Support/APFloat.cpp | 20 ++
llvm/unittests/ADT/APFloatTest.cpp| 38 +++
mlir/include/mlir-c/BuiltinTypes.h| 10 +
mlir/include/mlir/IR/Bui
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/97118
>From f6d1c7120bbb382a5b38bd2172e743e7808e304c Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 19:33:21 +
Subject: [PATCH 1/2] Rename f8E4M3 to f8E4M3FN in mlir.extras.types py package
---
llvm/lib/Support/APFloat.cpp | 4 ++--
llvm/unittests/ADT/APFloatTest.cpp | 12 ++--
mlir/python/mlir/extras/types.py | 2 +-
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 47618bc325951..3017a9b976658 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -83,8 +83,8 @@ enum class fltNanEncoding {
// exponent is all 1s and the significand is non-zero.
IEEE,
- // Represents the behavior in the Float8E4M3 floating point type where NaN is
- // represented by having the exponent and mantissa set to all 1s.
+ // Represents the behavior in the Float8E4M3FN floating point type where NaN
+ // is represented by having the exponent and mantissa set to all 1s.
// This behavior matches the FP8 E4M3 type described in
// https://arxiv.org/abs/2209.05433. We treat both signed and unsigned NaNs
// as non-signalling, although the paper does not state whether the NaN
diff --git a/llvm/unittests/ADT/APFloatTest.cpp
b/llvm/unittests/ADT/APFloatTest.cpp
index cf6bbd313c6c6..86a25f4394e19 100644
--- a/llvm/unittests/ADT/APFloatTest.cpp
+++ b/llvm/unittests/ADT/APFloatTest.cpp
@@ -5508,8 +5508,8 @@ TEST(APFloatTest, ConvertE4M3FNToE5M2) {
EXPECT_TRUE(losesInfo);
EXPECT_EQ(status, APFloat::opInexact);
- // Convert E4M3 denormal to E5M2 normal. Should not be truncated, despite the
- // destination format having one fewer significand bit
+ // Convert E4M3FN denormal to E5M2 normal. Should not be truncated, despite
+ // the destination format having one fewer significand bit
test = APFloat(APFloat::Float8E4M3FN(), "0x1.Cp-7");
status = test.convert(APFloat::Float8E5M2(), APFloat::rmNearestTiesToEven,
&losesInfo);
@@ -5647,8 +5647,8 @@ TEST(APFloatTest, Float8E4M3FNAdd) {
int category;
APFloat::roundingMode roundingMode = APFloat::rmNearestTiesToEven;
} AdditionTests[] = {
- // Test addition operations involving NaN, overflow, and the max E4M3
- // value (448) because E4M3 differs from IEEE-754 types in these regards
+ // Test addition operations involving NaN, overflow, and the max E4M3FN
+ // value (448) because E4M3FN differs from IEEE-754 types in these
regards
{FromStr("448"), FromStr("16"), "448", APFloat::opInexact,
APFloat::fcNormal},
{FromStr("448"), FromStr("18"), "NaN",
@@ -6278,8 +6278,8 @@ TEST(APFloatTest, ConvertE4M3FNUZToE5M2FNUZ) {
EXPECT_TRUE(losesInfo);
EXPECT_EQ(status, APFloat::opInexact);
- // Convert E4M3 denormal to E5M2 normal. Should not be truncated, despite the
- // destination format having one fewer significand bit
+ // Convert E4M3FNUZ denormal to E5M2 normal. Should not be truncated, despite
+ // the destination format having one fewer significand bit
losesInfo = true;
test = APFloat(APFloat::Float8E4M3FNUZ(), "0x1.Cp-8");
status = test.convert(APFloat::Float8E5M2FNUZ(),
APFloat::rmNearestTiesToEven,
diff --git a/mlir/python/mlir/extras/types.py b/mlir/python/mlir/extras/types.py
index db9e8229fb288..b93c46b172a9a 100644
--- a/mlir/python/mlir/extras/types.py
+++ b/mlir/python/mlir/extras/types.py
@@ -68,7 +68,7 @@ def ui(width):
bf16 = lambda: BF16Type.get()
f8E5M2 = lambda: Float8E5M2Type.get()
-f8E4M3 = lambda: Float8E4M3FNType.get()
+f8E4M3FN = lambda: Float8E4M3FNType.get()
f8E4M3B11FNUZ = lambda: Float8E4M3B11FNUZType.get()
none = lambda: NoneType.get()
>From 26fce2716911283d29cf1d0972c5fcecc2c7d4ec Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH 2/2] Add f8E4M3 IEEE 754 type
---
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h | 6 +++
llvm/lib/Support/APFloat.cpp | 20 ++
llvm/unittests/ADT/APFloatTest.cpp| 38 +++
mlir/include/mlir-c/BuiltinTypes.h| 10 +
mlir/include/mlir/IR/Builders.h | 1 +
mlir/include/mlir/IR/BuiltinTypes.h | 13 +--
mlir/include/mlir/IR/BuiltinTypes.td | 19 ++
mlir/include/mlir/IR/CommonTypeConstraints.td | 2 +
mlir/include/mlir/IR/Types.h | 1 +
mlir/lib/AsmParser/TokenKinds.def | 1 +
mlir/lib/AsmParser/TypeParser.cpp | 4 ++
mlir/lib/Bindings/Python/IRTypes.cpp | 23 ++-
mlir/lib/CAPI/IR/BuiltinTypes.cpp | 12 ++
.../Conversion/LLVMCommon/TypeConverter.cpp | 5 ++-
.../Transforms/EmulateUnsupportedFloats.cpp | 1 +
mlir/lib/IR/AsmPrinter.cpp| 1 +
mlir/lib/IR/Bui
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/97118
>From 8b0671585864e13d26596b9e8ada39364c542517 Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 19:33:21 +
Subject: [PATCH 1/2] Rename f8E4M3 to f8E4M3FN in mlir.extras.types py package
---
llvm/lib/Support/APFloat.cpp | 4 ++--
llvm/unittests/ADT/APFloatTest.cpp | 12 ++--
mlir/python/mlir/extras/types.py | 2 +-
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 47618bc325951..3017a9b976658 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -83,8 +83,8 @@ enum class fltNanEncoding {
// exponent is all 1s and the significand is non-zero.
IEEE,
- // Represents the behavior in the Float8E4M3 floating point type where NaN is
- // represented by having the exponent and mantissa set to all 1s.
+ // Represents the behavior in the Float8E4M3FN floating point type where NaN
+ // is represented by having the exponent and mantissa set to all 1s.
// This behavior matches the FP8 E4M3 type described in
// https://arxiv.org/abs/2209.05433. We treat both signed and unsigned NaNs
// as non-signalling, although the paper does not state whether the NaN
diff --git a/llvm/unittests/ADT/APFloatTest.cpp
b/llvm/unittests/ADT/APFloatTest.cpp
index cf6bbd313c6c6..86a25f4394e19 100644
--- a/llvm/unittests/ADT/APFloatTest.cpp
+++ b/llvm/unittests/ADT/APFloatTest.cpp
@@ -5508,8 +5508,8 @@ TEST(APFloatTest, ConvertE4M3FNToE5M2) {
EXPECT_TRUE(losesInfo);
EXPECT_EQ(status, APFloat::opInexact);
- // Convert E4M3 denormal to E5M2 normal. Should not be truncated, despite the
- // destination format having one fewer significand bit
+ // Convert E4M3FN denormal to E5M2 normal. Should not be truncated, despite
+ // the destination format having one fewer significand bit
test = APFloat(APFloat::Float8E4M3FN(), "0x1.Cp-7");
status = test.convert(APFloat::Float8E5M2(), APFloat::rmNearestTiesToEven,
&losesInfo);
@@ -5647,8 +5647,8 @@ TEST(APFloatTest, Float8E4M3FNAdd) {
int category;
APFloat::roundingMode roundingMode = APFloat::rmNearestTiesToEven;
} AdditionTests[] = {
- // Test addition operations involving NaN, overflow, and the max E4M3
- // value (448) because E4M3 differs from IEEE-754 types in these regards
+ // Test addition operations involving NaN, overflow, and the max E4M3FN
+ // value (448) because E4M3FN differs from IEEE-754 types in these
regards
{FromStr("448"), FromStr("16"), "448", APFloat::opInexact,
APFloat::fcNormal},
{FromStr("448"), FromStr("18"), "NaN",
@@ -6278,8 +6278,8 @@ TEST(APFloatTest, ConvertE4M3FNUZToE5M2FNUZ) {
EXPECT_TRUE(losesInfo);
EXPECT_EQ(status, APFloat::opInexact);
- // Convert E4M3 denormal to E5M2 normal. Should not be truncated, despite the
- // destination format having one fewer significand bit
+ // Convert E4M3FNUZ denormal to E5M2 normal. Should not be truncated, despite
+ // the destination format having one fewer significand bit
losesInfo = true;
test = APFloat(APFloat::Float8E4M3FNUZ(), "0x1.Cp-8");
status = test.convert(APFloat::Float8E5M2FNUZ(),
APFloat::rmNearestTiesToEven,
diff --git a/mlir/python/mlir/extras/types.py b/mlir/python/mlir/extras/types.py
index db9e8229fb288..b93c46b172a9a 100644
--- a/mlir/python/mlir/extras/types.py
+++ b/mlir/python/mlir/extras/types.py
@@ -68,7 +68,7 @@ def ui(width):
bf16 = lambda: BF16Type.get()
f8E5M2 = lambda: Float8E5M2Type.get()
-f8E4M3 = lambda: Float8E4M3FNType.get()
+f8E4M3FN = lambda: Float8E4M3FNType.get()
f8E4M3B11FNUZ = lambda: Float8E4M3B11FNUZType.get()
none = lambda: NoneType.get()
>From 7c3990ddce079dcd9f86852e499f0d706ca92989 Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH 2/2] Add f8E4M3 IEEE 754 type
---
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h | 6 +++
llvm/lib/Support/APFloat.cpp | 20 ++
llvm/unittests/ADT/APFloatTest.cpp| 38 +++
mlir/include/mlir-c/BuiltinTypes.h| 10 +
mlir/include/mlir/IR/Builders.h | 1 +
mlir/include/mlir/IR/BuiltinTypes.h | 13 +--
mlir/include/mlir/IR/BuiltinTypes.td | 19 ++
mlir/include/mlir/IR/CommonTypeConstraints.td | 2 +
mlir/include/mlir/IR/Types.h | 1 +
mlir/lib/AsmParser/TokenKinds.def | 1 +
mlir/lib/AsmParser/TypeParser.cpp | 4 ++
mlir/lib/Bindings/Python/IRTypes.cpp | 23 ++-
mlir/lib/CAPI/IR/BuiltinTypes.cpp | 12 ++
.../Conversion/LLVMCommon/TypeConverter.cpp | 5 ++-
.../Transforms/EmulateUnsupportedFloats.cpp | 1 +
mlir/lib/IR/AsmPrinter.cpp| 1 +
mlir/lib/IR/Bui
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type (PR #97118)
apivovarov wrote: Reed, Benjamin, Can you look at this PR too? @reedwm @d0k https://github.com/llvm/llvm-project/pull/97118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/97118
>From 8b0671585864e13d26596b9e8ada39364c542517 Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 19:33:21 +
Subject: [PATCH 1/2] Rename f8E4M3 to f8E4M3FN in mlir.extras.types py package
---
llvm/lib/Support/APFloat.cpp | 4 ++--
llvm/unittests/ADT/APFloatTest.cpp | 12 ++--
mlir/python/mlir/extras/types.py | 2 +-
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 47618bc325951..3017a9b976658 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -83,8 +83,8 @@ enum class fltNanEncoding {
// exponent is all 1s and the significand is non-zero.
IEEE,
- // Represents the behavior in the Float8E4M3 floating point type where NaN is
- // represented by having the exponent and mantissa set to all 1s.
+ // Represents the behavior in the Float8E4M3FN floating point type where NaN
+ // is represented by having the exponent and mantissa set to all 1s.
// This behavior matches the FP8 E4M3 type described in
// https://arxiv.org/abs/2209.05433. We treat both signed and unsigned NaNs
// as non-signalling, although the paper does not state whether the NaN
diff --git a/llvm/unittests/ADT/APFloatTest.cpp
b/llvm/unittests/ADT/APFloatTest.cpp
index cf6bbd313c6c6..86a25f4394e19 100644
--- a/llvm/unittests/ADT/APFloatTest.cpp
+++ b/llvm/unittests/ADT/APFloatTest.cpp
@@ -5508,8 +5508,8 @@ TEST(APFloatTest, ConvertE4M3FNToE5M2) {
EXPECT_TRUE(losesInfo);
EXPECT_EQ(status, APFloat::opInexact);
- // Convert E4M3 denormal to E5M2 normal. Should not be truncated, despite the
- // destination format having one fewer significand bit
+ // Convert E4M3FN denormal to E5M2 normal. Should not be truncated, despite
+ // the destination format having one fewer significand bit
test = APFloat(APFloat::Float8E4M3FN(), "0x1.Cp-7");
status = test.convert(APFloat::Float8E5M2(), APFloat::rmNearestTiesToEven,
&losesInfo);
@@ -5647,8 +5647,8 @@ TEST(APFloatTest, Float8E4M3FNAdd) {
int category;
APFloat::roundingMode roundingMode = APFloat::rmNearestTiesToEven;
} AdditionTests[] = {
- // Test addition operations involving NaN, overflow, and the max E4M3
- // value (448) because E4M3 differs from IEEE-754 types in these regards
+ // Test addition operations involving NaN, overflow, and the max E4M3FN
+ // value (448) because E4M3FN differs from IEEE-754 types in these
regards
{FromStr("448"), FromStr("16"), "448", APFloat::opInexact,
APFloat::fcNormal},
{FromStr("448"), FromStr("18"), "NaN",
@@ -6278,8 +6278,8 @@ TEST(APFloatTest, ConvertE4M3FNUZToE5M2FNUZ) {
EXPECT_TRUE(losesInfo);
EXPECT_EQ(status, APFloat::opInexact);
- // Convert E4M3 denormal to E5M2 normal. Should not be truncated, despite the
- // destination format having one fewer significand bit
+ // Convert E4M3FNUZ denormal to E5M2 normal. Should not be truncated, despite
+ // the destination format having one fewer significand bit
losesInfo = true;
test = APFloat(APFloat::Float8E4M3FNUZ(), "0x1.Cp-8");
status = test.convert(APFloat::Float8E5M2FNUZ(),
APFloat::rmNearestTiesToEven,
diff --git a/mlir/python/mlir/extras/types.py b/mlir/python/mlir/extras/types.py
index db9e8229fb288..b93c46b172a9a 100644
--- a/mlir/python/mlir/extras/types.py
+++ b/mlir/python/mlir/extras/types.py
@@ -68,7 +68,7 @@ def ui(width):
bf16 = lambda: BF16Type.get()
f8E5M2 = lambda: Float8E5M2Type.get()
-f8E4M3 = lambda: Float8E4M3FNType.get()
+f8E4M3FN = lambda: Float8E4M3FNType.get()
f8E4M3B11FNUZ = lambda: Float8E4M3B11FNUZType.get()
none = lambda: NoneType.get()
>From eead639faea28b1be195f725eb79e8293b7fb098 Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH 2/2] Add f8E4M3 IEEE 754 type
---
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h | 6 +++
llvm/lib/Support/APFloat.cpp | 20 ++
llvm/unittests/ADT/APFloatTest.cpp| 38 +++
mlir/include/mlir-c/BuiltinTypes.h| 10 +
mlir/include/mlir/IR/Builders.h | 1 +
mlir/include/mlir/IR/BuiltinTypes.h | 13 +--
mlir/include/mlir/IR/BuiltinTypes.td | 19 ++
mlir/include/mlir/IR/CommonTypeConstraints.td | 2 +
mlir/include/mlir/IR/Types.h | 1 +
mlir/lib/AsmParser/TokenKinds.def | 1 +
mlir/lib/AsmParser/TypeParser.cpp | 4 ++
mlir/lib/Bindings/Python/IRTypes.cpp | 23 ++-
mlir/lib/CAPI/IR/BuiltinTypes.cpp | 12 ++
.../Conversion/LLVMCommon/TypeConverter.cpp | 5 ++-
.../Transforms/EmulateUnsupportedFloats.cpp | 1 +
mlir/lib/IR/AsmPrinter.cpp| 1 +
mlir/lib/IR/Bui
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov edited https://github.com/llvm/llvm-project/pull/97118 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/97118
>From 0b76af07d0dc567cbbcceeca2bc3858837875498 Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 19:33:21 +
Subject: [PATCH 1/2] Rename f8E4M3 to f8E4M3FN in mlir.extras.types py package
---
llvm/lib/Support/APFloat.cpp | 4 ++--
llvm/unittests/ADT/APFloatTest.cpp | 12 ++--
mlir/python/mlir/extras/types.py | 2 +-
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 47618bc325951..3017a9b976658 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -83,8 +83,8 @@ enum class fltNanEncoding {
// exponent is all 1s and the significand is non-zero.
IEEE,
- // Represents the behavior in the Float8E4M3 floating point type where NaN is
- // represented by having the exponent and mantissa set to all 1s.
+ // Represents the behavior in the Float8E4M3FN floating point type where NaN
+ // is represented by having the exponent and mantissa set to all 1s.
// This behavior matches the FP8 E4M3 type described in
// https://arxiv.org/abs/2209.05433. We treat both signed and unsigned NaNs
// as non-signalling, although the paper does not state whether the NaN
diff --git a/llvm/unittests/ADT/APFloatTest.cpp
b/llvm/unittests/ADT/APFloatTest.cpp
index cf6bbd313c6c6..86a25f4394e19 100644
--- a/llvm/unittests/ADT/APFloatTest.cpp
+++ b/llvm/unittests/ADT/APFloatTest.cpp
@@ -5508,8 +5508,8 @@ TEST(APFloatTest, ConvertE4M3FNToE5M2) {
EXPECT_TRUE(losesInfo);
EXPECT_EQ(status, APFloat::opInexact);
- // Convert E4M3 denormal to E5M2 normal. Should not be truncated, despite the
- // destination format having one fewer significand bit
+ // Convert E4M3FN denormal to E5M2 normal. Should not be truncated, despite
+ // the destination format having one fewer significand bit
test = APFloat(APFloat::Float8E4M3FN(), "0x1.Cp-7");
status = test.convert(APFloat::Float8E5M2(), APFloat::rmNearestTiesToEven,
&losesInfo);
@@ -5647,8 +5647,8 @@ TEST(APFloatTest, Float8E4M3FNAdd) {
int category;
APFloat::roundingMode roundingMode = APFloat::rmNearestTiesToEven;
} AdditionTests[] = {
- // Test addition operations involving NaN, overflow, and the max E4M3
- // value (448) because E4M3 differs from IEEE-754 types in these regards
+ // Test addition operations involving NaN, overflow, and the max E4M3FN
+ // value (448) because E4M3FN differs from IEEE-754 types in these
regards
{FromStr("448"), FromStr("16"), "448", APFloat::opInexact,
APFloat::fcNormal},
{FromStr("448"), FromStr("18"), "NaN",
@@ -6278,8 +6278,8 @@ TEST(APFloatTest, ConvertE4M3FNUZToE5M2FNUZ) {
EXPECT_TRUE(losesInfo);
EXPECT_EQ(status, APFloat::opInexact);
- // Convert E4M3 denormal to E5M2 normal. Should not be truncated, despite the
- // destination format having one fewer significand bit
+ // Convert E4M3FNUZ denormal to E5M2 normal. Should not be truncated, despite
+ // the destination format having one fewer significand bit
losesInfo = true;
test = APFloat(APFloat::Float8E4M3FNUZ(), "0x1.Cp-8");
status = test.convert(APFloat::Float8E5M2FNUZ(),
APFloat::rmNearestTiesToEven,
diff --git a/mlir/python/mlir/extras/types.py b/mlir/python/mlir/extras/types.py
index db9e8229fb288..b93c46b172a9a 100644
--- a/mlir/python/mlir/extras/types.py
+++ b/mlir/python/mlir/extras/types.py
@@ -68,7 +68,7 @@ def ui(width):
bf16 = lambda: BF16Type.get()
f8E5M2 = lambda: Float8E5M2Type.get()
-f8E4M3 = lambda: Float8E4M3FNType.get()
+f8E4M3FN = lambda: Float8E4M3FNType.get()
f8E4M3B11FNUZ = lambda: Float8E4M3B11FNUZType.get()
none = lambda: NoneType.get()
>From 07550c04bbbd6213063445c6c0a5d5d88127b39d Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH 2/2] Add f8E4M3 IEEE 754 type
---
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h | 6 +++
llvm/lib/Support/APFloat.cpp | 20 ++
llvm/unittests/ADT/APFloatTest.cpp| 38 +++
mlir/include/mlir-c/BuiltinTypes.h| 10 +
mlir/include/mlir/IR/Builders.h | 1 +
mlir/include/mlir/IR/BuiltinTypes.h | 13 +--
mlir/include/mlir/IR/BuiltinTypes.td | 19 ++
mlir/include/mlir/IR/CommonTypeConstraints.td | 2 +
mlir/include/mlir/IR/Types.h | 1 +
mlir/lib/AsmParser/TokenKinds.def | 1 +
mlir/lib/AsmParser/TypeParser.cpp | 4 ++
mlir/lib/Bindings/Python/IRTypes.cpp | 23 ++-
mlir/lib/CAPI/IR/BuiltinTypes.cpp | 12 ++
.../Conversion/LLVMCommon/TypeConverter.cpp | 5 ++-
.../Transforms/EmulateUnsupportedFloats.cpp | 1 +
mlir/lib/IR/AsmPrinter.cpp| 1 +
mlir/lib/IR/Bui
[clang] [llvm] [mlir] Add f8E4M3 IEEE 754 type (PR #97118)
https://github.com/apivovarov updated
https://github.com/llvm/llvm-project/pull/97118
>From e5fb4d85889472fd9880e5262d3a9cf00e1b1f89 Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 19:33:21 +
Subject: [PATCH 1/2] Rename f8E4M3 to f8E4M3FN in mlir.extras.types py package
---
llvm/lib/Support/APFloat.cpp | 4 ++--
llvm/unittests/ADT/APFloatTest.cpp | 12 ++--
mlir/python/mlir/extras/types.py | 2 +-
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index 47618bc325951..3017a9b976658 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -83,8 +83,8 @@ enum class fltNanEncoding {
// exponent is all 1s and the significand is non-zero.
IEEE,
- // Represents the behavior in the Float8E4M3 floating point type where NaN is
- // represented by having the exponent and mantissa set to all 1s.
+ // Represents the behavior in the Float8E4M3FN floating point type where NaN
+ // is represented by having the exponent and mantissa set to all 1s.
// This behavior matches the FP8 E4M3 type described in
// https://arxiv.org/abs/2209.05433. We treat both signed and unsigned NaNs
// as non-signalling, although the paper does not state whether the NaN
diff --git a/llvm/unittests/ADT/APFloatTest.cpp
b/llvm/unittests/ADT/APFloatTest.cpp
index cf6bbd313c6c6..86a25f4394e19 100644
--- a/llvm/unittests/ADT/APFloatTest.cpp
+++ b/llvm/unittests/ADT/APFloatTest.cpp
@@ -5508,8 +5508,8 @@ TEST(APFloatTest, ConvertE4M3FNToE5M2) {
EXPECT_TRUE(losesInfo);
EXPECT_EQ(status, APFloat::opInexact);
- // Convert E4M3 denormal to E5M2 normal. Should not be truncated, despite the
- // destination format having one fewer significand bit
+ // Convert E4M3FN denormal to E5M2 normal. Should not be truncated, despite
+ // the destination format having one fewer significand bit
test = APFloat(APFloat::Float8E4M3FN(), "0x1.Cp-7");
status = test.convert(APFloat::Float8E5M2(), APFloat::rmNearestTiesToEven,
&losesInfo);
@@ -5647,8 +5647,8 @@ TEST(APFloatTest, Float8E4M3FNAdd) {
int category;
APFloat::roundingMode roundingMode = APFloat::rmNearestTiesToEven;
} AdditionTests[] = {
- // Test addition operations involving NaN, overflow, and the max E4M3
- // value (448) because E4M3 differs from IEEE-754 types in these regards
+ // Test addition operations involving NaN, overflow, and the max E4M3FN
+ // value (448) because E4M3FN differs from IEEE-754 types in these
regards
{FromStr("448"), FromStr("16"), "448", APFloat::opInexact,
APFloat::fcNormal},
{FromStr("448"), FromStr("18"), "NaN",
@@ -6278,8 +6278,8 @@ TEST(APFloatTest, ConvertE4M3FNUZToE5M2FNUZ) {
EXPECT_TRUE(losesInfo);
EXPECT_EQ(status, APFloat::opInexact);
- // Convert E4M3 denormal to E5M2 normal. Should not be truncated, despite the
- // destination format having one fewer significand bit
+ // Convert E4M3FNUZ denormal to E5M2 normal. Should not be truncated, despite
+ // the destination format having one fewer significand bit
losesInfo = true;
test = APFloat(APFloat::Float8E4M3FNUZ(), "0x1.Cp-8");
status = test.convert(APFloat::Float8E5M2FNUZ(),
APFloat::rmNearestTiesToEven,
diff --git a/mlir/python/mlir/extras/types.py b/mlir/python/mlir/extras/types.py
index db9e8229fb288..b93c46b172a9a 100644
--- a/mlir/python/mlir/extras/types.py
+++ b/mlir/python/mlir/extras/types.py
@@ -68,7 +68,7 @@ def ui(width):
bf16 = lambda: BF16Type.get()
f8E5M2 = lambda: Float8E5M2Type.get()
-f8E4M3 = lambda: Float8E4M3FNType.get()
+f8E4M3FN = lambda: Float8E4M3FNType.get()
f8E4M3B11FNUZ = lambda: Float8E4M3B11FNUZType.get()
none = lambda: NoneType.get()
>From 79567a1d3bd3e68946e4a80edbb6690e499e07b7 Mon Sep 17 00:00:00 2001
From: Alexander Pivovarov
Date: Fri, 28 Jun 2024 21:09:33 +
Subject: [PATCH 2/2] Add f8E4M3 IEEE 754 type
---
clang/include/clang/AST/Stmt.h| 6 +--
clang/lib/AST/MicrosoftMangle.cpp | 1 +
llvm/include/llvm/ADT/APFloat.h | 6 +++
llvm/lib/Support/APFloat.cpp | 20 ++
llvm/unittests/ADT/APFloatTest.cpp| 38 +++
mlir/include/mlir-c/BuiltinTypes.h| 10 +
mlir/include/mlir/IR/Builders.h | 1 +
mlir/include/mlir/IR/BuiltinTypes.h | 13 +--
mlir/include/mlir/IR/BuiltinTypes.td | 19 ++
mlir/include/mlir/IR/CommonTypeConstraints.td | 2 +
mlir/include/mlir/IR/Types.h | 1 +
mlir/lib/AsmParser/TokenKinds.def | 1 +
mlir/lib/AsmParser/TypeParser.cpp | 4 ++
mlir/lib/Bindings/Python/IRTypes.cpp | 23 ++-
mlir/lib/CAPI/IR/BuiltinTypes.cpp | 12 ++
.../Conversion/LLVMCommon/TypeConverter.cpp | 5 ++-
.../Transforms/EmulateUnsupportedFloats.cpp | 1 +
mlir/lib/IR/A
