[PATCH] D121368: [pseudo][WIP] Build Ambiguous forest node in the GLR Parser.

2022-03-14 Thread Alex Tsao via Phabricator via cfe-commits
alextsao1999 added inline comments.



Comment at: clang/lib/Tooling/Syntax/Pseudo/GLRParser.cpp:318
 Bases.push_back(
-{Base, ParsingTable.getGoToState(Base->State, ReduceRule.Target)});
+{Base, ParsingTable.getGoToState(Base->State, ReduceSymbolID)});
   llvm::sort(Bases, [](const BaseInfo &L, const BaseInfo &R) {

Maybe we can make goto more clear? like `performGoto` after every GLR reduction.


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[PATCH] D121779: [RISCV] Add zihintntl instructions

2022-03-16 Thread Alex Tsao via Phabricator via cfe-commits
alextsao1999 created this revision.
alextsao1999 added a reviewer: s.
Herald added subscribers: VincentWu, luke957, vkmr, frasercrmck, jdoerfert, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
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zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
hiraditya, arichardson.
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alextsao1999 requested review of this revision.
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MaskRay.
Herald added projects: clang, LLVM.

Add zihintntl compressed instructions and some files related to zihintntl


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121779

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoC.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zihintntl-invalid.s
  llvm/test/MC/RISCV/rv32zihintntl-valid.s
  llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
  llvm/test/MC/RISCV/rv32zihintntlc-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntlc-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntlc-valid.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: ntl.p1
+# CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
+ntl.p1
+
+# CHECK-ASM-AND-OBJ: ntl.pall
+# CHECK-ASM: encoding: [0x33,0x00,0x30,0x00]
+ntl.pall
+
+# CHECK-ASM-AND-OBJ: ntl.s1
+# CHECK-ASM: encoding: [0x33,0x00,0x40,0x00]
+ntl.s1
+
+# CHECK-ASM-AND-OBJ: ntl.all
+# CHECK-ASM: encoding: [0x33,0x00,0x50,0x00]
+ntl.all
+
+# CHECK-ASM-AND-OBJ: c.ntl.p1
+# CHECK-ASM: encoding: [0x0a,0x90]
+c.ntl.p1
+
+# CHECK-ASM-AND-OBJ: c.ntl.pall
+# CHECK-ASM: encoding: [0x0e,0x90]
+c.ntl.pall
+
+# CHECK-ASM-AND-OBJ: c.ntl.s1
+# CHECK-ASM: encoding: [0x12,0x90]
+c.ntl.s1
+
+# CHECK-ASM-AND-OBJ: c.ntl.all
+# CHECK-ASM: encoding: [0x16,0x90]
+c.ntl.all
Index: llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+
+c.ntl.p1 1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.pall 2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+c.ntl.s1 3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.all 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+
+c.ntl.p1 t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.pall t0, t1 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+c.ntl.s1 t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.all t0, t1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+
Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: add zero, zero, sp
+# CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
+ntl.p1
+
+# CHECK-ASM-AND-

[PATCH] D121779: [RISCV] Add zihintntl compressed instructions

2022-03-16 Thread Alex Tsao via Phabricator via cfe-commits
alextsao1999 updated this revision to Diff 415737.
alextsao1999 added a comment.

Update


Repository:
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Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoC.td
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zihintntl-invalid.s
  llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
  llvm/test/MC/RISCV/rv32zihintntlc-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntlc-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntlc-valid.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: ntl.p1
+# CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
+ntl.p1
+
+# CHECK-ASM-AND-OBJ: ntl.pall
+# CHECK-ASM: encoding: [0x33,0x00,0x30,0x00]
+ntl.pall
+
+# CHECK-ASM-AND-OBJ: ntl.s1
+# CHECK-ASM: encoding: [0x33,0x00,0x40,0x00]
+ntl.s1
+
+# CHECK-ASM-AND-OBJ: ntl.all
+# CHECK-ASM: encoding: [0x33,0x00,0x50,0x00]
+ntl.all
+
+# CHECK-ASM-AND-OBJ: c.ntl.p1
+# CHECK-ASM: encoding: [0x0a,0x90]
+c.ntl.p1
+
+# CHECK-ASM-AND-OBJ: c.ntl.pall
+# CHECK-ASM: encoding: [0x0e,0x90]
+c.ntl.pall
+
+# CHECK-ASM-AND-OBJ: c.ntl.s1
+# CHECK-ASM: encoding: [0x12,0x90]
+c.ntl.s1
+
+# CHECK-ASM-AND-OBJ: c.ntl.all
+# CHECK-ASM: encoding: [0x16,0x90]
+c.ntl.all
Index: llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+
+c.ntl.p1 1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.pall 2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+c.ntl.s1 3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.all 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+
+c.ntl.p1 t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.pall t0, t1 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+c.ntl.s1 t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+c.ntl.all t0, t1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+
Index: llvm/test/MC/RISCV/rv32zihintntl-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zihintntl-invalid.s
@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl < %s 2>&1 | FileCheck %s
+
+ntl.p1 1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ntl.pall 2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+ntl.s1 3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ntl.all 4 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
+ntl.p1 t0, t1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ntl.pall t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+ntl.s1 t0, t1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
+ntl.all t0, t1 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -175,3 +175,9 @@
 
 .attribute arch, "rv32i_zk1p0"
 # CHECK: attribute  5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
+
+.attribute arch, "rv32izihintntl0p2"
+# CHECK: attribute  5, "rv32i2p0_zihintntl0p2"
+
+.attribute arch, "rv32iczihintntl0p2"
+# CHECK: attribute  5, "rv32i2p0_c2p0_zihintntl0p2"
Index: llvm/lib/Target/RISCV/RISCVInstrInfoC.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -695,6 +695,13 @@
 // Assembler Pseudo Instructions
 //===--===//
 
+let Predicates = [HasStdE

[PATCH] D116722: [clang] Verify ssp buffer size is a valid integer

2022-01-28 Thread Alex Tsao via Phabricator via cfe-commits
alextsao1999 marked 2 inline comments as done.
alextsao1999 added inline comments.



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:3209
+} else
+  D.Diag(clang::diag::err_invalid_ssp_buffer_size);
   }

compnerd wrote:
> Please consistently use the braces (either applied to both or on neither).
Thanks, fixed. Are there any other issues?


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[PATCH] D119172: [pseudo] Implement LRGraph

2022-03-05 Thread Alex Tsao via Phabricator via cfe-commits
alextsao1999 added inline comments.
Herald added a project: All.



Comment at: clang/include/clang/Tooling/Syntax/Pseudo/LRGraph.h:96
+  uint8_t DotPos = 0;
+  uint8_t RuleLength = 0; // the length of rule body.
+};

Can we add LookaheadSymbol here to implement LR(1)?


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[PATCH] D119172: [pseudo] Implement LRGraph

2022-03-07 Thread Alex Tsao via Phabricator via cfe-commits
alextsao1999 added inline comments.



Comment at: clang/include/clang/Tooling/Syntax/Pseudo/LRGraph.h:96
+  uint8_t DotPos = 0;
+  uint8_t RuleLength = 0; // the length of rule body.
+};

hokein wrote:
> alextsao1999 wrote:
> > Can we add LookaheadSymbol here to implement LR(1)?
> we could do that. However, we don't have a plan to implement an `LR(1)` yet, 
> we use `SLR(1)`. (though LR(1) is more powerful than SLR(1), the typical 
> deterministic LR(1) parser cannot handle the C++ grammar, we need a "general" 
> parser GLR which can be able to handle arbitrary context-free grammars).
Thanks for your answering! Oh, I know some `GLR` parsers are based on `LR(1)` 
or `LALR`, so I think our `GLR` parser is based on `LR(1)` as well. I'm trying 
to keep up with your train of thought :)


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[PATCH] D119172: [pseudo] Implement LRGraph

2022-03-07 Thread Alex Tsao via Phabricator via cfe-commits
alextsao1999 added inline comments.



Comment at: clang/include/clang/Tooling/Syntax/Pseudo/LRGraph.h:96
+  uint8_t DotPos = 0;
+  uint8_t RuleLength = 0; // the length of rule body.
+};

sammccall wrote:
> alextsao1999 wrote:
> > hokein wrote:
> > > alextsao1999 wrote:
> > > > Can we add LookaheadSymbol here to implement LR(1)?
> > > we could do that. However, we don't have a plan to implement an `LR(1)` 
> > > yet, we use `SLR(1)`. (though LR(1) is more powerful than SLR(1), the 
> > > typical deterministic LR(1) parser cannot handle the C++ grammar, we need 
> > > a "general" parser GLR which can be able to handle arbitrary context-free 
> > > grammars).
> > Thanks for your answering! Oh, I know some `GLR` parsers are based on 
> > `LR(1)` or `LALR`, so I think our `GLR` parser is based on `LR(1)` as well. 
> > I'm trying to keep up with your train of thought :)
> Yeah, GLR changes the tradeoff between more sophisticated and simpler parsers 
> (LR(1) > LALR > SLR(1) > LR(0)).
> 
> Normally the sophisticated parsers are able to handle grammars/languages that 
> the simple ones can't, by avoiding action conflicts. So the value is very 
> high.
> 
> However with GLR we can handle action conflicts by branching, so the value is 
> "only" avoiding the performance hit of chasing branches that don't go 
> anywhere.
> 
> So it didn't really seem worth the extra implementation complexity (or extra 
> size of the in-memory grammar tables!) to use a more powerful parser than 
> SLR(1). Maybe we should even have given LR(0) more thought :-)
Yes, agree. `SLR` can reduce memory usage, but it can't handle operator 
precedence. With the help of GLR, we can resolve the problem of operator 
precedence by chosing one branch. Thanks, I got it!


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