[PATCH] D145214: [TSAN] add support for riscv64

[Alex Fan via Phabricator via cfe-commits]

alexfanqi updated this revision to Diff 557362.
alexfanqi added a comment.

thanks @hiraditya


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145214/new/

https://reviews.llvm.org/D145214

Files:
  clang/lib/Driver/ToolChains/Linux.cpp
  compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
  compiler-rt/lib/tsan/rtl/CMakeLists.txt
  compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
  compiler-rt/lib/tsan/rtl/tsan_platform.h
  compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
  compiler-rt/lib/tsan/rtl/tsan_rtl.h
  compiler-rt/lib/tsan/rtl/tsan_rtl_riscv64.S
  compiler-rt/test/tsan/map32bit.cpp
  compiler-rt/test/tsan/mmap_large.cpp
  compiler-rt/test/tsan/test.h

Index: compiler-rt/test/tsan/test.h
===
--- compiler-rt/test/tsan/test.h
+++ compiler-rt/test/tsan/test.h
@@ -76,6 +76,8 @@
 const int kPCInc = 1;
 #elif defined(__sparc__) || defined(__mips__)
 const int kPCInc = 8;
+#elif defined(__riscv) && __riscv_xlen == 64
+const int kPCInc = 2;
 #else
 const int kPCInc = 4;
 #endif
Index: compiler-rt/test/tsan/mmap_large.cpp
===
--- compiler-rt/test/tsan/mmap_large.cpp
+++ compiler-rt/test/tsan/mmap_large.cpp
@@ -17,7 +17,8 @@
 int main() {
 #ifdef __x86_64__
   const size_t kLog2Size = 39;
-#elif defined(__mips64) || defined(__aarch64__) || defined(__loongarch_lp64)
+#elif defined(__mips64) || defined(__aarch64__) || \
+defined(__loongarch_lp64) || (defined(__riscv) && __riscv_xlen == 64)
   const size_t kLog2Size = 32;
 #elif defined(__powerpc64__)
   const size_t kLog2Size = 39;
Index: compiler-rt/test/tsan/map32bit.cpp
===
--- compiler-rt/test/tsan/map32bit.cpp
+++ compiler-rt/test/tsan/map32bit.cpp
@@ -13,6 +13,7 @@
 // XFAIL: target=powerpc64{{.*}}
 // XFAIL: target=s390x{{.*}}
 // XFAIL: target=loongarch64{{.*}}
+// XFAIL: target=riscv64{{.*}}
 
 // MAP_32BIT doesn't exist on OS X and NetBSD.
 // UNSUPPORTED: darwin,target={{.*netbsd.*}}
Index: compiler-rt/lib/tsan/rtl/tsan_rtl_riscv64.S
===
--- /dev/null
+++ compiler-rt/lib/tsan/rtl/tsan_rtl_riscv64.S
@@ -0,0 +1,203 @@
+#include "sanitizer_common/sanitizer_asm.h"
+
+.section .text
+
+.comm _ZN14__interception11real_setjmpE,8,8
+.globl ASM_SYMBOL_INTERCEPTOR(setjmp)
+ASM_TYPE_FUNCTION(ASM_SYMBOL_INTERCEPTOR(setjmp))
+ASM_SYMBOL_INTERCEPTOR(setjmp):
+  CFI_STARTPROC
+
+  // Save frame pointer and return address register
+  addi sp, sp, -32
+  sd ra, 24(sp)
+  sd s0, 16(sp)
+  CFI_DEF_CFA_OFFSET (32)
+  CFI_OFFSET (1, -8)
+  CFI_OFFSET (8, -16)
+
+  // Adjust the SP for previous frame
+  addi s0, sp, 32
+  CFI_DEF_CFA_REGISTER (8)
+
+  // Save env parameter
+  sd a0, 8(sp)
+  CFI_OFFSET (10, -24)
+
+  // Obtain SP, first argument to `void __tsan_setjmp(uptr sp)`
+  addi  a0, s0, 0
+
+  // call tsan interceptor
+  call ASM_SYMBOL(__tsan_setjmp)
+
+  // Restore env parameter
+  ld a0, 8(sp)
+  CFI_RESTORE (10)
+
+  // Restore frame/link register
+  ld s0, 16(sp)
+  ld ra, 24(sp)
+  addi sp, sp, 32
+  CFI_RESTORE (8)
+  CFI_RESTORE (1)
+  CFI_DEF_CFA (2, 0)
+
+  // tail jump to libc setjmp
+  la t1, _ZN14__interception11real_setjmpE
+  ld t1, 0(t1)
+  jr t1
+
+  CFI_ENDPROC
+ASM_SIZE(ASM_SYMBOL_INTERCEPTOR(setjmp))
+
+.comm _ZN14__interception12real__setjmpE,8,8
+.globl ASM_SYMBOL_INTERCEPTOR(_setjmp)
+ASM_TYPE_FUNCTION(ASM_SYMBOL_INTERCEPTOR(_setjmp))
+ASM_SYMBOL_INTERCEPTOR(_setjmp):
+  CFI_STARTPROC
+
+  // Save frame pointer and return address register
+  addi sp, sp, -32
+  sd ra, 24(sp)
+  sd s0, 16(sp)
+  CFI_DEF_CFA_OFFSET (32)
+  CFI_OFFSET (1, -8)
+  CFI_OFFSET (8, -16)
+
+  // Adjust the SP for previous frame
+  addi s0, sp, 32
+  CFI_DEF_CFA_REGISTER (8)
+
+  // Save env parameter
+  sd a0, 8(sp)
+  CFI_OFFSET (10, -24)
+
+  // Obtain SP, first argument to `void __tsan_setjmp(uptr sp)`
+  addi  a0, s0, 0
+
+  // call tsan interceptor
+  call ASM_SYMBOL(__tsan_setjmp)
+
+  // Restore env parameter
+  ld a0, 8(sp)
+  CFI_RESTORE (10)
+
+  // Restore frame/link register
+  ld s0, 16(sp)
+  ld ra, 24(sp)
+  addi sp, sp, 32
+  CFI_RESTORE (8)
+  CFI_RESTORE (1)
+  CFI_DEF_CFA (2, 0)
+
+  // tail jump to libc setjmp
+  la t1, _ZN14__interception12real__setjmpE
+  ld t1, 0(t1)
+  jr t1
+
+  CFI_ENDPROC
+ASM_SIZE(ASM_SYMBOL_INTERCEPTOR(_setjmp))
+
+.comm _ZN14__interception14real_sigsetjmpE,8,8
+.globl ASM_SYMBOL_INTERCEPTOR(sigsetjmp)
+ASM_TYPE_FUNCTION(ASM_SYMBOL_INTERCEPTOR(sigsetjmp))
+ASM_SYMBOL_INTERCEPTOR(sigsetjmp):
+  CFI_STARTPROC
+
+  // Save frame pointer and return address register
+  addi sp, sp, -32
+  sd ra, 24(sp)
+  sd s0, 16(sp)
+  CFI_DEF_CFA_OFFSET (32)
+  CFI_OFFSET (1, -8)
+  CFI_OFFSET (8, -16)
+
+  // Adjust the SP for previous frame
+  addi s0, sp, 32
+  CFI_DEF_CFA_REGISTER (8)
+
+  // Save env

[PATCH] D145214: [TSAN] add support for riscv64

[Alex Fan via Phabricator via cfe-commits]

alexfanqi added a comment.

In D145214#4650189 , @hiraditya wrote:

> I tested it on a licheepi board (riscv64 debian) and all the tests modified 
> in this patch have passed. LGTM.

Can you help me land this patch?

> There are other tsan failures but i think it is okay if they can be fixed in 
> subsequent patches.

Do you have a list of these failures? I will try to reproduce on my machine and 
fix in later patch.


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[PATCH] D145214: [TSAN] add support for riscv64

[Alex Fan via Phabricator via cfe-commits]

alexfanqi added a comment.

>> While testing compiler-rt/test/tsan/RISCV64Config only 
>> compiler-rt/test/tsan/mmap_lots.cpp failed. I couldn't run all the 
>> compiler-rt tests on Licheepi because it is very slow

I had this only test failure before. When the upper memory space is fully 
mapped out, the kernel will try to use the lower memory range starting from 
0x00, but kLoAppMem leaves out the initial 0x00-0x1000. I saw other archs did 
the same, and maybe it won't hurt.


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[PATCH] D145214: [TSAN] add support for riscv64

[Alex Fan via Phabricator via cfe-commits]

alexfanqi added a comment.

In D145214#4646676 , @hiraditya wrote:

> @alexfanqi are you still actively working on this? maybe we can move it to 
> github then.

Yeah, but the patch is already complete and tsan functions well with tests 
passing on my local qemu system emulation. I am waiting for reviewers to have 
more feedback or accept this patch.


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[PATCH] D145214: [TSAN] add support for riscv64

[Alex Fan via Phabricator via cfe-commits]

alexfanqi created this revision.
Herald added subscribers: luke, Enna1, VincentWu, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
fedor.sergeev, arichardson.
Herald added a project: All.
alexfanqi updated this revision to Diff 502351.
alexfanqi added a comment.
alexfanqi retitled this revision from "[TSAN] add RISCV support" to "[TSAN] add 
support for riscv64".
alexfanqi edited the summary of this revision.
alexfanqi added reviewers: MaskRay, dvyukov, asb, StephenFan.
alexfanqi published this revision for review.
Herald added subscribers: Sanitizers, cfe-commits, pcwang-thead, eopXD.
Herald added projects: clang, Sanitizers.

fix tsan_rtl_riscv64.S and test failures

remaining test failure:
ThreadSanitizer-riscv64 :: custom_mutex5.cpp   
The debuginfo line reported is slightly off. 
custom_mutex5.cpp:14 -> 15
custom_mutex5.cpp:22 -> 23

ThreadSanitizer-riscv64 :: mmap_lots.cpp
flaky, the last 1000 sized mmap can get allocated to 0x-0x1000


Implements for sv39 and sv48 VMA layout.

Userspace only has access to the bottom half of vma range. The top half is used 
by kernel.
There is no dedicated vsyscall or heap segment.
PIE program is allocated to start at TASK_SIZE/3*2. Maximum ASLR is 
ARCH_MMAP_RND_BITS_MAX+PAGE_SHIFT=24+12=36
Loader, vdso and other libraries are allocated below stack from the top.

Both riscv32 and riscv64 need libatomic for 1,2 bytes atomic ops.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145214

Files:
  clang/lib/Driver/ToolChains/Linux.cpp
  compiler-rt/CMakeLists.txt
  compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
  compiler-rt/lib/tsan/rtl/CMakeLists.txt
  compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
  compiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
  compiler-rt/lib/tsan/rtl/tsan_platform.h
  compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
  compiler-rt/lib/tsan/rtl/tsan_rtl.h
  compiler-rt/lib/tsan/rtl/tsan_rtl_riscv64.S
  compiler-rt/lib/tsan/tests/CMakeLists.txt
  compiler-rt/test/tsan/map32bit.cpp
  compiler-rt/test/tsan/mmap_large.cpp
  compiler-rt/test/tsan/test.h

Index: compiler-rt/test/tsan/test.h
===
--- compiler-rt/test/tsan/test.h
+++ compiler-rt/test/tsan/test.h
@@ -73,6 +73,8 @@
 const int kPCInc = 1;
 #elif defined(__sparc__) || defined(__mips__)
 const int kPCInc = 8;
+#elif defined(__riscv) && __riscv_xlen == 64
+const int kPCInc = 2;
 #else
 const int kPCInc = 4;
 #endif
Index: compiler-rt/test/tsan/mmap_large.cpp
===
--- compiler-rt/test/tsan/mmap_large.cpp
+++ compiler-rt/test/tsan/mmap_large.cpp
@@ -17,7 +17,8 @@
 int main() {
 #ifdef __x86_64__
   const size_t kLog2Size = 39;
-#elif defined(__mips64) || defined(__aarch64__) || defined(__loongarch_lp64)
+#elif defined(__mips64) || defined(__aarch64__) || \
+defined(__loongarch_lp64) || (defined(__riscv) && __riscv_xlen == 64)
   const size_t kLog2Size = 32;
 #elif defined(__powerpc64__)
   const size_t kLog2Size = 39;
Index: compiler-rt/test/tsan/map32bit.cpp
===
--- compiler-rt/test/tsan/map32bit.cpp
+++ compiler-rt/test/tsan/map32bit.cpp
@@ -13,6 +13,7 @@
 // XFAIL: target=powerpc64{{.*}}
 // XFAIL: target=s390x{{.*}}
 // XFAIL: target=loongarch64{{.*}}
+// XFAIL: target=riscv64{{.*}}
 
 // MAP_32BIT doesn't exist on OS X and NetBSD.
 // UNSUPPORTED: darwin,target={{.*netbsd.*}}
Index: compiler-rt/lib/tsan/tests/CMakeLists.txt
===
--- compiler-rt/lib/tsan/tests/CMakeLists.txt
+++ compiler-rt/lib/tsan/tests/CMakeLists.txt
@@ -55,6 +55,9 @@
 else()
   list(APPEND TSAN_UNITTEST_LINK_FLAGS -fsanitize=thread)
   list(APPEND TSAN_UNITTEST_LINK_FLAGS -lm)
+  if("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "riscv")
+list(APPEND TSAN_UNITTEST_LINK_FLAGS -latomic)
+  endif()
   list(APPEND TSAN_UNITTEST_LINK_FLAGS ${COMPILER_RT_TEST_LIBDISPATCH_CFLAGS})
 endif()
 
Index: compiler-rt/lib/tsan/rtl/tsan_rtl_riscv64.S
===
--- /dev/null
+++ compiler-rt/lib/tsan/rtl/tsan_rtl_riscv64.S
@@ -0,0 +1,203 @@
+#include "sanitizer_common/sanitizer_asm.h"
+
+.section .text
+
+.comm _ZN14__interception11real_setjmpE,8,8
+.globl ASM_SYMBOL_INTERCEPTOR(setjmp)
+ASM_TYPE_FUNCTION(ASM_SYMBOL_INTERCEPTOR(setjmp))
+ASM_SYMBOL_INTERCEPTOR(setjmp):
+  CFI_STARTPROC
+
+  // Save frame pointer and return address register
+  addi sp, sp, -32
+  sd ra, 24(sp)
+  sd s0, 16(sp)
+  CFI_DEF_CFA_OFFSET (32)
+  CFI_OFFSET (1, -8)
+  CFI_OFFSET (8, -16)
+
+  // Adjust the SP for previous frame
+  addi s0, sp, 32
+  CFI_DEF_CFA_REGISTER (8)

[PATCH] D145214: [TSAN] add support for riscv64

[Alex Fan via Phabricator via cfe-commits]

alexfanqi updated this revision to Diff 502397.
alexfanqi added a comment.

remove libatomic link


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145214/new/

https://reviews.llvm.org/D145214

Files:
  clang/lib/Driver/ToolChains/Linux.cpp
  compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake
  compiler-rt/lib/tsan/rtl/CMakeLists.txt
  compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
  compiler-rt/lib/tsan/rtl/tsan_platform.h
  compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
  compiler-rt/lib/tsan/rtl/tsan_rtl.h
  compiler-rt/lib/tsan/rtl/tsan_rtl_riscv64.S
  compiler-rt/test/tsan/map32bit.cpp
  compiler-rt/test/tsan/mmap_large.cpp
  compiler-rt/test/tsan/test.h

Index: compiler-rt/test/tsan/test.h
===
--- compiler-rt/test/tsan/test.h
+++ compiler-rt/test/tsan/test.h
@@ -73,6 +73,8 @@
 const int kPCInc = 1;
 #elif defined(__sparc__) || defined(__mips__)
 const int kPCInc = 8;
+#elif defined(__riscv) && __riscv_xlen == 64
+const int kPCInc = 2;
 #else
 const int kPCInc = 4;
 #endif
Index: compiler-rt/test/tsan/mmap_large.cpp
===
--- compiler-rt/test/tsan/mmap_large.cpp
+++ compiler-rt/test/tsan/mmap_large.cpp
@@ -17,7 +17,8 @@
 int main() {
 #ifdef __x86_64__
   const size_t kLog2Size = 39;
-#elif defined(__mips64) || defined(__aarch64__) || defined(__loongarch_lp64)
+#elif defined(__mips64) || defined(__aarch64__) || \
+defined(__loongarch_lp64) || (defined(__riscv) && __riscv_xlen == 64)
   const size_t kLog2Size = 32;
 #elif defined(__powerpc64__)
   const size_t kLog2Size = 39;
Index: compiler-rt/test/tsan/map32bit.cpp
===
--- compiler-rt/test/tsan/map32bit.cpp
+++ compiler-rt/test/tsan/map32bit.cpp
@@ -13,6 +13,7 @@
 // XFAIL: target=powerpc64{{.*}}
 // XFAIL: target=s390x{{.*}}
 // XFAIL: target=loongarch64{{.*}}
+// XFAIL: target=riscv64{{.*}}
 
 // MAP_32BIT doesn't exist on OS X and NetBSD.
 // UNSUPPORTED: darwin,target={{.*netbsd.*}}
Index: compiler-rt/lib/tsan/rtl/tsan_rtl_riscv64.S
===
--- /dev/null
+++ compiler-rt/lib/tsan/rtl/tsan_rtl_riscv64.S
@@ -0,0 +1,203 @@
+#include "sanitizer_common/sanitizer_asm.h"
+
+.section .text
+
+.comm _ZN14__interception11real_setjmpE,8,8
+.globl ASM_SYMBOL_INTERCEPTOR(setjmp)
+ASM_TYPE_FUNCTION(ASM_SYMBOL_INTERCEPTOR(setjmp))
+ASM_SYMBOL_INTERCEPTOR(setjmp):
+  CFI_STARTPROC
+
+  // Save frame pointer and return address register
+  addi sp, sp, -32
+  sd ra, 24(sp)
+  sd s0, 16(sp)
+  CFI_DEF_CFA_OFFSET (32)
+  CFI_OFFSET (1, -8)
+  CFI_OFFSET (8, -16)
+
+  // Adjust the SP for previous frame
+  addi s0, sp, 32
+  CFI_DEF_CFA_REGISTER (8)
+
+  // Save env parameter
+  sd a0, 8(sp)
+  CFI_OFFSET (10, -24)
+
+  // Obtain SP, first argument to `void __tsan_setjmp(uptr sp)`
+  addi  a0, s0, 0
+
+  // call tsan interceptor
+  call ASM_SYMBOL(__tsan_setjmp)
+
+  // Restore env parameter
+  ld a0, 8(sp)
+  CFI_RESTORE (10)
+
+  // Restore frame/link register
+  ld s0, 16(sp)
+  ld ra, 24(sp)
+  addi sp, sp, 32
+  CFI_RESTORE (8)
+  CFI_RESTORE (1)
+  CFI_DEF_CFA (2, 0)
+
+  // tail jump to libc setjmp
+  la t1, _ZN14__interception11real_setjmpE
+  ld t1, 0(t1)
+  jr t1
+
+  CFI_ENDPROC
+ASM_SIZE(ASM_SYMBOL_INTERCEPTOR(setjmp))
+
+.comm _ZN14__interception12real__setjmpE,8,8
+.globl ASM_SYMBOL_INTERCEPTOR(_setjmp)
+ASM_TYPE_FUNCTION(ASM_SYMBOL_INTERCEPTOR(_setjmp))
+ASM_SYMBOL_INTERCEPTOR(_setjmp):
+  CFI_STARTPROC
+
+  // Save frame pointer and return address register
+  addi sp, sp, -32
+  sd ra, 24(sp)
+  sd s0, 16(sp)
+  CFI_DEF_CFA_OFFSET (32)
+  CFI_OFFSET (1, -8)
+  CFI_OFFSET (8, -16)
+
+  // Adjust the SP for previous frame
+  addi s0, sp, 32
+  CFI_DEF_CFA_REGISTER (8)
+
+  // Save env parameter
+  sd a0, 8(sp)
+  CFI_OFFSET (10, -24)
+
+  // Obtain SP, first argument to `void __tsan_setjmp(uptr sp)`
+  addi  a0, s0, 0
+
+  // call tsan interceptor
+  call ASM_SYMBOL(__tsan_setjmp)
+
+  // Restore env parameter
+  ld a0, 8(sp)
+  CFI_RESTORE (10)
+
+  // Restore frame/link register
+  ld s0, 16(sp)
+  ld ra, 24(sp)
+  addi sp, sp, 32
+  CFI_RESTORE (8)
+  CFI_RESTORE (1)
+  CFI_DEF_CFA (2, 0)
+
+  // tail jump to libc setjmp
+  la t1, _ZN14__interception12real__setjmpE
+  ld t1, 0(t1)
+  jr t1
+
+  CFI_ENDPROC
+ASM_SIZE(ASM_SYMBOL_INTERCEPTOR(_setjmp))
+
+.comm _ZN14__interception14real_sigsetjmpE,8,8
+.globl ASM_SYMBOL_INTERCEPTOR(sigsetjmp)
+ASM_TYPE_FUNCTION(ASM_SYMBOL_INTERCEPTOR(sigsetjmp))
+ASM_SYMBOL_INTERCEPTOR(sigsetjmp):
+  CFI_STARTPROC
+
+  // Save frame pointer and return address register
+  addi sp, sp, -32
+  sd ra, 24(sp)
+  sd s0, 16(sp)
+  CFI_DEF_CFA_OFFSET (32)
+  CFI_OFFSET (1, -8)
+  CFI_OFFSET (8, -16)
+
+  // Adjust the SP for previous frame
+  addi s0, sp, 32
+  CFI_DEF_CFA_REGISTER (8)
+
+  // Save env parameter
+  sd a0, 8(s

[PATCH] D145214: [TSAN] add support for riscv64

[Alex Fan via Phabricator via cfe-commits]

alexfanqi added inline comments.



Comment at: compiler-rt/lib/tsan/rtl/tsan_platform.h:971
 };
-const uptr indicator = 0x0e00ull;
+const uptr indicator = 0x0f00ull;
 const uptr ind_lsb = 1ull << LeastSignificantSetBitIndex(indicator);

jrtc27 wrote:
> ?
This is changed for sv48. Tsan compresses the address to 44 bits and uses the 
top 3 bits (42-44) to uncompress it by comparing with the corresponding bits in 
the mapping. So the 42-44th bits of each app mapping range must be all 
different from each other.  But 3 bits are not enough to distinguish mappings 
in this scheme of MappingRiscv64_48, so I increment it to 4 bits. An 
alternative of this would be reducing app mapping size by half.



Comment at: compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp:270-271
+#elif SANITIZER_RISCV64
+  // the bottom half of vma is allocated for userspace
+  vmaSize = vmaSize + 1;
+# if !SANITIZER_GO

jrtc27 wrote:
> Why don't other architectures need the +1?
I am not too sure about other architectures. Perhaps, because riscv kernel 
divides vma range further by 2. 
https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/asm/pgtable.h#L785
By https://docs.kernel.org/riscv/vm-layout.html, botton half is exposed for 
userspace, top half is for kernel.
The available userspace virtual address size for arm64 with same bit size is 
exactly double of riscv. For example, 39bit -> 0x40(riscv) vs 
0x80(arm64) 




Comment at: compiler-rt/test/tsan/test.h:77
+#elif defined(__riscv) && __riscv_xlen == 64
+const int kPCInc = 2;
 #else

jrtc27 wrote:
> What's this the length of? RVC is optional.
The same length as in GetPreviousInstructionPc. Without it, I got java_race_pc, 
race_range_pc test failure.


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[PATCH] D145214: [TSAN] add support for riscv64

[Alex Fan via Phabricator via cfe-commits]

alexfanqi added a comment.

friendly ping?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145214/new/

https://reviews.llvm.org/D145214

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