[PATCH] D102118: [BPF] add support for 32 bit registers in inline asm

[Alessandro Decina via Phabricator via cfe-commits]

alessandrod updated this revision to Diff 345599.
alessandrod added a comment.

Enable "w" constraint when -mcpu=v3 and fix whitespace.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102118/new/

https://reviews.llvm.org/D102118

Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  clang/test/CodeGen/bpf-inline-asm.c
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFISelLowering.h
  llvm/test/CodeGen/BPF/inlineasm-wreg.ll

Index: llvm/test/CodeGen/BPF/inlineasm-wreg.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/inlineasm-wreg.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=bpfel -mattr=+alu32 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -march=bpfeb -mattr=+alu32 -verify-machineinstrs | FileCheck %s
+
+; Test that %w works as input constraint
+; CHECK-LABEL: test_inlineasm_w_input_constraint
+define dso_local i32 @test_inlineasm_w_input_constraint() {
+  tail call void asm sideeffect "w0 = $0", "w"(i32 42)
+; CHECK: w0 = w1
+  ret i32 42
+}
+
+; Test that %w works as output constraint
+; CHECK-LABEL: test_inlineasm_w_output_constraint
+define dso_local i32 @test_inlineasm_w_output_constraint() {
+  %1 = tail call i32 asm sideeffect "$0 = $1", "=w,i"(i32 42)
+; CHECK: w0 = 42
+  ret i32 %1
+}
Index: llvm/lib/Target/BPF/BPFISelLowering.h
===
--- llvm/lib/Target/BPF/BPFISelLowering.h
+++ llvm/lib/Target/BPF/BPFISelLowering.h
@@ -46,6 +46,9 @@
   // with the given GlobalAddress is legal.
   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 
+  BPFTargetLowering::ConstraintType
+  getConstraintType(StringRef Constraint) const override;
+
   std::pair
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override;
Index: llvm/lib/Target/BPF/BPFISelLowering.cpp
===
--- llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -220,6 +220,20 @@
   return NumBits1 == 32 && NumBits2 == 64;
 }
 
+BPFTargetLowering::ConstraintType
+BPFTargetLowering::getConstraintType(StringRef Constraint) const {
+  if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+default:
+  break;
+case 'w':
+  return C_RegisterClass;
+}
+  }
+
+  return TargetLowering::getConstraintType(Constraint);
+}
+
 std::pair
 BPFTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 StringRef Constraint,
@@ -229,6 +243,10 @@
 switch (Constraint[0]) {
 case 'r': // GENERAL_REGS
   return std::make_pair(0U, &BPF::GPRRegClass);
+case 'w':
+  if (HasAlu32)
+return std::make_pair(0U, &BPF::GPR32RegClass);
+  break;
 default:
   break;
 }
Index: clang/test/CodeGen/bpf-inline-asm.c
===
--- /dev/null
+++ clang/test/CodeGen/bpf-inline-asm.c
@@ -0,0 +1,33 @@
+// REQUIRES: bpf-registered-target
+// RUN: %clang -target bpf -emit-llvm -S -Xclang -target-feature -Xclang +alu32 %s -o - | FileCheck %s
+// RUN: %clang -target bpf -emit-llvm -S -mcpu=v3 %s -o - | FileCheck %s
+
+long var;
+
+void test_generic_constraints(int var32, long var64) {
+  asm("%0 = %1"
+  : "=r"(var32)
+  : "0"(var32));
+  // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32*
+  // CHECK: call i32 asm "$0 = $1", "=r,0"(i32 [[R32_ARG]])
+
+  asm("%0 = %1"
+  : "=r"(var64)
+  : "0"(var64));
+  // CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, i64*
+  // CHECK: call i64 asm "$0 = $1", "=r,0"(i64 [[R64_ARG]])
+
+  asm("%0 = %1"
+  : "=r"(var64)
+  : "r"(var64));
+  // CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, i64*
+  // CHECK: call i64 asm "$0 = $1", "=r,r"(i64 [[R64_ARG]])
+}
+
+void test_constraint_w(int a) {
+  asm("%0 = %1"
+  : "=w"(a)
+  : "w"(a));
+  // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32*
+  // CHECK: call i32 asm "$0 = $1", "=w,w"(i32 [[R32_ARG]])
+}
Index: clang/lib/Basic/Targets/BPF.h
===
--- clang/lib/Basic/Targets/BPF.h
+++ clang/lib/Basic/Targets/BPF.h
@@ -23,6 +23,7 @@
 
 class LLVM_LIBRARY_VISIBILITY BPFTargetInfo : public TargetInfo {
   static const Builtin::Info BuiltinInfo[];
+  bool HasAlu32 = false;
 
 public:
   BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
@@ -55,6 +56,8 @@
  bool Enabled) const override {
 Features[Name] = Enabled;
   }
+  bool handleTargetFeatures(std::vector &Features,
+DiagnosticsEngine &Diags) override;
 
   ArrayRef getTargetBuiltins() const override;
 
@@ -68,7 +71,16 @@
   ArrayRef getGCCRegNames() const override { return None; }
 
   bool validateAsmConstraint

[PATCH] D102118: [BPF] add support for 32 bit registers in inline asm

[Alessandro Decina via Phabricator via cfe-commits]

alessandrod updated this revision to Diff 345680.
alessandrod added a comment.

Remove unused global from test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102118/new/

https://reviews.llvm.org/D102118

Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  clang/test/CodeGen/bpf-inline-asm.c
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFISelLowering.h
  llvm/test/CodeGen/BPF/inlineasm-wreg.ll

Index: llvm/test/CodeGen/BPF/inlineasm-wreg.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/inlineasm-wreg.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=bpfel -mattr=+alu32 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -march=bpfeb -mattr=+alu32 -verify-machineinstrs | FileCheck %s
+
+; Test that %w works as input constraint
+; CHECK-LABEL: test_inlineasm_w_input_constraint
+define dso_local i32 @test_inlineasm_w_input_constraint() {
+  tail call void asm sideeffect "w0 = $0", "w"(i32 42)
+; CHECK: w0 = w1
+  ret i32 42
+}
+
+; Test that %w works as output constraint
+; CHECK-LABEL: test_inlineasm_w_output_constraint
+define dso_local i32 @test_inlineasm_w_output_constraint() {
+  %1 = tail call i32 asm sideeffect "$0 = $1", "=w,i"(i32 42)
+; CHECK: w0 = 42
+  ret i32 %1
+}
Index: llvm/lib/Target/BPF/BPFISelLowering.h
===
--- llvm/lib/Target/BPF/BPFISelLowering.h
+++ llvm/lib/Target/BPF/BPFISelLowering.h
@@ -46,6 +46,9 @@
   // with the given GlobalAddress is legal.
   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 
+  BPFTargetLowering::ConstraintType
+  getConstraintType(StringRef Constraint) const override;
+
   std::pair
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override;
Index: llvm/lib/Target/BPF/BPFISelLowering.cpp
===
--- llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -220,6 +220,20 @@
   return NumBits1 == 32 && NumBits2 == 64;
 }
 
+BPFTargetLowering::ConstraintType
+BPFTargetLowering::getConstraintType(StringRef Constraint) const {
+  if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+default:
+  break;
+case 'w':
+  return C_RegisterClass;
+}
+  }
+
+  return TargetLowering::getConstraintType(Constraint);
+}
+
 std::pair
 BPFTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 StringRef Constraint,
@@ -229,6 +243,10 @@
 switch (Constraint[0]) {
 case 'r': // GENERAL_REGS
   return std::make_pair(0U, &BPF::GPRRegClass);
+case 'w':
+  if (HasAlu32)
+return std::make_pair(0U, &BPF::GPR32RegClass);
+  break;
 default:
   break;
 }
Index: clang/test/CodeGen/bpf-inline-asm.c
===
--- /dev/null
+++ clang/test/CodeGen/bpf-inline-asm.c
@@ -0,0 +1,31 @@
+// REQUIRES: bpf-registered-target
+// RUN: %clang -target bpf -emit-llvm -S -Xclang -target-feature -Xclang +alu32 %s -o - | FileCheck %s
+// RUN: %clang -target bpf -emit-llvm -S -mcpu=v3 %s -o - | FileCheck %s
+
+void test_generic_constraints(int var32, long var64) {
+  asm("%0 = %1"
+  : "=r"(var32)
+  : "0"(var32));
+  // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32*
+  // CHECK: call i32 asm "$0 = $1", "=r,0"(i32 [[R32_ARG]])
+
+  asm("%0 = %1"
+  : "=r"(var64)
+  : "0"(var64));
+  // CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, i64*
+  // CHECK: call i64 asm "$0 = $1", "=r,0"(i64 [[R64_ARG]])
+
+  asm("%0 = %1"
+  : "=r"(var64)
+  : "r"(var64));
+  // CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, i64*
+  // CHECK: call i64 asm "$0 = $1", "=r,r"(i64 [[R64_ARG]])
+}
+
+void test_constraint_w(int a) {
+  asm("%0 = %1"
+  : "=w"(a)
+  : "w"(a));
+  // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32*
+  // CHECK: call i32 asm "$0 = $1", "=w,w"(i32 [[R32_ARG]])
+}
Index: clang/lib/Basic/Targets/BPF.h
===
--- clang/lib/Basic/Targets/BPF.h
+++ clang/lib/Basic/Targets/BPF.h
@@ -23,6 +23,7 @@
 
 class LLVM_LIBRARY_VISIBILITY BPFTargetInfo : public TargetInfo {
   static const Builtin::Info BuiltinInfo[];
+  bool HasAlu32 = false;
 
 public:
   BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
@@ -55,6 +56,8 @@
  bool Enabled) const override {
 Features[Name] = Enabled;
   }
+  bool handleTargetFeatures(std::vector &Features,
+DiagnosticsEngine &Diags) override;
 
   ArrayRef getTargetBuiltins() const override;
 
@@ -68,7 +71,16 @@
   ArrayRef getGCCRegNames() const override { return None; }
 
   bool validateAsmConstraint(const char *&Name,
- 

[PATCH] D102118: [BPF] add support for 32 bit registers in inline asm

[Alessandro Decina via Phabricator via cfe-commits]

alessandrod added a comment.

In D102118#2761476 , @yonghong-song 
wrote:

> LGTM except one minor issue. Please do address the nit before merging. Thanks!

Done, thanks for the review! I don't have commit access so someone will have to 
merge this for me :)


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  rG LLVM Github Monorepo

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[PATCH] D102118: [BPF] add support for 32 bit registers in inline asm

[Alessandro Decina via Phabricator via cfe-commits]

alessandrod created this revision.
Herald added a subscriber: hiraditya.
alessandrod requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Add "w" constraint type which allows selecting 32 bit registers.

32 bit registers were added in 
https://reviews.llvm.org/rGca31c3bb3ff149850b664838fbbc7d40ce571879.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102118

Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  clang/test/CodeGen/bpf-inline-asm.c
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFISelLowering.h
  llvm/test/CodeGen/BPF/inlineasm-wreg.ll

Index: llvm/test/CodeGen/BPF/inlineasm-wreg.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/inlineasm-wreg.ll
@@ -0,0 +1,19 @@
+
+; RUN: llc < %s -march=bpfel -mattr=+alu32 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -march=bpfeb -mattr=+alu32 -verify-machineinstrs | FileCheck %s
+
+; Test that %w works as input constraint
+; CHECK-LABEL: test_inlineasm_w_input_constraint
+define dso_local i32 @test_inlineasm_w_input_constraint() {
+  tail call void asm sideeffect "w0 = $0", "w"(i32 42)
+; CHECK: w0 = w1
+  ret i32 42
+}
+
+; Test that %w works as output constraint
+; CHECK-LABEL: test_inlineasm_w_output_constraint
+define dso_local i32 @test_inlineasm_w_output_constraint() {
+  %1 = tail call i32 asm sideeffect "$0 = $1", "=w,i"(i32 42)
+; CHECK: w0 = 42
+  ret i32 %1
+}
\ No newline at end of file
Index: llvm/lib/Target/BPF/BPFISelLowering.h
===
--- llvm/lib/Target/BPF/BPFISelLowering.h
+++ llvm/lib/Target/BPF/BPFISelLowering.h
@@ -46,6 +46,9 @@
   // with the given GlobalAddress is legal.
   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 
+  BPFTargetLowering::ConstraintType
+  getConstraintType(StringRef Constraint) const override;
+
   std::pair
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override;
Index: llvm/lib/Target/BPF/BPFISelLowering.cpp
===
--- llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -220,6 +220,20 @@
   return NumBits1 == 32 && NumBits2 == 64;
 }
 
+BPFTargetLowering::ConstraintType
+BPFTargetLowering::getConstraintType(StringRef Constraint) const {
+  if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+default:
+  break;
+case 'w':
+  return C_RegisterClass;
+}
+  }
+
+  return TargetLowering::getConstraintType(Constraint);
+}
+
 std::pair
 BPFTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 StringRef Constraint,
@@ -229,6 +243,10 @@
 switch (Constraint[0]) {
 case 'r': // GENERAL_REGS
   return std::make_pair(0U, &BPF::GPRRegClass);
+case 'w':
+  if (HasAlu32)
+return std::make_pair(0U, &BPF::GPR32RegClass);
+  break;
 default:
   break;
 }
Index: clang/test/CodeGen/bpf-inline-asm.c
===
--- /dev/null
+++ clang/test/CodeGen/bpf-inline-asm.c
@@ -0,0 +1,32 @@
+// REQUIRES: bpf-registered-target
+// RUN: %clang -target bpf -emit-llvm -S -Xclang -target-feature -Xclang +alu32 %s -o - | FileCheck %s
+
+long var;
+
+void test_generic_constraints(int var32, long var64) {
+  asm("%0 = %1"
+  : "=r"(var32)
+  : "0"(var32));
+  // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32*
+  // CHECK: call i32 asm "$0 = $1", "=r,0"(i32 [[R32_ARG]])
+
+  asm("%0 = %1"
+  : "=r"(var64)
+  : "0"(var64));
+  // CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, i64*
+  // CHECK: call i64 asm "$0 = $1", "=r,0"(i64 [[R64_ARG]])
+
+  asm("%0 = %1"
+  : "=r"(var64)
+  : "r"(var64));
+  // CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, i64*
+  // CHECK: call i64 asm "$0 = $1", "=r,r"(i64 [[R64_ARG]])
+}
+
+void test_constraint_w(int a) {
+  asm("%0 = %1"
+  : "=w"(a)
+  : "w"(a));
+  // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32*
+  // CHECK: call i32 asm "$0 = $1", "=w,w"(i32 [[R32_ARG]])
+}
\ No newline at end of file
Index: clang/lib/Basic/Targets/BPF.h
===
--- clang/lib/Basic/Targets/BPF.h
+++ clang/lib/Basic/Targets/BPF.h
@@ -23,6 +23,7 @@
 
 class LLVM_LIBRARY_VISIBILITY BPFTargetInfo : public TargetInfo {
   static const Builtin::Info BuiltinInfo[];
+  bool HasAlu32 = false;
 
 public:
   BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
@@ -55,6 +56,8 @@
  bool Enabled) const override {
 Features[Name] = Enabled;
   }
+  bool handleTargetFeatures(std::vector &Features,
+DiagnosticsEngine &Diags) override;