[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-01 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse updated this revision to Diff 527345.
akshaykhadse added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Add CFE tests


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Files:
  clang/test/CodeGen/ms-inline-asm-64.c
  clang/test/CodeGen/ms-inline-asm.c
  llvm/lib/Target/X86/AsmParser/X86Operand.h
  llvm/test/MC/X86/x86-64-movdir64b-intel.s


Index: llvm/test/MC/X86/x86-64-movdir64b-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/x86-64-movdir64b-intel.s
@@ -0,0 +1,4 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel 
-output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: movdir64b rax, zmmword ptr [rax - 4096]
+// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x80,0x00,0xf0,0xff,0xff]
+  movdir64b rax, zmmword ptr [rax - 4096]
Index: llvm/lib/Target/X86/AsmParser/X86Operand.h
===
--- llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -383,6 +383,8 @@
   bool isMem512_GR16() const {
 if (!isMem512())
   return false;
+if (getMemDisp()->getKind() == llvm::MCExpr::SymbolRef)
+  return true;
 if (getMemBaseReg() &&
 !X86MCRegisterClasses[X86::GR16RegClassID].contains(getMemBaseReg()))
   return false;
@@ -391,6 +393,8 @@
   bool isMem512_GR32() const {
 if (!isMem512())
   return false;
+if (getMemDisp()->getKind() == llvm::MCExpr::SymbolRef)
+  return true;
 if (getMemBaseReg() &&
 !X86MCRegisterClasses[X86::GR32RegClassID].contains(getMemBaseReg()) &&
 getMemBaseReg() != X86::EIP)
@@ -404,6 +408,8 @@
   bool isMem512_GR64() const {
 if (!isMem512())
   return false;
+if (getMemDisp()->getKind() == llvm::MCExpr::SymbolRef)
+  return true;
 if (getMemBaseReg() &&
 !X86MCRegisterClasses[X86::GR64RegClassID].contains(getMemBaseReg()) &&
 getMemBaseReg() != X86::RIP)
Index: clang/test/CodeGen/ms-inline-asm.c
===
--- clang/test/CodeGen/ms-inline-asm.c
+++ clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm enqcmds eax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "enqcmds eax, zmmword ptr 
$0", "*m,~{flags},~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) 
%arr)
+}
+
 void dot_operator(void){
   // CHECK-LABEL: define{{.*}} void @dot_operator
__asm { mov eax, 3[ebx]A.b}
Index: clang/test/CodeGen/ms-inline-asm-64.c
===
--- clang/test/CodeGen/ms-inline-asm-64.c
+++ clang/test/CodeGen/ms-inline-asm-64.c
@@ -72,3 +72,10 @@
   // CHECK-SAME: jmp ${1:P}
   // CHECK-SAME: "*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(void 
(...)) @bar, ptr elementtype(void (...)) @bar)
 }
+
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm enqcmds rax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "enqcmds rax, zmmword ptr 
$0", "*m,~{flags},~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) 
%arr)
+}


Index: llvm/test/MC/X86/x86-64-movdir64b-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/x86-64-movdir64b-intel.s
@@ -0,0 +1,4 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: movdir64b rax, zmmword ptr [rax - 4096]
+// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x80,0x00,0xf0,0xff,0xff]
+  movdir64b rax, zmmword ptr [rax - 4096]
Index: llvm/lib/Target/X86/AsmParser/X86Operand.h
===
--- llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -383,6 +383,8 @@
   bool isMem512_GR16() const {
 if (!isMem512())
   return false;
+if (getMemDisp()->getKind() == llvm::MCExpr::SymbolRef)
+  return true;
 if (getMemBaseReg() &&
 !X86MCRegisterClasses[X86::GR16RegClassID].contains(getMemBaseReg()))
   return false;
@@ -391,6 +393,8 @@
   bool isMem512_GR32() const {
 if (!isMem512())
   return false;
+if (getMemDisp()->getKind() == llvm::MCExpr::SymbolRef)
+  return true;
 if (getMemBaseReg() &&
 !X86MCRegisterClasses[X86::GR32RegClassID].contains(getMemBaseReg()) &&
 getMemBaseReg() != X86::EIP)
@@ -404,6 +408,8 @@
   bool isMem512_GR64() const {
 if (!isMem512())
   return false;
+if (getMemDisp()->getKind() == llvm::M

[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-01 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse added a comment.

Please let me know if these tests and changes look okay.


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[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-01 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse added inline comments.



Comment at: clang/test/CodeGen/ms-inline-asm-64.c:79
+  int arr[1000];
+  __asm enqcmds rax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "enqcmds rax, zmmword ptr 
$0", "*m,~{flags},~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) 
%arr)

XinWang10 wrote:
> This could be movdir64b?
You are correct. Thanks! I will update it


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[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-01 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse updated this revision to Diff 527725.
akshaykhadse added a comment.

Update AsmParser


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Files:
  clang/test/CodeGen/ms-inline-asm-64.c
  clang/test/CodeGen/ms-inline-asm.c
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
  llvm/lib/Target/X86/AsmParser/X86Operand.h
  llvm/test/MC/X86/x86-64-movdir64b-intel.s


Index: llvm/test/MC/X86/x86-64-movdir64b-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/x86-64-movdir64b-intel.s
@@ -0,0 +1,4 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel 
-output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: movdir64b rax, zmmword ptr [rax - 4096]
+// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x80,0x00,0xf0,0xff,0xff]
+  movdir64b rax, zmmword ptr [rax - 4096]
Index: llvm/lib/Target/X86/AsmParser/X86Operand.h
===
--- llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -383,6 +383,8 @@
   bool isMem512_GR16() const {
 if (!isMem512())
   return false;
+if (getMemBaseReg() == X86::NoRegister)
+  return true;
 if (getMemBaseReg() &&
 !X86MCRegisterClasses[X86::GR16RegClassID].contains(getMemBaseReg()))
   return false;
@@ -391,6 +393,8 @@
   bool isMem512_GR32() const {
 if (!isMem512())
   return false;
+if (getMemBaseReg() == X86::NoRegister)
+  return true;
 if (getMemBaseReg() &&
 !X86MCRegisterClasses[X86::GR32RegClassID].contains(getMemBaseReg()) &&
 getMemBaseReg() != X86::EIP)
@@ -404,6 +408,8 @@
   bool isMem512_GR64() const {
 if (!isMem512())
   return false;
+if (getMemBaseReg() == X86::NoRegister)
+  return true;
 if (getMemBaseReg() &&
 !X86MCRegisterClasses[X86::GR64RegClassID].contains(getMemBaseReg()) &&
 getMemBaseReg() != X86::RIP)
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1776,10 +1776,9 @@
  BaseReg && IndexReg));
 return false;
   }
-  // Otherwise, we set the base register to a non-zero value
-  // if we don't know the actual value at this time.  This is necessary to
-  // get the matching correct in some cases.
-  BaseReg = BaseReg ? BaseReg : 1;
+  // Otherwise, we set the base register to a zero if we don't know the actual 
+  // value at this time.
+  BaseReg = BaseReg ? BaseReg : 0;
   Operands.push_back(X86Operand::CreateMem(
   getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
   Size,
Index: clang/test/CodeGen/ms-inline-asm.c
===
--- clang/test/CodeGen/ms-inline-asm.c
+++ clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b eax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b eax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
+
 void dot_operator(void){
   // CHECK-LABEL: define{{.*}} void @dot_operator
__asm { mov eax, 3[ebx]A.b}
Index: clang/test/CodeGen/ms-inline-asm-64.c
===
--- clang/test/CodeGen/ms-inline-asm-64.c
+++ clang/test/CodeGen/ms-inline-asm-64.c
@@ -72,3 +72,10 @@
   // CHECK-SAME: jmp ${1:P}
   // CHECK-SAME: "*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(void 
(...)) @bar, ptr elementtype(void (...)) @bar)
 }
+
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b rax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b rax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}


Index: llvm/test/MC/X86/x86-64-movdir64b-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/x86-64-movdir64b-intel.s
@@ -0,0 +1,4 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: movdir64b rax, zmmword ptr [rax - 4096]
+// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x80,0x00,0xf0,0xff,0xff]
+  movdir64b rax, zmmword ptr [rax - 4096]
Index: llvm/lib/Target/X86/AsmParser/X86Operand.h
===
--- llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -3

[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-01 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse added inline comments.



Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:1781
+  // value at this time.
+  BaseReg = BaseReg ? BaseReg : 0;
   Operands.push_back(X86Operand::CreateMem(

craig.topper wrote:
> This sets BaseReg to 0 if its already 0?
Oops. Is this even required? I think we can get rid of this. There are no tests 
that failed.


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[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-01 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse added inline comments.



Comment at: llvm/lib/Target/X86/AsmParser/X86Operand.h:386
   return false;
+if (getMemBaseReg() == X86::NoRegister)
+  return true;

craig.topper wrote:
> Now we're not checking the index register if there is no base register?
Let me fix this.


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[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-02 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse updated this revision to Diff 527764.
akshaykhadse added a comment.

Address review comments


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Files:
  clang/test/CodeGen/ms-inline-asm-64.c
  clang/test/CodeGen/ms-inline-asm.c
  llvm/lib/Target/X86/AsmParser/X86Operand.h
  llvm/test/MC/X86/x86-64-movdir64b-intel.s


Index: llvm/test/MC/X86/x86-64-movdir64b-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/x86-64-movdir64b-intel.s
@@ -0,0 +1,4 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel 
-output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: movdir64b rax, zmmword ptr [rax - 4096]
+// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x80,0x00,0xf0,0xff,0xff]
+  movdir64b rax, zmmword ptr [rax - 4096]
Index: llvm/lib/Target/X86/AsmParser/X86Operand.h
===
--- llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -383,6 +383,9 @@
   bool isMem512_GR16() const {
 if (!isMem512())
   return false;
+if (getMemBaseReg() == X86::AH) {
+  return true;
+}
 if (getMemBaseReg() &&
 !X86MCRegisterClasses[X86::GR16RegClassID].contains(getMemBaseReg()))
   return false;
@@ -391,27 +394,33 @@
   bool isMem512_GR32() const {
 if (!isMem512())
   return false;
-if (getMemBaseReg() &&
-!X86MCRegisterClasses[X86::GR32RegClassID].contains(getMemBaseReg()) &&
-getMemBaseReg() != X86::EIP)
-  return false;
 if (getMemIndexReg() &&
 !X86MCRegisterClasses[X86::GR32RegClassID].contains(getMemIndexReg()) 
&&
 getMemIndexReg() != X86::EIZ)
   return false;
+if (getMemBaseReg() == X86::AH) {
+  return true;
+}
+if (getMemBaseReg() &&
+!X86MCRegisterClasses[X86::GR32RegClassID].contains(getMemBaseReg()) &&
+getMemBaseReg() != X86::EIP)
+  return false;
 return true;
   }
   bool isMem512_GR64() const {
 if (!isMem512())
   return false;
-if (getMemBaseReg() &&
-!X86MCRegisterClasses[X86::GR64RegClassID].contains(getMemBaseReg()) &&
-getMemBaseReg() != X86::RIP)
-  return false;
 if (getMemIndexReg() &&
 !X86MCRegisterClasses[X86::GR64RegClassID].contains(getMemIndexReg()) 
&&
 getMemIndexReg() != X86::RIZ)
   return false;
+if (getMemBaseReg() == X86::AH) {
+  return true;
+}
+if (getMemBaseReg() &&
+!X86MCRegisterClasses[X86::GR64RegClassID].contains(getMemBaseReg()) &&
+getMemBaseReg() != X86::RIP)
+  return false;
 return true;
   }
 
Index: clang/test/CodeGen/ms-inline-asm.c
===
--- clang/test/CodeGen/ms-inline-asm.c
+++ clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b eax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b eax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
+
 void dot_operator(void){
   // CHECK-LABEL: define{{.*}} void @dot_operator
__asm { mov eax, 3[ebx]A.b}
Index: clang/test/CodeGen/ms-inline-asm-64.c
===
--- clang/test/CodeGen/ms-inline-asm-64.c
+++ clang/test/CodeGen/ms-inline-asm-64.c
@@ -72,3 +72,10 @@
   // CHECK-SAME: jmp ${1:P}
   // CHECK-SAME: "*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(void 
(...)) @bar, ptr elementtype(void (...)) @bar)
 }
+
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b rax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b rax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}


Index: llvm/test/MC/X86/x86-64-movdir64b-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/x86-64-movdir64b-intel.s
@@ -0,0 +1,4 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: movdir64b rax, zmmword ptr [rax - 4096]
+// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x80,0x00,0xf0,0xff,0xff]
+  movdir64b rax, zmmword ptr [rax - 4096]
Index: llvm/lib/Target/X86/AsmParser/X86Operand.h
===
--- llvm/lib/Target/X86/AsmParser/X86Operand.h
+++ llvm/lib/Target/X86/AsmParser/X86Operand.h
@@ -383,6 +383,9 @@
   bool isMem512_GR16() const {
 if (!isMem512())
   return false;
+if (getMemBaseReg() == X86::AH)

[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-02 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse added a comment.

If we could get rid of `BaseReg = BaseReg ? BaseReg : 1;` in 
`X86AsmParser::CreateMemForMSInlineAsm`, then we don't need any changes in the 
`X86Operand.h`.
F27787125: image.png 

I was not able to find any failing tests after making the change. But, this has 
existed for 11 years in the codebase, so I am not sure if making this change 
will break things in unexpected ways. Let me know what you think.


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[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-02 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse added a comment.

In D151863#4390132 , @craig.topper 
wrote:

> I still think replacing the `1` with a valid register for the mode is the 
> better fix.

So, should I create a new registers? Something like `X86::Sym16`, `X86::Sym32` 
and `X86::Sym64`?


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[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-02 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse updated this revision to Diff 527783.
akshaykhadse added a comment.

Implement solution mentioned in comments


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Files:
  clang/test/CodeGen/ms-inline-asm-64.c
  clang/test/CodeGen/ms-inline-asm.c
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
  llvm/test/MC/X86/x86-64-movdir64b-intel.s


Index: llvm/test/MC/X86/x86-64-movdir64b-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/x86-64-movdir64b-intel.s
@@ -0,0 +1,4 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel 
-output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: movdir64b rax, zmmword ptr [rax - 4096]
+// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x80,0x00,0xf0,0xff,0xff]
+  movdir64b rax, zmmword ptr [rax - 4096]
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1777,9 +1777,21 @@
 return false;
   }
   // Otherwise, we set the base register to a non-zero value
-  // if we don't know the actual value at this time.  This is necessary to
+  // if we don't know the actual value at this time. This is necessary to
   // get the matching correct in some cases.
-  BaseReg = BaseReg ? BaseReg : 1;
+  if (BaseReg == X86::NoRegister) {
+switch (getPointerWidth()) {
+  case 16:
+BaseReg = X86::AX;
+break;
+  case 32:
+BaseReg = X86::EAX;
+break;
+  case 64:
+BaseReg = X86::RAX;
+break;
+}
+  }
   Operands.push_back(X86Operand::CreateMem(
   getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
   Size,
Index: clang/test/CodeGen/ms-inline-asm.c
===
--- clang/test/CodeGen/ms-inline-asm.c
+++ clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b eax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b eax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
+
 void dot_operator(void){
   // CHECK-LABEL: define{{.*}} void @dot_operator
__asm { mov eax, 3[ebx]A.b}
Index: clang/test/CodeGen/ms-inline-asm-64.c
===
--- clang/test/CodeGen/ms-inline-asm-64.c
+++ clang/test/CodeGen/ms-inline-asm-64.c
@@ -72,3 +72,10 @@
   // CHECK-SAME: jmp ${1:P}
   // CHECK-SAME: "*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(void 
(...)) @bar, ptr elementtype(void (...)) @bar)
 }
+
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b rax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b rax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}


Index: llvm/test/MC/X86/x86-64-movdir64b-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/x86-64-movdir64b-intel.s
@@ -0,0 +1,4 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: movdir64b rax, zmmword ptr [rax - 4096]
+// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x80,0x00,0xf0,0xff,0xff]
+  movdir64b rax, zmmword ptr [rax - 4096]
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1777,9 +1777,21 @@
 return false;
   }
   // Otherwise, we set the base register to a non-zero value
-  // if we don't know the actual value at this time.  This is necessary to
+  // if we don't know the actual value at this time. This is necessary to
   // get the matching correct in some cases.
-  BaseReg = BaseReg ? BaseReg : 1;
+  if (BaseReg == X86::NoRegister) {
+switch (getPointerWidth()) {
+  case 16:
+BaseReg = X86::AX;
+break;
+  case 32:
+BaseReg = X86::EAX;
+break;
+  case 64:
+BaseReg = X86::RAX;
+break;
+}
+  }
   Operands.push_back(X86Operand::CreateMem(
   getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
   Size,
Index: clang/test/CodeGen/ms-inline-asm.c
===
--- clang/test/CodeGen/ms-inline-asm.c
+++ clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
   // CHECK: call void asm sideeffect inteldiale

[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-02 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse updated this revision to Diff 527797.
akshaykhadse added a comment.

Fix formatting


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Files:
  clang/test/CodeGen/ms-inline-asm-64.c
  clang/test/CodeGen/ms-inline-asm.c
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
  llvm/test/MC/X86/x86-64-movdir64b-intel.s


Index: llvm/test/MC/X86/x86-64-movdir64b-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/x86-64-movdir64b-intel.s
@@ -0,0 +1,4 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel 
-output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: movdir64b rax, zmmword ptr [rax - 4096]
+// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x80,0x00,0xf0,0xff,0xff]
+  movdir64b rax, zmmword ptr [rax - 4096]
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1777,9 +1777,21 @@
 return false;
   }
   // Otherwise, we set the base register to a non-zero value
-  // if we don't know the actual value at this time.  This is necessary to
+  // if we don't know the actual value at this time. This is necessary to
   // get the matching correct in some cases.
-  BaseReg = BaseReg ? BaseReg : 1;
+  if (BaseReg == X86::NoRegister) {
+switch (getPointerWidth()) {
+case 16:
+  BaseReg = X86::AX;
+  break;
+case 32:
+  BaseReg = X86::EAX;
+  break;
+case 64:
+  BaseReg = X86::RAX;
+  break;
+}
+  }
   Operands.push_back(X86Operand::CreateMem(
   getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
   Size,
Index: clang/test/CodeGen/ms-inline-asm.c
===
--- clang/test/CodeGen/ms-inline-asm.c
+++ clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b eax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b eax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
+
 void dot_operator(void){
   // CHECK-LABEL: define{{.*}} void @dot_operator
__asm { mov eax, 3[ebx]A.b}
Index: clang/test/CodeGen/ms-inline-asm-64.c
===
--- clang/test/CodeGen/ms-inline-asm-64.c
+++ clang/test/CodeGen/ms-inline-asm-64.c
@@ -72,3 +72,10 @@
   // CHECK-SAME: jmp ${1:P}
   // CHECK-SAME: "*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(void 
(...)) @bar, ptr elementtype(void (...)) @bar)
 }
+
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b rax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b rax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}


Index: llvm/test/MC/X86/x86-64-movdir64b-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/x86-64-movdir64b-intel.s
@@ -0,0 +1,4 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: movdir64b rax, zmmword ptr [rax - 4096]
+// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x80,0x00,0xf0,0xff,0xff]
+  movdir64b rax, zmmword ptr [rax - 4096]
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1777,9 +1777,21 @@
 return false;
   }
   // Otherwise, we set the base register to a non-zero value
-  // if we don't know the actual value at this time.  This is necessary to
+  // if we don't know the actual value at this time. This is necessary to
   // get the matching correct in some cases.
-  BaseReg = BaseReg ? BaseReg : 1;
+  if (BaseReg == X86::NoRegister) {
+switch (getPointerWidth()) {
+case 16:
+  BaseReg = X86::AX;
+  break;
+case 32:
+  BaseReg = X86::EAX;
+  break;
+case 64:
+  BaseReg = X86::RAX;
+  break;
+}
+  }
   Operands.push_back(X86Operand::CreateMem(
   getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
   Size,
Index: clang/test/CodeGen/ms-inline-asm.c
===
--- clang/test/CodeGen/ms-inline-asm.c
+++ clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", "~{eax},~{flags},~{dirflag},~{fp

[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-04 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse added a comment.

@craig.topper, @skan: Does this look good?


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[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-04 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse added inline comments.



Comment at: llvm/test/MC/X86/x86-64-movdir64b-intel.s:1
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel 
-output-asm-variant=1 --show-encoding %s | FileCheck %s
+// CHECK: movdir64b rax, zmmword ptr [rax - 4096]

skan wrote:
> The test can pass w/o this patch. I think we should replace it with IR test 
> (llc) here, the input should be the diff in ms-inline-asm-64.c.
It is better to remove this as it does not add any value.

We cannot write a llc test for this because:
  - If input IR is `call ... "movdir64b eax, ZMMWORD PTR arr ..."`, the 
generated assembly will be `movdir64b arr, %rax"
  - If input IR is `call ... "movdir64b eax, ZMMWORD PTR $0 ..."`, the 
generated assembly will be `movdir64b -4016(%rbp), %rax"

In other words, it's responsibility of front-end to generate the correct IR. If 
the IR is not correct, the back-end will not fix it and incorrect assembly will 
be generated.



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[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-04 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse added inline comments.



Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:1780
   // Otherwise, we set the base register to a non-zero value
-  // if we don't know the actual value at this time.  This is necessary to
+  // if we don't know the actual value at this time. This is necessary to
   // get the matching correct in some cases.

skan wrote:
> This logic was firstly added by 7ca135b25ff408fda31f3b01d5e9303054e8267f.
> 
> I am not sure whether it's out of date now. But if removing it can make your 
> test pass and not introduce LIT regression,  removing should be a better fix. 
> 
> We shouldn't turn a logic we don't understand into another logic we don't 
> understand, which would confuse later developers
Ok, let me change this.


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[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-05 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse updated this revision to Diff 528311.
akshaykhadse added a comment.

Remove logic to set BaseReg to non-zero value


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151863/new/

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Files:
  clang/test/CodeGen/ms-inline-asm-64.c
  clang/test/CodeGen/ms-inline-asm.c
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp


Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1776,10 +1776,6 @@
  BaseReg && IndexReg));
 return false;
   }
-  // Otherwise, we set the base register to a non-zero value
-  // if we don't know the actual value at this time.  This is necessary to
-  // get the matching correct in some cases.
-  BaseReg = BaseReg ? BaseReg : 1;
   Operands.push_back(X86Operand::CreateMem(
   getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
   Size,
Index: clang/test/CodeGen/ms-inline-asm.c
===
--- clang/test/CodeGen/ms-inline-asm.c
+++ clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b eax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b eax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
+
 void dot_operator(void){
   // CHECK-LABEL: define{{.*}} void @dot_operator
__asm { mov eax, 3[ebx]A.b}
Index: clang/test/CodeGen/ms-inline-asm-64.c
===
--- clang/test/CodeGen/ms-inline-asm-64.c
+++ clang/test/CodeGen/ms-inline-asm-64.c
@@ -72,3 +72,10 @@
   // CHECK-SAME: jmp ${1:P}
   // CHECK-SAME: "*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(void 
(...)) @bar, ptr elementtype(void (...)) @bar)
 }
+
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b rax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b rax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}


Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1776,10 +1776,6 @@
  BaseReg && IndexReg));
 return false;
   }
-  // Otherwise, we set the base register to a non-zero value
-  // if we don't know the actual value at this time.  This is necessary to
-  // get the matching correct in some cases.
-  BaseReg = BaseReg ? BaseReg : 1;
   Operands.push_back(X86Operand::CreateMem(
   getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
   Size,
Index: clang/test/CodeGen/ms-inline-asm.c
===
--- clang/test/CodeGen/ms-inline-asm.c
+++ clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", "~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b eax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b eax, zmmword ptr $0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
+
 void dot_operator(void){
   // CHECK-LABEL: define{{.*}} void @dot_operator
 	__asm { mov eax, 3[ebx]A.b}
Index: clang/test/CodeGen/ms-inline-asm-64.c
===
--- clang/test/CodeGen/ms-inline-asm-64.c
+++ clang/test/CodeGen/ms-inline-asm-64.c
@@ -72,3 +72,10 @@
   // CHECK-SAME: jmp ${1:P}
   // CHECK-SAME: "*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(void (...)) @bar, ptr elementtype(void (...)) @bar)
 }
+
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b rax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b rax, zmmword ptr $0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
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[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-05 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse updated this revision to Diff 528339.
akshaykhadse added a comment.

Add more tests


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Files:
  clang/test/CodeGen/ms-inline-asm-64.c
  clang/test/CodeGen/ms-inline-asm.c
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
  llvm/test/CodeGen/X86/movdir64b-inline-asm-x86_64.ll
  llvm/test/CodeGen/X86/movdir64b-inline-asm.ll


Index: llvm/test/CodeGen/X86/movdir64b-inline-asm.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/movdir64b-inline-asm.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+movdir64b | FileCheck %s 
--check-prefix=X86
+
+define void @test_movdir64b() {
+; X86-LABEL: test_movdir64b:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:subl $4000, %esp # imm = 0xFA0
+; X86-NEXT:.cfi_def_cfa_offset 4004
+; X86-NEXT:#APP
+; X86-EMPTY:
+; X86-NEXT:movdir64b (%esp), %eax
+; X86-EMPTY:
+; X86-NEXT:#NO_APP
+; X86-NEXT:addl $4000, %esp # imm = 0xFA0
+; X86-NEXT:.cfi_def_cfa_offset 4
+; X86-NEXT:retl
+entry:
+  %arr = alloca [1000 x i32], align 4
+  call void asm sideeffect inteldialect "movdir64b eax, zmmword ptr $0", 
"*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+  ret void
+}
Index: llvm/test/CodeGen/X86/movdir64b-inline-asm-x86_64.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/movdir64b-inline-asm-x86_64.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+movdir64b | FileCheck 
%s --check-prefix=X64
+
+define void @test_movdir64b() {
+; X64-LABEL: test_movdir64b:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:subq $3880, %rsp # imm = 0xF28
+; X64-NEXT:.cfi_def_cfa_offset 3888
+; X64-NEXT:#APP
+; X64-EMPTY:
+; X64-NEXT:movdir64b -{{[0-9]+}}(%rsp), %rax
+; X64-EMPTY:
+; X64-NEXT:#NO_APP
+; X64-NEXT:addq $3880, %rsp # imm = 0xF28
+; X64-NEXT:.cfi_def_cfa_offset 8
+; X64-NEXT:retq
+entry:
+  %arr = alloca [1000 x i32], align 16
+  call void asm sideeffect inteldialect "movdir64b rax, zmmword ptr $0", 
"*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+  ret void
+}
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1776,10 +1776,6 @@
  BaseReg && IndexReg));
 return false;
   }
-  // Otherwise, we set the base register to a non-zero value
-  // if we don't know the actual value at this time.  This is necessary to
-  // get the matching correct in some cases.
-  BaseReg = BaseReg ? BaseReg : 1;
   Operands.push_back(X86Operand::CreateMem(
   getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
   Size,
Index: clang/test/CodeGen/ms-inline-asm.c
===
--- clang/test/CodeGen/ms-inline-asm.c
+++ clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b eax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b eax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
+
 void dot_operator(void){
   // CHECK-LABEL: define{{.*}} void @dot_operator
__asm { mov eax, 3[ebx]A.b}
Index: clang/test/CodeGen/ms-inline-asm-64.c
===
--- clang/test/CodeGen/ms-inline-asm-64.c
+++ clang/test/CodeGen/ms-inline-asm-64.c
@@ -72,3 +72,10 @@
   // CHECK-SAME: jmp ${1:P}
   // CHECK-SAME: "*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(void 
(...)) @bar, ptr elementtype(void (...)) @bar)
 }
+
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b rax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b rax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}


Index: llvm/test/CodeGen/X86/movdir64b-inline-asm.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/movdir64b-inline-asm.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+movdir64b | FileCheck %s --ch

[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-06 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse marked an inline comment as done.
akshaykhadse added inline comments.



Comment at: llvm/test/CodeGen/X86/movdir64b-inline-asm-x86_64.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+movdir64b | FileCheck 
%s --check-prefix=X64

MaskRay wrote:
> I think we should reuse an existing `*-inline-asm-*` test file.
> 
> See 
> https://maskray.me/blog/2021-08-08-toolchain-testing#the-test-checks-at-the-wrong-layer
>  "I don't know an existing test can be enhanced"
**I could not find an appropriate existing test.**
I added a couple of cases in the CFE tests 
`clang/test/CodeGen/ms-inline-asm-64.c` and 
`clang/test/CodeGen/ms-inline-asm.c`.
Now, when I had to add backend tests, I searched for an appropriate file:
```
llvm-project$ find llvm/test/CodeGen/X86 -type f -name ms-inline-asm-*
llvm/test/CodeGen/X86/ms-inline-asm-variables-x86-2-regs.ll
llvm/test/CodeGen/X86/ms-inline-asm-array.ll
llvm/test/CodeGen/X86/ms-inline-asm-PR44272.ll
llvm/test/CodeGen/X86/ms-inline-asm-variables-x64-2-regs.ll
llvm/test/CodeGen/X86/ms-inline-asm-functions.ll
llvm/test/CodeGen/X86/ms-inline-asm-redundant-clobber.ll
llvm/test/CodeGen/X86/ms-inline-asm-variables-x64-1-reg.ll
llvm/test/CodeGen/X86/ms-inline-asm-variables-x86-1-reg.ll
llvm/test/CodeGen/X86/ms-inline-asm-avx512.ll
llvm/test/CodeGen/X86/ms-inline-asm-variables-x64-nopic.ll
```
As you can see, there are tests for variables, functions, arrays, but no 
general tests like `ms-inline-asm.ll`.
My general observation is that for a CFE test `*-inline-asm*.c` there's an 
equivalent test in LLVM backend which mentions the original test name in the 
comment. For example, `ms-inline-asm-variables-x86-2-regs.ll` mentions that 
`Tests come from "clang/test/CodeGen/ms-inline-asm-variables.c"`.
However, there is no such file which mentions either `ms-inline-asm.c` or 
`ms-inline-asm-64.c`
So, I picked up an assembly instruction `xgetbv` from `ms-inline-asm.c` and 
searched it in the available `.ll` backend test via `llvm-project$ find 
llvm/test -type f -name *.ll -exec grep -l "xgetbv" {} \;`. There was just one 
file `llvm/test/CodeGen/X86/system-intrinsics-xgetbv.ll` that contains test for 
just this one instruction.
**Please suggest an appropriate 32-bit and 64-bit file to add this test**


Repository:
  rG LLVM Github Monorepo

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[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-07 Thread Akshay Khadse via Phabricator via cfe-commits 
akshaykhadse updated this revision to Diff 529491.
akshaykhadse added a comment.

Rename test files


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151863/new/

https://reviews.llvm.org/D151863

Files:
  clang/test/CodeGen/ms-inline-asm-64.c
  clang/test/CodeGen/ms-inline-asm.c
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
  llvm/test/CodeGen/X86/inline-asm-movdir64b-x86_64.ll
  llvm/test/CodeGen/X86/inline-asm-movdir64b.ll


Index: llvm/test/CodeGen/X86/inline-asm-movdir64b.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/inline-asm-movdir64b.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+movdir64b | FileCheck %s 
--check-prefix=X86
+
+define void @test_movdir64b() {
+; X86-LABEL: test_movdir64b:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:subl $4000, %esp # imm = 0xFA0
+; X86-NEXT:.cfi_def_cfa_offset 4004
+; X86-NEXT:#APP
+; X86-EMPTY:
+; X86-NEXT:movdir64b (%esp), %eax
+; X86-EMPTY:
+; X86-NEXT:#NO_APP
+; X86-NEXT:addl $4000, %esp # imm = 0xFA0
+; X86-NEXT:.cfi_def_cfa_offset 4
+; X86-NEXT:retl
+entry:
+  %arr = alloca [1000 x i32], align 4
+  call void asm sideeffect inteldialect "movdir64b eax, zmmword ptr $0", 
"*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+  ret void
+}
Index: llvm/test/CodeGen/X86/inline-asm-movdir64b-x86_64.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/inline-asm-movdir64b-x86_64.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+movdir64b | FileCheck 
%s --check-prefix=X64
+
+define void @test_movdir64b() {
+; X64-LABEL: test_movdir64b:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:subq $3880, %rsp # imm = 0xF28
+; X64-NEXT:.cfi_def_cfa_offset 3888
+; X64-NEXT:#APP
+; X64-EMPTY:
+; X64-NEXT:movdir64b -{{[0-9]+}}(%rsp), %rax
+; X64-EMPTY:
+; X64-NEXT:#NO_APP
+; X64-NEXT:addq $3880, %rsp # imm = 0xF28
+; X64-NEXT:.cfi_def_cfa_offset 8
+; X64-NEXT:retq
+entry:
+  %arr = alloca [1000 x i32], align 16
+  call void asm sideeffect inteldialect "movdir64b rax, zmmword ptr $0", 
"*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+  ret void
+}
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1776,10 +1776,6 @@
  BaseReg && IndexReg));
 return false;
   }
-  // Otherwise, we set the base register to a non-zero value
-  // if we don't know the actual value at this time.  This is necessary to
-  // get the matching correct in some cases.
-  BaseReg = BaseReg ? BaseReg : 1;
   Operands.push_back(X86Operand::CreateMem(
   getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
   Size,
Index: clang/test/CodeGen/ms-inline-asm.c
===
--- clang/test/CodeGen/ms-inline-asm.c
+++ clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b eax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b eax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
+
 void dot_operator(void){
   // CHECK-LABEL: define{{.*}} void @dot_operator
__asm { mov eax, 3[ebx]A.b}
Index: clang/test/CodeGen/ms-inline-asm-64.c
===
--- clang/test/CodeGen/ms-inline-asm-64.c
+++ clang/test/CodeGen/ms-inline-asm-64.c
@@ -72,3 +72,10 @@
   // CHECK-SAME: jmp ${1:P}
   // CHECK-SAME: "*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(void 
(...)) @bar, ptr elementtype(void (...)) @bar)
 }
+
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b rax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b rax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}


Index: llvm/test/CodeGen/X86/inline-asm-movdir64b.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/inline-asm-movdir64b.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+movdir64b | FileCheck %s -

[PATCH] D151863: [x86][MC] Fix movdir64b addressing

2023-06-08 Thread Akshay Khadse via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG15f15ab2c895: [x86][MC] Fix movdir64b addressing (authored 
by akshaykhadse).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151863/new/

https://reviews.llvm.org/D151863

Files:
  clang/test/CodeGen/ms-inline-asm-64.c
  clang/test/CodeGen/ms-inline-asm.c
  llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
  llvm/test/CodeGen/X86/inline-asm-movdir64b-x86_64.ll
  llvm/test/CodeGen/X86/inline-asm-movdir64b.ll


Index: llvm/test/CodeGen/X86/inline-asm-movdir64b.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/inline-asm-movdir64b.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+movdir64b | FileCheck %s 
--check-prefix=X86
+
+define void @test_movdir64b() {
+; X86-LABEL: test_movdir64b:
+; X86:   # %bb.0: # %entry
+; X86-NEXT:subl $4000, %esp # imm = 0xFA0
+; X86-NEXT:.cfi_def_cfa_offset 4004
+; X86-NEXT:#APP
+; X86-EMPTY:
+; X86-NEXT:movdir64b (%esp), %eax
+; X86-EMPTY:
+; X86-NEXT:#NO_APP
+; X86-NEXT:addl $4000, %esp # imm = 0xFA0
+; X86-NEXT:.cfi_def_cfa_offset 4
+; X86-NEXT:retl
+entry:
+  %arr = alloca [1000 x i32], align 4
+  call void asm sideeffect inteldialect "movdir64b eax, zmmword ptr $0", 
"*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+  ret void
+}
Index: llvm/test/CodeGen/X86/inline-asm-movdir64b-x86_64.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/inline-asm-movdir64b-x86_64.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+movdir64b | FileCheck 
%s --check-prefix=X64
+
+define void @test_movdir64b() {
+; X64-LABEL: test_movdir64b:
+; X64:   # %bb.0: # %entry
+; X64-NEXT:subq $3880, %rsp # imm = 0xF28
+; X64-NEXT:.cfi_def_cfa_offset 3888
+; X64-NEXT:#APP
+; X64-EMPTY:
+; X64-NEXT:movdir64b -{{[0-9]+}}(%rsp), %rax
+; X64-EMPTY:
+; X64-NEXT:#NO_APP
+; X64-NEXT:addq $3880, %rsp # imm = 0xF28
+; X64-NEXT:.cfi_def_cfa_offset 8
+; X64-NEXT:retq
+entry:
+  %arr = alloca [1000 x i32], align 16
+  call void asm sideeffect inteldialect "movdir64b rax, zmmword ptr $0", 
"*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+  ret void
+}
Index: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
===
--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1776,10 +1776,6 @@
  BaseReg && IndexReg));
 return false;
   }
-  // Otherwise, we set the base register to a non-zero value
-  // if we don't know the actual value at this time.  This is necessary to
-  // get the matching correct in some cases.
-  BaseReg = BaseReg ? BaseReg : 1;
   Operands.push_back(X86Operand::CreateMem(
   getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,
   Size,
Index: clang/test/CodeGen/ms-inline-asm.c
===
--- clang/test/CodeGen/ms-inline-asm.c
+++ clang/test/CodeGen/ms-inline-asm.c
@@ -675,6 +675,13 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b eax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b eax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}
+
 void dot_operator(void){
   // CHECK-LABEL: define{{.*}} void @dot_operator
__asm { mov eax, 3[ebx]A.b}
Index: clang/test/CodeGen/ms-inline-asm-64.c
===
--- clang/test/CodeGen/ms-inline-asm-64.c
+++ clang/test/CodeGen/ms-inline-asm-64.c
@@ -72,3 +72,10 @@
   // CHECK-SAME: jmp ${1:P}
   // CHECK-SAME: "*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(void 
(...)) @bar, ptr elementtype(void (...)) @bar)
 }
+
+void t47(void) {
+  // CHECK-LABEL: define{{.*}} void @t47
+  int arr[1000];
+  __asm movdir64b rax, zmmword ptr [arr]
+  // CHECK: call void asm sideeffect inteldialect "movdir64b rax, zmmword ptr 
$0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype([1000 x i32]) %arr)
+}


Index: llvm/test/CodeGen/X86/inline-asm-movdir64b.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/inline-asm-movdir64b.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc