[clang] [CUDA] Add support for __grid_constant__ attribute (PR #114589)

[Akshay Deodhar via cfe-commits]

https://github.com/akshayrdeodhar approved this pull request.


https://github.com/llvm/llvm-project/pull/114589
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[clang] [CUDA] Add support for __grid_constant__ attribute (PR #114589)

[Akshay Deodhar via cfe-commits]

@@ -1,8 +1,17 @@ bool Sema::CheckFunctionDeclaration(Scope *S, 
FunctionDecl *NewFD,
 << NewFD;
 }
 
-if (!Redeclaration && LangOpts.CUDA)
+if (!Redeclaration && LangOpts.CUDA) {

akshayrdeodhar wrote:

This makes sense. Perhaps a warning? But even that might not be necessary- 
anyone who is using `__grid_constant__` knows what they are using it for. 

https://github.com/llvm/llvm-project/pull/114589
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[clang] [CUDA] Add support for __grid_constant__ attribute (PR #114589)

[Akshay Deodhar via cfe-commits]

akshayrdeodhar wrote:

The LLVM-facing parts of this lgtm

https://github.com/llvm/llvm-project/pull/114589
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[clang] [CUDA] Add support for __grid_constant__ attribute (PR #114589)

[Akshay Deodhar via cfe-commits]

@@ -1,8 +1,17 @@ bool Sema::CheckFunctionDeclaration(Scope *S, 
FunctionDecl *NewFD,
 << NewFD;
 }
 
-if (!Redeclaration && LangOpts.CUDA)
+if (!Redeclaration && LangOpts.CUDA) {

akshayrdeodhar wrote:

Is it possible to add a check for sm70+ for grid_constant here?

https://github.com/llvm/llvm-project/pull/114589
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[clang] [CUDA] Add support for __grid_constant__ attribute (PR #114589)

[Akshay Deodhar via cfe-commits]

@@ -1,8 +1,17 @@ bool Sema::CheckFunctionDeclaration(Scope *S, 
FunctionDecl *NewFD,
 << NewFD;
 }
 
-if (!Redeclaration && LangOpts.CUDA)
+if (!Redeclaration && LangOpts.CUDA) {

akshayrdeodhar wrote:

Makes sense. I also realized that you'd already addressed this in the 
description 🙂 
> One notable difference from NVCC is that the attribute can be used regardless 
> of the targeted GPU. On the older GPUs it will just be ignored. The attribute 
> is a performance hint, and does not warrant a hard error if compiler can't 
> benefit from it on a particular GPU variant.

https://github.com/llvm/llvm-project/pull/114589
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[clang] [llvm] [NVPTX] Auto-Upgrade llvm.nvvm.atomic.load.{inc,dec}.32 (PR #134111)

[Akshay Deodhar via cfe-commits]

@@ -2070,8 +2070,8 @@ defm INT_PTX_ATOMIC_UMIN_32 : F_ATOMIC_2_AS]>;
 
 // atom_inc  atom_dec

akshayrdeodhar wrote:

We don't have a PTX test to prove that the final lowering to PTX will be the 
same, but this looks good enough.

https://github.com/llvm/llvm-project/pull/134111
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[clang] [llvm] [NVPTX] Auto-Upgrade llvm.nvvm.atomic.load.{inc,dec}.32 (PR #134111)

[Akshay Deodhar via cfe-commits]

https://github.com/akshayrdeodhar approved this pull request.

LGTM! Comments are just questions.

https://github.com/llvm/llvm-project/pull/134111
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[clang] [llvm] [NVPTX] Auto-Upgrade llvm.nvvm.atomic.load.{inc,dec}.32 (PR #134111)

[Akshay Deodhar via cfe-commits]

https://github.com/akshayrdeodhar edited 
https://github.com/llvm/llvm-project/pull/134111
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[clang] [llvm] [NVPTX] Auto-Upgrade llvm.nvvm.atomic.load.{inc,dec}.32 (PR #134111)

[Akshay Deodhar via cfe-commits]

@@ -2314,6 +2317,12 @@ static Value *upgradeNVVMIntrinsicCall(StringRef Name, 
CallBase *CI,
 Value *Val = CI->getArgOperand(1);
 Rep = Builder.CreateAtomicRMW(AtomicRMWInst::FAdd, Ptr, Val, MaybeAlign(),
   AtomicOrdering::SequentiallyConsistent);
+  } else if (Name.consume_front("atomic.load.") && Name.consume_back(".32")) {
+Value *Ptr = CI->getArgOperand(0);
+Value *Val = CI->getArgOperand(1);
+auto Op = Name == "inc" ? AtomicRMWInst::UIncWrap : 
AtomicRMWInst::UDecWrap;
+Rep = Builder.CreateAtomicRMW(Op, Ptr, Val, MaybeAlign(),
+  AtomicOrdering::SequentiallyConsistent);

akshayrdeodhar wrote:

But we are lowering cmpxchg with seq_cst correctly by using fence.sc and 
atom.acq_rel.cas. @gonzalobg - will this also break frontends?

https://github.com/llvm/llvm-project/pull/134111
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[clang] [llvm] [NVPTX] Auto-Upgrade llvm.nvvm.atomic.load.{inc,dec}.32 (PR #134111)

[Akshay Deodhar via cfe-commits]

@@ -2314,6 +2317,12 @@ static Value *upgradeNVVMIntrinsicCall(StringRef Name, 
CallBase *CI,
 Value *Val = CI->getArgOperand(1);
 Rep = Builder.CreateAtomicRMW(AtomicRMWInst::FAdd, Ptr, Val, MaybeAlign(),
   AtomicOrdering::SequentiallyConsistent);
+  } else if (Name.consume_front("atomic.load.") && Name.consume_back(".32")) {
+Value *Ptr = CI->getArgOperand(0);
+Value *Val = CI->getArgOperand(1);
+auto Op = Name == "inc" ? AtomicRMWInst::UIncWrap : 
AtomicRMWInst::UDecWrap;
+Rep = Builder.CreateAtomicRMW(Op, Ptr, Val, MaybeAlign(),
+  AtomicOrdering::SequentiallyConsistent);

akshayrdeodhar wrote:

The intrinsic does not mention anything about ordering, but I suppose seq_cst 
is the safest?

https://github.com/llvm/llvm-project/pull/134111
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[clang] [llvm] [NVPTX] Auto-Upgrade llvm.nvvm.atomic.load.{inc,dec}.32 (PR #134111)

[Akshay Deodhar via cfe-commits]

akshayrdeodhar wrote:

For reference: 
https://docs.nvidia.com/cuda/nvvm-ir-spec/index.html#nvvm-specific-intrinsic-functions

https://github.com/llvm/llvm-project/pull/134111
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