[clang] [llvm] [PowerPC] Add BCDCOPYSIGN and BCDSETSIGN Instruction Support (PR #144874)

2025-06-19 Thread Aditi Medhane via cfe-commits 

https://github.com/AditiRM created 
https://github.com/llvm/llvm-project/pull/144874

Support the following BCD format conversion builtins for PowerPC.

- `__builtin_bcdcopysign` – Conversion that returns the decimal value of the 
first parameter combined with the sign code of the second parameter.  
- `__builtin_bcdsetsign` – Conversion that sets the sign code of the input 
parameter in packed decimal format.

## Prototypes

```c
vector unsigned char __builtin_bcdcopysign(vector unsigned char, vector 
unsigned char);
vector unsigned char __builtin_bcdsetsign(vector unsigned char, unsigned char);
```

## Reference Links

- 
[bcdcopysign](https://www.ibm.com/docs/en/xl-c-and-cpp-aix/16.1.0?topic=end-builtin-bcdcopysign-clang-based-front)

- 
[bcdsetsign](https://www.ibm.com/docs/en/xl-c-and-cpp-aix/16.1.0?topic=end-builtin-bcdsetsign-clang-based-front)


>From 8e287c19723361b0141c7bf9d1de34b145b9782c Mon Sep 17 00:00:00 2001
From: Aditi-Medhane 
Date: Thu, 19 Jun 2025 11:04:12 +
Subject: [PATCH] [PowerPC] Add BCDCOPYSIGN and BCDSETSIGN Instruction Support

---
 clang/include/clang/Basic/BuiltinsPPC.def |  4 ++
 clang/lib/Basic/Targets/PPC.cpp   |  2 +
 clang/lib/Sema/SemaPPC.cpp|  2 +
 .../CodeGen/PowerPC/builtins-bcd-helpers.c| 29 ++
 llvm/include/llvm/IR/IntrinsicsPowerPC.td |  8 
 llvm/lib/Target/PowerPC/PPCInstrAltivec.td|  6 ++-
 .../CodeGen/PowerPC/builtins-bcd-helpers.ll   | 40 +++
 7 files changed, 89 insertions(+), 2 deletions(-)
 create mode 100644 clang/test/CodeGen/PowerPC/builtins-bcd-helpers.c
 create mode 100644 llvm/test/CodeGen/PowerPC/builtins-bcd-helpers.ll

diff --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index bb7d54bbb793e..c3825822ce0b8 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -515,6 +515,10 @@ TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "", 
"power9-vector")
 TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector")
 TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector")
 
+//P9 BCD builtins
+TARGET_BUILTIN(__builtin_ppc_bcdcopysign, "V16UcV16UcV16Uc", "", 
"power9-vector")
+TARGET_BUILTIN(__builtin_ppc_bcdsetsign, "V16UcV16UcUc", "t", "power9-vector")
+
 // P7 BCD builtins.
 TARGET_BUILTIN(__builtin_cdtbcd, "UiUi", "", "isa-v206-instructions")
 TARGET_BUILTIN(__builtin_cbcdtd, "UiUi", "", "isa-v206-instructions")
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e6ef0ecc526ba..876348c29b707 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -88,6 +88,8 @@ bool 
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
 }
 
 static void defineXLCompatMacros(MacroBuilder &Builder) {
+  Builder.defineMacro("__builtin_bcdcopysign", "__builtin_ppc_bcdcopysign");
+  Builder.defineMacro("__builtin_bcdsetsign", "__builtin_ppc_bcdsetsign");
   Builder.defineMacro("__cdtbcd", "__builtin_ppc_cdtbcd");
   Builder.defineMacro("__cbcdtd", "__builtin_ppc_cbcdtd");
   Builder.defineMacro("__addg6s", "__builtin_ppc_addg6s");
diff --git a/clang/lib/Sema/SemaPPC.cpp b/clang/lib/Sema/SemaPPC.cpp
index 9b4d82745f881..71673062044af 100644
--- a/clang/lib/Sema/SemaPPC.cpp
+++ b/clang/lib/Sema/SemaPPC.cpp
@@ -106,6 +106,8 @@ bool SemaPPC::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI,
   switch (BuiltinID) {
   default:
 return false;
+  case PPC::BI__builtin_ppc_bcdsetsign:
+return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1);
   case PPC::BI__builtin_altivec_crypto_vshasigmaw:
   case PPC::BI__builtin_altivec_crypto_vshasigmad:
 return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1) ||
diff --git a/clang/test/CodeGen/PowerPC/builtins-bcd-helpers.c 
b/clang/test/CodeGen/PowerPC/builtins-bcd-helpers.c
new file mode 100644
index 0..0aeb720e545ed
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/builtins-bcd-helpers.c
@@ -0,0 +1,29 @@
+// NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -O2 -target-cpu pwr9 \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -O2 -target-cpu pwr9 \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-unknown -O2 -target-cpu pwr9 \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: test_bcdcopysign
+// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdcopysign(<16 
x i8> %a, <16 x i8> %b)
+// CHECK-NEXT:ret <16 x i8> [[TMP0]]
+vector unsigned char test_bcdcopysign(vector unsigned char a, vector unsigned 
char b) {
+return __builtin_ppc_bcdcopysign(a, b);
+}
+
+// CHECK-LABEL: test_bcdsetsign_imm0
+// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16

[clang] [llvm] [PowerPC] Add BCDCOPYSIGN and BCDSETSIGN Instruction Support (PR #144874)

2025-06-24 Thread Aditi Medhane via cfe-commits 


@@ -515,6 +515,10 @@ TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "", 
"power9-vector")
 TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector")
 TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector")
 
+//P9 BCD builtins
+TARGET_BUILTIN(__builtin_ppc_bcdcopysign, "V16UcV16UcV16Uc", "", 
"power9-vector")

AditiRM wrote:

This is another power9 instruction according to the documentation : 
[[documentation of XLC 
compiler](https://www.ibm.com/docs/en/xl-c-and-cpp-aix/16.1.0?topic=end-builtin-bcdcopysign-clang-based-front)]
Since bcdcopysign and bcdsetsign operate on vector types and are specific to 
Power9, the appropriate feature for these builtins is power9-vector.

https://github.com/llvm/llvm-project/pull/144874
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[clang] [llvm] [PowerPC] Add BCDCOPYSIGN and BCDSETSIGN Instruction Support (PR #144874)

2025-06-24 Thread Aditi Medhane via cfe-commits 

https://github.com/AditiRM edited 
https://github.com/llvm/llvm-project/pull/144874
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[clang] [llvm] [PowerPC] Add BCDCOPYSIGN and BCDSETSIGN Instruction Support (PR #144874)

2025-06-25 Thread Aditi Medhane via cfe-commits 

https://github.com/AditiRM updated 
https://github.com/llvm/llvm-project/pull/144874

>From 8e287c19723361b0141c7bf9d1de34b145b9782c Mon Sep 17 00:00:00 2001
From: Aditi-Medhane 
Date: Thu, 19 Jun 2025 11:04:12 +
Subject: [PATCH 1/2] [PowerPC] Add BCDCOPYSIGN and BCDSETSIGN Instruction
 Support

---
 clang/include/clang/Basic/BuiltinsPPC.def |  4 ++
 clang/lib/Basic/Targets/PPC.cpp   |  2 +
 clang/lib/Sema/SemaPPC.cpp|  2 +
 .../CodeGen/PowerPC/builtins-bcd-helpers.c| 29 ++
 llvm/include/llvm/IR/IntrinsicsPowerPC.td |  8 
 llvm/lib/Target/PowerPC/PPCInstrAltivec.td|  6 ++-
 .../CodeGen/PowerPC/builtins-bcd-helpers.ll   | 40 +++
 7 files changed, 89 insertions(+), 2 deletions(-)
 create mode 100644 clang/test/CodeGen/PowerPC/builtins-bcd-helpers.c
 create mode 100644 llvm/test/CodeGen/PowerPC/builtins-bcd-helpers.ll

diff --git a/clang/include/clang/Basic/BuiltinsPPC.def 
b/clang/include/clang/Basic/BuiltinsPPC.def
index bb7d54bbb793e..c3825822ce0b8 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -515,6 +515,10 @@ TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "", 
"power9-vector")
 TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector")
 TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector")
 
+//P9 BCD builtins
+TARGET_BUILTIN(__builtin_ppc_bcdcopysign, "V16UcV16UcV16Uc", "", 
"power9-vector")
+TARGET_BUILTIN(__builtin_ppc_bcdsetsign, "V16UcV16UcUc", "t", "power9-vector")
+
 // P7 BCD builtins.
 TARGET_BUILTIN(__builtin_cdtbcd, "UiUi", "", "isa-v206-instructions")
 TARGET_BUILTIN(__builtin_cbcdtd, "UiUi", "", "isa-v206-instructions")
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e6ef0ecc526ba..876348c29b707 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -88,6 +88,8 @@ bool 
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
 }
 
 static void defineXLCompatMacros(MacroBuilder &Builder) {
+  Builder.defineMacro("__builtin_bcdcopysign", "__builtin_ppc_bcdcopysign");
+  Builder.defineMacro("__builtin_bcdsetsign", "__builtin_ppc_bcdsetsign");
   Builder.defineMacro("__cdtbcd", "__builtin_ppc_cdtbcd");
   Builder.defineMacro("__cbcdtd", "__builtin_ppc_cbcdtd");
   Builder.defineMacro("__addg6s", "__builtin_ppc_addg6s");
diff --git a/clang/lib/Sema/SemaPPC.cpp b/clang/lib/Sema/SemaPPC.cpp
index 9b4d82745f881..71673062044af 100644
--- a/clang/lib/Sema/SemaPPC.cpp
+++ b/clang/lib/Sema/SemaPPC.cpp
@@ -106,6 +106,8 @@ bool SemaPPC::CheckPPCBuiltinFunctionCall(const TargetInfo 
&TI,
   switch (BuiltinID) {
   default:
 return false;
+  case PPC::BI__builtin_ppc_bcdsetsign:
+return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1);
   case PPC::BI__builtin_altivec_crypto_vshasigmaw:
   case PPC::BI__builtin_altivec_crypto_vshasigmad:
 return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1) ||
diff --git a/clang/test/CodeGen/PowerPC/builtins-bcd-helpers.c 
b/clang/test/CodeGen/PowerPC/builtins-bcd-helpers.c
new file mode 100644
index 0..0aeb720e545ed
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/builtins-bcd-helpers.c
@@ -0,0 +1,29 @@
+// NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 5
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -O2 -target-cpu pwr9 \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -O2 -target-cpu pwr9 \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-unknown -O2 -target-cpu pwr9 \
+// RUN:   -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: test_bcdcopysign
+// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdcopysign(<16 
x i8> %a, <16 x i8> %b)
+// CHECK-NEXT:ret <16 x i8> [[TMP0]]
+vector unsigned char test_bcdcopysign(vector unsigned char a, vector unsigned 
char b) {
+return __builtin_ppc_bcdcopysign(a, b);
+}
+
+// CHECK-LABEL: test_bcdsetsign_imm0
+// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 
x i8> %a, i32 0)
+// CHECK-NEXT:ret <16 x i8> [[TMP0]]
+vector unsigned char test_bcdsetsign_imm0(vector unsigned char a) {
+return __builtin_ppc_bcdsetsign(a, '\0');
+}
+
+// CHECK-LABEL: test_bcdsetsign_imm1
+// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 
x i8> %a, i32 1)
+// CHECK-NEXT:ret <16 x i8> [[TMP0]]
+vector unsigned char test_bcdsetsign_imm1(vector unsigned char a) {
+return __builtin_ppc_bcdsetsign(a, '\1');
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td 
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index 84c26599b5b70..bd9d85fdaab92 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -668,6 +668,14 @@ let TargetPrefix = "ppc" in {  // All i

[clang] [llvm] [PowerPC] Add BCDCOPYSIGN and BCDSETSIGN Instruction Support (PR #144874)

2025-06-23 Thread Aditi Medhane via cfe-commits 

https://github.com/AditiRM edited 
https://github.com/llvm/llvm-project/pull/144874
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