[PATCH] D114318: [clang] Add missing CPUID feature bit masks
adamdb5 created this revision. Herald added a subscriber: pengfei. adamdb5 retitled this revision from "Whilst working on a project which uses the x86 CPUID instruction, I noticed the header provided by clang (cpuid.h), is missing some bit masks for the feature registers." to "Add missing CPUID bit masks.". adamdb5 edited the summary of this revision. adamdb5 retitled this revision from "Add missing CPUID bit masks." to "Add missing CPUID feature bit masks.". adamdb5 retitled this revision from "Add missing CPUID feature bit masks." to "Add missing CPUID feature bit masks". adamdb5 retitled this revision from "Add missing CPUID feature bit masks" to "[clang] Add missing CPUID feature bit masks". adamdb5 added a project: clang. adamdb5 updated this revision to Diff 388718. adamdb5 added a comment. adamdb5 added reviewers: pengfei, chenyang.liu, xiangzhangllvm. adamdb5 published this revision for review. Herald added a subscriber: cfe-commits. ran clang-format adamdb5 added a comment. [clang] Add missing CPUID feature bit masks Whilst working on a project which uses the x86 CPUID instruction, I noticed the header provided by clang (cpuid.h), is missing some bit masks for the feature registers. I've implemented the missing masks, and also noticed that the previous mask for PKU was shifted one bit too far to the right. It was 0b100, when it should have been 0b1000. Sources: https://www.scss.tcd.ie/~jones/CS4021/processor-identification-cpuid-instruction-note.pdf https://www.felixcloutier.com/x86/cpuid This is my first commit, so please let me know if this is worth considering, and any feedback is appreciated. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D114318 Files: clang/lib/Headers/cpuid.h Index: clang/lib/Headers/cpuid.h === --- clang/lib/Headers/cpuid.h +++ clang/lib/Headers/cpuid.h @@ -73,248 +73,274 @@ #define signature_VORTEX_ecx 0x436f5320 /* Features in %ecx for leaf 1 */ -#define bit_SSE30x0001 -#define bit_PCLMULQDQ 0x0002 -#define bit_PCLMUL bit_PCLMULQDQ /* for gcc compat */ -#define bit_DTES64 0x0004 -#define bit_MONITOR 0x0008 -#define bit_DSCPL 0x0010 -#define bit_VMX 0x0020 -#define bit_SMX 0x0040 -#define bit_EIST0x0080 -#define bit_TM2 0x0100 -#define bit_SSSE3 0x0200 -#define bit_CNXTID 0x0400 -#define bit_FMA 0x1000 -#define bit_CMPXCHG16B 0x2000 -#define bit_xTPR0x4000 -#define bit_PDCM0x8000 -#define bit_PCID0x0002 -#define bit_DCA 0x0004 -#define bit_SSE41 0x0008 -#define bit_SSE4_1 bit_SSE41 /* for gcc compat */ -#define bit_SSE42 0x0010 -#define bit_SSE4_2 bit_SSE42 /* for gcc compat */ -#define bit_x2APIC 0x0020 -#define bit_MOVBE 0x0040 -#define bit_POPCNT 0x0080 +#define bit_SSE3 0x0001 +#define bit_PCLMULQDQ 0x0002 +#define bit_PCLMUL bit_PCLMULQDQ /* for gcc compat */ +#define bit_DTES64 0x0004 +#define bit_MONITOR 0x0008 +#define bit_DSCPL 0x0010 +#define bit_VMX 0x0020 +#define bit_SMX 0x0040 +#define bit_EIST 0x0080 +#define bit_TM2 0x0100 +#define bit_SSSE3 0x0200 +#define bit_CNXTID 0x0400 +#define bit_SDBG 0x0800 +#define bit_FMA 0x1000 +#define bit_CMPXCHG16B 0x2000 +#define bit_xTPR 0x4000 +#define bit_PDCM 0x8000 +#define bit_PCID 0x0002 +#define bit_DCA 0x0004 +#define bit_SSE41 0x0008 +#define bit_SSE4_1 bit_SSE41 /* for gcc compat */ +#define bit_SSE42 0x0010 +#define bit_SSE4_2 bit_SSE42 /* for gcc compat */ +#define bit_x2APIC 0x0020 +#define bit_MOVBE 0x0040 +#define bit_POPCNT 0x0080 #define bit_TSCDeadline 0x0100 -#define bit_AESNI 0x0200 -#define bit_AES bit_AESNI /* for gcc compat */ -#define bit_XSAVE 0x0400 -#define bit_OSXSAVE 0x0800 -#define bit_AVX 0x1000 -#define bit_F16C0x2000 -#define bit_RDRND 0x4000 +#define bit_AESNI 0x0200 +#define bit_AES bit_AESNI /* for gcc compat */ +#define bit_XSAVE 0x0400 +#define bit_OSXSAVE 0x0800 +#define bit_AVX 0x1000 +#define bit_F16C 0x2000 +#define bit_RDRND 0x4000 +#define bit_HYPERVISOR 0x8000 /* Features in %edx for leaf 1 */ -#define bit_FPU 0x0001 -#define bit_VME 0x0002 -#define bit_DE 0x0004 -#define bit_PSE 0x0008 -#define bit_TSC 0x0010 -#define bit_MSR 0x0020 -#define bit_PAE 0x0040 -#define bit_MCE 0x0080 -#define bit_CX8 0x0100 -#define bit_CMPXCHG8B bit_CX8 /* for gcc compat */ -#define bit_APIC0x0200 -#define bit_SEP 0x0800 -#define bit_MTRR0x1000 -#define bit_PGE 0x2000 -#define b
[PATCH] D114318: [clang] Add missing CPUID feature bit masks
adamdb5 updated this revision to Diff 388744. adamdb5 added a comment. undo clang-format Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D114318/new/ https://reviews.llvm.org/D114318 Files: clang/lib/Headers/cpuid.h Index: clang/lib/Headers/cpuid.h === --- clang/lib/Headers/cpuid.h +++ clang/lib/Headers/cpuid.h @@ -85,6 +85,7 @@ #define bit_TM2 0x0100 #define bit_SSSE3 0x0200 #define bit_CNXTID 0x0400 +#define bit_SDBG0x0800 #define bit_FMA 0x1000 #define bit_CMPXCHG16B 0x2000 #define bit_xTPR0x4000 @@ -106,6 +107,7 @@ #define bit_AVX 0x1000 #define bit_F16C0x2000 #define bit_RDRND 0x4000 +#define bit_HYPERVISOR 0x8000 /* Features in %edx for leaf 1 */ #define bit_FPU 0x0001 @@ -138,20 +140,26 @@ #define bit_SS 0x0800 #define bit_HTT 0x1000 #define bit_TM 0x2000 +#define bit_IA640x4000 #define bit_PBE 0x8000 /* Features in %ebx for leaf 7 sub-leaf 0 */ #define bit_FSGSBASE0x0001 +#define bit_TSCADJUST 0x0002 #define bit_SGX 0x0004 #define bit_BMI 0x0008 #define bit_HLE 0x0010 #define bit_AVX20x0020 +#define bit_FPUEXCEPT 0x0040 #define bit_SMEP0x0080 #define bit_BMI20x0100 #define bit_ENH_MOVSB 0x0200 #define bit_INVPCID 0x0400 #define bit_RTM 0x0800 +#define bit_RDTM0x1000 +#define bit_DEPRFPUCSDS 0x2000 #define bit_MPX 0x4000 +#define bit_RDTA0x8000 #define bit_AVX512F 0x0001 #define bit_AVX512DQ0x0002 #define bit_RDSEED 0x0004 @@ -159,6 +167,7 @@ #define bit_AVX512IFMA 0x0020 #define bit_CLFLUSHOPT 0x0080 #define bit_CLWB0x0100 +#define bit_IPT 0x0200 #define bit_AVX512PF0x0400 #define bit_AVX512ER0x0800 #define bit_AVX512CD0x1000 @@ -169,7 +178,8 @@ /* Features in %ecx for leaf 7 sub-leaf 0 */ #define bit_PREFTCHWT1 0x0001 #define bit_AVX512VBMI 0x0002 -#define bit_PKU 0x0004 +#define bit_UMIP 0x0004 +#define bit_PKU 0x0008 #define bit_OSPKE0x0010 #define bit_WAITPKG 0x0020 #define bit_AVX512VBMI2 0x0040 @@ -179,18 +189,27 @@ #define bit_VPCLMULQDQ 0x0400 #define bit_AVX512VNNI 0x0800 #define bit_AVX512BITALG 0x1000 +#define bit_TME_EN 0x2000 #define bit_AVX512VPOPCNTDQ 0x4000 +#define bit_LA57 0x0001 #define bit_RDPID0x0040 +#define bit_KL 0x0080 #define bit_CLDEMOTE 0x0200 #define bit_MOVDIRI 0x0800 #define bit_MOVDIR64B0x1000 #define bit_ENQCMD 0x2000 +#define bit_SGX_LC 0x4000 +#define bit_PKS 0x8000 /* Features in %edx for leaf 7 sub-leaf 0 */ #define bit_AVX5124VNNIW 0x0004 #define bit_AVX5124FMAPS 0x0008 +#define bit_FSRM 0x0010 #define bit_UINTR 0x0020 +#define bit_AVX512VPCINT 0x0100 +#define bit_MD_CLEAR 0x0400 #define bit_SERIALIZE 0x4000 +#define bit_HYBRID0x8000 #define bit_TSXLDTRK 0x0001 #define bit_PCONFIG 0x0004 #define bit_IBT 0x0010 @@ -198,6 +217,12 @@ #define bit_AVX512FP160x0080 #define bit_AMXTILE 0x0100 #define bit_AMXINT8 0x0200 +#define bit_IBRS_IBPB 0x0400 +#define bit_STIBP 0x0800 +#define bit_L1DFLUSH 0x1000 +#define bit_IA32_ARCH_CAP 0x2000 +#define bit_IA32_CORE_CAP 0x4000 +#define bit_SSBD 0x8000 /* Features in %eax for leaf 7 sub-leaf 1 */ #define bit_AVXVNNI 0x0008 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D114318: [clang] Add missing CPUID feature bit masks
adamdb5 updated this revision to Diff 388746. adamdb5 added a comment. Thanks for the feedback, please see the following comments: bit_HYPERVISOR: This seems to be standardized. See the following links: - https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/feature-discovery - https://kb.vmware.com/s/article/1009458 Let me know if you think this shouldn't be added. bit_IA64: I'm not entirely sure where I found this. I think it might have been wikipedia or something. I have removed it. bit_TSCADJUST:Changed to match Intel SDM (IA32_TSC_ADJUST). bit_FPUEXCEPT:Changed to match Intel SDM (FDP_EXCPTN_ONLY). bit_IA57: Appears to be defined in June 2021 Intel SDM at Vol. 2A 3-219 (PDF page 794). bit_AVX512VPCINT: Typo, changed to match Intel SDM (AVX512VP2INT). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D114318/new/ https://reviews.llvm.org/D114318 Files: clang/lib/Headers/cpuid.h Index: clang/lib/Headers/cpuid.h === --- clang/lib/Headers/cpuid.h +++ clang/lib/Headers/cpuid.h @@ -85,6 +85,7 @@ #define bit_TM2 0x0100 #define bit_SSSE3 0x0200 #define bit_CNXTID 0x0400 +#define bit_SDBG0x0800 #define bit_FMA 0x1000 #define bit_CMPXCHG16B 0x2000 #define bit_xTPR0x4000 @@ -106,6 +107,7 @@ #define bit_AVX 0x1000 #define bit_F16C0x2000 #define bit_RDRND 0x4000 +#define bit_HYPERVISOR 0x8000 /* Features in %edx for leaf 1 */ #define bit_FPU 0x0001 @@ -141,35 +143,42 @@ #define bit_PBE 0x8000 /* Features in %ebx for leaf 7 sub-leaf 0 */ -#define bit_FSGSBASE0x0001 -#define bit_SGX 0x0004 -#define bit_BMI 0x0008 -#define bit_HLE 0x0010 -#define bit_AVX20x0020 -#define bit_SMEP0x0080 -#define bit_BMI20x0100 -#define bit_ENH_MOVSB 0x0200 -#define bit_INVPCID 0x0400 -#define bit_RTM 0x0800 -#define bit_MPX 0x4000 -#define bit_AVX512F 0x0001 -#define bit_AVX512DQ0x0002 -#define bit_RDSEED 0x0004 -#define bit_ADX 0x0008 -#define bit_AVX512IFMA 0x0020 -#define bit_CLFLUSHOPT 0x0080 -#define bit_CLWB0x0100 -#define bit_AVX512PF0x0400 -#define bit_AVX512ER0x0800 -#define bit_AVX512CD0x1000 -#define bit_SHA 0x2000 -#define bit_AVX512BW0x4000 -#define bit_AVX512VL0x8000 +#define bit_FSGSBASE0x0001 +#define bit_IA32_TSC_ADJUST 0x0002 +#define bit_SGX 0x0004 +#define bit_BMI 0x0008 +#define bit_HLE 0x0010 +#define bit_AVX20x0020 +#define bit_FDP_EXCPTN_ONLY 0x0040 +#define bit_SMEP0x0080 +#define bit_BMI20x0100 +#define bit_ENH_MOVSB 0x0200 +#define bit_INVPCID 0x0400 +#define bit_RTM 0x0800 +#define bit_RDTM0x1000 +#define bit_DEPRFPUCSDS 0x2000 +#define bit_MPX 0x4000 +#define bit_RDTA0x8000 +#define bit_AVX512F 0x0001 +#define bit_AVX512DQ0x0002 +#define bit_RDSEED 0x0004 +#define bit_ADX 0x0008 +#define bit_AVX512IFMA 0x0020 +#define bit_CLFLUSHOPT 0x0080 +#define bit_CLWB0x0100 +#define bit_IPT 0x0200 +#define bit_AVX512PF0x0400 +#define bit_AVX512ER0x0800 +#define bit_AVX512CD0x1000 +#define bit_SHA 0x2000 +#define bit_AVX512BW0x4000 +#define bit_AVX512VL0x8000 /* Features in %ecx for leaf 7 sub-leaf 0 */ #define bit_PREFTCHWT1 0x0001 #define bit_AVX512VBMI 0x0002 -#define bit_PKU 0x0004 +#define bit_UMIP 0x0004 +#define bit_PKU 0x0008 #define bit_OSPKE0x0010 #define bit_WAITPKG 0x0020 #define bit_AVX512VBMI2 0x0040 @@ -179,18 +188,27 @@ #define bit_VPCLMULQDQ 0x0400 #define bit_AVX512VNNI 0x0800 #define bit_AVX512BITALG 0x1000 +#define bit_TME_EN 0x2000 #define bit_AVX512VPOPCNTDQ 0x4000 +#define bit_LA57 0x0001 #define bit_RDPID0x0040 +#define bit_KL 0x0080 #define bit_CLDEMOTE 0x0200 #define bit_MOVDIRI 0x0800 #define bit_MOVDIR64B0x1000 #define bit_ENQCMD 0x2000 +#define bit_SGX_LC 0x4000 +#define bit_PKS 0x8000 /* Features in %edx for leaf 7 sub-leaf 0 */ #define bit_AVX5124VNNIW 0x0004 #define bit_AVX5124FMAPS 0x0008 +#define bit_FSRM
[PATCH] D114318: [clang] Add missing CPUID feature bit masks
adamdb5 updated this revision to Diff 388751. adamdb5 added a comment. Renamed bit_DEPRFPUCSDS to bit_DEPR_FPU_CSDS Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D114318/new/ https://reviews.llvm.org/D114318 Files: clang/lib/Headers/cpuid.h Index: clang/lib/Headers/cpuid.h === --- clang/lib/Headers/cpuid.h +++ clang/lib/Headers/cpuid.h @@ -85,6 +85,7 @@ #define bit_TM2 0x0100 #define bit_SSSE3 0x0200 #define bit_CNXTID 0x0400 +#define bit_SDBG0x0800 #define bit_FMA 0x1000 #define bit_CMPXCHG16B 0x2000 #define bit_xTPR0x4000 @@ -106,6 +107,7 @@ #define bit_AVX 0x1000 #define bit_F16C0x2000 #define bit_RDRND 0x4000 +#define bit_HYPERVISOR 0x8000 /* Features in %edx for leaf 1 */ #define bit_FPU 0x0001 @@ -141,35 +143,42 @@ #define bit_PBE 0x8000 /* Features in %ebx for leaf 7 sub-leaf 0 */ -#define bit_FSGSBASE0x0001 -#define bit_SGX 0x0004 -#define bit_BMI 0x0008 -#define bit_HLE 0x0010 -#define bit_AVX20x0020 -#define bit_SMEP0x0080 -#define bit_BMI20x0100 -#define bit_ENH_MOVSB 0x0200 -#define bit_INVPCID 0x0400 -#define bit_RTM 0x0800 -#define bit_MPX 0x4000 -#define bit_AVX512F 0x0001 -#define bit_AVX512DQ0x0002 -#define bit_RDSEED 0x0004 -#define bit_ADX 0x0008 -#define bit_AVX512IFMA 0x0020 -#define bit_CLFLUSHOPT 0x0080 -#define bit_CLWB0x0100 -#define bit_AVX512PF0x0400 -#define bit_AVX512ER0x0800 -#define bit_AVX512CD0x1000 -#define bit_SHA 0x2000 -#define bit_AVX512BW0x4000 -#define bit_AVX512VL0x8000 +#define bit_FSGSBASE0x0001 +#define bit_IA32_TSC_ADJUST 0x0002 +#define bit_SGX 0x0004 +#define bit_BMI 0x0008 +#define bit_HLE 0x0010 +#define bit_AVX20x0020 +#define bit_FDP_EXCPTN_ONLY 0x0040 +#define bit_SMEP0x0080 +#define bit_BMI20x0100 +#define bit_ENH_MOVSB 0x0200 +#define bit_INVPCID 0x0400 +#define bit_RTM 0x0800 +#define bit_RDTM0x1000 +#define bit_DEPR_FPU_CSDS 0x2000 +#define bit_MPX 0x4000 +#define bit_RDTA0x8000 +#define bit_AVX512F 0x0001 +#define bit_AVX512DQ0x0002 +#define bit_RDSEED 0x0004 +#define bit_ADX 0x0008 +#define bit_AVX512IFMA 0x0020 +#define bit_CLFLUSHOPT 0x0080 +#define bit_CLWB0x0100 +#define bit_IPT 0x0200 +#define bit_AVX512PF0x0400 +#define bit_AVX512ER0x0800 +#define bit_AVX512CD0x1000 +#define bit_SHA 0x2000 +#define bit_AVX512BW0x4000 +#define bit_AVX512VL0x8000 /* Features in %ecx for leaf 7 sub-leaf 0 */ #define bit_PREFTCHWT1 0x0001 #define bit_AVX512VBMI 0x0002 -#define bit_PKU 0x0004 +#define bit_UMIP 0x0004 +#define bit_PKU 0x0008 #define bit_OSPKE0x0010 #define bit_WAITPKG 0x0020 #define bit_AVX512VBMI2 0x0040 @@ -179,18 +188,27 @@ #define bit_VPCLMULQDQ 0x0400 #define bit_AVX512VNNI 0x0800 #define bit_AVX512BITALG 0x1000 +#define bit_TME_EN 0x2000 #define bit_AVX512VPOPCNTDQ 0x4000 +#define bit_LA57 0x0001 #define bit_RDPID0x0040 +#define bit_KL 0x0080 #define bit_CLDEMOTE 0x0200 #define bit_MOVDIRI 0x0800 #define bit_MOVDIR64B0x1000 #define bit_ENQCMD 0x2000 +#define bit_SGX_LC 0x4000 +#define bit_PKS 0x8000 /* Features in %edx for leaf 7 sub-leaf 0 */ #define bit_AVX5124VNNIW 0x0004 #define bit_AVX5124FMAPS 0x0008 +#define bit_FSRM 0x0010 #define bit_UINTR 0x0020 +#define bit_AVX512VP2INT 0x0100 +#define bit_MD_CLEAR 0x0400 #define bit_SERIALIZE 0x4000 +#define bit_HYBRID0x8000 #define bit_TSXLDTRK 0x0001 #define bit_PCONFIG 0x0004 #define bit_IBT 0x0010 @@ -198,6 +216,12 @@ #define bit_AVX512FP160x0080 #define bit_AMXTILE 0x0100 #define bit_AMXINT8 0x0200 +#define bit_IBRS_IBPB 0x0400 +#define bit_STIBP 0x0800 +#define bit_L1DFLUSH 0x1000 +#define bit_IA32_ARCH_CAP 0x2000 +#define bit_IA32_CORE_CAP 0x4000 +#define bit_SSBD 0x8000 /* Features in %eax for leaf 7 sub-leaf 1 */ #define bit_AVXV
