[clang] [llvm] [LLVM][AMDGPU] Add Intrinsic and Builtin for ds_bpermute_fi_b32 (PR #124616)

2025-01-29 Thread Acim Maravic via cfe-commits 

https://github.com/Acim-Maravic closed 
https://github.com/llvm/llvm-project/pull/124616
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[clang] [llvm] [LLVM][AMDGPU] Add Intrinsic and Builtin for ds_bpermute_fi_b32 (PR #124616)

2025-01-27 Thread Acim Maravic via cfe-commits 

https://github.com/Acim-Maravic created 
https://github.com/llvm/llvm-project/pull/124616

None

>From dea0bd7a2cb5f67599257a7d6ae6d0bb0e8804ab Mon Sep 17 00:00:00 2001
From: Acim Maravic 
Date: Mon, 27 Jan 2025 19:26:03 +0100
Subject: [PATCH] [LLVM][AMDGPU] Add Intrinsic and Builtin for
 ds_bpermute_fi_b32

---
 clang/include/clang/Basic/BuiltinsAMDGPU.def  |   2 +
 .../CodeGenOpenCL/builtins-amdgcn-gfx12.cl|  23 +++
 llvm/include/llvm/IR/IntrinsicsAMDGPU.td  |   6 +
 .../Target/AMDGPU/AMDGPURegisterBankInfo.cpp  |   1 +
 llvm/lib/Target/AMDGPU/DSInstructions.td  |   3 +-
 .../AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll  | 154 ++
 6 files changed, 188 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll

diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def 
b/clang/include/clang/Basic/BuiltinsAMDGPU.def
index 1b29a8e359c205..39e295aced96b2 100644
--- a/clang/include/clang/Basic/BuiltinsAMDGPU.def
+++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def
@@ -504,6 +504,8 @@ TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4i16, 
"V4sV4s*1", "nc", "gf
 TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4f16, "V4hV4h*1", "nc", 
"gfx12-insts,wavefrontsize64")
 TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4bf16, "V4yV4y*1", "nc", 
"gfx12-insts,wavefrontsize64")
 
+TARGET_BUILTIN(__builtin_amdgcn_ds_bpermute_fi_b32, "iii", "nc", "gfx12-insts")
+
 
//===--===//
 // WMMA builtins.
 // Postfix w32 indicates the builtin requires wavefront size of 32.
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl 
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
index 5b5ae419f0a4a9..234ad4fd8cde61 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
@@ -296,3 +296,26 @@ void test_s_buffer_prefetch_data(__amdgpu_buffer_rsrc_t 
rsrc, unsigned int len)
   __builtin_amdgcn_s_buffer_prefetch_data(rsrc, 128, len);
   __builtin_amdgcn_s_buffer_prefetch_data(rsrc, 0, 31);
 }
+
+// CHECK-LABEL: @test_ds_bpermute_fi_b32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[OUT_ADDR:%.*]] = alloca ptr addrspace(1), align 8, 
addrspace(5)
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-NEXT:[[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) 
[[OUT_ADDR]] to ptr
+// CHECK-NEXT:[[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) 
[[A_ADDR]] to ptr
+// CHECK-NEXT:[[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) 
[[B_ADDR]] to ptr
+// CHECK-NEXT:store ptr addrspace(1) [[OUT:%.*]], ptr [[OUT_ADDR_ASCAST]], 
align 8
+// CHECK-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR_ASCAST]], align 4
+// CHECK-NEXT:store i32 [[B:%.*]], ptr [[B_ADDR_ASCAST]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR_ASCAST]], align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load i32, ptr [[B_ADDR_ASCAST]], align 4
+// CHECK-NEXT:[[TMP2:%.*]] = call i32 @llvm.amdgcn.ds.bpermute.fi.b32(i32 
[[TMP0]], i32 [[TMP1]])
+// CHECK-NEXT:[[TMP3:%.*]] = load ptr addrspace(1), ptr 
[[OUT_ADDR_ASCAST]], align 8
+// CHECK-NEXT:store i32 [[TMP2]], ptr addrspace(1) [[TMP3]], align 4
+// CHECK-NEXT:ret void
+//
+void test_ds_bpermute_fi_b32(global int* out, int a, int b)
+{
+  *out = __builtin_amdgcn_ds_bpermute_fi_b32(a, b);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td 
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index cc3584833202bf..f721d5267cd2a0 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2923,6 +2923,12 @@ def int_amdgcn_s_prefetch_data :
 "", [SDNPMemOperand]
   >;
 
+// llvm.amdgcn.ds.bpermute.fi.b32  
+def int_amdgcn_ds_bpermute_fi_b32 :
+  ClangBuiltin<"__builtin_amdgcn_ds_bpermute_fi_b32">,
+  Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+[IntrNoMem, IntrConvergent, IntrWillReturn, IntrNoCallback, IntrNoFree]>;
+
 
//===--===//
 // Deep learning intrinsics.
 
//===--===//
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 224c368cff4a1f..2e5f42c3bdc405 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -4675,6 +4675,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const 
MachineInstr &MI) const {
 case Intrinsic::amdgcn_set_inactive:
 case Intrinsic::amdgcn_set_inactive_chain_arg:
 case Intrinsic::amdgcn_permlane64:
+case Intrinsic::amdgcn_ds_bpermute_fi_b32:
   return getDefaultMappingAllVGPR(MI);
 case Intrinsic::amdgcn_cvt_pkrtz:
   if (Subtarget.hasSALUFloatInsts() && isSALUMapping(MI))
diff --git a/l

[clang] [llvm] [LLVM][AMDGPU] Add Intrinsic and Builtin for ds_bpermute_fi_b32 (PR #124616)

2025-01-28 Thread Acim Maravic via cfe-commits 

https://github.com/Acim-Maravic updated 
https://github.com/llvm/llvm-project/pull/124616

>From c9c461bf868e5f874dc0881d007e88dae7a83d43 Mon Sep 17 00:00:00 2001
From: Acim Maravic 
Date: Tue, 28 Jan 2025 20:42:28 +0100
Subject: [PATCH] [LLVM][AMDGPU] Add Intrinsic and Builtin for
 ds_bpermute_fi_b32

---
 clang/include/clang/Basic/BuiltinsAMDGPU.def  |   2 +
 .../builtins-amdgcn-gfx11-err.cl  |   6 +-
 .../CodeGenOpenCL/builtins-amdgcn-gfx12.cl|  23 +++
 llvm/include/llvm/IR/IntrinsicsAMDGPU.td  |   6 +
 .../Target/AMDGPU/AMDGPURegisterBankInfo.cpp  |   1 +
 llvm/lib/Target/AMDGPU/DSInstructions.td  |   3 +-
 .../AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll  | 154 ++
 llvm/test/MC/AMDGPU/gfx11_unsupported.s   |   3 +
 8 files changed, 194 insertions(+), 4 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.fi.b32.ll

diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def 
b/clang/include/clang/Basic/BuiltinsAMDGPU.def
index 1b29a8e359c205..39e295aced96b2 100644
--- a/clang/include/clang/Basic/BuiltinsAMDGPU.def
+++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def
@@ -504,6 +504,8 @@ TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4i16, 
"V4sV4s*1", "nc", "gf
 TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4f16, "V4hV4h*1", "nc", 
"gfx12-insts,wavefrontsize64")
 TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4bf16, "V4yV4y*1", "nc", 
"gfx12-insts,wavefrontsize64")
 
+TARGET_BUILTIN(__builtin_amdgcn_ds_bpermute_fi_b32, "iii", "nc", "gfx12-insts")
+
 
//===--===//
 // WMMA builtins.
 // Postfix w32 indicates the builtin requires wavefront size of 32.
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11-err.cl 
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11-err.cl
index 08f70a25276f17..d518fe3a11a81c 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11-err.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11-err.cl
@@ -2,7 +2,7 @@
 
 // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1100 -verify 
-emit-llvm -o - %s
 
-void test_s_sleep_var(int d)
-{
-  __builtin_amdgcn_s_sleep_var(d); // expected-error 
{{'__builtin_amdgcn_s_sleep_var' needs target feature gfx12-insts}}
+void builtin_test_unsupported(int a, int b) {
+  __builtin_amdgcn_s_sleep_var(a); // expected-error 
{{'__builtin_amdgcn_s_sleep_var' needs target feature gfx12-insts}}
+  b = __builtin_amdgcn_ds_bpermute_fi_b32(a, b); // expected-error 
{{'__builtin_amdgcn_ds_bpermute_fi_b32' needs target feature gfx12-insts}}
 }
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl 
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
index 5b5ae419f0a4a9..234ad4fd8cde61 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
@@ -296,3 +296,26 @@ void test_s_buffer_prefetch_data(__amdgpu_buffer_rsrc_t 
rsrc, unsigned int len)
   __builtin_amdgcn_s_buffer_prefetch_data(rsrc, 128, len);
   __builtin_amdgcn_s_buffer_prefetch_data(rsrc, 0, 31);
 }
+
+// CHECK-LABEL: @test_ds_bpermute_fi_b32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[OUT_ADDR:%.*]] = alloca ptr addrspace(1), align 8, 
addrspace(5)
+// CHECK-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-NEXT:[[B_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-NEXT:[[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) 
[[OUT_ADDR]] to ptr
+// CHECK-NEXT:[[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) 
[[A_ADDR]] to ptr
+// CHECK-NEXT:[[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) 
[[B_ADDR]] to ptr
+// CHECK-NEXT:store ptr addrspace(1) [[OUT:%.*]], ptr [[OUT_ADDR_ASCAST]], 
align 8
+// CHECK-NEXT:store i32 [[A:%.*]], ptr [[A_ADDR_ASCAST]], align 4
+// CHECK-NEXT:store i32 [[B:%.*]], ptr [[B_ADDR_ASCAST]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load i32, ptr [[A_ADDR_ASCAST]], align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load i32, ptr [[B_ADDR_ASCAST]], align 4
+// CHECK-NEXT:[[TMP2:%.*]] = call i32 @llvm.amdgcn.ds.bpermute.fi.b32(i32 
[[TMP0]], i32 [[TMP1]])
+// CHECK-NEXT:[[TMP3:%.*]] = load ptr addrspace(1), ptr 
[[OUT_ADDR_ASCAST]], align 8
+// CHECK-NEXT:store i32 [[TMP2]], ptr addrspace(1) [[TMP3]], align 4
+// CHECK-NEXT:ret void
+//
+void test_ds_bpermute_fi_b32(global int* out, int a, int b)
+{
+  *out = __builtin_amdgcn_ds_bpermute_fi_b32(a, b);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td 
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index cc3584833202bf..f721d5267cd2a0 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2923,6 +2923,12 @@ def int_amdgcn_s_prefetch_data :
 "", [SDNPMemOperand]
   >;
 
+// llvm.amdgcn.ds.bpermute.fi.b32  
+def int_amdgcn_ds_bpermute_fi_b32 :
+  ClangBuiltin<"__builtin_amdgcn_ds_bpermute_fi_b32">,
+  Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],

[clang] [llvm] [LLVM][AMDGPU] Add Intrinsic and Builtin for ds_bpermute_fi_b32 (PR #124616)

2025-01-28 Thread Acim Maravic via cfe-commits 


@@ -504,6 +504,8 @@ TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4i16, 
"V4sV4s*1", "nc", "gf
 TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4f16, "V4hV4h*1", "nc", 
"gfx12-insts,wavefrontsize64")
 TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4bf16, "V4yV4y*1", "nc", 
"gfx12-insts,wavefrontsize64")
 
+TARGET_BUILTIN(__builtin_amdgcn_ds_bpermute_fi_b32, "iii", "nc", "gfx12-insts")

Acim-Maravic wrote:

Added.

https://github.com/llvm/llvm-project/pull/124616
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[clang] [llvm] [LLVM][AMDGPU] Add Intrinsic and Builtin for ds_bpermute_fi_b32 (PR #124616)

2025-01-28 Thread Acim Maravic via cfe-commits 


@@ -699,7 +699,8 @@ def DS_PERMUTE_B32  : DS_1A1D_PERMUTE <"ds_permute_b32",
int_amdgcn_ds_permute>;
 def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
int_amdgcn_ds_bpermute>;
-def DS_BPERMUTE_FI_B32 : DS_1A1D_PERMUTE <"ds_bpermute_fi_b32">;
+def DS_BPERMUTE_FI_B32 : DS_1A1D_PERMUTE <"ds_bpermute_fi_b32",

Acim-Maravic wrote:

Yes, I overlooked that... Updated.

https://github.com/llvm/llvm-project/pull/124616
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[clang] [llvm] [LLVM] Add intrinsics for v_cvt_pk_norm_{i16, u16}_f16 (PR #135631)

2025-04-14 Thread Acim Maravic via cfe-commits 

https://github.com/Acim-Maravic created 
https://github.com/llvm/llvm-project/pull/135631

Added builtin and intrinsic for v_cvt_pk_norm_i16_f16 and v_cvt_pk_norm_u16_f16

>From 86976f24c00ae6471c95edf21e4d55b35682 Mon Sep 17 00:00:00 2001
From: Acim Maravic 
Date: Mon, 14 Apr 2025 16:29:11 +0200
Subject: [PATCH] [LLVM] Add intrinsics for v_cvt_pk_norm_{i16,u16}_f16

Added builtin and intrinsic for v_cvt_pk_norm_i16_f16 and
v_cvt_pk_norm_u16_f16
---
 clang/include/clang/Basic/BuiltinsAMDGPU.def  |   3 +
 .../CodeGenOpenCL/builtins-amdgcn-gfx9.cl |  16 +++
 llvm/include/llvm/IR/IntrinsicsAMDGPU.td  |  12 ++
 .../Target/AMDGPU/AMDGPURegisterBankInfo.cpp  |   2 +
 llvm/lib/Target/AMDGPU/SIInstrInfo.td |   1 +
 llvm/lib/Target/AMDGPU/VOP3Instructions.td|   7 +-
 .../AMDGPU/llvm.amdgcn.cvt.pk.norm.i16.f16.ll | 124 ++
 .../AMDGPU/llvm.amdgcn.cvt.pk.norm.u16.f16.ll | 124 ++
 8 files changed, 287 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.norm.i16.f16.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.norm.u16.f16.ll

diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def 
b/clang/include/clang/Basic/BuiltinsAMDGPU.def
index 39fef9e4601f8..0f3789d282304 100644
--- a/clang/include/clang/Basic/BuiltinsAMDGPU.def
+++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def
@@ -259,6 +259,9 @@ TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2bf16, 
"V2sV2s*3V2s", "t", "atom
 TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2f16, "V2hV2h*3V2h", "t", 
"atomic-ds-pk-add-16-insts")
 TARGET_BUILTIN(__builtin_amdgcn_global_load_lds, "vv*1v*3IUiIiIUi", "t", 
"vmem-to-lds-load-insts")
 
+TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_norm_i16_f16, "V2sxx", "nc", 
"gfx9-insts")
+TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_norm_u16_f16, "V2Usxx", "nc", 
"gfx9-insts")
+
 
//===--===//
 // Deep learning builtins.
 
//===--===//
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx9.cl 
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx9.cl
index 87f2da20a21a6..06417a693d303 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx9.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx9.cl
@@ -5,6 +5,8 @@
 #pragma OPENCL EXTENSION cl_khr_fp16 : enable
 typedef unsigned int uint;
 typedef unsigned long ulong;
+typedef short __attribute__((ext_vector_type(2))) short2;
+typedef unsigned short __attribute__((ext_vector_type(2))) ushort2;
 
 // CHECK-LABEL: @test_fmed3_f16
 // CHECK: call half @llvm.amdgcn.fmed3.f16(half %a, half %b, half %c)
@@ -26,3 +28,17 @@ void test_groupstaticsize(global uint* out)
 {
   *out = __builtin_amdgcn_groupstaticsize();
 }
+
+// CHECK-LABEL: define dso_local void @test_cvt_pk_norm_i16_f16(
+// CHECK: call <2 x i16> @llvm.amdgcn.cvt.pk.norm.i16.f16(half %src0, half 
%src1)
+void test_cvt_pk_norm_i16_f16(global short2* out, half src0, half src1)
+{
+  *out = __builtin_amdgcn_cvt_pk_norm_i16_f16(src0, src1);
+}
+
+// CHECK-LABEL: define dso_local void @test_cvt_pk_norm_u16_f16(
+// CHECK: call <2 x i16> @llvm.amdgcn.cvt.pk.norm.u16.f16(half %src0, half 
%src1)
+void test_cvt_pk_norm_u16_f16(global ushort2* out, half src0, half src1)
+{
+  *out = __builtin_amdgcn_cvt_pk_norm_u16_f16(src0, src1);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td 
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 217e43fcce4fd..60904e9202238 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2644,6 +2644,18 @@ def int_amdgcn_global_load_lds : AMDGPUGlobalLoadLDS;
 def int_amdgcn_pops_exiting_wave_id :
   DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrHasSideEffects]>;
 
+def int_amdgcn_cvt_pk_norm_i16_f16 :
+  ClangBuiltin<"__builtin_amdgcn_cvt_pk_norm_i16_f16">,
+  DefaultAttrsIntrinsic<[llvm_v2i16_ty], [llvm_half_ty, llvm_half_ty],
+[IntrNoMem, IntrSpeculatable]
+>;
+
+def int_amdgcn_cvt_pk_norm_u16_f16 :
+  ClangBuiltin<"__builtin_amdgcn_cvt_pk_norm_u16_f16">,
+  DefaultAttrsIntrinsic<[llvm_v2i16_ty], [llvm_half_ty, llvm_half_ty],
+[IntrNoMem, IntrSpeculatable]
+>;
+
 
//===--===//
 // GFX10 Intrinsics
 
//===--===//
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 1d0e81db5a5db..8d35721d6df8f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -4669,6 +4669,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const 
MachineInstr &MI) const {
 case Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8:
 case Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8:
 case Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8:
+case Intrinsic:

[clang] [llvm] [LLVM] Add intrinsics for v_cvt_pk_norm_{i16, u16}_f16 (PR #135631)

2025-04-17 Thread Acim Maravic via cfe-commits 

https://github.com/Acim-Maravic updated 
https://github.com/llvm/llvm-project/pull/135631

>From df4b39ea8558dcf18a0e6c2947c5f33eb356e77f Mon Sep 17 00:00:00 2001
From: Acim Maravic 
Date: Mon, 14 Apr 2025 16:29:11 +0200
Subject: [PATCH] [LLVM] Add intrinsics for v_cvt_pk_norm_{i16,u16}_f16

Added builtin and intrinsic for v_cvt_pk_norm_i16_f16 and
v_cvt_pk_norm_u16_f16
---
 clang/include/clang/Basic/BuiltinsAMDGPU.def  |   3 +
 .../CodeGenOpenCL/builtins-amdgcn-gfx9.cl |  16 +++
 llvm/include/llvm/IR/IntrinsicsAMDGPU.td  |  12 ++
 .../Target/AMDGPU/AMDGPURegisterBankInfo.cpp  |   2 +
 llvm/lib/Target/AMDGPU/SIInstrInfo.td |   1 +
 llvm/lib/Target/AMDGPU/VOP3Instructions.td|   7 +-
 .../AMDGPU/llvm.amdgcn.cvt.pk.norm.i16.f16.ll | 124 ++
 .../AMDGPU/llvm.amdgcn.cvt.pk.norm.u16.f16.ll | 124 ++
 8 files changed, 287 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.norm.i16.f16.ll
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.norm.u16.f16.ll

diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def 
b/clang/include/clang/Basic/BuiltinsAMDGPU.def
index 39fef9e4601f8..0f3789d282304 100644
--- a/clang/include/clang/Basic/BuiltinsAMDGPU.def
+++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def
@@ -259,6 +259,9 @@ TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2bf16, 
"V2sV2s*3V2s", "t", "atom
 TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2f16, "V2hV2h*3V2h", "t", 
"atomic-ds-pk-add-16-insts")
 TARGET_BUILTIN(__builtin_amdgcn_global_load_lds, "vv*1v*3IUiIiIUi", "t", 
"vmem-to-lds-load-insts")
 
+TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_norm_i16_f16, "V2sxx", "nc", 
"gfx9-insts")
+TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_norm_u16_f16, "V2Usxx", "nc", 
"gfx9-insts")
+
 
//===--===//
 // Deep learning builtins.
 
//===--===//
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx9.cl 
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx9.cl
index 87f2da20a21a6..06417a693d303 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx9.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx9.cl
@@ -5,6 +5,8 @@
 #pragma OPENCL EXTENSION cl_khr_fp16 : enable
 typedef unsigned int uint;
 typedef unsigned long ulong;
+typedef short __attribute__((ext_vector_type(2))) short2;
+typedef unsigned short __attribute__((ext_vector_type(2))) ushort2;
 
 // CHECK-LABEL: @test_fmed3_f16
 // CHECK: call half @llvm.amdgcn.fmed3.f16(half %a, half %b, half %c)
@@ -26,3 +28,17 @@ void test_groupstaticsize(global uint* out)
 {
   *out = __builtin_amdgcn_groupstaticsize();
 }
+
+// CHECK-LABEL: define dso_local void @test_cvt_pk_norm_i16_f16(
+// CHECK: call <2 x i16> @llvm.amdgcn.cvt.pk.norm.i16.f16(half %src0, half 
%src1)
+void test_cvt_pk_norm_i16_f16(global short2* out, half src0, half src1)
+{
+  *out = __builtin_amdgcn_cvt_pk_norm_i16_f16(src0, src1);
+}
+
+// CHECK-LABEL: define dso_local void @test_cvt_pk_norm_u16_f16(
+// CHECK: call <2 x i16> @llvm.amdgcn.cvt.pk.norm.u16.f16(half %src0, half 
%src1)
+void test_cvt_pk_norm_u16_f16(global ushort2* out, half src0, half src1)
+{
+  *out = __builtin_amdgcn_cvt_pk_norm_u16_f16(src0, src1);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td 
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 217e43fcce4fd..60904e9202238 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2644,6 +2644,18 @@ def int_amdgcn_global_load_lds : AMDGPUGlobalLoadLDS;
 def int_amdgcn_pops_exiting_wave_id :
   DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrHasSideEffects]>;
 
+def int_amdgcn_cvt_pk_norm_i16_f16 :
+  ClangBuiltin<"__builtin_amdgcn_cvt_pk_norm_i16_f16">,
+  DefaultAttrsIntrinsic<[llvm_v2i16_ty], [llvm_half_ty, llvm_half_ty],
+[IntrNoMem, IntrSpeculatable]
+>;
+
+def int_amdgcn_cvt_pk_norm_u16_f16 :
+  ClangBuiltin<"__builtin_amdgcn_cvt_pk_norm_u16_f16">,
+  DefaultAttrsIntrinsic<[llvm_v2i16_ty], [llvm_half_ty, llvm_half_ty],
+[IntrNoMem, IntrSpeculatable]
+>;
+
 
//===--===//
 // GFX10 Intrinsics
 
//===--===//
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 1d0e81db5a5db..8d35721d6df8f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -4669,6 +4669,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const 
MachineInstr &MI) const {
 case Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8:
 case Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8:
 case Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8:
+case Intrinsic::amdgcn_cvt_pk_norm_i16_f16:
+case Intrinsic::amdgcn_cvt_pk_norm_u16_f16:

[clang] [llvm] [LLVM] Add intrinsics for v_cvt_pk_norm_{i16, u16}_f16 (PR #135631)

2025-04-15 Thread Acim Maravic via cfe-commits 

Acim-Maravic wrote:

> Check code formatting job is failing in a weird way. I can't work out what 
> the issue is.

I have checked locally, and it seems that the whole AMDGPURegisterBankInfo.cpp 
is not clang-formatted... But my change did not introduce any new formatting 
issues... How should I procced? 

https://github.com/llvm/llvm-project/pull/135631
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