date:20231208

[lldb] [clang] fixing issue #64441 (PR #74814)

2023-12-08 Thread Michael Buch via cfe-commits



@@ -56,10 +56,10 @@ namespace Foo = A::B;   // namespace alias
 
 using Foo::myfunc;  // using declaration
 
-using namespace Foo;// using directive
+//removing namespace foo; for quality naming 

Michael137 wrote:

The `using` directive was used here to make sure LLDB does the right thing when 
doing qualified lookup in the presence of various `DW_TAG_imported_module` and 
name shadowing. I don't think we should change this because it risks subtly 
changing the test coverage.

https://github.com/llvm/llvm-project/pull/74814
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[compiler-rt] [clang-tools-extra] [clang] [llvm] [PGO][GlobalValue][LTO]In GlobalValues::getGlobalIdentifier, use semicolon as delimiter for local-linkage varibles. (PR #74008)

2023-12-08 Thread Mingming Liu via cfe-commits

minglotus-6 wrote:

> . For IR PGO, there is basically no need to do so as the instrumentation and 
> profile-use should be in-sync. For front-end instrumentation, there seem to 
> be some use cases to use out of sync profile: https://reviews.llvm.org/D51240.

Thanks for double checking. I noticed the ICP and stale profile tolerance 
discussions when read the Phab history; it's good Phab review history are still 
available nowadays.

IRPGO profiles could be used along with supplementary sample-pgo profiles. I'll 
probably read relevant code in llvm-profdata to understand how these interact 
in theory mostly for my own curiosity (hopefully no rough edges as long as  
`llvm-profdata` uses the same pgo name format used by latest compiler)

https://github.com/llvm/llvm-project/pull/74008
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[clang] [clang][NFC] Refactor expected directives in C++ DRs 700-1999 (PR #74767)

2023-12-08 Thread Vlad Serebrennikov via cfe-commits


https://github.com/Endilll closed 
https://github.com/llvm/llvm-project/pull/74767
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[clang] [llvm] [Sema] Implement support for -Wformat-signedness (PR #74440)

2023-12-08 Thread Karl-Johan Karlsson via cfe-commits


https://github.com/karka228 updated 
https://github.com/llvm/llvm-project/pull/74440

>From a80bf9d03f19d48c0aca4af7758dc49516da8825 Mon Sep 17 00:00:00 2001
From: Karl-Johan Karlsson 
Date: Tue, 5 Dec 2023 10:03:00 +0100
Subject: [PATCH 1/4] [Sema] Implement support for -Wformat-signedness

In gcc there exist a modifier option -Wformat-signedness that turns on
additional signedness warnings in the already existing -Wformat warning.

This patch implements that support in clang.
---
 clang/include/clang/AST/FormatString.h|   2 +
 .../include/clang/Basic/DiagnosticOptions.def |   1 +
 clang/include/clang/Driver/Options.td |   3 +
 clang/lib/AST/FormatString.cpp|  29 +++--
 clang/lib/Driver/ToolChains/Clang.cpp |   2 +
 clang/lib/Sema/SemaChecking.cpp   |  26 -
 format-strings-signedness.c   | 107 ++
 7 files changed, 158 insertions(+), 12 deletions(-)
 create mode 100644 format-strings-signedness.c

diff --git a/clang/include/clang/AST/FormatString.h 
b/clang/include/clang/AST/FormatString.h
index 5c4ad9baaef60..c267a32be4d6f 100644
--- a/clang/include/clang/AST/FormatString.h
+++ b/clang/include/clang/AST/FormatString.h
@@ -264,6 +264,8 @@ class ArgType {
 /// The conversion specifier and the argument type are compatible. For
 /// instance, "%d" and int.
 Match = 1,
+/// The conversion specifier and the argument type have different sign
+MatchSignedness,
 /// The conversion specifier and the argument type are compatible because 
of
 /// default argument promotions. For instance, "%hhd" and int.
 MatchPromotion,
diff --git a/clang/include/clang/Basic/DiagnosticOptions.def 
b/clang/include/clang/Basic/DiagnosticOptions.def
index 6d0c1b14acc12..a9562e7d8dcb0 100644
--- a/clang/include/clang/Basic/DiagnosticOptions.def
+++ b/clang/include/clang/Basic/DiagnosticOptions.def
@@ -44,6 +44,7 @@ DIAGOPT(Name, Bits, Default)
 #endif
 
 SEMANTIC_DIAGOPT(IgnoreWarnings, 1, 0)   /// -w
+DIAGOPT(FormatSignedness, 1, 0) /// -Wformat-signedness
 DIAGOPT(NoRewriteMacros, 1, 0)  /// -Wno-rewrite-macros
 DIAGOPT(Pedantic, 1, 0) /// -pedantic
 DIAGOPT(PedanticErrors, 1, 0)   /// -pedantic-errors
diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 1d04e4f6e7e6d..04fdf9a7eb92d 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -918,6 +918,9 @@ def Wdeprecated : Flag<["-"], "Wdeprecated">, 
Group,
   HelpText<"Enable warnings for deprecated constructs and define 
__DEPRECATED">;
 def Wno_deprecated : Flag<["-"], "Wno-deprecated">, Group,
   Visibility<[ClangOption, CC1Option]>;
+def Wformat_signedness : Flag<["-"], "Wformat-signedness">,
+  Flags<[HelpHidden]>, Visibility<[ClangOption, CC1Option]>,
+  MarshallingInfoFlag>;
 def Wl_COMMA : CommaJoined<["-"], "Wl,">, Visibility<[ClangOption, 
FlangOption]>,
   Flags<[LinkerInput, RenderAsInput]>,
   HelpText<"Pass the comma separated arguments in  to the linker">,
diff --git a/clang/lib/AST/FormatString.cpp b/clang/lib/AST/FormatString.cpp
index e0c9e18cfe3a2..670cde017d3ac 100644
--- a/clang/lib/AST/FormatString.cpp
+++ b/clang/lib/AST/FormatString.cpp
@@ -409,7 +409,7 @@ ArgType::matchesType(ASTContext &C, QualType argTy) const {
 return Match;
   if (const auto *BT = argTy->getAs()) {
 // Check if the only difference between them is signed vs unsigned
-// if true, we consider they are compatible.
+// if true, return match signedness.
 switch (BT->getKind()) {
   default:
 break;
@@ -419,44 +419,53 @@ ArgType::matchesType(ASTContext &C, QualType argTy) const 
{
 [[fallthrough]];
   case BuiltinType::Char_S:
   case BuiltinType::SChar:
+if (T == C.UnsignedShortTy || T == C.ShortTy)
+  return NoMatchTypeConfusion;
+if (T == C.UnsignedCharTy)
+  return MatchSignedness;
+if (T == C.SignedCharTy)
+  return Match;
+break;
   case BuiltinType::Char_U:
   case BuiltinType::UChar:
 if (T == C.UnsignedShortTy || T == C.ShortTy)
   return NoMatchTypeConfusion;
-if (T == C.UnsignedCharTy || T == C.SignedCharTy)
+if (T == C.UnsignedCharTy)
   return Match;
+if (T == C.SignedCharTy)
+  return MatchSignedness;
 break;
   case BuiltinType::Short:
 if (T == C.UnsignedShortTy)
-  return Match;
+  return MatchSignedness;
 break;
   case BuiltinType::UShort:
 if (T == C.ShortTy)
-  return Match;
+  return MatchSignedness;
 break;
   case BuiltinType::Int:
 if (T == C.UnsignedIntTy)
-  return Match;
+  return MatchSignedness;
 break;

[mlir] [clang] [llvm] [AMDGPU] - Add address space for strided buffers (PR #74471)

2023-12-08 Thread Jessica Del via cfe-commits


https://github.com/OutOfCache updated 
https://github.com/llvm/llvm-project/pull/74471

>From 94ed734c0d8864a08e3b77600dda811040270bd9 Mon Sep 17 00:00:00 2001
From: Jessica Del 
Date: Tue, 5 Dec 2023 13:45:58 +0100
Subject: [PATCH 1/5] [AMDGPU] - Add address space for strided buffers

This is an experimental address space for strided buffers.
These buffers can have structs as elements and
a stride > 1.
These pointers allow the indexed access in units of stride,
i.e., they point at `buffer[index * stride]`.
Thus, we can use the `idxen` modifier for buffer loads.

We assign address space 9 to 192-bit buffer pointers which
contain a 128-bit descriptor, a 32-bit offset and a 32-bit
index. Essentially, they are fat buffer pointers with
an additional 32-bit index.
---
 llvm/docs/AMDGPUUsage.rst | 48 -
 llvm/lib/Target/AMDGPU/AMDGPU.h   | 32 +
 .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp |  7 +-
 .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp |  2 +-
 .../AMDGPU/AMDGPUTargetTransformInfo.cpp  |  3 +-
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 13 +++-
 .../CodeGen/AMDGPU/amdgpu-alias-analysis.ll   | 70 +++
 .../AMDGPU/vectorize-buffer-fat-pointer.ll| 19 -
 8 files changed, 154 insertions(+), 40 deletions(-)

diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 7fb3d70bbeffeb..ff45efac7e8486 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -703,23 +703,24 @@ supported for the ``amdgcn`` target.
   .. table:: AMDGPU Address Spaces
  :name: amdgpu-address-spaces-table
 
- = === === 
 === 
- ..
 64-Bit Process Address Space
- - --- --- 
 
- Address Space NameLLVM IR Address HSA Segment Hardware
 Address NULL Value
-   Space NumberNameName
 Size
- = === === 
 === 
- Generic   0   flatflat
 64  0x
- Global1   global  global  
 64  0x
- Region2   N/A GDS 
 32  *not implemented for AMDHSA*
- Local 3   group   LDS 
 32  0x
- Constant  4   constant*same as 
global* 64  0x
- Private   5   private scratch 
 32  0x
- Constant 32-bit   6   *TODO*  
 0x
- Buffer Fat Pointer (experimental) 7   *TODO*
- Buffer Resource (experimental)8   *TODO*
- Streamout Registers   128 N/A GS_REGS
- = === === 
 === 
+ = === === 
 === 
+ ..
 64-Bit Process Address Space
+ - --- --- 
 
+ Address Space NameLLVM IR Address HSA Segment 
Hardware Address NULL Value
+   Space NumberNameName
 Size
+ = === === 
 === 
+ Generic   0   flatflat
 64  0x
+ Global1   global  global  
 64  0x
+ Region2   N/A GDS 
 32  *not implemented for AMDHSA*
+ Local 3   group   LDS 
 32  0x
+ Constant  4   constant*same 
as global* 64  0x
+ Private   5   private scratch 
 32  0x
+ Constant 32-bit   6   *TODO*  
 0x
+ Buffer Fat Pointer (experimental) 7   *TODO*
+

[lldb] [clang] fixing issue #64441 (PR #74814)

2023-12-08 Thread Jeevan Ghimire via cfe-commits



@@ -56,10 +56,10 @@ namespace Foo = A::B;   // namespace alias
 
 using Foo::myfunc;  // using declaration
 
-using namespace Foo;// using directive
+//removing namespace foo; for quality naming 

jeevanghimire wrote:

but it can create confusion if we just name the qualified lookup with standard 
naming it will make more sense

https://github.com/llvm/llvm-project/pull/74814
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[libunwind] [libunwind] Replace process_vm_readv with pipe (PR #74791)

2023-12-08 Thread Jordan R AW via cfe-commits



@@ -2822,13 +2825,18 @@ bool UnwindCursor::setInfoForSigReturn(Registers_s390x &) {
   // onto the stack.
   const pint_t pc = static_cast(this->getReg(UNW_REG_IP));
   // The PC might contain an invalid address if the unwind info is bad, so
-  // directly accessing it could cause a segfault. Use process_vm_readv to
+  // directly accessing it could cause a segfault. Use pipe/write/read to
   // read the memory safely instead.
   uint16_t inst;

ajordanr-google wrote:

Should be removed, since we redefined this lower down on line 2834.

https://github.com/llvm/llvm-project/pull/74791
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[clang] [Clang][SVE2p1]Add svboolx2 and svboolx4 types for svcreate, svget, s… (PR #74594)

2023-12-08 Thread via cfe-commits



@@ -1316,6 +1321,13 @@ def SVSET_3_BF16 : SInst<"svset3[_{d}]", "33id", "b", 
MergeNone, "", [IsTupleSet
 def SVSET_4_BF16 : SInst<"svset4[_{d}]", "44id", "b", MergeNone, "", 
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
 }
 
+let TargetGuard = "sve2p1" in {
+  def SVGET_2_B : SInst<"svget2[_{d}]", "d2i", "Pc", MergeNone, "", 
[IsTupleGet], [ImmCheck<1, ImmCheck0_1>]>;
+  def SVGET_4_B : SInst<"svget4[_{d}]", "d4i", "Pc", MergeNone, "", 
[IsTupleGet], [ImmCheck<1, ImmCheck0_3>]>;
+
+  def SVSET_2_B : SInst<"svset2[_{d}]", "22id", "Pc", MergeNone, "", 
[IsTupleSet], [ImmCheck<1, ImmCheck0_1>]>;
+  def SVSET_4_B : SInst<"svset4[_{d}]", "44id", "Pc", MergeNone, "", 
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
+}
 


CarolineConcatto wrote:

I thought we only needed that for when it is under streaming mode, with sme. 

https://github.com/llvm/llvm-project/pull/74594
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sander de Smalen via cfe-commits



@@ -3168,11 +3168,70 @@ static void checkArmStreamingBuiltin(Sema &S, CallExpr 
*TheCall,
 << TheCall->getSourceRange() << "streaming compatible";
 return;
   }
+
+  if (FnType == ArmNonStreaming && BuiltinType == ArmStreaming) {
+S.Diag(TheCall->getBeginLoc(), 
diag::warn_attribute_arm_sm_incompat_builtin)
+<< TheCall->getSourceRange() << "non-streaming";
+  }
+}

sdesmalen-arm wrote:

I think this functionality is big enough to warrant it own PR, such that we 
have:
* One PR for testing the compatibility of streaming-mode for both SVE and SME.
* One PR for testing that the calling function of a ZA-using builtin has ZA 
state.

https://github.com/llvm/llvm-project/pull/74064
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sander de Smalen via cfe-commits



@@ -1375,6 +1381,12 @@ void SVEEmitter::createHeader(raw_ostream &OS) {
   OS << "#define __aio static __inline__ __attribute__((__always_inline__, "
 "__nodebug__, __overloadable__))\n\n";
 
+  OS << "#ifdef __ARM_FEATURE_SME\n";
+  OS << "#define __asc __attribute__((arm_streaming_compatible))\n";

sdesmalen-arm wrote:

A few things:
* The `__attribute__((arm_streaming_compatible))` syntax is not supported.
* `__asc` is not used/emitted anywhere
* I'm not sure adding the attribute to the function prototype in the header 
file adds much value anyway. Better to just omit it.


https://github.com/llvm/llvm-project/pull/74064
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sander de Smalen via cfe-commits



@@ -20,3 +21,23 @@ int16x8_t incompat_neon_smc(int16x8_t splat) 
__arm_streaming_compatible {
   // expected-warning@+1 {{builtin call has undefined behaviour when called 
from a streaming compatible function}}
   return (int16x8_t)__builtin_neon_vqaddq_v((int8x16_t)splat, 
(int8x16_t)splat, 33);
 }
+
+void incompat_sme_norm(svbool_t pg, void const *ptr) __arm_shared_za {
+  // expected-warning@+1 {{builtin call has undefined behaviour when called 
from a non-streaming function}}
+  return __builtin_sme_svld1_hor_za128(0, 0, pg, ptr);

sdesmalen-arm wrote:

nit: returning a `void` value from a `void` function doesn't seem right.

Also, is `incompat_sme_norm` testing anything that `incompat_sme_sm` isn't 
testing?

Or should this be a test where we'd call a non-streaming SVE/SME builtin from a 
streaming-function?

https://github.com/llvm/llvm-project/pull/74064
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sander de Smalen via cfe-commits



@@ -500,6 +506,12 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper 
&Records) {
   case GenArmSmeRangeChecks:
 EmitSmeRangeChecks(Records, OS);
 break;
+  case GenArmSmeStreamingAttrs:

sdesmalen-arm wrote:

We also need to do this for SVE (you seem to have added the logic for it in 
SveEmitter.cpp, but are not using it otherwise).

https://github.com/llvm/llvm-project/pull/74064
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sander de Smalen via cfe-commits



@@ -3058,6 +3058,11 @@ bool Sema::ParseSVEImmChecks(
   if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1, 7))
 HasError = true;
   break;
+case SVETypeFlags::ImmCheck2_4_Mul2:

sdesmalen-arm wrote:

This shouldn't have moved.

https://github.com/llvm/llvm-project/pull/74064
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sander de Smalen via cfe-commits



@@ -6,20 +6,21 @@
 #include 
 
 __attribute__((target("sme")))
-void test_sme(svbool_t pg, void *ptr) {
+void test_sme(svbool_t pg, void *ptr) __arm_streaming __arm_shared_za {
   svld1_hor_za8(0, 0, pg, ptr);
 }
 
 __attribute__((target("arch=armv8-a+sme")))
-void test_arch_sme(svbool_t pg, void *ptr) {
+void test_arch_sme(svbool_t pg, void *ptr) __arm_streaming __arm_shared_za {
   svld1_hor_vnum_za32(0, 0, pg, ptr, 0);
 }
 
 __attribute__((target("+sme")))
-void test_plus_sme(svbool_t pg, void *ptr) {
+void test_plus_sme(svbool_t pg, void *ptr) __arm_streaming __arm_shared_za {
   svst1_ver_za16(0, 0, pg, ptr);
 }
 
-void undefined(svbool_t pg, void *ptr) {
-  svst1_ver_vnum_za64(0, 0, pg, ptr, 0); // expected-error 
{{'svst1_ver_vnum_za64' needs target feature sme}}
+__attribute__((target("+sme")))
+void undefined(svbool_t pg, void *ptr) __arm_shared_za {
+  svst1_ver_vnum_za64(0, 0, pg, ptr, 0); // expected-warning {{builtin call 
has undefined behaviour when called from a non-streaming function}}

sdesmalen-arm wrote:

This test should not have changed.

https://github.com/llvm/llvm-project/pull/74064
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sander de Smalen via cfe-commits



@@ -18,7 +18,7 @@
 // CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.zero(i32 0)
 // CHECK-CXX-NEXT:ret void
 //
-void test_svzero_mask_za() {
+__arm_new_za void test_svzero_mask_za() {

sdesmalen-arm wrote:

Why are these `__arm_new_za` rather than `__arm_shared_za`?

https://github.com/llvm/llvm-project/pull/74064
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sander de Smalen via cfe-commits



@@ -3168,11 +3168,70 @@ static void checkArmStreamingBuiltin(Sema &S, CallExpr 
*TheCall,
 << TheCall->getSourceRange() << "streaming compatible";
 return;
   }
+
+  if (FnType == ArmNonStreaming && BuiltinType == ArmStreaming) {
+S.Diag(TheCall->getBeginLoc(), 
diag::warn_attribute_arm_sm_incompat_builtin)
+<< TheCall->getSourceRange() << "non-streaming";
+  }
+}
+
+static bool hasSMEZAState(const FunctionDecl *FD) {
+  if (FD->hasAttr())
+return true;
+  if (const auto *T = FD->getType()->getAs())
+if (T->getAArch64SMEAttributes() & FunctionType::SME_PStateZASharedMask)
+  return true;
+  return false;
+}
+
+static bool hasSMEZAState(unsigned BuiltinID) {
+  switch (BuiltinID) {
+  default:
+return false;
+#define GET_SME_BUILTIN_HAS_ZA_STATE
+#include "clang/Basic/arm_sme_builtins_za_state.inc"
+#undef GET_SME_BUILTIN_HAS_ZA_STATE
+  }
+}
+
+bool Sema::CheckSMEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
+  if (const FunctionDecl *FD = getCurFunctionDecl()) {
+std::optional BuiltinType;

sdesmalen-arm wrote:

Why is this `std::optional` rather than `ArmStreamingType` ?
We could just set the `default:` case below to be `ArmNonStreaming`.

https://github.com/llvm/llvm-project/pull/74064
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[llvm] [clang] [AMDGPU] Improve selection of ballot.i64 intrinsic in wave32 mode. (PR #71556)

2023-12-08 Thread Valery Pykhtin via cfe-commits


https://github.com/vpykhtin updated 
https://github.com/llvm/llvm-project/pull/71556

>From b6204d32554f082821da100043bf872b62f1740b Mon Sep 17 00:00:00 2001
From: Valery Pykhtin 
Date: Mon, 20 Nov 2023 15:22:16 +0100
Subject: [PATCH] add instcombine rule

---
 clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl  |  8 ++--
 llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp   |  2 +-
 .../Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp| 13 +
 .../InstCombine/AMDGPU/amdgcn-intrinsics.ll |  6 --
 4 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl 
b/clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
index 43553131f63c5..a0e27ce22fe7d 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
@@ -24,13 +24,11 @@ void test_ballot_wave32_target_attr(global uint* out, int 
a, int b)
 }
 
 // CHECK-LABEL: @test_read_exec(
-// CHECK: call i64 @llvm.amdgcn.ballot.i64(i1 true)
+// CHECK: call i32 @llvm.amdgcn.ballot.i32(i1 true)
 void test_read_exec(global uint* out) {
   *out = __builtin_amdgcn_read_exec();
 }
 
-// CHECK: declare i64 @llvm.amdgcn.ballot.i64(i1) 
#[[$NOUNWIND_READONLY:[0-9]+]]
-
 // CHECK-LABEL: @test_read_exec_lo(
 // CHECK: call i32 @llvm.amdgcn.ballot.i32(i1 true)
 void test_read_exec_lo(global uint* out) {
@@ -38,9 +36,7 @@ void test_read_exec_lo(global uint* out) {
 }
 
 // CHECK-LABEL: @test_read_exec_hi(
-// CHECK: call i64 @llvm.amdgcn.ballot.i64(i1 true)
-// CHECK: lshr i64 [[A:%.*]], 32
-// CHECK: trunc i64 [[B:%.*]] to i32
+// CHECK: store i32 0, ptr addrspace(1) %out
 void test_read_exec_hi(global uint* out) {
   *out = __builtin_amdgcn_read_exec_hi();
 }
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index a6d1da94b8907..f71f257ae8184 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -2371,7 +2371,7 @@ void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
 auto CC = cast(Cond->getOperand(2))->get();
 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
 isNullConstant(Cond->getOperand(1)) &&
-// TODO: make condition below an assert after fixing ballot bitwidth.
+// We may encounter ballot.i64 in wave32 mode on -O0.
 VCMP.getValueType().getSizeInBits() == ST->getWavefrontSize()) {
   // %VCMP = i(WaveSize) AMDGPUISD::SETCC ...
   // %C = i1 ISD::SETCC %VCMP, 0, setne/seteq
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
index 5296415ab4c36..11022d01bbbf4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
@@ -961,6 +961,19 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, 
IntrinsicInst &II) const {
 return IC.replaceInstUsesWith(II, 
Constant::getNullValue(II.getType()));
   }
 }
+if (ST->isWave32() && II.getType()->getIntegerBitWidth() == 64) {
+  // %b64 = call i64 ballot.i64(...)
+  // =>
+  // %b32 = call i32 ballot.i32(...)
+  // %b64 = zext i32 %b32 to i64
+  Value *Call = IC.Builder.CreateZExtOrBitCast(
+  IC.Builder.CreateIntrinsic(Intrinsic::amdgcn_ballot,
+ {IC.Builder.getInt32Ty()},
+ {II.getArgOperand(0)}),
+  II.getType());
+  Call->takeName(&II);
+  return IC.replaceInstUsesWith(II, Call);
+}
 break;
   }
   case Intrinsic::amdgcn_wqm_vote: {
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll 
b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
index 804283cc20cd6..94c32e3cbe99f 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
@@ -2599,7 +2599,8 @@ declare i32 @llvm.amdgcn.ballot.i32(i1) nounwind readnone 
convergent
 
 define i64 @ballot_nocombine_64(i1 %i) {
 ; CHECK-LABEL: @ballot_nocombine_64(
-; CHECK-NEXT:[[B:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[I:%.*]])
+; CHECK-NEXT:[[TMP1:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[I:%.*]])
+; CHECK-NEXT:[[B:%.*]] = zext i32 [[TMP1]] to i64
 ; CHECK-NEXT:ret i64 [[B]]
 ;
   %b = call i64 @llvm.amdgcn.ballot.i64(i1 %i)
@@ -2616,7 +2617,8 @@ define i64 @ballot_zero_64() {
 
 define i64 @ballot_one_64() {
 ; CHECK-LABEL: @ballot_one_64(
-; CHECK-NEXT:[[B:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; CHECK-NEXT:[[TMP1:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 true)
+; CHECK-NEXT:[[B:%.*]] = zext i32 [[TMP1]] to i64
 ; CHECK-NEXT:ret i64 [[B]]
 ;
   %b = call i64 @llvm.amdgcn.ballot.i64(i1 1)

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[clang-tools-extra] [clang-tidy] Add check hicpp-ignored-remove-result (PR #73119)

2023-12-08 Thread Björn Svensson via cfe-commits


bjosv wrote:

Thanks for the informative review comments @PiotrZSL, much appreciated.

https://github.com/llvm/llvm-project/pull/73119
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[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)

2023-12-08 Thread Jianjian Guan via cfe-commits


https://github.com/jacquesguan updated 
https://github.com/llvm/llvm-project/pull/73489

>From dcc71641695128e117b290cd1e63879e0beeb796 Mon Sep 17 00:00:00 2001
From: Jianjian GUAN 
Date: Mon, 27 Nov 2023 16:14:04 +0800
Subject: [PATCH] [clang][RISCV] Change default abi with f extension but
 without d extension

Now we have default abi lp64 for rv64if and ilp32 for rv32if, which is 
different with riscv-gnu-toolchain.
In 
https://github.com/riscv-collab/riscv-gnu-toolchain/blob/8e9fb09a0c4b1e566492ee6f42e8c1fa5ef7e0c2/configure#L3385
 when have f but not, it prefers lp64f/ilp32f but no soft float. This patch 
tries to make their behaviors consistent.
---
 clang/test/Driver/riscv-abi.c  | 14 +-
 clang/test/Driver/riscv-cpus.c |  6 +++---
 llvm/docs/ReleaseNotes.rst |  1 +
 llvm/lib/Support/RISCVISAInfo.cpp  |  4 
 llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll |  4 ++--
 llvm/test/CodeGen/RISCV/calling-conv-half.ll   |  4 ++--
 .../CodeGen/RISCV/calling-conv-rv32f-ilp32.ll  |  2 +-
 .../CodeGen/RISCV/calling-conv-vector-float.ll |  2 +-
 .../RISCV/float-bitmanip-dagcombines.ll|  8 
 llvm/test/CodeGen/RISCV/float-frem.ll  |  7 +--
 llvm/test/CodeGen/RISCV/float-select-verify.ll |  2 +-
 .../CodeGen/RISCV/half-bitmanip-dagcombines.ll | 18 +-
 llvm/test/CodeGen/RISCV/half-fcmp.ll   |  8 
 13 files changed, 42 insertions(+), 38 deletions(-)

diff --git a/clang/test/Driver/riscv-abi.c b/clang/test/Driver/riscv-abi.c
index e67f790e0de0e..16568271564c7 100644
--- a/clang/test/Driver/riscv-abi.c
+++ b/clang/test/Driver/riscv-abi.c
@@ -4,8 +4,6 @@
 // RUN:   | FileCheck -check-prefix=CHECK-ILP32 %s
 // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imc 2>&1 \
 // RUN:   | FileCheck -check-prefix=CHECK-ILP32 %s
-// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \
-// RUN:   | FileCheck -check-prefix=CHECK-ILP32 %s
 // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### 2>&1 \
 // RUN:   | FileCheck -check-prefix=CHECK-ILP32 %s
 // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### \
@@ -24,6 +22,10 @@
 
 // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if -mabi=ilp32f 
2>&1 \
 // RUN:   | FileCheck -check-prefix=CHECK-ILP32F %s
+// RUN: %clang --target=riscv32-unknown-elf %s -### -mabi=ilp32f 2>&1 \
+// RUN:   | FileCheck -check-prefix=CHECK-ILP32F %s
+// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if 2>&1 \
+// RUN:   | FileCheck -check-prefix=CHECK-ILP32F %s
 
 // CHECK-ILP32F: "-target-abi" "ilp32f"
 
@@ -51,8 +53,6 @@
 // RUN:   | FileCheck -check-prefix=CHECK-LP64 %s
 // RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imc 2>&1 \
 // RUN:   | FileCheck -check-prefix=CHECK-LP64 %s
-// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \
-// RUN:   | FileCheck -check-prefix=CHECK-LP64 %s
 // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### 2>&1 \
 // RUN:   | FileCheck -check-prefix=CHECK-LP64  %s
 // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### \
@@ -60,7 +60,11 @@
 
 // CHECK-LP64: "-target-abi" "lp64"
 
-// RUN:  not %clang --target=riscv64-unknown-elf %s -### -march=rv64f 
-mabi=lp64f 2>&1 \
+// RUN:  %clang --target=riscv64-unknown-elf %s -### -march=rv64if -mabi=lp64f 
2>&1 \
+// RUN:   | FileCheck -check-prefix=CHECK-LP64F %s
+// RUN:  %clang --target=riscv64-unknown-elf %s -### -mabi=lp64f 2>&1 \
+// RUN:   | FileCheck -check-prefix=CHECK-LP64F %s
+// RUN:  %clang --target=riscv64-unknown-elf %s -### -march=rv64if 2>&1 \
 // RUN:   | FileCheck -check-prefix=CHECK-LP64F %s
 
 // CHECK-LP64F: "-target-abi" "lp64f"
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 6c31282d0c8d4..d7fa7c9854a48 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -113,7 +113,7 @@
 // MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f"
 // MCPU-SIFIVE-E24: "-target-feature" "+c"
 // MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-SIFIVE-E24: "-target-abi" "ilp32"
+// MCPU-SIFIVE-E24: "-target-abi" "ilp32f"
 
 // mcpu with default march
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck 
-check-prefix=MCPU-SIFIVE-E34 %s
@@ -121,7 +121,7 @@
 // MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f"
 // MCPU-SIFIVE-E34: "-target-feature" "+c"
 // MCPU-SIFIVE-E34: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
-// MCPU-SIFIVE-E34: "-target-abi" "ilp32"
+// MCPU-SIFIVE-E34: "-target-abi" "ilp32f"
 
 // mcpu with mabi option
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | 
FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s
@@ -178,7 +178,7 @@
 // MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "

[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)

2023-12-08 Thread Jianjian Guan via cfe-commits


jacquesguan wrote:

> I think the conclusion from the LLVM sync-up call was that everyone happy to 
> move in this direction, so please add the release note and we can do a final 
> review. Thanks!

Done, added release note.

https://github.com/llvm/llvm-project/pull/73489
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[clang] [Clang][SVE2p1]Add svboolx2 and svboolx4 types for svcreate, svget, s… (PR #74594)

2023-12-08 Thread via cfe-commits


https://github.com/CarolineConcatto updated 
https://github.com/llvm/llvm-project/pull/74594

>From 037dd51fd05ccd70f10dbf4ca75dd1f45e6548c4 Mon Sep 17 00:00:00 2001
From: Caroline Concatto 
Date: Wed, 6 Dec 2023 14:02:23 +
Subject: [PATCH 1/2] [Clang][SVE2p1]Add svboolx2 and svboolx4 types for
 svcreate, svget, svset

According to the PR#257[1]

[1]ARM-software/acle#257

Co-authored by: Matthew Devereau 
---
 clang/include/clang/Basic/arm_sve.td  | 12 
 .../acle_sve2p1_create2_bool.c| 38 ++
 .../acle_sve2p1_create4_bool.c| 42 +++
 .../acle_sve2p1_get2_bool.c   | 49 +
 .../acle_sve2p1_get4_bool.c   | 72 +++
 .../acle_sve2p1_set2_bool.c   | 52 ++
 .../acle_sve2p1_set4_bool.c   | 66 +
 7 files changed, 331 insertions(+)
 create mode 100644 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_create2_bool.c
 create mode 100644 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_create4_bool.c
 create mode 100644 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_get2_bool.c
 create mode 100644 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_get4_bool.c
 create mode 100644 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_set2_bool.c
 create mode 100644 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_set4_bool.c

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 3f69a3df9e616..9d4051a3ed34c 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1296,6 +1296,11 @@ def SVCREATE_3_BF16 : SInst<"svcreate3[_{d}]", "3ddd",  
"b", MergeNone, "", [IsT
 def SVCREATE_4_BF16 : SInst<"svcreate4[_{d}]", "4", "b", MergeNone, "", 
[IsTupleCreate]>;
 }
 
+let TargetGuard = "sve2p1" in {
+  def SVCREATE_2_B : SInst<"svcreate2[_{d}]", "2dd",   "Pc", MergeNone, "", 
[IsTupleCreate]>;
+  def SVCREATE_4_B : SInst<"svcreate4[_{d}]", "4", "Pc", MergeNone, "", 
[IsTupleCreate]>;
+}
+
 

 // Vector insertion and extraction
 def SVGET_2 : SInst<"svget2[_{d}]", "d2i", "csilUcUsUiUlhfd", MergeNone, "", 
[IsTupleGet], [ImmCheck<1, ImmCheck0_1>]>;
@@ -1316,6 +1321,13 @@ def SVSET_3_BF16 : SInst<"svset3[_{d}]", "33id", "b", 
MergeNone, "", [IsTupleSet
 def SVSET_4_BF16 : SInst<"svset4[_{d}]", "44id", "b", MergeNone, "", 
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
 }
 
+let TargetGuard = "sve2p1" in {
+  def SVGET_2_B : SInst<"svget2[_{d}]", "d2i", "Pc", MergeNone, "", 
[IsTupleGet], [ImmCheck<1, ImmCheck0_1>]>;
+  def SVGET_4_B : SInst<"svget4[_{d}]", "d4i", "Pc", MergeNone, "", 
[IsTupleGet], [ImmCheck<1, ImmCheck0_3>]>;
+
+  def SVSET_2_B : SInst<"svset2[_{d}]", "22id", "Pc", MergeNone, "", 
[IsTupleSet], [ImmCheck<1, ImmCheck0_1>]>;
+  def SVSET_4_B : SInst<"svset4[_{d}]", "44id", "Pc", MergeNone, "", 
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
+}
 

 // SVE2 WhileGE/GT
 let TargetGuard = "sve2" in {
diff --git 
a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_create2_bool.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_create2_bool.c
new file mode 100644
index 0..eb5a19b1d9d32
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_create2_bool.c
@@ -0,0 +1,38 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s \
+// RUN: | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s \
+// RUN: | opt -S -passes=mem2reg,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s 
\
+// RUN: | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x 
c++ %s\
+// RUN: | opt -S -passes=mem2reg,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -o /dev/null %s
+
+// REQUIRES: aarch64-registered-target
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+// CHECK-LABEL: @test_svcreate2_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:

[clang] [Clang][SVE2p1]Add svboolx2 and svboolx4 types for svcreate, svget, s… (PR #74594)

2023-12-08 Thread via cfe-commits


CarolineConcatto wrote:

I added the tests for svget and svset. I am not sure about the flag yet.

https://github.com/llvm/llvm-project/pull/74594
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[llvm] [flang] [clang] [NFC][AMDGPU] Move address space enum to LLVM directory (PR #73944)

2023-12-08 Thread Dominik Adamski via cfe-commits


https://github.com/DominikAdamski updated 
https://github.com/llvm/llvm-project/pull/73944

>From 60ceda3d1025891f5037f020a2efe35108f62ca3 Mon Sep 17 00:00:00 2001
From: Dominik Adamski 
Date: Thu, 30 Nov 2023 08:06:12 -0600
Subject: [PATCH 1/4] [NFC][AMDGPU] Move address space enum to LLVM directory

Types of AMDGPU address space were defined in Clang-specific
class. In consequence this enum cannot be reused by other frontends
like Flang.

If we move address space enum to LLVM directory, then we can reuse
it in other frontends like Flang.
---
 clang/lib/Basic/Targets/AMDGPU.cpp| 80 +--
 clang/lib/Basic/Targets/AMDGPU.h  | 17 ++--
 flang/lib/Frontend/FrontendActions.cpp| 10 +--
 llvm/include/llvm/TargetParser/TargetParser.h |  9 +++
 4 files changed, 56 insertions(+), 60 deletions(-)

diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp 
b/clang/lib/Basic/Targets/AMDGPU.cpp
index 409ae32ab4242..3fe9f9fa9c42d 100644
--- a/clang/lib/Basic/Targets/AMDGPU.cpp
+++ b/clang/lib/Basic/Targets/AMDGPU.cpp
@@ -37,50 +37,50 @@ static const char *const DataLayoutStringAMDGCN =
 "-ni:7:8";
 
 const LangASMap AMDGPUTargetInfo::AMDGPUDefIsGenMap = {
-Generic,  // Default
-Global,   // opencl_global
-Local,// opencl_local
-Constant, // opencl_constant
-Private,  // opencl_private
-Generic,  // opencl_generic
-Global,   // opencl_global_device
-Global,   // opencl_global_host
-Global,   // cuda_device
-Constant, // cuda_constant
-Local,// cuda_shared
-Global,   // sycl_global
-Global,   // sycl_global_device
-Global,   // sycl_global_host
-Local,// sycl_local
-Private,  // sycl_private
-Generic,  // ptr32_sptr
-Generic,  // ptr32_uptr
-Generic,  // ptr64
-Generic,  // hlsl_groupshared
+llvm::AMDGPU::Generic,  // Default
+llvm::AMDGPU::Global,   // opencl_global
+llvm::AMDGPU::Local,// opencl_local
+llvm::AMDGPU::Constant, // opencl_constant
+llvm::AMDGPU::Private,  // opencl_private
+llvm::AMDGPU::Generic,  // opencl_generic
+llvm::AMDGPU::Global,   // opencl_global_device
+llvm::AMDGPU::Global,   // opencl_global_host
+llvm::AMDGPU::Global,   // cuda_device
+llvm::AMDGPU::Constant, // cuda_constant
+llvm::AMDGPU::Local,// cuda_shared
+llvm::AMDGPU::Global,   // sycl_global
+llvm::AMDGPU::Global,   // sycl_global_device
+llvm::AMDGPU::Global,   // sycl_global_host
+llvm::AMDGPU::Local,// sycl_local
+llvm::AMDGPU::Private,  // sycl_private
+llvm::AMDGPU::Generic,  // ptr32_sptr
+llvm::AMDGPU::Generic,  // ptr32_uptr
+llvm::AMDGPU::Generic,  // ptr64
+llvm::AMDGPU::Generic,  // hlsl_groupshared
 };
 
 const LangASMap AMDGPUTargetInfo::AMDGPUDefIsPrivMap = {
-Private,  // Default
-Global,   // opencl_global
-Local,// opencl_local
-Constant, // opencl_constant
-Private,  // opencl_private
-Generic,  // opencl_generic
-Global,   // opencl_global_device
-Global,   // opencl_global_host
-Global,   // cuda_device
-Constant, // cuda_constant
-Local,// cuda_shared
+llvm::AMDGPU::Private,  // Default
+llvm::AMDGPU::Global,   // opencl_global
+llvm::AMDGPU::Local,// opencl_local
+llvm::AMDGPU::Constant, // opencl_constant
+llvm::AMDGPU::Private,  // opencl_private
+llvm::AMDGPU::Generic,  // opencl_generic
+llvm::AMDGPU::Global,   // opencl_global_device
+llvm::AMDGPU::Global,   // opencl_global_host
+llvm::AMDGPU::Global,   // cuda_device
+llvm::AMDGPU::Constant, // cuda_constant
+llvm::AMDGPU::Local,// cuda_shared
 // SYCL address space values for this map are dummy
-Generic, // sycl_global
-Generic, // sycl_global_device
-Generic, // sycl_global_host
-Generic, // sycl_local
-Generic, // sycl_private
-Generic, // ptr32_sptr
-Generic, // ptr32_uptr
-Generic, // ptr64
-Generic, // hlsl_groupshared
+llvm::AMDGPU::Generic, // sycl_global
+llvm::AMDGPU::Generic, // sycl_global_device
+llvm::AMDGPU::Generic, // sycl_global_host
+llvm::AMDGPU::Generic, // sycl_local
+llvm::AMDGPU::Generic, // sycl_private
+llvm::AMDGPU::Generic, // ptr32_sptr
+llvm::AMDGPU::Generic, // ptr32_uptr
+llvm::AMDGPU::Generic, // ptr64
+llvm::AMDGPU::Generic, // hlsl_groupshared
 
 };
 } // namespace targets
diff --git a/clang/lib/Basic/Targets/AMDGPU.h b/clang/lib/Basic/Targets/AMDGPU.h
index 300d9691d8a0f..1e12f9e12af59 100644
--- a/clang/lib/Basic/Targets/AMDGPU.h
+++ b/clang/lib/Basic/Targets/AMDGPU.h
@@ -29,13 +29,6 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : 
public TargetInfo {
 
   static const char *const GCCRegNames[];
 
-  enum AddrSpace {
-Generic = 0,
-Global = 1,
-Local = 3,
-Constant = 4,
-Private = 5
-  };
   static const LangASMap AMDGPUDefIsGenMap;
   static const LangASMap AMDGPUDefIsPrivMap;
 
@@ -106,7 +99

[llvm] [flang] [clang] [NFC][AMDGPU] Move address space enum to LLVM directory (PR #73944)

2023-12-08 Thread via cfe-commits


github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff a4e1aa256b14d74da47fdfeb245930a520f5fd64 
82ec7a5c59e0e6dbc28a18febc3bb19872616e3b -- 
llvm/include/llvm/Support/AMDGPUAddrSpace.h clang/lib/Basic/Targets/AMDGPU.cpp 
clang/lib/Basic/Targets/AMDGPU.h flang/lib/Frontend/FrontendActions.cpp 
llvm/lib/Target/AMDGPU/AMDGPU.h
``





View the diff from clang-format here.


``diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 95981af5c0..718f794f89 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -393,7 +393,6 @@ enum TargetIndex {
 };
 }
 
-
 namespace AMDGPU {
 
 // FIXME: Missing constant_32bit

``




https://github.com/llvm/llvm-project/pull/73944
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[flang] [clang] [flang][Driver] Let the linker fail on multiple definitions of main() (PR #73124)

2023-12-08 Thread Ricardo Jesus via cfe-commits


rj-jesus wrote:

> The solution is to add `-fno-fortran-main` to the linker options via 
> `CMAKE_SHARED_LINKER_FLAGS`. This will need PR #74139 land first. But this 
> option will be a good way to control if the flang compiler should attempt 
> linking in the `main` stub from its library.
> 
> It seems like `flang-new` when being used as a linker with `-shared` included 
> Fortran_main in the shared library. This seems wrong to me. The option 
> `-fno-fortran-main` avoids this. I'm pondering if `-shared` is buggy here. It 
> will require a bit more digging on my end to figure that out.

Thanks, sounds like a good workaround to me, though as you say I find strange 
the need to explicitly specify "don't include main" when building a library!

https://github.com/llvm/llvm-project/pull/73124
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[llvm] [clang-tools-extra] [clang] [Clang][AArch64] Add fix vector types to header into SVE (PR #73258)

2023-12-08 Thread via cfe-commits


https://github.com/CarolineConcatto updated 
https://github.com/llvm/llvm-project/pull/73258

>From e0f245e8d6a395afac5de471b55358c7b730a170 Mon Sep 17 00:00:00 2001
From: Caroline Concatto 
Date: Wed, 22 Nov 2023 10:03:50 +
Subject: [PATCH 1/6] [Clang][AArch64] Add  fix vector types to header into SVE

This patch is needed for the reduction instructions in sve2.1

It add ta new header to sve with all the fixed vector types.
The new types are only added if neon is not declared.
---
 clang/include/clang/Basic/arm_vector_type.td  |  13 ++
 clang/lib/Headers/CMakeLists.txt  |   3 +
 .../CodeGen/arm-vector_type-params-returns.c  | 113 ++
 clang/utils/TableGen/NeonEmitter.cpp  |  44 +++
 clang/utils/TableGen/SveEmitter.cpp   |   2 +
 clang/utils/TableGen/TableGen.cpp |  15 ++-
 clang/utils/TableGen/TableGenBackends.h   |   1 +
 7 files changed, 188 insertions(+), 3 deletions(-)
 create mode 100644 clang/include/clang/Basic/arm_vector_type.td
 create mode 100644 clang/test/CodeGen/arm-vector_type-params-returns.c

diff --git a/clang/include/clang/Basic/arm_vector_type.td 
b/clang/include/clang/Basic/arm_vector_type.td
new file mode 100644
index 00..5018b0cdfc1378
--- /dev/null
+++ b/clang/include/clang/Basic/arm_vector_type.td
@@ -0,0 +1,13 @@
+//===--- arm_vector_type.td - ARM Fixed vector types compiler interface 
---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+//  This file defines the TableGen definitions from which the ARM BF16 header
+//  file will be generated.
+//
+//===--===//
+include "arm_neon_incl.td"
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index 8b1e2bc4afa4dc..0beb6ade429204 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -385,6 +385,8 @@ if(ARM IN_LIST LLVM_TARGETS_TO_BUILD OR AArch64 IN_LIST 
LLVM_TARGETS_TO_BUILD)
   clang_generate_header(-gen-arm-mve-header arm_mve.td arm_mve.h)
   # Generate arm_cde.h
   clang_generate_header(-gen-arm-cde-header arm_cde.td arm_cde.h)
+  # Generate arm_vector_type.h
+  clang_generate_header(-gen-arm-vector-type arm_vector_type.td 
arm_vector_type.h)
 
   # Add headers to target specific lists
   list(APPEND arm_common_generated_files
@@ -401,6 +403,7 @@ if(ARM IN_LIST LLVM_TARGETS_TO_BUILD OR AArch64 IN_LIST 
LLVM_TARGETS_TO_BUILD)
 "${CMAKE_CURRENT_BINARY_DIR}/arm_sve.h"
 "${CMAKE_CURRENT_BINARY_DIR}/arm_sme_draft_spec_subject_to_change.h"
 "${CMAKE_CURRENT_BINARY_DIR}/arm_bf16.h"
+"${CMAKE_CURRENT_BINARY_DIR}/arm_vector_type.h"
 )
 endif()
 if(RISCV IN_LIST LLVM_TARGETS_TO_BUILD)
diff --git a/clang/test/CodeGen/arm-vector_type-params-returns.c 
b/clang/test/CodeGen/arm-vector_type-params-returns.c
new file mode 100644
index 00..48c19d01b6257c
--- /dev/null
+++ b/clang/test/CodeGen/arm-vector_type-params-returns.c
@@ -0,0 +1,113 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 3
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - %s 
| opt -S -passes=mem2reg,sroa | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -o - /dev/null %s
+#include 
+
+// function return types
+// CHECK-LABEL: define dso_local <8 x half> @test_ret_v8f16(
+// CHECK-SAME: <8 x half> noundef returned [[V:%.*]]) local_unnamed_addr 
#[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret <8 x half> [[V]]
+//
+float16x8_t test_ret_v8f16(float16x8_t v) {
+  return v;
+}
+
+// CHECK-LABEL: define dso_local <4 x float> @test_ret_v4f32(
+// CHECK-SAME: <4 x float> noundef returned [[V:%.*]]) local_unnamed_addr 
#[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret <4 x float> [[V]]
+//
+float32x4_t test_ret_v4f32(float32x4_t v) {
+  return v;
+}
+
+// CHECK-LABEL: define dso_local <2 x double> @test_ret_v2f64(
+// CHECK-SAME: <2 x double> noundef returned [[V:%.*]]) local_unnamed_addr 
#[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret <2 x double> [[V]]
+//
+float64x2_t test_ret_v2f64(float64x2_t v) {
+  return v;
+}
+
+// CHECK-LABEL: define dso_local <8 x bfloat> @test_ret_v8bf16(
+// CHECK-SAME: <8 x bfloat> noundef returned [[V:%.*]]) local_unnamed_addr 
#[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret <8 x bfloat> [[V]]
+//
+bfloat16x8_t test_ret_v8bf16(bfloat16x8_t v) {
+  return v;
+}
+
+// CHECK-LABEL: define dso_local <16 x i8> @test_ret_v16s8(
+// CHECK-SAME: <16 x i8> noundef returned [[V:%.*]]) local_unnamed_addr 
#[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret <16 x

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray created 
https://github.com/llvm/llvm-project/pull/74822

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52


>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52
---
 clang/docs/ReleaseNotes.rst|  1 +
 clang/test/CodeGen/arm-target-features.c   |  3 +++
 clang/test/Driver/arm-cortex-cpus-2.c  |  3 +++
 clang/test/Misc/target-invalid-cpu-note.c  |  2 +-
 llvm/docs/ReleaseNotes.rst |  2 +-
 llvm/include/llvm/TargetParser/ARMTargetParser.def |  3 +++
 llvm/lib/Target/ARM/ARM.td | 11 +++
 llvm/lib/Target/ARM/ARMSubtarget.cpp   |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h |  1 +
 llvm/lib/TargetParser/Host.cpp |  1 +
 llvm/unittests/TargetParser/TargetParserTest.cpp   |  8 +++-
 11 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c044658197139..6f3b6efbfe08c0 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc1..ad4bfd45c408b5 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f3..4bf2b3a50412d0 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f2..f921c4605bb976 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
corte

[llvm] [flang] [clang] [NFC][AMDGPU] Move address space enum to LLVM directory (PR #73944)

2023-12-08 Thread Dominik Adamski via cfe-commits


https://github.com/DominikAdamski updated 
https://github.com/llvm/llvm-project/pull/73944

>From 60ceda3d1025891f5037f020a2efe35108f62ca3 Mon Sep 17 00:00:00 2001
From: Dominik Adamski 
Date: Thu, 30 Nov 2023 08:06:12 -0600
Subject: [PATCH 1/4] [NFC][AMDGPU] Move address space enum to LLVM directory

Types of AMDGPU address space were defined in Clang-specific
class. In consequence this enum cannot be reused by other frontends
like Flang.

If we move address space enum to LLVM directory, then we can reuse
it in other frontends like Flang.
---
 clang/lib/Basic/Targets/AMDGPU.cpp| 80 +--
 clang/lib/Basic/Targets/AMDGPU.h  | 17 ++--
 flang/lib/Frontend/FrontendActions.cpp| 10 +--
 llvm/include/llvm/TargetParser/TargetParser.h |  9 +++
 4 files changed, 56 insertions(+), 60 deletions(-)

diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp 
b/clang/lib/Basic/Targets/AMDGPU.cpp
index 409ae32ab4242..3fe9f9fa9c42d 100644
--- a/clang/lib/Basic/Targets/AMDGPU.cpp
+++ b/clang/lib/Basic/Targets/AMDGPU.cpp
@@ -37,50 +37,50 @@ static const char *const DataLayoutStringAMDGCN =
 "-ni:7:8";
 
 const LangASMap AMDGPUTargetInfo::AMDGPUDefIsGenMap = {
-Generic,  // Default
-Global,   // opencl_global
-Local,// opencl_local
-Constant, // opencl_constant
-Private,  // opencl_private
-Generic,  // opencl_generic
-Global,   // opencl_global_device
-Global,   // opencl_global_host
-Global,   // cuda_device
-Constant, // cuda_constant
-Local,// cuda_shared
-Global,   // sycl_global
-Global,   // sycl_global_device
-Global,   // sycl_global_host
-Local,// sycl_local
-Private,  // sycl_private
-Generic,  // ptr32_sptr
-Generic,  // ptr32_uptr
-Generic,  // ptr64
-Generic,  // hlsl_groupshared
+llvm::AMDGPU::Generic,  // Default
+llvm::AMDGPU::Global,   // opencl_global
+llvm::AMDGPU::Local,// opencl_local
+llvm::AMDGPU::Constant, // opencl_constant
+llvm::AMDGPU::Private,  // opencl_private
+llvm::AMDGPU::Generic,  // opencl_generic
+llvm::AMDGPU::Global,   // opencl_global_device
+llvm::AMDGPU::Global,   // opencl_global_host
+llvm::AMDGPU::Global,   // cuda_device
+llvm::AMDGPU::Constant, // cuda_constant
+llvm::AMDGPU::Local,// cuda_shared
+llvm::AMDGPU::Global,   // sycl_global
+llvm::AMDGPU::Global,   // sycl_global_device
+llvm::AMDGPU::Global,   // sycl_global_host
+llvm::AMDGPU::Local,// sycl_local
+llvm::AMDGPU::Private,  // sycl_private
+llvm::AMDGPU::Generic,  // ptr32_sptr
+llvm::AMDGPU::Generic,  // ptr32_uptr
+llvm::AMDGPU::Generic,  // ptr64
+llvm::AMDGPU::Generic,  // hlsl_groupshared
 };
 
 const LangASMap AMDGPUTargetInfo::AMDGPUDefIsPrivMap = {
-Private,  // Default
-Global,   // opencl_global
-Local,// opencl_local
-Constant, // opencl_constant
-Private,  // opencl_private
-Generic,  // opencl_generic
-Global,   // opencl_global_device
-Global,   // opencl_global_host
-Global,   // cuda_device
-Constant, // cuda_constant
-Local,// cuda_shared
+llvm::AMDGPU::Private,  // Default
+llvm::AMDGPU::Global,   // opencl_global
+llvm::AMDGPU::Local,// opencl_local
+llvm::AMDGPU::Constant, // opencl_constant
+llvm::AMDGPU::Private,  // opencl_private
+llvm::AMDGPU::Generic,  // opencl_generic
+llvm::AMDGPU::Global,   // opencl_global_device
+llvm::AMDGPU::Global,   // opencl_global_host
+llvm::AMDGPU::Global,   // cuda_device
+llvm::AMDGPU::Constant, // cuda_constant
+llvm::AMDGPU::Local,// cuda_shared
 // SYCL address space values for this map are dummy
-Generic, // sycl_global
-Generic, // sycl_global_device
-Generic, // sycl_global_host
-Generic, // sycl_local
-Generic, // sycl_private
-Generic, // ptr32_sptr
-Generic, // ptr32_uptr
-Generic, // ptr64
-Generic, // hlsl_groupshared
+llvm::AMDGPU::Generic, // sycl_global
+llvm::AMDGPU::Generic, // sycl_global_device
+llvm::AMDGPU::Generic, // sycl_global_host
+llvm::AMDGPU::Generic, // sycl_local
+llvm::AMDGPU::Generic, // sycl_private
+llvm::AMDGPU::Generic, // ptr32_sptr
+llvm::AMDGPU::Generic, // ptr32_uptr
+llvm::AMDGPU::Generic, // ptr64
+llvm::AMDGPU::Generic, // hlsl_groupshared
 
 };
 } // namespace targets
diff --git a/clang/lib/Basic/Targets/AMDGPU.h b/clang/lib/Basic/Targets/AMDGPU.h
index 300d9691d8a0f..1e12f9e12af59 100644
--- a/clang/lib/Basic/Targets/AMDGPU.h
+++ b/clang/lib/Basic/Targets/AMDGPU.h
@@ -29,13 +29,6 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : 
public TargetInfo {
 
   static const char *const GCCRegNames[];
 
-  enum AddrSpace {
-Generic = 0,
-Global = 1,
-Local = 3,
-Constant = 4,
-Private = 5
-  };
   static const LangASMap AMDGPUDefIsGenMap;
   static const LangASMap AMDGPUDefIsPrivMap;
 
@@ -106,7 +99

[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread via cfe-commits


llvmbot wrote:



@llvm/pr-subscribers-clang-driver

@llvm/pr-subscribers-backend-arm

Author: Jonathan Thackray (jthackray)


Changes

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52


---
Full diff: https://github.com/llvm/llvm-project/pull/74822.diff


11 Files Affected:

- (modified) clang/docs/ReleaseNotes.rst (+1) 
- (modified) clang/test/CodeGen/arm-target-features.c (+3) 
- (modified) clang/test/Driver/arm-cortex-cpus-2.c (+3) 
- (modified) clang/test/Misc/target-invalid-cpu-note.c (+1-1) 
- (modified) llvm/docs/ReleaseNotes.rst (+1-1) 
- (modified) llvm/include/llvm/TargetParser/ARMTargetParser.def (+3) 
- (modified) llvm/lib/Target/ARM/ARM.td (+11) 
- (modified) llvm/lib/Target/ARM/ARMSubtarget.cpp (+1) 
- (modified) llvm/lib/Target/ARM/ARMSubtarget.h (+1) 
- (modified) llvm/lib/TargetParser/Host.cpp (+1) 
- (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+7-1) 


``diff
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c04465819713..6f3b6efbfe08c 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc..ad4bfd45c408b 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f..4bf2b3a50412d 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f..f921c4605bb97 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-a32, cortex-a35, cortex-a53, 
cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-x1, 
c

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread via cfe-commits


llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Jonathan Thackray (jthackray)


Changes

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52


---
Full diff: https://github.com/llvm/llvm-project/pull/74822.diff


11 Files Affected:

- (modified) clang/docs/ReleaseNotes.rst (+1) 
- (modified) clang/test/CodeGen/arm-target-features.c (+3) 
- (modified) clang/test/Driver/arm-cortex-cpus-2.c (+3) 
- (modified) clang/test/Misc/target-invalid-cpu-note.c (+1-1) 
- (modified) llvm/docs/ReleaseNotes.rst (+1-1) 
- (modified) llvm/include/llvm/TargetParser/ARMTargetParser.def (+3) 
- (modified) llvm/lib/Target/ARM/ARM.td (+11) 
- (modified) llvm/lib/Target/ARM/ARMSubtarget.cpp (+1) 
- (modified) llvm/lib/Target/ARM/ARMSubtarget.h (+1) 
- (modified) llvm/lib/TargetParser/Host.cpp (+1) 
- (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+7-1) 


``diff
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c044658197139..6f3b6efbfe08c0 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc1..ad4bfd45c408b5 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f3..4bf2b3a50412d0 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f2..f921c4605bb976 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-a32, cortex-a35, cortex-a53, 
cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, cortex-a76, 
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-x1, 
cortex-x1c, neoverse-n1, neoverse

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread via cfe-commits


github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff ea85345eb69f751fdfd793016c854605f14f9dfc 
5925f180b6a8623ae1f1497f89c1f6ef35517e4a -- 
clang/test/CodeGen/arm-target-features.c clang/test/Driver/arm-cortex-cpus-2.c 
clang/test/Misc/target-invalid-cpu-note.c llvm/lib/Target/ARM/ARMSubtarget.cpp 
llvm/lib/Target/ARM/ARMSubtarget.h llvm/lib/TargetParser/Host.cpp 
llvm/unittests/TargetParser/TargetParserTest.cpp
``





View the diff from clang-format here.


``diff
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp 
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index acd0b9b9d6..c58a029b19 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -267,7 +267,8 @@ INSTANTIATE_TEST_SUITE_P(
 ARMCPUTestsPart2, ARMCPUTestFixture,
 ::testing::Values(
 ARMCPUTestParams("cortex-a9", "armv7-a", "neon-fp16",
-   ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP, 
"7-A"),
+   ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP,
+   "7-A"),
 ARMCPUTestParams("cortex-a12", "armv7-a", "neon-vfpv4",
ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB 
|
@@ -284,25 +285,28 @@ INSTANTIATE_TEST_SUITE_P(
ARM::AEK_DSP,
"7-A"),
 ARMCPUTestParams("krait", "armv7-a", "neon-vfpv4",
-   ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | 
ARM::AEK_DSP,
+   ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
+   ARM::AEK_DSP,
"7-A"),
 ARMCPUTestParams("cortex-r4", "armv7-r", "none",
-   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB | 
ARM::AEK_DSP,
- "7-R"),
+   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB |
+   ARM::AEK_DSP,
+   "7-R"),
 ARMCPUTestParams("cortex-r4f", "armv7-r", "vfpv3-d16",
- ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
- "7-R"),
-ARMCPUTestParams("cortex-r5", "armv7-r", "vfpv3-d16",
- ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB 
|
+   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB |
ARM::AEK_DSP,
"7-R"),
+ARMCPUTestParams("cortex-r5", "armv7-r", "vfpv3-d16",
+   ARM::AEK_MP | ARM::AEK_HWDIVARM |
+   ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
+   "7-R"),
 ARMCPUTestParams("cortex-r7", "armv7-r", "vfpv3-d16-fp16",
-   ARM::AEK_MP | ARM::AEK_HWDIVARM | 
ARM::AEK_HWDIVTHUMB |
-   ARM::AEK_DSP,
+   ARM::AEK_MP | ARM::AEK_HWDIVARM |
+   ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"7-R"),
 ARMCPUTestParams("cortex-r8", "armv7-r", "vfpv3-d16-fp16",
-   ARM::AEK_MP | ARM::AEK_HWDIVARM | 
ARM::AEK_HWDIVTHUMB |
- ARM::AEK_DSP,
+   ARM::AEK_MP | ARM::AEK_HWDIVARM |
+   ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"7-R"),
 ARMCPUTestParams("cortex-r52", "armv8-r", "neon-fp-armv8",
ARM::AEK_NONE | ARM::AEK_CRC | ARM::AEK_MP |
@@ -314,171 +318,184 @@ INSTANTIATE_TEST_SUITE_P(
 ARMCPUTestParams("cortex-m3", "armv7-m", "none",
ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB, "7-M"),
 ARMCPUTestParams("cortex-m4", "armv7e-m", "fpv4-sp-d16",
-   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB | 
ARM::AEK_DSP,
+   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB |
+   ARM::AEK_DSP,
"7E-M"),
 ARMCPUTestParams("cortex-m7", "armv7e-m", "fpv5-d16",
-   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB | 
ARM::AEK_DSP,
+   ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB |
+   ARM::AEK_DSP,
"7E-M"),
-ARMCPUTestParams("cortex-a32", "armv8-a", 
"crypto-neon-fp-armv8",
+ARMCPUTestParams("cortex-a

[clang] [Clang][SVE2p1]Add svboolx2 and svboolx4 types for svcreate, svget, s… (PR #74594)

2023-12-08 Thread Kerry McLaughlin via cfe-commits


https://github.com/kmclaughlin-arm edited 
https://github.com/llvm/llvm-project/pull/74594
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[clang] [Clang][SVE2p1]Add svboolx2 and svboolx4 types for svcreate, svget, s… (PR #74594)

2023-12-08 Thread Kerry McLaughlin via cfe-commits



@@ -167,3 +167,23 @@ void test_svpmov_lane(){
   zn_u32 = svpmov_lane_u32_m(zn_u32, pn, 5); // expected-error {{argument 
value 5 is outside the valid range [1, 3]}}
   zn_u64 = svpmov_lane_u64_m(zn_u64, pn, 8); // expected-error {{argument 
value 8 is outside the valid range [1, 7]}}
 }
+
+__attribute__((target("+sve2p1")))
+void test_svget_b(uint64_t idx, svboolx2_t tuple2, svboolx4_t tuple4){
+  svbool_t res;
+
+  svset2(tuple2, -1, res); // expected-error {{argument value 
18446744073709551615 is outside the valid range [0, 1]}}
+  svset2(tuple2, 2,  res); // expected-error {{argument value 2 is outside the 
valid range [0, 1]}}
+  svset4(tuple4, -1, res); // expected-error {{argument value 
18446744073709551615 is outside the valid range [0, 3]}}
+  svset4(tuple4, 4,  res); // expected-error {{argument value 4 is outside the 
valid range [0, 3]}}
+
+  res = svget2(tuple2, -1); // expected-error {{argument value 
18446744073709551615 is outside the valid range [0, 1]}}
+  res = svget2(tuple2,  2); // expected-error {{argument value 2 is outside 
the valid range [0, 1]}}
+  res = svget4(tuple4, -1); // expected-error {{argument value 
18446744073709551615 is outside the valid range [0, 3]}}
+  res = svget4(tuple4,  4); // expected-error {{argument value 4 is outside 
the valid range [0, 3]}}

kmclaughlin-arm wrote:

I don't think you need to use `res =` here, you can just call svget similar to 
svset above

https://github.com/llvm/llvm-project/pull/74594
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[clang] [Clang][SVE2p1]Add svboolx2 and svboolx4 types for svcreate, svget, s… (PR #74594)

2023-12-08 Thread Kerry McLaughlin via cfe-commits



@@ -167,3 +167,23 @@ void test_svpmov_lane(){
   zn_u32 = svpmov_lane_u32_m(zn_u32, pn, 5); // expected-error {{argument 
value 5 is outside the valid range [1, 3]}}
   zn_u64 = svpmov_lane_u64_m(zn_u64, pn, 8); // expected-error {{argument 
value 8 is outside the valid range [1, 7]}}
 }
+
+__attribute__((target("+sve2p1")))
+void test_svget_b(uint64_t idx, svboolx2_t tuple2, svboolx4_t tuple4){
+  svbool_t res;

kmclaughlin-arm wrote:

nit: can this be added to the list of args for `test_svget_b`, along with idx & 
tuple2/4?

https://github.com/llvm/llvm-project/pull/74594
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[clang] [Clang][SVE2p1]Add svboolx2 and svboolx4 types for svcreate, svget, s… (PR #74594)

2023-12-08 Thread Kerry McLaughlin via cfe-commits


https://github.com/kmclaughlin-arm commented:

Thank you for adding the tests @CarolineConcatto!

https://github.com/llvm/llvm-project/pull/74594
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[clang] [Clang][SVE2p1]Add svboolx2 and svboolx4 types for svcreate, svget, s… (PR #74594)

2023-12-08 Thread Kerry McLaughlin via cfe-commits



@@ -1316,6 +1321,13 @@ def SVSET_3_BF16 : SInst<"svset3[_{d}]", "33id", "b", 
MergeNone, "", [IsTupleSet
 def SVSET_4_BF16 : SInst<"svset4[_{d}]", "44id", "b", MergeNone, "", 
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
 }
 
+let TargetGuard = "sve2p1" in {
+  def SVGET_2_B : SInst<"svget2[_{d}]", "d2i", "Pc", MergeNone, "", 
[IsTupleGet], [ImmCheck<1, ImmCheck0_1>]>;
+  def SVGET_4_B : SInst<"svget4[_{d}]", "d4i", "Pc", MergeNone, "", 
[IsTupleGet], [ImmCheck<1, ImmCheck0_3>]>;
+
+  def SVSET_2_B : SInst<"svset2[_{d}]", "22id", "Pc", MergeNone, "", 
[IsTupleSet], [ImmCheck<1, ImmCheck0_1>]>;
+  def SVSET_4_B : SInst<"svset4[_{d}]", "44id", "Pc", MergeNone, "", 
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
+}
 


kmclaughlin-arm wrote:

You're right, we only need to add the flag once it's enabled for SME2

https://github.com/llvm/llvm-project/pull/74594
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[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Spickett via cfe-commits


DavidSpickett wrote:

I also made a small change in this area the other day and got a mountain of 
clang-format-diff changes.

So in case it's not clear, you can ignore the formatter and it won't block the 
approval/merge. Makes sense not to fill the change with unrelated formatting 
changes.

https://github.com/llvm/llvm-project/pull/74822
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[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Spickett via cfe-commits



@@ -102,7 +102,7 @@ Changes to the AMDGPU Backend
 
 * Implemented :ref:`llvm.get.rounding `
 
-* Added support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs.
+* Added support for Cortex-A520, Cortex-A720, Cortex-X4 and Cortex-M52 CPUs.

DavidSpickett wrote:

This line seems to have been in the wrong section to begin with. I think the 
AArch64 CPUs need to go in that section, then this one in the ARM section below.

https://github.com/llvm/llvm-project/pull/74822
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sam Tebbs via cfe-commits



@@ -3058,6 +3058,11 @@ bool Sema::ParseSVEImmChecks(
   if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1, 7))
 HasError = true;
   break;
+case SVETypeFlags::ImmCheck2_4_Mul2:

SamTebbs33 wrote:

I think you were looking at an old commit as I fixed that in 
[48ee745](https://github.com/llvm/llvm-project/pull/74064/commits/48ee745a815f0fda41cb1791f91d73db73e4aeba)

https://github.com/llvm/llvm-project/pull/74064
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Spickett via cfe-commits


DavidSpickett wrote:

Going by the page (didn't see a link to a manual, maybe I missed it), MVE and 
FPU are optional.

"Optional Helium technology (M-profile Vector Extension) supporting up to:"
"Optional FPU with support for half precision (fp16), single precision (fp32) 
and double precision (fp64) floating-point operations."

Is this following a pattern from previous CPUs where these things are optional, 
but users are expected to pass `+nomve` etc. to disable them? (I don't disagree 
with that, just want to keep it consistent)

https://github.com/llvm/llvm-project/pull/74822
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[lld] [polly] [openmp] [llvm] [flang] [clang] [mlir] [compiler-rt] [lldb] [VPlan] Compute scalable VF in preheader for induction increment. (PR #74762)

2023-12-08 Thread Florian Hahn via cfe-commits



@@ -340,8 +340,13 @@ Value *VPInstruction::generateInstruction(VPTransformState 
&State,
   auto *Phi = State.get(getOperand(0), 0);
   // The loop step is equal to the vectorization factor (num of SIMD
   // elements) times the unroll factor (num of SIMD instructions).
-  Value *Step =
-  createStepForVF(Builder, Phi->getType(), State.VF, State.UF);
+  Value *Step;
+  {
+BasicBlock *VectorPH = State.CFG.getPreheaderBBFor(this);
+IRBuilder<>::InsertPointGuard Guard(Builder);
+Builder.SetInsertPoint(VectorPH->getTerminator());

fhahn wrote:

Adjusted in the latest version, thanks!

https://github.com/llvm/llvm-project/pull/74762
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/74822

>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/2] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52
---
 clang/docs/ReleaseNotes.rst|  1 +
 clang/test/CodeGen/arm-target-features.c   |  3 +++
 clang/test/Driver/arm-cortex-cpus-2.c  |  3 +++
 clang/test/Misc/target-invalid-cpu-note.c  |  2 +-
 llvm/docs/ReleaseNotes.rst |  2 +-
 llvm/include/llvm/TargetParser/ARMTargetParser.def |  3 +++
 llvm/lib/Target/ARM/ARM.td | 11 +++
 llvm/lib/Target/ARM/ARMSubtarget.cpp   |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h |  1 +
 llvm/lib/TargetParser/Host.cpp |  1 +
 llvm/unittests/TargetParser/TargetParserTest.cpp   |  8 +++-
 11 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c04465819713..6f3b6efbfe08c 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc..ad4bfd45c408b 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f..4bf2b3a50412d 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f..f921c4605bb97 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-a32, cortex-a35, c

[llvm] [clang] [RISCV] Add support for experimental Zimop extension (PR #74824)

2023-12-08 Thread Jivan Hakobyan via cfe-commits


https://github.com/JivanH created 
https://github.com/llvm/llvm-project/pull/74824

This implements experimental support for the Zimop extension as specified here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.

This change adds intrinsics of mop.r.[n] and mop.rr.[n] instructions for Zimop 
extension based on 
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md. 


>From 2940a49eed5214668d4235ddaf3c82d076202b94 Mon Sep 17 00:00:00 2001
From: ln8-8 
Date: Fri, 8 Dec 2023 12:25:49 +0400
Subject: [PATCH] [RISCV] Add support for experimental Zimop extension

 This implements experimental support for the Zimop extension as specified 
here: https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.

This change adds IR intrinsics of mop.r.[n] and mop.rr.[n] instructions for 
Zimop extension based on 
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md. 
Also added assembly support.
---
 clang/include/clang/Basic/BuiltinsRISCV.def   |   5 +
 clang/lib/CodeGen/CGBuiltin.cpp   |  34 
 clang/lib/Sema/SemaChecking.cpp   |   8 +
 .../test/CodeGen/RISCV/rvb-intrinsics/zimop.c | 104 +++
 llvm/docs/RISCVUsage.rst  |   3 +
 llvm/include/llvm/IR/IntrinsicsRISCV.td   |  23 +++
 llvm/lib/Support/RISCVISAInfo.cpp |   2 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|   5 +
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   | 171 ++
 llvm/lib/Target/RISCV/RISCVISelLowering.h |   6 +
 llvm/lib/Target/RISCV/RISCVInstrFormats.td|  21 +++
 llvm/lib/Target/RISCV/RISCVInstrInfo.td   |  53 ++
 llvm/lib/Target/RISCV/RISCVSchedRocket.td |   1 +
 llvm/lib/Target/RISCV/RISCVSchedSiFive7.td|   1 +
 .../Target/RISCV/RISCVSchedSyntacoreSCR1.td   |   1 +
 llvm/lib/Target/RISCV/RISCVSchedule.td|  14 ++
 llvm/test/CodeGen/RISCV/attributes.ll |   4 +
 .../test/CodeGen/RISCV/rv32zimop-intrinsic.ll |  47 +
 .../test/CodeGen/RISCV/rv64zimop-intrinsic.ll |  96 ++
 llvm/test/MC/RISCV/rv32zimop-invalid.s|   6 +
 llvm/test/MC/RISCV/rvzimop-valid.s|  26 +++
 llvm/unittests/Support/RISCVISAInfoTest.cpp   |   1 +
 22 files changed, 632 insertions(+)
 create mode 100644 clang/test/CodeGen/RISCV/rvb-intrinsics/zimop.c
 create mode 100644 llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll
 create mode 100644 llvm/test/MC/RISCV/rv32zimop-invalid.s
 create mode 100644 llvm/test/MC/RISCV/rvzimop-valid.s

diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def 
b/clang/include/clang/Basic/BuiltinsRISCV.def
index 1528b18c82ead..6ba5288f9cbd1 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -89,5 +89,10 @@ TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh")
 TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl")
 TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl")
 
+TARGET_BUILTIN(__builtin_riscv_mopr_32, "UiUiUi", "nc", "experimental-zimop")
+TARGET_BUILTIN(__builtin_riscv_mopr_64, "UWiUWiUWi", "nc", 
"experimental-zimop,64bit")
+TARGET_BUILTIN(__builtin_riscv_moprr_32, "UiUiUiUi", "nc", 
"experimental-zimop")
+TARGET_BUILTIN(__builtin_riscv_moprr_64, "UWiUWiUWiUWi", "nc", 
"experimental-zimop,64bit")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 0d8b3e4aaad47..11ba665dda938 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -20808,6 +20808,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
   case RISCV::BI__builtin_riscv_clz_64:
   case RISCV::BI__builtin_riscv_ctz_32:
   case RISCV::BI__builtin_riscv_ctz_64:
+  case RISCV::BI__builtin_riscv_mopr_32:
+  case RISCV::BI__builtin_riscv_mopr_64:
+  case RISCV::BI__builtin_riscv_moprr_32:
+  case RISCV::BI__builtin_riscv_moprr_64:
   case RISCV::BI__builtin_riscv_clmul_32:
   case RISCV::BI__builtin_riscv_clmul_64:
   case RISCV::BI__builtin_riscv_clmulh_32:
@@ -20848,6 +20852,36 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
   return Result;
 }
 
+// Zimop
+case RISCV::BI__builtin_riscv_mopr_32:
+case RISCV::BI__builtin_riscv_mopr_64: {
+  unsigned N = cast(Ops[1])->getZExtValue();
+  Function *F = nullptr;
+  if (N <= 1) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr0 + N, {ResultType});
+  } else if (N >= 10 && N <= 19) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr10 + N - 10, {ResultType});
+  } else if (N == 2) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr2, {ResultType});
+  } else if (N >= 20 && N <= 29) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr20 + N - 20, {ResultType});
+  } else if (N == 3) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr3, {ResultType});
+  } else if (N

[llvm] [clang] [RISCV] Add support for experimental Zimop extension (PR #74824)

2023-12-08 Thread via cfe-commits


llvmbot wrote:



@llvm/pr-subscribers-clang

@llvm/pr-subscribers-llvm-ir

Author: Jivan Hakobyan (JivanH)


Changes

This implements experimental support for the Zimop extension as specified here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.

This change adds intrinsics of mop.r.[n] and mop.rr.[n] instructions for Zimop 
extension based on 
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md. 


---

Patch is 39.04 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/74824.diff


22 Files Affected:

- (modified) clang/include/clang/Basic/BuiltinsRISCV.def (+5) 
- (modified) clang/lib/CodeGen/CGBuiltin.cpp (+34) 
- (modified) clang/lib/Sema/SemaChecking.cpp (+8) 
- (added) clang/test/CodeGen/RISCV/rvb-intrinsics/zimop.c (+104) 
- (modified) llvm/docs/RISCVUsage.rst (+3) 
- (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+23) 
- (modified) llvm/lib/Support/RISCVISAInfo.cpp (+2) 
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+5) 
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+171) 
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.h (+6) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrFormats.td (+21) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+53) 
- (modified) llvm/lib/Target/RISCV/RISCVSchedRocket.td (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFive7.td (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVSchedule.td (+14) 
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+4) 
- (added) llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll (+47) 
- (added) llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll (+96) 
- (added) llvm/test/MC/RISCV/rv32zimop-invalid.s (+6) 
- (added) llvm/test/MC/RISCV/rvzimop-valid.s (+26) 
- (modified) llvm/unittests/Support/RISCVISAInfoTest.cpp (+1) 


``diff
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def 
b/clang/include/clang/Basic/BuiltinsRISCV.def
index 1528b18c82ead..6ba5288f9cbd1 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -89,5 +89,10 @@ TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh")
 TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl")
 TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl")
 
+TARGET_BUILTIN(__builtin_riscv_mopr_32, "UiUiUi", "nc", "experimental-zimop")
+TARGET_BUILTIN(__builtin_riscv_mopr_64, "UWiUWiUWi", "nc", 
"experimental-zimop,64bit")
+TARGET_BUILTIN(__builtin_riscv_moprr_32, "UiUiUiUi", "nc", 
"experimental-zimop")
+TARGET_BUILTIN(__builtin_riscv_moprr_64, "UWiUWiUWiUWi", "nc", 
"experimental-zimop,64bit")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 0d8b3e4aaad47..11ba665dda938 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -20808,6 +20808,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
   case RISCV::BI__builtin_riscv_clz_64:
   case RISCV::BI__builtin_riscv_ctz_32:
   case RISCV::BI__builtin_riscv_ctz_64:
+  case RISCV::BI__builtin_riscv_mopr_32:
+  case RISCV::BI__builtin_riscv_mopr_64:
+  case RISCV::BI__builtin_riscv_moprr_32:
+  case RISCV::BI__builtin_riscv_moprr_64:
   case RISCV::BI__builtin_riscv_clmul_32:
   case RISCV::BI__builtin_riscv_clmul_64:
   case RISCV::BI__builtin_riscv_clmulh_32:
@@ -20848,6 +20852,36 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
   return Result;
 }
 
+// Zimop
+case RISCV::BI__builtin_riscv_mopr_32:
+case RISCV::BI__builtin_riscv_mopr_64: {
+  unsigned N = cast(Ops[1])->getZExtValue();
+  Function *F = nullptr;
+  if (N <= 1) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr0 + N, {ResultType});
+  } else if (N >= 10 && N <= 19) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr10 + N - 10, {ResultType});
+  } else if (N == 2) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr2, {ResultType});
+  } else if (N >= 20 && N <= 29) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr20 + N - 20, {ResultType});
+  } else if (N == 3) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr3, {ResultType});
+  } else if (N >= 30 && N <= 31) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr30 + N - 30, {ResultType});
+  } else if (N >= 4 && N <= 9) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr4 + N - 4, {ResultType});
+  } else {
+llvm_unreachable("unexpected builtin ID");
+  }
+  return Builder.CreateCall(F, {Ops[0]}, "");
+}
+case RISCV::BI__builtin_riscv_moprr_32:
+case RISCV::BI__builtin_riscv_moprr_64: {
+  unsigned N = cast(Ops[2])->getZExtValue();
+  Function *F = CGM.getIntrinsic(Intrinsic::riscv_moprr0 + N, 
{ResultType});
+  return Builder.CreateCall(F, {Ops[0], Ops[1]}, "");
+}
 // Zbc
 case RISCV::BI__builti

[llvm] [clang] [RISCV] Add support for experimental Zimop extension (PR #74824)

2023-12-08 Thread via cfe-commits


llvmbot wrote:




@llvm/pr-subscribers-llvm-support

Author: Jivan Hakobyan (JivanH)


Changes

This implements experimental support for the Zimop extension as specified here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.

This change adds intrinsics of mop.r.[n] and mop.rr.[n] instructions for Zimop 
extension based on 
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md. 


---

Patch is 39.08 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/74824.diff


22 Files Affected:

- (modified) clang/include/clang/Basic/BuiltinsRISCV.def (+5) 
- (modified) clang/lib/CodeGen/CGBuiltin.cpp (+34) 
- (modified) clang/lib/Sema/SemaChecking.cpp (+8) 
- (added) clang/test/CodeGen/RISCV/rvb-intrinsics/zimop.c (+104) 
- (modified) llvm/docs/RISCVUsage.rst (+3) 
- (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+23) 
- (modified) llvm/lib/Support/RISCVISAInfo.cpp (+2) 
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+5) 
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+171) 
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.h (+6) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrFormats.td (+21) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+53) 
- (modified) llvm/lib/Target/RISCV/RISCVSchedRocket.td (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFive7.td (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVSchedule.td (+14) 
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+4) 
- (added) llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll (+47) 
- (added) llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll (+96) 
- (added) llvm/test/MC/RISCV/rv32zimop-invalid.s (+6) 
- (added) llvm/test/MC/RISCV/rvzimop-valid.s (+26) 
- (modified) llvm/unittests/Support/RISCVISAInfoTest.cpp (+1) 


``diff
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def 
b/clang/include/clang/Basic/BuiltinsRISCV.def
index 1528b18c82eade..6ba5288f9cbd1f 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -89,5 +89,10 @@ TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh")
 TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl")
 TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl")
 
+TARGET_BUILTIN(__builtin_riscv_mopr_32, "UiUiUi", "nc", "experimental-zimop")
+TARGET_BUILTIN(__builtin_riscv_mopr_64, "UWiUWiUWi", "nc", 
"experimental-zimop,64bit")
+TARGET_BUILTIN(__builtin_riscv_moprr_32, "UiUiUiUi", "nc", 
"experimental-zimop")
+TARGET_BUILTIN(__builtin_riscv_moprr_64, "UWiUWiUWiUWi", "nc", 
"experimental-zimop,64bit")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 0d8b3e4aaad470..11ba665dda938c 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -20808,6 +20808,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
   case RISCV::BI__builtin_riscv_clz_64:
   case RISCV::BI__builtin_riscv_ctz_32:
   case RISCV::BI__builtin_riscv_ctz_64:
+  case RISCV::BI__builtin_riscv_mopr_32:
+  case RISCV::BI__builtin_riscv_mopr_64:
+  case RISCV::BI__builtin_riscv_moprr_32:
+  case RISCV::BI__builtin_riscv_moprr_64:
   case RISCV::BI__builtin_riscv_clmul_32:
   case RISCV::BI__builtin_riscv_clmul_64:
   case RISCV::BI__builtin_riscv_clmulh_32:
@@ -20848,6 +20852,36 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned 
BuiltinID,
   return Result;
 }
 
+// Zimop
+case RISCV::BI__builtin_riscv_mopr_32:
+case RISCV::BI__builtin_riscv_mopr_64: {
+  unsigned N = cast(Ops[1])->getZExtValue();
+  Function *F = nullptr;
+  if (N <= 1) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr0 + N, {ResultType});
+  } else if (N >= 10 && N <= 19) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr10 + N - 10, {ResultType});
+  } else if (N == 2) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr2, {ResultType});
+  } else if (N >= 20 && N <= 29) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr20 + N - 20, {ResultType});
+  } else if (N == 3) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr3, {ResultType});
+  } else if (N >= 30 && N <= 31) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr30 + N - 30, {ResultType});
+  } else if (N >= 4 && N <= 9) {
+F = CGM.getIntrinsic(Intrinsic::riscv_mopr4 + N - 4, {ResultType});
+  } else {
+llvm_unreachable("unexpected builtin ID");
+  }
+  return Builder.CreateCall(F, {Ops[0]}, "");
+}
+case RISCV::BI__builtin_riscv_moprr_32:
+case RISCV::BI__builtin_riscv_moprr_64: {
+  unsigned N = cast(Ops[2])->getZExtValue();
+  Function *F = CGM.getIntrinsic(Intrinsic::riscv_moprr0 + N, 
{ResultType});
+  return Builder.CreateCall(F, {Ops[0], Ops[1]}, "");
+}
 // Zbc
 case RISCV::BI__builtin_riscv_clmul_32:

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/74822

>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/3] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52
---
 clang/docs/ReleaseNotes.rst|  1 +
 clang/test/CodeGen/arm-target-features.c   |  3 +++
 clang/test/Driver/arm-cortex-cpus-2.c  |  3 +++
 clang/test/Misc/target-invalid-cpu-note.c  |  2 +-
 llvm/docs/ReleaseNotes.rst |  2 +-
 llvm/include/llvm/TargetParser/ARMTargetParser.def |  3 +++
 llvm/lib/Target/ARM/ARM.td | 11 +++
 llvm/lib/Target/ARM/ARMSubtarget.cpp   |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h |  1 +
 llvm/lib/TargetParser/Host.cpp |  1 +
 llvm/unittests/TargetParser/TargetParserTest.cpp   |  8 +++-
 11 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c04465819713..6f3b6efbfe08c 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc..ad4bfd45c408b 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f..4bf2b3a50412d 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f..f921c4605bb97 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-a32, cortex-a35, c

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits



@@ -102,7 +102,7 @@ Changes to the AMDGPU Backend
 
 * Implemented :ref:`llvm.get.rounding `
 
-* Added support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs.
+* Added support for Cortex-A520, Cortex-A720, Cortex-X4 and Cortex-M52 CPUs.

jthackray wrote:

Thanks, David. Good spot. I added those new CPUs a month ago, and somehow 
missed they were in the wrong section. Now fixed.

https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [Sema] Implement support for -Wformat-signedness (PR #74440)

2023-12-08 Thread Karl-Johan Karlsson via cfe-commits


https://github.com/karka228 updated 
https://github.com/llvm/llvm-project/pull/74440

>From a80bf9d03f19d48c0aca4af7758dc49516da8825 Mon Sep 17 00:00:00 2001
From: Karl-Johan Karlsson 
Date: Tue, 5 Dec 2023 10:03:00 +0100
Subject: [PATCH 1/5] [Sema] Implement support for -Wformat-signedness

In gcc there exist a modifier option -Wformat-signedness that turns on
additional signedness warnings in the already existing -Wformat warning.

This patch implements that support in clang.
---
 clang/include/clang/AST/FormatString.h|   2 +
 .../include/clang/Basic/DiagnosticOptions.def |   1 +
 clang/include/clang/Driver/Options.td |   3 +
 clang/lib/AST/FormatString.cpp|  29 +++--
 clang/lib/Driver/ToolChains/Clang.cpp |   2 +
 clang/lib/Sema/SemaChecking.cpp   |  26 -
 format-strings-signedness.c   | 107 ++
 7 files changed, 158 insertions(+), 12 deletions(-)
 create mode 100644 format-strings-signedness.c

diff --git a/clang/include/clang/AST/FormatString.h 
b/clang/include/clang/AST/FormatString.h
index 5c4ad9baaef608..c267a32be4d6f4 100644
--- a/clang/include/clang/AST/FormatString.h
+++ b/clang/include/clang/AST/FormatString.h
@@ -264,6 +264,8 @@ class ArgType {
 /// The conversion specifier and the argument type are compatible. For
 /// instance, "%d" and int.
 Match = 1,
+/// The conversion specifier and the argument type have different sign
+MatchSignedness,
 /// The conversion specifier and the argument type are compatible because 
of
 /// default argument promotions. For instance, "%hhd" and int.
 MatchPromotion,
diff --git a/clang/include/clang/Basic/DiagnosticOptions.def 
b/clang/include/clang/Basic/DiagnosticOptions.def
index 6d0c1b14acc120..a9562e7d8dcb0d 100644
--- a/clang/include/clang/Basic/DiagnosticOptions.def
+++ b/clang/include/clang/Basic/DiagnosticOptions.def
@@ -44,6 +44,7 @@ DIAGOPT(Name, Bits, Default)
 #endif
 
 SEMANTIC_DIAGOPT(IgnoreWarnings, 1, 0)   /// -w
+DIAGOPT(FormatSignedness, 1, 0) /// -Wformat-signedness
 DIAGOPT(NoRewriteMacros, 1, 0)  /// -Wno-rewrite-macros
 DIAGOPT(Pedantic, 1, 0) /// -pedantic
 DIAGOPT(PedanticErrors, 1, 0)   /// -pedantic-errors
diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 1d04e4f6e7e6d9..04fdf9a7eb92d6 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -918,6 +918,9 @@ def Wdeprecated : Flag<["-"], "Wdeprecated">, 
Group,
   HelpText<"Enable warnings for deprecated constructs and define 
__DEPRECATED">;
 def Wno_deprecated : Flag<["-"], "Wno-deprecated">, Group,
   Visibility<[ClangOption, CC1Option]>;
+def Wformat_signedness : Flag<["-"], "Wformat-signedness">,
+  Flags<[HelpHidden]>, Visibility<[ClangOption, CC1Option]>,
+  MarshallingInfoFlag>;
 def Wl_COMMA : CommaJoined<["-"], "Wl,">, Visibility<[ClangOption, 
FlangOption]>,
   Flags<[LinkerInput, RenderAsInput]>,
   HelpText<"Pass the comma separated arguments in  to the linker">,
diff --git a/clang/lib/AST/FormatString.cpp b/clang/lib/AST/FormatString.cpp
index e0c9e18cfe3a24..670cde017d3ac2 100644
--- a/clang/lib/AST/FormatString.cpp
+++ b/clang/lib/AST/FormatString.cpp
@@ -409,7 +409,7 @@ ArgType::matchesType(ASTContext &C, QualType argTy) const {
 return Match;
   if (const auto *BT = argTy->getAs()) {
 // Check if the only difference between them is signed vs unsigned
-// if true, we consider they are compatible.
+// if true, return match signedness.
 switch (BT->getKind()) {
   default:
 break;
@@ -419,44 +419,53 @@ ArgType::matchesType(ASTContext &C, QualType argTy) const 
{
 [[fallthrough]];
   case BuiltinType::Char_S:
   case BuiltinType::SChar:
+if (T == C.UnsignedShortTy || T == C.ShortTy)
+  return NoMatchTypeConfusion;
+if (T == C.UnsignedCharTy)
+  return MatchSignedness;
+if (T == C.SignedCharTy)
+  return Match;
+break;
   case BuiltinType::Char_U:
   case BuiltinType::UChar:
 if (T == C.UnsignedShortTy || T == C.ShortTy)
   return NoMatchTypeConfusion;
-if (T == C.UnsignedCharTy || T == C.SignedCharTy)
+if (T == C.UnsignedCharTy)
   return Match;
+if (T == C.SignedCharTy)
+  return MatchSignedness;
 break;
   case BuiltinType::Short:
 if (T == C.UnsignedShortTy)
-  return Match;
+  return MatchSignedness;
 break;
   case BuiltinType::UShort:
 if (T == C.ShortTy)
-  return Match;
+  return MatchSignedness;
 break;
   case BuiltinType::Int:
 if (T == C.UnsignedIntTy)
-  return Match;
+  return MatchSignedness;
 b

[llvm] [clang] [RISCV] Add support for experimental Zimop extension (PR #74824)

2023-12-08 Thread Jivan Hakobyan via cfe-commits


JivanH wrote:

@topperc 
@asb 
@michaelmaitland 
@wangpc-pp 

https://github.com/llvm/llvm-project/pull/74824
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[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits


jthackray wrote:

> Going by the page (didn't see a link to a manual, maybe I missed it), MVE and 
> FPU are optional.
> 
> "Optional Helium technology (M-profile Vector Extension) supporting up to:" 
> "Optional FPU with support for half precision (fp16), single precision (fp32) 
> and double precision (fp64) floating-point operations."
> 
> Is this following a pattern from previous CPUs where these things are 
> optional, but users are expected to pass `+nomve` etc. to disable them? (I 
> don't disagree with that, just want to keep it consistent)

Yes, that's correct. We enable all mandatory and optional architecture 
extensions, with the exception of crypto.

https://github.com/llvm/llvm-project/pull/74822
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[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Green via cfe-commits



@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).

davemgreen wrote:

Is it worth splitting this list into one for -target=aarch64 and another for 
-target=arm?

https://github.com/llvm/llvm-project/pull/74822
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[clang] [llvm] [RISCV] Add support for experimental Zimop extension (PR #74824)

2023-12-08 Thread Yingwei Zheng via cfe-commits


dtcxzyw wrote:

I guess you should split it into patch series.
+ [ ] MC support (and docs)
+ [ ] Sched support
+ [ ] ISel support
+ [ ] Builtin intrinsic support in clang


https://github.com/llvm/llvm-project/pull/74824
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sam Tebbs via cfe-commits



@@ -20,3 +21,23 @@ int16x8_t incompat_neon_smc(int16x8_t splat) 
__arm_streaming_compatible {
   // expected-warning@+1 {{builtin call has undefined behaviour when called 
from a streaming compatible function}}
   return (int16x8_t)__builtin_neon_vqaddq_v((int8x16_t)splat, 
(int8x16_t)splat, 33);
 }
+
+void incompat_sme_norm(svbool_t pg, void const *ptr) __arm_shared_za {
+  // expected-warning@+1 {{builtin call has undefined behaviour when called 
from a non-streaming function}}
+  return __builtin_sme_svld1_hor_za128(0, 0, pg, ptr);

SamTebbs33 wrote:

> nit: returning a `void` value from a `void` function doesn't seem right.

Agreed, I'll fix that.
> Also, is `incompat_sme_norm` testing anything that `incompat_sme_sm` isn't 
> testing?
> Or should this be a test where we'd call a non-streaming SVE/SME builtin from 
> a streaming-function?

Yeah it doesn't look like it is. That would be better!





https://github.com/llvm/llvm-project/pull/74064
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[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Spickett via cfe-commits


DavidSpickett wrote:

> Yes, that's correct. We enable all mandatory and optional architecture 
> extensions, with the exception of crypto.

Cool.

That said then, should CDE be added?
```
Accelerator support 

Optional coprocessor interface (64-bit) supporting up to 8 coprocessor units 
for custom compute accelerators
Optional [Arm Custom 
Instructions](https://developer.arm.com/architectures/instruction-sets/custom-instructions)
``` 

https://github.com/llvm/llvm-project/pull/74822
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sam Tebbs via cfe-commits



@@ -6,20 +6,21 @@
 #include 
 
 __attribute__((target("sme")))
-void test_sme(svbool_t pg, void *ptr) {
+void test_sme(svbool_t pg, void *ptr) __arm_streaming __arm_shared_za {
   svld1_hor_za8(0, 0, pg, ptr);
 }
 
 __attribute__((target("arch=armv8-a+sme")))
-void test_arch_sme(svbool_t pg, void *ptr) {
+void test_arch_sme(svbool_t pg, void *ptr) __arm_streaming __arm_shared_za {
   svld1_hor_vnum_za32(0, 0, pg, ptr, 0);
 }
 
 __attribute__((target("+sme")))
-void test_plus_sme(svbool_t pg, void *ptr) {
+void test_plus_sme(svbool_t pg, void *ptr) __arm_streaming __arm_shared_za {
   svst1_ver_za16(0, 0, pg, ptr);
 }
 
-void undefined(svbool_t pg, void *ptr) {
-  svst1_ver_vnum_za64(0, 0, pg, ptr, 0); // expected-error 
{{'svst1_ver_vnum_za64' needs target feature sme}}
+__attribute__((target("+sme")))
+void undefined(svbool_t pg, void *ptr) __arm_shared_za {
+  svst1_ver_vnum_za64(0, 0, pg, ptr, 0); // expected-warning {{builtin call 
has undefined behaviour when called from a non-streaming function}}

SamTebbs33 wrote:

In a previous review you asked me to do so:

> I think instead you want to compile this test with 
> __attribute__((target("+sme"))) but without the __arm_streaming to ensure you 
> get a diagnostic on the builtin call that the behaviour is undefined when the 
> (parent) function is not a streaming function.

https://github.com/llvm/llvm-project/pull/74064
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[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Green via cfe-commits


davemgreen wrote:

CDE is enabled per decode block and probably doesn't make a lot of sense to 
enable universally. The cde options each pick between two features (CDE vs 
co-processor), and so isn't quite the same as on vs off.

https://github.com/llvm/llvm-project/pull/74822
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sam Tebbs via cfe-commits



@@ -18,7 +18,7 @@
 // CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.zero(i32 0)
 // CHECK-CXX-NEXT:ret void
 //
-void test_svzero_mask_za() {
+__arm_new_za void test_svzero_mask_za() {

SamTebbs33 wrote:

I did try `__arm_shared_za` but got 

> '__arm_shared_za' only applies to non-K&R-style functions

and

> error: '__arm_shared_za' only applies to function types; type here is 'void 
> ()'

https://github.com/llvm/llvm-project/pull/74064
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sam Tebbs via cfe-commits



@@ -3168,11 +3168,70 @@ static void checkArmStreamingBuiltin(Sema &S, CallExpr 
*TheCall,
 << TheCall->getSourceRange() << "streaming compatible";
 return;
   }
+
+  if (FnType == ArmNonStreaming && BuiltinType == ArmStreaming) {
+S.Diag(TheCall->getBeginLoc(), 
diag::warn_attribute_arm_sm_incompat_builtin)
+<< TheCall->getSourceRange() << "non-streaming";
+  }
+}
+
+static bool hasSMEZAState(const FunctionDecl *FD) {
+  if (FD->hasAttr())
+return true;
+  if (const auto *T = FD->getType()->getAs())
+if (T->getAArch64SMEAttributes() & FunctionType::SME_PStateZASharedMask)
+  return true;
+  return false;
+}
+
+static bool hasSMEZAState(unsigned BuiltinID) {
+  switch (BuiltinID) {
+  default:
+return false;
+#define GET_SME_BUILTIN_HAS_ZA_STATE
+#include "clang/Basic/arm_sme_builtins_za_state.inc"
+#undef GET_SME_BUILTIN_HAS_ZA_STATE
+  }
+}
+
+bool Sema::CheckSMEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
+  if (const FunctionDecl *FD = getCurFunctionDecl()) {
+std::optional BuiltinType;

SamTebbs33 wrote:

Sure thing.

https://github.com/llvm/llvm-project/pull/74064
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sam Tebbs via cfe-commits



@@ -1375,6 +1381,12 @@ void SVEEmitter::createHeader(raw_ostream &OS) {
   OS << "#define __aio static __inline__ __attribute__((__always_inline__, "
 "__nodebug__, __overloadable__))\n\n";
 
+  OS << "#ifdef __ARM_FEATURE_SME\n";
+  OS << "#define __asc __attribute__((arm_streaming_compatible))\n";

SamTebbs33 wrote:

Omitting it works for me, cheers.

https://github.com/llvm/llvm-project/pull/74064
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[clang] [AArch64][SME] Warn when using a streaming builtin from a non-streaming function (PR #74064)

2023-12-08 Thread Sam Tebbs via cfe-commits



@@ -500,6 +506,12 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper 
&Records) {
   case GenArmSmeRangeChecks:
 EmitSmeRangeChecks(Records, OS);
 break;
+  case GenArmSmeStreamingAttrs:

SamTebbs33 wrote:

I remember you suggesting that we have the SME and SVE changes in separate PRs 
but I can bring the SVE changes into this one.

https://github.com/llvm/llvm-project/pull/74064
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[clang] [Clang][SVE2p1]Add svboolx2 and svboolx4 types for svcreate, svget, s… (PR #74594)

2023-12-08 Thread via cfe-commits


https://github.com/CarolineConcatto updated 
https://github.com/llvm/llvm-project/pull/74594

>From 037dd51fd05ccd70f10dbf4ca75dd1f45e6548c4 Mon Sep 17 00:00:00 2001
From: Caroline Concatto 
Date: Wed, 6 Dec 2023 14:02:23 +
Subject: [PATCH 1/3] [Clang][SVE2p1]Add svboolx2 and svboolx4 types for
 svcreate, svget, svset

According to the PR#257[1]

[1]ARM-software/acle#257

Co-authored by: Matthew Devereau 
---
 clang/include/clang/Basic/arm_sve.td  | 12 
 .../acle_sve2p1_create2_bool.c| 38 ++
 .../acle_sve2p1_create4_bool.c| 42 +++
 .../acle_sve2p1_get2_bool.c   | 49 +
 .../acle_sve2p1_get4_bool.c   | 72 +++
 .../acle_sve2p1_set2_bool.c   | 52 ++
 .../acle_sve2p1_set4_bool.c   | 66 +
 7 files changed, 331 insertions(+)
 create mode 100644 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_create2_bool.c
 create mode 100644 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_create4_bool.c
 create mode 100644 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_get2_bool.c
 create mode 100644 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_get4_bool.c
 create mode 100644 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_set2_bool.c
 create mode 100644 
clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_set4_bool.c

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 3f69a3df9e616..9d4051a3ed34c 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1296,6 +1296,11 @@ def SVCREATE_3_BF16 : SInst<"svcreate3[_{d}]", "3ddd",  
"b", MergeNone, "", [IsT
 def SVCREATE_4_BF16 : SInst<"svcreate4[_{d}]", "4", "b", MergeNone, "", 
[IsTupleCreate]>;
 }
 
+let TargetGuard = "sve2p1" in {
+  def SVCREATE_2_B : SInst<"svcreate2[_{d}]", "2dd",   "Pc", MergeNone, "", 
[IsTupleCreate]>;
+  def SVCREATE_4_B : SInst<"svcreate4[_{d}]", "4", "Pc", MergeNone, "", 
[IsTupleCreate]>;
+}
+
 

 // Vector insertion and extraction
 def SVGET_2 : SInst<"svget2[_{d}]", "d2i", "csilUcUsUiUlhfd", MergeNone, "", 
[IsTupleGet], [ImmCheck<1, ImmCheck0_1>]>;
@@ -1316,6 +1321,13 @@ def SVSET_3_BF16 : SInst<"svset3[_{d}]", "33id", "b", 
MergeNone, "", [IsTupleSet
 def SVSET_4_BF16 : SInst<"svset4[_{d}]", "44id", "b", MergeNone, "", 
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
 }
 
+let TargetGuard = "sve2p1" in {
+  def SVGET_2_B : SInst<"svget2[_{d}]", "d2i", "Pc", MergeNone, "", 
[IsTupleGet], [ImmCheck<1, ImmCheck0_1>]>;
+  def SVGET_4_B : SInst<"svget4[_{d}]", "d4i", "Pc", MergeNone, "", 
[IsTupleGet], [ImmCheck<1, ImmCheck0_3>]>;
+
+  def SVSET_2_B : SInst<"svset2[_{d}]", "22id", "Pc", MergeNone, "", 
[IsTupleSet], [ImmCheck<1, ImmCheck0_1>]>;
+  def SVSET_4_B : SInst<"svset4[_{d}]", "44id", "Pc", MergeNone, "", 
[IsTupleSet], [ImmCheck<1, ImmCheck0_3>]>;
+}
 

 // SVE2 WhileGE/GT
 let TargetGuard = "sve2" in {
diff --git 
a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_create2_bool.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_create2_bool.c
new file mode 100644
index 0..eb5a19b1d9d32
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_create2_bool.c
@@ -0,0 +1,38 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s \
+// RUN: | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s \
+// RUN: | opt -S -passes=mem2reg,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s 
\
+// RUN: | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x 
c++ %s\
+// RUN: | opt -S -passes=mem2reg,tailcallelim | FileCheck %s 
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -o /dev/null %s
+
+// REQUIRES: aarch64-registered-target
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+// CHECK-LABEL: @test_svcreate2_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:

[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits



@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).

jthackray wrote:

Sure. Something like this?

```
+  --target=arm
+ * Arm Cortex-M52 (cortex-m52).
+
+  --target=aarch64
+ * Arm Cortex-A520 (cortex-a520).
+ * Arm Cortex-A720 (cortex-a720).
+ * Arm Cortex-X4 (cortex-x4).
```

https://github.com/llvm/llvm-project/pull/74822
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[flang] [lldb] [mlir] [polly] [openmp] [compiler-rt] [lld] [clang] [llvm] [VPlan] Compute scalable VF in preheader for induction increment. (PR #74762)

2023-12-08 Thread Florian Hahn via cfe-commits


https://github.com/fhahn closed https://github.com/llvm/llvm-project/pull/74762
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[llvm] [flang] [lld] [polly] [lldb] [openmp] [clang] [compiler-rt] [mlir] [VPlan] Initial modeling of VF * UF as VPValue. (PR #74761)

2023-12-08 Thread Florian Hahn via cfe-commits


https://github.com/fhahn edited https://github.com/llvm/llvm-project/pull/74761
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[clang] [flang] [flang][Driver] Let the linker fail on multiple definitions of main() (PR #73124)

2023-12-08 Thread Andrzej Warzyński via cfe-commits

banach-space wrote:

> It seems like flang-new when being used as a linker with -shared included 
> Fortran_main in the shared library. This seems wrong to me.

I am trying to recall the rationale behind that, but it's been a while :( 

Here's a relevant discussion/bug that hasn't been resolved yet. It might feel 
off-topic at first, but it's in fact a very similar problem - where and when 
should `main` be defined? It would be incredibly helpful if somebody resolved 
that 🙏🏻 .

https://github.com/llvm/llvm-project/pull/73124
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[clang] c1cfa17 - [Clang] Emit TBAA info for enums in C (#73326)

2023-12-08 Thread via cfe-commits


Author: David Sherwood
Date: 2023-12-08T12:58:39Z
New Revision: c1cfa1757c208cd15efec3541aadea6bec52092d

URL: 
https://github.com/llvm/llvm-project/commit/c1cfa1757c208cd15efec3541aadea6bec52092d
DIFF: 
https://github.com/llvm/llvm-project/commit/c1cfa1757c208cd15efec3541aadea6bec52092d.diff

LOG: [Clang] Emit TBAA info for enums in C (#73326)

When emitting TBAA information for enums in C code we currently just
treat the data as an 'omnipotent char'. However, with C strict aliasing
this means we fail to optimise certain cases. For example, in the
SPEC2017 xz benchmark there are structs that contain arrays of enums,
and clang pessmistically assumes that accesses to those enums could
alias with other struct members that have a different type.

According to

https://en.cppreference.com/w/c/language/enum

enums should be treated as 'int' types unless explicitly specified (C23)
or if 'int' would not be large enough to hold all the enumerated values.
In the latter case the compiler is free to choose a suitable integer
that would hold all such values.

When compiling C code this patch generates TBAA information for the enum
by using an equivalent integer of the size clang has already chosen for
the enum. I have ignored C++ for now because the rules are more complex.

New test added here:

  clang/test/CodeGen/tbaa.c

Added: 
clang/test/CodeGen/tbaa.c

Modified: 
clang/docs/ReleaseNotes.rst
clang/lib/CodeGen/CodeGenTBAA.cpp

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c044658197139..2403a3d48a09bb 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -204,6 +204,9 @@ C Language Changes
   number of elements in the flexible array member. This information can improve
   the results of the array bound sanitizer and the
   ``__builtin_dynamic_object_size`` builtin.
+- Enums will now be represented in TBAA metadata using their actual underlying
+  integer type. Previously they were treated as chars, which meant they could
+  alias with all other types.
 
 C23 Feature Support
 ^^^

diff  --git a/clang/lib/CodeGen/CodeGenTBAA.cpp 
b/clang/lib/CodeGen/CodeGenTBAA.cpp
index 5906b14dd93cf0..dc288bc3f6157a 100644
--- a/clang/lib/CodeGen/CodeGenTBAA.cpp
+++ b/clang/lib/CodeGen/CodeGenTBAA.cpp
@@ -196,11 +196,14 @@ llvm::MDNode *CodeGenTBAA::getTypeInfoHelper(const Type 
*Ty) {
   // Enum types are distinct types. In C++ they have "underlying types",
   // however they aren't related for TBAA.
   if (const EnumType *ETy = dyn_cast(Ty)) {
+if (!Features.CPlusPlus)
+  return getTypeInfo(ETy->getDecl()->getIntegerType());
+
 // In C++ mode, types have linkage, so we can rely on the ODR and
 // on their mangled names, if they're external.
 // TODO: Is there a way to get a program-wide unique name for a
 // decl with local linkage or no linkage?
-if (!Features.CPlusPlus || !ETy->getDecl()->isExternallyVisible())
+if (!ETy->getDecl()->isExternallyVisible())
   return getChar();
 
 SmallString<256> OutName;

diff  --git a/clang/test/CodeGen/tbaa.c b/clang/test/CodeGen/tbaa.c
new file mode 100644
index 00..0ab81f60a71941
--- /dev/null
+++ b/clang/test/CodeGen/tbaa.c
@@ -0,0 +1,116 @@
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -no-struct-path-tbaa 
-disable-llvm-passes %s -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -disable-llvm-passes %s 
-emit-llvm -o - | FileCheck %s -check-prefixes=PATH
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -O0 -disable-llvm-passes %s 
-emit-llvm -o - | FileCheck %s -check-prefix=NO-TBAA
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -relaxed-aliasing 
-disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefix=NO-TBAA
+// Test TBAA metadata generated by front-end.
+//
+// NO-TBAA-NOT: !tbaa
+
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned int uint32_t;
+typedef unsigned long long uint64_t;
+
+typedef enum {
+  RED_AUTO_32,
+  GREEN_AUTO_32,
+  BLUE_AUTO_32
+} EnumAuto32;
+
+typedef enum {
+  RED_AUTO_64,
+  GREEN_AUTO_64,
+  BLUE_AUTO_64 = 0x1ull
+} EnumAuto64;
+
+typedef enum : uint16_t {
+  RED_16,
+  GREEN_16,
+  BLUE_16
+} Enum16;
+
+typedef enum : uint8_t {
+  RED_8,
+  GREEN_8,
+  BLUE_8
+} Enum8;
+
+uint32_t g0(EnumAuto32 *E, uint32_t *val) {
+// CHECK-LABEL: define{{.*}} i32 @g0(
+// CHECK: store i32 5, ptr %{{.*}}, align 4, !tbaa [[TAG_i32:!.*]]
+// CHECK: store i32 0, ptr %{{.*}}, align 4, !tbaa [[TAG_i32]]
+// CHECK: load i32, ptr %{{.*}}, align 4, !tbaa [[TAG_i32]]
+// PATH-LABEL: define{{.*}} i32 @g0(
+// PATH: store i32 5, ptr %{{.*}}, align 4, !tbaa [[TAG_i32:!.*]]
+// PATH: store i32 0, ptr %{{.*}}, align 4, !tbaa [[TAG_i32]]
+// PATH: load i32, ptr %{{.*}}, align 4, !tbaa [[TAG_i32]]
+  *val = 5;
+  *E = RED_AUTO_32;
+  return *val;
+}
+
+uint64_t

[clang] [llvm] [Clang] Emit TBAA info for enums in C (PR #73326)

2023-12-08 Thread David Sherwood via cfe-commits


https://github.com/david-arm closed 
https://github.com/llvm/llvm-project/pull/73326
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[clang] [clang-tools-extra] [llvm] [Clang][AArch64] Add fix vector types to header into SVE (PR #73258)

2023-12-08 Thread via cfe-commits


https://github.com/CarolineConcatto updated 
https://github.com/llvm/llvm-project/pull/73258

>From e0f245e8d6a395afac5de471b55358c7b730a170 Mon Sep 17 00:00:00 2001
From: Caroline Concatto 
Date: Wed, 22 Nov 2023 10:03:50 +
Subject: [PATCH 1/7] [Clang][AArch64] Add  fix vector types to header into SVE

This patch is needed for the reduction instructions in sve2.1

It add ta new header to sve with all the fixed vector types.
The new types are only added if neon is not declared.
---
 clang/include/clang/Basic/arm_vector_type.td  |  13 ++
 clang/lib/Headers/CMakeLists.txt  |   3 +
 .../CodeGen/arm-vector_type-params-returns.c  | 113 ++
 clang/utils/TableGen/NeonEmitter.cpp  |  44 +++
 clang/utils/TableGen/SveEmitter.cpp   |   2 +
 clang/utils/TableGen/TableGen.cpp |  15 ++-
 clang/utils/TableGen/TableGenBackends.h   |   1 +
 7 files changed, 188 insertions(+), 3 deletions(-)
 create mode 100644 clang/include/clang/Basic/arm_vector_type.td
 create mode 100644 clang/test/CodeGen/arm-vector_type-params-returns.c

diff --git a/clang/include/clang/Basic/arm_vector_type.td 
b/clang/include/clang/Basic/arm_vector_type.td
new file mode 100644
index 0..5018b0cdfc137
--- /dev/null
+++ b/clang/include/clang/Basic/arm_vector_type.td
@@ -0,0 +1,13 @@
+//===--- arm_vector_type.td - ARM Fixed vector types compiler interface 
---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+//  This file defines the TableGen definitions from which the ARM BF16 header
+//  file will be generated.
+//
+//===--===//
+include "arm_neon_incl.td"
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index 8b1e2bc4afa4d..0beb6ade42920 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -385,6 +385,8 @@ if(ARM IN_LIST LLVM_TARGETS_TO_BUILD OR AArch64 IN_LIST 
LLVM_TARGETS_TO_BUILD)
   clang_generate_header(-gen-arm-mve-header arm_mve.td arm_mve.h)
   # Generate arm_cde.h
   clang_generate_header(-gen-arm-cde-header arm_cde.td arm_cde.h)
+  # Generate arm_vector_type.h
+  clang_generate_header(-gen-arm-vector-type arm_vector_type.td 
arm_vector_type.h)
 
   # Add headers to target specific lists
   list(APPEND arm_common_generated_files
@@ -401,6 +403,7 @@ if(ARM IN_LIST LLVM_TARGETS_TO_BUILD OR AArch64 IN_LIST 
LLVM_TARGETS_TO_BUILD)
 "${CMAKE_CURRENT_BINARY_DIR}/arm_sve.h"
 "${CMAKE_CURRENT_BINARY_DIR}/arm_sme_draft_spec_subject_to_change.h"
 "${CMAKE_CURRENT_BINARY_DIR}/arm_bf16.h"
+"${CMAKE_CURRENT_BINARY_DIR}/arm_vector_type.h"
 )
 endif()
 if(RISCV IN_LIST LLVM_TARGETS_TO_BUILD)
diff --git a/clang/test/CodeGen/arm-vector_type-params-returns.c 
b/clang/test/CodeGen/arm-vector_type-params-returns.c
new file mode 100644
index 0..48c19d01b6257
--- /dev/null
+++ b/clang/test/CodeGen/arm-vector_type-params-returns.c
@@ -0,0 +1,113 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --version 3
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - %s 
| opt -S -passes=mem2reg,sroa | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-disable-O0-optnone -Werror -Wall -o - /dev/null %s
+#include 
+
+// function return types
+// CHECK-LABEL: define dso_local <8 x half> @test_ret_v8f16(
+// CHECK-SAME: <8 x half> noundef returned [[V:%.*]]) local_unnamed_addr 
#[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret <8 x half> [[V]]
+//
+float16x8_t test_ret_v8f16(float16x8_t v) {
+  return v;
+}
+
+// CHECK-LABEL: define dso_local <4 x float> @test_ret_v4f32(
+// CHECK-SAME: <4 x float> noundef returned [[V:%.*]]) local_unnamed_addr 
#[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret <4 x float> [[V]]
+//
+float32x4_t test_ret_v4f32(float32x4_t v) {
+  return v;
+}
+
+// CHECK-LABEL: define dso_local <2 x double> @test_ret_v2f64(
+// CHECK-SAME: <2 x double> noundef returned [[V:%.*]]) local_unnamed_addr 
#[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret <2 x double> [[V]]
+//
+float64x2_t test_ret_v2f64(float64x2_t v) {
+  return v;
+}
+
+// CHECK-LABEL: define dso_local <8 x bfloat> @test_ret_v8bf16(
+// CHECK-SAME: <8 x bfloat> noundef returned [[V:%.*]]) local_unnamed_addr 
#[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret <8 x bfloat> [[V]]
+//
+bfloat16x8_t test_ret_v8bf16(bfloat16x8_t v) {
+  return v;
+}
+
+// CHECK-LABEL: define dso_local <16 x i8> @test_ret_v16s8(
+// CHECK-SAME: <16 x i8> noundef returned [[V:%.*]]) local_unnamed_addr 
#[[ATTR0]] {
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret <16 x i8> [[

[llvm] [clang] [flang] [NFC][AMDGPU] Move address space enum to LLVM directory (PR #73944)

2023-12-08 Thread Dominik Adamski via cfe-commits



@@ -0,0 +1,31 @@
+//=== AMDGPUAddrSpace.h -*- C++ 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+/// \file
+/// AMDGPU address space definition
+///
+//
+//===--===//
+
+#ifndef LLVM_SUPPORT_AMDGPUADDRSPACE_H
+#define LLVM_SUPPORT_AMDGPUADDRSPACE_H
+
+namespace llvm {
+namespace AMDGPU {
+enum class AddrSpace {

DominikAdamski wrote:

@arsenm done. I unified the clang enum with LLVM enum. I haven't modified the 
names of LLVM enum and I haven't introduced `enum class` instead of `AMDGPUAS 
namespace`. Please let me know if is ok for you.

https://github.com/llvm/llvm-project/pull/73944
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[clang] [Clang][SVE2p1]Add svboolx2 and svboolx4 types for svcreate, svget, s… (PR #74594)

2023-12-08 Thread Kerry McLaughlin via cfe-commits


https://github.com/kmclaughlin-arm approved this pull request.


https://github.com/llvm/llvm-project/pull/74594
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[clang] [Clang][C++20] Implement constexpr std::bit_cast for bit-fields (& [Sema] Print more static_assert exprs) (PR #74775)

2023-12-08 Thread via cfe-commits



@@ -49,19 +48,33 @@
 #include "clang/AST/OptionalDiagnostic.h"
 #include "clang/AST/RecordLayout.h"
 #include "clang/AST/StmtVisitor.h"
+#include "clang/AST/Type.h"
 #include "clang/AST/TypeLoc.h"
 #include "clang/Basic/Builtins.h"
-#include "clang/Basic/DiagnosticSema.h"
+#include "clang/Basic/DiagnosticAST.h"
 #include "clang/Basic/TargetInfo.h"
 #include "llvm/ADT/APFixedPoint.h"
+#include "llvm/ADT/APInt.h"
+#include "llvm/ADT/APSInt.h"
 #include "llvm/ADT/SmallBitVector.h"
+#include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/IR/LLVMContext.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/SaveAndRestore.h"
+#include "llvm/Support/SwapByteOrder.h"
 #include "llvm/Support/TimeProfiler.h"
 #include "llvm/Support/raw_ostream.h"
+#include 
+#include 
+#include 
 #include 
 #include 
+#include 
+#include 
 #include 

sethp wrote:

Not entirely sure how I'm getting away with this on Linux/gcc, but it looks 
like the CI build failed because of a missing #include:

```suggestion
#include 
#include 
```

https://github.com/llvm/llvm-project/pull/74775
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[clang] [Clang][C++20] Implement constexpr std::bit_cast for bit-fields (& [Sema] Print more static_assert exprs) (PR #74775)

2023-12-08 Thread Timm Baeder via cfe-commits


tbaederr wrote:

I don't have the capacity to review this properly, but the changes to the 
`static_assert` diagnostics should be split out IMO.

https://github.com/llvm/llvm-project/pull/74775
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[clang] [llvm] [AMDGPU] GFX12: Add Split Workgroup Barrier (PR #74836)

2023-12-08 Thread via cfe-commits


llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Mariusz Sikora (mariusz-sikora-at-amd)


Changes



---

Patch is 112.63 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/74836.diff


27 Files Affected:

- (modified) clang/include/clang/Basic/BuiltinsAMDGPU.def (+16) 
- (added) clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-err.cl (+24) 
- (added) clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl (+174) 
- (modified) llvm/include/llvm/IR/IntrinsicsAMDGPU.td (+39) 
- (modified) llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (+152) 
- (modified) llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h (+3) 
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (+44-1) 
- (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+11-1) 
- (modified) llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (+11) 
- (modified) llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h (+1) 
- (modified) llvm/lib/Target/AMDGPU/GCNSubtarget.h (+3) 
- (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp (+1) 
- (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp (+1) 
- (modified) llvm/lib/Target/AMDGPU/SIDefines.h (+9) 
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+111-1) 
- (modified) llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp (+5) 
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+8-1) 
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.td (+7) 
- (modified) llvm/lib/Target/AMDGPU/SOPInstructions.td (+112) 
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (+1) 
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp (+10) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll (+77) 
- (added) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll (+1366) 
- (modified) llvm/test/MC/AMDGPU/gfx12_asm_sop1.s (+45) 
- (modified) llvm/test/MC/AMDGPU/gfx12_asm_sopp.s (+9) 
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt (+53) 
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt (+9) 


``diff
diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def 
b/clang/include/clang/Basic/BuiltinsAMDGPU.def
index 8b59b3790d7bc6..7465f13d552d6e 100644
--- a/clang/include/clang/Basic/BuiltinsAMDGPU.def
+++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def
@@ -406,5 +406,21 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_fp8_f32, "iffiIb", 
"nc", "fp8-insts")
 TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf8_f32, "ifiiIi", "nc", "fp8-insts")
 TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-insts")
 
+//===--===//
+// GFX12+ only builtins.
+//===--===//
+
+TARGET_BUILTIN(__builtin_amdgcn_s_barrier_signal, "vIi", "n", "gfx12-insts")
+TARGET_BUILTIN(__builtin_amdgcn_s_barrier_signal_var, "vi", "n", "gfx12-insts")
+TARGET_BUILTIN(__builtin_amdgcn_s_barrier_wait, "vIs", "n", "gfx12-insts")
+TARGET_BUILTIN(__builtin_amdgcn_s_barrier_signal_isfirst, "bIi", "n", 
"gfx12-insts")
+TARGET_BUILTIN(__builtin_amdgcn_s_barrier_signal_isfirst_var, "bi", "n", 
"gfx12-insts")
+TARGET_BUILTIN(__builtin_amdgcn_s_barrier_init, "vii", "n", "gfx12-insts")
+TARGET_BUILTIN(__builtin_amdgcn_s_barrier_join, "vi", "n", "gfx12-insts")
+TARGET_BUILTIN(__builtin_amdgcn_s_wakeup_barrier, "vi", "n", "gfx12-insts")
+TARGET_BUILTIN(__builtin_amdgcn_s_barrier_leave, "b", "n", "gfx12-insts")
+TARGET_BUILTIN(__builtin_amdgcn_s_get_barrier_state, "Uii", "n", "gfx12-insts")
+
+
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-err.cl 
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-err.cl
new file mode 100644
index 00..5e0153c42825e3
--- /dev/null
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-err.cl
@@ -0,0 +1,24 @@
+// REQUIRES: amdgpu-registered-target
+
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1200 -verify 
-S -emit-llvm -o - %s
+
+kernel void builtins_amdgcn_s_barrier_signal_err(global int* in, global int* 
out, int barrier) {
+
+  __builtin_amdgcn_s_barrier_signal(barrier); // expected-error 
{{'__builtin_amdgcn_s_barrier_signal' must be a constant integer}}
+  __builtin_amdgcn_s_barrier_wait(-1);
+  *out = *in;
+}
+
+kernel void builtins_amdgcn_s_barrier_wait_err(global int* in, global int* 
out, int barrier) {
+
+  __builtin_amdgcn_s_barrier_signal(-1);
+  __builtin_amdgcn_s_barrier_wait(barrier); // expected-error 
{{'__builtin_amdgcn_s_barrier_wait' must be a constant integer}}
+  *out = *in;
+}
+
+kernel void builtins_amdgcn_s_barrier_signal_isfirst_err(global int* in, 
global int* out, int barrier) {
+
+  __builtin_amdgcn_s_barrier_signal_isfirst(barrier); // expected-error 
{{'__builtin_amdgcn_s_barrier_signal_isfirst' must be a constant integer}}
+  __builtin_amdgcn_s_barrier_wait(-1);
+  *out = *in;
+}
diff --git a/clang/test/CodeGenOpenCL/builtins

[clang] d5e2cbd - [clang][Interp] Implement builtin_expect (#69713)

2023-12-08 Thread via cfe-commits


Author: Timm Baeder
Date: 2023-12-08T14:46:25+01:00
New Revision: d5e2cbd01a17edeb56aad2f161c76ce3f854676f

URL: 
https://github.com/llvm/llvm-project/commit/d5e2cbd01a17edeb56aad2f161c76ce3f854676f
DIFF: 
https://github.com/llvm/llvm-project/commit/d5e2cbd01a17edeb56aad2f161c76ce3f854676f.diff

LOG: [clang][Interp] Implement builtin_expect (#69713)

Added: 


Modified: 
clang/lib/AST/Interp/InterpBuiltin.cpp
clang/test/AST/Interp/builtin-functions.cpp
clang/test/Sema/builtin-expect-with-probability.cpp

Removed: 




diff  --git a/clang/lib/AST/Interp/InterpBuiltin.cpp 
b/clang/lib/AST/Interp/InterpBuiltin.cpp
index 9cf206ecc212ad..4384ace6b6be5e 100644
--- a/clang/lib/AST/Interp/InterpBuiltin.cpp
+++ b/clang/lib/AST/Interp/InterpBuiltin.cpp
@@ -34,6 +34,19 @@ PrimType getIntPrimType(const InterpState &S) {
   llvm_unreachable("Int isn't 16 or 32 bit?");
 }
 
+PrimType getLongPrimType(const InterpState &S) {
+  const TargetInfo &TI = S.getCtx().getTargetInfo();
+  unsigned LongWidth = TI.getLongWidth();
+
+  if (LongWidth == 64)
+return PT_Sint64;
+  else if (LongWidth == 32)
+return PT_Sint32;
+  else if (LongWidth == 16)
+return PT_Sint16;
+  llvm_unreachable("long isn't 16, 32 or 64 bit?");
+}
+
 /// Peek an integer value from the stack into an APSInt.
 static APSInt peekToAPSInt(InterpStack &Stk, PrimType T, size_t Offset = 0) {
   if (Offset == 0)
@@ -110,6 +123,19 @@ static void pushAPSInt(InterpState &S, const APSInt &Val) {
   }
 }
 
+/// Pushes \p Val to the stack, as a target-dependent 'long'.
+static void pushLong(InterpState &S, int64_t Val) {
+  PrimType LongType = getLongPrimType(S);
+  if (LongType == PT_Sint64)
+S.Stk.push>(Integral<64, true>::from(Val));
+  else if (LongType == PT_Sint32)
+S.Stk.push>(Integral<32, true>::from(Val));
+  else if (LongType == PT_Sint16)
+S.Stk.push>(Integral<16, true>::from(Val));
+  else
+llvm_unreachable("Long isn't 16, 32 or 64 bit?");
+}
+
 static void pushSizeT(InterpState &S, uint64_t Val) {
   const TargetInfo &TI = S.getCtx().getTargetInfo();
   unsigned SizeTWidth = TI.getTypeWidth(TI.getSizeType());
@@ -533,6 +559,26 @@ static bool interp__builtin_classify_type(InterpState &S, 
CodePtr OpPC,
   return true;
 }
 
+// __builtin_expect(long, long)
+// __builtin_expect_with_probability(long, long, double)
+static bool interp__builtin_expect(InterpState &S, CodePtr OpPC,
+   const InterpFrame *Frame,
+   const Function *Func, const CallExpr *Call) 
{
+  // The return value is simply the value of the first parameter.
+  // We ignore the probability.
+  unsigned NumArgs = Call->getNumArgs();
+  assert(NumArgs == 2 || NumArgs == 3);
+
+  PrimType ArgT = *S.getContext().classify(Call->getArg(0)->getType());
+  unsigned Offset = align(primSize(getLongPrimType(S))) * 2;
+  if (NumArgs == 3)
+Offset += align(primSize(PT_Float));
+
+  APSInt Val = peekToAPSInt(S.Stk, ArgT, Offset);
+  pushLong(S, Val.getSExtValue());
+  return true;
+}
+
 bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const Function *F,
   const CallExpr *Call) {
   InterpFrame *Frame = S.Current;
@@ -702,6 +748,12 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const 
Function *F,
   return false;
 break;
 
+  case Builtin::BI__builtin_expect:
+  case Builtin::BI__builtin_expect_with_probability:
+if (!interp__builtin_expect(S, OpPC, Frame, F, Call))
+  return false;
+break;
+
   default:
 return false;
   }

diff  --git a/clang/test/AST/Interp/builtin-functions.cpp 
b/clang/test/AST/Interp/builtin-functions.cpp
index 0726dab37cb4eb..35a1f9a75092a0 100644
--- a/clang/test/AST/Interp/builtin-functions.cpp
+++ b/clang/test/AST/Interp/builtin-functions.cpp
@@ -331,3 +331,11 @@ namespace bitreverse {
   char bitreverse3[__builtin_bitreverse32(0x12345678) == 0x1E6A2C48 ? 1 : -1];
   char bitreverse4[__builtin_bitreverse64(0x0123456789ABCDEFULL) == 
0xF7B3D591E6A2C480 ? 1 : -1];
 }
+
+namespace expect {
+  constexpr int a() {
+return 12;
+  }
+  static_assert(__builtin_expect(a(),1) == 12, "");
+  static_assert(__builtin_expect_with_probability(a(), 1, 1.0) == 12, "");
+}

diff  --git a/clang/test/Sema/builtin-expect-with-probability.cpp 
b/clang/test/Sema/builtin-expect-with-probability.cpp
index 2b72c7b27ae93e..c55cde84b25483 100644
--- a/clang/test/Sema/builtin-expect-with-probability.cpp
+++ b/clang/test/Sema/builtin-expect-with-probability.cpp
@@ -1,4 +1,5 @@
 // RUN: %clang_cc1 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -fsyntax-only -verify 
-fexperimental-new-constant-interpreter %s
 
 __attribute__((noreturn)) extern void bar();
 



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[clang] [clang][Interp] Implement builtin_expect (PR #69713)

2023-12-08 Thread Timm Baeder via cfe-commits


https://github.com/tbaederr closed 
https://github.com/llvm/llvm-project/pull/69713
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[clang] [AArch64][SME2] Add PEXT, PSEL builtins for SME2 (PR #72827)

2023-12-08 Thread Dinar Temirbulatov via cfe-commits


https://github.com/dtemirbulatov updated 
https://github.com/llvm/llvm-project/pull/72827

>From 7aa69c9cb936b3883de7922f72ed9417be5a16f5 Mon Sep 17 00:00:00 2001
From: Dinar Temirbulatov 
Date: Mon, 20 Nov 2023 07:04:18 +
Subject: [PATCH 1/4] [AArch64][SME2] Add PEXT, PSEL builtins for SME2

This change enables PEXT, PSEL builtins for SME2 target.
---
 clang/include/clang/Basic/arm_sve.td  |  30 +--
 .../acle_sve2p1_pext.c| 207 +-
 .../acle_sve2p1_psel.c|   5 +
 3 files changed, 218 insertions(+), 24 deletions(-)

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 40e474d5f0a8f4..96c5ac366574bf 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1859,19 +1859,28 @@ def SVBGRP   : SInst<"svbgrp[_{d}]",   "ddd", 
"UcUsUiUl", MergeNone, "aarch64_sv
 def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", "UcUsUiUl", MergeNone, 
"aarch64_sve_bgrp_x">;
 }
 
+let TargetGuard = "sve2p1|sme" in {
+def SVPSEL_B : SInst<"svpsel_lane_b8",  "PPPm", "Pc", MergeNone, "", 
[IsStreamingCompatible], []>;
+def SVPSEL_H : SInst<"svpsel_lane_b16", "PPPm", "Ps", MergeNone, "", 
[IsStreamingCompatible], []>;
+def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "", 
[IsStreamingCompatible], []>;
+def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "", 
[IsStreamingCompatible], []>;
+}
+
+let TargetGuard = "sve2p1|sme2" in {
+def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8",  "}}Pm", "Pc", MergeNone, 
"", [IsStreamingCompatible], []>;
+def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone, 
"", [IsStreamingCompatible], []>;
+def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone, 
"", [IsStreamingCompatible], []>;
+def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone, 
"", [IsStreamingCompatible], []>;
+
+def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>;
+def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl", 
MergeNone, "aarch64_sve_pext_x2", [IsStreamingCompatible], [ImmCheck<1, 
ImmCheck0_1>]>;
+}
+
 let TargetGuard = "sve2p1" in {
 def SVFCLAMP   : SInst<"svclamp[_{d}]", "", "hfd", MergeNone, 
"aarch64_sve_fclamp", [], []>;
 def SVPTRUE_COUNT  : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone, 
"aarch64_sve_ptrue_{d}", [IsOverloadNone], []>;
 def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "", 
[IsOverloadNone]>;
 
-def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_pext", [], [ImmCheck<1, ImmCheck0_3>]>;
-def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl", 
MergeNone, "aarch64_sve_pext_x2", [], [ImmCheck<1, ImmCheck0_1>]>;
-
-def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8",  "}}Pm", "Pc", MergeNone, 
"", [], []>;
-def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone, 
"", [], []>;
-def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone, 
"", [], []>;
-def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone, 
"", [], []>;
-
 def SVWHILEGE_COUNT  : SInst<"svwhilege_{d}",  "}lli", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilege_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
 def SVWHILEGT_COUNT  : SInst<"svwhilegt_{d}",  "}lli", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilegt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
 def SVWHILELE_COUNT  : SInst<"svwhilele_{d}",  "}lli", "QcQsQiQl", MergeNone, 
"aarch64_sve_whilele_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
@@ -1971,11 +1980,6 @@ let TargetGuard = "sve2p1" in {
 def SVSCLAMP : SInst<"svclamp[_{d}]", "", "csil", MergeNone, 
"aarch64_sve_sclamp", [], []>;
 def SVUCLAMP : SInst<"svclamp[_{d}]", "", "UcUsUiUl", MergeNone, 
"aarch64_sve_uclamp", [], []>;
 
-def SVPSEL_B : SInst<"svpsel_lane_b8",  "PPPm", "Pc", MergeNone, "", [], []>;
-def SVPSEL_H : SInst<"svpsel_lane_b16", "PPPm", "Ps", MergeNone, "", [], []>;
-def SVPSEL_S : SInst<"svpsel_lane_b32", "PPPm", "Pi", MergeNone, "", [], []>;
-def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "", [], []>;
-
 def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone, 
"aarch64_sve_cntp_{d}", [IsOverloadNone], [ImmCheck<1, ImmCheck2_4_Mul2>]>;
 
 defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c 
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
index fe15d5a9db81f2..76603e384b99ca 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pext.c
@@ -1,10 +1,17 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: aarch64-registered-

[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/74822

>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/4] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52
---
 clang/docs/ReleaseNotes.rst|  1 +
 clang/test/CodeGen/arm-target-features.c   |  3 +++
 clang/test/Driver/arm-cortex-cpus-2.c  |  3 +++
 clang/test/Misc/target-invalid-cpu-note.c  |  2 +-
 llvm/docs/ReleaseNotes.rst |  2 +-
 llvm/include/llvm/TargetParser/ARMTargetParser.def |  3 +++
 llvm/lib/Target/ARM/ARM.td | 11 +++
 llvm/lib/Target/ARM/ARMSubtarget.cpp   |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h |  1 +
 llvm/lib/TargetParser/Host.cpp |  1 +
 llvm/unittests/TargetParser/TargetParserTest.cpp   |  8 +++-
 11 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c044658197139..6f3b6efbfe08c0 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc1..ad4bfd45c408b5 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f3..4bf2b3a50412d0 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f2..f921c4605bb976 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-a32, corte

[clang] [AArch64][SME2] Add PEXT, PSEL builtins for SME2 (PR #72827)

2023-12-08 Thread Sander de Smalen via cfe-commits


https://github.com/sdesmalen-arm approved this pull request.


https://github.com/llvm/llvm-project/pull/72827
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[clang] [AArch64][SME2] Add PEXT, PSEL builtins for SME2 (PR #72827)

2023-12-08 Thread Sander de Smalen via cfe-commits



@@ -1,13 +1,19 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +sme2 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme 
-target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +sme2 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s 
-check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -DTEST_SME2 -target-feature 
+sve -target-feature +sme2 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S 
-O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -DTEST_SME2 -target-feature 
+sve -target-feature +sme2 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck 
%s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -DTEST_SME2 -target-feature 
+sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s

sdesmalen-arm wrote:

nit: I think it's sufficient to test these two RUN lines with only `+sve2p1`.

https://github.com/llvm/llvm-project/pull/72827
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[clang] [AArch64][SME2] Add PEXT, PSEL builtins for SME2 (PR #72827)

2023-12-08 Thread Sander de Smalen via cfe-commits


https://github.com/sdesmalen-arm edited 
https://github.com/llvm/llvm-project/pull/72827
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[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Spickett via cfe-commits



@@ -896,9 +896,13 @@ Arm and AArch64 Support
 
   Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
 
-  * Arm Cortex-A520 (cortex-a520).
-  * Arm Cortex-A720 (cortex-a720).
-  * Arm Cortex-X4 (cortex-x4).
+  --target=arm
+ * Arm Cortex-M52 (cortex-m52).
+
+  --target=aarch64
+ * Arm Cortex-A520 (cortex-a520).
+ * Arm Cortex-A720 (cortex-a720).
+ * Arm Cortex-X4 (cortex-x4).

DavidSpickett wrote:

When rendered into HTML, this may not turn out the way you expect it to.

You can add `LLVM_BUILD_DOCS` and `SPHINX_OUTPUT_HTML` to your cmake config 
then build them with the `docs-clang-html` target 
(https://llvm.org/docs/CMake.html).

Also github can render the file, but I'm not sure if the result is always going 
to be the same.

https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Spickett via cfe-commits



@@ -896,9 +896,13 @@ Arm and AArch64 Support
 
   Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
 
-  * Arm Cortex-A520 (cortex-a520).
-  * Arm Cortex-A720 (cortex-a720).
-  * Arm Cortex-X4 (cortex-x4).
+  --target=arm
+ * Arm Cortex-M52 (cortex-m52).
+
+  --target=aarch64
+ * Arm Cortex-A520 (cortex-a520).
+ * Arm Cortex-A720 (cortex-a720).
+ * Arm Cortex-X4 (cortex-x4).

DavidSpickett wrote:

And if you checked that already, I'm probably just seeing a weird artifact in 
Github's rendering of it.

https://github.com/llvm/llvm-project/pull/74822
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Green via cfe-commits



@@ -896,9 +896,13 @@ Arm and AArch64 Support
 
   Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
 
-  * Arm Cortex-A520 (cortex-a520).
-  * Arm Cortex-A720 (cortex-a720).
-  * Arm Cortex-X4 (cortex-x4).
+  --target=arm
+ * Arm Cortex-M52 (cortex-m52).
+
+  --target=aarch64
+ * Arm Cortex-A520 (cortex-a520).
+ * Arm Cortex-A720 (cortex-a720).
+ * Arm Cortex-X4 (cortex-x4).

davemgreen wrote:

Maybe just "For Arm:" and "For AArch64:" if the --target is awkward. Otherwise 
this LGTM if David Agrees

https://github.com/llvm/llvm-project/pull/74822
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[clang] [clang][Interp] Implement __builtin_rotate{right, left} (PR #72984)

2023-12-08 Thread Timm Baeder via cfe-commits



@@ -331,3 +331,17 @@ namespace bitreverse {
   char bitreverse3[__builtin_bitreverse32(0x12345678) == 0x1E6A2C48 ? 1 : -1];
   char bitreverse4[__builtin_bitreverse64(0x0123456789ABCDEFULL) == 
0xF7B3D591E6A2C480 ? 1 : -1];
 }
+
+namespace rotateleft {
+  char rotateleft1[__builtin_rotateleft8(0x01, 5) == 0x20 ? 1 : -1];
+  char rotateleft2[__builtin_rotateleft16(0x3210, 11) == 0x8190 ? 1 : -1];
+  char rotateleft3[__builtin_rotateleft32(0x76543210, 22) == 0x841D950C ? 1 : 
-1];
+  char rotateleft4[__builtin_rotateleft64(0xFEDCBA9876543210ULL, 55) == 
0x87F6E5D4C3B2A19ULL ? 1 : -1];
+}
+
+namespace rotateright {
+  char rotateright1[__builtin_rotateright8(0x01, 5) == 0x08 ? 1 : -1];
+  char rotateright2[__builtin_rotateright16(0x3210, 11) == 0x4206 ? 1 : -1];
+  char rotateright3[__builtin_rotateright32(0x76543210, 22) == 0x50C841D9 ? 1 
: -1];
+  char rotateright4[__builtin_rotateright64(0xFEDCBA9876543210ULL, 55) == 
0xB97530ECA86421FDULL ? 1 : -1];

tbaederr wrote:

They builtin functions are defined as having unsigned parameters, so does a 
test like that make sense?

https://github.com/llvm/llvm-project/pull/72984
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[clang] [clang][Interp] Add inline descriptor to global variables (PR #72892)

2023-12-08 Thread Timm Baeder via cfe-commits

Timm =?utf-8?q?B=C3=A4der?= ,
Timm =?utf-8?q?B=C3=A4der?= 
Message-ID:
In-Reply-To: 


tbaederr wrote:

Ping

https://github.com/llvm/llvm-project/pull/72892
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[clang] [clang][Interp] Implement IntegralAP::{div, rem} (PR #72614)

2023-12-08 Thread Timm Baeder via cfe-commits


tbaederr wrote:

Ping

https://github.com/llvm/llvm-project/pull/72614
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[clang] [clang][Interp] Diagnose reads from non-const global variables (PR #71919)

2023-12-08 Thread Timm Baeder via cfe-commits

Timm =?utf-8?q?B=C3=A4der?= 
Message-ID:
In-Reply-To: 


tbaederr wrote:

Ping

https://github.com/llvm/llvm-project/pull/71919
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[clang] [clang][Interp] Add an EvaluationResult class (PR #71315)

2023-12-08 Thread Timm Baeder via cfe-commits

Timm =?utf-8?q?B=C3=A4der?= 
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tbaederr wrote:

Ping

https://github.com/llvm/llvm-project/pull/71315
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[clang] [clang][Interp] Fix float->int casts overflowing (PR #72658)

2023-12-08 Thread Timm Baeder via cfe-commits


tbaederr wrote:

Ping

https://github.com/llvm/llvm-project/pull/72658
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[clang] [clang][Interp] Implement inc/dec for IntegralAP (PR #69597)

2023-12-08 Thread Timm Baeder via cfe-commits

Timm =?utf-8?q?B=C3=A4der?= 
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tbaederr wrote:

Ping

https://github.com/llvm/llvm-project/pull/69597
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[clang] [clang][Interp] Handle std::move etc. builtins (PR #70772)

2023-12-08 Thread Timm Baeder via cfe-commits

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tbaederr wrote:

Ping

https://github.com/llvm/llvm-project/pull/70772
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[clang] [clang][Interp] Decay arrays to the first element (PR #72660)

2023-12-08 Thread Timm Baeder via cfe-commits


tbaederr wrote:

Ping

https://github.com/llvm/llvm-project/pull/72660
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[clang] [clang][Interp] IndirectMember initializers (PR #69900)

2023-12-08 Thread Timm Baeder via cfe-commits


tbaederr wrote:

Ping

https://github.com/llvm/llvm-project/pull/69900
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[clang] [clang][Interp] Use array filler expression (PR #72865)

2023-12-08 Thread Timm Baeder via cfe-commits


tbaederr wrote:

Ping

https://github.com/llvm/llvm-project/pull/72865
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[llvm] [clang] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread David Spickett via cfe-commits



@@ -896,9 +896,13 @@ Arm and AArch64 Support
 
   Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
 
-  * Arm Cortex-A520 (cortex-a520).
-  * Arm Cortex-A720 (cortex-a720).
-  * Arm Cortex-X4 (cortex-x4).
+  --target=arm
+ * Arm Cortex-M52 (cortex-m52).
+
+  --target=aarch64
+ * Arm Cortex-A520 (cortex-a520).
+ * Arm Cortex-A720 (cortex-a720).
+ * Arm Cortex-X4 (cortex-x4).

DavidSpickett wrote:

That's certainly easier to format, so go with that. Wouldn't be surprised if 
`--` looked to RST like a formatting directive.

https://github.com/llvm/llvm-project/pull/74822
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[clang] 9b154da - [OpenACC][NFC] Change Readonly token check to use isSpecialTokenKind

2023-12-08 Thread via cfe-commits


Author: erichkeane
Date: 2023-12-08T06:14:21-08:00
New Revision: 9b154dad5b465bfc45b962488682ed4f95e049a3

URL: 
https://github.com/llvm/llvm-project/commit/9b154dad5b465bfc45b962488682ed4f95e049a3
DIFF: 
https://github.com/llvm/llvm-project/commit/9b154dad5b465bfc45b962488682ed4f95e049a3.diff

LOG: [OpenACC][NFC] Change Readonly token check to use isSpecialTokenKind

As brought up in a previous review, instead of checking a token's
spelling in text everywhere, we added a 'special token kind'.
This adds the only other use of a special kind to use the checking
function instead.

Added: 


Modified: 
clang/lib/Parse/ParseOpenACC.cpp

Removed: 




diff  --git a/clang/lib/Parse/ParseOpenACC.cpp 
b/clang/lib/Parse/ParseOpenACC.cpp
index 40b53dd180c79..83a91d44f73fa 100644
--- a/clang/lib/Parse/ParseOpenACC.cpp
+++ b/clang/lib/Parse/ParseOpenACC.cpp
@@ -84,6 +84,7 @@ OpenACCAtomicKind getOpenACCAtomicKind(Token Tok) {
 }
 
 enum class OpenACCSpecialTokenKind {
+  ReadOnly,
   DevNum,
   Queues,
 };
@@ -93,6 +94,8 @@ bool isOpenACCSpecialToken(OpenACCSpecialTokenKind Kind, 
Token Tok) {
 return false;
 
   switch (Kind) {
+  case OpenACCSpecialTokenKind::ReadOnly:
+return Tok.getIdentifierInfo()->isStr("readonly");
   case OpenACCSpecialTokenKind::DevNum:
 return Tok.getIdentifierInfo()->isStr("devnum");
   case OpenACCSpecialTokenKind::Queues:
@@ -422,8 +425,7 @@ void Parser::ParseOpenACCCacheVarList() {
   // specifications.  First, see if we have `readonly:`, else we back-out and
   // treat it like the beginning of a reference to a potentially-existing
   // `readonly` variable.
-  if (getCurToken().is(tok::identifier) &&
-  getCurToken().getIdentifierInfo()->isStr("readonly") &&
+  if (isOpenACCSpecialToken(OpenACCSpecialTokenKind::ReadOnly, Tok) &&
   NextToken().is(tok::colon)) {
 // Consume both tokens.
 ConsumeToken();



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[clang] [lldb] fixing issue #64441 (PR #74814)

2023-12-08 Thread Felipe de Azevedo Piovezan via cfe-commits



@@ -56,10 +56,10 @@ namespace Foo = A::B;   // namespace alias
 
 using Foo::myfunc;  // using declaration
 
-using namespace Foo;// using directive
+//removing namespace foo; for quality naming 

felipepiovezan wrote:

Hi @jeevanghimire, please note that this is a test, so we must ensure that LLDB 
does the right thing regardless of the input it receives, even if said input is 
not considered best practices. The test was likely created to either ensure 
LLDB works in the case, or because it didn't use to work and  someone created a 
test at the same time the fix was done.

 As such, I don't think we should change this.


https://github.com/llvm/llvm-project/pull/74814
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[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits


https://github.com/jthackray updated 
https://github.com/llvm/llvm-project/pull/74822

>From 5925f180b6a8623ae1f1497f89c1f6ef35517e4a Mon Sep 17 00:00:00 2001
From: Jonathan Thackray 
Date: Thu, 23 Nov 2023 15:54:01 +
Subject: [PATCH 1/5] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
  https://developer.arm.com/processors/cortex-m52
---
 clang/docs/ReleaseNotes.rst|  1 +
 clang/test/CodeGen/arm-target-features.c   |  3 +++
 clang/test/Driver/arm-cortex-cpus-2.c  |  3 +++
 clang/test/Misc/target-invalid-cpu-note.c  |  2 +-
 llvm/docs/ReleaseNotes.rst |  2 +-
 llvm/include/llvm/TargetParser/ARMTargetParser.def |  3 +++
 llvm/lib/Target/ARM/ARM.td | 11 +++
 llvm/lib/Target/ARM/ARMSubtarget.cpp   |  1 +
 llvm/lib/Target/ARM/ARMSubtarget.h |  1 +
 llvm/lib/TargetParser/Host.cpp |  1 +
 llvm/unittests/TargetParser/TargetParserTest.cpp   |  8 +++-
 11 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 5c044658197139..6f3b6efbfe08c0 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -899,6 +899,7 @@ Arm and AArch64 Support
   * Arm Cortex-A520 (cortex-a520).
   * Arm Cortex-A720 (cortex-a720).
   * Arm Cortex-X4 (cortex-x4).
+  * Arm Cortex-M52 (cortex-m52).
 
 Android Support
 ^^^
diff --git a/clang/test/CodeGen/arm-target-features.c 
b/clang/test/CodeGen/arm-target-features.c
index bd051059fb0cc1..ad4bfd45c408b5 100644
--- a/clang/test/CodeGen/arm-target-features.c
+++ b/clang/test/CodeGen/arm-target-features.c
@@ -113,6 +113,9 @@
 // RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m85 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M85-LINUX
 // CHECK-ARMV81M-CORTEX-M85-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
 
+// RUN: %clang_cc1 -triple thumb-linux-gnueabi -target-cpu cortex-m52 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-ARMV81M-CORTEX-M52-LINUX
+// CHECK-ARMV81M-CORTEX-M52-LINUX: 
"target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+pacbti,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp"
+
 // RUN: %clang_cc1 -triple thumbv9.3a-linux-gnueabihf -emit-llvm -o - %s | 
FileCheck %s --check-prefix=CHECK-ARCH93
 // CHECK-ARCH93: 
"target-features"="+armv9.3-a,+thumb-mode,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8.8a,+v9.1a,+v9.2a,+v9.3a,+v9a"
 
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c 
b/clang/test/Driver/arm-cortex-cpus-2.c
index 5b52488bc498f3..4bf2b3a50412d0 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -562,6 +562,9 @@
 // RUN: %clang -target arm -mcpu=cortex-m85 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M85 %s
 // CHECK-CORTEX-M85:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m85"
 
+// RUN: %clang -target arm -mcpu=cortex-m52 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M52 %s
+// CHECK-CORTEX-M52:  "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} 
"-target-cpu" "cortex-m52"
+
 // RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-NEOVERSE-N2 %s
 // CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" 
"neoverse-n2"
 
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index c7146e63add5f2..f921c4605bb976 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -1,7 +1,7 @@
 // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if 
there is anything extra in the output.
 // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix ARM
 // ARM: error: unknown target CPU 'not-a-cpu'
-// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, 
strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, 
arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, 
arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, 
arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, 
arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, 
sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, 
cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, 
cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, 
cortex-m35p, cortex-m55, cortex-m85, cortex-a32, corte

[clang] [llvm] [ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (PR #74822)

2023-12-08 Thread Jonathan Thackray via cfe-commits



@@ -896,9 +896,13 @@ Arm and AArch64 Support
 
   Support has been added for the following processors (-mcpu identifiers in 
parenthesis):
 
-  * Arm Cortex-A520 (cortex-a520).
-  * Arm Cortex-A720 (cortex-a720).
-  * Arm Cortex-X4 (cortex-x4).
+  --target=arm
+ * Arm Cortex-M52 (cortex-m52).
+
+  --target=aarch64
+ * Arm Cortex-A520 (cortex-a520).
+ * Arm Cortex-A720 (cortex-a720).
+ * Arm Cortex-X4 (cortex-x4).

jthackray wrote:

Thanks. I've adjusted the formatting so they render correctly as two lists.

https://github.com/llvm/llvm-project/pull/74822
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[clang] [lldb] fixing issue #64441 (PR #74814)

2023-12-08 Thread Felipe de Azevedo Piovezan via cfe-commits



@@ -34,7 +34,7 @@ namespace A {
 int myfunc (int a);
 int myfunc2(int a)
 {
- return a + 2;
+return a + 2; //just changing tab not much

felipepiovezan wrote:

In general, we don't add diffs that are unrelated to the problem being solved 
by the PR.
On a similar note, this comment seems to be trying to communicate with 
reviewers, not future readers of this test file. As such, this is the kind of 
comment that should be part of the commit message / PR description, and not 
part of the test itself

https://github.com/llvm/llvm-project/pull/74814
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