[clang] ecb235d - [Matrix] Implement static cast for matrix types

[Saurabh Jha via cfe-commits]

Author: Saurabh Jha
Date: 2021-05-16T08:09:12+01:00
New Revision: ecb235d94014903ec60e1539e6f0105ea6a4b089

URL: 
https://github.com/llvm/llvm-project/commit/ecb235d94014903ec60e1539e6f0105ea6a4b089
DIFF: 
https://github.com/llvm/llvm-project/commit/ecb235d94014903ec60e1539e6f0105ea6a4b089.diff

LOG: [Matrix] Implement static cast for matrix types

This patch implements static casts for matrix types. This patch finishes all 
the work needed for https://bugs.llvm.org/show_bug.cgi?id=47141

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D102125

Added: 


Modified: 
clang/lib/Sema/SemaCast.cpp
clang/test/CodeGenCXX/matrix-casts.cpp
clang/test/SemaCXX/matrix-casts.cpp

Removed: 




diff  --git a/clang/lib/Sema/SemaCast.cpp b/clang/lib/Sema/SemaCast.cpp
index 8a9ee1a309941..7ed62cc8990eb 100644
--- a/clang/lib/Sema/SemaCast.cpp
+++ b/clang/lib/Sema/SemaCast.cpp
@@ -1179,6 +1179,13 @@ void CastOperation::CheckStaticCast() {
   return;
   }
 
+  if (DestType->getAs() ||
+  SrcExpr.get()->getType()->getAs()) {
+if (Self.CheckMatrixCast(OpRange, DestType, SrcExpr.get()->getType(), 
Kind))
+  SrcExpr = ExprError();
+return;
+  }
+
   // This test is outside everything else because it's the only case where
   // a non-lvalue-reference target type does not lead to decay.
   // C++ 5.2.9p4: Any expression can be explicitly converted to type "cv void".

diff  --git a/clang/test/CodeGenCXX/matrix-casts.cpp 
b/clang/test/CodeGenCXX/matrix-casts.cpp
index 26fd77fd26f60..fea585bb0ba29 100644
--- a/clang/test/CodeGenCXX/matrix-casts.cpp
+++ b/clang/test/CodeGenCXX/matrix-casts.cpp
@@ -6,8 +6,8 @@ using matrix_4_4 = X __attribute__((matrix_type(4, 4)));
 template 
 using matrix_5_5 = Y __attribute__((matrix_type(5, 5)));
 
-// CHECK-LABEL: define{{.*}} void @_Z19CastCharMatrixToIntv
-void CastCharMatrixToInt() {
+// CHECK-LABEL: define{{.*}} void @_Z25CastCharMatrixToIntCStylev()
+void CastCharMatrixToIntCStyle() {
   // CHECK: [[C:%.*]] = load <25 x i8>, <25 x i8>* {{.*}}, align 1
   // CHECK-NEXT: [[CONV:%.*]] = sext <25 x i8> [[C]] to <25 x i32>
   // CHECK-NEXT: [[CONV1:%.*]] = bitcast [25 x i32]* {{.*}} to <25 x i32>*
@@ -18,8 +18,20 @@ void CastCharMatrixToInt() {
   i = (matrix_5_5)c;
 }
 
-// CHECK-LABEL: define{{.*}} void @_Z27CastCharMatrixToUnsignedIntv
-void CastCharMatrixToUnsignedInt() {
+// CHECK-LABEL: define{{.*}} void @_Z29CastCharMatrixToIntStaticCastv()
+void CastCharMatrixToIntStaticCast() {
+  // CHECK: [[C:%.*]] = load <25 x i8>, <25 x i8>* {{.*}}, align 1
+  // CHECK-NEXT: [[CONV:%.*]] = sext <25 x i8> [[C]] to <25 x i32>
+  // CHECK-NEXT: [[CONV1:%.*]] = bitcast [25 x i32]* {{.*}} to <25 x i32>*
+  // CHECK-NEXT: store <25 x i32> [[CONV]], <25 x i32>* [[CONV1]], align 4
+
+  matrix_5_5 c;
+  matrix_5_5 i;
+  i = static_cast>(c);
+}
+
+// CHECK-LABEL: define{{.*}} void @_Z33CastCharMatrixToUnsignedIntCStylev
+void CastCharMatrixToUnsignedIntCStyle() {
   // CHECK:   [[C:%.*]] = load <25 x i8>, <25 x i8>* {{.*}}, align 1
   // CHECK-NEXT:  [[CONV:%.*]] = sext <25 x i8> [[C]] to <25 x i32>
   // CHECK-NEXT:  [[CONV1:%.*]] = bitcast [25 x i32]* {{.*}} to <25 x i32>*
@@ -31,8 +43,21 @@ void CastCharMatrixToUnsignedInt() {
   u = (matrix_5_5)c;
 }
 
-// CHECK-LABEL: define{{.*}} void @_Z32CastUnsignedLongIntMatrixToShortv
-void CastUnsignedLongIntMatrixToShort() {
+// CHECK-LABEL: define{{.*}} void @_Z37CastCharMatrixToUnsignedIntStaticCastv
+void CastCharMatrixToUnsignedIntStaticCast() {
+  // CHECK:   [[C:%.*]] = load <25 x i8>, <25 x i8>* {{.*}}, align 1
+  // CHECK-NEXT:  [[CONV:%.*]] = sext <25 x i8> [[C]] to <25 x i32>
+  // CHECK-NEXT:  [[CONV1:%.*]] = bitcast [25 x i32]* {{.*}} to <25 x i32>*
+  // CHECK-NEXT:  store <25 x i32> [[CONV]], <25 x i32>* [[CONV1]], align 4
+  // CHECK-NEXT:  ret void
+
+  matrix_5_5 c;
+  matrix_5_5 u;
+  u = static_cast>(c);
+}
+
+// CHECK-LABEL: define{{.*}} void @_Z38CastUnsignedLongIntMatrixToShortCStylev
+void CastUnsignedLongIntMatrixToShortCStyle() {
   // CHECK:  [[U:%.*]] = load <25 x i64>, <25 x i64>* {{.*}}, align 8
   // CHECK-NEXT: [[CONV:%.*]] = trunc <25 x i64> {{.*}} to <25 x i16>
   // CHECK-NEXT: [[CONV1:%.*]] = bitcast [25 x i16]* {{.*}} to <25 x i16>*
@@ -44,8 +69,21 @@ void CastUnsignedLongIntMatrixToShort() {
   s = (matrix_5_5)u;
 }
 
-// CHECK-LABEL: define{{.*}} void @_Z20CastIntMatrixToShortv()
-void CastIntMatrixToShort() {
+// CHECK-LABEL: define{{.*}} void 
@_Z42CastUnsignedLongIntMatrixToShortStaticCastv
+void CastUnsignedLongIntMatrixToShortStaticCast() {
+  // CHECK:  [[U:%.*]] = load <25 x i64>, <25 x i64>* {{.*}}, align 8
+  // CHECK-NEXT: [[CONV:%.*]] = trunc <25 x i64> {{.*}} to <25 x i16>
+  // CHECK-NEXT: [[CONV1:%.*]] = bitcast [25 x i16]* {{.*}} to <25 x i16>*
+  // CHECK-NEXT: store <25 x i16> [[CONV]], <25 x i16>* [[CONV1]], align 2
+  // CHECK-NEXT: ret void
+
+  matrix_5

[PATCH] D102125: [Matrix] Implement static cast for matrix types

[Saurabh Jha via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGecb235d94014: [Matrix] Implement static cast for matrix 
types (authored by SaurabhJha).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102125/new/

https://reviews.llvm.org/D102125

Files:
  clang/lib/Sema/SemaCast.cpp
  clang/test/CodeGenCXX/matrix-casts.cpp
  clang/test/SemaCXX/matrix-casts.cpp

Index: clang/test/SemaCXX/matrix-casts.cpp
===
--- clang/test/SemaCXX/matrix-casts.cpp
+++ clang/test/SemaCXX/matrix-casts.cpp
@@ -46,6 +46,37 @@
 }
 
 void f2() {
+  matrix_4_4 m1;
+  matrix_4_4 m2;
+  matrix_4_4 m3;
+  matrix_5_5 m4;
+  int i;
+  vec v;
+  test_struct *s;
+
+  m2 = static_cast>(m1);
+  m3 = static_cast>(m2);
+  static_cast>(m3); // expected-error {{conversion between matrix types 'matrix_5_5' (aka 'int __attribute__\
+((matrix_type(5, 5)))') and 'matrix_4_4' (aka 'short __attribute__((matrix_type(4, 4)))') of different size is not\
+ allowed}}
+
+  static_cast(m3);// expected-error {{conversion between matrix type 'matrix_4_4' (aka 'short __attribute__\
+((matrix_type(4, 4)))') and incompatible type 'int' is not allowed}}
+  static_cast>(i); // expected-error {{conversion between matrix type 'matrix_4_4' (aka 'int __attribute__\
+((matrix_type(4, 4)))') and incompatible type 'int' is not allowed}}
+
+  static_cast(m2); // expected-error {{conversion between matrix type 'matrix_4_4' (aka 'int __attribute__\
+((matrix_type(4, 4)))') and incompatible type 'vec' (vector of 1 'int' value) is not allowed}}
+  static_cast>(v); // expected-error {{conversion between matrix type 'matrix_4_4' (aka 'char __attribute__\
+((matrix_type(4, 4)))') and incompatible type 'vec' (vector of 1 'int' value) is not allowed}}
+
+  static_cast(m1);// expected-error {{conversion between matrix type 'matrix_4_4' (aka 'char __attribute__\
+((matrix_type(4, 4)))') and incompatible type 'test_struct *' is not allowed}}'
+  static_cast>(s); // expected-error {{conversion between matrix type 'matrix_5_5' (aka 'float __attribute__\
+((matrix_type(5, 5)))') and incompatible type 'test_struct *' is not allowed}}'
+}
+
+void f3() {
   matrix_4_4 m1;
   matrix_4_4 m2;
   matrix_5_5 m3;
@@ -65,3 +96,24 @@
   m6 = (matrix_5_5)m4;
   m4 = (matrix_5_5)m6;
 }
+
+void f4() {
+  matrix_4_4 m1;
+  matrix_4_4 m2;
+  matrix_5_5 m3;
+  matrix_5_5 m4;
+  matrix_4_4 m5;
+  matrix_5_5 m6;
+  float f;
+
+  m2 = static_cast>(m1);
+  static_cast>(m1); // expected-error {{conversion between matrix types 'matrix_5_5' (aka 'double __\
+attribute__((matrix_type(5, 5)))') and 'matrix_4_4' (aka 'float __attribute__((matrix_type(4, 4)))') of different\
+ size is not allowed}}
+  m4 = static_cast>(m3);
+  m5 = static_cast>(m4); // expected-error {{assigning to 'matrix_4_4' (aka 'unsigned int \
+__attribute__((matrix_type(4, 4)))') from incompatible type 'matrix_5_5' (aka 'unsigned int __attribute__\
+((matrix_type(5, 5)))')}}
+  m6 = static_cast>(m4);
+  m4 = static_cast>(m6);
+}
Index: clang/test/CodeGenCXX/matrix-casts.cpp
===
--- clang/test/CodeGenCXX/matrix-casts.cpp
+++ clang/test/CodeGenCXX/matrix-casts.cpp
@@ -6,8 +6,8 @@
 template 
 using matrix_5_5 = Y __attribute__((matrix_type(5, 5)));
 
-// CHECK-LABEL: define{{.*}} void @_Z19CastCharMatrixToIntv
-void CastCharMatrixToInt() {
+// CHECK-LABEL: define{{.*}} void @_Z25CastCharMatrixToIntCStylev()
+void CastCharMatrixToIntCStyle() {
   // CHECK: [[C:%.*]] = load <25 x i8>, <25 x i8>* {{.*}}, align 1
   // CHECK-NEXT: [[CONV:%.*]] = sext <25 x i8> [[C]] to <25 x i32>
   // CHECK-NEXT: [[CONV1:%.*]] = bitcast [25 x i32]* {{.*}} to <25 x i32>*
@@ -18,8 +18,20 @@
   i = (matrix_5_5)c;
 }
 
-// CHECK-LABEL: define{{.*}} void @_Z27CastCharMatrixToUnsignedIntv
-void CastCharMatrixToUnsignedInt() {
+// CHECK-LABEL: define{{.*}} void @_Z29CastCharMatrixToIntStaticCastv()
+void CastCharMatrixToIntStaticCast() {
+  // CHECK: [[C:%.*]] = load <25 x i8>, <25 x i8>* {{.*}}, align 1
+  // CHECK-NEXT: [[CONV:%.*]] = sext <25 x i8> [[C]] to <25 x i32>
+  // CHECK-NEXT: [[CONV1:%.*]] = bitcast [25 x i32]* {{.*}} to <25 x i32>*
+  // CHECK-NEXT: store <25 x i32> [[CONV]], <25 x i32>* [[CONV1]], align 4
+
+  matrix_5_5 c;
+  matrix_5_5 i;
+  i = static_cast>(c);
+}
+
+// CHECK-LABEL: define{{.*}} void @_Z33CastCharMatrixToUnsignedIntCStylev
+void CastCharMatrixToUnsignedIntCStyle() {
   // CHECK:   [[C:%.*]] = load <25 x i8>, <25 x i8>* {{.*}}, align 1
   // CHECK-NEXT:  [[CONV:%.*]] = sext <25 x i8> [[C]] to <25 x i32>
   // CHECK-NEXT:  [[CONV1:%.*]] = bitcast [25 x i32]* {{.*}} to <25 x i32>*
@@ -31,8 +43,21 @@
   u = (matrix_5_5)c;
 }
 
-// CHECK-LABEL: define{{.*}} void @_Z32CastUnsignedLongIntMatrixToShortv
-void CastUnsignedLongIntMatrixToShort() {
+// CHECK-LABEL: define{{.*}} void @_Z37CastCharMatrixToUnsignedInt

[PATCH] D102118: [BPF] add support for 32 bit registers in inline asm

[Alessandro Decina via Phabricator via cfe-commits]

alessandrod updated this revision to Diff 345680.
alessandrod added a comment.

Remove unused global from test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102118/new/

https://reviews.llvm.org/D102118

Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  clang/test/CodeGen/bpf-inline-asm.c
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFISelLowering.h
  llvm/test/CodeGen/BPF/inlineasm-wreg.ll

Index: llvm/test/CodeGen/BPF/inlineasm-wreg.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/inlineasm-wreg.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=bpfel -mattr=+alu32 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -march=bpfeb -mattr=+alu32 -verify-machineinstrs | FileCheck %s
+
+; Test that %w works as input constraint
+; CHECK-LABEL: test_inlineasm_w_input_constraint
+define dso_local i32 @test_inlineasm_w_input_constraint() {
+  tail call void asm sideeffect "w0 = $0", "w"(i32 42)
+; CHECK: w0 = w1
+  ret i32 42
+}
+
+; Test that %w works as output constraint
+; CHECK-LABEL: test_inlineasm_w_output_constraint
+define dso_local i32 @test_inlineasm_w_output_constraint() {
+  %1 = tail call i32 asm sideeffect "$0 = $1", "=w,i"(i32 42)
+; CHECK: w0 = 42
+  ret i32 %1
+}
Index: llvm/lib/Target/BPF/BPFISelLowering.h
===
--- llvm/lib/Target/BPF/BPFISelLowering.h
+++ llvm/lib/Target/BPF/BPFISelLowering.h
@@ -46,6 +46,9 @@
   // with the given GlobalAddress is legal.
   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 
+  BPFTargetLowering::ConstraintType
+  getConstraintType(StringRef Constraint) const override;
+
   std::pair
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override;
Index: llvm/lib/Target/BPF/BPFISelLowering.cpp
===
--- llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -220,6 +220,20 @@
   return NumBits1 == 32 && NumBits2 == 64;
 }
 
+BPFTargetLowering::ConstraintType
+BPFTargetLowering::getConstraintType(StringRef Constraint) const {
+  if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+default:
+  break;
+case 'w':
+  return C_RegisterClass;
+}
+  }
+
+  return TargetLowering::getConstraintType(Constraint);
+}
+
 std::pair
 BPFTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 StringRef Constraint,
@@ -229,6 +243,10 @@
 switch (Constraint[0]) {
 case 'r': // GENERAL_REGS
   return std::make_pair(0U, &BPF::GPRRegClass);
+case 'w':
+  if (HasAlu32)
+return std::make_pair(0U, &BPF::GPR32RegClass);
+  break;
 default:
   break;
 }
Index: clang/test/CodeGen/bpf-inline-asm.c
===
--- /dev/null
+++ clang/test/CodeGen/bpf-inline-asm.c
@@ -0,0 +1,31 @@
+// REQUIRES: bpf-registered-target
+// RUN: %clang -target bpf -emit-llvm -S -Xclang -target-feature -Xclang +alu32 %s -o - | FileCheck %s
+// RUN: %clang -target bpf -emit-llvm -S -mcpu=v3 %s -o - | FileCheck %s
+
+void test_generic_constraints(int var32, long var64) {
+  asm("%0 = %1"
+  : "=r"(var32)
+  : "0"(var32));
+  // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32*
+  // CHECK: call i32 asm "$0 = $1", "=r,0"(i32 [[R32_ARG]])
+
+  asm("%0 = %1"
+  : "=r"(var64)
+  : "0"(var64));
+  // CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, i64*
+  // CHECK: call i64 asm "$0 = $1", "=r,0"(i64 [[R64_ARG]])
+
+  asm("%0 = %1"
+  : "=r"(var64)
+  : "r"(var64));
+  // CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, i64*
+  // CHECK: call i64 asm "$0 = $1", "=r,r"(i64 [[R64_ARG]])
+}
+
+void test_constraint_w(int a) {
+  asm("%0 = %1"
+  : "=w"(a)
+  : "w"(a));
+  // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32*
+  // CHECK: call i32 asm "$0 = $1", "=w,w"(i32 [[R32_ARG]])
+}
Index: clang/lib/Basic/Targets/BPF.h
===
--- clang/lib/Basic/Targets/BPF.h
+++ clang/lib/Basic/Targets/BPF.h
@@ -23,6 +23,7 @@
 
 class LLVM_LIBRARY_VISIBILITY BPFTargetInfo : public TargetInfo {
   static const Builtin::Info BuiltinInfo[];
+  bool HasAlu32 = false;
 
 public:
   BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
@@ -55,6 +56,8 @@
  bool Enabled) const override {
 Features[Name] = Enabled;
   }
+  bool handleTargetFeatures(std::vector &Features,
+DiagnosticsEngine &Diags) override;
 
   ArrayRef getTargetBuiltins() const override;
 
@@ -68,7 +71,16 @@
   ArrayRef getGCCRegNames() const override { return None; }
 
   bool validateAsmConstraint(const char *&Name,
- 

[PATCH] D102118: [BPF] add support for 32 bit registers in inline asm

[Alessandro Decina via Phabricator via cfe-commits]

alessandrod added a comment.

In D102118#2761476 , @yonghong-song 
wrote:

> LGTM except one minor issue. Please do address the nit before merging. Thanks!

Done, thanks for the review! I don't have commit access so someone will have to 
merge this for me :)


Repository:
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[PATCH] D102576: [clang-tidy] cppcoreguidelines-avoid-do-while: a new check

[Fabian Thurnheer via Phabricator via cfe-commits]

DNS320 created this revision.
DNS320 added reviewers: aaron.ballman, njames93, alexfh.
DNS320 added a project: clang-tools-extra.
Herald added subscribers: shchenz, kbarton, xazax.hun, mgorny, nemanjai.
DNS320 requested review of this revision.

This simple check flags do-while statements according to rule ES.75 

 of the C++ Core Guidelines.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102576

Files:
  clang-tools-extra/clang-tidy/cppcoreguidelines/AvoidDoWhileCheck.cpp
  clang-tools-extra/clang-tidy/cppcoreguidelines/AvoidDoWhileCheck.h
  clang-tools-extra/clang-tidy/cppcoreguidelines/CMakeLists.txt
  clang-tools-extra/clang-tidy/cppcoreguidelines/CppCoreGuidelinesTidyModule.cpp
  clang-tools-extra/docs/ReleaseNotes.rst
  clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines-avoid-do-while.rst
  clang-tools-extra/docs/clang-tidy/checks/list.rst
  
clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-avoid-do-while.cpp

Index: clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-avoid-do-while.cpp
===
--- /dev/null
+++ clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-avoid-do-while.cpp
@@ -0,0 +1,21 @@
+// RUN: %check_clang_tidy %s cppcoreguidelines-avoid-do-while %t
+
+void func1() {
+  int I{0};
+  const int Limit{10};
+
+  // CHECK-MESSAGES: :[[@LINE+1]]:3: warning: Try to avoid using do-while loops in terms of readability. Consider using a while loop instead. [cppcoreguidelines-avoid-do-while]
+  do {
+I++;
+  } while (I <= Limit);
+}
+
+void func2() {
+  int I{0};
+  const int Limit{10};
+
+  // OK
+  while (I <= Limit) {
+I++;
+  }
+}
Index: clang-tools-extra/docs/clang-tidy/checks/list.rst
===
--- clang-tools-extra/docs/clang-tidy/checks/list.rst
+++ clang-tools-extra/docs/clang-tidy/checks/list.rst
@@ -144,6 +144,7 @@
`clang-analyzer-valist.Unterminated `_,
`concurrency-mt-unsafe `_,
`concurrency-thread-canceltype-asynchronous `_,
+   `cppcoreguidelines-avoid-do-while `_,
`cppcoreguidelines-avoid-goto `_,
`cppcoreguidelines-avoid-non-const-global-variables `_,
`cppcoreguidelines-init-variables `_, "Yes"
Index: clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines-avoid-do-while.rst
===
--- /dev/null
+++ clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines-avoid-do-while.rst
@@ -0,0 +1,32 @@
+.. title:: clang-tidy - cppcoreguidelines-avoid-do-while
+
+cppcoreguidelines-avoid-do-while
+
+
+Checks if a do-while loop exists and flags it.
+
+Using a while loop instead of a do-while could improve readability and prevents overlooking the condition at the end.
+
+.. code-block:: c++
+
+  void func1() {
+int I{0};
+const int Limit{10};
+
+// Consider using a while loop
+do {
+  I++;
+} while (I <= Limit);
+  }
+
+  void func2() {
+int I{0};
+const int Limit{10};
+
+// Better
+while (I <= Limit) {
+  I++;
+}
+  }
+
+This check implements rule `ES.75 `_ of the C++ Core Guidelines.
Index: clang-tools-extra/docs/ReleaseNotes.rst
===
--- clang-tools-extra/docs/ReleaseNotes.rst
+++ clang-tools-extra/docs/ReleaseNotes.rst
@@ -108,6 +108,11 @@
   Finds inner loops that have not been unrolled, as well as fully unrolled
   loops with unknown loops bounds or a large number of iterations.
 
+- New :doc:`cppcoreguidelines-avoid-do-while
+  ` check.
+
+  Checks if a do-while loop exists and flags it.
+
 - New :doc:`cppcoreguidelines-prefer-member-initializer
   ` check.
 
Index: clang-tools-extra/clang-tidy/cppcoreguidelines/CppCoreGuidelinesTidyModule.cpp
===
--- clang-tools-extra/clang-tidy/cppcoreguidelines/CppCoreGuidelinesTidyModule.cpp
+++ clang-tools-extra/clang-tidy/cppcoreguidelines/CppCoreGuidelinesTidyModule.cpp
@@ -14,6 +14,7 @@
 #include "../modernize/AvoidCArraysCheck.h"
 #include "../modernize/UseOverrideCheck.h"
 #include "../readability/MagicNumbersCheck.h"
+#include "AvoidDoWhileCheck.h"
 #include "AvoidGotoCheck.h"
 #include "AvoidNonConstGlobalVariablesCheck.h"
 #include "InitVariablesCheck.h"
@@ -46,6 +47,8 @@
   void addCheckFactories(ClangTidyCheckFactories &CheckFactories) override {
 CheckFactories.registerCheck(
 "cppcoreguidelines-avoid-c-arrays");
+CheckFactories.registerCheck(
+"cppcoreguidelines-avoid-do-while");
 CheckFactories.registerCheck(
 "cppcoreguidelines-avoid-goto");
 CheckFactories.registerCheck(
Index: clang-tools-extra/clang-tidy/cppcoreguidelines/CMakeLists.txt
===

[PATCH] D102478: [Matrix] Emit assumption that matrix indices are valid.

[Florian Hahn via Phabricator via cfe-commits]

fhahn updated this revision to Diff 345702.
fhahn added a comment.
Herald added a subscriber: hiraditya.

Thanks for taking a look! I added a phase ordering test and updated the 
pipeline tests as well.


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/test/CodeGen/matrix-type-operators.c
  clang/test/CodeGenCXX/matrix-type-operators.cpp
  clang/test/CodeGenObjC/matrix-type-operators.m
  llvm/include/llvm/IR/MatrixBuilder.h
  llvm/lib/Passes/PassBuilder.cpp
  llvm/lib/Transforms/IPO/PassManagerBuilder.cpp
  llvm/test/Other/opt-O3-pipeline-enable-matrix.ll
  llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll

Index: llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
===
--- llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
+++ llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
@@ -26,8 +26,7 @@
 ; CHECK-NEXT:[[TMP9:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP7]], i64 0, i64 [[TMP1]]
 ; CHECK-NEXT:[[MATRIXEXT7:%.*]] = load double, double* [[TMP9]], align 8
 ; CHECK-NEXT:[[SUB:%.*]] = fsub double [[MATRIXEXT7]], [[MUL]]
-; CHECK-NEXT:[[TMP10:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP7]], i64 0, i64 [[TMP1]]
-; CHECK-NEXT:store double [[SUB]], double* [[TMP10]], align 8
+; CHECK-NEXT:store double [[SUB]], double* [[TMP9]], align 8
 ; CHECK-NEXT:ret void
 ;
 entry:
@@ -93,43 +92,99 @@
 ; CHECK-NEXT:[[CONV6:%.*]] = zext i32 [[I:%.*]] to i64
 ; CHECK-NEXT:[[TMP1:%.*]] = bitcast [225 x double]* [[B:%.*]] to <225 x double>*
 ; CHECK-NEXT:[[CMP212_NOT:%.*]] = icmp eq i32 [[I]], 0
-; CHECK-NEXT:br i1 [[CMP212_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER_US_PREHEADER:%.*]]
-; CHECK:   for.cond1.preheader.us.preheader:
-; CHECK-NEXT:[[DOTPRE_PRE:%.*]] = load <225 x double>, <225 x double>* [[TMP1]], align 8
-; CHECK-NEXT:br label [[FOR_COND1_PREHEADER_US:%.*]]
+; CHECK-NEXT:br i1 [[CMP212_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER_US:%.*]]
 ; CHECK:   for.cond1.preheader.us:
-; CHECK-NEXT:[[DOTPRE:%.*]] = phi <225 x double> [ [[MATINS_US:%.*]], [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:%.*]] ], [ [[DOTPRE_PRE]], [[FOR_COND1_PREHEADER_US_PREHEADER]] ]
-; CHECK-NEXT:[[J_014_US:%.*]] = phi i32 [ [[INC13_US:%.*]], [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ]
-; CHECK-NEXT:[[CONV5_US:%.*]] = zext i32 [[J_014_US]] to i64
-; CHECK-NEXT:[[TMP2:%.*]] = mul nuw nsw i64 [[CONV5_US]], 15
-; CHECK-NEXT:[[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], [[CONV6]]
-; CHECK-NEXT:[[TMP4:%.*]] = icmp ult i64 [[TMP3]], 225
-; CHECK-NEXT:tail call void @llvm.assume(i1 [[TMP4]])
+; CHECK-NEXT:[[TMP2:%.*]] = icmp ult i32 [[I]], 225
+; CHECK-NEXT:tail call void @llvm.assume(i1 [[TMP2]])
+; CHECK-NEXT:[[TMP3:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP1]], i64 0, i64 [[CONV6]]
 ; CHECK-NEXT:br label [[FOR_BODY4_US:%.*]]
 ; CHECK:   for.body4.us:
-; CHECK-NEXT:[[TMP5:%.*]] = phi <225 x double> [ [[DOTPRE]], [[FOR_COND1_PREHEADER_US]] ], [ [[MATINS_US]], [[FOR_BODY4_US]] ]
 ; CHECK-NEXT:[[K_013_US:%.*]] = phi i32 [ 0, [[FOR_COND1_PREHEADER_US]] ], [ [[INC_US:%.*]], [[FOR_BODY4_US]] ]
 ; CHECK-NEXT:[[CONV_US:%.*]] = zext i32 [[K_013_US]] to i64
-; CHECK-NEXT:[[TMP6:%.*]] = add nuw nsw i64 [[TMP2]], [[CONV_US]]
-; CHECK-NEXT:[[TMP7:%.*]] = icmp ult i64 [[TMP6]], 225
-; CHECK-NEXT:tail call void @llvm.assume(i1 [[TMP7]])
-; CHECK-NEXT:[[TMP8:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP0]], i64 0, i64 [[TMP6]]
-; CHECK-NEXT:[[MATRIXEXT_US:%.*]] = load double, double* [[TMP8]], align 8
-; CHECK-NEXT:[[MATRIXEXT8_US:%.*]] = extractelement <225 x double> [[TMP5]], i64 [[TMP3]]
+; CHECK-NEXT:[[TMP4:%.*]] = icmp ult i32 [[K_013_US]], 225
+; CHECK-NEXT:tail call void @llvm.assume(i1 [[TMP4]])
+; CHECK-NEXT:[[TMP5:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP0]], i64 0, i64 [[CONV_US]]
+; CHECK-NEXT:[[MATRIXEXT_US:%.*]] = load double, double* [[TMP5]], align 8
+; CHECK-NEXT:[[MATRIXEXT8_US:%.*]] = load double, double* [[TMP3]], align 8
 ; CHECK-NEXT:[[MUL_US:%.*]] = fmul double [[MATRIXEXT_US]], [[MATRIXEXT8_US]]
-; CHECK-NEXT:[[MATRIXEXT11_US:%.*]] = extractelement <225 x double> [[TMP5]], i64 [[TMP6]]
+; CHECK-NEXT:[[TMP6:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP1]], i64 0, i64 [[CONV_US]]
+; CHECK-NEXT:[[MATRIXEXT11_US:%.*]] = load double, double* [[TMP6]], align 8
 ; CHECK-NEXT:[[SUB_US:%.*]] = fsub double [[MATRIXEXT11_US]], [[MUL_US]]

[PATCH] D102478: [Matrix] Emit assumption that matrix indices are valid.

[Florian Hahn via Phabricator via cfe-commits]

fhahn updated this revision to Diff 345703.
fhahn added a comment.

Undo unrelated changes.


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Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/test/CodeGen/matrix-type-operators.c
  clang/test/CodeGenCXX/matrix-type-operators.cpp
  clang/test/CodeGenObjC/matrix-type-operators.m
  llvm/include/llvm/IR/MatrixBuilder.h

Index: llvm/include/llvm/IR/MatrixBuilder.h
===
--- llvm/include/llvm/IR/MatrixBuilder.h
+++ llvm/include/llvm/IR/MatrixBuilder.h
@@ -231,9 +231,25 @@
: (IsUnsigned ? B.CreateUDiv(LHS, RHS) : B.CreateSDiv(LHS, RHS));
   }
 
-  /// Extracts the element at (\p RowIdx, \p ColumnIdx) from \p Matrix.
-  Value *CreateExtractElement(Value *Matrix, Value *RowIdx, Value *ColumnIdx,
-  unsigned NumRows, Twine const &Name = "") {
+  /// Create an assumption that \p Idx is less than \p NumElements.
+  void CreateIndexAssumption(Value *Idx, unsigned NumElements,
+ Twine const &Name = "") {
+
+Value *NumElts =
+B.getIntN(Idx->getType()->getScalarSizeInBits(), NumElements);
+
+auto *Cmp = B.CreateICmpULT(Idx, NumElts);
+if (!isa(Cmp)) {
+  Function *TheFn =
+  Intrinsic::getDeclaration(getModule(), Intrinsic::assume);
+  B.CreateCall(TheFn->getFunctionType(), TheFn, {Cmp}, Name);
+}
+  }
+
+  /// Compute the index to access the element at (\p RowIdx, \p ColumnIdx) from
+  /// a matrix with \p NumRows embedded in a vector.
+  Value *CreateIndex(Value *RowIdx, Value *ColumnIdx, unsigned NumRows,
+ Twine const &Name = "") {
 
 unsigned MaxWidth = std::max(RowIdx->getType()->getScalarSizeInBits(),
  ColumnIdx->getType()->getScalarSizeInBits());
@@ -241,9 +257,7 @@
 RowIdx = B.CreateZExt(RowIdx, IntTy);
 ColumnIdx = B.CreateZExt(ColumnIdx, IntTy);
 Value *NumRowsV = B.getIntN(MaxWidth, NumRows);
-return B.CreateExtractElement(
-Matrix, B.CreateAdd(B.CreateMul(ColumnIdx, NumRowsV), RowIdx),
-"matext");
+return B.CreateAdd(B.CreateMul(ColumnIdx, NumRowsV), RowIdx);
   }
 };
 
Index: clang/test/CodeGenObjC/matrix-type-operators.m
===
--- clang/test/CodeGenObjC/matrix-type-operators.m
+++ clang/test/CodeGenObjC/matrix-type-operators.m
@@ -22,9 +22,11 @@
 // CHECK-NEXT:[[IV2_PTR:%.*]] = bitcast %0* [[IV2]] to i8*
 // CHECK-NEXT:[[CALL1:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* [[IV2_PTR]], i8* [[SEL2]])
 // CHECK-NEXT:[[CONV2:%.*]] = sext i32 [[CALL1]] to i64
-// CHECK-NEXT:[[MAT:%.*]] = load <16 x double>, <16 x double>* {{.*}} align 8
 // CHECK-NEXT:[[IDX1:%.*]] = mul i64 [[CONV2]], 4
 // CHECK-NEXT:[[IDX2:%.*]] = add i64 [[IDX1]], [[CONV]]
+// CHECK-NEXT:   [[CMP:%.*]] = icmp ult i64 [[IDX2]], 16
+// CHECK-NEXT:call void @llvm.assume(i1 [[CMP]])
+// CHECK-NEXT:[[MAT:%.*]] = load <16 x double>, <16 x double>* {{.*}} align 8
 // CHECK-NEXT:[[MATEXT:%.*]] = extractelement <16 x double> [[MAT]], i64 [[IDX2]]
 // CHECK-NEXT:ret double [[MATEXT]]
 //
@@ -49,12 +51,14 @@
 // CHECK-NEXT:[[IV2_PTR:%.*]] = bitcast %0* [[IV2]] to i8*
 // CHECK-NEXT:[[CALL1:%.*]] = call i32 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i32 (i8*, i8*)*)(i8* [[IV2_PTR]], i8* [[SEL2]])
 // CHECK-NEXT:[[CONV2:%.*]] = sext i32 [[CALL1]] to i64
+// CHECK-NEXT:[[IDX1:%.*]] = mul i64 [[CONV2]], 4
+// CHECK-NEXT:[[IDX2:%.*]] = add i64 [[IDX1]], [[CONV]]
+// CHECK-NEXT:[[CMP:%.*]] = icmp ult i64 [[IDX2]], 16
+// CHECK-NEXT:call void @llvm.assume(i1 [[CMP]])
 // CHECK-NEXT:[[M:%.*]] = load %1*, %1** %m.addr, align 8
 // CHECK-NEXT:[[SEL3:%.*]] = load i8*, i8** @OBJC_SELECTOR_REFERENCES_, align 8, !invariant.load !7
 // CHECK-NEXT:[[M_PTR:%.*]] = bitcast %1* [[M]] to i8*
 // CHECK-NEXT:[[MAT:%.*]] = call <16 x double> bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to <16 x double> (i8*, i8*)*)(i8* [[M_PTR]], i8* [[SEL3]])
-// CHECK-NEXT:[[IDX1:%.*]] = mul i64 [[CONV2]], 4
-// CHECK-NEXT:[[IDX2:%.*]] = add i64 [[IDX1]], [[CONV]]
 // CHECK-NEXT:[[MATEXT:%.*]] = extractelement <16 x double> [[MAT]], i64 [[IDX2]]
 // CHECK-NEXT:ret double [[MATEXT]]
 //
Index: clang/test/CodeGenCXX/matrix-type-operators.cpp
===
--- clang/test/CodeGenCXX/matrix-type-operators.cpp
+++ clang/test/CodeGenCXX/matrix-type-operators.cpp
@@ -219,6 +219,8 @@
   // CHECK-NEXT:[[IDX1:%.*]] = mul i64 [[J_EXT]], 2
   // CHECK-NEXT:[[IDX2:%.*]] = add i64 [[IDX1]], [[I_EXT]]
   // CHECK-NEXT:[[MAT_ADDR:%.*]] = bitcast [4 x i32]* {{.*}} to <4 x i32>*
+  // CHECK-NEXT:[[CMP:%.*]]

[PATCH] D102577: TreeTransform.h: make the switch case more beautiful

[zhouyizhou via Phabricator via cfe-commits]

zhouyizhou created this revision.
zhouyizhou added reviewers: sepavloff, craig.topper, rsmith, klimek, 
doug.gregor.
Herald added a subscriber: pengfei.
zhouyizhou requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Hi, 


I am new to LLVM, and I really want to get involved in LLVM community.


  

I guess if the following switch case of function


TransformNestedNameSpecifierLoc could possibly made more beautiful with 


'break' stmt moved inside of the right brace.


  

I think move of 'break' stmt will not change the invoking destructor of 


IdInfo.


  

Thanks for your effort.


  

I have done make check-all on x86_64-linux  


Signed-off-by: Zhouyi Zhou 


Repository:
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https://reviews.llvm.org/D102577

Files:
  clang/lib/Sema/TreeTransform.h


Index: clang/lib/Sema/TreeTransform.h
===
--- clang/lib/Sema/TreeTransform.h
+++ clang/lib/Sema/TreeTransform.h
@@ -3964,8 +3964,8 @@
   if (SemaRef.BuildCXXNestedNameSpecifier(/*Scope=*/nullptr, IdInfo, false,
   SS, FirstQualifierInScope, 
false))
 return NestedNameSpecifierLoc();
-}
   break;
+}
 
 case NestedNameSpecifier::Namespace: {
   NamespaceDecl *NS


Index: clang/lib/Sema/TreeTransform.h
===
--- clang/lib/Sema/TreeTransform.h
+++ clang/lib/Sema/TreeTransform.h
@@ -3964,8 +3964,8 @@
   if (SemaRef.BuildCXXNestedNameSpecifier(/*Scope=*/nullptr, IdInfo, false,
   SS, FirstQualifierInScope, false))
 return NestedNameSpecifierLoc();
-}
   break;
+}
 
 case NestedNameSpecifier::Namespace: {
   NamespaceDecl *NS
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[PATCH] D102576: [clang-tidy] cppcoreguidelines-avoid-do-while: a new check

[Eugene Zelenko via Phabricator via cfe-commits]

Eugene.Zelenko added inline comments.



Comment at: clang-tools-extra/docs/ReleaseNotes.rst:114
+
+  Checks if a do-while loop exists and flags it.
+

Please highlight do-while with double back-ticks.



Comment at: 
clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines-avoid-do-while.rst:6
+
+Checks if a do-while loop exists and flags it.
+

Please highlight do-while with double back-ticks.



Comment at: 
clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines-avoid-do-while.rst:8
+
+Using a while loop instead of a do-while could improve readability and 
prevents overlooking the condition at the end.
+

Please highlight do-while and while with double back-ticks.


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[clang] 656296b - Reapply [CaptureTracking] Do not check domination

[Nikita Popov via cfe-commits]

Author: Nikita Popov
Date: 2021-05-16T15:46:31+02:00
New Revision: 656296b1c2eca127cb48612227fa5f381c81b53b

URL: 
https://github.com/llvm/llvm-project/commit/656296b1c2eca127cb48612227fa5f381c81b53b
DIFF: 
https://github.com/llvm/llvm-project/commit/656296b1c2eca127cb48612227fa5f381c81b53b.diff

LOG: Reapply [CaptureTracking] Do not check domination

Reapply after adjusting the synchronized.m test case, where the
TODO is now resolved. The pointer is only captured on the exception
handling path.

-

For the CapturesBefore tracker, it is sufficient to check that
I can not reach BeforeHere. This does not necessarily require
that BeforeHere dominates I, it can also occur if the capture
happens on an entirely disjoint path.

This change was previously accepted in D90688, but had to be
reverted due to large compile-time impact in some cases: It
increases the number of reachability queries that are performed.

After recent changes, the compile-time impact is largely mitigated,
so I'm reapplying this patch. The remaining compile-time impact
is largely proportional to changes in code-size.

Added: 


Modified: 
clang/test/CodeGenObjC/synchronized.m
llvm/lib/Analysis/CaptureTracking.cpp
llvm/test/Transforms/MemCpyOpt/callslot.ll

Removed: 




diff  --git a/clang/test/CodeGenObjC/synchronized.m 
b/clang/test/CodeGenObjC/synchronized.m
index 6d37e6fc06ca..44f4826d19dc 100644
--- a/clang/test/CodeGenObjC/synchronized.m
+++ b/clang/test/CodeGenObjC/synchronized.m
@@ -39,7 +39,6 @@ void foo(id a) {
 // CHECK: unreachable
 
 // CHECK:  call void @objc_exception_try_exit
-// CHECK:  [[T:%.*]] = load i8*, i8** [[SYNC]]
 // CHECK-NEXT: call i32 @objc_sync_exit
 // CHECK: ret void
 return;
@@ -49,9 +48,8 @@ void foo(id a) {
 
 // CHECK-LABEL: define{{.*}} i32 @f0(
 int f0(id a) {
-  // TODO: we can optimize the ret to a constant if we can figure out
-  // either that x isn't stored to within the synchronized block or
-  // that the synchronized block can't longjmp.
+  // We can optimize the ret to a constant as we can figure out
+  // that x isn't stored to within the synchronized block.
 
   // CHECK: [[X:%.*]] = alloca i32
   // CHECK: store i32 1, i32* [[X]]
@@ -59,8 +57,7 @@ int f0(id a) {
   @synchronized((x++, a)) {
   }
 
-  // CHECK: [[T:%.*]] = load i32, i32* [[X]]
-  // CHECK: ret i32 [[T]]
+  // CHECK: ret i32 1
   return x;
 }
 

diff  --git a/llvm/lib/Analysis/CaptureTracking.cpp 
b/llvm/lib/Analysis/CaptureTracking.cpp
index e14f6f25dc18..25815fc57463 100644
--- a/llvm/lib/Analysis/CaptureTracking.cpp
+++ b/llvm/lib/Analysis/CaptureTracking.cpp
@@ -143,14 +143,8 @@ namespace {
 return !isPotentiallyReachableFromMany(Worklist, BB, nullptr, DT);
   }
 
-  // If the value is defined in the same basic block as use and BeforeHere,
-  // there is no need to explore the use if BeforeHere dominates use.
   // Check whether there is a path from I to BeforeHere.
-  if (DT->dominates(BeforeHere, I) &&
-  !isPotentiallyReachable(I, BeforeHere, nullptr, DT))
-return true;
-
-  return false;
+  return !isPotentiallyReachable(I, BeforeHere, nullptr, DT);
 }
 
 bool captured(const Use *U) override {

diff  --git a/llvm/test/Transforms/MemCpyOpt/callslot.ll 
b/llvm/test/Transforms/MemCpyOpt/callslot.ll
index 037a95ec5176..b9eab2ef8778 100644
--- a/llvm/test/Transforms/MemCpyOpt/callslot.ll
+++ b/llvm/test/Transforms/MemCpyOpt/callslot.ll
@@ -252,8 +252,8 @@ define void @capture_nopath_call(i1 %cond) {
 ; CHECK-NEXT:call void @accept_ptr(i8* [[DEST_I8]])
 ; CHECK-NEXT:ret void
 ; CHECK:   nocaptures:
-; CHECK-NEXT:call void @accept_ptr(i8* [[SRC_I8]]) #[[ATTR3]]
-; CHECK-NEXT:call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[DEST_I8]], i8* 
[[SRC_I8]], i64 16, i1 false)
+; CHECK-NEXT:[[DEST1:%.*]] = bitcast [16 x i8]* [[DEST]] to i8*
+; CHECK-NEXT:call void @accept_ptr(i8* [[DEST1]]) #[[ATTR3]]
 ; CHECK-NEXT:ret void
 ;
   %dest = alloca [16 x i8]



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[PATCH] D102577: TreeTransform.h: make the switch case more beautiful

[zhouyizhou via Phabricator via cfe-commits]

zhouyizhou updated this revision to Diff 345710.
zhouyizhou added a comment.

I use git diff -U9 instead


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Files:
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Index: clang/lib/Sema/TreeTransform.h
===
--- clang/lib/Sema/TreeTransform.h
+++ clang/lib/Sema/TreeTransform.h
@@ -3964,8 +3964,8 @@
   if (SemaRef.BuildCXXNestedNameSpecifier(/*Scope=*/nullptr, IdInfo, false,
   SS, FirstQualifierInScope, 
false))
 return NestedNameSpecifierLoc();
-}
   break;
+}
 
 case NestedNameSpecifier::Namespace: {
   NamespaceDecl *NS


Index: clang/lib/Sema/TreeTransform.h
===
--- clang/lib/Sema/TreeTransform.h
+++ clang/lib/Sema/TreeTransform.h
@@ -3964,8 +3964,8 @@
   if (SemaRef.BuildCXXNestedNameSpecifier(/*Scope=*/nullptr, IdInfo, false,
   SS, FirstQualifierInScope, false))
 return NestedNameSpecifierLoc();
-}
   break;
+}
 
 case NestedNameSpecifier::Namespace: {
   NamespaceDecl *NS
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[PATCH] D96033: [clang-repl] Land initial infrastructure for incremental parsing

[Vassil Vassilev via Phabricator via cfe-commits]

v.g.vassilev added a comment.

In D96033#2761581 , 
@hubert.reinterpretcast wrote:

> In D96033#2761428 , 
> @hubert.reinterpretcast wrote:
>
>> If you have some ideas, please let me know. Meanwhile, I am trying out 
>> `system-aix` as the "feature" to XFAIL on.
>
> https://reviews.llvm.org/D102560 posted to use `system-aix` so other PPC 
> configurations will run the test. Possible further changes is for the code to 
> choose the process triple, for the test to possibly specify 
> `-fintegrated-as`, and (alternatively) for the system assembler step to be 
> integrated into this use scenario.

Thanks for the fix. Indeed I will commit the change wrt getting the process 
triple although it may require further adjustments for out-of-process execution.

I'd like to avoid requiring addition of the intricate `fintegrated-as` in the 
test (but also from users). It seems that the clang driver creates a program 
action. In cases where we have `fintegrated-as` it appends `-emit-obj` which is 
then converted to the `frontend::EmitObj` action. In that case clang-repl, just 
ignores this and replaces it with `frontend::EmitLLVMOnly`. IIUC, AIX has a 
default `fno-integrated-as` and I am still puzzled (and cannot find the 
relevant code) what is the program action kind for AIX in that case 
(`frontend::???`). FWIW, I tried to add some functionality to write it to the 
diagnostics message but it requires opening too many interfaces.

Maybe applying that diff can give us a hint:

  diff --git a/clang/lib/Interpreter/IncrementalParser.cpp 
b/clang/lib/Interpreter/IncrementalParser.cpp
  index 70baabfeb8fb..4c2292e0bde9 100644
  --- a/clang/lib/Interpreter/IncrementalParser.cpp
  +++ b/clang/lib/Interpreter/IncrementalParser.cpp
  @@ -55,6 +55,7 @@ public:
   std::errc::state_not_recoverable,
   "Driver initialization failed. "
   "Incremental mode for action is not supported");
  +printf("ActionKind=%d\n", CI.getFrontendOpts().ProgramAction);
   return Act;
 case frontend::ASTDump:
   LLVM_FALLTHROUGH;


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[PATCH] D102478: [Matrix] Emit assumption that matrix indices are valid.

[Dávid Bolvanský via Phabricator via cfe-commits]

xbolva00 added inline comments.



Comment at: llvm/include/llvm/IR/MatrixBuilder.h:242
+auto *Cmp = B.CreateICmpULT(Idx, NumElts);
+if (!isa(Cmp)) {
+  Function *TheFn =

Prefer early exit?


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[PATCH] D102118: [BPF] add support for 32 bit registers in inline asm

[Yonghong Song via Phabricator via cfe-commits]

yonghong-song added a comment.

Sure. I will merge the patch for you.


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[PATCH] D102478: [Matrix] Emit assumption that matrix indices are valid.

[Dávid Bolvanský via Phabricator via cfe-commits]

xbolva00 added inline comments.



Comment at: llvm/include/llvm/IR/MatrixBuilder.h:245
+  Intrinsic::getDeclaration(getModule(), Intrinsic::assume);
+  B.CreateCall(TheFn->getFunctionType(), TheFn, {Cmp}, Name);
+}

B.CreateAssumption(Cmp) may work well as well? and shorter.


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[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

[Zakk Chen via Phabricator via cfe-commits]

khchen updated this revision to Diff 345712.
khchen added a comment.
Herald added a subscriber: vkmr.

Pass -target-abi option into LTO codegenerator base on D102582 
 patch.

please see D102582  for more detal.


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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.h
  clang/lib/Driver/ToolChains/BareMetal.cpp
  clang/lib/Driver/ToolChains/BareMetal.h
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/lib/Driver/ToolChains/RISCVToolchain.cpp
  clang/lib/Driver/ToolChains/RISCVToolchain.h
  clang/test/Driver/lto.c

Index: clang/test/Driver/lto.c
===
--- clang/test/Driver/lto.c
+++ clang/test/Driver/lto.c
@@ -77,3 +77,14 @@
 //
 // CHECK-TUNING-LLDB:   "-plugin-opt=-debugger-tune=lldb"
 // CHECK-NO-TUNING-NOT: "-plugin-opt=-debugger-tune
+
+// Need to pass -target-abi in RISC-V target.
+// RUN: %clang -target riscv64-unknown-elf %s -fuse-ld=gold -flto \
+// RUN:   -mabi=lp64f -### 2>&1 | FileCheck %s --check-prefix=RISCV
+// RUN: %clang -target riscv64-unknown-elf %s -fuse-ld=lld -flto \
+// RUN:   -mabi=lp64f -### 2>&1 | FileCheck %s --check-prefix=RISCV
+// RUN: %clang -target riscv64-unknown-linux-gnu %s -fuse-ld=gold -flto \
+// RUN:   -mabi=lp64f -### 2>&1 | FileCheck %s --check-prefix=RISCV
+// RUN: %clang -target riscv64-unknown-linux-gnu %s -fuse-ld=lld -flto \
+// RUN:   -mabi=lp64f -### 2>&1 | FileCheck %s --check-prefix=RISCV
+// RISCV: "-plugin-opt=target-abi=lp64f"
Index: clang/lib/Driver/ToolChains/RISCVToolchain.h
===
--- clang/lib/Driver/ToolChains/RISCVToolchain.h
+++ clang/lib/Driver/ToolChains/RISCVToolchain.h
@@ -29,6 +29,7 @@
   RuntimeLibType GetDefaultRuntimeLibType() const override;
   UnwindLibType
   GetUnwindLibType(const llvm::opt::ArgList &Args) const override;
+  bool HasNativeLLVMSupport() const override { return true; }
   void
   AddClangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs,
 llvm::opt::ArgStringList &CC1Args) const override;
Index: clang/lib/Driver/ToolChains/RISCVToolchain.cpp
===
--- clang/lib/Driver/ToolChains/RISCVToolchain.cpp
+++ clang/lib/Driver/ToolChains/RISCVToolchain.cpp
@@ -7,6 +7,7 @@
 //===--===//
 
 #include "RISCVToolchain.h"
+#include "Arch/RISCV.h"
 #include "CommonArgs.h"
 #include "InputInfo.h"
 #include "clang/Driver/Compilation.h"
@@ -158,6 +159,12 @@
 CmdArgs.push_back("elf32lriscv");
   }
 
+  if (D.isUsingLTO()) {
+assert(!Inputs.empty() && "Must have at least one input.");
+addLTOOptions(ToolChain, Args, CmdArgs, Output, Inputs[0],
+  D.getLTOMode() == LTOK_Thin);
+  }
+
   std::string Linker = getToolChain().GetLinkerPath();
 
   bool WantCRTs =
Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -12,6 +12,7 @@
 #include "Arch/M68k.h"
 #include "Arch/Mips.h"
 #include "Arch/PPC.h"
+#include "Arch/RISCV.h"
 #include "Arch/SystemZ.h"
 #include "Arch/VE.h"
 #include "Arch/X86.h"
@@ -629,6 +630,17 @@
 
   addX86AlignBranchArgs(D, Args, CmdArgs, /*IsLTO=*/true);
 
+  // pass more options in specific target
+  switch (ToolChain.getArch()) {
+  default:
+break;
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64: {
+riscv::addRISCVTargetABIArgs(ToolChain, Args, CmdArgs);
+break;
+  }
+  }
+
   // Handle remark diagnostics on screen options: '-Rpass-*'.
   renderRpassOptions(Args, CmdArgs);
 
Index: clang/lib/Driver/ToolChains/BareMetal.h
===
--- clang/lib/Driver/ToolChains/BareMetal.h
+++ clang/lib/Driver/ToolChains/BareMetal.h
@@ -40,6 +40,7 @@
 
 public:
   bool useIntegratedAs() const override { return true; }
+  bool HasNativeLLVMSupport() const override { return true; }
   bool isCrossCompiling() const override { return true; }
   bool isPICDefault() const override { return false; }
   bool isPIEDefault() const override { return false; }
Index: clang/lib/Driver/ToolChains/BareMetal.cpp
===
--- clang/lib/Driver/ToolChains/BareMetal.cpp
+++ clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -319,6 +319,13 @@
   CmdArgs.push_back("-o");
   CmdArgs.push_back(Output.getFilename());
 
+  const Driver &D = TC.getDriver();
+  if (D.isUsingLTO()) {
+assert(!Inputs.empty() && "Must have at least one input.");
+addLTOOptions(TC, Args, CmdArgs, Output, Inputs[0],
+  

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added inline comments.



Comment at: clang/test/Driver/lto.c:81-90
+// Need to pass -target-abi in RISC-V target.
+// RUN: %clang -target riscv64-unknown-elf %s -fuse-ld=gold -flto \
+// RUN:   -mabi=lp64f -### 2>&1 | FileCheck %s --check-prefix=RISCV
+// RUN: %clang -target riscv64-unknown-elf %s -fuse-ld=lld -flto \
+// RUN:   -mabi=lp64f -### 2>&1 | FileCheck %s --check-prefix=RISCV
+// RUN: %clang -target riscv64-unknown-linux-gnu %s -fuse-ld=gold -flto \
+// RUN:   -mabi=lp64f -### 2>&1 | FileCheck %s --check-prefix=RISCV

This isn't a great test, anything that unconditionally passes 
`-plugin-opt=target-abi=lp64f` passes it. Test RV32 vs RV64 and with multiple 
ABIs for each to have confidence it does the right thing. Also have a test for 
not passing anything.


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[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

In D71387#1820995 , @efriedma wrote:

> Okay.  Please let me know if you want me to review anything.

Hi all,
We had encoded the target-abi into module now, but I feel it does not make 
sense to 
support overwrite ABI option and datalayout in TargetMahcine/IR by target-abi 
module flag in IR.

So I think maybe passing the target-abi option by clang driver can make 
anything more simple, the only one limitation is users need to specific `-mabi` 
in below cases at the last command.

  clang -target riscv64-unknown-elf a.c -flto -march=rv64gc -mabi=lp64f -o a.o
  clang -target riscv64-unknown-elf b.c -flto -march=rv64gc -mabi=lp64f -o b.o
  clang -target riscv64-unknown-elf a.o b.o -flto -march=rv64gc -o foo




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[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

[Jessica Clarke via Phabricator via cfe-commits]

jrtc27 added a comment.

In D71387#2762115 , @khchen wrote:

> In D71387#1820995 , @efriedma wrote:
>
>> Okay.  Please let me know if you want me to review anything.
>
> Hi all,
> We had encoded the target-abi into module now, but I feel it does not make 
> sense to 
> support overwrite ABI option and datalayout in TargetMahcine/IR by target-abi 
> module flag in IR.
>
> So I think maybe passing the target-abi option by clang driver can make 
> anything more simple, the only one limitation is users need to specific 
> `-mabi` in below cases at the last command.
>
>   clang -target riscv64-unknown-elf a.c -flto -march=rv64gc -mabi=lp64f -o a.o
>   clang -target riscv64-unknown-elf b.c -flto -march=rv64gc -mabi=lp64f -o b.o
>   clang -target riscv64-unknown-elf a.o b.o -flto -march=rv64gc -o foo

We should treat a missing `-mabi=` as an implicit 
`-mabi=whatever-the-default-is` for consistency with non-LTO. So yes, if the 
default ABI differs from what you've compiled the .o's with, you should have to 
provide it. This is needed already _anyway_ for multilib toolchains to 
determine the right library search path, though there are cases currently when 
you can get away without providing it, at least with Clang.


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[PATCH] D96033: [clang-repl] Land initial infrastructure for incremental parsing

[Hubert Tong via Phabricator via cfe-commits]

hubert.reinterpretcast added a comment.

In D96033#2762056 , @v.g.vassilev 
wrote:

> IIUC, AIX has a default `fno-integrated-as` and I am still puzzled (and 
> cannot find the relevant code) what is the program action kind for AIX in 
> that case (`frontend::???`).

This is rooted in `IsIntegratedAssemblerDefault` and the relevant code is more 
a relevant //lack// of code. The default implementation, 
`ToolChain::IsIntegratedAssemblerDefault`, returns `false`.

> Maybe applying that diff can give us a hint:

Output is:

  $ cat /home/hstong/.Liodine/llvmproj/clang/test/Interpreter/execute.cpp | 
/home/hstong/.Nrtphome/.Liodine/llcrossbld/dev/build/bin/clang-repl
  ActionKind=7
  clang-repl: Driver initialization failed. Incremental mode for action is not 
supported


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[clang] d29f7f1 - [clang] Fix ternary operator in the second for loop statement

[Richard Smith via cfe-commits]

Author: Danila Kutenin
Date: 2021-05-16T10:42:52-07:00
New Revision: d29f7f1a7b47345289d63318e7b2a28cc56e169d

URL: 
https://github.com/llvm/llvm-project/commit/d29f7f1a7b47345289d63318e7b2a28cc56e169d
DIFF: 
https://github.com/llvm/llvm-project/commit/d29f7f1a7b47345289d63318e7b2a28cc56e169d.diff

LOG: [clang] Fix ternary operator in the second for loop statement

Fix ternary operator in for loop argument, it was by mistake not set as 
CanBeForRangeDecl and led to incorrect codegen. It fixes 
https://bugs.llvm.org/show_bug.cgi?id=50038. I don't have commit rights. Danila 
Kutenin. kutdan...@yandex.ru

Reviewed By: rsmith

Differential Revision: https://reviews.llvm.org/D102502

Added: 
clang/test/CodeGenCXX/for-loop-init-ternary-operator-statement.cpp
clang/test/PCH/for-loop-init-ternary-operator-statement.cpp

Modified: 
clang/lib/Parse/ParseExprCXX.cpp
clang/lib/Parse/ParseTentative.cpp
clang/test/Parser/cxx2a-init-statement.cpp

Removed: 




diff  --git a/clang/lib/Parse/ParseExprCXX.cpp 
b/clang/lib/Parse/ParseExprCXX.cpp
index 644df55bf46e8..93f578edc09e6 100644
--- a/clang/lib/Parse/ParseExprCXX.cpp
+++ b/clang/lib/Parse/ParseExprCXX.cpp
@@ -2033,6 +2033,8 @@ Sema::ConditionResult 
Parser::ParseCXXCondition(StmtResult *InitStmt,
 DeclGroupPtrTy DG = ParseSimpleDeclaration(DeclaratorContext::ForInit,
DeclEnd, attrs, false, FRI);
 FRI->LoopVar = Actions.ActOnDeclStmt(DG, DeclStart, Tok.getLocation());
+assert((FRI->ColonLoc.isValid() || !DG) &&
+   "cannot find for range declaration");
 return Sema::ConditionResult();
   }
 

diff  --git a/clang/lib/Parse/ParseTentative.cpp 
b/clang/lib/Parse/ParseTentative.cpp
index 3bf2bc455bfe8..c0bfbbde40ac8 100644
--- a/clang/lib/Parse/ParseTentative.cpp
+++ b/clang/lib/Parse/ParseTentative.cpp
@@ -353,8 +353,8 @@ struct Parser::ConditionDeclarationOrInitStatementState {
   if (CanBeForRangeDecl) {
 // Skip until we hit a ')', ';', or a ':' with no matching '?'.
 // The final case is a for range declaration, the rest are not.
+unsigned QuestionColonDepth = 0;
 while (true) {
-  unsigned QuestionColonDepth = 0;
   P.SkipUntil({tok::r_paren, tok::semi, tok::question, tok::colon},
   StopBeforeMatch);
   if (P.Tok.is(tok::question))

diff  --git 
a/clang/test/CodeGenCXX/for-loop-init-ternary-operator-statement.cpp 
b/clang/test/CodeGenCXX/for-loop-init-ternary-operator-statement.cpp
new file mode 100644
index 0..a40898b0e84d1
--- /dev/null
+++ b/clang/test/CodeGenCXX/for-loop-init-ternary-operator-statement.cpp
@@ -0,0 +1,42 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | 
FileCheck %s
+
+// CHECK-LABEL: @_Z1fv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT:[[I:%.*]] = alloca i32, align 4
+// CHECK-NEXT:[[X:%.*]] = alloca i32, align 4
+// CHECK-NEXT:store i32 0, i32* [[I]], align 4
+// CHECK-NEXT:br label [[FOR_COND:%.*]]
+// CHECK:   for.cond:
+// CHECK-NEXT:[[TMP0:%.*]] = load i32, i32* [[I]], align 4
+// CHECK-NEXT:[[CMP:%.*]] = icmp slt i32 [[TMP0]], 2
+// CHECK-NEXT:[[TMP1:%.*]] = zext i1 [[CMP]] to i64
+// CHECK-NEXT:[[COND:%.*]] = select i1 [[CMP]], i32 1, i32 0
+// CHECK-NEXT:store i32 [[COND]], i32* [[X]], align 4
+// CHECK-NEXT:[[TMP2:%.*]] = load i32, i32* [[X]], align 4
+// CHECK-NEXT:[[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:br i1 [[TOBOOL]], label [[FOR_BODY:%.*]], label 
[[FOR_END:%.*]]
+// CHECK:   for.body:
+// CHECK-NEXT:[[TMP3:%.*]] = load i32, i32* [[X]], align 4
+// CHECK-NEXT:store i32 [[TMP3]], i32* [[RETVAL]], align 4
+// CHECK-NEXT:br label [[RETURN:%.*]]
+// CHECK:   for.inc:
+// CHECK-NEXT:[[TMP4:%.*]] = load i32, i32* [[I]], align 4
+// CHECK-NEXT:[[INC:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK-NEXT:store i32 [[INC]], i32* [[I]], align 4
+// CHECK-NEXT:br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
+// CHECK:   for.end:
+// CHECK-NEXT:store i32 0, i32* [[RETVAL]], align 4
+// CHECK-NEXT:br label [[RETURN]]
+// CHECK:   return:
+// CHECK-NEXT:[[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4
+// CHECK-NEXT:ret i32 [[TMP5]]
+//
+int f() {
+  for (int i = 0; int x = i < 2 ? 1 : 0; i++) {
+return x;
+  }
+  return 0;
+}
+

diff  --git a/clang/test/PCH/for-loop-init-ternary-operator-statement.cpp 
b/clang/test/PCH/for-loop-init-ternary-operator-statement.cpp
new file mode 100644
index 0..50819e79e6f6f
--- /dev/null
+++ b/clang/test/PCH/for-loop-init-ternary-operator-statement.cpp
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -emit-pch -o %t %s
+// RUN: %clang_cc1 -x ast -ast-print %t | Fil

[PATCH] D102502: [clang] Fix ternary operator in the second for loop statement

[Richard Smith - zygoloid via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd29f7f1a7b47: [clang] Fix ternary operator in the second for 
loop statement (authored by danlark, committed by rsmith).

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Files:
  clang/lib/Parse/ParseExprCXX.cpp
  clang/lib/Parse/ParseTentative.cpp
  clang/test/CodeGenCXX/for-loop-init-ternary-operator-statement.cpp
  clang/test/PCH/for-loop-init-ternary-operator-statement.cpp
  clang/test/Parser/cxx2a-init-statement.cpp

Index: clang/test/Parser/cxx2a-init-statement.cpp
===
--- clang/test/Parser/cxx2a-init-statement.cpp
+++ clang/test/Parser/cxx2a-init-statement.cpp
@@ -15,6 +15,8 @@
   int A<0>::*arr2[3];
   for (int n = 5; int A::*x : arr2) {}
 
+  for (int i = 0; int x = i < 2 ? 1 : 0; i++) {}
+
   F (*arr3[3])(int);
   for (int n = 5; F (*p)(int n) : arr3) {}
   for (int n = 5; F (*p)(int (n)) : arr3) {}
Index: clang/test/PCH/for-loop-init-ternary-operator-statement.cpp
===
--- /dev/null
+++ clang/test/PCH/for-loop-init-ternary-operator-statement.cpp
@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -emit-pch -o %t %s
+// RUN: %clang_cc1 -x ast -ast-print %t | FileCheck %s
+
+int f() {
+  // CHECK: for (int i = 0; x; i++) {
+  for (int i = 0; int x = i < 2 ? 1 : 0; i++) {
+return x;
+  }
+  return 0;
+}
+
Index: clang/test/CodeGenCXX/for-loop-init-ternary-operator-statement.cpp
===
--- /dev/null
+++ clang/test/CodeGenCXX/for-loop-init-ternary-operator-statement.cpp
@@ -0,0 +1,42 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @_Z1fv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT:[[I:%.*]] = alloca i32, align 4
+// CHECK-NEXT:[[X:%.*]] = alloca i32, align 4
+// CHECK-NEXT:store i32 0, i32* [[I]], align 4
+// CHECK-NEXT:br label [[FOR_COND:%.*]]
+// CHECK:   for.cond:
+// CHECK-NEXT:[[TMP0:%.*]] = load i32, i32* [[I]], align 4
+// CHECK-NEXT:[[CMP:%.*]] = icmp slt i32 [[TMP0]], 2
+// CHECK-NEXT:[[TMP1:%.*]] = zext i1 [[CMP]] to i64
+// CHECK-NEXT:[[COND:%.*]] = select i1 [[CMP]], i32 1, i32 0
+// CHECK-NEXT:store i32 [[COND]], i32* [[X]], align 4
+// CHECK-NEXT:[[TMP2:%.*]] = load i32, i32* [[X]], align 4
+// CHECK-NEXT:[[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-NEXT:br i1 [[TOBOOL]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+// CHECK:   for.body:
+// CHECK-NEXT:[[TMP3:%.*]] = load i32, i32* [[X]], align 4
+// CHECK-NEXT:store i32 [[TMP3]], i32* [[RETVAL]], align 4
+// CHECK-NEXT:br label [[RETURN:%.*]]
+// CHECK:   for.inc:
+// CHECK-NEXT:[[TMP4:%.*]] = load i32, i32* [[I]], align 4
+// CHECK-NEXT:[[INC:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK-NEXT:store i32 [[INC]], i32* [[I]], align 4
+// CHECK-NEXT:br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
+// CHECK:   for.end:
+// CHECK-NEXT:store i32 0, i32* [[RETVAL]], align 4
+// CHECK-NEXT:br label [[RETURN]]
+// CHECK:   return:
+// CHECK-NEXT:[[TMP5:%.*]] = load i32, i32* [[RETVAL]], align 4
+// CHECK-NEXT:ret i32 [[TMP5]]
+//
+int f() {
+  for (int i = 0; int x = i < 2 ? 1 : 0; i++) {
+return x;
+  }
+  return 0;
+}
+
Index: clang/lib/Parse/ParseTentative.cpp
===
--- clang/lib/Parse/ParseTentative.cpp
+++ clang/lib/Parse/ParseTentative.cpp
@@ -353,8 +353,8 @@
   if (CanBeForRangeDecl) {
 // Skip until we hit a ')', ';', or a ':' with no matching '?'.
 // The final case is a for range declaration, the rest are not.
+unsigned QuestionColonDepth = 0;
 while (true) {
-  unsigned QuestionColonDepth = 0;
   P.SkipUntil({tok::r_paren, tok::semi, tok::question, tok::colon},
   StopBeforeMatch);
   if (P.Tok.is(tok::question))
Index: clang/lib/Parse/ParseExprCXX.cpp
===
--- clang/lib/Parse/ParseExprCXX.cpp
+++ clang/lib/Parse/ParseExprCXX.cpp
@@ -2033,6 +2033,8 @@
 DeclGroupPtrTy DG = ParseSimpleDeclaration(DeclaratorContext::ForInit,
DeclEnd, attrs, false, FRI);
 FRI->LoopVar = Actions.ActOnDeclStmt(DG, DeclStart, Tok.getLocation());
+assert((FRI->ColonLoc.isValid() || !DG) &&
+   "cannot find for range declaration");
 return Sema::ConditionResult();
   }
 
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[clang] 803c52d - Recommit "[Clang,Driver] Add -fveclib=Darwin_libsystem_m support."

[Florian Hahn via cfe-commits]

Author: Florian Hahn
Date: 2021-05-16T18:49:53+01:00
New Revision: 803c52d0dba929652280a38dcf90c491ab33d03b

URL: 
https://github.com/llvm/llvm-project/commit/803c52d0dba929652280a38dcf90c491ab33d03b
DIFF: 
https://github.com/llvm/llvm-project/commit/803c52d0dba929652280a38dcf90c491ab33d03b.diff

LOG: Recommit "[Clang,Driver] Add -fveclib=Darwin_libsystem_m support."

Recommit D102489, with the test case requiring the AArch64 backend.

This reverts the revert 59b419adc6e608db8d7c31efcc37f34c0b57b7d0.

Added: 
clang/test/CodeGen/veclib-darwin-libsystem-m.c

Modified: 
clang/include/clang/Basic/CodeGenOptions.h
clang/include/clang/Driver/Options.td
clang/lib/CodeGen/BackendUtil.cpp
clang/test/Driver/autocomplete.c
clang/test/Driver/fveclib.c

Removed: 




diff  --git a/clang/include/clang/Basic/CodeGenOptions.h 
b/clang/include/clang/Basic/CodeGenOptions.h
index 90388b169f5e0..901013033ba6a 100644
--- a/clang/include/clang/Basic/CodeGenOptions.h
+++ b/clang/include/clang/Basic/CodeGenOptions.h
@@ -55,11 +55,12 @@ class CodeGenOptions : public CodeGenOptionsBase {
   };
 
   enum VectorLibrary {
-NoLibrary,  // Don't use any vector library.
-Accelerate, // Use the Accelerate framework.
-LIBMVEC,// GLIBC vector math library.
-MASSV,  // IBM MASS vector library.
-SVML// Intel short vector math library.
+NoLibrary, // Don't use any vector library.
+Accelerate,// Use the Accelerate framework.
+LIBMVEC,   // GLIBC vector math library.
+MASSV, // IBM MASS vector library.
+SVML,  // Intel short vector math library.
+Darwin_libsystem_m // Use Darwin's libsytem_m vector functions.
   };
 
   enum ObjCDispatchMethodKind {

diff  --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index c1d096f358d9e..303b5b95e76d7 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2171,9 +2171,10 @@ def fno_experimental_isel : Flag<["-"], 
"fno-experimental-isel">, Group;
 def fveclib : Joined<["-"], "fveclib=">, Group, Flags<[CC1Option]>,
 HelpText<"Use the given vector functions library">,
-Values<"Accelerate,libmvec,MASSV,SVML,none">,
+Values<"Accelerate,libmvec,MASSV,SVML,Darwin_libsystem_m,none">,
 NormalizedValuesScope<"CodeGenOptions">,
-NormalizedValues<["Accelerate", "LIBMVEC", "MASSV", "SVML", "NoLibrary"]>,
+NormalizedValues<["Accelerate", "LIBMVEC", "MASSV", "SVML",
+  "Darwin_libsystem_m", "NoLibrary"]>,
 MarshallingInfoEnum, "NoLibrary">;
 def fno_lax_vector_conversions : Flag<["-"], "fno-lax-vector-conversions">, 
Group,
   Alias, AliasArgs<["none"]>;

diff  --git a/clang/lib/CodeGen/BackendUtil.cpp 
b/clang/lib/CodeGen/BackendUtil.cpp
index e5a2a089563ef..837ffd0950753 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -402,6 +402,10 @@ static TargetLibraryInfoImpl *createTLII(llvm::Triple 
&TargetTriple,
   case CodeGenOptions::SVML:
 TLII->addVectorizableFunctionsFromVecLib(TargetLibraryInfoImpl::SVML);
 break;
+  case CodeGenOptions::Darwin_libsystem_m:
+TLII->addVectorizableFunctionsFromVecLib(
+TargetLibraryInfoImpl::DarwinLibSystemM);
+break;
   default:
 break;
   }

diff  --git a/clang/test/CodeGen/veclib-darwin-libsystem-m.c 
b/clang/test/CodeGen/veclib-darwin-libsystem-m.c
new file mode 100644
index 0..23915147ded14
--- /dev/null
+++ b/clang/test/CodeGen/veclib-darwin-libsystem-m.c
@@ -0,0 +1,16 @@
+// RUN: %clang_cc1 -fveclib=Darwin_libsystem_m -triple arm64-apple-darwin %s 
-target-cpu apple-a7 -vectorize-loops -emit-llvm -O3 -o - | FileCheck %s
+
+// REQUIRES: aarch64-registered-target
+
+// Make sure -fveclib=Darwin_libsystem_m gets passed through to LLVM as
+// expected: a call to _simd_sin_f4 should be generated.
+
+extern float sinf(float);
+
+// CHECK-LABEL: define{{.*}}@apply_sin
+// CHECK: call <4 x float> @_simd_sin_f4(
+//
+void apply_sin(float *A, float *B, float *C, unsigned N) {
+  for (unsigned i = 0; i < N; i++)
+C[i] = sinf(A[i]) + sinf(B[i]);
+}

diff  --git a/clang/test/Driver/autocomplete.c 
b/clang/test/Driver/autocomplete.c
index 85bf6c7912a45..3efe141de6fc1 100644
--- a/clang/test/Driver/autocomplete.c
+++ b/clang/test/Driver/autocomplete.c
@@ -76,6 +76,7 @@
 // FLTOALL-NEXT: thin
 // RUN: %clang --autocomplete=-fveclib= | FileCheck %s -check-prefix=FVECLIBALL
 // FVECLIBALL: Accelerate
+// FVECLIBALL-NEXT: Darwin_libsystem_m
 // FVECLIBALL-NEXT: libmvec
 // FVECLIBALL-NEXT: MASSV
 // FVECLIBALL-NEXT: none

diff  --git a/clang/test/Driver/fveclib.c b/clang/test/Driver/fveclib.c
index 5036422f57913..2bf7558a02af8 100644
--- a/clang/test/Driver/fveclib.c
+++ b/clang/test/Driver/fveclib.c
@@ -2,12 +2,14 @@
 // RUN: %clang -### -c -fveclib=Accelerate %s 2>&1 | FileCh

[PATCH] D102489: [Clang,Driver] Add -fveclib=Darwin_libsystem_m support.

[Florian Hahn via Phabricator via cfe-commits]

fhahn added a comment.

In D102489#2761195 , @dyung wrote:

> The test added in this commit was failing on the PS4 bot 
> (https://lab.llvm.org/buildbot/#/builders/139/builds/4059). I've reverted the 
> change in 59b419adc6e608db8d7c31efcc37f34c0b57b7d0 
>  to get 
> the bot green again.



In D102489#2761313 , @thakis wrote:

> (Failed on our bots too -- the new test probably just needs a ` REQUIRES: 
> aarch64-registered-target`)

Thanks! I re-landed the change  in 803c52d0dba9 
 with ` 
REQUIRES: aarch64-registered-target`


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[clang] 833e9b2 - [BPF] add support for 32 bit registers in inline asm

[Yonghong Song via cfe-commits]

Author: Alessandro Decina
Date: 2021-05-16T11:01:47-07:00
New Revision: 833e9b2ea7a7290f8833d524c8f8865558c1016a

URL: 
https://github.com/llvm/llvm-project/commit/833e9b2ea7a7290f8833d524c8f8865558c1016a
DIFF: 
https://github.com/llvm/llvm-project/commit/833e9b2ea7a7290f8833d524c8f8865558c1016a.diff

LOG: [BPF] add support for 32 bit registers in inline asm

Add "w" constraint type which allows selecting 32 bit registers.
32 bit registers were added in 
https://reviews.llvm.org/rGca31c3bb3ff149850b664838fbbc7d40ce571879.

Differential Revision: https://reviews.llvm.org/D102118

Added: 
clang/test/CodeGen/bpf-inline-asm.c
llvm/test/CodeGen/BPF/inlineasm-wreg.ll

Modified: 
clang/lib/Basic/Targets/BPF.cpp
clang/lib/Basic/Targets/BPF.h
llvm/lib/Target/BPF/BPFISelLowering.cpp
llvm/lib/Target/BPF/BPFISelLowering.h

Removed: 




diff  --git a/clang/lib/Basic/Targets/BPF.cpp b/clang/lib/Basic/Targets/BPF.cpp
index 2fe2450b9a654..0b0298df30a57 100644
--- a/clang/lib/Basic/Targets/BPF.cpp
+++ b/clang/lib/Basic/Targets/BPF.cpp
@@ -46,3 +46,14 @@ ArrayRef BPFTargetInfo::getTargetBuiltins() 
const {
   return llvm::makeArrayRef(BuiltinInfo, clang::BPF::LastTSBuiltin -
  Builtin::FirstTSBuiltin);
 }
+
+bool BPFTargetInfo::handleTargetFeatures(std::vector &Features,
+ DiagnosticsEngine &Diags) {
+  for (const auto &Feature : Features) {
+if (Feature == "+alu32") {
+  HasAlu32 = true;
+}
+  }
+
+  return true;
+}

diff  --git a/clang/lib/Basic/Targets/BPF.h b/clang/lib/Basic/Targets/BPF.h
index 06b451db189af..393a91ff53a51 100644
--- a/clang/lib/Basic/Targets/BPF.h
+++ b/clang/lib/Basic/Targets/BPF.h
@@ -23,6 +23,7 @@ namespace targets {
 
 class LLVM_LIBRARY_VISIBILITY BPFTargetInfo : public TargetInfo {
   static const Builtin::Info BuiltinInfo[];
+  bool HasAlu32 = false;
 
 public:
   BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
@@ -55,6 +56,8 @@ class LLVM_LIBRARY_VISIBILITY BPFTargetInfo : public 
TargetInfo {
  bool Enabled) const override {
 Features[Name] = Enabled;
   }
+  bool handleTargetFeatures(std::vector &Features,
+DiagnosticsEngine &Diags) override;
 
   ArrayRef getTargetBuiltins() const override;
 
@@ -68,7 +71,16 @@ class LLVM_LIBRARY_VISIBILITY BPFTargetInfo : public 
TargetInfo {
   ArrayRef getGCCRegNames() const override { return None; }
 
   bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &info) const override {
+ TargetInfo::ConstraintInfo &Info) const override {
+switch (*Name) {
+default:
+  break;
+case 'w':
+  if (HasAlu32) {
+Info.setAllowsRegister();
+  }
+  break;
+}
 return true;
   }
 
@@ -93,6 +105,10 @@ class LLVM_LIBRARY_VISIBILITY BPFTargetInfo : public 
TargetInfo {
   void fillValidCPUList(SmallVectorImpl &Values) const override;
 
   bool setCPU(const std::string &Name) override {
+if (Name == "v3") {
+  HasAlu32 = true;
+}
+
 StringRef CPUName(Name);
 return isValidCPUName(CPUName);
   }

diff  --git a/clang/test/CodeGen/bpf-inline-asm.c 
b/clang/test/CodeGen/bpf-inline-asm.c
new file mode 100644
index 0..d85bcbe02bc3f
--- /dev/null
+++ b/clang/test/CodeGen/bpf-inline-asm.c
@@ -0,0 +1,31 @@
+// REQUIRES: bpf-registered-target
+// RUN: %clang -target bpf -emit-llvm -S -Xclang -target-feature -Xclang 
+alu32 %s -o - | FileCheck %s
+// RUN: %clang -target bpf -emit-llvm -S -mcpu=v3 %s -o - | FileCheck %s
+
+void test_generic_constraints(int var32, long var64) {
+  asm("%0 = %1"
+  : "=r"(var32)
+  : "0"(var32));
+  // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32*
+  // CHECK: call i32 asm "$0 = $1", "=r,0"(i32 [[R32_ARG]])
+
+  asm("%0 = %1"
+  : "=r"(var64)
+  : "0"(var64));
+  // CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, i64*
+  // CHECK: call i64 asm "$0 = $1", "=r,0"(i64 [[R64_ARG]])
+
+  asm("%0 = %1"
+  : "=r"(var64)
+  : "r"(var64));
+  // CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, i64*
+  // CHECK: call i64 asm "$0 = $1", "=r,r"(i64 [[R64_ARG]])
+}
+
+void test_constraint_w(int a) {
+  asm("%0 = %1"
+  : "=w"(a)
+  : "w"(a));
+  // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32*
+  // CHECK: call i32 asm "$0 = $1", "=w,w"(i32 [[R32_ARG]])
+}

diff  --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp 
b/llvm/lib/Target/BPF/BPFISelLowering.cpp
index 8b16e0d3a23d0..c543dfcfca953 100644
--- a/llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -220,6 +220,20 @@ bool BPFTargetLowering::isZExtFree(EVT VT1, EVT VT2) const 
{
   return NumBits1 == 32 && NumBits2 == 64;
 }
 
+BPFTargetLowering::ConstraintType
+BPFTargetLowering::getConstraintType(StringRef Constraint) const

[PATCH] D102118: [BPF] add support for 32 bit registers in inline asm

[Yonghong Song via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG833e9b2ea7a7: [BPF] add support for 32 bit registers in 
inline asm (authored by alessandrod, committed by yonghong-song).

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Files:
  clang/lib/Basic/Targets/BPF.cpp
  clang/lib/Basic/Targets/BPF.h
  clang/test/CodeGen/bpf-inline-asm.c
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFISelLowering.h
  llvm/test/CodeGen/BPF/inlineasm-wreg.ll

Index: llvm/test/CodeGen/BPF/inlineasm-wreg.ll
===
--- /dev/null
+++ llvm/test/CodeGen/BPF/inlineasm-wreg.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=bpfel -mattr=+alu32 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -march=bpfeb -mattr=+alu32 -verify-machineinstrs | FileCheck %s
+
+; Test that %w works as input constraint
+; CHECK-LABEL: test_inlineasm_w_input_constraint
+define dso_local i32 @test_inlineasm_w_input_constraint() {
+  tail call void asm sideeffect "w0 = $0", "w"(i32 42)
+; CHECK: w0 = w1
+  ret i32 42
+}
+
+; Test that %w works as output constraint
+; CHECK-LABEL: test_inlineasm_w_output_constraint
+define dso_local i32 @test_inlineasm_w_output_constraint() {
+  %1 = tail call i32 asm sideeffect "$0 = $1", "=w,i"(i32 42)
+; CHECK: w0 = 42
+  ret i32 %1
+}
Index: llvm/lib/Target/BPF/BPFISelLowering.h
===
--- llvm/lib/Target/BPF/BPFISelLowering.h
+++ llvm/lib/Target/BPF/BPFISelLowering.h
@@ -46,6 +46,9 @@
   // with the given GlobalAddress is legal.
   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 
+  BPFTargetLowering::ConstraintType
+  getConstraintType(StringRef Constraint) const override;
+
   std::pair
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override;
Index: llvm/lib/Target/BPF/BPFISelLowering.cpp
===
--- llvm/lib/Target/BPF/BPFISelLowering.cpp
+++ llvm/lib/Target/BPF/BPFISelLowering.cpp
@@ -220,6 +220,20 @@
   return NumBits1 == 32 && NumBits2 == 64;
 }
 
+BPFTargetLowering::ConstraintType
+BPFTargetLowering::getConstraintType(StringRef Constraint) const {
+  if (Constraint.size() == 1) {
+switch (Constraint[0]) {
+default:
+  break;
+case 'w':
+  return C_RegisterClass;
+}
+  }
+
+  return TargetLowering::getConstraintType(Constraint);
+}
+
 std::pair
 BPFTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 StringRef Constraint,
@@ -229,6 +243,10 @@
 switch (Constraint[0]) {
 case 'r': // GENERAL_REGS
   return std::make_pair(0U, &BPF::GPRRegClass);
+case 'w':
+  if (HasAlu32)
+return std::make_pair(0U, &BPF::GPR32RegClass);
+  break;
 default:
   break;
 }
Index: clang/test/CodeGen/bpf-inline-asm.c
===
--- /dev/null
+++ clang/test/CodeGen/bpf-inline-asm.c
@@ -0,0 +1,31 @@
+// REQUIRES: bpf-registered-target
+// RUN: %clang -target bpf -emit-llvm -S -Xclang -target-feature -Xclang +alu32 %s -o - | FileCheck %s
+// RUN: %clang -target bpf -emit-llvm -S -mcpu=v3 %s -o - | FileCheck %s
+
+void test_generic_constraints(int var32, long var64) {
+  asm("%0 = %1"
+  : "=r"(var32)
+  : "0"(var32));
+  // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32*
+  // CHECK: call i32 asm "$0 = $1", "=r,0"(i32 [[R32_ARG]])
+
+  asm("%0 = %1"
+  : "=r"(var64)
+  : "0"(var64));
+  // CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, i64*
+  // CHECK: call i64 asm "$0 = $1", "=r,0"(i64 [[R64_ARG]])
+
+  asm("%0 = %1"
+  : "=r"(var64)
+  : "r"(var64));
+  // CHECK: [[R64_ARG:%[a-zA-Z0-9]+]] = load i64, i64*
+  // CHECK: call i64 asm "$0 = $1", "=r,r"(i64 [[R64_ARG]])
+}
+
+void test_constraint_w(int a) {
+  asm("%0 = %1"
+  : "=w"(a)
+  : "w"(a));
+  // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32*
+  // CHECK: call i32 asm "$0 = $1", "=w,w"(i32 [[R32_ARG]])
+}
Index: clang/lib/Basic/Targets/BPF.h
===
--- clang/lib/Basic/Targets/BPF.h
+++ clang/lib/Basic/Targets/BPF.h
@@ -23,6 +23,7 @@
 
 class LLVM_LIBRARY_VISIBILITY BPFTargetInfo : public TargetInfo {
   static const Builtin::Info BuiltinInfo[];
+  bool HasAlu32 = false;
 
 public:
   BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
@@ -55,6 +56,8 @@
  bool Enabled) const override {
 Features[Name] = Enabled;
   }
+  bool handleTargetFeatures(std::vector &Features,
+DiagnosticsEngine &Diags) override;
 
   ArrayRef getTargetBuiltins() const override;
 
@@ -68,7 +71,16 @@
   ArrayRef getGCCRegNames

[PATCH] D102576: [clang-tidy] cppcoreguidelines-avoid-do-while: a new check

[Nathan James via Phabricator via cfe-commits]

njames93 added a comment.

This is going to be very noisey for codebases that use a do...while macro:

  #define MACRO() do { Something(); With(); Multiple(); Statements(); } while 
(false)

Maybe you should ignore do statements that are in macro expansions as well as 
potentially do statements with a false condition.


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[PATCH] D96033: [clang-repl] Land initial infrastructure for incremental parsing

[Vassil Vassilev via Phabricator via cfe-commits]

v.g.vassilev added a comment.

In D96033#2762134 , 
@hubert.reinterpretcast wrote:

> In D96033#2762056 , @v.g.vassilev 
> wrote:
>
>> IIUC, AIX has a default `fno-integrated-as` and I am still puzzled (and 
>> cannot find the relevant code) what is the program action kind for AIX in 
>> that case (`frontend::???`).
>
> This is rooted in `IsIntegratedAssemblerDefault` and the relevant code is 
> more a relevant //lack// of code. The default implementation, 
> `ToolChain::IsIntegratedAssemblerDefault`, returns `false`.
>
>> Maybe applying that diff can give us a hint:
>
> Output is:
>
>   $ cat /home/hstong/.Liodine/llvmproj/clang/test/Interpreter/execute.cpp | 
> /home/hstong/.Nrtphome/.Liodine/llcrossbld/dev/build/bin/clang-repl
>   ActionKind=7
>   clang-repl: Driver initialization failed. Incremental mode for action is 
> not supported

Thanks!

That patch should probably get us to a point where we can mark the test as 
`XFAIL: system-aix`

  diff --git a/clang/lib/Interpreter/IncrementalParser.cpp 
b/clang/lib/Interpreter/IncrementalParser.cpp
  index 70baabfeb8fb..84b4d779d43c 100644
  --- a/clang/lib/Interpreter/IncrementalParser.cpp
  +++ b/clang/lib/Interpreter/IncrementalParser.cpp
  @@ -54,7 +54,8 @@ public:
   Err = llvm::createStringError(
   std::errc::state_not_recoverable,
   "Driver initialization failed. "
  -"Incremental mode for action is not supported");
  +"Incremental mode for action %d is not supported",
  +CI.getFrontendOpts().ProgramAction);
   return Act;
 case frontend::ASTDump:
   LLVM_FALLTHROUGH;
  @@ -63,6 +64,8 @@ public:
 case frontend::ParseSyntaxOnly:
   Act = CreateFrontendAction(CI);
   break;
  +  case frontend::EmitAssembly:
  +LLVM_FALLTHROUGH;
 case frontend::EmitObj:
   LLVM_FALLTHROUGH;
 case frontend::EmitLLVMOnly:

If that works on your platform I will happily open a review for the changes.


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[PATCH] D91628: [SystemZ][NFC] Group SystemZ tests in SystemZ folder

[Fangrui Song via Phabricator via cfe-commits]

MaskRay added a comment.

.ll -> .s tests should be placed in llvm/test/CodeGen/SystemZ, not in clang


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[PATCH] D102583: -fno-semantic-interposition: Don't set dso_local on GlobalVariable

[Fangrui Song via Phabricator via cfe-commits]

MaskRay created this revision.
MaskRay added reviewers: foutrelis, rnk, serge-sans-paille, xbolva00.
MaskRay requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

`clang -fpic -fno-semantic-interposition` may set dso_local on variables for 
-fpic.

GCC folks consider there are 'address interposition' and 'semantic 
interposition',
and 'disabling semantic interposition' can optimize function calls but
cannot change variable references to use local aliases
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100483).

This patch removes dso_local for variables in
`clang -fpic -fno-semantic-interposition` mode so that the built shared objects 
can
work with copy relocations.

Example:

  // a.c
  int var;
  int *addr() { return var; }
  
  // old: cannot be interposed
  movslq  .Lvar$local(%rip), %rax
  // new: can be interposed
  movqvar@GOTPCREL(%rip), %rax
  movslq  (%rax), %rax

The local alias lowering for `GlobalVariable`s is kept in case there is a
future option allowing local aliases.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102583

Files:
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c
  clang/test/CodeGen/attr-weakref2.c
  clang/test/CodeGen/semantic-interposition.c
  clang/test/CodeGenCUDA/device-stub.cu
  clang/test/CodeGenCUDA/device-var-linkage.cu
  clang/test/CodeGenCUDA/managed-var.cu
  clang/test/CodeGenCUDA/static-device-var-rdc.cu
  clang/test/OpenMP/declare_target_only_one_side_compilation.cpp

Index: clang/test/OpenMP/declare_target_only_one_side_compilation.cpp
===
--- clang/test/OpenMP/declare_target_only_one_side_compilation.cpp
+++ clang/test/OpenMP/declare_target_only_one_side_compilation.cpp
@@ -67,9 +67,9 @@
 // DEVICE-NOT: llvm.used
 // DEVICE-NOT: omp_offload
 
-// HOST-DAG: @G7 = dso_local global i32 0, align 4
+// HOST-DAG: @G7 = global i32 0, align 4
 // HOST-DAG: @_ZL2G8 = internal global i32 0, align 4
-// HOST-DAG: @G9 = dso_local global i32 0, align 4
+// HOST-DAG: @G9 = global i32 0, align 4
 // HOST-DAG: @_ZL3G10 = internal global i32 0, align 4
-// HOST-DAG: @G11 = dso_local global i32 0, align 4
+// HOST-DAG: @G11 = global i32 0, align 4
 // HOST-DAG: @_ZL3G12 = internal global i32 0, align 4
Index: clang/test/CodeGenCUDA/static-device-var-rdc.cu
===
--- clang/test/CodeGenCUDA/static-device-var-rdc.cu
+++ clang/test/CodeGenCUDA/static-device-var-rdc.cu
@@ -51,14 +51,14 @@
 // HOST-DAG: @_ZL1y = internal global i32 undef
 
 // Test normal static device variables
-// INT-DEV-DAG: @_ZL1x = dso_local addrspace(1) externally_initialized global i32 0
+// INT-DEV-DAG: @_ZL1x = addrspace(1) externally_initialized global i32 0
 // INT-HOST-DAG: @[[DEVNAMEX:[0-9]+]] = {{.*}}c"_ZL1x\00"
 
 // Test externalized static device variables
-// EXT-DEV-DAG: @_ZL1x.static.[[HASH:.*]] = dso_local addrspace(1) externally_initialized global i32 0
+// EXT-DEV-DAG: @_ZL1x.static.[[HASH:.*]] = addrspace(1) externally_initialized global i32 0
 // EXT-HOST-DAG: @[[DEVNAMEX:[0-9]+]] = {{.*}}c"_ZL1x.static.[[HASH:.*]]\00"
 
-// POSTFIX: @_ZL1x.static.[[HASH:.*]] = dso_local addrspace(1) externally_initialized global i32 0
+// POSTFIX: @_ZL1x.static.[[HASH:.*]] = addrspace(1) externally_initialized global i32 0
 // POSTFIX: @[[DEVNAMEX:[0-9]+]] = {{.*}}c"_ZL1x.static.[[HASH]]\00"
 
 static __device__ int x;
@@ -69,11 +69,11 @@
 static __device__ int x2;
 
 // Test normal static device variables
-// INT-DEV-DAG: @_ZL1y = dso_local addrspace(4) externally_initialized global i32 0
+// INT-DEV-DAG: @_ZL1y = addrspace(4) externally_initialized global i32 0
 // INT-HOST-DAG: @[[DEVNAMEY:[0-9]+]] = {{.*}}c"_ZL1y\00"
 
 // Test externalized static device variables
-// EXT-DEV-DAG: @_ZL1y.static.[[HASH]] = dso_local addrspace(4) externally_initialized global i32 0
+// EXT-DEV-DAG: @_ZL1y.static.[[HASH]] = addrspace(4) externally_initialized global i32 0
 // EXT-HOST-DAG: @[[DEVNAMEY:[0-9]+]] = {{.*}}c"_ZL1y.static.[[HASH]]\00"
 
 static __constant__ int y;
Index: clang/test/CodeGenCUDA/managed-var.cu
===
--- clang/test/CodeGenCUDA/managed-var.cu
+++ clang/test/CodeGenCUDA/managed-var.cu
@@ -27,21 +27,21 @@
   float x,y,z;
 };
 
-// DEV-DAG: @x.managed = dso_local addrspace(1) externally_initialized global i32 1, align 4
-// DEV-DAG: @x = dso_local addrspace(1) externally_initialized global i32 addrspace(1)* null
+// DEV-DAG: @x.managed = addrspace(1) externally_initialized global i32 1, align 4
+// DEV-DAG: @x = addrspace(1) externally_initialized global i32 addrspace(1)* null
 // NORDC-DAG: @x.managed = internal global i32 1
-// RDC-DAG: @x.managed = dso_local global i32 1
+// RDC-DAG: @x.managed = global i32 1
 // NORDC-DAG: @x = internal externally_initialized global i32* null
-// RDC

[PATCH] D102585: [M68k] Support inline asm operands w/ simple constraints

[Min-Yih Hsu via Phabricator via cfe-commits]

myhsu created this revision.
myhsu added reviewers: echristo, craig.topper.
Herald added a subscriber: hiraditya.
myhsu requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch adds supports for inline assembly operands and some simple
operand constraints, including register and constant operands.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102585

Files:
  clang/lib/Basic/Targets/M68k.cpp
  clang/lib/Basic/Targets/M68k.h
  clang/test/Sema/inline-asm-validate-m68k.c
  llvm/lib/Target/M68k/M68kAsmPrinter.cpp
  llvm/lib/Target/M68k/M68kAsmPrinter.h
  llvm/lib/Target/M68k/M68kISelLowering.cpp
  llvm/lib/Target/M68k/M68kISelLowering.h
  llvm/test/CodeGen/M68k/inline-asm.ll

Index: llvm/test/CodeGen/M68k/inline-asm.ll
===
--- /dev/null
+++ llvm/test/CodeGen/M68k/inline-asm.ll
@@ -0,0 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=m68k < %s -o - | FileCheck %s
+
+; This function is verifying constant constraints that can NOT
+; be easily checked by Clang. For example, 'K' and 'M' are both
+; constraints for values that are outside certain numerical range.
+define void @constant_constraints() {
+; CHECK-LABEL: constant_constraints:
+; CHECK: .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %entry
+; CHECK-NEXT:;APP
+; CHECK-NEXT:move.l #-129, %d1
+; CHECK-NEXT:;NO_APP
+; CHECK-NEXT:;APP
+; CHECK-NEXT:move.l #128, %d1
+; CHECK-NEXT:;NO_APP
+; CHECK-NEXT:;APP
+; CHECK-NEXT:move.l #-257, %d1
+; CHECK-NEXT:;NO_APP
+; CHECK-NEXT:;APP
+; CHECK-NEXT:move.l #256, %d1
+; CHECK-NEXT:;NO_APP
+; CHECK-NEXT:;APP
+; CHECK-NEXT:move.l #-32769, %d1
+; CHECK-NEXT:;NO_APP
+; CHECK-NEXT:;APP
+; CHECK-NEXT:move.l #32768, %d1
+; CHECK-NEXT:;NO_APP
+; CHECK-NEXT:rts
+entry:
+  call void asm sideeffect "move.l $0, %d1", "K"(i32 -129)
+  call void asm sideeffect "move.l $0, %d1", "K"(i32 128)
+  call void asm sideeffect "move.l $0, %d1", "M"(i32 -257)
+  call void asm sideeffect "move.l $0, %d1", "M"(i32 256)
+  call void asm sideeffect "move.l $0, %d1", "^Cj"(i32 -32769)
+  call void asm sideeffect "move.l $0, %d1", "^Cj"(i32 32768)
+  ret void
+}
+
+define void @register_constraints() {
+; CHECK-LABEL: register_constraints:
+; CHECK: .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %entry
+; CHECK-NEXT:sub.l #4, %sp
+; CHECK-NEXT:.cfi_def_cfa_offset -8
+; CHECK-NEXT:;APP
+; CHECK-NEXT:move.l #94, %d0
+; CHECK-NEXT:;NO_APP
+; CHECK-NEXT:move.l %d0, (0,%sp)
+; CHECK-NEXT:;APP
+; CHECK-NEXT:move.l #87, %d0
+; CHECK-NEXT:;NO_APP
+; CHECK-NEXT:move.l %d0, (0,%sp)
+; CHECK-NEXT:;APP
+; CHECK-NEXT:move.l #66, %a0
+; CHECK-NEXT:;NO_APP
+; CHECK-NEXT:move.l %a0, (0,%sp)
+; CHECK-NEXT:add.l #4, %sp
+; CHECK-NEXT:rts
+entry:
+  %out = alloca i32, align 4
+  %0 = call i32 asm sideeffect "move.l #94, $0", "=r"()
+  store i32 %0, i32* %out, align 4
+  %1 = call i32 asm sideeffect "move.l #87, $0", "=d"()
+  store i32 %1, i32* %out, align 4
+  %2 = call i32 asm sideeffect "move.l #66, $0", "=a"()
+  store i32 %2, i32* %out, align 4
+  ret void
+}
+
Index: llvm/lib/Target/M68k/M68kISelLowering.h
===
--- llvm/lib/Target/M68k/M68kISelLowering.h
+++ llvm/lib/Target/M68k/M68kISelLowering.h
@@ -156,6 +156,17 @@
  unsigned JTI,
  MCContext &Ctx) const override;
 
+  ConstraintType getConstraintType(StringRef ConstraintStr) const override;
+
+  std::pair
+  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
+   StringRef Constraint, MVT VT) const override;
+
+  // Lower operand with C_Immediate and C_Other constraint type
+  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
+std::vector &Ops,
+SelectionDAG &DAG) const override;
+
   MachineBasicBlock *
   EmitInstrWithCustomInserter(MachineInstr &MI,
   MachineBasicBlock *MBB) const override;
Index: llvm/lib/Target/M68k/M68kISelLowering.cpp
===
--- llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -2689,6 +2689,193 @@
   return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
 }
 
+M68kTargetLowering::ConstraintType
+M68kTargetLowering::getConstraintType(StringRef Constraint) const {
+  if (Constraint.size() > 0) {
+switch (Constraint[0]) {
+case 'a':
+case 'd':
+  return C_RegisterClass;
+case 'I':
+case 'J':
+case 'K':
+case 'L':
+case 'M':
+case 'N':
+case 'O':
+case 'P':
+ 

[PATCH] D102586: [Clang] Do not discard arguments for non-builtin CXX11-style attributes

[Till Schnittka via Phabricator via cfe-commits]

Till created this revision.
Till requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

When parsing unkown CXX11-style attributes, clang discards the
argument lists, propably to skip over non-c++ expressions.

However, it seems like this has not been updated for user-defined
attributes using the ParsedAttrInfoRegistry (e.G. in
clang/examples/Attribute/Attribute.cpp);
clang::hasAttribute only returns a version number for builtin
attributes.

This uses ParsedAttrInfo::get to check if an attribute is known
to the attribute registry, because this is currently the only
place where these attributes are instanciated.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D102586

Files:
  clang/lib/Parse/ParseDeclCXX.cpp


Index: clang/lib/Parse/ParseDeclCXX.cpp
===
--- clang/lib/Parse/ParseDeclCXX.cpp
+++ clang/lib/Parse/ParseDeclCXX.cpp
@@ -4098,11 +4098,18 @@
   const LangOptions &LO = getLangOpts();
   ParsedAttr::Syntax Syntax =
   LO.CPlusPlus ? ParsedAttr::AS_CXX11 : ParsedAttr::AS_C2x;
+  bool IsKnownRegisteredAttribute =
+  ParsedAttrInfo::get(AttributeCommonInfo(AttrName, ScopeName,
+  SourceRange(LParenLoc, *EndLoc),
+  *EndLoc,
+  AttributeCommonInfo::AS_CXX11))
+  .AttrKind != AttributeCommonInfo::UnknownAttribute;
 
   // If the attribute isn't known, we will not attempt to parse any
   // arguments.
   if (!hasAttribute(LO.CPlusPlus ? AttrSyntax::CXX : AttrSyntax::C, ScopeName,
-AttrName, getTargetInfo(), getLangOpts())) {
+AttrName, getTargetInfo(), getLangOpts()) &&
+  !IsKnownRegisteredAttribute) {
 // Eat the left paren, then skip to the ending right paren.
 ConsumeParen();
 SkipUntil(tok::r_paren);


Index: clang/lib/Parse/ParseDeclCXX.cpp
===
--- clang/lib/Parse/ParseDeclCXX.cpp
+++ clang/lib/Parse/ParseDeclCXX.cpp
@@ -4098,11 +4098,18 @@
   const LangOptions &LO = getLangOpts();
   ParsedAttr::Syntax Syntax =
   LO.CPlusPlus ? ParsedAttr::AS_CXX11 : ParsedAttr::AS_C2x;
+  bool IsKnownRegisteredAttribute =
+  ParsedAttrInfo::get(AttributeCommonInfo(AttrName, ScopeName,
+  SourceRange(LParenLoc, *EndLoc),
+  *EndLoc,
+  AttributeCommonInfo::AS_CXX11))
+  .AttrKind != AttributeCommonInfo::UnknownAttribute;
 
   // If the attribute isn't known, we will not attempt to parse any
   // arguments.
   if (!hasAttribute(LO.CPlusPlus ? AttrSyntax::CXX : AttrSyntax::C, ScopeName,
-AttrName, getTargetInfo(), getLangOpts())) {
+AttrName, getTargetInfo(), getLangOpts()) &&
+  !IsKnownRegisteredAttribute) {
 // Eat the left paren, then skip to the ending right paren.
 ConsumeParen();
 SkipUntil(tok::r_paren);
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[PATCH] D80344: [Windows SEH]: HARDWARE EXCEPTION HANDLING (MSVC -EHa) - Part 1

[Ten Tzen via Phabricator via cfe-commits]

tentzen added a comment.

Passed many CodeGen related test suites over the weekend.
It landed in..

commit 9ca9be098fedb14182c50c9dd700f3fa91c8d4c7 (HEAD -> main)
Author: Ten Tzen 
Date:   Sun May 16 18:12:47 2021 -0700

  [Windows SEH]: HARDWARE EXCEPTION HANDLING (MSVC -EHa) - Part 1


Repository:
  rG LLVM Github Monorepo

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[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

[Zakk Chen via Phabricator via cfe-commits]

khchen added a comment.

In D71387#2762120 , @jrtc27 wrote:

> In D71387#2762115 , @khchen wrote:
>
>> In D71387#1820995 , @efriedma wrote:
>>
>>> Okay.  Please let me know if you want me to review anything.
>>
>> Hi all,
>> We had encoded the target-abi into module now, but I feel it does not make 
>> sense to 
>> support overwrite ABI option and datalayout in TargetMahcine/IR by 
>> target-abi module flag in IR.
>>
>> So I think maybe passing the target-abi option by clang driver can make 
>> anything more simple, the only one limitation is users need to specific 
>> `-mabi` in below cases at the last command.
>>
>>   clang -target riscv64-unknown-elf a.c -flto -march=rv64gc -mabi=lp64f -o 
>> a.o
>>   clang -target riscv64-unknown-elf b.c -flto -march=rv64gc -mabi=lp64f -o 
>> b.o
>>   clang -target riscv64-unknown-elf a.o b.o -flto -march=rv64gc -o foo
>
> We should treat a missing `-mabi=` as an implicit 
> `-mabi=whatever-the-default-is` for consistency with non-LTO. So yes, if the 
> default ABI differs from what you've compiled the .o's with, you should have 
> to provide it. This is needed already _anyway_ for multilib toolchains to 
> determine the right library search path, though there are cases currently 
> when you can get away without providing it, at least with Clang.

Hi @jrtc27, do you mean in clang, we need encode an explicitly -target-abi 
string (compute by RISCVABI::computeTargetABI) rather than an empty string in 
IR module?


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[clang] 976a3e5 - [SelectionDAG] Make fast and linearize visible by clang -pre-RA-sched

[via cfe-commits]

Author: Pan, Tao
Date: 2021-05-17T11:25:15+08:00
New Revision: 976a3e5f61415e784c85b341180eac300cc8b7a5

URL: 
https://github.com/llvm/llvm-project/commit/976a3e5f61415e784c85b341180eac300cc8b7a5
DIFF: 
https://github.com/llvm/llvm-project/commit/976a3e5f61415e784c85b341180eac300cc8b7a5.diff

LOG: [SelectionDAG] Make fast and linearize visible by clang -pre-RA-sched

ScheduleDAGFast.cpp is compiled to object file, but the ScheduleDAGFast
object file isn't linked into clang executable file as no symbol is
referred by outside. Add calling to createXxx of ScheduleDAGFast.cpp,
then the ScheduleDAGFast object file will be linked into clang
executable file. The static RegisterScheduler will register scheduler
fast and linearize at clang boot time.

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D101601

Added: 
clang/test/CodeGen/pre-ra-sched.c

Modified: 
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Removed: 




diff  --git a/clang/test/CodeGen/pre-ra-sched.c 
b/clang/test/CodeGen/pre-ra-sched.c
new file mode 100644
index 0..3bd7594a5db90
--- /dev/null
+++ b/clang/test/CodeGen/pre-ra-sched.c
@@ -0,0 +1,4 @@
+// RUN: %clang %s -mllvm -pre-RA-sched=fast -c -o - | FileCheck %s
+// RUN: %clang %s -mllvm -pre-RA-sched=linearize -c -o - | FileCheck %s
+
+// CHECK-NOT: clang (LLVM option parsing): for the --pre-RA-sched option: 
Cannot find option named

diff  --git a/llvm/include/llvm/CodeGen/TargetLowering.h 
b/llvm/include/llvm/CodeGen/TargetLowering.h
index b3f7843a03501..13079b8f17fc1 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -94,14 +94,16 @@ class Value;
 
 namespace Sched {
 
-  enum Preference {
-None, // No preference
-Source,   // Follow source order.
-RegPressure,  // Scheduling for lowest register pressure.
-Hybrid,   // Scheduling for both latency and register pressure.
-ILP,  // Scheduling for ILP in low register pressure mode.
-VLIW  // Scheduling for VLIW targets.
-  };
+enum Preference {
+  None,// No preference
+  Source,  // Follow source order.
+  RegPressure, // Scheduling for lowest register pressure.
+  Hybrid,  // Scheduling for both latency and register pressure.
+  ILP, // Scheduling for ILP in low register pressure mode.
+  VLIW,// Scheduling for VLIW targets.
+  Fast,// Fast suboptimal list scheduling
+  Linearize// Linearize DAG, no scheduling
+};
 
 } // end namespace Sched
 

diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 6983d6fcb0f7e..3d035e875925f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -270,6 +270,10 @@ namespace llvm {
   return createHybridListDAGScheduler(IS, OptLevel);
 if (TLI->getSchedulingPreference() == Sched::VLIW)
   return createVLIWDAGScheduler(IS, OptLevel);
+if (TLI->getSchedulingPreference() == Sched::Fast)
+  return createFastDAGScheduler(IS, OptLevel);
+if (TLI->getSchedulingPreference() == Sched::Linearize)
+  return createDAGLinearizer(IS, OptLevel);
 assert(TLI->getSchedulingPreference() == Sched::ILP &&
"Unknown sched type!");
 return createILPListDAGScheduler(IS, OptLevel);



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[PATCH] D101601: [SelectionDAG] Make fast and linearize visible by clang -pre-RA-sched

[Pengfei Wang via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG976a3e5f6141: [SelectionDAG] Make fast and linearize visible 
by clang -pre-RA-sched (authored by TaoPan, committed by pengfei).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101601/new/

https://reviews.llvm.org/D101601

Files:
  clang/test/CodeGen/pre-ra-sched.c
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
===
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -270,6 +270,10 @@
   return createHybridListDAGScheduler(IS, OptLevel);
 if (TLI->getSchedulingPreference() == Sched::VLIW)
   return createVLIWDAGScheduler(IS, OptLevel);
+if (TLI->getSchedulingPreference() == Sched::Fast)
+  return createFastDAGScheduler(IS, OptLevel);
+if (TLI->getSchedulingPreference() == Sched::Linearize)
+  return createDAGLinearizer(IS, OptLevel);
 assert(TLI->getSchedulingPreference() == Sched::ILP &&
"Unknown sched type!");
 return createILPListDAGScheduler(IS, OptLevel);
Index: llvm/include/llvm/CodeGen/TargetLowering.h
===
--- llvm/include/llvm/CodeGen/TargetLowering.h
+++ llvm/include/llvm/CodeGen/TargetLowering.h
@@ -94,14 +94,16 @@
 
 namespace Sched {
 
-  enum Preference {
-None, // No preference
-Source,   // Follow source order.
-RegPressure,  // Scheduling for lowest register pressure.
-Hybrid,   // Scheduling for both latency and register pressure.
-ILP,  // Scheduling for ILP in low register pressure mode.
-VLIW  // Scheduling for VLIW targets.
-  };
+enum Preference {
+  None,// No preference
+  Source,  // Follow source order.
+  RegPressure, // Scheduling for lowest register pressure.
+  Hybrid,  // Scheduling for both latency and register pressure.
+  ILP, // Scheduling for ILP in low register pressure mode.
+  VLIW,// Scheduling for VLIW targets.
+  Fast,// Fast suboptimal list scheduling
+  Linearize// Linearize DAG, no scheduling
+};
 
 } // end namespace Sched
 
Index: clang/test/CodeGen/pre-ra-sched.c
===
--- /dev/null
+++ clang/test/CodeGen/pre-ra-sched.c
@@ -0,0 +1,4 @@
+// RUN: %clang %s -mllvm -pre-RA-sched=fast -c -o - | FileCheck %s
+// RUN: %clang %s -mllvm -pre-RA-sched=linearize -c -o - | FileCheck %s
+
+// CHECK-NOT: clang (LLVM option parsing): for the --pre-RA-sched option: 
Cannot find option named


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
===
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -270,6 +270,10 @@
   return createHybridListDAGScheduler(IS, OptLevel);
 if (TLI->getSchedulingPreference() == Sched::VLIW)
   return createVLIWDAGScheduler(IS, OptLevel);
+if (TLI->getSchedulingPreference() == Sched::Fast)
+  return createFastDAGScheduler(IS, OptLevel);
+if (TLI->getSchedulingPreference() == Sched::Linearize)
+  return createDAGLinearizer(IS, OptLevel);
 assert(TLI->getSchedulingPreference() == Sched::ILP &&
"Unknown sched type!");
 return createILPListDAGScheduler(IS, OptLevel);
Index: llvm/include/llvm/CodeGen/TargetLowering.h
===
--- llvm/include/llvm/CodeGen/TargetLowering.h
+++ llvm/include/llvm/CodeGen/TargetLowering.h
@@ -94,14 +94,16 @@
 
 namespace Sched {
 
-  enum Preference {
-None, // No preference
-Source,   // Follow source order.
-RegPressure,  // Scheduling for lowest register pressure.
-Hybrid,   // Scheduling for both latency and register pressure.
-ILP,  // Scheduling for ILP in low register pressure mode.
-VLIW  // Scheduling for VLIW targets.
-  };
+enum Preference {
+  None,// No preference
+  Source,  // Follow source order.
+  RegPressure, // Scheduling for lowest register pressure.
+  Hybrid,  // Scheduling for both latency and register pressure.
+  ILP, // Scheduling for ILP in low register pressure mode.
+  VLIW,// Scheduling for VLIW targets.
+  Fast,// Fast suboptimal list scheduling
+  Linearize// Linearize DAG, no scheduling
+};
 
 } // end namespace Sched
 
Index: clang/test/CodeGen/pre-ra-sched.c
===
--- /dev/null
+++ clang/test/CodeGen/pre-ra-sched.c
@@ -0,0 +1,4 @@
+// RUN: %clang %s -mllvm -pre-RA-sched=fast -c -o - | FileCheck %s
+// RUN: %cla