[Bug ld/13991] powerpc-rtems ld failure [regression]
http://sourceware.org/bugzilla/show_bug.cgi?id=13991
Sebastian Huber changed:
What|Removed |Added
CC||sebastian.huber@embedded-br
||ains.de
--- Comment #4 from Sebastian Huber
2012-04-23 12:16:35 UTC ---
If I run the following script
rm -f log.txt
for i in `nm -g hello.exe | awk '/ T / {print $3}'` ; do
sed s%__rtems_start%$i% < ppcboot.lds > ppcboot.lds.tmp
if powerpc-rtems4.11-ld -o hello.ralf bootloader.o --just-symbols=hello.exe
-b binary rtems.gz -T ppcboot.lds.tmp -Map hello.map ; then
echo good $i >> log.txt
else
echo bad $i >> log.txt
fi
done
with the attached test case, then some symbols lead to the error and some not.
It seems to be pretty arbitrary.
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[Bug binutils/16690] New: BFD: b-qoriq_core_1/app.elf: section `.data' can't be allocated in segment 2
https://sourceware.org/bugzilla/show_bug.cgi?id=16690 Bug ID: 16690 Summary: BFD: b-qoriq_core_1/app.elf: section `.data' can't be allocated in segment 2 Product: binutils Version: 2.25 (HEAD) Status: NEW Severity: normal Priority: P2 Component: binutils Assignee: unassigned at sourceware dot org Reporter: sebastian.hu...@embedded-brains.de Created attachment 7463 --> https://sourceware.org/bugzilla/attachment.cgi?id=7463&action=edit Evil ELF file. I have an ELF file that looks ok to me, but I cannot strip it: powerpc-rtems4.11-objcopy -S app.exe app.elf BFD: app.elf: section `.data' can't be allocated in segment 2 LOAD: .data .sdata .sbss .bss .rwextra .work BFD: app.elf: section `.sdata' can't be allocated in segment 2 LOAD: .data .sdata .sbss .bss .rwextra .work BFD: app.elf: section `.sbss' can't be allocated in segment 2 LOAD: .data .sdata .sbss .bss .rwextra .work BFD: app.elf: section `.bss' can't be allocated in segment 2 LOAD: .data .sdata .sbss .bss .rwextra .work BFD: app.elf: section `.rwextra' can't be allocated in segment 2 LOAD: .data .sdata .sbss .bss .rwextra .work BFD: app.elf: section `.work' can't be allocated in segment 2 LOAD: .data .sdata .sbss .bss .rwextra .work readelf -l app.exe Elf file type is EXEC (Executable file) Entry point 0x400 There are 3 program headers, starting at offset 52 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0xa0 0x0400 0x0400 0x753dc 0x100 RWE 0x20 LOAD 0x075480 0x0500 0x0500 0x0cdcc 0x100 RW 0x8 LOAD 0x082260 0x0600 0x0600 0x01fbc 0x200 RW 0x20 Section to Segment mapping: Segment Sections... 00 .start .text .init .fini .robarrier 01 .rodata .eh_frame .ctors .dtors .jcr .got2 .rtemsroset .rwbarrier 02 .data .sdata .sbss .bss .rwextra .work readelf -l app.elf Elf file type is EXEC (Executable file) Entry point 0x400 There are 3 program headers, starting at offset 52 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0xa0 0x0400 0x0400 0x753dc 0x100 RWE 0x20 LOAD 0x075480 0x0500 0x0500 0x0cdcc 0x100 RW 0x8 LOAD 0x08225c 0x07fff51c 0x0600 0x01fbc 0x200 RW 0x20 Section to Segment mapping: Segment Sections... 00 .start .text .init .fini .robarrier 01 .rodata .eh_frame .ctors .dtors .jcr .got2 .rtemsroset .rwbarrier 02 -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug binutils/16690] BFD: app.elf: section `.data' can't be allocated in segment 2
https://sourceware.org/bugzilla/show_bug.cgi?id=16690 Sebastian Huber changed: What|Removed |Added Summary|BFD:|BFD: app.elf: section |b-qoriq_core_1/app.elf: |`.data' can't be allocated |section `.data' can't be|in segment 2 |allocated in segment 2 | -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/19554] New: PowerPC/e6500: esync E simplified mnemonic not supported
https://sourceware.org/bugzilla/show_bug.cgi?id=19554 Bug ID: 19554 Summary: PowerPC/e6500: esync E simplified mnemonic not supported Product: binutils Version: 2.27 (HEAD) Status: NEW Severity: normal Priority: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: sebastian.hu...@embedded-brains.de Target Milestone: --- The simplified mnemonic for elemental sync, esync E, is not supported. See e6500 Core Reference Manual, Table 3-62. Memory synchronization Instructions. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/19554] PowerPC/e6500: esync E simplified mnemonic not supported
https://sourceware.org/bugzilla/show_bug.cgi?id=19554 Sebastian Huber changed: What|Removed |Added Target||powerpc CC||catalin.udma at freescale dot com -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/20196] New: Opcode regressions for e6500
https://sourceware.org/bugzilla/show_bug.cgi?id=20196 Bug ID: 20196 Summary: Opcode regressions for e6500 Product: binutils Version: 2.26 Status: UNCONFIRMED Severity: normal Priority: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: sebastian.hu...@embedded-brains.de Target Milestone: --- The following commit https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=4fff86c517abb5ba454befe0ec0f284f720dde00 broke the e6500 support. cat test.s lbarx 3, 0, 2 stbcx. 0, 0, 2 sync0, 0x8 sync0, 0x1 powerpc-rtems4.12-as -v -me6500 -memb -a32 -o test.o test.s GNU assembler version 2.26.51 (powerpc-rtems4.12) using BFD version (GNU Binutils) 2.26.51.20160530 test.s: Assembler messages: test.s:1: Error: unrecognized opcode: `lbarx' test.s:2: Error: unrecognized opcode: `stbcx.' test.s:3: Error: incompatible L operand value test.s:4: Error: incompatible L operand value It worked with Binutils 2.25. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/20196] Opcode regressions for e6500
https://sourceware.org/bugzilla/show_bug.cgi?id=20196 Sebastian Huber changed: What|Removed |Added Target||powerpc CC||bergner at vnet dot ibm.com -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/20196] Opcode regressions for e6500
https://sourceware.org/bugzilla/show_bug.cgi?id=20196 Sebastian Huber changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|--- |FIXED --- Comment #6 from Sebastian Huber --- Thanks a lot for this really quick fix. In addition, thanks for adding the consistency checks to the sync L, E in https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=7b9341139a693eac8d316275004b2d752b1f0cb8 Thus, error 3 and 4 are actually errors on our side thanks to the vague e6500 reference manual. The Power ISA 2.07 document clarified this. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/19554] PowerPC/e6500: esync E simplified mnemonic not supported
https://sourceware.org/bugzilla/show_bug.cgi?id=19554 Sebastian Huber changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |WONTFIX --- Comment #1 from Sebastian Huber --- The esync E simplified mnemonic is not present in the Power ISA 2.07, thus it seems to be e6500 specific. Its probably not worth to add it. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug ld/23244] New: RISC-V 64 relocation truncated to fit in case of undefined weak references
https://sourceware.org/bugzilla/show_bug.cgi?id=23244
Bug ID: 23244
Summary: RISC-V 64 relocation truncated to fit in case of
undefined weak references
Product: binutils
Version: unspecified
Status: UNCONFIRMED
Severity: normal
Priority: P2
Component: ld
Assignee: unassigned at sourceware dot org
Reporter: sebastian.hu...@embedded-brains.de
Target Milestone: ---
The following test program
void f(void) __attribute__((__weak__));
void _start(void)
{
if (f != 0) {
f();
f();
}
}
leads to
riscv64-elf-gcc weakref.c -T weakref.ld -mcmodel=medany
ld: weakref.o: in function `.L0 ':
weakref.c:(.text+0x12): relocation truncated to fit: R_RISCV_CALL against
undefined symbol `f'
collect2: error: ld returned 1 exit status
using this linker script
ENTRY(_start)
SECTIONS {
.text 0x9000 : {
*(.text*)
}
}
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[Bug ld/23244] RISC-V 64 relocation truncated to fit in case of undefined weak references
https://sourceware.org/bugzilla/show_bug.cgi?id=23244
--- Comment #2 from Sebastian Huber ---
Thanks for your analysis.
Calling a weakly undefined function is undefined behaviour. Would it be
possible to replace the call to zero with a call to the current PC (infinite
loop) or a nop?
On the ARM architecture it looks like a nop is created:
.type _start, %function
_start:
@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
push{r3, lr}
movwr3, #:lower16:f
movtr3, #:upper16:f
cbz r3, .L1
bl f
bl f
.L1:
pop {r3, pc}
.size _start, .-_start
.weak f
Final executable code (Thumb-2):
Disassembly of section .text:
9000 <_start>:
9000: b508push{r3, lr}
9002: f240 0300 movwr3, #0
9006: f2c0 0300 movtr3, #0
900a: b11bcbz r3, 9014 <_start+0x14>
900c: f3af 8000 nop.w
9010: f3af 8000 nop.w
9014: bd08pop {r3, pc}
9016: bf00nop
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[Bug gas/23305] New: RISC-V illegal operands with lla and .set
https://sourceware.org/bugzilla/show_bug.cgi?id=23305
Bug ID: 23305
Summary: RISC-V illegal operands with lla and .set
Product: binutils
Version: unspecified
Status: UNCONFIRMED
Severity: normal
Priority: P2
Component: gas
Assignee: unassigned at sourceware dot org
Reporter: sebastian.hu...@embedded-brains.de
Target Milestone: ---
The following test assembler file:
.option nopic
.text
.globl sym
.set sym, 0xabc
.align 1
.globl f
.type f, @function
f:
lla a0,sym
ret
.size f, .-f
Leads to:
riscv32-rtems5-as -march=rv64gc -mabi=lp64 lla.s
lla.s: Assembler messages:
lla.s:11: Error: illegal operands `lla a0,sym'
This code can be generated by GCC with:
extern char sym[];
__asm__(
"\t.globl sym\n"
"\t.set sym, 0xabc\n"
);
long f(void)
{
return (long)sym;
}
riscv32-rtems5-gcc -S -o - test.c -march=rv64gc -mabi=lp64 -mcmodel=medany -O2
.file "test.c"
.option nopic
.text
#APP
.globl sym
.set sym, 0xabc
#NO_APP
.align 1
.globl f
.type f, @function
f:
lla a0,sym
ret
.size f, .-f
.ident "GCC: (GNU) 9.0.0 20180605
Using -mcmodel=medlow works since a different load sequence is generated:
lui a0,%hi(sym)
addia0,a0,%lo(sym)
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[Bug gas/23305] RISC-V illegal operands with lla and .set
https://sourceware.org/bugzilla/show_bug.cgi?id=23305 Sebastian Huber changed: What|Removed |Added CC||wilson at gcc dot gnu.org -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/23305] RISC-V illegal operands with lla and .set
https://sourceware.org/bugzilla/show_bug.cgi?id=23305
--- Comment #1 from Sebastian Huber ---
One problem is that:
opcodes/riscv-opc.c:{"lla", "I", "d,A", 0,(int) M_LLA,
match_never, INSN_MACRO },
Running the test case in GDB yields:
1487 for (args = insn->args;; ++args)
(gdb)
2120}
(gdb)
1489 s += strspn (s, " \t");
(gdb)
1490 switch (*args)
(gdb)
1929 my_getExpression (imm_expr, s);
(gdb)
1930 normalize_constant_expr (imm_expr);
(gdb)
1932 if (imm_expr->X_op != O_symbol)
(gdb)
2121 s = argsStart;
(gdb)
2122 error = _("illegal operands");
(gdb) p imm_expr->X_op
$1 = O_constant
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[Bug gas/23305] RISC-V illegal operands with lla and .set
https://sourceware.org/bugzilla/show_bug.cgi?id=23305 --- Comment #3 from Sebastian Huber --- Created attachment 11083 --> https://sourceware.org/bugzilla/attachment.cgi?id=11083&action=edit Potential fix. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/23305] RISC-V illegal operands with lla and .set
https://sourceware.org/bugzilla/show_bug.cgi?id=23305 --- Comment #4 from Sebastian Huber --- The C code test case works at least on arm, bfin, epiphany, lm32, m32c, m68k, mips, moxie, nios2, or1k, powerpc, sh, sparc64, sparc, v850, and x86_64. The use case for this is that high level configuration code can pass some information to low level initialization code. During the execution of the low level initialization code the read-only or read-write global data may be not available, e.g. due to some magic address mapping mode of a processor. Addresses may be used as configuration constants in this scenario, e.g. to get the location and size of the initialization stack. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/23305] RISC-V illegal operands with lla and .set
https://sourceware.org/bugzilla/show_bug.cgi?id=23305 Sebastian Huber changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #7 from Sebastian Huber --- Fixed from my point of view. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/23451] New: RISC-V gas aborts with "Error: unknown default architecture `'" in GCC configure tests
https://sourceware.org/bugzilla/show_bug.cgi?id=23451 Bug ID: 23451 Summary: RISC-V gas aborts with "Error: unknown default architecture `'" in GCC configure tests Product: binutils Version: 2.31 Status: UNCONFIRMED Severity: normal Priority: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: sebastian.hu...@embedded-brains.de Target Milestone: --- I tried to build a riscv-rtems5 GCC using Binutils 2.31.1 and a recent GCC 9. There are several configure tests in GCC which test gas features. They fail now with a "Error: unknown default architecture `'" error message (about 30 tests), e.g. configure:24456: checking assembler for thread-local storage support configure:24469: /build/rtems/5/riscv-rtems5/bin/as --fatal-warnings -o conftest.o conftest.s >&5 Assembler messages: Error: unknown default architecture `' configure:24472: $? = 1 configure: failed program was .section .tdata,"awT",@progbits x: .word 2 .text la.tls.gd a0,x call __tls_get_addr -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/23451] RISC-V gas aborts with "Error: unknown default architecture `'" in GCC configure tests
https://sourceware.org/bugzilla/show_bug.cgi?id=23451 Sebastian Huber changed: What|Removed |Added Target||riscv-rtems5 CC||wilson at gcc dot gnu.org -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/23451] RISC-V gas aborts with "Error: unknown default architecture `'" in GCC configure tests
https://sourceware.org/bugzilla/show_bug.cgi?id=23451 --- Comment #2 from Sebastian Huber --- I am not sure at which level this should be fixed now. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/23451] RISC-V gas aborts with "Error: unknown default architecture `'" in GCC configure tests
https://sourceware.org/bugzilla/show_bug.cgi?id=23451 --- Comment #5 from Sebastian Huber --- Thanks, for the fix. The tools did build fine with this error. I only noticed the problem due to some TLS test run-time failures since emutls was picked up by GCC. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug gas/27145] New: [AArch64] opcodes/aarch64-opc.c: missing system registers
https://sourceware.org/bugzilla/show_bug.cgi?id=27145 Bug ID: 27145 Summary: [AArch64] opcodes/aarch64-opc.c: missing system registers Product: binutils Version: 2.36 (HEAD) Status: UNCONFIRMED Severity: normal Priority: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: sebastian.hu...@embedded-brains.de Target Milestone: --- The following system registers are defined in "Arm Architecture Reference Manual, Armv8, for Armv8-A architecture profile" issue F.c in chapter D13 "AArch64 System Register Descriptions" and not supported by "opcodes/aarch64-opc.c": AMCFGR_EL0 AMCG1IDR_EL0 AMCGCR_EL0 AMCNTENCLR0_EL0 AMCNTENCLR1_EL0 AMCNTENSET0_EL0 AMCNTENSET1_EL0 AMCR_EL0 AMEVCNTR0_N_EL0 AMEVCNTR1_N_EL0 AMEVCNTVOFF0_N_EL2 AMEVCNTVOFF1_N_EL2 AMEVTYPER0_N_EL0 AMEVTYPER1_N_EL0 AMUSERENR_EL0 CCSIDR2_EL1 CNTPCTSS_EL0 CNTPOFF_EL2 CNTVCTSS_EL0 DBGBCR_N_EL1 DBGBVR_N_EL1 DBGWCR_N_EL1 DBGWVR_N_EL1 HAFGRTR_EL2 HDFGRTR_EL2 HDFGWTR_EL2 HFGITR_EL2 HFGRTR_EL2 HFGWTR_EL2 ID_DFR1_EL1 ID_ISAR6_EL1 ID_MMFR5_EL1 LORC_EL1 LOREA_EL1 LORID_EL1 LORN_EL1 LORSA_EL1 PMEVCNTR_N_EL0 PMEVTYPER_N_EL0 PMMIR_EL1 TRFCR_EL1 TRFCR_EL2 -- You are receiving this mail because: You are on the CC list for the bug.
