[Bug binutils/19921] New: enable specification of data width when writing verilog hex format

2016-04-07 Thread jamey.hicks at gmail dot com
https://sourceware.org/bugzilla/show_bug.cgi?id=19921

Bug ID: 19921
   Summary: enable specification of data width when writing
verilog hex format
   Product: binutils
   Version: 2.27 (HEAD)
Status: NEW
  Severity: enhancement
  Priority: P2
 Component: binutils
  Assignee: unassigned at sourceware dot org
  Reporter: jamey.hicks at gmail dot com
  Target Milestone: ---

Verilog $readmemh is rather limited and reads one array value per white-space
separated number. In order to read into a 32-bit or 64-bit array, the data must
be formatted accordingly.

I propose to modify the verilog target in order to add data width
specification. I see several ways to go about this:

 * define verilog16, verilog32, and verilog64 targets, so that the target
specifies the data width
 * default to the data width of the architecture
 * add options to object copy similar to srec-len.

The first option is the most flexible, but I'm looking for the option that
binutils maintainers would be willing to accept.

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[Bug binutils/19921] enable specification of data width when writing verilog hex format

2016-04-08 Thread jamey.hicks at gmail dot com
https://sourceware.org/bugzilla/show_bug.cgi?id=19921

--- Comment #2 from Jamey Hicks  ---
After talking about it with others who use the verilog output, a new option
seems best because it is the most flexible. The data width of a ROM does not
necessarily match the data width of the processor.

I think the changes will be very small in this case. A new option in objcopy
and a change to verilog.c to use the specified data width.

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[Bug binutils/19921] enable specification of data width when writing verilog hex format

2016-04-08 Thread jamey.hicks at gmail dot com
https://sourceware.org/bugzilla/show_bug.cgi?id=19921

--- Comment #3 from Jamey Hicks  ---
Created attachment 9170
  --> https://sourceware.org/bugzilla/attachment.cgi?id=9170&action=edit
patch adding --verilog-data-width option to objcopy

This patch adds --verilog-data-width option to objcopy. It includes several
test cases.

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[Bug binutils/19921] enable specification of data width when writing verilog hex format

2016-04-11 Thread jamey.hicks at gmail dot com
https://sourceware.org/bugzilla/show_bug.cgi?id=19921

--- Comment #6 from Jamey Hicks  ---
Created attachment 9179
  --> https://sourceware.org/bugzilla/attachment.cgi?id=9179&action=edit
revised patch

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[Bug binutils/19921] enable specification of data width when writing verilog hex format

2019-05-14 Thread jamey.hicks at gmail dot com
https://sourceware.org/bugzilla/show_bug.cgi?id=19921

--- Comment #12 from Jamey Hicks  ---
Thank you, Nick!


On Tue, May 14, 2019 at 5:51 AM nickc at redhat dot com <
sourceware-bugzi...@sourceware.org> wrote:

> https://sourceware.org/bugzilla/show_bug.cgi?id=19921
>
> Nick Clifton  changed:
>
>What|Removed |Added
>
> 
>  Status|NEW |RESOLVED
>  Resolution|--- |FIXED
>
> --- Comment #11 from Nick Clifton  ---
> (In reply to Donato Kava from comment #9)
> > Adding a comment here to ask if someone could actually work on this bug.
>
> Well nobody else seems to want to fix the testsuite problems, so I have
> gone ahead and done so myself.  A little bit of code tidying as well,
> and the patch is now in.
>
> Cheers
>   Nick
>
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> You are receiving this mail because:
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