[Bug binutils/25403] [AArch64, ARMv8.4] objdump doesn't disassemble cfinv correctly
https://sourceware.org/bugzilla/show_bug.cgi?id=25403 --- Comment #1 from cvs-commit at gcc dot gnu.org --- The master branch has been updated by Tamar Christina : https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=7568c93bf95a518797dfb2987b04911164c14a36 commit 7568c93bf95a518797dfb2987b04911164c14a36 Author: Tamar Christina Date: Mon Jan 27 10:40:02 2020 + AArch64: Fix cfinv disassembly issues This fixes the preferred disassembly for cfinv. The Armv8.4-a instruction overlaps with the possible encoding space for msr. This because msr allows you to use unallocated encoding space using the general sA_B_cC_cD_E form. However when an encoding does become allocated then we need to ensure that it's used as the preferred disassembly. The problem with cfinv is that its mask has all bits sets because it has no arguments. This causes issues for the Alias resolver in gas as it uses the mask to build alias graph. In this case it can't do it since it thinks almost everything would alias with cfinv. So instead we can only fix this by moving cfinv before msr. gas/ChangeLog: PR 25403 * testsuite/gas/aarch64/armv8_4-a.d: Add cfinv. * testsuite/gas/aarch64/armv8_4-a.s: Likewise. opcodes/ChangeLog: PR 25403 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. * aarch64-asm-2.c: Regenerate * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gas/25465] spam
https://sourceware.org/bugzilla/show_bug.cgi?id=25465 Alan Modra changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED URL|https://www.nevastech.com/s | |olutions/dynamics-365-busin | |ess-central-pricing-licensi | |ng | Resolution|--- |INVALID Summary|Dynamics 365 Business |spam |Central Pricing & Licensing | --- Comment #1 from Alan Modra --- spam -- You are receiving this mail because: You are on the CC list for the bug.
[Bug binutils/25403] [AArch64, ARMv8.4] objdump doesn't disassemble cfinv correctly
https://sourceware.org/bugzilla/show_bug.cgi?id=25403 --- Comment #2 from cvs-commit at gcc dot gnu.org --- The binutils-2_34-branch branch has been updated by Tamar Christina : https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=2cd7b00eb1337e427fa6149779157d8638eb57d9 commit 2cd7b00eb1337e427fa6149779157d8638eb57d9 Author: Tamar Christina Date: Mon Jan 27 10:40:02 2020 + AArch64: Fix cfinv disassembly issues This fixes the preferred disassembly for cfinv. The Armv8.4-a instruction overlaps with the possible encoding space for msr. This because msr allows you to use unallocated encoding space using the general sA_B_cC_cD_E form. However when an encoding does become allocated then we need to ensure that it's used as the preferred disassembly. The problem with cfinv is that its mask has all bits sets because it has no arguments. This causes issues for the Alias resolver in gas as it uses the mask to build alias graph. In this case it can't do it since it thinks almost everything would alias with cfinv. So instead we can only fix this by moving cfinv before msr. gas/ChangeLog: PR 25403 * testsuite/gas/aarch64/armv8_4-a.d: Add cfinv. * testsuite/gas/aarch64/armv8_4-a.s: Likewise. opcodes/ChangeLog: PR 25403 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. * aarch64-asm-2.c: Regenerate * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. (cherry picked from commit 7568c93bf95a518797dfb2987b04911164c14a36) -- You are receiving this mail because: You are on the CC list for the bug.
[Bug binutils/25403] [AArch64, ARMv8.4] objdump doesn't disassemble cfinv correctly
https://sourceware.org/bugzilla/show_bug.cgi?id=25403 --- Comment #3 from cvs-commit at gcc dot gnu.org --- The binutils-2_33-branch branch has been updated by Tamar Christina : https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=2a8719fecde2f27bb91440317c3df166be1c511f commit 2a8719fecde2f27bb91440317c3df166be1c511f Author: Tamar Christina Date: Mon Jan 27 10:40:02 2020 + AArch64: Fix cfinv disassembly issues This fixes the preferred disassembly for cfinv. The Armv8.4-a instruction overlaps with the possible encoding space for msr. This because msr allows you to use unallocated encoding space using the general sA_B_cC_cD_E form. However when an encoding does become allocated then we need to ensure that it's used as the preferred disassembly. The problem with cfinv is that its mask has all bits sets because it has no arguments. This causes issues for the Alias resolver in gas as it uses the mask to build alias graph. In this case it can't do it since it thinks almost everything would alias with cfinv. So instead we can only fix this by moving cfinv before msr. gas/ChangeLog: PR 25403 * testsuite/gas/aarch64/armv8_4-a.d: Add cfinv. * testsuite/gas/aarch64/armv8_4-a.s: Likewise. opcodes/ChangeLog: PR 25403 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. * aarch64-asm-2.c: Regenerate * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. (cherry picked from commit 7568c93bf95a518797dfb2987b04911164c14a36) -- You are receiving this mail because: You are on the CC list for the bug.
[Bug binutils/25403] [AArch64, ARMv8.4] objdump doesn't disassemble cfinv correctly
https://sourceware.org/bugzilla/show_bug.cgi?id=25403 Tamar Christina changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC||tnfchris at sourceware dot org Version|2.34|2.33 Resolution|--- |FIXED Assignee|unassigned at sourceware dot org |tnfchris at sourceware dot org Target Milestone|--- |2.33 --- Comment #4 from Tamar Christina --- Fixed in master and backported to 2.33 and 2.34 -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gas/25468] New: Hero bikes
https://sourceware.org/bugzilla/show_bug.cgi?id=25468 Bug ID: 25468 Summary: Hero bikes Product: binutils Version: 2.31 Status: UNCONFIRMED Severity: normal Priority: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: jayaseelamurugan at hotmail dot com Target Milestone: --- Find here Hero Bike dealers, retailers & distributors in India. Get latest details on Hero Bike prices, models & wholesale prices and companies selling Hero Bike. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gas/25468] Hero bikes
https://sourceware.org/bugzilla/show_bug.cgi?id=25468 Jayaseela Murugan changed: What|Removed |Added URL||https://www.autonews360.com ||/new-bikes/launch/hero/ -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gas/25469] New: [Z80][PATCH] Add support for GameBoy Z80 CPU
https://sourceware.org/bugzilla/show_bug.cgi?id=25469 Bug ID: 25469 Summary: [Z80][PATCH] Add support for GameBoy Z80 CPU Product: binutils Version: unspecified Status: UNCONFIRMED Severity: enhancement Priority: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: sergey.belyashov at gmail dot com Target Milestone: --- Created attachment 12232 --> https://sourceware.org/bugzilla/attachment.cgi?id=12232&action=edit Add support GBZ80 This patch completes support for GameBoy Z80 CPU. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gas/25469] [Z80][PATCH] Add support for GameBoy Z80 CPU
https://sourceware.org/bugzilla/show_bug.cgi?id=25469 Sergey Belyashov changed: What|Removed |Added Target||z80-unknown-* CC||nickc at redhat dot com -- You are receiving this mail because: You are on the CC list for the bug.
[Bug binutils/25445] movsxd without REX_W prefix incorrectly disassembled
https://sourceware.org/bugzilla/show_bug.cgi?id=25445 --- Comment #8 from cvs-commit at gcc dot gnu.org --- The master branch has been updated by H.J. Lu : https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=bc31405ebb2c4297ae815ab59f59165014347528 commit bc31405ebb2c4297ae815ab59f59165014347528 Author: H.J. Lu Date: Mon Jan 27 04:38:10 2020 -0800 x86-64: Properly encode and decode movsxd movsxd is a 64-bit only instruction. It supports both 16-bit and 32-bit destination registers. Its AT&T mnemonic is movslq which only supports 64-bit destination register. There is also a discrepancy between AMD64 and Intel64 on movsxd with 16-bit destination register. AMD64 supports 32-bit source operand and Intel64 supports 16-bit source operand. This patch updates movsxd encoding and decoding to alow 16-bit and 32-bit destination registers. It also handles movsxd with 16-bit destination register for AMD64 and Intel 64. gas/ PR binutils/25445 * config/tc-i386.c (check_long_reg): Also convert to QWORD for movsxd. * doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA differences. Document movslq and movsxd. * testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests. * testsuite/gas/i386/x86-64-movsxd-intel.d: New file. * testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise. * testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise. * testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise. * testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise. * testsuite/gas/i386/x86-64-movsxd.d: Likewise. * testsuite/gas/i386/x86-64-movsxd.s: Likewise. opcodes/ PR binutils/25445 * i386-dis.c (MOVSXD_Fixup): New function. (movsxd_mode): New enum. (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd. (intel_operand_size): Handle movsxd_mode. (OP_E_register): Likewise. (OP_G): Likewise. * i386-opc.tbl: Remove Rex64 and allow 32-bit destination register on movsxd. Add movsxd with 16-bit destination register for AMD64 and Intel64 ISAs. * i386-tbl.h: Regenerated. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug binutils/25445] movsxd without REX_W prefix incorrectly disassembled
https://sourceware.org/bugzilla/show_bug.cgi?id=25445 H.J. Lu changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED Target Milestone|--- |2.35 --- Comment #9 from H.J. Lu --- Fixed for 2.35. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gold/25426] [gold] TLSDESC relaxation doesn't work for x32
https://sourceware.org/bugzilla/show_bug.cgi?id=25426 H.J. Lu changed: What|Removed |Added URL|TLSDESC relaxation doesn't |https://sourceware.org/ml/b |work for x32|inutils/2020-01/msg00291.ht ||ml Target Milestone|--- |2.35 -- You are receiving this mail because: You are on the CC list for the bug.
[Bug ld/25458] --gc-sections removes _environ symbol since version 2.21
https://sourceware.org/bugzilla/show_bug.cgi?id=25458 H.J. Lu changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #6 from H.J. Lu --- Fixed for 2.35. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gas/25472] New: [Arm] +mve does not enable DSP instructions
https://sourceware.org/bugzilla/show_bug.cgi?id=25472 Bug ID: 25472 Summary: [Arm] +mve does not enable DSP instructions Product: binutils Version: 2.33 Status: NEW Severity: normal Priority: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: avieira at gcc dot gnu.org Target Milestone: --- MVE architecturally demands the implementation of the DSP extensions, so +mve should also enable DSP instructions like uadd8 r0, r1, r2. -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gas/25472] [Arm] +mve does not enable DSP instructions
https://sourceware.org/bugzilla/show_bug.cgi?id=25472 Andre Vieira changed: What|Removed |Added Assignee|unassigned at sourceware dot org |avieira at gcc dot gnu.org -- You are receiving this mail because: You are on the CC list for the bug.
Re: ld: Neither "FILL(x);" nor "{ }>Memory = x" allow symbols
On Fri, Jan 24, 2020 at 03:34:45PM +1100, john.adri...@bigpond.com wrote:
[on trying to use a symbol in a fill expression]
> arm-none-eabi/bin/ld.exe: bfd_link_hash_lookup failed: no error (It's the
> "no error" part that I like the most!)
Yes, that is silly. I'm going to commit the following to fix that.
* ldexp.c (fold_name): Don't print bfd_link_hash_lookup failed
in first phase.
diff --git a/ld/ldexp.c b/ld/ldexp.c
index 1fda65d714..6d1457b929 100644
--- a/ld/ldexp.c
+++ b/ld/ldexp.c
@@ -730,7 +730,10 @@ fold_name (etree_type *tree)
tree->name.name,
TRUE, FALSE, TRUE);
if (!h)
- einfo (_("%F%P: bfd_link_hash_lookup failed: %E\n"));
+ {
+ if (expld.phase != lang_first_phase_enum)
+ einfo (_("%F%P: bfd_link_hash_lookup failed: %E\n"));
+ }
else if (h->type == bfd_link_hash_defined
|| h->type == bfd_link_hash_defweak)
{
> It seems like the Fill algorithm doesn't like to use symbols.
Right. The fill expression is evaluated when parsing the script for
the first time, before the symbol table is even created.
--
Alan Modra
Australia Development Lab, IBM
[Bug gas/25468] spam
https://sourceware.org/bugzilla/show_bug.cgi?id=25468 Alan Modra changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED URL|https://www.autonews360.com | |/new-bikes/launch/hero/ | Resolution|--- |INVALID Summary|Hero bikes |spam --- Comment #1 from Alan Modra --- spam -- You are receiving this mail because: You are on the CC list for the bug.
[Bug binutils/25464] spam
https://sourceware.org/bugzilla/show_bug.cgi?id=25464 Alan Modra changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED URL|https://www.nevastech.com/s | |olutions/microsoft-dynamics | |-erp/microsoft-dynamics-gp/ | Resolution|--- |INVALID Summary|Dynamics GP |spam --- Comment #1 from Alan Modra --- spam -- You are receiving this mail because: You are on the CC list for the bug.
[Bug gold/25473] New: [gold] Gold doesn't handle GDesc -> LE transition correctly
https://sourceware.org/bugzilla/show_bug.cgi?id=25473
Bug ID: 25473
Summary: [gold] Gold doesn't handle GDesc -> LE transition
correctly
Product: binutils
Version: 2.35 (HEAD)
Status: NEW
Severity: normal
Priority: P2
Component: gold
Assignee: ccoutant at gmail dot com
Reporter: hjl.tools at gmail dot com
CC: ian at airs dot com
Target Milestone: ---
Target: x86-64
[hjl@gnu-cfl-2 gcc]$ cat x.s
.text
.p2align 4
.globl test
.type test, @function
test:
.cfi_startproc
subq$8, %rsp
.cfi_def_cfa_offset 16
leaqfoo@TLSDESC(%rip), %r9
movq%r9, %rax
call*foo@TLSCALL(%rax)
addq%fs:0, %rax
addq$8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.size test, .-test
.section.tdata,"awT",@progbits
.align 4
.type foo, @object
.size foo, 4
foo:
.long 30
.section.note.GNU-stack,"",@progbits
[hjl@gnu-cfl-2 gcc]$ cat main.c
extern int *test (void);
int
main ()
{
return *test ();
}
[hjl@gnu-cfl-2 gcc]$ gcc -c main.c x.s
[hjl@gnu-cfl-2 gcc]$ objdump -dwr x.o
x.o: file format elf64-x86-64
Disassembly of section .text:
:
0: 48 83 ec 08 sub$0x8,%rsp
4: 4c 8d 0d 00 00 00 00lea0x0(%rip),%r9# b
7: R_X86_64_GOTPC32_TLSDESC foo-0x4
b: 4c 89 c8mov%r9,%rax
e: ff 10 callq *(%rax) e: R_X86_64_TLSDESC_CALL
foo
10: 64 48 03 04 25 00 00 00 00 add%fs:0x0,%rax
19: 48 83 c4 08 add$0x8,%rsp
1d: c3 retq
[hjl@gnu-cfl-2 gcc]$ gcc main.o x.o
[hjl@gnu-cfl-2 gcc]$ objdump -dw --disassemble=test a.out
a.out: file format elf64-x86-64
Disassembly of section .init:
Disassembly of section .text:
00401120 :
401120: 48 83 ec 08 sub$0x8,%rsp
401124: 49 c7 c1 fc ff ff ffmov$0xfffc,%r9
40112b: 4c 89 c8mov%r9,%rax
40112e: 66 90 xchg %ax,%ax
401130: 64 48 03 04 25 00 00 00 00 add%fs:0x0,%rax
401139: 48 83 c4 08 add$0x8,%rsp
40113d: c3 retq
Disassembly of section .fini:
[hjl@gnu-cfl-2 gcc]$ gcc main.o x.o -fuse-ld=gold
x.o:function test: error: TLS relocation against invalid instruction
collect2: error: ld returned 1 exit status
[hjl@gnu-cfl-2 gcc]$
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