[Bug gas/11030] New: Missing opcode for assembly instruction 'stldsr' in isa aplus of m68k assembler

2009-11-29 Thread massimo dot ruoroch at polito dot it
 

-- 
   Summary: Missing opcode for assembly instruction 'stldsr' in isa
aplus of m68k assembler
   Product: binutils
   Version: 2.17
Status: NEW
  Severity: normal
  Priority: P2
 Component: gas
AssignedTo: unassigned at sources dot redhat dot com
ReportedBy: massimo dot ruoroch at polito dot it
CC: bug-binutils at gnu dot org
  GCC host triplet: i686-pc-linux-gnu
GCC target triplet: m68k-elf


http://sourceware.org/bugzilla/show_bug.cgi?id=11030

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[Bug gas/11030] Missing opcode for assembly instruction 'stldsr' in isa aplus of m68k assembler

2009-11-29 Thread massimo dot ruoroch at polito dot it

--- Additional Comments From massimo dot ruoroch at polito dot it  
2009-11-29 14:50 ---
Created an attachment (id=4422)
 --> (http://sourceware.org/bugzilla/attachment.cgi?id=4422&action=view)
The attachment is a patch to solve the problem in version 2.17

The patch add the stldsr instruction to the ISA A+ of Coldfire.


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[Bug gas/11030] Missing opcode for assembly instruction 'stldsr' in isa aplus of m68k assembler

2009-11-29 Thread massimo dot ruoroch at polito dot it

--- Additional Comments From massimo dot ruoroch at polito dot it  
2009-11-29 14:55 ---
The same bug apply also to following versions of binutils. As a test I checked
with the latest one (2.20), and the error is again at line 2029:

{"stldsr", 6,   two(0x40e7, 0x46fc),two(0x, 0x), "#w", mcfisa_c },

must be corrected to:

{"stldsr", 6,   two(0x40e7, 0x46fc),two(0x, 0x), "#w", mcfisa_aa |
mcfisa_c },


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[Bug gas/11030] Missing opcode for assembly instruction 'stldsr' in isa aplus of m68k assembler

2009-11-29 Thread massimo dot ruoroch at polito dot it

--- Additional Comments From massimo dot ruoroch at polito dot it  
2009-11-29 14:59 ---
Please notice that this bug is aproblem for embedded system developers, as the
stldsr instruction is the only atomic instruction which can be used to implement
test-and-set operations, missing on the ISA A+ of Coldfire.

-- 
   What|Removed |Added

 Status|NEW |WAITING


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[Bug ld/11006] A "relaxed" link order of libraries is requested for improved compatibilty

2009-11-29 Thread cvs-commit at gcc dot gnu dot org

--- Additional Comments From cvs-commit at gcc dot gnu dot org  2009-11-30 
00:27 ---
Subject: Bug 11006

CVSROOT:/cvs/src
Module name:src
Changes by: amo...@sourceware.org   2009-11-30 00:27:45

Modified files:
ld : ChangeLog lexsup.c 

Log message:
PR ld/11006
* lexsup.c (parse_args): Allow nested --start-group, --end-group.

Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/ChangeLog.diff?cvsroot=src&r1=1.2087&r2=1.2088
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/ld/lexsup.c.diff?cvsroot=src&r1=1.117&r2=1.118



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[Bug ld/11006] A "relaxed" link order of libraries is requested for improved compatibilty

2009-11-29 Thread amodra at bigpond dot net dot au


-- 
   What|Removed |Added

 AssignedTo|unassigned at sources dot   |amodra at bigpond dot net
   |redhat dot com  |dot au
 Status|NEW |ASSIGNED
   Last reconfirmed|-00-00 00:00:00 |2009-11-30 00:29:00
   date||


http://sourceware.org/bugzilla/show_bug.cgi?id=11006

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[Bug ld/11006] A "relaxed" link order of libraries is requested for improved compatibilty

2009-11-29 Thread amodra at bigpond dot net dot au

--- Additional Comments From amodra at bigpond dot net dot au  2009-11-30 
00:33 ---
The patch I've just committed should allow you to implement this behaviour with
a simple wrapper script, something like the following:

#! /bin/sh
exec real_ld --start-group "$@" --end-group

You could have done the same prior to my patch, but the script would have been a
little more complicated as you'd need to remove existing
--start-group/--end-group options.

-- 
   What|Removed |Added

 Status|ASSIGNED|RESOLVED
 Resolution||FIXED


http://sourceware.org/bugzilla/show_bug.cgi?id=11006

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[Bug binutils/10924] Bug in objdump when disassembling raw armv4t binaries

2009-11-29 Thread chris at seberino dot org

--- Additional Comments From chris at seberino dot org  2009-11-30 04:55 
---
Subject: Re:  Bug in objdump when disassembling raw
armv4t binaries

On Tue, Nov 10, 2009 at 10:32:26AM -, nickc at redhat dot com wrote:
>   I am planning on applying the uploaded patch to address this issue, but I
> would like your feedback on the new behaviour.  With the patch applied your
> testcase will disassemble as:
>
>    <.text>:
>  0:   002000b0strheq  r0, [r0], -r0 

You ended up adding a comment for the above unpredictable instruction flagging
it as unpredictable.

There are thousands of other loads and stores you still need to flag as
unpredictable.What they all have in common is they have W=1 and P=0.
(bits #21 and #24) for addressing mode 3.

Please flag all loads and stores with the following format as unpredictable...

0xX02X
0xX03X
0xX06X
0xX07X
0xX0aX
0xX0bX
0xX0eX
..etc.

(Notice they all have bit 24 unset and bit 21 set.)

cs


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